Electronic device having ferroelectric memory

Abstract: An electronic device maintains data utilizing a ferroelectric memory, not requiring a backup power source voltage. Data such as schedule data and telephone number data is stored in a ferroelectric RAM (16) which switches between a dynamic mode and a nonvolatile mode. When a clock mode is designated by a "CLK" key (12a), a memory control circuit (17) causes the ferroelectric RAM (16) to be switched to the nonvolatile mode to maintain the data stored therein. When a schedule mode or a telephone mode is designated by means of a "Sch" key (12b) or a "Tel" key (12c), the ferroelectric RAM (16) is switched to the nonvolatile mode to write/read data therein/therefrom. When it is detected that a battery voltage is lowered or the battery is removed from the electronic device, the ferroelectric RAM (16) is switched to the nonvolatile mode to protect the stored data.

Description: The invention relates to an electronic device having a ferroelectric memory which can switch between a dynamic mode and a nonvolatile mode, and more particularly to a mode switch control in the memory, as set forth in the preamble of claim 1 or claim 4, respectively. An electronic device of this kind is known from DE-A-4119248. The aforementioned document discloses a large scale integrated nonvolatile semi-conductor memory circuit comprising a dynamic RAM, a capacitor having a ferroelectric dielectric and a transistor serving as a switch for charging and discharging said capacitor. The circuit comprises means that enable the dynamic RAM which inherently is volatile to be used as a nonvolatile memory by adding said transistor and the capacitor having the ferroelectric dielectric. The state of the dynamic RAM i.e. whether volatile or nonvolatile, is controlled by the transistor. From HP100LX users guide, March 1993, Hewlett-Packard Corporation (XP2021386), an electronic notebook is known which is capable of executing a number of functions. It comprises an RAM disk used just like a hard disk of a PC and which is a nonvolatile memory. This notebook may be equipped with memory cards to expand data and program storage. The notebook comprises a main battery and a back-up battery. Volatile data are saved when replacing the batteries if the batteries are replaced one after the other. Conventionally, notebooks memorize personal schedules, and the addresses and telephone numbers of acquaintances. An electronic notebook stores data in a semi-conductor memory by means of key-input operation and reads data from the memory, and can display it on a display section, if necessary. In the electronic notebook, data is stored in a RAM such as a DRAM (dynamic RAM) or a SRAM (static RAM), which is incorporated in the electronic notebook or in a card serving as an external memory medium. A backup voltage is supplied to the RAM to maintain the stored data, even if the power source is turned off or the card is removed from the electronic notebook. A cell or a battery is generally used as the power source for an electronic device of this type. Therefore, if the cell or battery is consumed over a long period of time, the backup voltage cannot be supplied to the RAM and the data in the RAM will be lost. To prevent this, some conventional electronic devices have an alarm function for informing the user, by means of the display or the buzzer, that the cell or battery needs to be exchanged, when the power source voltage if reduced below a predetermined level. However, even in an electronic device with the cell or battery exchange alarm function, if the device is not used for a long period of time, the user will not be aware of the alarm and the power will continue to be consumed. In this case, data in the RAM will be lost, despite of the alarm function. In recent years, new memories have been developed. One of them is a ferroelectric memory, which has not only a reading/writing characteristic equivalent to that of a normal semiconductor RAM but also a nonvolatile characteristic. The ferroelectric memory operates in a dynamic mode or a nonvolatile mode: in the former, the memory operates as a normal DRAM; and in the latter, it operates as a nonvolatile memory. More specifically, in a dynamic mode operation, the memory is used as a DRAM capacitor cell due to its high dielectric constant obtained by a special memory structure. In non-volatile mode operation, data can be maintained without a power source owing to a stable state due to its polarization. The object of the present invention is to provide an electronic device which stores data in a ferroelectric memory, without a backup power source, in which the modes of the ferroelectric memory are accurately controlled. This object is attained by the features of claim 1. Preferred embodiments of the invention are subject matter of the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram showing a power supplying structure of an electronic device; FIG. 2 is a block diagram showing a detailed structure of the electronic circuit of the electronic device shown in FIG. 1; FIG. 3 is a diagram showing a terminal structure of a ferroelectric RAM incorporated in the electronic circuit shown in FIG. 2; FIG. 4 is a timing chart illustrating a mode switching operation of the ferroelectric RAM incorporated in the electronic circuit shown in FIG. 2; FIG. 5 is a flowchart illustrating an operation of the electronic device of Fig. 1; and FIG. 6 is a circuit diagram showing a power supplying structure of an electronic device according to a third embodiment of the present invention. FIG. 1 is a circuit diagram showing a power supplying circuitry for an electronic circuit, in which a non-volatile ferroelectric memory is switched between a dynamic mode and a nonvolatile mode in association with operations of detecting a source voltage and setting the mode of the device. The source voltage is supplied from a battery source B constituted by a cell or a battery to an electronic circuit 10, i.e., a main part of the electronic device such as an electronic notebook, through a power switch SW and a constant voltage regulator R. An output voltage of the constant voltage regulator R is detected by a voltage detector D which outputs a voltage detection signal to be supplied to the electronic circuit 10. FIG. 2 is a block diagram showing the electronic circuit 10 of the electronic device. In the electronic circuit 10, a CPU (central processing unit) 11 activates a system program prestored in a ROM 13 in response to a key operation signal supplied from a key input section 12, so that the operation of each section of the circuit 10 can be controlled. The CPU 11 is connected to the key input section 12, the ROM 13 and the voltage detector D. It is also connected to a RAM 14 operating as a working memory, a time measuring section 15, a ferroelectric memory (ferroelectric RAM) 16, a memory control circuit 17 and a display 18. The key input section 12 comprises various keys (not shown), such as letter keys, numeric keys and symbol keys, which are used to input personal schedule data or data on the addresses and telephone numbers of acquaintances. It also comprises a "CLK" key 12a which is operated to set the device 10 in a clock mode for displaying a time, an "Sch" key 12b which is operated to set the device 10 in a schedule mode for recording or displaying schedule data, and a "Tel" key 12c which is operated to set the device in a telephone mode for recording and displaying phone number data. The ferroelectric RAM 16 switches between a volatile mode (dynamic mode) in which it operates as a normal DRAM and a nonvolatile mode in which no backup voltage is required. The ferroelectric RAM 16 stores, as record data, the schedule data or telephone number data which have been input in the schedule mode and the telephone mode. Control signals, such as a mode switching signal D/NV for switching between the dynamic mode and the nonvolatile mode and a refreshing signal RFSH, are supplied from the memory control circuit 17 to the ferroelectric RAM 16 in response to the instructions from the CPU 11. The memory control circuit 17 outputs a mode switching signal D/NV through a flip-flop (FF) 17a incorporated therein. When the signal D/NV is "1", the ferroelectric RAM 16 is set to the dynamic mode and when the signal D/NV is "0", the RAM 16 is set to the nonvolatile mode. FIG. 3 is a diagram showing the terminal structure of the ferroelectric RAM 16 incorporated in the electronic circuit 10. The ferroelectric RAM 16 comprises a source terminal V cc , a ground terminal GND and connection terminals connected to address and data lines. It also comprises control signal input terminals for receiving a mode switching signal D/NV, a refresh signal RFSH, a chip enable signal CE, a write enable signal "WE" and an output enable signal OE. FIG. 4 is a timing chart showing a mode switching operation of the ferroelectric RAM 16 incorporated in the electronic circuit 10. When a chip enable (pulse) signal CE is supplied to the ferroelectric RAM 16 for a predetermined period of time in the nonvolatile mode and the mode switching signal D/NV is changed from "0" (V IL ) to "1" (V IH ) at the end of the mode switching period, the ferroelectric RAM 16 is switched to the dynamic mode, in which a refresh signal RFSH is supplied. In the dynamic mode, when the supply of the refresh signal RFSH is stopped, the mode switching signal D/NV is changed from "1" (V IH ) to "0" (V IL ) and a chip enable (pulse) signal CE is supplied to the ferroelectric RAM 16 for a predetermined period of time, then the ferroelectric RAM 16 is switched to the nonvolatile mode after the mode switching period. An operation of the above-described electronic device will now be described with reference to the flowchart shown in FIG. 5. When the power switch SW (shown in FIG. 1) is turned on, the CPU 11 determines, based on the voltage detection signal from the voltage detector D, whether the source voltage of the battery B supplied to the electronic circuit 10 is lowered to a predetermined level, which is necessary for the operation (step S1). If it is determined that the source voltage is not lowered to the predetermined level in step S1 ("NO"), the electronic device waits for a key operation signal supplied from the key input section 12 (step S1 → step S2). Clock Mode When the user set the clock mode by operating the "CLK" key 12a of the key input section 12, the CPU 11 determines whether the mode switching signal D/NV generated from the flip-flop 17a of the memory control circuit 17 is "1" or not, i.e., whether the current operation mode of the ferroelectric RAM 16 is the dynamic mode or not (step S3 → step S4). If the CPU 11 determines that the current operation mode is the dynamic mode, the memory control circuit 17 stops supplying of the refresh signal RFSH, changes the mode switching signal D/NV from "1" (V IH ) to "0" (V IL ), and causes the chip enable signal CE to be supplied to the ferroelectric RAM 16 for a predetermined period of time. Thus, the RAM 16 is switched to the nonvolatile mode (steps S5, S6 and S7). Based on time data from the time measuring section 15, the display 18 displays the time (step S8). In the clock mode, since data is not written in (recorded) or read from the ferroelectric RAM 16 (displayed), the ferroelectric RAM 16 is changed to the nonvolatile mode, so as to avoid waste of power. If the CPU 11 determines that the current operation mode is the nonvolatile mode, steps S5 to S7 are passed and the flow advances to the time display step (step S8). Schedule Mode and Telephone Mode In the waiting state in step S2, if the user sets the schedule mode or the telephone mode by operating the "Sch" key 12b or the "Tel" key 12c of the key input section 12, the CPU 11 determines whether the mode switching signal D/NV supplied from the memory control circuit 17 is "1" or not, i.e., whether the current operation mode of the ferroelectric RAM 16 is the dynamic mode or not (step S9 → step S10). If the CPU 11 determines that the current operation mode is not the dynamic mode, the memory control circuit 17 causes the chip enable signal CE to be supplied to the ferroelectric RAM 16 for a predetermined period of time, changes the mode switching signal D/NV from "0" (V IL ) to "1" (V IH ), and starts supplying the refresh signal RFSH. Thus, the ferroelectric RAM 16 is switched to the dynamic mode (steps S11, S12 and S13). In this state, schedule data or telephone number data can be written in or read from the ferroelectric RAM 16 in accordance with the key input operation and the recording or displaying process can be executed (step S14). In the schedule mode or telephone mode, since the data is written in (recorded) or read from the ferroelectric RAM 16 (displayed), the RAM 16 is switched to the dynamic mode, in which it operates as a DRAM. If the CPU 11 determines that the current operation mode is the dynamic mode in step S10, steps S11 to S13 are passed and the flow advances to the schedule or telephone processing step (step S14). Low Voltage State If it is determined that the source voltage is lowered to the predetermined level or lower in step S1, the CPU 11 determines whether the mode switching signal D/NV set in the memory control circuit 17 is "1" or not, i.e., whether the current operation mode of the ferroelectric RAM 16 is the dynamic mode or not (step S1 → step S17). If the CPU 11 determines that the current operation mode is the dynamic mode, the memory control circuit 17 stops supplying the refresh signal RFSH, changes the mode switching signal D/NV from "1" (V IH ) to "0" (V IL ), and causes the chip enable signal CE to be supplied to the ferroelectric RAM 16 for a predetermined period of time. Thus, the ferroelectric RAM 16 is switched to the nonvolatile mode (step S18). If it is determined that the current operation mode is the nonvolatile mode in step S17, the mode is maintained. Then, an alarm process, for informing the user that the battery B needs to be exchanged, is performed by displaying a message or driving a buzzer (step S19). In summary, when the remaining power in the battery B becomes so little that the data stored in the ferroelectric RAM 16 in the dynamic mode may be damaged or lost, the RAM 16 is switched to the nonvolatile mode. Thus, in the electronic device as described above, when the clock mode is selected or the voltage detector D detects a source voltage lower than a predetermined level, the ferroelectric RAM 16 is switched by the memory control circuit 17 to the nonvolatile mode in order to maintain the stored data. When the schedule mode or the telephone mode is selected, the ferroelectric RAM 16 is switched to the dynamic mode to execute data writing (recording) or reading (displaying). In this manner, since power is consumed only when the data memory needs to be accessed, the lifetime of the battery B can be prolonged. FIG. 6 is a circuit diagram showing a power supplying circuitry of an electronic device according to the invention, in which the operation mode of the ferroelectric RAM is switched in association with a battery exchange. A source voltage is supplied from a battery source B composed of a cell or a battery to an electronic circuit 10 through a power switch SW and a constant voltage regulator R. A battery exchange association switch SW (B) is inserted in a stage between the power switch SW and the circuit 10. When the battery B is exchanged, a battery exchange detection signal is supplied to the electronic circuit 10. The switch SW (B) operates in association with, for example, opening and closing of a battery cover, so as to be operated whenever the battery B is exchanged. According to the electronic device shown in FIG. 6, when the battery B is exchanged the battery cover is made open and then closed to generate a battery exchange detection signal which is supplied to the electronic circuit 10 in accordance with the exchange of the battery B, the ferroelectric RAM 16 incorporated in the electronic circuit 10 is switched to the nonvolatile mode. When the exchange of the battery B is completed and the supply of the battery exchange detection signal is stopped, the ferroelectric RAM 16 is switched to the dynamic mode. Thus, the stored data cannot be lost even when the battery B is removed from the electronic device.

Claims: An electronic device (10) comprising: a ferroelectric memory (16) switchable between two memory modes including a dynamic memory mode in which data can be written and read out and a nonvolatile memory mode in which storage data can be retained without supply of power; characterized by further comprising: a switch (SW(B)) operated when a battery (B) is taken out and replaced with another; and switching means (10), operating in response to the switch (SW(B)) being operated, for switching the ferroelectric memory (16) from the dynamic memory mode to the nonvolatile memory mode, and vice versa. An electronic device according to claim 1, characterized in that said switch (SW(B)) is operated in association with an operation of opening or closing a battery lid of a battery storage section. An electronic device according to claim 2, characterized in that said switching means (10) includes signal generation means for supplying a chip enable signal (CE) and a switching signal (D/NV) to the ferroelectric memory (16) when the memory modes are switched from one to the other, said chip enable signal (CE) being a pulse signal that becomes active for a predetermined length of time.

Inventors: ISHIKAWA RYO, KANEKO KATSUYOSHI, ORIMOTO TAKASHI, SHIRASAKA TAKASHI, SUZUKI SHIGETO, ISHIKAWA, RYO, KANEKO, KATSUYOSHI, ORIMOTO, TAKASHI, SHIRASAKA, TAKASHI, ISHIKAWA, RYO, C/O CASIO COMPUTER CO., LTD., KANEKO, KATSUYOSHI, C/O CASIO COMPUTER CO., LTD., ORIMOTO, TAKASHI, C/O CASIO COMPUTER CO., LTD., SHIRASAKA, TAKASHI, C/O CASIO COMPUTER CO., LTD., SUZUKI SHIGETO C/O CASIO COMPUTER CO LTD PAT. DPT
Applicants: CASIO COMPUTER CO LTD, CASIO COMPUTER CO., LTD.
Application year: 1994
Main classification: G11C11
IPC codes: G11C11, G11C5, G11C14