Driving circuit for electronic semiconductor devices including at least a power transistor

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

Description: Field of the Invention This invention relates to a control circuit for semiconductor electronic devices which include at least one power transistor. The invention specifically concerns a control circuit for electronic power devices monolithically integrated on a semiconductor substrate which has been doped by a first dopant type and on which a first epitaxial layer doped by the same dopant type as the substrate has been grown, an isolation well doped by a second type of dopant being formed therein for at least a first transistor of the control circuit. The invention also relates to a semiconductor electronic device structure, in particular a field-effect transistor. Further, the invention relates to a process for making the above control circuit and semiconductor device structure. Background Art As is well known, at least one control circuit comprising low voltage operating transistors and at least one high voltage operating power transistor are integrated into many electronic devices. An isolation structure is used for the control circuit, and its related transistors are integrated in a single well, known as the isolation well, such as the one shown at 3' in Figure 1. Figure 1 shows schematically a semiconductor IC device which has been integrated monolithically in accordance with prior art methods and comprises a control circuit C' and a power transistor TP of the bipolar NPN HV type. The IC device has a pair of isolation terminals ISO1 and ISO2. For simplicity of description, the control circuit C' of Figure 1 has been depicted as having two bipolar components only, namely a transistor T1 of the NPN LV type and a transistor T2 of the PNP LV type. The control transistors T1 and T2 are accommodated in a single isolation well 3' formed within an epitaxial layer 2' of the N- type grown on a substrate 1' of the N+ type. The isolation well 3' is virtually a necessity with semiconductor devices of this kind, but involves the appearance of certain parasitic transistors which impair the proper operation of the control circuit. The formation of each of the control transistors T1 and T2 involves the presence, in the isolation well 3', of respective buried layers 4' and 4'' having a dopant type which is the opposite from that of the well 3'. These buried layers 4' and 4'' are responsible for the appearance of several parasitic transistors. A pair of parasitic transistors P1' and P2' are associated with the first control transistor T1. In this respect, Figure 2 shows, drawn to an enlarged scale, a portion of Figure 1 where just the transistor T1 and the layer 4' are provided. An equivalent electric circuit of the structure of Figure 2 is shown in Figure 3. During normal operation of the device, when the transistor T1 would be saturated, the base-emitter junction of the parasitic transistor P2' is forward biased and its collector, which is coincident with a contact ISO1 of the isolation well 3', is at a ground reference potential GND. Under these conditions, the transistor P2' will be in the active zone and will inject current into an isolation area 9' which is associated with the contact ISO1 through a resistance Rp being the intrinsic resistance of the well 3'. It is desirable that such a current be prevented from producing a potential difference across the resistance Rp capable of also turning on the other parasitic transistor P1'. This occurrence may result from the presence of ramp voltages applied to the substrate 1', which can charge a parasitic capacitance Cp, present between the substrate 1' and the well 3', and produce a current flow which can turn on the parasitic transistor P1'. Likewise, associated with the control transistor T2 is a further pair of parasitic transistors P3' and P4' which add to the parasitic transistor P1'. For convenience of illustration, Figure 4A is an enlarged view of the structure of the transistor T2, while Figure 4B shows an equivalent electric circuit of Figure 4A. The presence of the parasitic transistor P1' is less critical to the control transistor T2 than to the previous transistor T1 because the emitter of the transistor P1' is at a higher voltage than the ground voltage, and to turn on the transistor P1', its base-emitter junction must be brought up to an even higher value. The current which is forced to flow through the resistance Rp is, therefore, a larger one if compared to the control transistor T1. In conclusion, in order to prevent the parasitic transistor P1' from conducting, the following would be necessary: to minimize the resistance Rp present between the transistor P1' and the isolation well 3' contacts ISO1 and ISO2, normally connected to ground GND; to minimize the current gain of the first parasitic transistor P1'; and to decrease the gain of the other parasitic transistors P2', P3' and P4'. A first known technical solution to meet such requirements consists of using an isolation well 3' obtained by epitaxial growth rather than implantation followed by dopant diffusion. In such a manner, the base of the parasitic transistor P1' is more strongly doped, and this brings down the transistor gain. While being advantageous in many respects, this first solution fails to fully remove the effects of the transistor P1' or of the other parasitic transistors P2', P3', P4' present. A second solution provides for the use of an intermediate epitaxial layer to make the base of the parasitic transistor P1' broader and more strongly doped, is described in US Patent No. 4,889,822, for example. While the provision of this intermediate layer further decreases the gain of the parasitic transistor P1', not even this solution can completely rule out the possibility of the parasitic transistor being turned on. A prior art solution is disclosed in the patent applications EP No. 0 385 524 A3 and EP No. 0 443 326 A2 for realizing a control circuit comprising CMOS device isolated by a region formed beetween n-channel FET and p-channel FET. The technical problem underlying this invention is to provide a control circuit adapted for monolithic integration, with at least one driven power transistor, and having such structural and functional features as to afford a drastic reduction in the parasitic components that appear in previously known solutions in the art. Summary of the Invention The solutive idea on which the invention stands is one of providing the control circuit with at least one N-channel MOS transistor placed in a well in direct contact with the isolation well. Based on this solutive idea, the technical problem is solved by a control circuit as previously indicated and as defined in Claim 1. The problem is also solved by a process for making such a circuit, as defined in Claim 5. The features and advantages of a device according to this invention will be apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 is a schematic view showing in vertical section a semiconductor to which a control circuit has been integrated in accordance with the prior art; Figure 2 shows schematically a detail of the circuit in Figure 1; Figure 3 shows an equivalent electric circuit of the detail in Figure 2; Figure 4A shows schematically a further detail of the circuit in Figure 1; Figure 4B shows an equivalent electric circuit of the detail in Figure 4A; Figures 5 and 6 are respective schematic views illustrating in vertical section successive steps of a process for making semiconductor integrated circuits, preliminary to forming the circuit of this invention; Figure 7 shows schematically, in vertical section, the structure of a control circuit embodying this invention, at the end of the process steps which result in its formation; Figure 8 is an enlarged scale view of a detail of the example shown in Figure 7; and Figure 9 is an enlarged scale view of a further detail of the example shown in Figure 7. Detailed Description With reference to the drawing figures, and specifically to the example in Figure 7, generally denoted by the character C is a control circuit embodying this invention. Omitted from that Figure is a bipolar power transistor TP which is understood to have been conventionally integrated monolithically together with the control circuit C to be driven by the latter. For simplicity of description, only a control circuit C comprising just two transistors M1 and M2 will be considered for discussion. Advantageously, in accordance with the invention, such transistors are field-effect, in particular MOS, transistors of the N-channel and the P-channel type, respectively. Furthermore, they are formed in a single isolation well 3, as will be brought out hereinafter in connection with the circuit manufacturing process. With reference in particular to Figures 5 and 6, on a semiconductor substrate 1 having a high concentration of a dopant of a first type, e.g. of the N+ type, a first growth step is carried out to provide a first epitaxial layer 2 which has the same first dopant type. This first epitaxial layer 2 contains N dopant to a lower concentration than the substrate 1. Thereafter, a step of implantation and diffusion of a second dopant type, e.g. a P type, is carried out on the epitaxial layer 2, thereby to form an isolation well 3 in the epitaxial layer 2. The isolation well 3 is then subjected to a third implantation and diffusion step at a high concentration of the first N+ dopant type to form a layer 4. The last-mentioned layer 4 will be termed "buried" hereinafter for reasons to be explained. Advantageously, according to the invention, the buried layer 4 is used to form a single MOS transistor, the P-channel transistor M2. Subsequently, a fourth growth step is carried out to grow a second epitaxial layer 5 having a low concentration of the first type of N dopant, which low concentration is comparable to that of the first epitaxial layer 2. A fifth implantation step of the second type of P dopant will result in a second P-well 6 being formed within the second epitaxial layer 5. A sixth implantation step of the first type of N dopant will provide a third N-well 7 over the buried layer 4. This implant will also affect the epitaxial layer surrounding the P-well 6, raising its dopant concentration. A subsequent thermal diffusion step will settle the dopings of the wells 6 and 7. At this time, a seventh implantation step is carried out followed by diffusion of the second type of P dopant. This implant will essentially define three discrete connect channels extending from the semiconductor surface down the isolation well 3. These connect channels 9 bound the third N-well 7 and a fourth N-well 8 accommodating the P-well 6 over the isolation well 3. On completion of this process step, the circuit structure will show up as in Figure 6, with an isolation well 3 accommodating and enclosing two N-wells 7, 8, one being formed over the buried layer 4 and the other housing a P-well 6. The attention will be directed hereinafter to the making of the active areas of the transistors M1 and M2. The first MOS transistor M1 of the N-channel type and the second MOS transistor M2 of the P-channel type are respectively formed in the wells 6 and 7. For clarity of illustration, these transistors M1 and M2 have been shown in their final structure condition, separately and to an enlarged scale, in Figures 8 and 9. An implantation and associated diffusion step of the second type of P dopant into the well 6 allows definition of deep body regions 12, 12' as well as the regions 13, 13' in the well 7. At this time, a layer 17 of polysilicon is deposited onto the semiconductor surface and suitably doped to form the gates G1 and G2 of the MOS transistors M1 and M2. This deposition step is followed by an implantation and diffusion step of dopant of the second P type into the third well 7 to form the drain and source active areas 14 and 14' of the P-channel transistor M2. Conventional metallic contacts D2 and S2 are provided for the drain and source regions 14 and 14'. Thereafter, another implantation and diffusion step is carried out in the second well 6, using the first type of N+ dopant, to form the drain and source active areas 15 and 16 of the transistor M1. Terminal contacts D1 and S1 are provided over these regions. The fabricating process is completed by a step of definition and metallization of the drain contact areas D1, D2 and source contact areas S1, S2. The resultant device is as shown in Figure 7. Advantageously, according to this invention, the transistor M1 has no buried layer of dopant of the first N type, as was instead the case with prior art bipolar transistors. It will be recalled, in fact, that the NPN transistor T1 of Figures 1 and 2 has its collector defined by the buried layer 4', which provides a near-vertical, substantially U-like current flow pattern. The absence of a buried layer from the circuit of this invention causes the dopant, such as boron, used for the isolation well 3 to also diffuse in the upward direction. This poses no problems to the MOS transistor M1 of the N-channel type in the control circuit C of this invention because the current flow between the source S1 and the drain D1 of that transistor M1 takes place at the surface, which would not be reached by the dopant of the isolation well 3. By eliminating the buried layer of the first dopant type, a first parasitic transistor P1, whose emitter is indeed formed by that layer, can also be suppressed. Nor is there, in the control circuit C of this invention, any second parasitic transistor P2 such as affects, by contrast, all prior embodiments. In fact, the source S1 of the transistor M1 is connected to the ground reference potential GND, and so is, therefore, the deep body region 12' to which that source S1 is connected. Thus, the emitter and base of the parasitic transistor P2 are shorted together and the transistor P2 cannot be turned on. The buried layer 4 of the first type of N+ dopant is, however, still present in the well 7 where the P-channel transistor M2 is formed, which prevents shorting of the source S2 to the drain D2 of that transistor M2. Accordingly, the formation of the control transistor M2 will imply the presence of a parasitic transistor P1 due to the buried layer 4 provided. Advantageously though, during normal operation of the control circuit C according to the invention, the P + -N junction between the region 13 and the well 7 of the control transistor M2 will at all times be reverse biased to prevent said parasitic transistor P1 from becoming turned on. Furthermore, the source contact S2 stops operation of a further parasitic transistor P3 by shorting its base to its emitter, coincident with the regions 11 and 13'. To sum it up, the control circuit C of this invention does remove the problems brought about by the appearance of parasitic elements, thereby overcoming the drawbacks of similar prior art circuits.

Claims: A power integrated circuit, comprising: a power transistor (TP) integrated monolithically in a N-type semiconductor substrate (2); a patterned P-type isolation well (3) in said substrate (2) ; a N-channel field-effect transistor (M1) being located inside a second P-type well (6) formed in a first N-well (8) formed in said P-type isolation well (3); a P-channel field-effect transistor (M2) being located inside a second N-type well (7) formed in said P-type isolation well (3), an N-type buried layer (4) formed in said P-type isolation well (3) and at the bottom of said second N-type well (7) and having a higher doping concentration than that of said second N-type well (7). A power integrated circuit according to Claim 1, where said N-channel field-effect transistor (M1) further comprises a P-type contact diffusion region (12, 12') bounding the side edge of said second P-type well (6) and being connected to the source of said N-channel field-effect transistor (M1). A power integrated circuit according to Claim 1, where said P-channel field-effect transistor (M2) further comprises P-type contact diffusion regions (13, 13') bounding respectively the source and drain regions of said P-channel transistor (M2) inside said second N-type well (7). A power integrated circuit according to Claim 1 or 2 or 3, where said N-channel field-effect transistor (M1) and P-channel field-effect transistor (M2) are MOS transistors. A process for making a power integrated circuit for electronic semiconductor devices monolithically integrated along with at least one power component, being of a type which comprises a first growing step of a first epitaxial N-type layer (2) on a N + -type semiconductor substrate (1), a first step of implantation of a P-type dopant to define a P-type isolation well (3), a second step of implantation to define a N + -type buried layer (4) in a portion of the surface of said P-type isolation well (3), and a second growing step of a second N-type epitaxial layer (5) on the first epitaxial layer (2), a further implantation step carried out using a P-type dopant to form three discrete P + -type channels (9) extending from the surface of said second N + -type epitaxial layer (5) to said P-type isolation well (3), whereby a first N-type well (8) in said second epitaxial layer (5) and a second N-type well (7) in said second epitaxial layer (5) on said N + -type buried layer (4) and separated from said first N-type well (8) by one of said three discrete P + -type channels (9) are defined, and subsequently a further implantation step to define a second P-type well (6) formed in said first N-type well (8), forming a n-channel field-effect transistor (M1) in said second P-type well (3) and forming a second p-channel field-effect transistor (M2) in said second N-type well (7) formed on said N-type buried layer (4). A process according to Claim 5, where said N-channel field-effect transistor (M1) and P-channel field-effect transistor (M2) are MOS transistors.

Inventors: CACCIOLA GIOVANNA, LEONARDI SALVATORE, MONTALBANO GIANPIERO, CACCIOLA, GIOVANNA, LEONARDI, SALVATORE, MONTALBANO, GIANPIERO
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1994
Main classification: H01L27
IPC codes: H01L27, H01L21