Information processing system including a cache and means for prefetching data

Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

Description: The present invention relates to an information processing system, and in particular to one having a system memory and a cache memory. Many systems for processing information include both a system memory and a cache memory. A cache memory is a relatively small highspeed memory that stores a copy of information from one or more portions of the system memory. Frequently, the cache memory is physically distinct from the system memory. Such a cache memory can be integral with a processor device of the system or be non-integral with the processor. Information can be copied from a portion of the system memory into the cache memory. The information in the cache memory can be modified. Further, modified information from the cache memory can be copied back to a portion of the system memory. In response to instructions, execution units of the processor are able to process information stored in the cache memory. Such instructions include memory instructions for transferring data information between the cache memory and registers of the processor. In a cache miss situation where information for a memory instruction (such as a "load/store" instruction or a "read/write" instruction) is not stored in the cache memory, such information is requested from the system memory. A significant amount of delay can occur while waiting for information from the system memory in response to a cache miss situation. To reduce negative consequences of such a cache miss situation, the processor can support a prefetch instruction (such as a "touch load" instruction) for loading the cache memory with data information from a specified address within the system memory well in advance of the information being used for another instruction of the processor. Nevertheless, if the prefetch instruction itself results in a cache miss situation, and if the cache memory is a "blocking" cache memory, then additional memory instructions are blocked from using the cache memory until information is received from the system memory. The additional memory instructions are blocked irrespective of whether they specify information already stored in the cache memory. Accordingly, with previous blocking cache memories, such a prefetch instruction is relatively ineffective and possibly even degrades the performance of the processor. With previous techniques, a prefetch operation is significantly less practical unless the cache memory is made non-blocking. In a non-blocking cache memory, additional memory instructions are not blocked from using the cache memory if they specify information already stored in the cache memory. However, logic for a non-blocking cache memory is more complex than logic for a blocking cache memory. Moreover, it is difficult to verify proper operation of a non-blocking cache memory because additional memory instructions are not blocked from using the cache memory even while waiting for information from the system memory. Data prefetching is described in "An architecture for Software-controlled data prefetching" by Klaiber and Levy, 8345 Computer Architecture News, 18th Ann. Int. Symp. Computer Architecture, 19(1991) May, No. 3, New York, US, p43-53. This provides for a fetchbuffer in addition to the main cache which is loaded using the FETCH instruction. On a LOAD or STORE operation the CPU performs a lookup in both the fetchbuffer and the cache. Accordingly, the invention provides an information processing system in which a processor processes instructions, said system including: a system memory for storing information; a supplemental memory coupled to said system memory for accessing and storing first information from said system memory in response to a prefetch instruction; and a cache memory coupled to said supplemental and system memories for accessing and storing second information in response to a memory instruction, said second information being from said system memory if said first information does not include said second information; and characterised in that if said first information does include said second information, then said cache memory accesses said second information from said supplemental memory. In such an information processing system the negative consequences of a cache miss situation are reduced. Moreover, when said cache memory is a blocking cache memory, a prefetch instruction is effective. It is convenient for both the cache memory and the supplemental memory to be integral with said processor. Typically supplemental memory is a prefetch memory, and said first instruction is a prefetch instruction. Usually the processor is coupled to the system and supplemental memories for processing instructions, and outputs a signal to designate said first instruction to said supplemental memory in response to said first instruction, the supplemental memory storing said first information in response to said signal. In a preferred embodiment, said second information from said system memory is stored in said cache memory without adding said second information to said supplemental memory. It is also preferred that the system further includes means coupled to said supplemental memory for maintaining coherency of said first information in said supplemental memory. Generally said supplemental memory is smaller than said cache memory and said supplemental memory is smaller than said system memory. Preferably said supplemental memory stores said first information in response to said first instruction having a first instruction type, and said cache memory stores said second information in response to said second instruction having a second instruction type. Thus in an information processing system a supplemental memory stores first information from a system memory in response to a first instruction. In response to a second instruction, a cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise. Such an arrangement allows prefetch instruction to be effective for a system having a blocking cache memory, and reduces the negative consequences of a cache miss situation. Various embodiments of the invention will now be described in detail by way of example, with reference to the following drawings: FIGURE 1 is a block diagram of an information processing system according to the preferred embodiment; FIGURE 2 is a flow chart of a method of operating a prefetch memory of FIGURE 1; FIGURE 3 is a flow chart of a method of operating a cache memory of FIGURE 1; and FIGURE 4 is a block diagram of an information processing system according to an alternative embodiment. FIGURE 1 is a block diagram of an information processing system, indicated generally at 10, according to the preferred embodiment. FIGURE 1 can be regarded as a very simplified diagram of the system unit in a computer workstation. In system 10, a cache memory 12 is integral with a processor 16. Processor 16 is a single integrated circuit superscalar microprocessor. In an alternative embodiment, cache memory 12 is non-integral with processor 16. Other possible variations include for processor 16 to be a multi-chip microprocessor or a non-superscalar processor. Processor 16 includes a bus interface unit ("BIU") 18, a snoop register 20, a write register 22, and a read register 24. Moreover, processor 16 includes execution units 19. Processor 16 further includes a prefetch memory 26 formed by a touch load register ("TLR"). In addition to processor 16, system 10 includes a system bus 28 and a system memory 30 connected thereto. Also, BIU 18 of processor 16 is connected to system bus 28. Prefetch memory 26 is a supplemental memory, in that prefetch memory 26 is additional to system memory 30 and cache memory 12 within system 10. Processor 16 inputs data information from an address within system memory 30. Such data information is input by BIU 18 from system memory 30 through system bus 28, and the data information is stored into read register 24 from BIU 18. At a suitable moment, the data information is stored into cache memory 12 from read register 24. Processor 16 associates the data information with its corresponding address by storing address information together with the data information. Similarly, processor outputs data information to an address within system memory 30. Such data information is stored into write register 22 from cache memory 12. At a suitable moment, the data information is output from write register 22 to BIU 18, and BIU 18 outputs the data information to system memory 30 through system bus 28. The data information is stored at its corresponding address within system memory 30. For maintaining coherency of stored data information, processor 16 snoops address information on system bus 28. Such address information is input by BIU 18 from system bus 28, and the address information is then stored into snoop register 20 from BIU 18. The address information stored in snoop register 20 is compared with address information in cache memory 12, in write register 22, and in read register 24. Significantly, the address information stored in snoop register 20 is further compared with address information in prefetch memory 26 (TLR 26 in FIGURE 1). If the address information stored in snoop register 20 matches address information stored in cache memory 12, in write register 22, in read register 24 or in prefetch memory 26, then processor 16 responds with appropriate coherency action. In response to instructions, execution units 19 process information stored in cache memory 12. These instructions include memory instructions for transferring data information between cache memory 12 and registers of processor 16. In a cache miss situation where information for a memory instruction (such as a "load/store" instruction or a "read/write" instruction) is not stored in cache memory 12, processor 16 requests such information from system memory 30. A significant amount of delay can occur while processor 16 waits for information from system memory 30 in response to a cache miss situation. In the preferred embodiment, cache memory 12 is a "blocking" cache memory. Logic for a blocking cache memory is less complex relative to logic for a non-blocking cache memory. Accordingly, while processor 16 waits for information from system memory 30 in response to a cache miss situation, additional memory instructions are blocked from using cache memory 12 until such information is received from system memory 30. The additional memory instructions are blocked irrespective of whether they specify information already stored in cache memory 12. By comparison, in a non-blocking cache memory, additional memory instructions are not blocked from using the cache memory if they specify information already stored in the cache memory. To reduce negative consequences of such a cache miss situation where processor 16 waits for information from system memory 30, processor 16 supports a prefetch instruction (such as a "touch load" instruction) for loading cache memory 12 with data information from a specified address within system memory 30 well in advance of the information being used for another instruction of processor 16. With previous blocking cache memories, such a prefetch instruction is relatively ineffective and possibly even degrades the performance of processor 16. This is because, if the prefetch instruction results in a cache miss situation, additional memory instructions are blocked from using cache memory 12 until processor 16 receives information from system memory 30. Processor 16 of the preferred embodiment includes prefetch memory 26. As discussed further hereinbelow in connection with FIGURES 2 and 3, prefetch memory 26 supports the prefetch operation without significantly complicating the logic of blocking cache memory 12. FIGURE 2 is a flow chart of a method of operating prefetch memory 26 (TLR 26 in FIGURE 1). Initially, the method self-loops at a decision step 50 until processor 16 determines a prefetch instruction (such as a "touch load" instruction) is pending execution. In an alternative embodiment, the method self-loops at decision step 50 until processor 16 determines an instruction having a particular type is pending execution; notably, in such an alternative embodiment, the particular type of instruction can be an instruction type other than a prefetch instruction type. With continued reference to FIGURE 2, in response to a prefetch instruction pending execution, the method continues to a decision step 51 where processor 16 determines whether the targeted data information is already stored in cache memory 12. If the targeted data information is already stored in cache memory 12, the method returns to decision step 50. If the targeted data information is not already stored in cache memory 12 (i.e. a cache miss situation), the method continues from decision step 51 to a step 52 where processor 16 requests the targeted data information from system memory 30 through system bus 28. After step 52, the method self-loops at a decision step 54 until the requested data information is received from system memory 30 through system bus 28. In FIGURE 1, BIU 18 inputs the received data information. In response to the data information being received, the method continues to a step 56 where the information is stored into prefetch memory 26 instead of cache memory 12. After step 56, the method returns to decision step 50. Since the requested data information for a prefetch instruction is stored into prefetch memory 26 instead of cache memory 12, additional memory instructions (such as a "load/store" instruction or a "read/write" instruction) are not blocked from using cache memory 12 while processor 16 waits for the data information from system memory 30. FIGURE 3 is a flow chart of a method of operating cache memory 12. Initially, the method self-loops at a decision step 60 until processor 16 determines a memory instruction is pending execution. In response to a memory instruction pending execution, the method continues to a decision step 62 where processor 16 determines whether the targeted data information is already stored in cache memory 12. If the targeted data information is already stored in cache memory 12, the method continues to a step 64 where processor 16 executes the memory instruction with the data information already stored in cache memory 12. After step 64, the method returns to decision step 60. If the targeted data information is not already stored in cache memory 12, the method continues from decision step 62 to decision step 66 where processor 16 determines whether the targeted data information is stored in prefetch memory 26 (TLR 26 in FIGURE 1). If the targeted data information is stored in prefetch memory 26, the method continues to a step 68 where processor 16 stores the targeted data information into cache memory 12 from prefetch memory 26. After step 68, the method continues to step 64. If the targeted data information is not stored in prefetch memory 26, the method continues from decision step 66 to a step 70 where processor 16 requests the targeted data information from system memory 30 through system bus 28. After step 70, the method self-loops at a decision step 72 until the requested data information is received from system memory 30 through system bus 28. BIU 18 inputs the received data information. In response to the data information being received, the method continues to a step 74 where the information is stored into read register 24. After step 74, the method continues to a step 76 where processor 16 stores the information into cache memory 12 from read register 24. After step 76, the method continues to step 64. Accordingly, if the targeted data information is not stored in prefetch memory 26, the information is stored into cache memory 12 from system memory 30 without adding the information to prefetch memory 26. Moreover, even in an embodiment in which such information is added to prefetch memory 26, cache memory 12 advantageously bypasses prefetch memory 26 when cache memory 12 stores the information from system memory 30. By bypassing prefetch memory 26, cache memory 12 stores the information from system memory 30 more quickly without waiting for prefetch memory 26 to store the information. FIGURE 4 is a block diagram of an information processing system, indicated generally at 90, according to an alternative embodiment. In FIGURE 4, prefetch memory 26 is not integral with processor 16. Instead, prefetch memory 26 is formed by a memory array connected to system bus 28. Like system 10 of FIGURE 1, system 90 operates according to the methods of FIGURES 2 and 3. Accordingly, at step 52 of FIGURE 2, in response to a prefetch instruction, processor 16 outputs a special purpose communication signal on system bus 28 to designate the operation on system bus 28 as a prefetch operation. System bus 28 supports such a special purpose communication signal, and prefetch memory 26 includes logic for responding thereto. In response to the special purpose communication signal on system bus 28, prefetch memory 26 stores information at step 56 of FIGURE 2 after such information is received from system memory 30 through system bus 28. Since the requested data information for a prefetch instruction is stored into prefetch memory 26 instead of cache memory 12, additional memory instructions (such as a "load/store" instruction or a "read/write" instruction) are not blocked from using cache memory 12 while prefetch memory 26 waits for the data information from system memory 30. Prefetch memory 26 is significantly smaller than system memory 30. Accordingly, cache memory 12 is able to input information significantly faster from prefetch memory 26 (steps 66 and 68 of FIGURE 2) than from system memory 30 (steps 70-74 of FIGURE 2). Like processor 16, prefetch memory 26 of FIGURE 4 associates data information with its corresponding address by storing address information together with the data information. In both FIGURES 1 and 4, prefetch memory 26 operates as a separate cache line for a prefetch operation. If a memory instruction requests information absent from cache memory 12 (i.e. a cache miss situation), yet the information is stored in prefetch memory 26, then the information is transferred from prefetch memory 26 to cache memory 12. In such a situation, the cache miss situation does not result in processor 16 requesting such information from system memory 30. In the embodiment shown in FIGURE 1, prior to such a transfer to cache memory 12, the information in prefetch memory 26 is subject to being overwritten by information for a subsequent prefetch operation. By comparison, in the embodiment shown in FIGURE 4, information for multiple prefetch operations can be stored simultaneously in prefetch memory 26. Referring to FIGURE 1, if the address information stored in snoop register 28 matches address information stored in prefetch memory 26, then processor 16 invalidates the contents of prefetch memory 26. In such a situation, processor 16 does not cast out information from prefetch memory 26, because information is not modified within prefetch memory 26. Referring to FIGURE 4, for maintaining coherency of stored data information like processor 16, prefetch memory 26 of FIGURE 4 includes logic for snooping address information on system bus 28. If the snooped address information matches address information stored in prefetch memory 26, then prefetch memory 26 of FIGURE 4 invalidates its data contents corresponding to the snooped address information. With continuing reference to FIGURE 4, prefetch memory 26 does not cast out information, because information is not modified within prefetch memory 26. Notably, in both FIGURE 1 and FIGURE 4, prefetch memory 26 operates as a level-2 cache memory relative to cache memory 12. Nevertheless, unlike typical previous level-2 cache memories, prefetch memory 26 has a faster access time, less complex logic, and a smaller size than its corresponding level-1 cache memory 12. Prefetch memory 26 is significantly smaller and faster than system memory 30 and also is significantly smaller and faster than cache memory 12. This is possible because information stored in prefetch memory 26 is not required to be inclusive of all information stored in cache memory 12. Prefetch memory 26 operates as a level-2 cache memory relative to cache memory 12 only for prefetch instructions. Accordingly, cache memory 12 is able to input information significantly faster from prefetch memory 26 (steps 66 and 68 of FIGURE 2) than from system memory 30 (steps 70-74 of FIGURE 2). Without prefetch memory 26, a prefetch operation is significantly less practical unless cache memory 12 is made non-blocking. Nevertheless, it is difficult to verify proper operation of a non-blocking cache memory because additional memory instructions are not blocked from using cache memory 12 even while processor 16 waits for information from system memory 30. Moreover, logic for a non-blocking cache memory is more complex than logic for a blocking cache memory. Accordingly, relative to the alternative of cache memory 12 being made non-blocking, the combination of prefetch memory 26 with blocking cache memory 12 is advantageous. Such a combination is non-blocking with respect to prefetch instructions and is blocking with respect to other memory instructions.

Claims: An information processing system (10) in which a processor (16) processes instructions, said system including: a system memory (30) for storing information; a supplemental memory (26) coupled to said system memory for accessing and storing first information from said system memory in response to a prefetch instruction; and a cache memory (12) coupled to said supplemental and system memories for accessing and storing second information in response to a memory instruction, said second information being from said system memory if said first information does not include said second information; and characterised in that if said first information does include said second information, then said cache memory accesses said second information from said supplemental memory. The system of Claim 1 wherein said cache memory is a blocking cache memory. The system of Claim 1 or 2 wherein said cache memory is integral with said processor. The system of any preceding Claim wherein said supplemental memory is integral with said processor. The system of any preceding Claim wherein said supplemental memory is a prefetch memory. The system of Claim 5 wherein said first instruction is a prefetch instruction. The system of any preceding Claim wherein said second information from said system memory is stored in said cache memory without adding said second information to said supplemental memory. The system of any preceding Claim, further including means (20) coupled to said supplemental memory for maintaining coherency of said first information in said supplemental memory. The system of any preceding Claim wherein said supplemental memory is smaller than said cache memory. The system of any preceding Claim wherein said supplemental memory is smaller than said system memory. The system of any preceding Claim wherein said supplemental memory stores said first information in response to said first instruction having a first instruction type. The system of Claim 11 wherein said cache memory stores said second information in response to said second instruction having a second instruction type.

Inventors: KAHLE JAMES ALLAN, KAHLE, JAMES ALLAN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1994
Main classification: G06F12
IPC codes: G06F9, G06F12