Liquid crystal display panel driving device

Abstract: A liquid crystal display driving device which restrains fluctuation in pixel density when combining Multiple Line Selection and Pulse Width Modulation of display half tone. The orthonormal function generating circuit (7) applies a plurality of row signals represented by a set of orthonormal functions to the group of row electrodes (2) through the vertical driver (4) for each of selecting periods by set sequential scanning. The dot product computation circuit (8) carries out dot product computation between the set of orthonormal functions and the set of selected pixel data. The horizontal driver (5) applies to the column signal having the voltage level according to the result of the dot product computation, to the group of column electrodes (3). The frame memory (6) holds pixel data with gray shading including a plurality of bits. The dot product computation circuit (8) divides the set of pixel data by the bits and carries out the above dot product computation to generate the column signal components corresponding to the respective bit significance. The horizontal driver (5) arranges the column signal components in an order from the column signal component corresponding to a more significant bit with a large pulse width to that corresponding to a less significant bit with a small pulse width to compose the column signal and applies the signal to the group of column electrodes (3). The voltage level circuit (12) lowers the voltage level to the predetermined reference potential once between the column signal components and supplies the voltage level to the horizontal driver (5).

Description: The present invention relates to a device for driving a liquid crystal display panel. More specifically, but not exclusively, the present invention relates to a driving device suitable for Multiple Line Selection addressing, and to a driving circuit suitable for half tone display by Pulse Width Modulation (PWM). The liquid crystal display panel may be of the plain matrix type, and may employ STN liquid crystal. A plain matrix type liquid crystal display panel is composed of a liquid crystal layer interposed between a group of row electrodes and a group of column electrodes thereby providing pixels in a matrix. Conventionally, such liquid crystal display panels are driven by a Voltage Averaging Method. In this method, the respective row electrodes are sequentially selected one by one and data signals representative of ON/OFF status of pixels in synchronization with each timing are supplied to the selected electrodes. Consequently, each pixel receives a high voltage for one time slot (1/N of a frame time interval) within one frame period, during which all of (N number of) the row electrodes are selected, while the same pixel receives a constant bias voltage in the remaining time interval ((N-1)/N of the frame time interval). If the liquid crystal material used has a slow response, then there can be obtained a brightness corresponding to an effective value of the applied voltage waveform during one frame period. However, if a frame frequency is lowered as the multiplexing number increases, the difference between the one frame period and a liquid crystal response time is reduced, so that the liquid crystal responds to each applied pulse to thereby cause a brightness flicker called "frame response" which degrades the contrast. GB 2,014,822 discloses a video display apparatus in which a video signal representative of one line is sampled. Each sample represents a plurality of pixels in a line, each having n bits of different bit levels. All of the bits of one level are serially read out to a displaying means and then all of the bits of another level are serially read out, and so on. Recently, "Multiple Line Selection" has been proposed as a means to deal with such a problem of the frame response, for instance, disclosed in Japanese patent application 100642 of 1993. In this Multiple Line Selection method, each of the row electrodes is not selected one by one in the conventional manner, but a plurality of row electrodes are simultaneously selected to achieve the same effect as the high frequency drive, thereby reducing the above-mentioned problem at frame response. Being different from single line selection, multiple line selection requires a specific technique for realizing a free display. Namely, it is necessary to arithmetically process original image data and supply the processed data to a column electrode. Practically, a plurality of row signals represented by a set of orthonormal functions are applied to the group of row electrodes in sequence of the set of orthonormal functions during each selecting period. On the other hand, a dot product computation is carried out sequentially between the set of orthonormal functions and a set of selected pixel data, and then a column signal that has a voltage level corresponding to a result of the computation is applied to the group of column electrodes in synchronisation with the set sequential scanning during each selecting period. The above-mentioned Multiple Line Selection can be also adapted for use with a half tone display. There are a variety of methods for providing a halftone display, especially Pulse Width Modulation. This can be easily combined with a Multiple Line Selection, for instance, as disclosed also in the above-mentioned Japanese patent application 100642. In this method a given pixel data has a plurality of bits and gray shading is displayed therewith. When the dot product computation is carried out between the set of orthonormal functions and the set of pixel data, the set of pixel data is divided by the bits to carry out the computation and generate column signal components corresponding to significance of the bits. Further, the column signal components are arranged in the order of significance of the bits during each selecting period to compose a column signal, which is applied to a group of column electrodes, thereby obtaining a desired halftone display. Publication of the 12th International Display Research Conference, Japan Display 192 12/10/92 - 14/10/02, Horoshima, pp69-72; A.R. Corner et al: "Pulse-Height Modulation Gray Shading methods for Passive Matrix LCDs" discloses a number of Gray Shading methods using inter alia, pulse width modulation. Figure 9 shows an example of column signal according to the PWM. In this example, a pixel data is composed of 4 bits and can be displayed in 2 4 =26 gray levels. Four column signal components A, B, C and D are arranged in accordance with the significance of the respective bits during each of selecting periods Δt. A first column signal component A corresponds to the least significant bit, whose pulse width is represented by "1", A second column signal component B corresponds to the second least significant bit, whose pulse width is twice as large as that of the component A. A third column signal component C corresponds to the third least significant bit, whose pulse width is four times as large as that of the component A. A final column signal component D corresponds to the most significant bit, whose pulse width is eight times as large as that of the component A. Further, the voltage level of each column signal component is obtained by a dot product computation by corresponding significance of each bit. An effective voltage during the selecting period Δt is obtained as a weighted mean of the column signal components A to D. Further, the column signal component D corresponding to the most significant bit is the most dominant, while the column signal component A corresponding to the least significant bit makes the least contribution. The voltage levels of the column signal components A to D are switched very swiftly during the selecting period Δt. Therefore, the waveform is distorted when the voltage level is switched, resulting in an error in the hatched part of the waveform shown in Figure 9. The larger the difference between two adjacent voltage levels, the larger the degree of distortion of the waveform. This distortion prevents accurate half-tone display. Particularly, the error in column signal components corresponding to the more significant bits has more influence on fluctuation in half-tone display level compared with the error in those corresponding to the less significant bits. The example shown by Figure 9 has a problem in that the error in column signal components corresponding to the more significant bits is brought about according to voltage levels of the column signal components corresponding the less significant bits, finally resulting in a large fluctuation. That is to say, the error in a more significant bit is caused due to the difference between the voltages of the more significant bit and the preceding less significant bit. In view of the above-mentioned problems of the prior art, an object of the present invention is to prevent a decline in image quality in a half-tone display which is driven by combining Multiple Line Selection and Pulse Width Modulation. According to a first aspect of the invention, there is provided a liquid crystal display device for generating a displayed image from image data, characterised by means (5) for generating a matrix drive signal (G(t)) from said image data, the drive signal (G(t)) comprising a plurality of pulses (g1, g2 and g3) and returning to a reference level for a predetermined time period between each of said pulses. According to another aspect of the invention, there is provided a liquid crystal display panel driving device for driving, according to a given pixel data, a liquid crystal display panel having a pixel in a matrix by interposing a liquid crystal layer between a group of row electrodes, and a group of column electrodes; the device comprising: a first means for applying a plurality of row signals represented by a set of orthonormal functions to the group of row electrodes by set sequential scanning for each of the selecting periods; and a second means for sequentially carrying out a dot product computation between the set of orthonormal functions and a set of pixel data, and applying a column signal having a voltage level corresponding to a result of the computation, to each of the group of column electrodes in synchronisation with the set sequential scanning of each of the selecting periods; characterised in that the second means has a frame memory for holding pixel data with gray shading, each of which includes a plurality of bits, a dot product computing means for dividing the set of pixel data by the bits and carrying out the computation to generate a column signal components corresponding to a significance of each bit, and a driving means for arranging column signal components corresponding to bit significance in an order of the bit significance during each of selecting periods to compose the column signal, and lowering a voltage level between the column signal components to a predetermined reference potential and applying the column signal to the group of column electrodes. For a better understanding of the invention, an embodiment will now be described by way of example with reference to the accompanying drawings, in which:- Figure 1 is a block diagram showing a basic structure of the device for driving a liquid crystal display panel; Figure 2 is a waveform chart used to explain an operation of the device for driving a liquid crystal display panel shown in Figure 1; Figure 3 is a table showing a bit structure of the pixel data; Figure 4 is a waveform chart showing an example of the waveform of the column signal; Figure 5 is a waveform chart showing an example of the orthonormal or orthogonal functions; Figure 6 is a circuit diagram showing an example of the voltage level circuit included in the device for driving a liquid crystal display panel shown in Figure 1; Figure 7 is a circuit diagram showing an example of the pulse circuit used for controlling the voltage level circuit shown in Figure 6; Figure 8 is a waveform chart used to explain an operation of the pulse circuit shown in Figure 7; and Figure 9 is a waveform showing a column signal waveform generated by the conventional Pulse Width Modulation. In brief, a first feature of the embodiment, in contrast to the prior art shown in Figure 9, is that the column signal components corresponding to the significance of the respective bits are arranged in the sequence from those of the more significant bit to those of the less significant bit. Therefore, the voltage level of the column signal components of more significant bits causes the waveform of the column signal components of less significant bits to distort. In other words, the signal components making a large contribution to pixel density gives an error to the signal components making less contribution, so that it is possible to restrict errors in pixel density compared with the prior art. Further, as a second feature of the embodiment, the voltage level of the column signal components is once lowered to a predetermined reference potential, then it shifts to the next voltage level. As a result, the difference between two adjacent voltage levels may be decreased on average, the distortion of the waveform of the column signal can be restricted more than is the case in the prior art. Therefore, on the whole, it is possible to restrain fluctuation in pixel density, which was difficult in the prior art. Figure 1 is a schematic block diagram showing the inventive liquid crystal panel driving device. As shown in Figure 1, the inventive driving device is connected with a plain matrix type liquid crystal panel 1. This liquid crystal display panel 1 has a flat panel structure in which a liquid crystal layer is interposed between a group of row electrodes 2 and a group of column electrodes 3. STN liquid crystal, for example, can be used as the liquid crystal layer. The driving device has a vertical driver 4 which is connected with the group of row electrodes 2 to drive them. The driving device has also a horizontal driver 5 which is connected with the group of column electrodes 3 to drive them. The driving device further has a frame memory 6, an orthonormal or orthogonal function generating circuit 7, a dot product computing circuit 8. The frame memory 6 holds pixel data input in each frame. The pixel data represents the density of pixels provided at cross sections of the group of row electrodes 2 and the group of column electrodes 3. The pixel data has a plurality of bits which enables pixel density to be displayed with gray shading. In relation to this, the frame memory 6 has a bit plane corresponding to the significance of each bit. In Figure 1 a first bit plane corresponding to the most significant bit is shown on the top. The orthonormal or orthogonal function generating circuit 7 generates a plurality of orthonormal or orthogonal functions which are orthonormal or orthogonal to each other, and supplies sequentially the orthonormal or orthogonal functions in appropriate sets to the vertical driver 4. The vertical driver 4 applies a plurlaity of row signals represented by the sets of orthonormal or orthogonal functions to the group of row electrodes 2 by a set sequential scanning for each selecting period. Therefore, the orthonormal or orthogonal function generating circuit 7 and the vertical driver 4 may correspond to the above-mentioned first means. The dot product computing circuit 8 carries out a predetermined dot product computation between a set of pixel data sequentially read out from the frame memory 6 and a set of orthonormal or orthogonal functions transferred from the orthonormal or orthogonal function generating circuit 7 and feeds the result of the computation to the horizontal driver 5. The horizontal driver 5 applies a column signal, that has a voltage level according to the result of the dot product computation, to the group of column electrodes 3 in synchronization with the set sequential scanning for each selecting period. The voltage level necessary for composing the column signal is supplied from a voltage level circuit 12 in advance. Therefore, the horizontal driver 5 selects the voltage level according to the result of the dot product computation, and supplies it as the column signal to the group of column elecrodes 3. As understood from the above explanation,the frame memory 6, the dot product computing circuit 8, the horizontal driver 5, and the voltage level circuit 12 may comprise the above-mentioned second means. The voltage level circuit 12 supplies the predetermined voltage level also to the vertical driver 4. The vertical driver 4 sequentially selects a voltage level according to the orthonormal or orthogonal functions, and supplies it as the row signal to the group of row electrodes 2. The present device has a synchronizing circuit 9, a R/W address generating circuit 10, and a drive controlling circuit 11 in addition to the above main elements. The synchronizing circuit 9 makes a pixel data read timing from the frame memory 6 and a signal transfer timing from the orthonormal or orthogonal function generating circuit 7 synchronize with each other. A desired image is displayed by repeating the set sequential scanning in a frame time interval. The R/W address generating circuit 10 controls read/write of pixel data into the frame memory 6 by each bit plane. The address generating circuit 10 is controlled by the synchronizing circuit 9, and supplies a predetermined read out address signal to the frame memory 6. The drive controlling circuit 11 is controlled by the synchronizing circuit 9 and supplies a predetermined clock signal to the vertical driver 4 and the horizontal driver 5. As mentioned above, in order to display gray shading of the pixel by Pulse Width Modulation, the frame memory 6 divides pixel data composed of a plurality of bits into each bit plane and holds them. When the above specific dot product computation is carried out between the set of orthonormal or orthogonal functions and the set of pixel data, the dot product computing circuit 8 divides the set of pixel data by the bits, and carries out the dot product computation to generate column signal components corresponding to the significance of the respective bits. The horizontal driver 5 arranges the column signal components in an order from the column signal component corresponding to the more significant bit with a large pulse width to that corresponding to the less significant bit with a small pulse width during one selecting period to compose the column signal, and supplies it to the group of column electrodes 3. When the voltage level circuit 12 supplies a predetermined voltage level to the horizontal driver 5, the voltage level is once lowered to a predetermined reference potential among column signal components. Hereinafter, description is given to the multiple line selection where seven lines of the row electrodes are concurrently selected. Figure 2 shows a waveform of the seven line concurrent driving. F 1 (t) - F 8 (t) denote row signals applied to respective row electrodes. G 1 (t) - G 3 (t) denote column signals applied to respective column electrodes. The row signal F is set according to a Walsh function which is one of the complete orthonormal or orthogonal functions in (0, 1). The scanning waveform is set to "-Vr" corresponding to "0", set to "=Vr" corresponding to "1", and set to V 0 during a nonselection period. The voltage level V 0 for the nonselection period is set to "OV". Seven lines are selected concurrently as a group such that each group is sequentially scanned from top to bottom of the display. Eight times of the group sequential scanning corresponds to one period of the Walsh function to complete a first half cycle. In a next period, a second half cycle is carried out while the polarity of the signal is inverted to thereby remove a DC component. In a further next period, a combination pattern of the orthonormal or orthogonal functions is vertically shifted to compose row signals, and the row signals are applied to the group of row electrodes 2. The vertical shift is not necessarily required. On the other hand, the column signal applied to the group of column electrodes are dealt with by predetermined dot product computation in which each pixel data is Iij where "i" denotes a row number of the matrix, and "j" denotes a column number of the matrix. Supposing a case in which pixel data includes not a plurality of bits but a single bit, each dot data I ij is set to "-1" for the ON state pixel and set to "+1" for the OFF state pixel. Then, the column data signal Gj(t) applied to each signal electrode is basically set by carrying out the following dot product computation: In the above computation, the summation is effected only for the selected rows since the row signal is set to "0" level in the nonselection period. Accordingly, in the concurrent selection of the seven lines, the column signal can take eight voltage levels. Namely, the column signal requires a certain number of voltage levels equal to "concurrently selected line numbers + one". This potential level is supplied from the voltage level circuit 12 shown in Figure 1 as mentioned above. The above-mentioned dot product computation is applied to the pixel data having a single bit, and does not display gray shading. When the gray shading is displayed by the Pulse Width Modulation, each of the pixel data has a plurality of bits. The dot product computation for this will be explained hereinafter. Figure 3 shows a case where the pixel data having three bits is input to display half-tone with eight gray-levels. As shown in Figure 3, each of the pixel data has a first bit corresponding to the most significant bit, a second bit corresponding to the bit with middle significance, and a third corresponding to the least significant bit. Each of the bits is binary, taking 0 (zero) or 1. When all the three bits of the pixel data are "0", the pixel data displays the lowest level, a zeroth level. When all the three bits are "1", the pixel data displays the hgihest level, a seventh level. A desired half tone can be displayed according to numbers taken by the respective bits. In order to carry out a dot product computation with regard to the pixel data having three bits, the pixel data are divided into first, second and third bits. In other words, first of all, the dot product computation is carried out between the set of first bits and the set of the orthonormal or orthogonal functions to generate the column signal component corresponding to the most significant bit. Next, the similar dot product computation is carried out between the set of second bits and the set of the orthonormal or orthogonal functions to generate the column signal component corresponding to the middle significant bit. Lastly, the similar dot product computation is carried out between the set of the third bits and the set of the orthonormal or orthogonal functions to generate the column signal component corresponding to the least significant bit. Figure 4 shows an example in which the column signal components that are generated are arranged to compose the column signal. In Figure 4, a horizontal axis is denoted as a passed time t, and a vertical axis is denoted as a voltage level of a column signal G(t). As mentioned above, the column signal G(t) takes one of eight voltage levels V 1 to V 8 according to a result of the dot product computation. The column signal G(t) includes three column signal components g1, g2 and g3 in one selecting period Dt according to the three bits included in the pixel data The first column signal component gl is obtained by the dot product computation by using the set of the first bits shown in Fig. 3, and corresponds to the most significant bit. Therefore, its pulse width P1 is the largest of all. The second column signal component g2 corresponds to the middle significant bit, whose pulse width P2 is half as large as P1. The last column signal component g3 corresponds to the least significant bit, whose pulse width P3 is half as large as P2. An effective voltage of the column signal G(t) is represented by a total of the column signal components G1, G2 and G3, and desired half tone is displayed with those components. The column signal components are arranged in an order from the more significant bit to the less significant bit, and are applied to the column electrodes in this order. Further, the column signal components are once lowered to a predetermined reference level, and then shifted to the next voltage level. Therefore, a difference in potential between two adjacent voltage levels is decreased on average, thereby restraining distortion in wavelength of applied voltage. Fig. 5 shows waveforms of Walsh functions. In case of the concurrent seven-lines selection, for example, seven Walsh functions of the second to eighth orders may be utilized to form the set of the row signals. As can be understood from a comparison between Fig. 2 and Fig. 5, for instance, the row signal F 1 (t) corresponds to the Walsh function 2 of the second order of Figure 5. The function has a high level in a first half of one period and a low level in a second half of one period. Accordingly, the signal F1(t) is composed of pulses in the sequence (1,1,1,1,0,0,0,0). In a similar manner, the signal F 2 (t) corresponds to the third order Walsh function so that the pulses are arranged in the sequence of (1,1,0,0,0,0,1,1). Further, the signal F 3 (t) corresponds to the fourth order Walsh function so that the pulses are arranged in the sequence of (1,1,0,0,1,1,0,0). As can be understood from the above description, the set of the row signals concurrently applied to one group of the row electrodes are represented by an adequate combination pattern based on orthonormal or orthogonal relationship. In the Figure 2 case, the second group receives the set of the orthonormal or orthogonal signals F 8 (t) - F 14 (t) having the same combination pattern. In a similar manner, the third and further groups receive the set of the row signals corresponding to the same combination pattern. In a similar manner, the third and further groups receive the set of the row signals corresponding to the same combination pattern. Finally, Fig. 6 is a circuit diagram showing a structural example of the voltage level circuit 12 shown in Figure 1. As mentioned above, the voltage level circuit 12 supplies eight voltage levels V 1 to V 8 necessary to generate the column signals and also performs a predetermined switching operation to lower the respective voltage levels to the reference potential once. This switching operation is in synchronization with timing of applying the column signal components and is switched and controlled by a clock signal that is supplied from the drive controlling circuit 11 shown in, for instance, Fig. 1. As shown in Fig. 6, the voltage level circuit 12 has a front voltage dividing portion 31. This front voltage dividing portion 31 has two voltage dividing units each or which is composed of a resistor, a condenser and an operational amplifier, and divides a predetermined power source voltage according to a resistance ratio to obtain three voltage Levels -Vr, Vo, and + Vr. These voltage levels are supplied to the vertical driver 4 shown in Fig. 1 and used to synthesize a waveform of the row signal. The voltage level circuit 12 includes a middle voltage dividing portion 32, which includes eight voltage dividing units that are connected in series between -Vr and -Vr. The respective voltage dividing units output the eight voltage levels V 1 to V 8 that are equally divided. The voltage level circuit 12 further includes a rear voltage dividing portion 33, which includes eight voltage dividing units as the middle voltage dividing unit does. The respective voltage dividing units output eight voltage levels for controlling charge and discharge. Finally, eight switches with three terminals 34 are provided according to the respective voltage dividing units. The respective switches with three terminals output eight voltage levels to be supplied to the horizontal driver 5 shown in Fig. 1. The first input terminals 1 ○ of the respective switches with three terminals are applied with the voltage level that is output from the voltage dividing unit corresponding to the rear voltage dividing portion 33. Further, the second input terminals 2 ○ are commonly applied with a reference potential V 0 that is output from the front voltage dividing portion 31. Further, the third input terminals 3 ○ are applied with the voltage level that is output form the voltage dividing unit corresponding to the middle voltage dividing portion 32. Opening and closing of these input terminals 1 ○, 2 ○ and 3 ○ is controlled in accordance with predetermined control signals, and eight voltage levels V 1 to V 8 that have been once lowered to the reference potential can be obtained. In order to facilitate understanding, the control signals applied to the respective input terminals are represented by the corresponding numbers circled. Fig. 7 shows an example of a pulse circuit for supplying the control signals 1 ○, 2 ○ and 3 ○. This pulse circuit includes a flip flop, an AND gate with two terminals and two inverters. The pulse circuit generates desired control signals 1 ○, 2 ○ and 3 ○ according to clock signals CL1 and CL2 that are supplied from the drive controlling circuit 11 shown in Fig. 1. Fig. 8 is a waveform chart used to explain operation of the pulse circuit shown in Fig. 7. As shown in Fig. 8, synchronization pulses are generated at predetermined periodic intervals in the clock signal CL1. Synchronization pulses are also generated at predetermined periodic intervals in the clock signal CL2. The control signals 1 ○ are obtained by processing a pair of the clocks CL1 and CL2 with the flip flop shown in Fig. 7. The control signals 1 ○ includes pulses of negative polarity that are generated instantaneously in synchronization with the clock signals. The switches with three terminals shown in Fig. 6 are of low-active type, and the first input terminals 1 ○ are instantaneously energized in response to the negative pulses. As a result, the respective lines are charged and discharged. Then, the control signals 2 ○ generate negative pulses, and the second input terminals 2 ○ of the respective switches are energized. As a result, the respective lines are once connected with the reference potential V 0 . Then, the level of the control signals 3 ○ becomes low, and the third input terminals 3 ○ are closed. As a result, the respective lines are supplied with eight voltage levels V 1 to V 8 that are output from the middle voltage dividing portion 32. As mentioned above, according to the first feature of the present embodiment the column signal components are arranged in an order from the column signal components corresponding to a more significant bit with a large pulse width to those corresponding to a less significant bit with a small pulse width to compose a column signal during one selecting period. Then, the column signal is applied to the group of column electrodes to drive the liquid crystal panel by Multiple Line Section. This brings about an effect that fluctuation in display density of each pixel can be restrained when half tone is displayed by Pulse Width Modulation. Moreover, according to the second feature of the present embodiment, the voltage level is once lowered to the predetermined potential between the column signal components before the column signal is applied to the group of column electrodes. This operation brings about effects that distortion in voltage waveform of the column signal can be restrained, and that fluctuation in display density of each pixel can be restrained. As can be seen from Figure 4, the column signal G(t) includes three column signal components g1, g2 and g3 represented by pulses. Between the respective pulses of the column signal, the column signal G(t) reverts to a reference potential for a predetermined period. The reference potential, in the example shown in Figure 4, has a value half way between V 4 and V 5 - which is mid way between the maximum value (V 8 ) and the minimum value (V 1 ) which the column signal G(t) can assume. In the prior art illustrated in Figure 9, the column signal consists of four pulses representing column signal components A-D. The pulses in the column signal follow each other in immediate succession, i.e. there is no period between the respective pulses when the column signal reverts to a reference potential. In the present embodiment, one of the advantages of providing this period where the column signals reverts to the reference potential is that the rate of change of the column signal may be reduced in some instances, and therefore the quality of the displayed image may be improved because the waveform distortion (shown as hatched portions in Figure 9), due to rapid change in voltage level, is reduced. In some instances. however, the reversion of the column signal to the reference potential will actually increase the rate of change of the column signal (for example between pulses g1 and g2 in Figure 4). In most circumstances, the overall effect of the period at reference potential is to improve the quality of the displayed image.

Claims: A liquid crystal display device for generating a displayed image from image data, characterised by means (5) for generating a matrix drive signal (G(t)) from said image data, the drive signal (G(t)) comprising a plurality of pulses (g1, g2 and g3) and returning to a reference level for a predetermined time period between each of said pulses. A liquid crystal display panel driving device for driving, according to a given pixel data, a liquid crystal display panel having a pixel in a matrix by interposing a liquid crystal layer between a group of row electrodes (2), and a group of column electrodes (3); the device comprising: a first means (4) for applying a plurality of row signals represented by a set of orthonormal functions to the group of row electrodes (2) by set sequential scanning for each of the selecting periods; and a second means (5) for sequentially carrying out a dot product computation between the set of orthonormal functions and a set of pixel data, and applying a column signal having a voltage level corresponding to a result of the computation, to each of the group of column electrodes (3) in synchronisation with the set sequential scanning of each of the selecting periods; characterised in that the second means (5) has a frame memory for holding pixel data with gray shading, each of which includes a plurality of bits, a dot product computing means for dividing the set of pixel data by the bits and carrying out the computation to generate a column signal components corresponding to a significance of each bit, and a driving means for arranging column signal components corresponding to bit significance in an order of the bit significance during each of selecting periods to compose the column signal, and lowering a voltage level between the column signal components to a predetermined reference potential and applying the column signal to the group of column electrodes (3).

Inventors: EBIHARA TERUO, FIJITA HIROYUKI, HOSHINO MASAFUMI, MATSU FUJIO, ONIWA HIROTOMO, YAMAMOTO SYUHEI, EBIHARA, TERUO, FIJITA, HIROYUKI, HOSHINO, MASAFUMI, MATSU, FUJIO, ONIWA, HIROTOMO, YAMAMOTO, SYUHEI, EBIHARA, TERUO, C/O SEIKO INSTRUMENTS INC., FIJITA, HIROYUKI, C/O SEIKO INSTRUMENTS INC., HOSHINO, MASAFUMI, C/O SEIKO INSTRUMENTS INC., MATSU, FUJIO, C/O SEIKO INSTRUMENTS INC., ONIWA, HIROTOMO, C/O SEIKO INSTRUMENTS INC., YAMAMOTO, SYUHEI, C/O SEIKO INSTRUMENTS INC.
Applicants: SEIKO INSTR INC, SEIKO INSTRUMENTS INC.
Application year: 1994
Main classification: G09G3
IPC codes: G09G3, G02F1