Power supply wiring for semiconductor device

Abstract: Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed between the power source and the ground. As a result, a large capacitance bypass capacitor can be formed between the power source and the ground, and a power supply wiring which is great in effect of eliminating power supply noise can be obtained.

Description: FIELD OF THE INVENTION The present invention relates to a power supply wiring of a semiconductor device and, in particular, to a power supply wiring which pays attention to the reduction of noise of a semi-conductor integrated circuit device which requires high speed operation. BACKGROUND OF THE INVENTION In a CMOS circuit, current flows therethrough when the output value changes. In particular, if the CMOS circuit is operated at a fast speed, then the current is increased, and a large current will flow in a short period of time. This current causes noise to be generated at the power supply line and the ground line. In order to reduce the noise, a bypass capacitor may be connected between the power source and the ground to supply electric charges thereto. In Japanese Patent Application Laid-Open No. 62-237756 ("MOS Integrated Circuit"), there is disclosed a method of forming the foregoing bypass capacitor on a semiconductor chip. This is intended for forming the bypass capacitor between a power supply line 1 and a substrate, that is, a chip 10 by forming an oxide film 3, which is similar to the gate oxide film, below the power supply line 1 lying on the chip 10, as shown in Fig, 1. However, in the conventional process of making the CMOS integrated circuit, since an electrically conductive film is formed on the gate oxide film by using polysilicon or polycide, which is high in resistivity, if only the oxide film similar to the gate oxide film is formed below the power supply line made of the polysilicon or polycide, parasitic resistance is increased and the effect of eliminating noise becomes low. In Japanese Patent Application Laid-Open No. 2-144936 ("Semiconductor Integrated Circuit Device"), there is disclosed a method of forming a bypass capacitor in the wiring area of the gate array. This is intended for forming the gate oxide film 3 in the wiring area 11, on which the gate 4 is formed, as shown in Fig. 2. The area of the gate oxide film is made to extend up to the power supply line 1 to be connected through a contact 5 to the power source while the gate is made to extend up to the ground line 2 to be connected to the ground. A portion where the gate oxide film and the gate are overlapped forms a capacitor, which forms the bypass capacitor. However, since the wiring area of the gate array is wide, the parasitic resistance of the gate oxide film area and the gate is still increased, and the effect of eliminating the noise is low. Further, in an entirely laid-out gate array which provides no special wiring area, this method cannot be used. In the proceedings of the 1990 IEEE International Solid-State Circuit Conference, page 48, left column, third paragraph and the slide supplement, page 36, there is described a method of suppressing the parasitic resistance sufficiently small by connecting the capacitor similar in construction to the MOS transistor, in which the size of the gate 4 is limited to 12.5 µm in width (corresponding to the channel length) and 150 µm in length, to the nMOS transistor in parallel, as shown in Fig. 3, and by applying power source potential to the gate and ground potential to the source/drain. This is intended for determining the configuration of the capacity area made of the gate 4 and the gate oxide film 3 so that the area and the time constant become optimal. However, in the case of this size, if they are accommodated below the power supply wiring, it is necessary to set the width of the power supply wiring to more than 150µm. Further, since the gate electrode is thin such as 12.5µm in width, there is a possibility that it cannot cope with more higher operating speed in the future when the sheet resistance of the gate layer is high. EP-A-0 154 998 discloses a device according to the first part of claim 1. EP-A-0 230 154 discloses a MOS capacitor. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bypass capacitor formed on the chip which is very effective to remove the noise generated at the power supply wiring by laying it out so that the parasitic capacitor can be made smaller. That is, the object of the present invention is to provide a power supply wiring capable of effectively eliminating the power supply noise. The present invention also aims at providing a power supply wiring which is very effective to supply a sufficiently large current. According to the present invention, in order to achieve the foregoing end, there is provided a power supply wiring of a semiconductor device as defined in claim 1. A plurality of first power supply line structures and a plurality of second power supply line structures may be alternately disposed. A plurality of through holes of the first insulating layer may be formed at the substantially central portion of the first power supply line structure relative to the width direction thereof. The through holes of the first insulating layer may be disposed at an interval smaller than the substantially the same distance as the width of the first power supply line structure in the direction in which the first power supply line structure extends. The capacitance forming insulating film may comprise silicon oxide. The capacitance forming electrically conductive film may comprise polysilicon or polycide. The first and second insulating layers may be made of silicon oxide. The first and second power supply lines may be made of metal such as aluminum or aluminum alloy. The first power supply line may include a first metal layer formed on the capacitance forming electrically conductive film via the first insulating layer and electrically connected to the capacitance forming electrically conductive film through through hole of the first insulating layer and a second metal layer formed on the first metal layer via a first additional insulating layer and elecctrically connected to the first metal layer through through hole of the first additional insulating layer. A plurality of through holes of the first additional insulating layer may be disposed at an interval substantially equal to that at which through holes of the first insulating layer are disposed. The second power supply line may include a first metal layer formed on the semiconductor substrate via the second insulating layer and electrically connected to the semiconductor substrate through the through hole of the second insulating layer and a second metal layer formed on the first metal layer via a second additional insulating layer and electrically connected to the first metal layer through through hole of the second additional insulting layer. The first and second power supply lines may lie at the substantially same level and their adjacent lateral end portions may be so close that they form a capacitance. The parasitic resistance can be suppressed small by shortening the length and thickening the width of the electrode of the bypass capacitor. Therefore, the width of the power supply line is thinned and a long gate electrode is formed on the entire surface therebelow, the second power supply lines are arranged in parallel to the first power supply line and thereby a bypass capacitor is formed so as to provide a wider and shorter electrode of the bypass capacitor, which allows the parasitic capacitance to be made smaller. Further, by alternately disposing the first and second power supply lines, an amount of current as much as one which flows through a thick power supply line can be supplied. If the foregoing power supply wiring according to the present invention is used, then the gate capacitance which is about a half as large as the area of the master power supply line on a chip can be used as the bypass capacitor, and a large capacitance bypass capacitor can be formed between the power source and the ground. Further, since the value of the parasitic resistance which is connected to the bypass capacitor is small, the effect of eliminating the power supply noise is great. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view of a conventional bypass capacitor; Fig. 2 is a view of another conventional bypass capacitor; Fig. 3 is a view of still another conventional bypass capacitor; Fig. 4 is a cross-sectional view illustrating a specific embodiment of a power supply wiring according to the present invention; Fig. 5 is a partially cut-away plan view of Fig. 4; Fig. 6 is a schematic plan view illustrating a semiconductor integrated circuit device provided with a power supply wiring of Fig. 4; and Fig. 7 is a partially cut-away, partial plan view of the embodiment of Fig. 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention are hereinafter described with reference to the accompanying drawings. Fig. 4 illustrates a cross-sectional view of a power supply wiring according to the present invention, Fig. 5 a partially cut-away plan view thereof and Fig. 6 a schematic plan view of a semiconductor integrated circuit device provided with such a power supply wiring. Fig. 4 corresponds to a cross-sectional view taken along line IV-IV of Fig. 6. In Fig. 6, 20 denotes a p-type silicon substrate (chip), in which a CMOS integrated circuit is formed on the central area 23 of the surface. 21 denotes a bonding pad to be connected to the power supply potential, and 22 a bonding pad to be connected to the ground potential. A power supply line (first power supply line structure) 1 extends from the pad 21 up to the proximity of the pad 22 about the CMOS integrated circuit area 23. A ground line (second power supply line structure) 2 extends from the pad 22 up to the proximity of the pad 21 about the CMOS integrated circuit area 23. As illustrated in Fig. 4, ground lines 2, 2 are disposed so as to sandwich the power supply line 1. In each line structure, first metal layers 7a, 7b and second metal layers 6a, 6b are overlapped so as to lower the resistance. These first and second metal layers are made of, for example, aluminum or aluminum alloy. The thickness of these layers account for, for example, 0.5 through 2.0 µm. Further, 16a, 16b are each an insulating layer interleaved between the second metal layers 6a, 6b and the first metal layers 7a, 7b, and 17a, 17b are each an insulating layer disposed below the first metal layers 7a, 7b. These insulating layers are made of, for example, silicon oxide. The thickness of these insulating layers account for, for example, 0.5 through 2.0 µm. A silicon oxide film (hereinafter referred to as "gate oxide film") 3 similar to the gate oxide film and an electrically conductive film (hereinafter referred to as "gate") 4 made of polysilicon or polycide, which is similar to the gate, are formed on a p-type silicon substrate 20 below the power supply line 1 according to a process similar to that of making an ordinary nMOS transistor. Here, a portion where the gate 4 dose not overlap is provided below the ground line 2 outwardly of both ends of the gate oxide film of the power supply line 1 (that is, the edge portion of the power supply line 1 where it lies adjacent to the ground line 2), and an n-type area 8 is formed according to the process similar to that of making the source/drain area of the nMOS transistor. A p + -type area 9 is formed over most part of the remainder of the silicon substrate 20 below the ground line 2. Through holes TH1a are formed through the insulating layer 17a in order to make the first metal layer 7a and the gate 4 electrically interconnected. Through holes TH1b are formed through the insulating layer 17b and the gate oxide film in order to make the first metal layer 7b and the n-type area 8 or p + -type area 9 electrically interconnected. Through holes TH2a are formed through the insulating layer 16a in order to make the first metal layer 7a and the second metal layer 6a electrically interconnected. Through holes TH2b are formed through the insulating layer 16b in order to make the first metal layer 7b and the second metal layer 6b electrically interconnected. Thus, the edge of the ground line 2 is connected to the n-type area 8, and most central part of the ground line 2 is connected to the p + -type area 9. Interconnection of the ground line 2 and the p + -type area 9 forms a substrate contact, which serves to stabilize the substrate potential. Since the potential of the gate 4 equals that of the power source, an inversion layer is formed on the surface of the substrate below the gate oxide film 3, which is opposed to the gate 4, and turns into the ground potential through the n-type area 8. Thus, by sandwiching the gate oxide film 3 between the gate 4 and the inversion layer, a bypass capacitor is formed. A shown in Fig. 7, through holes TH1a, TH1a, which are formed through the insulating layer 17a on the gate 4, are disposed at the central portion relative to the width direction of the gate 4, that is, in the width direction of the power supply line 1. The through holes TH1a, TH1a are disposed at a predetermined interval P 1 in the direction in which the power supply line 1 extends. This interval P 1 is smaller than the width of the gate 4, that is, the width W of the power supply line 1. Through holes TH2a, TH1b and TH2b are each disposed at an interval similar to one for the foregoing through holes TH1a. The portion where the gate oxide film 3 and the gate 4 are overlapped lends itself to the creation of capacitance of the foregoing bypass capacitor and, hence, this capacitor will equal in length (the distance from the contact with the through hole TH1a up to the edge thereof) about a half of the width of the power supply line 1 and in width about the length of the power supply line 1. Since the inversion area also equals in length (the distance from the contact with the n-type area 8 up to the central portion thereof) about a half of the width of the power supply line 1 and in width about the length of the power supply line 1, the resistance will become small. Fig. 5 is a view of the structure of Fig. 4 as viewed from above. If the power supply is not sufficient when a single power supply line 1 is sandwiched between two ground lines 2, 2, the power supply line 1 and the ground line 2 may be additionally alternately disposed to obtain a power supply wiring having a power supply similar to the power supply line 1 of large width, as shown in Fig. 5. In this case, the capacitance of the bypass capacitor may also be increased. Although, in this figure, a large current can flow through a narrow width by overlapping the second metal layer and the first metal layer, as conventionally a power supply wiring structure comprising only the first metal layer or the second metal layer may be used. The case of the single first metal layer is obtained by removing the second metal layers 6a, 6b and through holes TH2a, TH2b of the insulating layers 16a, 16b in Fig. 4. In order to arrange the power supply wiring structure only with the second metal layer, a first metal layer will become necessary at the contact portion to be connected to the gate, n-type area and p + -type area. Since the thickness of the first and second metal layers is relatively thick and, further, the power supply wiring is laid out long, by making the interval between the power supply line 1 and the ground line 2 close to the minimum interval as desired (for example, 0.2 through 1.0 µm), capacitance may also directly be formed between the metal layer of the power supply line 1 and the metal layer of the ground line 2. This capacitor, which is disposed parallel to the capacitor comprised of the gate oxide film and the gate, serves to increase the capacitance. Incidentally, although the foregoing embodiment was described with reference to the semiconductor device comprising the CMOS integrated circuit device, it is obvious that the present invention can be equally applied to the nMOS integrated circuit device or the pMOS integrated circuit device. In this case, the electrically conductive type of the semiconductor substrate and the areas formed thereon is set reverse to that of the foregoing embodiment, as necessary. For example, the area 8 of Fig. 4 may be set to the p-type and the area 9 may be changed into the n-type. In this case, the first power supply line is set to the low potential and the second power supply line is set to the high potential. Further, in the foregoing embodiment, although the second power supply line was chosen as the ground line, the second power supply line may be one which differs from the first power supply line and yet which applies the voltage other than the ground voltage. As described above, if the semiconductor device comprises the MIS structure and especially the MOS structure, it is advantageous because the capacitance forming insulating film and the capacitance forming electrically conductive film of the power supply wiring can be made according to the process similar to that of making the circuit elements. However, the present invention may also be applied to the semiconductor devices other than the MIS structure devices. The present invention should not be understood to be restricted to the foregoing embodiments, but includes all the embodiments following the technical ideas represented by the claims.

Claims: A power supply wiring of a semiconductor device, having at least one first power supply line structure (1) and at least two second power supply line structures (2) which are disposed adjacent to both sides of said first power supply line structure (1), wherein said first power supply line structure (1) comprises a capacitance forming insulating film (3) formed on a semiconductor substrate (20), a capacitance forming electrically conductive film (4) on said capacitance forming insulating film (3) and a first power supply line (7a, 6a) formed on said capacitance forming electrically conductive film (4) via a first insulating layer (17a) and electrically connected to said capacitance forming electrically conductive film (4) through a through hole (THla) of said first insulating layer (17a), and, said second power supply line structures (2) each comprise a second power supply line (7b, 6b) formed on said semiconductor substrate (20) via a second insulating layer (17b) and electrically connected to said semiconductor substrate (20) through a through hole (THlb) of said second insulating layer (17b), characterized in that each of said second power supply line structures (2) includes a first area (8) of a first electrical conductivity type formed on a first surface portion of said semiconductor substrate (20) adjacent to said first power supply line structure (1) and a second area (9) of a second electrical conductivity type formed on a second surface portion of said semiconductor substrate (20), said second area (9) being adjacent and isolated from said first area (8), and, said second power supply line (7b, 6b) is electrically connected to said first area (8) and said second area (9), so that a bypass capacitor is formed between said first and second power supply lines by said capacitance forming electrically conductive film (4), said capacitance forming insulating film (3) and an inversion layer formed on a third surface portion of said semiconductor substrate (20) opposing said capacitance forming electrically conductive film (4). The power supply wiring of a semiconductor device as set forth in claim 1, wherein a plurality of first power supply line structures (1) and a plurality of second power supply line structures (2) are alternately disposed. The power supply wiring of a semiconductor device as set forth in claim 1, wherein a plurality of through holes (TH1a) of said first insulating layer (17a) are formed along the length of said first power supply line structure (1), in a region opposing a substantially central portion thereof. The power supply wiring of a semiconductor device as set forth in claim 3, wherein said through holes (TH1a) of said first insulating layer (17a) are disposed at an interval along the direction in which said first power supply line structure (1) extends that is smaller than the width of said first power supply line structure (1). The power supply wiring of a semiconductor device as set forth in Claim 1, wherein said capacitance forming insulating film (3) comprises silicon oxide. The power supply wiring of a semiconductor device as set forth in claim 1, wherein said capacitance forming electrically conductive film (4) comprises polysilicon or polycide. The power supply wiring of a semiconductor device as set forth in claim 1, wherein said first and second insulating layers (17a, 17b) are made of silicon oxide. The power supply wiring of a semiconductor device as set forth in claim 1, wherein said first and second power supply lines (7a, 6a,, 7b, 6b) are made of metal. The power supply wiring of a semiconductor device as set forth in claim 8, wherein said first and second power supply lines (7a, 6a, 7b, 6b) are made of aluminium or aluminium alloy. The power supply wiring of a semiconductor device as set forth in claim 1, wherein said first power supply line includes a first metal layer (7a) formed on said capacitance forming electrically conductive film (4) via the first insulating layer (17a) and electrically connected to said capacitance forming electrically conductive film (4) through a through hole (TH1a) of said first insulating layer (17a) and a second metal layer (6a) formed on said first metal layer (7a) via a first additional insulating layer (16a) and electrically connected to said first metal layer (7a) through a through hole (TH2a) of said first additional insulating layer (16a). The power supply wiring of a semiconductor device as set forth in claim 10, wherein a plurality of through holes (TH2a) of said first additional insulating layer (16a) are disposed at an interval substantially equal to that at which through holes (TH1a) of said first insulating layer (17a) are disposed. The power supply wiring of a semiconductor device as set forth in claim 1, wherein said second power supply line includes a third metal layer (7b) formed on said semiconductor substrate (20) via said second insulating layer (17b) and electrically connected to said semiconductor substrate (20) through said through hole (TH1b) of said second insulating layer (17b) and a fourth metal layer (6b) formed on said third metal layer (7b) via a second additional insulating layer (16b) and electrically connected to said first metal layer (7b) through a through hole (TH2b) of said second additional insulating layer (16b). The power supply wiring of a semiconductor device as set forth in claim 1, wherein said first and second power supply lines lie at substantially the same level.

Inventors: SUZUKI KAZUMASA, SUZUKI, KAZUMASA, SUZUKI, KAZUMASA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H01L23
IPC codes: H01L23, H01L27, H01L21