Driving method and apparatus for a ferroelectric liquid crystal display using compensation pulses

Abstract: A liquid crystal display device having a matrix of pixels in driven for gradational display with better temperature compensation and better flicker suppression by a driving method, wherein (a) a first voltage signal is applied to a pixel on a selected scanning line, the first voltage signal including a clear pulse, a writing pulse of a polarity opposite to that of the clear pulse and a correction pulse of a polarity opposite to that of the writing pulse, (b) a second voltage signal is applied to an associated pixel on a subsequent scanning line, the second voltage signal including a clear pulse, a writing pulse and a correction pulse of which polarities are respectively opposite to corresponding pulses of the first voltage signal, and (c) the correction pulse applied to the pixel on the selected scanning line is determined based on gradation data for the associated pixel on the subsequent scanning line, and the writing pulse applied to the pixel on the selected scanning line is determined based on gradation data for the pixel on the selected scanning line and the above-determined correction pulse.

Description: The present invention relates to a method of driving liquid crystal apparatus, particularly apparatus for use in television receivers, word processors, typewriters, apparatus inclusive of a light valve for projectors, a view finder for video camera recorders, or a computer terminal monitor, particularly such liquid crystal apparatus using a ferroelectric liquid crystal (hereinafter sometimes abbreviated as "FLC") as a display medium. It also concerns a liquid crystal apparatus adapted to perform such method. Clark and Lagerwall have disclosed a bistable FLC device using a surface-stabilised ferroelectric liquid crystal in, e.g. Applied Physics Letters, Vol. 36, No. 11 (June 1, 1980), pp 899-901; Japanese Laid-Open Patent Application JP-A-56-107217, U.S. Patent Nos. 4,367,924 and 4,563,059. Such a bistable ferroelectric liquid crystal device has been realised by disposing a liquid crystal between a pair of substrates disposed with a spacing small enough to suppress the formation of a helical structure inherent to liquid crystal molecules in chiral smectic C phase (SmC*) or H phase (SmH*) of bulk state and align vertical (smectic) molecular layers each comprising a plurality of liquid crystal molecules in one direction. Further, as a display device using such a ferroelectric liquid crystal (FLC), there is known one wherein a pair of transparent substrates respectively having thereon a transparent electrode and subjected to an aligning treatment are disposed to be opposite to each other with a cell gap of about 1 - 3 µm therebetween so that their transparent electrodes are disposed on the inner sides to form a blank cell, which is then filled with a ferroelectric liquid crystal, as disclosed in U.S. Patent No. 4,639,089; 4,655,561; and 4,681,404. The above-type of liquid crystal display device using a ferroelectric liquid crystal has two advantages. One is that a ferroelectric liquid crystal has a spontaneous polarization so that a coupling force between the spontaneous polarization and an external electric field can be utilized for switching. Another is that the long axis direction of a ferroelectric liquid crystal molecule corresponds to the direction of the spontaneous polarization in a one-to-one relationship so that the switching is effected by the polarity of the external electric field. More specifically, the ferroelectric liquid crystal in its chiral smectic phase shows bistability, i.e., a property of assuming either one of a first and a second optically stable state depending on the polarity of an applied voltage and maintaining the resultant state in the absence of an electric field. Further, the ferroelectric liquid crystal shows a quick response to a change in applied electric field. Accordingly, the device is expected to be widely used in the field of e.g., a high-speed and memory-type display apparatus. A ferroelectric liquid crystal generally comprises a chiral smectic liquid crystal (SmC* or SmH*), of which molecular long axes form helixes in the bulk state of the liquid crystal. If the chiral smectic liquid crystal is disposed within a cell having a small gap of about 1 - 3 µm as described above, the helixes of liquid crystal molecular long axes are unwound (N.A. Clark, et al., MCLC (1983), Vol. 94, p.p. 213 - 234). A liquid crystal display apparatus having a display panel constituted by such a ferroelectric liquid crystal device may be driven by a multiplexing drive scheme as described in U.S. Patent No. 4,655,561, issued to Kanbe et al to form a picture with a large capacity of pixels. The liquid crystal display apparatus may be utilized for constituting a display panel suitable for, e.g., a word processor, a personal computer, a micro-printer, and a television set. A ferroelectric liquid crystal has been principally used in a binary (bright-dark) display device in which two stable states of the liquid crystal are used as a light-transmitting state and a light-interrupting state but can be used to effect a multi-value display, i.e., a halftone display. In a halftone display method, the areal ratio between bistable states (light transmitting state and light-interrupting state) within a pixel is controlled to realize an intermediate light-transmitting state. The gradational display method of this type (hereinafter referred to as an "areal modulation" method) will now be described in detail. Figure 1 is a graph schematically representing a relationship between a transmitted light quantity I through a ferroelectric liquid crystal cell and a switching pulse voltage V. More specifically, Figure 1A shows plots of transmitted light quantities I given by a pixel versus voltages V when the pixel initially placed in a complete light-interrupting (dark) state is supplied with single pulses of various voltages V and one polarity as shown in Figure 1B. When a pulse voltage V is below threshold Vth (V < Vth), the transmitted light quantity does not change and the pixel state is as shown in Figure 2B which is not different from the state shown in Figure 2A before the application of the pulse voltage. If the pulse voltage V exceeds the threshold Vth (Vth < V < Vsat), a portion of the pixel is switched to the other stable state, thus being transitioned to a pixel state as shown in Figure 2C showing an intermediate transmitted light quantity as a whole. If the pulse voltage V is further increased to exceed a saturation value Vsat (Vsat < V), the entire pixel is switched to a light-transmitting state as shown in Figure 2D so that the transmitted light quantity reaches a constant value (i.e., is saturated). That is, according to the areal modulation method, the pulse voltage V applied to a pixel is controlled within a range of Vth < V < Vsat to display a halftone corresponding to the pulse voltage. However, actually, the voltage (V) - transmitted light quantity (I) relationship shown in Figure 1 depends on the cell thickness and temperature. Accordingly, if a display panel is accompanied with an unintended cell thickness distribution or a temperature distribution, the display panel can display different gradation levels in response to a pulse voltage having a constant voltage. Figure 3 is a graph for illustrating the above phenomenon which is a graph showing a relationship between pulse voltage (V) and transmitted light quantity (I) similar to that shown in Figure 1 but showing two curves including a curve H representing a relationship at a high temperature and a curve L at a low temperature. In a display panel having a large display size, it is rather common that the panel is accompanied with a temperature distribution. In such a case, however, even if a certain halftone level is intended to be displayed by application of a certain drive voltage Vap, the resultant halftone levels can be fluctuated within the range of I 1 to I 2 as shown in Figure 3 within the same panel, thus failing to provide a uniform gradational display state. In order to solve the above-mentioned problem, our research and development group has already proposed a drive method (hereinafter referred to as the "four pulse method") as disclosed in Japanese Patent Application JP-A 4-218022 and European Patent Application EP-A-0510606. In the four pulse method, as illustrated in Figures 4 and 5, all pixels having mutually different thresholds on a common scanning line in a panel are supplied with plural pulses (corresponding to pulses (A) - (D) in Figure 4) to show consequently identical transmitted quantities as shown at Figure 4(D). In Figure 5, T 1 , T 2 and T 3 denote selection periods set in synchronism with the pulses (B), (C) and (D), respectively. Further, Q 0 , Q 0 ', Q 1 , Q 2 and Q 3 in Figure 4 represent gradation levels of a pixel, inclusive of Q 0 representing black (0%) and Q 0 ' representing white (100 %). Each pixel in Figure 4 is provided with a threshold distribution within the pixel increasing from the leftside toward the right side as represented by a cell thickness increase. Our research and development group has also proposed a drive method (a so-called "pixel shift method", as disclosed in European Patent Appln. EP-A-0545400 entitled "LIQUID CRYSTAL DISPLAY APPARATUS"), requiring a shorter writing time than in the four pulse method. In the pixel shift method, plural scanning lines are simultaneously supplied with different scanning signals for selection to provide an electric field intensity distribution spanning the plural scanning lines, thereby effecting a gradational display. According to this method, a variation in threshold due to a temperature variation can be absorbed by shifting a writing region over plural scanning lines. A similar concept is also disclosed in JP-A 63-29733. An outline of the pixel shift method will now be described below. A liquid crystal cell (panel) suitably used may be one having a threshold distribution within one pixel. Such a liquid crystal cell may for example have a sectional structure as shown in Figure 6. The cell shown in Figure 6 has an FLC layer 55 disposed between a pair of glass substrates 53',53' including one, 53, having thereon transparent stripe electrodes 51 constituting data lines and an alignment film 54 and the other having thereon a ripple-shaped film 52' of e.g., an insulating resin, providing a saw-teeth shape cross section, transparent stripe electrodes 51' constituting scanning lines and an alignment film 54 In the liquid crystal cell, the FLC layer 55 between the electrodes has a gradient in thickness within one pixel so that the switching threshold of FLC is also caused to have a distribution. When such a pixel is supplied with an increasing voltage, the pixel is gradually switched from a smaller thickness portion to a larger thickness portion. The switching behavior is illustrated with reference to Figure 7A. Referring to Figure 7A, a panel in consideration is assumed to have portions having temperatures T 1 , T 2 and T 3 . The switching threshold voltage of FLC is lowered at a higher temperature. Figure 7A shows three curves each representing a relationship between applied voltage and resultant transmittance at temperature T 1 , T 2 or T 3 . Incidentally, the threshold change can be caused by a factor other than a temperature change, such as a layer thickness fluctuation, but an embodiment of the present invention will be described while referring to a threshold change caused by a temperature change, for convenience of explanation. As is understood from Figure 7A, when a pixel at a temperature T 1 is supplied with a voltage Vi, a transmittance of X % results at the pixel. If, however, the temperature of the pixel is increased to T 2 or T 3 , a pixel supplied with the same voltage Vi is caused to show a transmittance of 100 %, thus failing to perform a normal gradational display. Figure 7C shows inversion states of pixels after writing. Under such conditions, written gradation data is lost due to a temperature change, so that the panel is applicable to only a limited use of display device. In contrast thereto, it becomes possible to effect a gradational display stable against a temperature change by display data for one pixel on two scanning lines S1 and S2 as shown in Figure 7D. The drive scheme will be described in further detail hereinbelow. (1) A ferroelectric liquid crystal cell as shown in Figure 6 having a continuous threshold distribution within each pixel is provided. It is also possible to use a cell structure providing a potential gradient within each pixel as proposed by our research and development group in U.S. Patent No. 4,815,823 or a cell structure having a capacitance gradient. In any way, by providing a continuous threshold distribution within each cell, it is possible to form a domain corresponding to a bright state and a domain corresponding to a dark state in mixture within one pixel, so that a gradational display becomes possible by controlling the areal ratio between the domains. The method is applicable to a stepwise transmittance modulation (e.g., at 16 levels) but a continuous transmittance modulation is required for an analog gradational display. (2) Two scanning lines are selected simultaneously. The operation is described with reference to Figure 8. Figure 8A shows an overall transmittance - applied voltage characteristic for combined pixels on two scanning lines. In Figure 8A, a transmittance of 0 - 100 % is allotted to be displayed by a pixel B on a scanning line 2 and a transmittance of 100 - 200 % is allotted to be displayed by a pixel A on a scanning line 1. More specifically, as one pixel is constituted by one scanning line, a transmittance of 200 % is displayed when both the pixels A and B are wholly in a transparent state by scanning two scanning lines simultaneously. Herein, two scanning lines are selected for displaying one gradation data but a region having an area of one pixel is allotted to displaying one gradation data. This is explained with reference to Figure 8B. At temperature T 1 , inputted gradation data is written in a region corresponding to 0 % at an applied voltage V 0 and in a region corresponding to 100 % at V 100 . As shown in Figure 8B, at temperature T 1 , the range (pixel region) is wholly on the scanning line 2 (as denoted by a hatched region in Figure 8B). When the temperature is raised from T 1 to T 2 , however, the threshold voltage of the liquid crystal is lowered correspondingly, the same amplitude of voltage causes an inversion in a larger region in the pixel than at temperature T 1 .For correcting the deviation, a pixel region at temperature T 2 is set to span on scanning lines 1 and 2 (a hatched portion at T 2 in Figure 8B).Then, when the temperature is further raised to temperature T 3 , a pixel region corresponding to an applied voltage in the range of V 0 - V 100 is set to be on only the scanning line 1 (a hatched portion at T 3 in Figure 8B).By shifting the pixel region for a gradational display on two scanning lines depending on the temperature, it becomes possible to retain a normal gradation display in the temperature region of T 1 - T 3 . (3) Different scanning signals are applied to the two scanning lines selected simultaneously. As described at (2) above, in order to compensate for the change in threshold of liquid crystal inversion due to a temperature range by selecting two scanning lines simultaneously, it is necessary to apply different scanning signals to the two selected scanning lines. This point is explained with reference to Figure 7. Scanning signals applied to scanning lines 1 and 2 are set so that the threshold of a pixel B on the scanning line 2 and the threshold of a pixel A on the scanning line 1 varies continuously. Referring to Figure 7B, a transmittance-voltage curve at temperature T 1 indicates that a transmittance up to 100 % is displayed in a region on the scanning line 2 and a transmittance thereabove and up to 200 % is displayed in a region on the scanning line 1. It is necessary to set the transmittance curve so that it is continuous and has an equal slope spanning from the pixel B to the pixel A. As a result, even if the pixel A on the scanning line 1 and the pixel B on the scanning line 2 are set to have identical cell shapes as shown in FIgure 9B, it becomes possible to effect a display substantially similar to that in the case where the pixel A and the pixel B are provided with a continuous threshold characteristic (cell at the right side of Figure 7B). In the above-described known pixel shift method, pixels on an N-th scanning line and pixels on a preceding and adjacent (N-1)-th scanning line are written by simultaneously receiving different selection signals, so that data on the N-th scanning line is shifted to the (N-1)-th scanning line corresponding to a threshold change in associated pixels due to a temperature change, etc., thereby correcting the threshold change due to a temperature change, etc. In such a driving scheme, however, the scanning lines have to be selected consecutively and line-sequentially, so that the scheme is not compatible with an interlaced scanning scheme wherein physically adjacent scanning lines are skipped and are selected in different field scans. On the other hand, in an FLC device, one picture-writing time (one frame scanning period) amounts to 102.8 msec if it is assumed that one line-scanning time is 100 µsec and one picture is constituted by 1028 scanning lines. This corresponds to a drive frequency of 9.73 Hz, i.e., 9.73 times of picture writing in one second. If a brightness irregularity on a display picture is caused as a regular movement, the state is noticeable as flickering on the picture to human eyes. In order to remove the flickering, it is required to raise the drive frequency to about 40 Hz or adopt an interlaced scanning (thinning out or jump scanning) scheme. In order to raise the drive frequency to 40 Hz, it is necessary to set the one line-scanning period to 24 µsec in the above-mentioned case of driving 1028 scanning lines. This is difficult to be accomplished (A) in view of the presence of a delay in transmission of an applied voltage waveform along a liquid crystal panel and (B) if the gradation signal is constituted by pulse width modulation. Thus, this is difficult to be applied to a display panel of a large area and a high resolution. In order to prevent the flicker by providing an apparently increased drive frequency, a method of applying a so-called dummy scanning signal has been proposed by our research and development group as disclosed in JP-A 4-105285 However, this method is accompanied with a difficulty that a decrease in contrast is inevitably caused. Several interlaced scanning schemes are present in order to prevent the flicker. Among these, it is most desirable to use a scheme wherein the interlacing is performed at a weak regularity. For example, a first scanning line is first selected and subsequent scanning is performed with skipping of 8 lines in a first vertical scanning; a fifth scanning line instead of a second scanning line is first selected and subsequent scanning is performed with skipping of 8 lines in a second vertical scanning; a second scanning line is first selected and subsequent scanning is performed with skipping of 8 lines; and so on. That is a so-called random interlaced scanning scheme, which however is not compatible with the above-mentioned pixel shift method essentially requiring consecutive line-sequential scanning. With regard to a preferred embodiment of the present invention, it is mentioned that a liquid crystal apparatus is also accompanied with another problem as described below. The liquid crystal layer in an FLC device has a very small thickness on the order of 1 - 3 µm so as to assume a non-helical structure and, accordingly, a very small spacing between each pair of opposing electrodes for applying a voltage to the liquid crystal layer. It is thus necessary to provide an insulating layer for preventing short circuits between the opposing electrodes in addition to the alignment layer for aligning ferroelectric liquid crystal molecules in a certain direction. These layers are ordinarily composed of an electrically insulating material. On the other hand, in the case of an FLC, the liquid crystal layer per se has a spontaneous polarisation, so that an internal electric field is developed within the liquid crystal layer and positive and negative charges are generated so as to sandwich the liquid crystal layer and cancel the internal electric field. The generation of an electric field counter-acting the internal electric field caused by the spontaneous polarization is performed in most cases by movement of an ionic substance within the liquid crystal layer, the alignment film and the insulating film. Such an ionic substance generally has a certain mobility and requires a certain period for its movement in a certain distance through a medium such as the liquid crystal layer under a certain electric field. FLC molecules may be oriented in an UP state (the spontaneous polarization being directed from an upper substrate to a lower substrate) and a DOWN STATE (the spontaneous polarization being directed from the lower substrate to the upper substrate). In case where liquid crystal molecules in a pixel uniformly oriented in the UP state are switched into the DOWN state by application of an electric field therefor, the counter electric field (or charges) present so as to sandwich the liquid crystal layer for canceling the internal electric field in the UP state is not simultaneously removed but remains for a certain period. The magnitude of the counter electric field may be different depending on the magnitude of the spontaneous polarization and the capacity of the insulating layers (including the alignment layer). The remaining electric field is caused to disappear with time, and then an internal electric field due to the spontaneous polarization in the DOWN state and a counter electric field for canceling the internal electric field are formed. However, in the period until the disappearance of the counter electric field, the liquid crystal molecules are in a very unstable state that, while they are in the DOWN state, they are liable to be returned to the UP state due to the remaining counter electric field. Particularly, liquid crystal molecules inverted into the DOWN state close to a domain wall, i.e., a boundary between the DOWN state and the UP state, are in a state that they are liable to be returned to the UP state. Accordingly, if a voltage of the same polarity as an inversion voltage for switching to the UP state is applied to the liquid crystal molecules before the disappearance of the remaining electric field, the liquid crystal molecules can be returned to the UP state if the voltage is below the prescribed inversion voltage. The inversion of FLC due to application of a voltage is generally governed by a relationship of (pulse width) x (voltage) A = constant (wherein A is an experimentally determined value in the range of 1 < A < 3). Accordingly, even if the voltage is very low (1 - 2 volts), a re-inversion from DOWN to UP can occur when the voltage is applied to the liquid crystal layer for a long period. The presence of the counter electric field may be particularly problematic in case of gradational (halftone) display wherein a pixel is provided with an inversion threshold distribution and a plurality of domain walls are present in a pixel. For example, it may be problematic in case of writing in a pixel already having domain walls (i.e., a pixel after first writing) in a drive system, such as the above-mentioned pixel shift method, wherein a threshold change due to, e.g., a temperature change, is corrected by application of plural pulses. In such a drive method, a temperature change is compensated for according to the principle that a pixel subjected to overwriting in the first writing is subjected to return-writing in the second writing. This process inherently requires the co-presence of plural domain walls in a pixel. In effecting temperature compensation, it is necessary to effect a second writing without being affected by a first written state. This is explained with reference to Figure 10. Figures 10(a) and 10(b) show states satisfying the condition. Pixels at (a) and (b) after the clearing are written with different data in a first writing and then subjected to a second writing. In this case, if the pixels at (a) and (b) are subjected to an identical temperature change, identical areas of black domain must be written in the second writing. On the other hand, in view of pixels at (c) and (d), the pixel at (c) as a result of the second writing is subjected to writing of black domain C and also movement of the domain wall formed in the first writing to C'. Similarly, a pixel at (d) as a result of the second writing is subjected to not only the formation of D but also to movement of the domain wall formed in the first writing to D' and connections between D and D'. These phenomena at the pixels (c) and (d) are caused by application of an inversion voltage while liquid crystal molecules in the vicinity of the domain wall are unstable and susceptible to re-inversion, so that even unstable liquid crystal molecules not expected to be re-inverted are re-inverted. If such movement of domain walls to C' and D' and connection of domains occur, a required additivity of the first and second writings (i.e., the requirement of the second writing not being affected by the first written state) is not satisfied, so that an accurate temperature compensation is not effected. Such movement of or connection between domain walls are also dependent on the amount of the first writing (i.e., the electric field intensity at the time of the first writing) and it is generally difficult to satisfy the required additivity when the domain walls are required to be set with a small spacing therebetween. For example, in case where a cell having a structure as shown in Figure 6 was prepared by forming 30 nm (300Å)-thick alignment films 54,54' from a polyimide precursor liquid ("LQ-1802" available from Hitachi Kasei K.K.), a layer 55 of a liquid crystal material the same as the one used in an Example appearing hereinafter and 200 nm (2000Å)-thick insulating layers (not shown) of Ta 2 O 5 below the alignment films 54,54' an exact additivity could not be satisfied when the domain wall spacing was reduced to 20 - 30 µm or less. As described above, in an FLC device, a certain period is required because of a counter electric field corresponding to the internal electric field until inverted liquid crystal molecules are stabilized. Accordingly, in case of effecting a display through application of plural pulses, it has been necessary to place a certain period between writings to use a longer period of writing in a pixel or to effect a certain degree of excessive writing. Particularly in case of gradational display through formation of plural domain walls, a connection is liable to be formed between the domain walls, so that a higher degree of temperature compensation has been prevented. SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method of a ferroelectric liquid crystal device capable of effecting a gradational display with more accurate compensation for a threshold change as caused by a temperature change. According to the present invention, there is provided a method of driving a liquid crystal device of the type comprising a pair of oppositely disposed electrode plates having thereon a group of scanning lines and a group of data lines, respectively, and a layer of ferroelectric liquid crystal disposed between the pair of electrode plates, a pixel being provided at each intersection of the scanning lines and data lines; said driving method comprising: applying prescribed scanning signals to selected scanning lines and applying prescribed data signals to the data lines in synchronism with each scanning signal, whereby (a) a first voltage signal is applied across a first pixel at the intersection of one of the data lines and a selected scanning line, the first voltage signal including in the following order a clear pulse, a writing pulse of a polarity opposite to that of the clear pulse and a correction pulse of a polarity opposite to that of the writing pulse, and (b) following the completion of the application of said first voltage signal as aforesaid, a second voltage signal is applied across an associated second pixel at the intersection of said one of the data lines and the next sequentially selected scanning line, the second voltage signal including in the following order a clear pulse, a writing pulse and a correction pulse of which polarities are respectively opposite to corresponding pulses of the first voltage signal, wherein (c) the correction pulse applied across said first pixel is determined based on gradation data for said pixel on the next sequentially selected scanning line, and the writing pulse applied across said first pixel on the selected scanning line is determined based on gradation data for said first pixel and the above-determined correction pulse. Preferably the aforesaid method is applied to a liquid crystal device comprising a pair of oppositely disposed electrode plates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and a ferroelectric liquid crystal layer disposed between the pair of electrode plates so as to form a pixel at each intersection of the scanning electrodes and data electrodes; and drive means including scanning signal application means and data signal application means for writing plural times in each pixel to form a domain wall separating regions of different optical states in the pixel to effect a desired gradational display, wherein a film layer having a volume resistivity of at most 10 8 ohm.cm is disposed between the ferroelectric liquid crystal layer and at least one of said groups of scanning electrodes and data electrodes. The film having a volume resistivity of at most 10 8 ohm.cm may preferably comprise at least two layers including an organic layer disposed on the liquid crystal side for alignment control of the liquid crystal and an inorganic layer disposed on the electrode side. The lower resistivity film between the electrode and the liquid crystal layer is effective in accelerating the moment of charges occurring in response to the spontaneous polarization to the electrode side, so that domain walls formed in a pixel are stabilized between successive writings among a plurality of writings in a pixel to increase the additivity in temperature-compensating drive scheme, thereby providing an improved stability of display level during gradational display. These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A and 1B are graphs illustrating a relationship between switching pulse voltage and a transmitted light quantity contemplated in a conventional areal modulation method. Figures 2A - 2D illustrate pixels showing various transmittance levels depending on applied pulse voltages. Figure 3 is a graph for describing a deviation in threshold characteristic due to a temperature distribution. Figure 4 is an illustration of pixels showing various transmittance levels given in the conventional four-pulse method. Figure 5 is a time chart for describing the four-pulse method. Figure 6 is a schematic sectional view of a liquid crystal cell applicable to the invention. Figures 7A - 7D are views for illustrating a pixel shift method. Figures 8A, 8B, 9A and 9B are other views for illustrating a pixel shift method. Figure 10 is an illustration of instability of domain walls observed. Figure 11 is a waveform diagram showing a set of drive signals according to an embodiment of the present invention. Figures 12A and 12B show waveforms for illustrating a function of the present invention. Figure 13 is a graph for illustrating an inversion threshold change. Figure 14 is a graph having normalized scales for illustrating a threshold change corresponding to that shown in Figure 13. Figures 15 - 17 are schematic illustrations for describing gradation data shift by successive pulses according to the present invention. Figure 18 is a block diagram of a liquid crystal apparatus for performing the present invention. Figure 19 is a block diagram of another liquid crystal apparatus for performing the present invention. Figure 20 is a time chart for controlled drive of the apparatus shown in Figure 19. Figure 21 is a graph showing the results of Example 1 of the present invention appearing hereinafter. Figure 22 is a sectional view of a liquid crystal device used in Example 2. Figure 23 is an illustration of a display state obtained in Example 2. Figure 24 is an illustration of conditions adopted in Example 3. Figure 25 is a waveform diagram showing a set of drive signals used in an embodiment of the present invention. Figures 26A and 26B illustrate a manner of constituting data signals in the waveform shown in Figure 25. Figure 27A shows plots of a relationship between transmittance and a modulation parameter, and Figure 27B illustrates voltage signals involved in the waveform shown in Figure 25. Figure 28 is a sectional view showing a structure of liquid crystal device according to another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 11 shows a set of drive signal waveforms according to an embodiment of the present invention. At S 1 - S 4 are shown scanning selection signals applied to mutually adjacent first to fourth scanning lines S 1 - S 4 and at I is shown a succession of data signals applied to a data line I in synchronism with the scanning selection signals to determine the display states of pixels on the data line I. A voltage of V app (i.e. I-S 2 ) is applied to a pixel at the intersection of the scanning line S 2 and the data line I. A scanning selection signal includes a clear pulse (A), a first selection pulse (B) and a second selection pulse (C). The clear pulse (A) is a pulse for resetting the pixels on a scanning line to either one of bright and dark states regardless of the content of data signals synchronized therewith and has a pulse width t 1 and a peak height Vs 0 . The first selection pulse (writing pulse) (B) is a pulse for inverting a 0 - 100 % region of a reset pixel in cooperation with a data pulse (Vi 1 ) applied to a data line in synchronism therewith and has a pulse width t 2 and a peak height Vs 1 . The second selection pulse (C) is a pulse for causing at a pixel on a scanning line concerned (S 1 ) a display state corresponding to a data pulse (Vi 2 ) determined based on a display state expected to be displayed at a pixel on a subsequent scanning line (S 2 ). It is to be noted that the pulse (C) is different from a known auxiliary signal for canceling the DC component on the scanning line. Such a known auxiliary signal is set to have a pulse width and a peak height determined so as not to change an already formed display state of pixels concerned. In contrast thereto, the second selection pulse (C) in the present invention is set to have a pulse width which is determined to change a display state of a pixel on a scanning line concerned depending on a display data for a pixel on a next adjacent scanning line so as to compensate for a possible threshold change at the pixel on the scanning line concerned due to a temperature change, etc. The second selection pulse (C) is applied in succession to the first selection pulse (B) in contrast with a pulse (C) shown in Figure 5 which is applied after lapse of a certain period after a pulse (B), in which period a pulse (B) for another scanning line is also applied. In other words, a succession of the clear pulse (A) and selection pulses (B) and (C) are applied to an n-th scanning line and thereafter an identical succession of the pulses (A), (B) and (C) is applied to a subsequent (n+1)-th scanning line. Accordingly, after the writing into pixels on an n-th scanning line is completed inclusive of a compensation for a threshold change, a subsequent scanning line is selected, so that the subsequent scanning line need not be a physically adjacent (n+1)-th scanning line but can be an arbitrary scanning line, such as an (n+10)th scanning line or an (n+100)th scanning line. The scanning selection signal including the pulses (A), (B) and (C) in Figure 11 may preferably be adopted in an interlaced scanning scheme so as to suppress a flicker on a panel which may be driven at a low frequency according to the pixel shift method. Alternatively, the scanning selection signal may also be adopted in a partial rewrite scheme wherein a part of scanning lines, e.g., m-th to (m+ 1 )th scanning lines, among all the scanning lines are selected (repetitively) to partially rewrite a part of the displayed picture, so as to effect a multi-window display at a high display quality free from flicker. In the above-mentioned pixel shift method, before a pulse (C) for a pixel on an n-th scanning line is applied, pulses (A) and (B) for a subsequently selected scanning line are applied, so that a disturbance of a displayed picture is caused, if skipping of scanning lines is performed as in an interlaced scanning scheme or a random access as in a partial rewrite. The driving method according to the present invention may be called a "random pixel shift method" if the possibility of random access of scanning lines in the pixel shift method is noted. Now, the driving method using the signal waveforms shown in Figure 11 will be described in further detail. When a succession of pulses shown in Figure 12A (similar to a scanning selection signal shown at S 2 in Figure 11) is applied to a liquid crystal layer at a pixel in an FLC device, the orientation of the liquid crystal is reset to one state (referred to as "DOWN") by application of a voltage pulse V 0 (reset state). Then, the liquid crystal can be re-inverted from DOWN state to the other orientation state (referred to as "UP") by application of a voltage pulse V 1 . At this time, if a pixel is provided with a threshold distribution, e.g., by a cell thickness distribution, it is possible to effect a gradational display. Now, it is assumed that a pixel having no threshold distribution is reset by application of pulse V 0 , then written in UP by application of pulse V 1 and further written in DOWN by application of pulse V 2 . At this time, the magnitude of the voltage pulse V 2 required for uniformly orienting the pixel to DOWN largely depends on the magnitude of the voltage pulse V 1 . In a specific case wherein a liquid crystal device cell identical to the one used in Example 1 described hereinafter was prepared and subjected to refresh-writing by application of signals as shown in Figure 12B (free from DC component as an average voltage within one cycle) at a cycle of about 30 Hz (t = 40 µsec). Figure 13 summarizes a relationship of re-inversion voltage pulses V 2 required for re-inversion after application of V 1 pulses with varying magnitude. In Figure 13, the voltage V 1 of the writing pulse is taken on the abscissa, and the ordinate represents the peak height of the pulse V 2 required for re-inversion when applied subsequent to the pulse V 1 having a peak height indicated on the abscissa. The results obtained at 30 °C and 40 °C are respectively shown in Figure 13. When the drive waveform shown in Figure 12B is applied, the liquid crystal is reset to DOWN state by application of the V 0 pulse and then re-written to UP state by application of the V 1 pulse. According to the data at 30 °C in Figure 13, if the V 1 pulse had a voltage value of 10.08 volts (pulse width = 40 µsec), the orientation state could be re-inverted to DOWN state by application of a V 2 pulse having a voltage value of 2.0 volts. However, if the V 1 pulse had a voltage of 11 volts, the V 2 pulse required a voltage value of 5 volts. In this way, the voltage value required for re-inversion by application of the V 2 pulse varied depending on the V 1 pulse and was saturated above a certain V 1 pulse as shown in figure 13. In either case of V 1 = 10.08 volts or 12 volts, the pixel was entirely written in UP when the V 2 pulse was 0 volt. Accordingly, it is also understood that, even if two pulses equally forming UP state are applied and then a re-inversion pulse for writing DOWN is applied, the magnitude of the re-inversion pulse required for the reinversion varies depending on the magnitude of the preceding pulse for forming UP state. The UP states formed by application of two V 1 pulses having different magnitudes appear to be optically identical to each other but can have different molecular alignment states. In other words, it may be said that the threshold for re-inversion by the V 2 pulse varies depending on the state of liquid crystal molecules subjected to application of the V 2 pulse. The phenomenon that the re-inversion threshold voltage by application of the V 2 pulse varies depending on the magnitude of the preceding V 1 pulse and is saturated above a certain V 1 voltage, is equally observed at different temperatures (Figure 13). Further examination of the relationship between the V 1 pulse and the V 2 pulse has also shown the following fact. If voltages V 1 and V 2 are normalized so as to provide "1" at the saturation of the re-inversion voltage V 2 , a relationship shown in Figure 14 is obtained. Figure 14 shows that the above-mentioned characteristic shows little dependence on temperature. That is, with reference to the V 1 and V 2 values at the saturation of the re-inversion voltage V 2 versus V 1 , if V 1 causes a certain proportion of change, V 2 also causes a corresponding proportional change. More specifically, if V 1 reduces to 0.8 with respect to a reference value (i.e., V 1 at the saturation of V 2 ), V 2 uniformly reduces to about 0.2 with respect to a reference value (i.e., V 2 at the saturation of V 2 or maximum V 2 ) regardless of the temperature being at 30 °C or 40 °C. From the characteristics shown in Figures 13 and 14, in the case where a driving voltage waveform as shown in Figure 12A or Figure 12B is applied to a liquid crystal layer in an FLC device having a threshold distribution in a pixel, it is possible to estimate the quantity of re-inversion by application of a V 2 pulse after writing by application of V 1 pulse. According to Figure 14 showing results obtained by a device having a cell thickness gradient in a pixel, it is understood that, when a pixel is written to a cell thickness d 1 and then supplied with pulses of V 1 = 1 (normalized value) and V 2 = 0.6, the domain walls can be reinverted in the range of 1 - 0.85 up to a cell thickness position of d 1 /d 2 = 0.85. The phenomenon is further described with reference to Figure 15. At a low temperature T 1 , a pixel is written in W 1 % by application of a V 1 pulse and returned by δW 1 % by application of a V 2 pulse. At a high temperature T 2 , a pixel is written in W 2 % (W 2 > W 1 ) by application of the V 1 pulse and returned by δW 2 % by application of the V 2 pulse. At this time, δW 1 =δW 2 . This means that the change in written amount (δW 1 and δW 2 ) by a succession of the V 1 and V 2 pulses is constant regardless of the temperature. Accordingly, a data quantity δΔ obtained by removing a writing change δW 2 ' caused by a temperature change does not depend on the temperature. Accordingly, if a writing quantity change (δW 2 ' in the above) can be corrected separately, a gradation data can be written by a succession of pulses V 1 and V 2 . Figure 16 illustrates functions of the V 1 and V 2 pulses. Referring to Figure 16, both a high temperature pixel and a low temperature pixel are reset to a wholly black state by application of a V 0 pulse and then written into "white" by application of a V 1 pulse. The white-writing quantity by the V 1 pulse differs at a high temperature and a low temperature, and the difference is corrected by a V 2 pulse More specifically, by application of the V 2 pulse subsequent to the V 1 pulse, (a) the written state formed by the V 1 pulse is corrected, and (b) the temperature-dependent difference or deviation is corrected. The voltage value for the V 2 pulse is determined first for (b) the temperature-dependent deviation, and then the V 1 voltage is determined so as to obtain a desired written quantity when followed by the V 2 voltage pulse. According to Figure 14, it is possible to know a re-inversion quantity by application of the determined V 2 voltage pulse depending on the magnitude of the V 1 voltage pulse, so that a desired gradation can be written by determining the V 1 voltage while taking the re-inversion quantity into consideration. The above driving principle is applicable not only to a device having a cell thickness gradient (electric field intensity distribution) in a pixel as shown in Figure 6 but generally to a device having an inversion threshold distribution in a pixel. In the above, it has been described possible to display a certain data by applying a succession of V 1 and V 2 pulses while removing the temperature-dependent deviation. Now, a temperature-compensation function of a V 2 pulse will be described with reference to Figure 17. In Figure 17, the abscissa represents a transmittance W (%). A device is assumed to have a monotonous threshold distribution in a pixel as shown in Figure 6 so as to satisfy a linear relationship between the transmittance W and the logarithm of a voltage ( l n V) at constant pulse width. It is actually possible to design such a cell thickness gradient. In case of writing in a pixel on a scanning line (N) which is assumed to be subjected to a sequence of "black" reset and "white" writing, a correction pulse V 2 is set in a direction of writing "black". Correspondingly, a subsequently selected (N+1)-th line may be subjected to a sequence of white reset, black writing and white correction. This is because the data on the (N+1)th line is shifted toward the N th line corresponding to a temperature deviation, the data carried by V 2 is naturally in the black writing direction in order to enter the Nth line and the expected gradational display on the (N+1)th line by V 1 is in the direction of writing black. In the present invention, a temperature range T 1 - T 2 allowing a temperature compensation is such a temperature range that the threshold change of FLC due to the temperature change amounts to 1/x wherein x denotes a threshold ratio in a pixel. This means a temperature range such that the lower limit of the threshold distribution at T 1 is equal to the upper limit of the threshold distribution at T 2 . V 2 assumes a voltage range of V 21 - V 22 allowing gradational display of 0 - 100 % corresponding to the threshold at T 2 (before being affected by V 1 ). In Figure 17, a horizontal line i represents a threshold of inversion after resetting at a low temperature T 1 . Accordingly, if a voltage in excess of i is applied, FLC causes a state inversion thereof. Herein, the V 1 pulse and the V 2 pulse have symmetrical thresholds while their polarities are different and, in Figure 17, the voltages are indicated with an identical sign. Next, the setting of V 2 and V 1 based on expected gradation data will be described. In consideration of the inversion threshold change due to V 1 described with reference to Figures 13 and 14, V 11 is assumed to represent a value of V 1 by which the resultant state is returned to 0 % display by application of V 21 , and V 12 is assumed represent a value of V 1 capable of retaining 100 % display even after application of V 22 , so that V 1 can assume a voltage range of V 11 - V 12 . Solid lines a - d in Figure 17 represent V 12 , V 11 , V 22 and V 21 , respectively, and actually have slopes because of an electric field intensity gradient due to a threshold distribution in a pixel. Referring to Figure 17, when V 11 is applied, a pixel is caused to have a gradation of Q 1 (%) at which a domain wall (hereinafter called a "wave plane Q 1 ") is formed. By the application of V 11 , the inversion threshold is changed from i to a dashed line e . The inversion threshold change ratio is constant as described before. With respect to the wave plane Q 1 , any voltage of V 21 - V 22 exceeds the above-mentioned e , so that the pixel is returned to 0 % display by the application of V 2 . Further, in case where Vq slightly higher than V 11 is applied as V 1 , a pixel is caused to display a gradation of Q 2 (%) higher than Q 1 and the inversion threshold is changed to a dashed line f . With respect to the line f , V 22 is always not below the line so that the wave plane Q 1 is inverted to 0 % display by application of V 22 but V 21 is partly below f , so that the inversion cannot be effected at the part. The part is denoted by Q 3 in Figure 17. Accordingly, in case where a gradation of 0 % is expected to be displayed, V 11 may be applied as V 1 even if V 2 determined based on gradation data is any of V 21 - V 22 . In case where a gradation of Q 3 is expected to be displayed, Vq may be applied as V 1 for V 21 , and a voltage higher than Vq may be applied for V 22 since 0 % display results if V 1 = Vq. For displaying a gradation of 100 %, a value of V 1 providing Q 4 is applied for V 2 = V 21 and a value of V 1 providing Q 5 is applied for V 22 . More specifically, V 1 providing Q 5 is V 12 . Incidentally, the gradation display upper limit is 100 %, Q 4 and Q 5 actually mean 100 % display but, as the inversion threshold change depending on V 1 is present, Q 4 and Q 5 are indicated in excess of 100 % so as to cover such cases. Dashed lines g and h represent the respective threshold changes. A temperature change in Figure 17 is assumed to correspond to an increase in applied voltage V 1 and V 2 relative to the inversion threshold of the liquid crystal and is regarded as identical to parallel movement of 0 % position and 100 % position toward a K-axis. This corresponds to parallel movement of a [0, 100] region to a [-100, 0] region in Figure 17. In case of a temperature increase, writing by a V 2 pulse occurs in a 0 % side. This is because V 2 for an N-th line is determined by gradation data for an (N+1)-th line. Thus, the threshold is lowered due to the temperature increase and, corresponding to the threshold change, the gradation data for the (N+1)-th line is written on the N-th line. On the N-th line, V 2 and V 1 are of mutually opposite polarities. The writing directions on the N-th and (N+1)-th lines are mutually opposite. Accordingly, the shift of gradation data for the (N+1)-th line by V 2 is effected in black-writing if the N-th line is subjected to white writing. Gradation data for the N-th line is shifted to an (N-1)-th line by V 2 corresponding to the shift of gradation data for the (N+1)-th line thereto. Accordingly, gradation data are displayed while being sequentially shifted to adjacent lines. For example, in case where the gradation data for the (N+1)-th line is 50 %, a pixel is inverted to 50 % black by black writing with V 1 at T 1 and, even if 50 % of gradation data is shifted to the N-th line due to a temperature increase, the gradation data shifted to the N-th line is the remaining white (50 %), so that no black writing by V 2 is caused on the N-th line. In the case of the same 50 % shift, however, if the gradation data on the (N+1)-th line is 80 % black, the remaining 20 % white and 30 % black are shifted to the N-th line, so that 30 % black writing is effected by V 2 . If the gradation on the (N+1)-th line is 100 % black, 50 % black writing is effected by V 2 on the N-th line. The above point will be further described with reference to Figure 17, wherein an intersection of a dot-and-dash line j and a solid line i provided a projection Q 6 on the abscissa which is at an exactly mid point in the range [-100, 0], so that the line j exceeds the inversion threshold in the range [-100, Q 6 ) and is below the inversion threshold in the range [Q 6 , 0]. Accordingly, in case of the V 2 pulse having a voltage of V 2 j, writing on the 0 % side does not occur unless the threshold change due to a temperature change requires a rewriting of 50 % or higher. A necessary condition for effecting a drive in combination with temperature compensation by applying a succession of V 1 and V 2 pulses according to the present invention is that the liquid crystal threshold distribution after writing with the V 1 pulse is steeper than the electric field intensity distribution applied to the pixel. According to the above-described driving principle, as shown in strips at the lower part of Figure 17, data (indicated as a hatched part) displayed on scanning lines are continuously changed from a low temperature (T 1 ) to a high temperature (T 2 ) so that data expected to be displayed on an (N+1)-th line at T 1 is displayed on an N-th line at T 2 . According to the driving method of the present invention, when an entire liquid crystal panel is at a temperature of, e.g., T 1 , all the pixels effect expected gradational display of their own scanning lines and, when the entire liquid crystal panel is at a temperature T 2 , all the pixels display gradation data on respectively subsequent scanning lines. Accordingly, in the latter case, the display is deviated by one line but the one-line deviation can be substantially ignored since an actual liquid crystal panel includes a large number of scanning lines. Further, in case where a temperature gradient from a side of T 1 to an opposite side of T 1 is developed along a panel, the expected display is performed on the T 1 side but the shift of gradation data is gradually increased toward the T 2 side. As described above, however, one-line shift can be substantially negligible and adjacent two scanning lines can be regarded as at the same temperature, so that substantially no problem is caused by such a temperature distribution. Figure 18 is a block diagram of a liquid crystal apparatus including a drive circuit for supplying a drive signal waveform as shown in Figure 11 to a liquid crystal panel 32. Referring to Figure 18, the apparatus includes an image data source 21 for supplying a set of image data I 1 for pixels on a scanning line and image data I 2 for pixels on a subsequently selected scanning line. These data are converted into binary signals by an A/D converter 22. The binary signals are divided through a controller 23 to scanning signals and data signals supplied to a scanning side drive circuit and a data side drive circuit. The data side drive circuit includes a data signal generator circuit 24 for determining Vj 2 (V 2 for pixels on a j-th scanning line) from the image data I 2 and a data signal generator circuit for determining Vj 1 (V 1 for pixels on the j-th scanning line) from Vj 2 and I 1 . These data signals are supplied through a data side shift register 26, a decoder 27 and an analog switch 28 to the liquid crystal panel 32. The scanning side drive circuit includes a scanning side shift register 29, a decoder 30 and an analog switch 31, through which scanning selection signal are supplied to scanning lines constituting the liquid crystal panel 32 based on scanning line address data. A liquid crystal apparatus for performing the above described method may include a liquid crystal device having a structure as shown in Figure 6 including a film 54 or 54' between the electrode and the liquid crystal layer, which film is characterised by a volume resistivity of at most 10 8 ohm.cm and drive means suitable for causing partial inversion of the pixels by the method described above. The film disposed between the electrode and the liquid crystal layer used in the liquid crystal apparatus has a volume resistivity of at most 10 8 ohm.cm, preferably 10 4 - 10 7 ohm.cm. In case where the film has a volume resistivity of below 10 4 ohm.cm, an electrical continuity between the pixels cannot be ignored, so that it becomes necessary to pattern the film similarly as the electrode. It is desired that the film has a thickness of at most 200 nm (2000Å), preferably at most 100 nm (1000Å). The film may preferably comprise a known alignment film material, such as polyimide or polysiloxane, containing conductive or semiconductive fine particles, such as those of SnO 2 and In 2 O 3 , therein. Alternatively, the film may have a laminar structure comprising at least two layers including an alignment film of an organic conductor, such as polypyrrole, polyaniline or polyacetylene, or a known organic insulating alignment film material, such as polyimide, on the liquid crystal side; and an inorganic film layer of a conductive or semiconductor material such as Sn x O y , In x O y or a composite of these, or an inorganic insulating material on the electrode side. The film may have an appropriate composition, dopant content or thickness ratio so as to provide a volumetric resistivity of at most 10 8 ohm.cm, preferably 10 4 - 10 7 ohm.cm. The volumetric resistivity VR of a laminate film may be calculated as follows: VR = (VR 1 ·t 1 + VR 2 ·t 2 + ...)/(t 1 + t 2 ...), wherein VR 1 , R 2 ... denote the volumetric resistivities of the materials constituting the component layers and t 1 , t 2 ... denote the thicknesses of the component layers. The liquid crystal device having such a film between the electrode and the liquid crystal layer, preferably on both substrates, may be included as a display panel 103 in a liquid crystal apparatus as represented by a block diagram shown in Figure 19. More specifically, Figure 19 is a block diagram of a display panel and a control system for a liquid crystal display apparatus and Figure 20 is a time chart for communication of image data therefor. Hereinbelow, the operation of the apparatus will be described with reference to these figures. A graphic controller 102 supplies scanning line address data for designating a scanning electrode and image data PD0 - PD3 for pixels on the scanning line designated by the address data to a display drive circuit constituted by a scanning line drive circuit 104 and a data line drive circuit 105 of a liquid crystal display apparatus 101. The scanning line address data (A0 - A15) and display data (D0 - D1279) must be differentiated. A signal AH/DL is used for the differentiation. The AH/DL signal at a high (Hi) level represents scanning line address data, and the AH/DL signal at a low (Lo) level represents display data. The scanning line address data is extracted from the image data PD0 - PD3 in a drive control circuit 111 in the liquid crystal display apparatus 101 outputted to the scanning line drive circuit 104 in synchronism with the timing of driving a designated scanning line. The scanning line address data is inputted to a decoder 106 within the scanning line drive circuit 104, and a designated scanning electrode within a display panel is driven by a scanning signal generation circuit 107 via the decoder 106. On the other hand, display data is introduced to a shift register 108 within the data line drive circuit 105 and shifted by four pixels as a unit based on a transfer clock pulse. When the shifting for 1280 pixels on a horizontal one scanning line is completed by the shift register 108, display data for the 1280 pixels are transferred to a line memory 109 disposed in parallel, memorized therein for a period of one horizontal scanning period and outputted to the respective data electrodes from a data signal generation circuit 110. The drive of the display panel 103 in the liquid crystal display apparatus 101 and the generation of the scanning line address data and display data in the graphic controller 102 are performed in a non-synchronous manner, so that it is necessary to synchronize the graphic controller 102 and the display apparatus 101 at the time of image data transfer. The synchronization is performed by a signal SYNC which is generated for each one horizontal scanning period by the drive control circuit 111 within the liquid crystal display apparatus 101. The graphic controller 102 always watches the SYNC signal, so that image data is transferred when the SYNC signal is at a low level and image data transfer is not performed after transfer of image data for one scanning line at a high level. More specifically, referring to Figure 19, when a low level of the SYNC signal is detected by the graphic controller 102, the AH/DL signal is immediately turned to a high level to start the transfer of image data for one horizontal scanning line. Then, the SYNC signal is turned to a high level by the drive control circuit 111 in the liquid crystal display apparatus 101. After completion of writing in the display panel 103 with lapse of one horizontal scanning period, the drive control circuit 111 again returns the SYNC signal to a low level so as to receive image data for a subsequent scanning line. Example 1 A liquid crystal cell having a sectional structure as shown in Figure 6 was prepared. The lower glass substrate 53'was provided with a saw-teeth shape cross-section by transferring an original pattern formed on a mould onto a UV-curable resin layer applied thereon to form a cured acrylic resin layer 52'· The thus-formed UV-cured uneven resin layer 52'was then provided with stripe electrodes 51' of ITO film by sputtering and then coated with an about 30 nm (300 Å)-thick alignment film 54' (formed with "LQ-1802", available from Hitachi Kasei K.K.). The opposite glass substrate 53 was provided with stripe electrodes 51 of ITO film on a flat inner surface and coated with an identical alignment film 54. Both substrates (more accurately, the alignment films 54 ,54' thereon) were rubbed respectively in one direction and superposed with each other so that their rubbing directions were roughly parallel but the rubbing direction of the lower substrate formed a clockwise angle of about 6 degrees with respect to the rubbing direction of the upper substrate. The cell thickness (spacing) was controlled to be from about 1.10 µm as the smallest thickness to about 1.64 µm as the largest thickness. Further, the lower stripe electrodes 51'were formed along the ridge or ripple (extending in the thickness direction of the drawing) so as to provide one pixel width having one saw tooth span. Thus, rectangular pixels each having a size of 300 µm x 200 µm were formed. Then, the cell was filled with a chiral smectic liquid crystal showing the following phase transition series and properties. The liquid crystal cell (device) thus prepared was driven by applying a set of drive signals shown in Figure 11. The respective pulses were characterized by parameters of t 1 = 150 µsec, t 2 = 40 µsec, Vs 0 = 7.0 volts, Vs 1 = 13.1 volts, Vs 2 = 6.9 volts, -3.1 volts ≦ Vi 1 ≦ 3.1 volts, -1.41 volts ≦ Vi 2 ≦ 1.41 volts. The liquid crystal device driven in the above-described manner showed a display characteristic represented by a curve A in Figure 21 wherein the abscissa represents V 1 = Vs 1 - Vi 1 and the ordinate represents a relative transmittance (%). On the other hand, when the same device was driven in the same manner by using driving waveforms shown in Figure 11 while omitting the pulses corresponding to the selection signal (c) (i.e., Vs 2 = 0 and Vi 2 = 0), the device showed the display characteristics represented by curves B in Figure 21. Thus, in this case, the resultant transmittances were remarkably different depending on a temperature change, thus failing to show a good gradation characteristic. In contrast thereto, the curve A obtained according to the drive method of the present invention showed a good gradation characteristic with temperature compensation. Incidentally, a better gradation display characteristic with less influence by a subsequent data signal was obtained when a longer interval period (Y in Figure 11) was placed between successively applied data signals, and a particularly good result was attained when Y was about 200 µsec. Example 2 A liquid crystal cell (device) having a cell thickness gradient as shown in Figure 22 was obtained in a similar manner as in Example 1 except that the cell thickness distribution was in the range of 1.0 - 1.4 µm, and the rubbing directions applied to the two substrates were set to cross at an angle of about 10 degrees in addition to the change in the sectional structure. The device was driven by applying a set of drive signals as shown in Figure 11 by using a circuit as shown in Figure 18. The liquid crystal device used in this Example included pixels formed by scanning lines 51' each having a width A as shown in Figure 22, so that it could not cause a complete pixel shift as described hereinabove. However, as the brightness control could be effected in the device, a temperature compensation could be effected according to the driving method of the present invention. Figure 23 schematically show a display state formed in this Example. In each of the above-described Examples 1 and 2, the gradational display drive was effected by voltage modulation, but the modulation can also effected by either pulse width modulation or phase modulation. Example 3 In Example 1, the best result was obtained when the length of Y was set to about 200 µsec. In this Example, it was tried to shorten the period Y by applying a crosstalk prevention signal determined based on a data signal. The other features were identical to those adopted in Example 1. In order to produce a crosstalk prevention signal, the effect of pulses applied immediately after the Vs 2 pulse in the waveform shown in Figure 11 is examined with time. Figure 24 summarizes the analysis. Figure 24(a) shows a waveform except for the period Y. At (b) are shown addresses of the waveform. At (c) are shown experimentally measured effect factors obtained when the waveform at (a) was applied subsequent to the Vs 2 pulse. At (d) are shown example voltages of pulses included in the waveform at (a). These values are determined based on image data for a pixel on a scanning line concerned and image data for an adjacent pixel on an adjacent scanning line similarly as in Example 1. At (e) are shown values obtained by dividing the values at (d) with the values at (c). If the applied voltages at the period Y are assumed to be V Y1 and V Y2 , the effects thereof are shown as V Y1 /3 and V Y2 /7, respectively. The total of the values at (e) from Address 3 to Address 10 amounts to 0.037. This value may be reduced to zero by adjusting the voltages within the period Y. The values of V Y1 and V Y2 therefor must satisfy the following conditions: (V Y1 /3) + (V Y2 /7) = -0.0037 V Y1 = -V Y2 By solving the above equations, V Y1 and V Y2 are obtained as follows: V Y1 = -0.2 volt V Y2 = 0.2 volt By determining the waveform within the period Y in the above-described manner, it is possible to accomplish a good gradational display with less crosstalk. Example 4 A liquid crystal cell (device) having a sectional structure also as shown in figure 6 was prepared in the following manner. The lower glass substrate 53'was provided with a saw-teeth shape cross section by transferring an original pattern formed on a mold onto a UV-curable resin layer applied thereon to form a cured acrylic resin layer 52'· The thus-formed UV-cured uneven resin layer 52' was then provided with stripe electrodes 51' of ITO film by sputtering and then coated with a film 54', which was formed by applying a solution of polyaniline (molecular weight = ca. 200 - 300) and camphorsulfonic acid (as a strong acid) at concentrations of 0.7 wt. % and 0.3 wt. %, respectively in a mixture solvent of N-methylpyrrolidone and n-butylcellosolve by spinner coating at 1500 rpm for 20 sec, followed by baking at 200 °C for 1 hour. The opposite glass substrate 53 was provided with stripe electrodes 51 of ITO on a flat inner surface and coated with an identical polyaniline film 54 in the same manner as above. As a result of separate formation of an identical films 54,54' on a flat ITO coated glass substrate, the films 54, 54' showed a thickness of ca. 400 A and a volume resistivity of ca. 10 7 ohm.cm. The two-substrates were subjected to rubbing in the same manner as in Example 1. Further, by using the above-treated two substrates and the same liquid crystal material as in Example 1, a liquid crystal device including pixels each having a size of 300 µm x 200 µm was prepared otherwise in the same manner as in Example 1. Figure 25 is a waveform diagram showing a set of driven signal waveforms used in this Example including scanning signals applied to scanning lines S 1 , S 2 , S 3 , ..., data signals applied to a data line I, and a combined voltage signal applied to a pixel S 2 - I (i.e., a pixel at the intersection of the scanning line, and the data line I). In this Example, a gradation drive scheme according to the pixel shift method was adopted, so that adjacent two scanning lines were supplied with scanning signals having mutually reverse polarities at corresponding phases. Referring to Figure 25, the respective pulses were characterized by parameters of |Ve| = 18.0 volts, |Vs| = 17.0 volts, |Vi| = 5.0 volts, T = 40 µsec, δ = 26 µsec, t 1 = 7 µsec and t 2 = 7 µsec. The data signal modulation was effected according to a phase modulation scheme, and an outline of the data signal modulation is illustrated in Figure 26B. Figure 26B shows data signal voltage waveforms in the range of I (0 %) to I (100 %) for displaying the states respectively indicated in the parentheses. In the respective data signals, the width of a pulse portion A is variably modulated so as to provide a voltage signal having a width δ with writing data. The modulation of the portion A is set so that the width δ and the marginal width of the ΔT have a ratio of 1/γ:(1-1/γ). Such a ratio is set so as to make continuous the thresholds of inversion at a pixel which has been supplied with a scanning signal A in the first writing and a scanning signal B in the second writing in Figure 25. The width δ is 1/γ of the selection period ΔT of the scanning signal A. This condition is also given in order to make the thresholds continuous. Herein, γ denotes a slope ∂T/∂λ on a curve shown on a coordinate system having an ordinate of transmittance (T) and an abscissa of modulation parameter (λ) as shown in Figure 16A. Now, the modulation parameter (λ) will be described. Figure 27 shows a graph showing a relationship between transmittance (T) and modulation parameter (λ). In the case of using a modulation scheme as shown in Figure 26B , the abscissa is expressed on a logarithmic scale (ln) so as to represent the change in threshold of a liquid crystal by a parallel shift on the graph. In the drive scheme shown in Figure 25, the voltage applied to a pixel corresponding to a scanning selection pulse A in a scanning signal varies in a range of from a rectangular voltage of V 1 = Vth = 14 volts (as shown at (b-1) of Figure 27B) to a rectangular voltage of V 2 = Vsat = 20 volts (at (b-3) of Figure 27B). Then, if a modulation parameter (λ) is defined as a period (pulse width) weighed (e.g., multiplied) by a (varying) voltage, it is possible to obtain a relationship between transmittance (T) - Lnλ which is linear and may be shifted in parallel in accordance with a temperature change. The manner of weighing with a voltage (peak value) is explained based on an example. A pulse having a portion showing a peak value V 1 in a pulse length of t 1 (in total if two portions having V 1 are present) and a portion having a peak value V 2 in a pulse length t 2 may be determined to have a modulation parameter given by: λ = (V 2 /V 1 )·t 1 +t 2 . In case of Figure 27B, t 1 + t 2 = 40 µsec, V 1 = 14 volts and V 2 = 20 volts. If λ is determined in this way under the conditions of Figures 25 and 26, the selection voltage waveform varies in the range of from an L-shaped one having a portion of 10 volts - 32 µsec and a portion of 22 volts - 8µsec to a rectangular one having a 100 %-portion of 22 volts - 40 µsec. The above range is used for gradational display and a pulse of 10 volts - 40 µsec is used for display of 0 %. The latter corresponds to a voltage waveform given by a data signal I (-0 %) in Figure 26B. By disposing a low-resistivity film layer between the liquid crystal and the electrode as described above, it was possible to increase the stability of domain walls in a pixel during plural times of writing for a pixel, and also possible to provide an increased degree of temperature compensation. Further, the irregular movement of domain wall and fusion or connection of domain walls as described with reference to Figure 10(c) and (d) were prevented until the spacing between domain walls was reduced to 10 - 20 µm, compared with 20 - 30 µm as in a conventional device. Further, the number of reliably displayed gradation levels could be increased from about 8 to about 13, thus providing a remarkably improved gradational display characteristic. Example 5 A liquid crystal cell having a sectional pixel structure as schematically shown in Figure 28 was prepared. The cell included an uneven substrate structure including a glass substrate 41a, an uneven ITO film 32a, an SnO 2 layer 43a and a polyaniline layer 44a; an even substrate structure including a glass substrate 41a, an ITO film 42b, an SnO 2 layer 43b and a polyaniline layer 44b; and an FLC layer 45 disposed between the substrates. The ITO film 42a was provided with ca. 2 µm-wide stripe projections extending in the direction of thickness of the drawing which were spaced thee different pitches of 2 µm, 3 µm and 5 µm laterally from one side to the other side. The SnO 2 films 43a and 43b were formed in a thickness of 90 nm (900Å) by ion plating at a rate of 6 Å/sec in an Ar/O 2 (100/70) mixture environment under the conditions, the resultant SnO 2 film showed a volume resistivity of ca. 10 5 ohm.cm. Such an SnO 2 film may also be formed by sputtering in a volume resistivity of, e.g., 10 6 - 10 7 ohm.cm. The thus formed SnO 2 film 43a and 43b were coated with polyaniline layers 44a and 44b, respectively, in a thickness of ca. 100 Å each, in the same manner as in Example 4. The resultant laminate film including the SnO 2 film and the polyaniline film showed a volume resistivity of 1.5x10 7 ohm.cm. The resultant polyaniline layer 44a on the uneven substrate was provided with stripe projections of ca. 200 nm (2000 Å) in height corresponding to the uneven ITO film 42a and rubbed in a direction of the stripe projections. The polyaniline layer 44b on the other even substrate was also rubbed in one direction. The two substrates were applied to each other with SiO 2 spacer beads (of 1.4 µm-dia.) dispersed therebetween so that the rubbing direction on the even substrate formed a clockwise angle of 10 degrees with respect to the rubbing direction of the uneven substrate as viewed from the uneven substrate. The resultant blank cell was filled with the same liquid crystal material as in Example 1 to form a liquid crystal cell. The thus-formed liquid crystal cell was found to show a gradational display characteristic such that domain inversion was initiated from a side of pitches being formed with a small spacing (2 µm) and propagated toward the other side in a pixel. At a pulse width ΔT = 40 µsec, the inversion was partly initiated at V = 18 volts and 100 % inversion was caused at 22 volts, thus showing a threshold distribution rate of 1.22. By forming an electroconductive primary layer (SnO 2 layer) below the alignment layer as described above, the domain stability was improved. When the device was subjected to a matrix drive by application of waveforms shown in Figure 25, disappearance of small domains (2 µm or smaller in diameter) was suppressed and the stability of domains were increased against plural times of writing in a pixel, thus providing an improved display characteristic. As described hereinabove, a gradational display system capable of correcting a temperature-dependent deviation and also capable of interlaced scanning drive is provided by applying specific sequential pulses after a clearing pulse. As a result, it has become possible to realize a good gradational display with reduced flicker and contrast irregularity.

Claims: A method of driving a liquid crystal device of the type comprising a pair of oppositely disposed electrode plates (53',53) having thereon a group of scanning lines (51') and a group of data lines (51), respectively, and a layer of ferroelectric liquid crystal (55) disposed between the pair of electrode plates, a pixel being provided at each intersection of the scanning lines and data lines; said driving method comprising: applying prescribed scanning signals to selected scanning lines and applying prescribed data signals to the data lines in synchronism with each scanning signal, whereby (a) a first voltage signal is applied across a first pixel at the intersection of one of the data lines and a selected scanning line, the first voltage signal including in the following order a clear pulse, a writing pulse of a polarity opposite to that of the clear pulse and a correction pulse of a polarity opposite to that of the writing pulse, and (b) following the completion of the application of said first voltage signal as aforesaid, a second voltage signal is applied across an associated second pixel at the intersection of said one of the data lines and the next sequentially selected scanning line, the second voltage signal including in the following order a clear pulse, a writing pulse and a correction pulse of which polarities are respectively opposite to corresponding pulses of the first voltage signal, wherein (c) the correction pulse applied across said first pixel is determined based on gradation data for said pixel on the next sequentially selected scanning line, and the writing pulse applied across said first pixel on the selected scanning line is determined based on gradation data for said first pixel and the above-determined correction pulse. A method according to claim 1 wherein said scanning signals are applied to said scanning lines in an interlaced manner whereby said selected scanning line and said next sequentially selected scanning line are not physically adjacent to each other but are separated by at least one later selected scanning line. A method according to claim 1 wherein said scanning signals are applied to said scanning lines in a line sequential manner whereby said selected scanning line and said next sequentially selected scanning line are physically adjacent. A liquid crystal apparatus for performing the method of any one of the preceding claims, said apparatus comprising: a liquid crystal device (32) of the type comprising a pair of oppositely disposed electrode plates having thereon a group of scanning lines (51') and a group of data lines (51), respectively, and a layer of ferroelectric liquid crystal (55) disposed between the pair of electrode plates, a pixel being provided at each intersection of the scanning lines and data lines; scanning signal supply means (23, 29-31) for applying prescribed scanning signals (S 1 -S 4 ,...) to selected scanning lines (51'); and data signal supply means (21-28) for applying prescribed data signals (I) to said data lines (51) in synchronism with said prescribed scanning signals; wherein, said scanning signal supply means (23,29-31) is adapted to apply prescribed scanning signals (S 1 -S 4 ,...) each having first, second, and third adjoining pulses (V S0 ,V S1 ,V S2 ) alternating in polarity with respect to each other, and the first, second and third pulses of each prescribed scanning signal (S 1 ,S 2 ,S 3 ) being alternate in polarity to the first, second and third pulses of the next sequential scanning signal (S 2 ,S 3 ,S 4 ,.); said data signal supply means (21-28) is adapted to apply prescribed data signals (I) having first and second pulses (V j1 ,-V j2 ) which are in synchronism with said second and third pulses (V S1 ,V S2 ) of said prescribed scanning signals (S 1 -S 4 ,..) to form, as respective resultant voltage signal, (I-S 1 ,I-S 2 ,...) across a selected pixel, and an associated pixel on the same data line intersected by the next sequentially selected scanning line, a respective first voltage signal (I-S 1 ) including a first clear pulse (V 0 ), a first correcting pulse (-V 1 ) of a polarity opposite to that of said first clear pulse, and a first correction pulse (V 2 ) of a polarity opposite to that of said first writing pulse, and a respective second voltage signal (I-S 2 ) including a second clear pulse (-V 0 ), a second writing pulse (V 1 ) and a second correction pulse (V 2 ) of which polarities are opposite to the corresponding first clear pulse, first writing pulse and first correction pulse of said first voltage signal, said second voltage signal commencing with said second clear pulse following completion of the first correction pulse of said first voltage signal; and said data signal supply means (21-28) includes data signal generator means (24,25), operable to set the voltage (V j2 ) of said second pulse of the data signal (I) for said selected pixel, based on gradation data for said associated pixel to set the voltage of the first correction pulse for said selected pixel, and to set the voltage (V j1 ) of said first pulse of the data signal (I) for said selected pixel based on the gradation data for said selected pixel and based on said first correction pulse. Apparatus according to claim 4 wherein said liquid crystal device (32) includes a film layer (54',54) interposed between one or both of said group of scanning lines (51') and said group of data lines (51) and said layer of ferroelectric liquid crystal, said film layer (54',54) having a volume resistivity of at least 10 8 ohm.cm. Apparatus according to claim 5 wherein said film layer (54',54) has a laminate structure comprising at least two layers including an organic layer disposed adjacent to said layer of ferroelectric liquid crystal for alignment control of the liquid crystal molecules, and an inorganic layer disposed adjacent to said group of scanning lines on said group of data lines.

Inventors: INABA YUTAKA, KANEKO SHUZO, KATAKURA KAZUNORI, MIYATA HIROKATSU, OKADA SHINJIRO, SHINJO KATSUHIKO, INABA, YUTAKA, KANEKO, SHUZO, KATAKURA, KAZUNORI, MIYATA, HIROKATSU, OKADA, SHINJIRO, SHINJO, KATSUHIKO, INABA, YUTAKA, C/O CANON KABUSHIKI KAISH, KANEKO, SHUZO, C/O CANON KABUSHIKI KAISH, KATAKURA, KAZUNORI, C/O CANON KABUSHIKI KAISH, MIYATA, HIROKATSU, C/O CANON KABUSHIKI KAISH, OKADA, SHINJIRO, C/O CANON KABUSHIKI KAISH, SHINJO, KATSUHIKO, C/O CANON KABUSHIKI KAISH
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: G09G3
IPC codes: G09G3