Error correction method including erasure correction, and apparatus therefore

Abstract: A multiplier calculates a product S'(x) = S(x)·λ(x) mod X d-1 of a syndrome polynomial S(x) generated by a syndrome generator and an erasure position polynomial λ(x) generated by an erasure position polynomial generator, modulo X d-1 . A constant multiplier sequentially multiplies coefficients of the polynomial S'(x) and the erasure position polynomial λ(x) with a power of a primitive root α of a code. The power exponents in this multiplication are determined in units of coefficients. Every time this multiplication is executed, an adder sequentially adds predetermined combinations of products. A plurality of arithmetic and logic operations according to the numbers of correctable erasures and errors are sequentially executed using the sums. A divisor and dividend are selected in accordance with the number of erasures included in the code on the basis of the plurality of arithmetic and logic operation results. A division is executed using the selected divisor and dividend. A value at a position, discriminated to be an error position, of the code is corrected based on the division result, thus performing error correction including erasure correction with a simple circuit arrangement.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an error correction method for detecting and correcting data errors of data storage media such as optical disks, magnetooptical disks, and the like, data communication paths in satellite communications, and the like using error correction codes and, more particularly, to an error correction method using codes defined on a finite field such as Reed Solomon codes (to be referred to as RS codes hereinafter) and an apparatus therefor. Related Background Art In recent years, in order to improve reliability of various digital systems such as a memory system using a storage medium (e.g., an optical disk), an error correction method using error correction codes is popularly utilized. In particular, as such error correction codes, RS codes are widely used in optical disks, magnetooptical disks, satellite communications, and the like since they have an important feature for practical applications, i.e., they achieve the lowest redundancy among codes having the same code length and correction performance. However, in a conventional method for processing encoding/decoding of RS codes at high speed, when erasure correction is not considered, and correction performance is as small as about 1 to 2, an apparatus can be relatively easily realized. However, when erasure is taken into consideration, processing is considerably complicated as compared to processing including no erasure correction even when the error correction performance is small. US Patent 5,170,399 describes a method and apparatus for correction of errors and erasures using a Reed-Solomon decoder. The decoder uses a Euclid stack configured to function as a Euclid divide or a Euclid multiply module. In that way, the provision of separate Euclid divide and multiply stacks can be avoided. Therefore, when the decoder disclosed in the US patent is implemented by means of an integrated circuit, it can be produced on a smaller area than if it comprised separate Euclid divide and Euclid multiply stacks. In that way, the implementation of the decoder can be made using a die with reduced size, and so manufacturing yield from a particular wafer of semiconducting material can be increased. SUMMARY OF THE INVENTION It is, therefore, an objective of the present invention to provide a decoding method for performing error correction including erasure correction using a simple circuit arrangement, and an apparatus therefor. It is another objective of the present invention to provide a decoding method for performing erasure correction at high speed by simple processing, and an apparatus therefor. According to one aspect, the present invention which achieves these objectives relates to an error correction method comprising the steps of: generating a syndrome polynomial for a code to be corrected; generating an erasure position polynomial for the code to be corrected; calculating partial polynomials corresponding to portions, which have degrees smaller by at least 2 than a designed distance of the code, of a product of the generated syndrome polynomial and the generated erasure position polynomial; executing a multiplication for sequentially multiplying coefficients of the partial polynomials and the erasure position polynomials with a power of a primitive element of the code, power exponents being determined in units of coefficients; sequentially calculating sums of predetermined combinations of products every time the multiplication is executed; selecting a divisor and a dividend in accordance with the number of erasures included in the code on the basis of results of a plurality of predetermined arithmetic and logic operations which are sequentially executed using the sums; executing a division using the selected divisor and dividend; discriminating, based on the results of the predetermined arithmetic and logic operations which are sequentially executed using the sums, whether or not each of positions of the code is an error position; and correcting values of the code at the positions determined to be the error positions and at erasure positions on the basis of the result of the division. According to another aspect, the present invention which achieves these objectives relates to an error correction apparatus comprising: first generation means for generating a syndrome polynomial for a code to be corrected; second generation means for generating an erasure position polynomial for the code to be corrected, in use; first arithmetic operation means for calculating partial polynomials corresponding to portions, which have degrees smaller by at least 2 than a desired distance of the code to he corrected, in use, of a product of the syndrome polynomial and the erasure position polynomial respectively generated by the first and second generation means; multiplication means for sequentially multiplying coefficients of the partial polynomials and the erasure position polynomials with a power of a primitive element of the code to be corrected, in use, power exponents being determined in units of coefficients; addition means for sequentially calculating sums of predetermined combinations of products every time the multiplication means executes the multiplication; second arithmetic operation means for sequentially executing a plurality of predetermined arithmetic and logic operations using the sums; selection means for selecting a divisor and a dividend in accordance with the number of erasures included in the code on the basis of a plurality of arithmetic operation results from the second arithmetic operation means; division means for executing a division using the divisor and dividend selected by the selection means; discrimination means for discriminating, based on the arithmetic operation results from the second arithmetic operation means, whether or not each of positions of the code is an error position; and correction means for correcting values of the code to be corrected, in use, at the positions determined to be the error positions and at erasure positions on the basis of the division result from the division means. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the processing sequence of an error correction apparatus according to a specific embodiment of the present invention; Fig. 2 is a block diagram showing the arrangement of an error correction apparatus of the specific embodiment; Fig. 3 is a block diagram showing the detailed arrangement of a circuit for calculating the position and magnitude of an error in the specific embodiment; and Fig. 4 is a block diagram showing the arrangement of an alternative error correction apparatus illustrated by way of example but not forming part of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings. (Specific Embodiment) For the sake of simplicity, a case of RS codes with a designed distance = "5" will be explained below. In RS codes, since a minimum distance d is equal to the designed distance, d = 5. In general, if the number of errors is represented by t, and the number of erasures is represented by s, d ≥ 2t + s + 1 is satisfied. For this reason, when d = 5, a total of the numbers of correctable errors and erasures is at most 4, and correctable combinations are as follows. That is, when the number of erasures is 3 to 4, the number of errors is 0; when the number of erasures is 1 to 2, the number of errors is 1; and when the number of erasures is 0, the number of errors is 4. Thus, in the following description, the code length of RS codes is represented by n, and of 0th to (n-1)th positions in a code unit, the positions of errors or erasures are represented by h, i, j, and k. In correction, assume that the position of an erasure is obtained but its magnitude is unknown, and neither of the position and magnitude of an error are known. Also, the primitive root of the nth power of 1 is represented by α. A decoding sequence of a received word as the principle of the present invention will be described below with reference to the flow chart in Fig. 1. In step S1, if a received word polynomial is represented by W(x), the following syndrome polynomial is generated based on S m = W(α m ) : S(x) = S 3 ·x 3 + S 2 ·x 2 + S 1 ·x + S 0 More specifically, we have: S 0 = e h + e i + e j + e k S 1 = α h ·e h + α i ·e i + α j ·e j + α k ·e k S 2 = α 2h ·e h + α 2i ·e i + α 2j ·e j + α 2k ·e k S 3 = α 3h ·e h + α 3i ·e i + α 3j ·e j + a 3k ·e k Then, in step S2, an erasure position polynomial λ(x) = λ 3 ·x 3 + λ 2 ·x 2 + λ 1 ·x + λ 0 is generated. More specifically, we have: λ 4 = α h+i+j+k λ 3 = α h+i+j + α h+i+k + α h+j+k + α i+j+k λ 2 = α h+i + α h+j + α h+k + α i+k + α j+k λ 1 = α h + α i + α j + α k λ 0 = 1 In step S3, a product of the syndrome polynomial S(x) and the erasure position polynomial λ(x), modulo X d-1 , is calculated as follows: S'(x) = S(x)·λ(x) mod X d-1 = S' 3 ·x 3 + S' 2 ·x 2 + S' 1 ·x + S' 0 More specifically, we have: S' 3 = S 3 λ 0 + S 2 λ 1 + S 1 λ 2 + S 0 λ 3 S' 2 = S 2 λ 0 + S 1 λ 1 + S 0 λ 2 S' 1 = S 1 λ 0 + S 0 λ 1 S' 0 = S 0 λ 0 Furthermore, in step S4, the coefficients, S'(x) and λ(x), are multiplied with α -1 , α -2 , or α -3 a times (0 ≤ a ≤ n-1) as follows: S x3 = S' 3 ·(α -3 ) a S x2 = S' 2 ·(α -2 ) a S x1 = S' 1 ·(α -1 ) a λ x3 = λ 3 ·(α -3 ) a λ x2 = λ 2 ·(α -2 ) a λ x1 = λ 1 ·(α -1 ) a In step S5, sums of the calculation results in step S4 for each a are calculated: A x2 = S x3 + S x2 A x1 = S x2 + S x1 A x0 = S x1 + S 0 B x2 = λ x3 + λ x1 B x1 = λ x2 + λ x1 Using the above results, in step S6, the position and magnitude of an error are calculated by the following calculations: When the number of erasures is 0, double error position: position of a satisfying L2 = A x0 ·A x2 + A x1 2 = 0 single error position: position of a satisfying L1 = A x2 = 0 magnitude of error: EI = S 0 + A x0 2 /(A x0 + A x1 ) When the number of errors is 1 to 2, error position: position of a satisfying L1 = A x2 = 0 magnitude of error: EI = S x2 /(B x1 + 1) magnitude of erasure: EJ = (A x2 ·A x0 + S x2 2 )/(A x2 ·λ x1 ) When the number of errors is 3 to 4, magnitude of erasure: EJ = (A x2 + A x0 )/B x2 Finally, in step S7, a correction operation is performed at the positions, which are determined to be error positions, on the basis of the error magnitudes. Equations shown in step S6 will be proved below. When the number of erasures is 3 to 4, the number of errors is 0, as described above, and all h, i, j, and k are erasures. At this time, since we have: then, when, for example, a = h , we can prove: (A x2 + A x0 )/B x2 = (S x3 + S x2 + S x1 + S 0 )/(λ x3 + λ x1 ) = (α i+j+k-3h + α i+j-2h + α i+k-2h + α j+k-2h + α i-h + α j-h + α k-h + 1)·e h /{(α h+i+j + α h+i+k + α h+j+k + α i+j+k )·α -3h + (α h + α i + α j + α k )·α -h } = e h The same applies to a = i, j, and k . A case will be examined below wherein the number of erasures is 1 to 2. At this time, the number of errors is 1, as described above. Thus, j and k are assumed to be the erasure positions, and i is assumed to be the error position. At this time, since we have: then, A x2 = S x3 + S x2 = (α 2i + α i+j + α i+k + α j+k )·e 1 ·(α -3 ) a ·(α i + α a ) Therefore, only when a = i , A x2 = 0. For this reason, by checking the value of A x2 , the error position can be detected. When a = i, S x2 /(B x1 + 1) = e i , and this calculation yields the magnitude of the error. Furthermore, when a = j, (A x2 ·A x0 + S x2 2 )/(A x2 ·λ x1 ) = e j , and similarly, when a = k , this results in e k , thus obtaining erasure values. Finally, when the number or erasures is 0, a correction technique for this case is known to those who are skilled in the art, and a detailed description thereof will be omitted. According to the present invention, when the number of erasures is 0, a conventional method is used, and when the number of erasures is 1 or more, the method of the present invention is used. Therefore, processing can be performed by a simple arrangement independently of the presence/absence of erasures. Fig. 2 shows the circuit arrangement based on the above-mentioned decoding sequence. Referring to Fig. 2, a syndrome generator 1 generates a syndrome polynomial S(x) from a received word in step S1. An erasure position polynomial generator 2 generates an erasure position polynomial λ(x) in step S2 on the basis of a given erasure position. A multiplier 3 performs multiplication in step S3 for calculating the product S'(x) = S(x)·λ(x) mod X d-1 of the syndrome polynomial S(x) and the erasure position polynomial λ(x), modulo X d-1 . A constant multiplier 4 executes processing in step S4 for multiplying a constant α -i with the respective coefficients in the polynomial. An adder 5 adds the coefficients in the polynomial in step S5. An arithmetic and logic operation unit 6 executes an arithmetic operation in step S6 for calculating the position and magnitude of an error and the magnitude of an erasure. In the correction operation, L1 or L2 = 0 for each position of codes sequentially output via a buffer 9 is detected by a zero detector 7 to discriminate an error position. When 0 is detected, EI is passed by an AND gate 8, and an adder 10 corrects the error. At the erasure position known in advance, the adder 10 corrects the erasure using EJ. Fig. 3 is a circuit diagram showing the detailed arrangement of the arithmetic and logic operation circuit 6. Each of adders 11a to 11f adds two inputs, and outputs a sum. Each of multipliers 12a and 12b outputs a product of two inputs. Each of square circuits 13a to 13c outputs a square of an input. Each of selectors 14a and 14b selects one output from four inputs in accordance with the number and positions of erasures. A divider 15 executes division using the output from the selector 14a as a divisor and the output from the selector 14b as a dividend, and outputs the magnitude EI of an error or the magnitude EJ of an erasure. More specifically, when the number of erasures is 3 to 4, the selector 14a selects B x2 , and the selector 14b selects the output from the adder 11d. When the number of erasures is 1 to 2, at the positions of erasures, the selector 14a selects the output from the adder 11b and the selector 14b selects the output from the adder 11e, and at other positions, the selector 14a selects the output from the adder 11b and the selector 14b selects S x2 . When the number of erasures is 0, the selector 14a selects the output from the adder 11c, and the selector 14b selects the output from the square circuit 13c. The divider 15 obtains the reciprocal number of a divisor by reciprocal number conversion based on a table such as a ROM, and calculates a product of the obtained reciprocal number and a dividend. When the number of erasures is 0, EI is obtained by further adding S 0 to the output from the divider 15. In Fig. 3, inputs of the same values and same arithmetic operations are separately illustrated. However, on an actual circuit, these components may be connected to be able to commonly use the same values. As described above, according to this embodiment, an error including an erasure can be corrected by a simple circuit arrangement. (Alternative Arrangement) As an alternative arrangement to the present invention, a circuit for correcting a single error irrespective of generation of an erasure will be described below. For the sake of simplicity, as in the specific embodiment, a case of RS codes with a minimum distance d = 5 will be explained. A case will be examined below wherein the number of erasures is 1 to 2. At this time, the number of correctable errors is 1, as described above. Thus, j and k are assumed to be the erasure positions and i is assumed to be the error position. At this time, the syndrome polynomial S(x) is given by: S(x) = S 3 ·x 3 + S 2 ·x 2 + S 1 ·x + S 0 S 0 = e i + e j + e k S 1 = α i ·e i + α j ·e j + α k ·e k S 2 = α 2i ·e i + α 2j ·e j + α 2k ·e k S 3 = α 3i ·e i + α 3j ·e j + α 3k ·e k On the other hand, the erasure position polynomial λ(x) is given by: λ(x) = λ 2 ·x 2 + λ 1 ·x + λ 0 = α j+k ·x 2 + (α j + α k )·x + 1 Therefore, when a product S'(x) = 2(x)·λ(x) mod X d-1 = S' 3 ·x 3 + S' 2 ·x 2 + S' 1 ·x + 2' 0 of the syndrome polynomial S(x) and the erasure position polynomial λ(x), modulo X d-1 , is calculated, we have: S' 3 = S 3 λ 0 + S 2 λ 1 + S 1 λ 2 + S 0 λ 3 S' 2 = S 2 λ 0 + S 1 λ 1 + S 0 λ 2 S' 1 = S 1 λ 0 + S 0 λ 1 S' 0 = S 0 λ 0 In particular, S' 3 = e i ·α 3i ·λ(α -i ) S' 2 = e i ·α 2i ·λ(α -i ) Therefore, the position i and magnitude e i of an error can be respectively calculated by: α -i = S' 2 /S' 3 e i = S' 3 /(λ(α -i )·α 3i ) When α -i is expressed by x, (λ(x)·x -3 ) in an equation for calculating e i corresponds to a pattern obtained by altering the degree of the erasure position polynomial. When e i is expressed as e i = S' 3 α -3i /λ(α -i ) , e i corresponds to a pattern obtained by multiplying S' 3 with a constant α -3i and dividing the product with the erasure position polynomial λ(α -i ). Therefore, arithmetic operations required for the above-mentioned method can be realized by an apparatus shown in Fig. 4. Referring to Fig. 4, a syndrome generator 1 generates a syndrome polynomial S(x) from a received word. An erasure position polynomial generator 2 generates an erasure position polynomial λ(x) on the basis of a given erasure position. A multiplier 3 calculates a product S'(x) = S(x)·λ(x) mod X d-1 of the syndrome polynomial S(x) and the erasure position polynomial λ(x), modulo X d-1 . The above-mentioned circuits are the same as those in the specific embodiment. Also, each of dividers 16a and 16b obtains the reciprocal number of a divisor by reciprocal number conversion based on a table such as a ROM, and calculates a product of the obtained reciprocal number and a dividend. A polynomial evaluation circuit 17 obtains a new polynomial λ(x)·x -3 by altering the degree of the erasure position polynomial λ(x) generated by the erasure position polynomial generator 2, and then calculates a value obtained by substituting α -i in the new polynomial. As can be understood from the fact that a polynomial A(x) can be expressed by: A(x) = a n ·x n + a n-1 ·x n-1 + ··· + a 1 ·x + a 0 = ((··· (a n ·x + a n-1 )·x + a n-2 )···)·x + a 0 such a polynomial evaluation circuit can be realized by repeating a multiplication/addition in the form of A·X+B . This multiplication/addition is realized by a repetitive arithmetic operation using a single circuit or parallel processing using a plurality of circuits. A position detector 18 opens an AND gate 8 at an error position i on the basis of α -i output from the divider 16, and an adder 10 corrects a code output from a buffer 9 as in the specific embodiment of the invention. As described above, according to this arrangement, a single error can be corrected by a simple circuit arrangement independently of generation of erasures.

Claims: An error correction method comprising the steps of: generating (S1) a syndrome polynomial for a code to be corrected; generating (S2) an erasure position polynomial for the code to be corrected; and calculating (S3) partial polynomials corresponding to portions, which have degrees smaller by at least 2 than a designed distance of the code, of a product of the generated syndrome polynomial and the generated erasure position polynomial; characterised by the steps of: executing (S4) a multiplication comprising sequentially multiplying coefficients of the partial polynomials and the erasure position polynomials with a power of a primitive element of the code, the power in each case corresponding with an ordinal of the coefficient; sequentially calculating (S5) sums of predetermined combinations of products every time the multiplication is executed; selecting a divisor and a dividend in accordance with the number of erasures included in the code on the basis of results of a plurality of predetermined arithmetic and logic operations which are sequentially executed using the sums; executing a division using the selected divisor and dividend; discriminating (S6), based on the results of the predetermined arithmetic and logic operations which are sequentially executed using the sums, whether or not each of positions of the code is an error position; and correcting (S7) values of the code at the positions determined to be the error positions and at erasure positions on the basis of the result of the division. A method according to claim 1, wherein, in the plurality of arithmetic and logic operations, different arithmetic operations are executed in parallel at each of the positions of the code in accordance with the numbers of correctable erasures and errors. A method according to claim 1, wherein the discrimination and correction steps (S6, S7) are sequentially executed in correspondence with the positions of the code. An error correction apparatus comprising: first generation means (1) for generating a syndrome polynomial for a code to be corrected; second generation means (2) for generating an erasure position polynomial for the code to be corrected, in use; and first arithmetic operation means (3) for calculating partial polynomials corresponding to portions, which have degrees smaller by at least 2 than a designed distance of the code to be corrected, in use, of a product of the syndrome polynomial and the erasure position polynomial respectively generated by said first and second generation means (1, 2); characterised by: multiplication means (4a, 4b) for sequentially multiplying coefficients of the partial polynomials and the erasure position polynomials with a power of a primitive element of the code to be corrected, in use, power exponents being determined in units of coefficients; addition means (5a, 5b) for sequentially calculating sums of predetermined combinations of products every time said multiplication means executes the multiplication; second arithmetic operation means (6) for sequentially executing a plurality of predetermined arithmetic and logic operations using the sums; selection means (14a, 14b) for selecting a divisor and a dividend in accordance with the number of erasures included in the code to be corrected, in use, on the basis of a plurality of arithmetic operation results from said second arithmetic operation means; division means (15) for executing a division using the divisor and dividend selected by said selection means; discrimination means (7, 8) for discriminating, based on the arithmetic operation results from said second arithmetic operation means, whether or not each of positions of the code to be corrected, in use, is an error position; and correction means (10) for correcting values of the code to be corrected, in use, at the positions determined to be the error positions and at erasure positions on the basis of the division result from said division means (15). An apparatus according to claim 4, wherein said second arithmetic operation means (6) parallelly executes different arithmetic operations at each of the positions of the code to be corrected, in use, in accordance with the numbers of correctable erasures and errors as the plurality of arithmetic and logic operations. An apparatus according to claim 4 or claim 5, wherein the discrimination means (7, 8) and the correction means (10) are operable so as to perform respective discrimination and correction sequentially in accordance with said positions of the code to be corrected, in use.

Inventors: AIZAWA TAKAYUKI, IWAMURA KEIICHI, NARITA IZUMI, SUZUKI TAKATOSHI, AIZAWA, TAKAYUKI, IWAMURA, KEIICHI, NARITA, IZUMI, SUZUKI, TAKATOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: H03M13
IPC codes: H03M13, G06F11