Memory array cell reading device

Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

Description: The present invention relates to a memory array cell reading device. As is known, all currently marketed types of memory read the array cells by comparing the content of the cells with the known content of a selected reference cell and using a structure of the type in Figure 1, which shows a memory cell 1, whose content is to be read, connected (together with other cells not shown) to a bit line 2. Bit line 2 is connected to a selection circuit 4 in turn connected to an array branch 3 forming part of the reading device and comprising a current/voltage converter 5. Selection circuit 4 comprises pass transistors, and receives a decoding signal DEC for read-enabling, or not, bit line 2 by connecting/disconnecting it to/from converter 5. Converter 5 comprises a precharge circuit 6 and a load 7 connected in series between selection circuit 4 and a supply line V CC . Node 8 between precharge circuit 6 and load 7 constitutes the output of array branch 3 and is connected to one input of a single- or two-stage sense amplifier 10 having another input connected to the output 11 of a reference branch 12 with the same structure as array branch 3. More specifically, reference branch 12 comprises a current/voltage converter 14. Converter 14 comprises a load 15 and a precharge circuit 16; the load 15 is connected between supply line V CC and precharge circuit 16; and precharge circuit 16 is connected to a reference cell 17 (whose content is known) via a selection simulating circuit 18 also comprising a pass transistor, the gate terminal of which is so biased as to maintain an active connection between reference cell 17 and converter 14. In known manner, the memory array comprises n array reading branches 3 (one for each output of the reading device plus a redundancy branch) and one reference branch 12. In the Figure 1 arrangement, converters 5, 14 detect the currents through read cell 1 and reference cell 17 respectively, and convert them into a voltage. More specifically, the current along bit line 2, and hence through load 7, depends on the state (programmed or erased) of cell 1, whereas the current in reference branch 12 is known; and the two voltages at outputs 8, 11 are then compared in amplifier 10. For the array cells to be read correctly, the reference branch must be as similar as possible to the array branch, with the exception of the load. The reference branch load in fact is normally formed by two or more identical current paths to the supply, so that, if the read cell is erased, the reference current (through reference cell 17) equals or is twice or a multiple of the current through the array branch. According to one known solution, the load of all the array branches is formed by a diode-connected MOS transistor, and the reference branch comprises two MOS transistors of the same type as the array branch transistors, also diode-connected, and connected parallel between node 11 and supply line V CC . Also, as some situations require that one of the current paths of the reference branch be turned off, so that the reference current equals the current through an erased array cell, the switchable current path presents a controlled switch in the form of a MOS transistor connected in series with the respective load transistor. To achieve a correct relationship between the reference and array branch currents, the current paths must be the same, so similar transistors (simulating controlled switches and of the same size and characteristics) must be provided along the other current path of the reference branch and along each array branch, which additional transistors are so biased as to be permanently on. As the additional transistors must be large to operate effectively as switches, and must be provided in all the array branches, the above solution is extremely cumbersome. EP-A-0 576 045 discloses a memory device according to the preamble of claim 1. In this known memory device, the load of the reference branch is formed by two parallel connected transistors designed so that the sum of their conduction resistance is equal to the resistance of conventional reference loads. One of the two reference load transistors has a control terminal connected to an ATD pulse generator and is switched off during row switching for reducing rise of the reference potential in this step. It is an object of the present invention to provide a memory reading device which is compact, while at the same time providing for equal current paths, and the possibility of switching one or more of the paths. According to the present invention, there is provided a memory array cell reading device as claimed in Claim 1. In practice, according to the present invention, one current path of the reference branch is formed by a single diode-connected load transistor, and the other current path by a single load transistor switchable by a switching network driven by at least one external signal and located between the gate and drain terminals of the transistor, so that the switchable load transistor is turned off when the second current path is to be disabled, and is diode-connected when the second current path is desired. A preferred non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a known type of reading device; Figure 2 shows a simplified electric diagram of one embodiment of the device according to the present invention. In Figure 2, the reading device is indicated by 20 and, like the known device in Figure 1, comprises a number of array reading branches 21 (only one shown) and a reference branch 22. The array reading branch 21 shown comprises a precharge and selection circuit 24 (incorporating circuits 4, 5 in Figure 1) connected to a bit line 2 to which the cell 1 to be read is also connected. Like circuit 4, precharge and selection circuit 24 presents an input 25 supplied with a decoding signal DEC, and is connected to a V CC supply line 26 via a load 27 formed by a P-channel MOS transistor. Similarly, reference branch 22 presents a precharge and selection circuit 30 connected to reference cell 17 and to a reference line 31. Between reference line 31 and supply line 26, there are provided two current paths 32a, 33a formed by respective loads 32, 33 in the form of P-channel transistors of the same size and fabrication specifications as transistor 27. More specifically, transistor 32 presents the gate terminal short-circuited to the drain terminal and connected to the gate terminal of load transistor 27 of array branch 21 and to reference line 31; and transistor 33 presents the gate terminal (defining node 34) connected to reference line 31 via a first N-channel selection transistor 35. The gate terminal of first selection transistor 35 is connected to the output of an inverter 45, the input of which constitutes an input node 46 of circuit 20 supplying a logic signal R1 switchable only between supply line potential and zero. Input node 46 is also connected to the gate terminal of a second, P-channel, selection transistor 47 with its source terminal connected to node 34, and its drain terminal connected to reference line 31. A third, P-channel, selection transistor 48 is interposed between supply line 26 and node 34, the gate terminal of which defines an input node 50 supplying a second logic selection signal R2. Like the Figure 1 device, node 51 (defined by the drain terminal of load transistor 27 of array branch 21) and reference line 31 are connected to respective inputs of a sense amplifier 52, the output 53 of which defines the output of circuit 20. Selection transistors 35, 47, 48 present a high W/L ratio so that they are highly conductive. Circuit 20 in Figure 2 operates as follows. When both selection signals R1, R2 are low, transistors 48, 47 are turned on and bring reference line 31 to supply voltage V CC . Conversely, load transistor 33 and selection transistor 35 are off due to the insufficient voltage drop between the source and gate terminals (selection transistor 35 presents the supply voltage at both the gate terminal connected to the output of inverter 45, and the source terminal connected to reference line 31; and load transistor 33 presents the supply voltage at both the source terminal connected to line 26, and the gate terminal). The above operating condition is desired to bring device 20 rapidly to the operating condition prior to reading the cell. When selection signal R1 is high and R2 low, selection transistors 35, 47 are off and selection transistor 48 on; selection transistor 48 connects node 34 to supply line 26 so that load transistor 33, whose gate and source terminals are short-circuited, is off. As such, only current path 32a is enabled, and reading is performed with the same current in the reference and array branches. In fact, the connection between the gate terminals of load transistor 27 of array branch 21 and load transistor 32 of reference branch 22 ensures both branches operate under the same conditions. When selection signal R1 is low and R2 high, selection transistor 48 is off and selection transistor 35 or 47 is turned on depending on the voltage of reference line 31. More specifically, prior to reading the cell, the reference line is at supply voltage V CC , so that selection transistor 35 is turned off by presenting the same potential at the source and gate terminals. Conversely, transistor 47 is turned on and bypasses the gate terminal of load transistor 33 to reference line 31. Transistor 33 is thus in the same operating condition as load transistors 27, 32, and its current is added to that of transistor 32 (both current paths 32a, 33a are enabled) to supply reference cell 17 with a current 2I, where I is the current supplied singly by transistors 27, 32, 33. During reading, the potential of reference line 31 falls, in known manner, due to the reference cell being conductive; and, as the potential falls, upon the voltage drop between the source and gate terminals of selection transistor 35 reaching the threshold value, transistor 35 is turned on and connection between the gate terminal of load transistor 33 and reference line 31 is assured by both transistors 35, 47. As the potential of reference line 31 (and hence at node 34) falls, upon the voltage drop between the source and gate terminals of transistor 47 falling below the threshold value, transistor 47 is turned off and the diode connection of load transistor 33 is assured solely by selection transistor 35. Throughout the cell reading phase, therefore, the reference branch provides for supplying twice the current of a conductive array cell. A configuration wherein both selection signals R1, R2 are high is not permitted. The advantages of the device described are as follows. In particular, as compared with the known solution comprising two transistors (one load transistor and an additional switching transistor) connected in series for each current path, the device according to the present invention is more compact by eliminating one transistor per array branch. Moreover, the solution described is both simple and reliable. Clearly, changes may be made to the device as described and illustrated herein without, however, departing from the scope of the present invention.

Claims: A memory array cell reading device (20) comprising at least one array branch (21) and a reference branch (22) connected to a sense ampflifier (52); said array branch comprising an array load element (27) interposed between a reference potential line (26) and an array output node (51) and defining an array current path; and said reference branch (22) comprising at least a first reference load element (32) and a second reference load element (33) interposed, parallel to each other, between said reference potential line (26) and a reference output node (31) and defining a first and second reference current path (32a, 33a); at least said second reference current path (33a) comprising switching means (35-50); said load elements each being a transistor element (27, 32, 33) with a control terminal; and said control terminal of said transistor element (33) of said second reference current path (33a) defining a turn-on terminal (34) connected to said switching means (35-50) for enabling and disabling said transistor element (33) of said second current path, characterized in that said switching means (35-50) comprise at least a first controlled switch (47) interposed between a common line (31) and said turn-on terminal (34); said control terminals of said transistor elements (27, 32) of said array current path (21) and said first reference current path (32a) being connected to said common line (31). A device as claimed in Claim 1, characterized in that said switching means (35-50) comprise at least a second controlled switch (48) interposed between said turn-on terminal (34) and a bias line (26) at a potential for turning off said transistor element (33) of said second reference current path (33a). A device as claimed in Claim 2, characterized in that said switching means (35-50) comprise a third controlled switch (35) interposed between said turn-on terminal (34) and said reference output node (31). A device as claimed in Claim 3, characterized in that said controlled switches (35, 47, 48) comprise transistors, each having a control terminal supplied with a respective switching signal. A device as claimed in claim 3 or 4, characterized in that said load transistor elements (27, 32, 33) comprise P-channel MOS transistors; said common line (31) forms said reference output node; and said bias line is formed by said reference potential line (26). A device as claimed in Claim 5, characterized in that said first and second controlled switches (47, 48) comprise a P-channel MOS transistor; and said third controlled switch (35) comprises an N-channel MOS transistor; said first controlled switch (47) being controlled by a first control signal (R1); and said third controlled switch (35) being controlled by a second control signal in phase opposition with respect to said first control signal.

Inventors: GOLLA CARLA MARIA, OLIVO MARCO, PADOAN SILVIA, GOLLA, CARLA MARIA, OLIVO, MARCO, PADOAN, SILVIA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G11C7
IPC codes: G11C11, G11C16, G11C7