Semiconductor integrated circuit device

Abstract: A word line driver according to the present invention has a decoder for outputting decode signals having first and second logic levels, level shifters for receiving the respective decode signals, each level shifter outputting drive signal having first and third logic levels in response to the received decode signal, the third logic level being higher than the second logic level; a pumping circuit for outputting word line activation signals, at least one of the word line activation signals having the third logic level; and groups of output circuits, each group having the output circuits connected to one of the level shifters and a word line, respectively, each of the output circuits outputting the word line activation signal to the respective word line in response to the decode signal and the drive signal.

Description: This invention relates to a semiconductor integrated circuit device such as a Dynamic Random Access Memory (hereinafter called "DRAM"), a Static Random Access Memory (hereinafter called "SRAM"), a Read Only Memory (hereinafter called "ROM") or the like, and particularly to a word line driver employed in the semiconductor integrated circuit device. A semiconductor memory device such as a DRAM has a word line driver for selecting one of memory cells. This type of word line driver has been disclosed in, for example, JP-A-63113888. It is an object of the present invention to provide a word line driver capable of reducing the number of elements as compared with a word line driver employed in a conventional semiconductor memory device and providing a reliable operation. According to the present invention there is provided a word line driver circuit arrangement as defined in appended Claim 1. The second switching means may be switched by a drive signal in dependence on the common decode signal. The drive signal and the decode signal may be of opposite phase. Accordingly, the driver may comprise a plurality of level shifters comprising: a voltage supply at pump voltage, a latch for selecting and outputting the drive signal and a switching circuit for controlling the latch in dependence of the common decode signal. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a circuit diagram of a part of a word line driver showing an embodiment of the present invention; Fig. 2 is a view illustrating a DRAM to which the word line driver shown in Fig. 1, according to the present invention is applied; Fig. 3 is a timing chart for describing the operation of the word line driver shown in Fig. 1; and Fig. 4 is a whole circuit diagram of the word line driver shown in Fig. 1. Fig. 1 is a circuit diagram of a part of a word line driver 6 showing one embodiment of the present invention. The word line driver 6 is employed in a DRAM, for example. A block diagram of the DRAM to which the word line driver 6 a part of which is shown in Fig. 1 is applied, is shown in Fig. 2. The DRAM to which the present invention is applied, will first be described with reference to Fig. 2. The DRAM comprises a timing control circuit 1 for receiving a control signal CT and a clock CK therein and outputting therefrom control signals S 1 for controlling timings provided for respective components, a row address decoder 2 for decoding a row address ADR j so as to output a group of decode signals A having a plurality of decode signals A-1 through A-l therefrom, a column address decoder 3 for decoding a column address ARC so as to output a decode signal for selecting any of bit lines BL 1 through BL n, and a pumping circuit 4 for pumping or boosting a power source voltage VCC (first power source voltage) so as to generate a pumped voltage VP (= VCC + V t + α, where V t : threshold voltage and α : positive voltage value). The word line driver 6 is electrically connected to the pumping circuit 4 through a pumping driver 5. A pumping means comprises the pumping circuit 4 and the pumping driver 5. The pumping driver 5 serves as a circuit for outputting word line activation signals PW 1 through PW m to the word line driver 6 based on a row address ADR i. The word line driver 6 serves as a circuit for selectively driving word lines WL 1-1 through WL l-m based on the group of decode signals A and word line activation signals PW 1 through PW m . A memory cell array 7 is electrically connected to the word line driver 6. The memory cell array 7 is constructed in such a manner that a plurality of memory cells 7a are respectively electrically connected to points where a plurality of word lines WL 1-1 through WL l-m and a plurality of bit lines BL 1 through BL n intersect respectively and the memory cells 7a are arranged in matrix form. A bit line driver 8 is electrically connected to the bit lines BL 1 through BL n . The bit line driver 8 serves as a circuit for selectively driving the bit lines BL 1 through BL n based on the decode signal output from the column address decoder 3. Further, an input buffer 9 is provided in the DRAM. The input buffer 9 serves as a circuit for receiving input data D i therein and outputting the same to a read/write (hereinafter abbreviated as "R/W") controller 10. The R/W controller 10 serves as a circuit for determining, based on the control signal S 1 , whether data is written into or read from a corresponding memory cell 7a. An output buffer 12 is electrically connected to the R/W controller 10 through a sense amplifier 11. The sense amplifier 11 serves as a circuit for amplifying the output of each memory cell 7a. The output buffer 12 serves as a circuit for receiving the output of the sense amplifier 11 and outputting output data D o therefrom. The word line driver 6 provided in the DRAM shown in Fig. 2 will now be described with reference to Fig. 1. The word line driver 6 a part of which is shown in Fig. 1 is comprised of complementary MOS (Complementary Metal Oxide Semiconductor hereinafter called "CMOS") transistors and basically has a plurality of level shifters 40-1 through 40-l (Fig.1 shows only one level shifter 40-1) and a plurality of groups of output units 50-1-1 through 50-l-m (Fig.1 shows only one group of output units 50-1-1 through 50-1-m). The level shifter 40-1 has an inverter 41-1 for inverting the decode signal A-1 and an N-channel MOS (hereinafter called "NMOS") transistor42-1 serving as a pull-down switching means whose gate is controlled based on the decode signal A-1. The gate of an NMOS43-1 is electrically connected to a node N41-1 on the output side of the inverter 41-1 and the source thereof is electrically connected to the ground. Further, the drain of the NMOS transistor 43-1 is electrically connected to a latch circuit for latching a pumped voltage VP therein. The latch circuit comprises P-channel MOS (hereinafter called "PMOS") transistors 44-1 and 45-1. The drain and gate of the PMOS44-1 and the drain and gate of the PMOS45-1 are electrically cross-connected between a node N43-1 and the node N45-1. Further, the sources of the PMOSs 44-1 and 45-1 are connected to the boosted voltage VP. The output unit 50-1-1 comprises a PMOS (first transistor) 51-1-1 and NMOSs (second and third transistors) 52-1-1 and 53-1-1. The source (first electrode), drain (second electrode) and gate of the PMOS51-1-1 are respectively electrically connected to the word line activation signal PW 1 , the word line WL 1-1 and the node N45-1 on the output side of the level shifter 40-1. The NMOS52-1-1 whose gate is controlled based on a potential at the node N45-1, is electrically connected between the drain of the PMOS51-1-1 and the ground. The drain of the NMOS53-1-1 whose gate is controlled based on the decode signal A-1, is electrically connected to the word line activation signal PW 1 . Further, the source of the NMOS53-1-1 is electrically connected to the word line WL 1-1 . Other output units 50-1-2 through 50-1-m respectively connected to the node N45-1 respectively have a circuit configuration identical to that of the output unit 50-1-1. Namely, the output unit 50-1-m comprises a PMOS51-1-m, an NMOS52-1-m and an NMOS53-1-m. The source, drain and gate of the PMOS51-1-m are respectively electrically connected to the word line activation signal PW m , the word line WL 1-m and the node N45-1 on the output side of the level shifter 40-1. The NMOS52-1-m whose gate is controlled based on the potential at the node N45-1, is electrically connected between the drain of the PMOS51-1-m and the ground. The drain of the NMOS53-1-m whose gate is controlled based on the decode signal A-1, is electrically connected to the word line activation signal PW m . Further, the source of the NMOS53-1-m whose gate is controlled based on the first decode signal A-1, is electrically connected to the word line WL 1-m . The operation of the word line driver 6 will now be described below. Fig. 3 is a timing chart for describing the operation of the word line driver 6 shown in Fig. 1. The axis of abscissa indicates the time and the axis of ordinate indicates the voltage. Write and read operations (1) and (2), which are executed where the output circuit 50-1 is activated and the word line WL 1-1 is selected, will be described below with reference to Fig. 3 as an illustrative example. (1) Write operation When the power source voltage VCC is applied, the timing control circuit 1 outputs the control signals S 1 for controlling the timings provided for the respective components, based on the control signal CT and the clock CK. Further, the pumping driver 5 outputs the word line activation signals PW 1 through PWm to the word line driver 6 based on the row address ADR i (each of the word line activation signals is of a signal having a ground level or a VP level and any of the signals PW 1 through PW m is selectively brought to the VP level). On the other hand, the row address decoder 2 decodes the row address ADR j so as to output the group of decode signals A therefrom. Further, the column address decoder 3 decodes the column address ARC so as to output the decode signal for selecting any of the bit lines BL 1 through BL n . On the other hand, the R/W controller 10 is brought into a data write operating state based on the control signal S 1 input from the timing control circuit 1. (a) Set operation When the level of the decode signal A-1 which is one of the group of decode signals A changes from the ground level to the VCC, the NMOSs 42-1 and 53-1-1 through 53-1-m are turned on so that the potential at the node N45-1 is brought to the ground level. As a result, the PMOSs 51-1-1 through 51-1-m are brought into an on state. On the other hand, when the level of the word line activation signal PW 1 changes from the ground level to the VP level, the VP level is supplied to the word line WL 1-1 through the NMOSs 53-1-1 which have been already turned on but is not fully supplied thereto due to the threshold of the NMOS53-1-1. However, the word line activation signal having the VP level is sent to the word line WL 1-1 through the PMOS51-1-1. Thus, a plurality of memory cells electrically connected to the word line WL 1-1 are turned on. Further, one of the bit lines BL 1 through BL n is selected by the bit line driver 8 so that one memory cell 7a is selected. (b) Reset operation When the level of the word line activation signal PW 1 changes from the VP level to the ground level, the word line activation signal having the ground level is sent to the word line WL 1-1 through the NMOS53-1-1 and the PMOS51-1-1 which have already been turned on. When the level of the decode signal A-1 then changes from the VCC level to the ground level, the NMOS42-1 and the NMOS53-1-1 are brought into an off state. Further, the inverter 41-1 changes the level of the node N41-1 from the ground level to the VCC level. Thus, the NMOS43-1 is turned on, so that the level of the node N43-1 is brought to the ground level so as to turn on the PMOS45-1. As a result, the level of the node N45-1 changes from ground level to the VP level. Thus, the PMOS51-1-1 is turned off and the NMOS52-1-1 is turned on in response to the VP level of the node N45-1 so that the resetting of the word line WL 1-1 is completed. (2) Read operation The R/W controller 10 is brought into a data read operating state based on the control signal S 1 . Set and reset operations for selecting a desired word line are performed in a manner similar to the write operation. The output data D o can be read out from the output buffer 12 based on an address selected by the bit line driver 8. The word line driver of the present embodiment shows only one level shifter 40-1 which is selected based on the decode signal A-1. However, the word line driver includes level shifters 40-1 to 40-1 and output circuits 50-1-1 to 50-l-m as shown in Fig. 4. In Fig. 4, the word line activation signal PW 1 is input to output circuits 50-1-1 to 50-l-1. In the same manner, the word line activation signals PW 2 (not shown in Fig. 4) to PW m are input to output circuits 50-1-2 to 50-l-2 (not shown in Fig. 4) to 50-1-m to 50-l-m. In the present embodiment, only one of the word line activation signals PW 1 to PW l has the VP level, while the other word line activation signals have the ground level. The word line driver shown in Fig. 4 has level shifters 40-1 to 40-l each of which receives one of the decode signals A-1 to A-l, respectively. The level shifters 40-1 to 40-l are coupled to the output circuits 50-1-1 to 50-l-1, 50-1-2 to 50-l-2, ....., 50-1-m to 50-l-m, respectively. In the present embodiment, only one of the decode signals A-1 to A-l has the VCC level which is lower than the VP level, while the other decode signals have the ground level. Now, the case will be explained that the word line activation signal PW 1 having the VP level is input to the output circuits 50-1-1 to 50-l-1 and the decode signal A-1 having the VCC level is input to the level shifter 40-1, i.e., the word line WL 1-1 is selected. At this time, a voltage level of the gate of the NMOS53-1-1 of the selected output circuit 50-1-1 is the VCC level and a voltage level of the gate of the PMOS51-1-1 of the selected output circuit 50-1-1 is the ground level since the selected level shifter 40-1 outputs the ground level signal to the node N45-1. Then, both of the NMOS53-1-1 and PMOS51-1-1 are on state. Therefore, the word line activation signal PW 1 having the VP level is supplied to the word line WL 1-1 through the NMOS53-1-1 and PMOS51-1-1. At the same time, for example, a voltage level of the gate of the NMOS53-l-1 of the non-selected output circuit 50-l-1 is the ground level and a voltage level of the gate of the PMOS51-l-1 of the non-selected output circuit 50-l-1 is the VP level since the decode signal A-l has the ground level and the non-selected level shifter 40-l outputs the VP level signal to the node N45-l. Then, both of the NMOS53-l-1 and PMOS51-l-1 are off state. Therefore, the word line activation signal PW 1 having the VP level is not supplied to the word line WL 1-l through the NMOS53-l-1 and PMOS51-l-1. If the word line driver does not have the level shifter 40-l as the prior word line driver does, the PMOS51-l-1 of the non-selected output circuit 50-l-1 receives the VCC level since the inverted decode signal A-l has the VCC level. Then, the PMOS51-l-1 is not completely off state since the VP level signal is applied to the source of the PMOS51-l-1. Therefore, a part of the voltage level of the word line activation signal PW 1 leaks out to the non-selected word line WL I-1 through the PMOS51-l-1. According to the present invention, as has been described the above, the NMOSs 53-1-1 through 53-l-m for receiving the decode signals A-1 through A-l as the gate input corresponding to the input of each level shifter and the PMOSs 51-1-1 through 51-l-m whose each gate is controlled based on the voltage having the VP level, which corresponds to the output of the level shifter, are used as means for transmitting the word line activation signals to their corresponding word lines. Therefore, the word line activation signal can be reliably sent to a desired word line alone. Thus, the read and write operations can be stably performed. Further, since one level shifter serves so as to drive a plurality of output circuits, the number of elements can be reduced. While the present invention has been described with reference to the illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiment will be apparent to those skilled in the art on reference to this description.

Claims: A word line driver circuit arrangement for a plurality of word lines, comprising: a plurality of output circuits (50) for the word lines respectively, each of the output circuits including first and second switching means (53, 51) providing parallel switched charging paths for the respective word line (WL) from a voltage source (PW), wherein the first switching means (53) comprises a transistor of a first conductivity type and the second switching means (51) comprises a transistor of a second conductivity type, and a switched discharge path (52) for discharging the word line, wherein the switched discharge path (52) comprises a transistor of the first conductivity type, characterised in that the output circuits are arranged in groups (1...m), and to select one of the groups, the first switching means (53) of each output circuit thereof is switched by a common decode signal voltage (A) for the group that can change between first and second voltages, and the second switching means (51) of each output circuit of the group is switched by a voltage that can change between a pump voltage greater than the first and second voltages and said first voltage, and respective ones of said voltage sources (PW1...PWm) are provided for the charging paths of the (l) output circuits of the groups (m) to apply a pump voltage greater than the first and second voltages selectively thereto, whereby to select a particular one of the output circuits (50) within the selected group to drive its associated word line. A driver according to any preceding claim wherein the second switching means is switched by a drive signal (N45) in dependence on the common decode signal (A). A driver according to claim 2 wherein the drive signal (N45) and the decode signal (A) are of opposite phase. A driver according to either claim 2 or 3 comprising a plurality of level shifters (40) comprising: a voltage supply at pump voltage (VP), a latch (44, 45) for selecting and outputting the drive signal (N45) and a switching circuit (41, 42, 43) for controlling the latch in dependence of the common decode signal (A). A driver according to any preceding claim wherein the switched discharge path (52) is to ground.

Inventors: SUGIO KENICHIRO, SUGIO, KENICHIRO
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1994
Main classification: G11C8
IPC codes: G11C8, G11C11