Chrominance signal processing circuit

Abstract: Chrominance signals of a digitized composite video signal are processed by including automatic phase control and automatic chroma control operations that use circuit elements that are concurrently available for both operations as well as for other signal processing operations. The automatic phase control operation calculates a phase error corresponding to a phase difference between a reference clock signal and a burst synchronization signal of the chrominance signal. The reference clock signal is generated in response to the phase error data, such that the phase error is minimized and the reference clock signal coincides with the burst synchronization signal. The automatic chroma control operation multiplies the chrominance signal by coefficient data corresponding to the difference between the chrominance signal and a reference value to generate a constant level chrominance signal.

Description: The present invention relates to apparatus and methods for processing chrominance signals of a composite video signal, and, more particularly, to apparatus and methods which incorporate automatic phase control (APC) and automatic chroma control (ACC) operations in processing chrominance signals. A composite video signal includes a modulated color sub-carrier signal (chrominance signal), shown in Fig. 1A, combined with a monochrome signal (luminance signal) and shown in Fig. 1B. The chrominance signal contains information regarding the color portion of an image, and this information is represented by both the amplitude and phase of the chrominance signal. Because color information is stored in the phase of the signal, an operation that processes the chrominance signal must be closely synchronized with the phase of the signal to avoid loss of color information, such as the tint or hue of an image recreated from the processed signal. Preferably, the phase of the processing operation should be within 2° of the chrominance signal. To maintain a precise phase relationship between the transmitted chrominance signal and a chrominance signal processing operation, a color synchronizing burst signal, shown in Fig. 1A, is transmitted with the chrominance signal to provide a phase reference for the processing operation. The color synchronizing burst is a short, unmodulated signal usually consisting of nine cycles and is located on the back-porch of the horizontal blanking interval, after the horizontal sync pulses. A chrominance processing operation uses the color synchronizing burst to generate an internal reference signal. The reference signal is generated by an Automatic Phase Control (APC) operation which separates and amplifies the color synchronizing burst signal, and then locks the phase of a local reference oscillator of the same frequency as the burst signal to the phase of burst signal. In analog chrominance signal processing, the phase-locking is usually provided by a phase locked-loop, as shown in Fig. 2, or a phase controlled oscillator. Typically, the phase-locked loop is formed by a DC voltage controlled oscillator (VCO) 40, which generates the internal reference signal, in combination with a phase detector 42 and a low pass filter 41. The phase detector 42 is supplied with the VCO output signal and the color synchronizing burst signal and generates a DC output having polarity and amplitude proportional to the direction and magnitude of the relative phase difference between the VCO output signal and the color synchronizing burst signal. The DC output is filtered by the low pass filter 41 and supplied to the VCO 40 to control the phase of the oscillator output signal. The DC output is varied until the phase of the oscillator output signal matches the phase of the color synchronizing burst signal. The low pass filter 41 modifies the dynamic performance of the phase locked loop by changing the DC loop gain. To achieve proper balance between the color and the luminance amplitudes, and thus avoid oversaturation of bright colors in reproduced image, the gain of the chrominance signal must be maintained at a constant level to compensate for changes in the chrominance signal caused by variations in scenes, transmission, propagation and receiver fine tuning. Typically, the color and the luminance amplitudes are balanced by an Automatic Chroma Control (ACC) operation provided by a feedback system which detects the amplitude of the color synchronizing burst signal and supplies a DC voltage to an amplifier to maintain the burst signal at a constant level and thus prevent the maximum amplitude of the chrominance signal from exceeding a predetermined value. Similarly, in digital chrominance signal processing, APC and ACC operations are necessary. As an example, Fig. 3 illustrates a known circuit for processing a digitized composite video signal to generate primary color signals. The circuit includes a Y/C separating circuit 20, a video processing circuit 21, an automatic chroma control (ACC) circuit 23, an automatic phase control (APC) circuit 24, a color signal demodulator 25, and a circuit 22. The Y/C separating circuit 20 separates the composite digital video signal into a portion representing a digitized luminance signal (Y signal) and a portion representing a digitized chrominance signal (C signal). The Y/C separating circuit 20 delivers the Y signal to the video processing circuit 21 which functions to amplify the Y signal, perform additional processing operations and deliver the processed y signal to matrix circuit 22. The Y/C separating circuit 20 also delivers the C signal to the ACC circuit 23 which operates to balance the amplitude of the C signal to provide a constant level C signal. The ACC circuit delivers the constant level C signal to the automatic phase control (APC) circuit 24 and to the color signal demodulator circuit 25. The APC circuit 24 responds to a burst gate pulse signal to process the constant level C signal to generate a reference clock signal f SC having a phase locked to the color synchronizing burst signal. The APC circuit 24 also generates a sampling clock signal of frequency 4f SC . The circuit 24 delivers the sampling clock signal 4f SC to the color signal demodulator circuit 25 which uses the sampling clock signal as an internal reference clock for demodulating the constant level C signal delivered by ACC circuit 23. The color signal demodulator circuit 25 recovers color difference signals R-Y, G-Y and B-Y by sampling the C signal under the timing of the sampling clock signal 4f SC and delivers the color difference signals to matrix circuit 22 which linearly cross-mixes the color difference signals R-Y, G-Y and B-Y with the Y signal in predetermined proportions to produce primary color signals R, G and B. Fig. 4 illustrates the APC circuit 24 shown in Fig. 3. Generally, the APC circuit 24 phase-locks the reference clock signal f SC to the phase of the color synchronizing burst signal in a manner analogous to the analog APC circuit shown in Fig. 2. As shown in Fig. 4, the APC circuit includes a phase comparator circuit 26, a lag/lead filter circuit 27, a digital-to-analog (D/A) converter circuit 28, a voltage controlled oscillator (VCO) circuit 29 and a frequency divider circuit 30 sequentially arranged to form a phase-locked loop. The phase comparator circuit 26 is operative to separate the color synchronizing burst signal portion of the digitized chrominance signal using the burst gate pulse signal as a reference. The phase comparator circuit 26 compares the phase data derived from the color synchronizing burst signal portion of the C signal with the reference clock signal f SC and delivers a digital signal representing the direction and magnitude of the relative phase difference between the color synchronizing burst signal and the reference clock signal f SC to the lag/lead filter 27. The lag/lead filter 27 operates to modify the dynamic performance of the phase locked loop in a manner analogous to that of the low pass filter 41 of the analog circuit of Fig. 2, and the lag/lead filter 27 delivers filtered digital output to D/A converter 28. The filtered digital output is converted to an analog DC output by D/A converter 28 which delivers the DC output to the VCO 29. The VCO 29 generates a sampling clock signal 4f SC having a frequency four times that of the reference clock signal and having a phase controlled by the DC output and delivers the sampling clock signal to the frequency divider 30 to generate the reference clock signal f SC . As in the analog APC circuit, the relative phase difference between the color synchronizing burst signal and the reference clock signal causes the VCO 29 to generate a sampling clock signal 4f SC of different phase such that the relative phase difference is smaller. The phase of the sampling clock signal is varied until the relative phase difference between the color synchronizing burst signal and the reference clock signal is eliminated. When the relative phase difference is eliminated, the phase of the sampling clock and reference-clock signals remain constant, and the APC circuit is phase locked. Fig. 5 illustrates the analog chrominance signal from which the digitized chrominance signal is generated and shows locations corresponding to those sampled by the color signal demodulator circuit 25. When the APC circuit 24 is properly phase locked, the APC circuit 24 delivers the sampling clock signal 4f SC to the color signal demodulator circuit 25 to time the chrominance signal sampling such that the chrominance signal is sampled at those locations whereat the color difference values B-Y and the color difference values R-Y are indicated. The phase locking of the APC circuit thus allows recovery of the B-Y and R-Y color difference signals in one sampling operation. Fig. 6 illustrates the ACC circuit 23 shown in Fig. 3. Generally, the ACC circuit operates in a manner analogous to the ACC circuit used in processing analog chrominance signals and prevents the maximum amplitude represented by the digital chrominance signal from exceeding a predetermined value. As shown in Fig. 6, the ACC circuit includes, in sequence, a multiplier circuit 31, a burst peak detector circuit 32, a comparator circuit 33 and an integrator circuit 34 arranged to form a feedback loop. The multiplier 31 is operative to deliver the digitized chrominance signal to burst detector 32 which detects the maximum amplitude of the color synchronizing burst signal and supplies the detected maximum amplitude to the comparator circuit 33. The comparator circuit 33 compares the detected maximum amplitude to a reference level and forms a difference signal representing the difference between the detected maximum amplitude and the reference level. The comparator circuit 33 delivers the difference signal to the integrator circuit 34 which integrates the difference signal over a time period, such as over one horizontal line period, to calculate coefficient data which correspond to the difference between the detected maximum amplitude and the reference level. The integrator circuit 34 supplies the coefficient data to multiplier circuit 31 which multiplies each component of the chrominance signal by a portion of the coefficient data to modify the amplitude of the C signal and generate a digital chrominance signal having a constant level. The multiplier 31 delivers the constant level chrominance signal to the APC circuit 24 for phase locking and to the demodulator circuit 25 for separation of the color difference signals, as well as to the burst peak detector 32 for further level balancing. As shown in Fig. 3, the known digital chrominance signal processing circuit has the drawback that the circuit elements are dedicated to only one operation. The APC circuit elements are used only for the APC operation and are not available for other signal processing operations, such as for the ACC operation, though the two operations have overlapping functions. Likewise, the ACC circuit elements are available only for the ACC operation and are not available for other signal processing operations, such as the APC operation. Because the circuit elements are dedicated to only one operation, the number of circuit elements used in the signal processing circuit is greatly increased and the size of the circuit is likewise increased. Furthermore, because separate circuit elements are used to perform overlapping functions in several operations, the circuit elements are used inefficiently. Therefore, an object of the present invention is to provide apparatus and methods for processing chrominance signals which avoid the aforementioned disadvantages of the related art. According to the present invention, there is provided a chrominance signal processing apparatus as defined in claim 1 and a method of processing a chrominance signal as defined in claim 16. A latched burst gate control signal may be generated as a function of a burst gate control signal and the reference clock signal to control switching of the portion of the chrominance signal and so enable the storing of the portion of the chrominance signal. The generating of the sequence of addresses may be reset in accordance with the latched burst gate control signal. The phase error data may be calculated by calculating respective differences between selected ones of the samples and then averaging these differences, and the averages may be lag-lead filtered. The phase error data may be accumulated over a horizontal scan period, and the accumulated phase error data stored in a register. A sub-carrier clock signal, from which the reference clock signal is generated, may also be generated. The difference data may be calculated by calculating respective sums of absolute values of the adjacent samples and then determining a maximum value of the respective sums. A reference value may be subtracted from the maximum value to form the difference value, and the difference value may be integrated over a horizontal scan period. Coefficient data that correspond to the integrated reference value may then be selected. Thus, there may be provided apparatus and methods for processing chrominance signals in which automatic phase control and automatic chroma control operations are performed using circuit elements that are available for both operations. There may also be provided apparatus and methods for processing chrominance signals in which automatic phase control operations or automatic chroma control operations are carried out using circuit elements that are also available for other chrominance signal processing operations. The above, and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the present invention given by way of example only with reference to the accompanying drawings in which corresponding parts are identified by the same reference numeral and in which: Figs. 1A and 1B are diagrams respectively illustrating a chrominance signal and a combined luminance and chrominance signal of a video signal; Fig. 2 is a block diagram showing a known analog automatic phase control circuit; Fig. 3 is a block diagram showing a known digital chrominance signal processing circuit; Fig. 4 is a block diagram showing the automatic phase control circuit of the known chrominance signal processing circuit of Fig. 3; Fig. 5 is a diagram illustrating the desired locations from which the chrominance signal waveform is sampled; Fig. 6 is a block diagram showing the automatic chroma control circuit of the known chrominance signal processing circuit of Fig. 3; Fig. 7 is a block diagram showing a chrominance signal processing circuit according to an embodiment of the present invention; Figs. 8A-8F are diagrams illustrating the signals and waveforms operated on by the chrominance signal processing circuit of Fig. 7; Figs. 9A-9B are diagrams illustrating locations from which the chrominance signal waveform is sampled by the chrominance signal processing circuit of Fig. 7 when a phase error is present; Fig. 10 is a flow chart referred to in explaining the automatic phase control operation of the chrominance signal processing circuit of Fig. 7; and Fig. 11 is a flow chart referred to in explaining the automatic chroma control operation of the chrominance signal processing circuit of Fig. 7. The present invention incorporates automatic phase control and automatic chroma control operations into the processing of chrominance signals by using circuit elements that are available for both operations as well as for other chrominance signal processing operations. Fig. 7 is a block diagram of a circuit for processing a digitized chrominance signal according to an embodiment of the present invention. The circuit shown in Fig. 7 is operable to perform APC and ACC operations and, as an example, is operable in place of the ACC circuit 23 and the APC circuit 24 shown in Fig. 3. The digital chrominance signal processing circuit shown in Fig. 7 includes an automatic phase control (APC) phase locked loop and an automatic chroma control (ACC) feedback loop. The APC loop includes a flip-flop circuit 3; a reset circuit 4; an address counter 5; a microprocessor 16 including a memory 2, a calculation unit 6, an accumulator 8, a data bus 9 and an APC register 10 under the control of a control unit 7; a D/A converter 12; a voltage controlled oscillator (VCO) 13; and a frequency divider 14. The ACC loop includes a multiplier 1; a memory 2, calculation unit 6, accumulator 8, data bus 9, and an ACC register 11 of the microprocessor 16 under the control of the control unit 7; and a ROM 15. In the APC loop, a burst gate pulse signal (BGP) which coincides with the portion of the digital chrominance signal in which the color subcarrier data is stored, shown in Fig 8(a), and a reference clock signal f SC , shown in Fig. 8(b), are supplied to the flip-flop circuit 3. The flip-flop circuit 3, which may be a D-type flip-flop, is triggered to change the state of its output with the first rise in reference clock signal f SC that follows a change in the state of the burst gate pulse signal and thus generates a latched burst gate pulse signal having a duration of fourteen reference clock signal cycles, shown in Fig. 8(c). The flip-flop circuit 3 delivers the latched burst gate pulse signal to the reset circuit 4 which operates to detect a leading edge of the latched burst gate pulse signal and then supplies a counter reset pulse signal, shown in Fig. 8(d), to the address counter 5. The address counter 5, in response to the counter reset pulse, initiates counting a sampling clock signal 4f SC supplied by the VCO 13, and generates a sequence of addresses corresponding to the cycles of the sampling clock signal, shown in Fig. 8(e). The address counter 5 delivers a new address to memory 2 of microprocessor 16 with each increase in the count. The flip-flop circuit 3 also delivers the latched burst gate pulse to the memory 2 and to a switch SW of the microprocessor 16. During the latched burst gate pulse signal interval, shown in Fig. 8(c), the switch SW contacts, position "a" to connect the multiplier 1 to the memory 2. During this interval, the multiplier 1 delivers the digitized chrominance signal to the memory 2 which stores respective samples of the chrominance signal at the addresses supplied by the address counter 5. The digitized chrominance signal is sampled with each sampling clock signal 4f SC which, when correctly in phase, correspond to the locations shown in the analog representation of the chrominance signal shown in Fig. 8(f). During intervals other than the latched burst gate pulse interval, the switch SW contacts position "b" to connect the memory 2 to the data bus 9, and additional data is delivered to the memory 2, as described below. The memory 2 delivers the samples of the chrominance signal to the calculation unit 6 via the data bus 9 under the control of the control unit 7. The calculation unit 6 calculates phase error data as a function of the samples of the chrominance data and delivers the phase error data to the accumulator 8 which accumulates the phase error data over a time period, such as during a horizontal line scan period. The accumulator 8 delivers the accumulated phase error data to the memory 2 for storage therein and to the APC register 10 for temporary storage. The accumulator 8 and the APC register 10 function in a manner well known in the art. The APC register 10 delivers the stored phase error data to the D/A converter circuit 12 which converts the phase error data to an analog DC output and delivers the DC output to the VCO 13. The VCO 13 generates a sampling clock signal 4f SC and delivers the sampling clock signal to the frequency divider circuit 14 which generates the reference clock signal f SC which, as described above, is supplied to the flip-flop circuit 3. The VCO 13 also delivers the sampling clock signal 4f SC to the address counter 5 for counting, as is also described above. The VCO 13 and the frequency divider circuit 14, as a function of the phase error data, are caused to vary the phase of the sampling clock signal 4f SC and the phase of the reference clock signal f SC such that the timing of the address counting and the timing of the chrominance signal sampling are changed which, in turn, changes the values of subsequently calculated phase error data. Figs. 9A and 9B show the analog chrominance signal from which the digitized chrominance signal is derived and illustrate the effect of the phase of the sampling clock signal 4f SC , and accordingly the effect of the timing of the chrominance signal sampling, on the values of the phase error data. As shown in Fig. 9A, when the chrominance signal is sampled at a later time than desired, as represented by the dark dots, the phase error data represents a positive shift and effects change in the phase of the sampling clock signal such that subsequent sampling of the chrominance signal occurs earlier in time, and in turn reduces the values of subsequently calculated phase error data. Likewise, as shown in Fig. 9B, when the chrominance signal is sampled at an earlier time than is desired, the phase error data represents a negative shift and effects a change in the phase of the sampling clock signal such that subsequent sampling of the chrominance signal occurs later in time and in turn reduces the values of the subsequently calculated phase error data. Thus, the phase of the sampling clock signal is varied until the values of the phase error data are at a minimum. When the phase error data are at a minimum, the phase of the sampling clock and reference clock signals remain constant, and the APC loop is phase locked. The phase error data is stored in memory 2 for subsequent correction of the samples of the chrominance signal. The manner in which the calculation unit 6 calculates the phase error data will now be described with reference to the flow diagram depicted in Fig. 10. Generally, the calculation unit 6 determines the phase difference values as a function of the respective differences between selected samples of the chrominance signal. As shown in Fig. 10, the calculation unit 6 of the microprocessor 16 calculates a plurality of difference values C n by determining the difference between values D representing alternately sampled locations of the chrominance signal, namely the sampled locations nearest the zero crossing points shown in Figs. 9A-9B and then halving the respective differences, as shown at step 204. The determination of the values C n are summarized in the following manner: C n = D (4 n ) - D (4 n +2) 2 wherein 4n and 4n+2 represent the indices of the addresses shown in Figs. 8(e) and 9A-9B, and n - 0-13. The calculation unit 6 calculates the C n and delivers each C n to the memory 2 via the data bus 9 for storage in the memory 2. After the fourteen respective values of C n are calculated and stored, the calculation unit 6 averages the C n , summarized in the following manner: The calculation unit 6 lag/lead filters the value C n , average, as shown at step 208, to generate the phase error data and the calculation unit 6 delivers the phase error data to the memory 2 via the data bus 9 and the switch SW. As shown at step 210, the calculation unit 6 also delivers the phase error data to the accumulator 8 which accumulates the phase error data over a time period, as described above, and the accumulated phase error data is delivered via the data bus 9 to the APC register 10 for storage. The APC register 10 outputs the stored accumulated phase error data from the microprocessor 16 and delivers the accumulated phase error data to the D/A converter 12, as is also described above. In the ACC loop, shown in Fig. 7, the multiplier 1 delivers the digitized chrominance signal to the memory 2 of the microprocessor 16 via switch "a" during the latched burst gate pulse signal interval, and the memory 2 stores the respective samples of the chrominance signal during this interval, as described above. The memory 2 delivers the respective samples of the chrominance signal to the calculation unit 6 via the data bus 9. The calculation unit 6 calculates difference data from adjacent samples of the chrominance signal and delivers the difference data to the accumulator 8 which accumulates the difference data over a time period, such as during a horizontal line scan interval, as is known in the art. The accumulator 8 delivers the accumulated difference data to the ACC register 11 via the data bus 9 wherein the accumulated difference data is stored, as is also known in the art. The ACC register 11 delivers the accumulated difference data to the ROM 15. The ROM 15 stores coefficient data corresponding to possible difference data values and arranged in a data table. The ROM 15 retrieves the respective coefficient data corresponding to the difference data delivered by the ACC register 11 and delivers the retrieved coefficient data to the multiplier 1. The multiplier 1 multiplies the digitized chrominance signal by the coefficient data and forms a digital chrominance signal having a constant level. The multiplier 1 delivers the constant level chrominance signal to a color signal demodulator circuit as, for example, shown in Fig. 4. The multiplier 1 also delivers the constant level chrominance signal to the memory 2 of the microprocessor 16, and the constant level chrominance signal is sampled and stored therein. The ACC loop thus generates a constant level chrominance signal by multiplying the supplied digitized chrominance signal by coefficient data that correspond to difference data derived from the supplied digitized chrominance signal. The values of the coefficient data are selected such that difference data subsequently calculated from sampling the constant level digital chrominance signal have zero value. The manner in which the calculation unit 6 of the microprocessor 16 determines the difference data will now be described with reference to Fig. 11. The memory 2 of the microprocessor 16 supplies the calculation unit 6 with the sampled digital chrominance signal. As shown in step 304, the calculation unit 6 calculates a plurality of values M n derived from the absolute values of adjacent samples, D, summarized in the following manner: M n =| D 2 n | + | D 2 n +1 | wherein 2n and 2n+1 represent the indices of the addresses shown in Fig. 8(e) and n - 0-27. The calculation unit 6 delivers the values M n to the memory 2 via data bus 9. As shown at step 306, the calculation unit 6 selects from the values M n the one having the maximum value, denoted by M max . The calculation unit 6, as shown at step 308, then calculates a difference value X by subtracting a reference value A from the maximum value M max . The calculation unit 6 delivers the difference value X to the accumulator 8. As shown at step 310, the accumulator 8 calculates an integrated difference value Y n by combining the difference value with a previously integrated difference value Y n-1 . The integrated difference value Y n is generated during a predefined period, such as during a horizontal line scan interval. The accumulator 8 delivers the integrated difference value Y n to the ACC register 11 for storage, as shown in step 312. The ACC register 11 outputs the integrated difference value Y n from the microprocessor 16 and delivers the value Y n to the ROM 15 which retrieves coefficient data corresponding to the integrated difference value Y n , as described above, and delivers this coefficient data to the multiplier 1. Alternatively, the manner in which the calculation unit 6 calculates the difference values may be simplified and M max determined from the sampled digital chrominance signals stored at alternate addresses, such as at the odd indexed addresses 2n±1 of Fig. 8(e). As mentioned above, the sample having the maximum value is selected as M max . However, it may be preferable to calculate the value M max using the steps shown in Fig. 11 when random noises are present in the chrominance signal, such as when the chrominance signal is derived from a weak broadcast signal. As described above, the APC loop and the ACC loop of this embodiment of the present invention, shown in Fig. 7, each incorporate circuit elements used in both the APC and the ACC operations. Thus the number of circuit elements required by the circuit of Fig. 7 is reduced. Moreover, the circuit elements used in these operations are also available for other signal processing operations. Although an illustrative embodiment of the present invention, and various modifications thereof, have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to this precise embodiment and the described modifications, and that various changes and further modifications may be effected therein by one skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A chrominance signal processing apparatus for processing a chrominance signal containing a burst synchronization signal, comprising: address generating means (5) for generating a sequence of addresses as a function of a reference clock signal (4fsc); first memory means (2) for storing respective samples of a predetermined portion of said chrominance signal at respective ones of said sequence of addresses; calculating means (6) for calculating phase error data indicative of a phase difference between said reference clock signal and said burst synchronization signal as a function of said samples of said predetermined portion of said chrominance signal and for determining difference data derived from adjacent ones of said samples; oscillator means (13) for generating said reference clock signal in response to said phase error data such that said phase error data is minimized and said reference clock signal coincides with said burst synchronization signal; additional memory means (15) for storing coefficient data corresponding to said difference data; and multiplying means (1) for multiplying said predetermined portion of said chrominance signal by said coefficient data to form a constant level chrominance signal and for delivering said constant level chrominance signal to said first memory means (2). The apparatus of claim 1, further comprising a burst gate control signal source and latching means (3) responsive to said reference clock signal (fsc) for latching the burst gate control signal to switch (sw) said predetermined portion of said chrominance signal to said memory means (2). The apparatus of claim 1 or 2, further comprising reset means (4) for resetting said address generating means (5) to initiate generating said sequence of addresses as a function of said latched burst gate control signal. The apparatus of claim 1, 2 or 3 wherein said calculating means (6) calculates respective differences between selected ones of said samples and averages said differences. The apparatus of claim 4, wherein said calculating means (6) lag-lead filters said average to calculate said phase error data. The apparatus of any preceding claim, further comprising accumulator means (8) for accumulating said phase error data over a horizontal scan period for delivery to said oscillator means (13) for generating said reference clock signal. The apparatus of claim 6, further comprising register means (10) for storing said accumulated phase error data for delivery to said oscillator means (13). The apparatus of any preceding claim, further comprising digital-to-analog converter means (12) for converting said phase error data to an analog DC voltage. The apparatus of claim 8, wherein said oscillator means comprises a voltage controlled oscillator (12) for generating a sampling clock signal (4fsc) as a function of said analog DC voltage. The apparatus of claim 9, further comprising dividing means (14) for dividing said sampling clock signal (4fsc) to generate said reference clock signal (fsc). The apparatus of any preceding claim, wherein said memory means (2) stores said phase error data. The apparatus of any preceding claim, wherein said calculating means (6) calculates respective sums of absolute values of said adjacent ones of said samples and determines a maximum value (Mmax) of said respective sums. The apparatus of claim 12, wherein said calculating means (6) calculates said difference data by subtracting a reference value (A) from said maximum value (Mmax). The apparatus of claim 13, further comprising accumulator means (8) for calculating an integrated reference value by integrating said reference values over a horizontal scan period. The apparatus of claim 14, wherein said additional memory means (15) selects coefficient data corresponding to said integrated reference value for delivery to said multiplying means (1). A method of processing a chrominance signal containing a burst synchronization signal, comprising the steps of: generating (5) a sequence of addresses as a function of a reference clock signal (4fsc); storing (2) respective samples of a predetermined portion of said chrominance signal at respective ones of said sequence of addresses; calculating (6) phase error data indicative of a phase difference between said reference clock signal and said burst synchronization signal as a function of said samples of said predetermined portion of said chrominance signal; generating (13) said reference clock signal in response to said phase error data such that said phase error data is minimized and said reference clock signal coincides with said burst synchronization signal; determining difference data derived from adjacent ones of said samples; storing coefficient data corresponding to said difference data; multiplying (1) said predetermined portion of said chrominance signal by said coefficient data to form a constant level chrominance signal; and storing said constant level chrominance signal. The method of claim 16, further comprising the steps of providing a burst qate control siqnal, latching (3) said burst gate control signal in response to said reference clock signal, and switching said predetermined portion of said chrominance signal to said memory means (2) as a function of said latched burst gate control signal. The method of claim 17, further comprising the step of resetting (4) said generating of said sequence of addresses as a function of said latched burst gate control signal. The method of claim 16, 17 or 18, wherein the step of calculating phase error data includes calculating (6) respective differences between selected ones of said samples and averaging said differences. The method of claim 19, wherein the step of calculating (6) phase error data further includes lag-lead filtering said average to calculate said phase error data. The method of any one of claims 16 to 20, further comprising the step of accumulating (8) said phase error data over a horizontal scan period. The method of claim 21, further comprising the step of storing (10) said accumulated phase error data. The method of any one of claims 16 to 22, further comprising the step of digital-to-analog converting (12) said phase error data to an analog DC voltage. The method of claim 23, wherein the step of generating said reference clock signal includes generating (12) a sub-carrier clock signal as a function of said analog DC voltage. The method of claim 24, wherein the step of generating said reference clock signal includes dividing (14) said sub-carrier clock signal to generate said reference clock signal. The method of any one of claims 16 to 25, further comprising the step of storing said phase error data. The method of any one of claims 16 to 26, wherein the step of determining difference data includes calculating (6) respective sums of absolute values of said adjacent ones of said samples and determines a maximum value of said respective sums. The method of claim 27, wherein the step of determining difference data includes subtracting a reference value from said maximum value. The method of claim 16, 27 or 28, further comprising the step of calculating (8) an integrated reference value by integrating said reference values over a horizontal scan period. The method of claim 29, further comprising the step of selecting (15) coefficient data corresponding to said integrated reference value.

Inventors: MIYASAKI SHINICHIROU, WATANABE KAZUO, MIYASAKI, SHINICHIROU, WATANABE, KAZUO, MIYASAKI, SHINICHIROU C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: H04N9
IPC codes: H04N9