An A/D conversion control apparatus for an internal combustion engine

Abstract: An A/D conversion control apparatus(10) includes a control circuit (129) for controlling various actuators and an A/D converter (14) having a plurality of signal input channels. The control circuit (12) and the A/D converter (14) are packed in different IC packages and perform communication of a handshake system therebetween. Because the control of the A/D converter (14) is performed based on channel start signals which are sequentially transmitted from a time synchronous register (32), complicated control such as schedule control in software is not required. A start signal stored in an asynchronous register (30) is transmitted in response to a signal generated at an asynchronous timing and therefore can be processed at a different timing.

Description: The present invention relates to an A/D conversion control apparatus for internal combustion engine, which apparatus has a plurality of signal input channels. For control of an internal combustion engine for an automobile or the like, an analog/digital (A/D) converter is provided for converting analog signals inputted from various sensors for detecting states of an objective to be controlled, into digital signals. In JP-A-2-153248 is proposed an A/D conversion control apparatus in which a plurality of analog signals are sequentially A/D-converted at a predetermined period by a hardware construction to be stored in predetermined storage areas so that the load of software processing can be decreased. In the control of an internal combustion engine, however, the A/D conversion needs to be performed in synchronism with external signals such as a signal indicating engine rotation positions, as well as the A/D conversion at the predetermined period as in the above conventional apparatus. Thus, because the A/D conversion is performed only at the predetermined period in the conventional A/D conversion control apparatus, the internal combustion engine can not be controlled precisely. The present invention has been made to solve the above problem and has, as an object, to provide an A/D conversion control apparatus in which not only the load of software processing can be decreased but also the A/D conversion can be performed both at a predetermined period and in synchronism with an external signal. EP 474025 discloses an analogue to digital conversion system module for use in an automotive engine control system to convert analogue signals from transducers for processing by an engine micro-computer. The module comprises an A/D converter which has inputs through a plurality of external multiplexers. A control register and logic circuit is provided with signal paths between it and RAM storing a table of command control words, a results table and an address decode circuit. A trigger select and priority circuit coupled to a periodic timer in responsive to external trigger signals to initiate A/D conversion. According to the invention there is provided an A/D conversion control apparatus for an internal combustion engine comprising: A/D converter means having a plurality of input channels; first means for storing start signals for starting designated ones of said plurality of input channels; and second means for storing a start signal required for starting a designated one of said plurality of input channels and for transmitting said start signal based on an external signal, wherein said A/D converter means starts the input channel corresponding to the start signal based on the start signal transmitted from the first and second means, the apparatus further comprising: an analog multiplexer connecting a plurality of input channels to said A/D converter means in response to start signals such that the analog signals are inputted to said A/D converter means through the input channels; and wherein the first means comprises a time synchronous register having a plurality of storage areas, for storing the start signals for said input channels and for sequentially outputting start signals for starting the input channels start at a predetermined period of time (f2), in synchronism with time; and said second means comprises an asynchronous register for outputting a prestored start signal at a time synchronous with generation of the external signal; an AD schedule control circuit for receiving the start signals from both said registers and selecting one of the received start signals to output the selected start signal to said A/D converter means (14) and wherein said AD schedule control circuit is arranged to output when the start signal is received from said asynchronous register during the sequential output of the start signals from the time synchronous register, the start signal supplied from said asynchronous register to said A/D converter means when one half of the period of time elapses, if a time elapsed from when the start signal from said time synchronous register immediately before the reception of the start signal from said asynchronous register is outputted, is shorter than the half of the period of time, and the start signal from said asynchronous register after the half of the period of time from when the next start signal supplied from said time synchronous register is outputted if the elapsed time is longer than the half of the period of time. Thus the first means stores the plurality of start signals for starting the designated ones of the plurality of input channels of the A/D converter means. Similarly, the second means stores the start signal for starting the designated one of the plurality of input channels of the A/D converter means and outputs the start signal based on the external signal. The A/D converter means starts the input channels corresponding to the start signals from the first means or the start signal from the second means, respectively. The control of the A/D converter means is performed based on the start signals sequentially transmitted from the first means and the start signal transmitted from the second means. Because the start signal is transmitted from the second means in response to the external signal, the control of the A/D converter means can be performed not only based on the start signal from the first means but also at the timing different from the timing of the start signals from the first means. For the internal combustion engine, the control of the A/D converter means needs to be performed at the different timings, e.g., at every predetermined period and in response to engine rotation. Even in such a case, the start signals stored in the first means can be outputted at the timing of the predetermined period or completion of the A/D conversion and the start signal stored in the second means can be outputted in synchronism with engine rotation. Figs. 1A and 1B are schematic block diagrams; Fig. 2 is a block diagram showing the structure of an A/D conversion control apparatus for an internal combustion engine according to an embodiment of the present invention; Fig. 3 is a flow chart for explaining the operation when a CPU starts the synchronous register; Fig. 4A-1 to 4B are diagrams to explain the data communication system of the embodiment, where Fig. 4A-1 shows a sequential register, Fig. 4A-2 shows an asynchronous register, Fig. 4A-3 shows a data pick-up register and Fig. 4B shows the operation timing. Figs. 5A through 5C are timing charts of the operation of an A/D converter, where Fig. 5A shows the timing chart; Fig. 5B shows the timing chart in a normal scan mode and Fig. 5C shows the timing chart in an external trigger mode. Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Fig. 2 is a block diagram showing an A/D conversion control apparatus 10 according to an embodiment of the present invention. The apparatus 10 includes a control circuit 12 for controlling various actuators and an A/D converter 14 having a plurality of input channels. The control circuit 12 and the A/D converter 14 are constituted as separate or discrete IC packages and communication of a handshake system is performed therebetween. The control circuit 12 is a microcomputer for performing various types of controls such as fuel injection control, ignition timing control, idle rotation speed control and transmission control. Also, the control circuit 12 executes predetermined operations based on digital data supplied from various sensors, digital data A/D-converted by the A/D converter 14, control signals supplied from an external unit. The digital data supplied to the control circuit 12 from the various sensors are such as a crank position, an engine speed, an ignition monitor value, an oxygen sensor value, an automobile speed, an idle signal value, air conditioner signal and a starter signal value. The control circuit 12 includes a CPU 20, a ROM (read only memory) 22, a RAM (random access memory) 24, a timer 26, an asynchronous register 30, a time synchronous register 32, a data pickup register 34, an AD schedule control circuit 36, a shift clock 38 and a shift register 40 therein. The CPU 20 is a central processing unit for, based on a control program stored in the ROM 22, executing various processes, and storing in the RAM 24 or transmitting to the external unit the operation result. The timer 26 supplies synchronous clock pulses to control the whole control circuit 12. The asynchronous register 30 stores a start signal for starting or selecting a designated one of a plurality of signal input channels of the A/D converter 14 and is started or controlled by the CPU 20 based on an asynchronous timing signal which is synchronous with a crank position sensor input or the like so that the start signal for the A/D conversion is outputted. The time synchronous register 32 stores a plurality of start signals for starting or selecting designated ones of the plurality of input channels of the A/D converter 14. The start signals stored therein are sequentially outputted in synchronism with a synchronous signal from the timer 26. The data pickup register 34 stores after-conversion data obtained by the A/D conversion by the A/D converter 14. The data pickup register 34 has storage addresses in correspondence to the start signal stored in the asynchronous register 30 and the start signals stored in the time synchronous register 32. The AD schedule control circuit 36 is a logic circuit for selecting one of the start signals supplied from the asynchronous register 30 or the time synchronous register 32 and supplying the selected start signal to the shift clock 38. Also, the AD schedule control circuit 36 receives the after-conversion data from the A/D converter 14 to write it in the data pickup register 34 at the same time. The shift clock 38 generates pulses for the number of bits in the after-conversion data at the timing determined by the AD schedule control circuit 36. Based on the pulses generated by the shift clock 38, the timings for the supply of the start signal for each channel of the A/D converter 14 and the reception of the after-conversion data from the A/D converter 14 are determined. In the embodiment, because 16-bit data is transmitted or received, the shift clock 38 generates the pulses for 16 bits. The timing synchronous with time and the timing determined by the synchronous signal which is generated based on the external input such as a crank position sensor input or the like could be considered as the timing determined by the AD schedule control circuit 36. The shift register 40 transmits the start signal for each channel of the A/D converter 14 and receives the after-conversion data from the A/D converter 14. It transmits or receives 16-bit serial data in the embodiment. The A/D converter 14 having a plurality of input channels converts each of analog signals supplied from various sensors into digital data and transmits the digital data to the control circuit 12. As the analog signals supplied to the A/D converter 14 are analog signals indicating a combustion pressure, a knock, an air flow rate, a battery voltage, a water temperature, an inlet air temperature, a throttle opening, and the like. The A/D converter 14 includes an analog multiplexer 50, an ADC core 52, an ADC control circuit 54 and a shift register 56. The analog multiplexer 50 switches 24 input channels of CH0 to CH23 to select the analog signal to be inputted to the A/D converter 14. The selection control of the input channel by the analog multiplexer 50 is controlled by the ADC control circuit 54. The analog signal inputted from the selected channel is supplied to the ADC core 52. The ADC core 52 converts the analog signals into digital signals. The function of A/D conversion by the ADC core 52 is used commonly to the analog signals from the input channels. Thus, one analog signal is selected from among the plurality of analog signals inputted to the analog multiplexer 50 and is subjected to the A/D conversion. The ADC control circuit 54 controls the analog multiplexer 50, the ADC core 52 and the shift register 56 to achieve the A/D conversion by the A/D converter 14. The ADC control circuit 54 transmits the channel start signal supplied from the shift register 56 to the analog multiplexer 50 to make the designated input channel selected and receives after-conversion data from the ADC core 52 to transmit the same to the shift register 56. The shift register 56 receives a start signal for each input channel from the control circuit 12 and transmits the after-conversion data from the ADC core 52 to the control circuit 12. In the embodiment, 16-bit serial data is transmitted and received. According to the above construction, the A/D converter 14 corresponds to A/D converter means and the CPU 20 corresponds to control means. Further, the time synchronous register 32 and the AD schedule control circuit 36 collectively correspond to first storage means and asynchronous register 30 and the AD schedule control circuit 36 collectively correspond to second storage means. A data communication system achieved by the above construction will be described below in detail. Figs. 4A-1, 4A-2, 4A-3 and 4B show a data communication system of the embodiment. As shown in Fig. 4A-1 in the embodiment, a sequential register 32a is provided. The sequential register 32a stores channel start signals SCDR0 to SCDR15 for 16 bytes. Fig. 4A-2 shows an asynchronous register 30a and the register 30a stores the channel start signal ACDR as data. A data pickup register 34a is shown in Fig. 4A-3 and stores after-conversion data SCBF0 to SCBF15 and ACBF for 17 bytes in correspondence to the channel start signals SCDR0 to SCDR15 and ACDR. The channel start signals SCDR0 to SCDR15 in the embodiment are transmitted at a period f2 (f2 = 256 µs) That is, for the period f1 satisfying t < f1 where t is the A/D conversion time, in the embodiment the period f2 is used satisfying f2 > 2 x f1. In this case, a half of the period f2 is longer than the A/D conversion time t. In the embodiment, the data communication system when an asynchronous request is received is as follows. The channel start signals SCDR0 to SCDR15 are sequentially read out from the sequential register 32a one by one from the smallest address, i.e. the channel start signal SCDR0. When the channel start signal SCDR15 of which address is largest is read out, the channel start signal SCDR0 is read out again. Thus, as far as a stop request is not inputted from the external unit, the channel start signals SCDR0 to SCDR15 are read out repeatedly and transmitted to the A/D converter 14. It is shown in Fig. 4B how the registers 30a to 34a of the control circuit 12 perform read operations or write operations at what timing. In the embodiment, the control circuit 12 also performs the handshake data communication with the A/D converter 14. The transmission of the channel start signals SCDR0 to SCDR15 and ACDR and the reception of after-conversion data SCBF0 to SCBF15 and ACBF are performed at the timings of pulses supplied from the control circuit 12. As shown in Fig. 4B, the channel start signals SCDR0 to SCDR15 are sequentially and repeatedly read out one by one to be transmitted to the A/D converter 14. In synchronism with this, data A/D-converted by the A/D converter 14 are received from the A/D converter 14 as after-conversion data SCBF0 to SCBF15 to be stored in the data pickup register 34a. It is assumed that the asynchronous request for the A/D conversion is issued after the channel start signal SCDR3 is transmitted but before the next channel start signal SCDR4 is transmitted. In the example shown in Fig. 4B, it is assumed that the asynchronous request is issued after a half of the period f2 from the time when the channel start signal SCDR3 is transmitted. In this case, the A/D conversion for the channel start signal SCDR3 is first performed and then the A/D conversion for the asynchronous request is performed after time t1. More particularly, the after-conversion data SCBF3 for the channel start signal SCDR3 is received after the period f2 to be stored in the data pickup register 34a. The next channel start signal SCDR4 is transmitted simultaneously with the reception of the after-conversion data SCBF3. After the time f2/2 has elapsed, the after-conversion data SCBF4 for the channel start signal SCDR4 is received to be stored in the data pickup register 34a. Because the period f2 is set to be long, the A/D conversion can be regarded to be completed if a half of the period f2 has elapsed. Further, at the same time when the after-conversion data SCBF4 is received, the channel start signal ACDR is read out from the asynchronous register 30a in response to the asynchronous request already inputted as an interrupt to be supplied to the A/D converter 14. At the time when a half of the period f2, i.e., a time t2 has elapsed, the after-conversion data ACBF for the channel start signal ACDR is received and the next channel start signal SCDR5 is transmitted. If the asynchronous request is inputted before the time f2/2 elapses after the channel start signal SCDR3 has been transmitted, the after-conversion data SCBF3 can be received without waiting for the next channel start signal SCDR4 at the time when the time f2/2 elapses after the channel start signal SCDR3 has been transmitted and then the channel start signal ACDR can be transmitted. For this reason, the time t1 from when the asynchronous request is inputted to when the channel start signal ACDR is transmitted is shorter than the period f2. Such an operation is repeated and, when the channel start signal SCDR15 is transmitted, the operation is automatically returned to the channel start signal SCDR0 and repeated until a signal instructing stop is inputted. The CPU 20 is interrupted at the timing when the channel start signal SCDR0 is transmitted to the A/D converter 14 and the after-conversion data SCBF0 to SCBF15 are collectively subjected to the code error detection and various operation processes. In the embodiment, there is provided the period f2 having a time margin such that the A/D conversion for an asynchronous request can be performed without distorting the synchronous process when the asynchronous request is issued. That is, the timings for the channel start signals SCDRO to SCDR15 to be sequentially transmitted need not be deviated. For instance, if the deviation from the synchronous timing is for the throttle opening to be inputted synchronously, the difference of the actual operation amount from a desired operation amount is caused so that the good operability cannot be sufficiently achieved. Thus, the embodiment is effective when a sensor signal should be inputted without deviation from the synchronous timing. Further, in the embodiment, although the processing for the asynchronous request is possibly delayed for the time f2 at maximum, because the time f2 is sufficiently long, the response characteristic results in obtaining remarkably good effects compared with conventional apparatus. Next, the process executed by the A/D converter 14 will be described below. The embodiment is designed to receive the after-conversion data from the A/D converter 14 at the timings of pulses from the control circuit 12 However, in order to obtain the effect according to the structure in which the channel start signals are transmitted at two different timings, there may be employed a structure in which an A/D conversion end flag from the A/D converter 14 may be detected and transmitted by the control circuit 12. Figs. 5 to 5c show the timings of the transmission and reception of data at the A/D converter 14. Fig. 5A shows the timing of the communication system according to the embodiment. The channel start signals SCDR0 to SCDR15 are sequentially transmitted at the period f2 based on the signal transmitted from the control circuit 12. The process for the asynchronous request is performed after the time t1 shorter than the period f2. The detail of this has been already described. Fig. 5B shows the case where the A/D converter 14 is set in a normal mode. The after-conversion data is transmitted based on a flag set at the time t when the A/D conversion by the A/D converter 14 is completed. In this construction, data is transmitted at the timing on the A/D converter 14 side but the effect according to the first embodiment can be obtained. Fig. 5C shows a case where the A/D converter 14 is set in an external trigger mode. The A/D conversion is started in response to an external trigger. The after-conversion data is also transmitted to the control circuit 12 at the timing on the A/D converter 14 side in this construction.

Claims: An A/D conversion control apparatus for an internal combustion engine comprising: A/D converter means (14) having a plurality of input channels; first means (32a) for storing start signals for starting designated ones of said plurality of input channels; and second means for storing a start signal required for starting a designated one of said plurality of input channels and for transmitting said start signal based on an external signal, wherein said A/D converter means starts the input channel corresponding to the start signal based on the start signal transmitted from the first and second means, the apparatus further comprising: an analog multiplexer (50) connecting a plurality of input channels to said AID converter means in response to start signals such that the analog signals are inputted to said A/D converter means through the input channels; and wherein the first means comprises a time synchronous register (32) having a plurality of storage areas, for storing the start signals for said input channels and for sequentially outputting start signals for starting the input channels start at a predetermined period of time (f2), in synchronism with time; and said second means comprises an asynchronous register (30) for outputting a prestored start signal at a time synchronous with generation of the external signal; an AD schedule control circuit (36,136) for receiving the start signals from both said registers (30,32) and selecting one of the received start signals to output the selected start signal to said A/D converter means (14) and wherein said AD schedule control circuit is arranged to output when the start signal is received from said asynchronous register during the sequential output of the start signals from the time synchronous register, the start signal supplied from said asynchronous register to said A/D converter means when one half of the period of time (f2) elapses, if a time elapsed from when the start signal from said time synchronous register immediately before the reception of the start signal from said asynchronous register is outputted, is shorter than the half of the period of time (f2), and the start signal from said asynchronous register after the half of the period of time (f2) from when the next start signal supplied from said time synchronous register is outputted if the elapsed time is longer than the half of the period of time (f2). An A/D conversion control apparatus for an internal combustion engine according to claim 1, wherein said first means is arranged to sequentially output the plurality of start signals at a predetermined period of time (f1, f2) longer than a time (t) required for A/D conversion by said A/D converter means. An A/D conversion control apparatus for an internal combustion engine according to claim 1 or claim 2, wherein the time of the predetermined period (f2) is twice or more as long as the said required time. An A/D conversion control apparatus for an internal combustion engine according to any preceding claim, wherein the apparatus further comprises a CPU (20) for designating the input channels corresponding to the analogue signals to be A/D converted.

Inventors: GOTO YOSHINORI, OGINO TETSUYA, GOTO, YOSHINORI, OGINO, TETSUYA
Applicants: NIPPON DENSO CO, NIPPONDENSO CO., LTD.
Application year: 1994
Main classification: F02D41
IPC codes: G06F3, F02D41