Video processing circuit for a simultaneous display of two pictures

Abstract: In case a video signal of an aspect ratio of 4:3 of an NTSC system is fed by the first picture generating means and such video signal of an aspect ratio of 16:9 as for a high vision broadcast is fed by the second picture generating means, when a mode of displaying two pictures at such aspect ratios is directed, the first and second switching switches of the compressing means will be switched on, the digitalized video signal of the first picture will be compressed in the time axis at a compressing rate of 3/8 and the video signal of the second picture digitalized simultaneously with it will have a timing signal produced from the synchronous signals of the first picture and second picture. This timing signal is written into a memory and is read out by the timing lagged in the synchronization by 3H/8 from the first picture and the the digital processing circuit is controlled to compress in the time axis the video signal of the second picture at a compressing rate of 5/8 by the controlling means. Thereafter, the compressed video signal of the first picture and the compressed video signal of the second picture are converted to analogue signals and are then converted respectively to RGB signals in the matrix circuit. Then, the RGB signals are added together by means of the adding means and are driven to the cathode ray tube of an aspect ratio of 16:9 and the two pictures display divided to be 6:10 in the horizontal direction can be displayed. The vertical amplitude is controlled by means of the deflecting means and controlling means, thereby the vertical deflecting current fed to the cathode ray tube is controlled and a two pictures display wherein the optimum aspect ratios of the aspect ratio of 4:3 of the first picture and the aspect ratio of 16:9 of the second picture are obtained can be realized.

Description: Background of the Invention Field of the Invention: This invention relates to a television receiver provided with a cathode ray tube of an aspect ratio of 16:9 at which a wide aspect broadcast can be received and more particularly to a two pictures video processing circuit wherein a picture of an aspect ratio of 4:3, for example, of an NTSC system and a picture of an aspect ratio of 16:9 of a wide aspect broadcast can be two-pictures-displayed at the optimum aspect ratio in a television receiver wherein two pictures can be displayed by digitalizing and processing the video signal. Description of the Related Arts: Recently, with the multi-purpose use of television receivers, the displayed picture is being widened. For example, a wide aspect television receiver (which shall be abbreviated as a wide aspect television hereinafter) wherein such satellite broadcast as a hi-vision broadcast, such wide aspect broadcast as HD-MAC and PAL Plus and such general broadcast as an ordinary NTSC system broadcast can be received as compatible with each other is noted. As well known, this wide aspect television is provided with a displayed picture (CRT) having an aspect ratio of 16:9 so that the audience may effectively obtain a present feel or pressing feel and, for example, not only displays a picture of a video of 16:9 characterized by the hi-vision broadcast, for example, by using a MUSE-MTSC converter but also can naturally display the picture of a video of 4:3 of the current broadcast of the NTSC system. Besides such function, for example, an expanding function of expanding and displaying the video of 4:3 of the current broadcast on all the displayed picture surface of 16:9 and various functions of displaying the video of 4:3 on the displayed picture surface of 16:9 have been suggested. On the other hand, with the digitalization of the video technique, as well known, a digital television receiver wherein a video signal is processed by using a digital signal has prevailed. For example, the functions of improving the picture quality by digitalizing the video processing circuit, displaying such pictures as parent and son pictures (two pictures display) and displaying multi-pictures and reproducing stationary pictures by applying memories have also become well known. Thus, with the digitalization of the video technique, the wide aspect television can be provided with various functions, for example, by video-processing such analogue signal as a broadcast signal to be a digital signal and is expected to coexist with the hi-vision broadcast, satellite broadcast or current broadcast of the NTSC system. Therefore, an example of block diagram of such wide aspect television is shown in Fig. 3. Fig. 3 is a block diagram showing an example of block diagram of a conventional wide aspect television. As shown in Fig. 3, the reference numeral 100 represents an input terminal which a broadcast signal of the NTSC system is fed. The video signal input from this input terminal 100 is fed to a video processing circuit 101 formed of at least video intermediate frequency amplifying and video detecting circuits (not illustrated), is converted to an intermediate frequency signal and is taken out. Then this video signal is separated into a luminance signal Y (which shall be abbreviated as a Y signal hereinafter) and a chroma signal and then the chroma signal is demodulated to color difference signals (R-Y, B-Y). The Y signal and color difference signals demodulated by the video processing circuit 101 are fed to an A/D converting circuit 102 wherein the Y signal and color difference signals as analogue signals are converted to digital signals. The output signals of this A/D converting circuit 102 are fed to a time axis compressing circuit 103 compressing the input signals at a predetermined compressing rate. The digital signals are here compressed at the predetermined compressing rate and are fed to a D/A converting circuit 104. The digital signals compressed by the time axis compressing circuit 103 are converted to analogue signals by this D/A converting circuit 104 and are fed to a video processing circuit 105. Then the video signals compressed in the time axes are processed in the video by a video processing circuit 105 as in an ordinary television receiver and the respective color difference signals and Y signal are added to obtain R (red), G (green) and B (blue) signals and a CRT 107 is driven to display the picture compressed in the times axes in the CRT 107 formed with an aspect ratio of 16:9. Now, when the relations, for example, between the compressing rate of the time axis compressing circuit 103 and the video displayed in the picture in the CRT 107 are considered, first, in case the input video signal is not compressed by the time axis compressing circuit 103, as shown in Fig. 4 (a), for example, in case the input normal video signal is, of course, an NTSC signal of an aspect ratio of 4:3 and is a circle 150 as a video, an ellipse 150a to be a horizontally long video will be displayed in the displayed picture of the CRT 107 of an aspect ratio of 16:9. Therefore, the horizontally long video as mentioned above can be displayed in a normal video, that is, such video of an aspect ratio of 4:3 as, for example, the circle 150 can be displayed in the displayed picture of an aspect ratio of 16:9, by compressing the displayed video shown in the Fig. 4 (a) at a predetermined compressing rate from right and left. That is to say, as the video of an aspect ratio of 4:3 of the current broadcast (NTSC) can be displayed in the displayed picture of the CRT 107 of an aspect ratio of 16:9 as mentioned above, the predetermined compressing rate will be: (9/3) × 4/16=3/4. That is to say, if the displayed video is compressed at a compressing rated of 3/4, a normal video of 4:3 will be able to be displayed in the picture. Also, it is well known that such video signal compressing process can be easily carried out by using a digital signal and a digital processing circuit. On the other hand, in case, as mentioned above, the video signal input at a compressing rate of 3/4 is compressed and a video of an aspect ratio of 4:3 is displayed in the displayed picture of an aspect ratio of 16:9, as shown in Fig. 4 (b), a part of no signal, that is, a blank part 107a will be produced on the right and/or left of the displayed picture of the CRT 107. Therefore, in order to effectively utilize such blank part 107a and to enliven the feature of the wide aspect television, a function called a picture out picture function of displaying a son picture, for example, in the blank part 107a, that is, a function of a two pictures video has been already adopted. Fig. 5 is a block diagram showing an example of wide aspect television provided with such two pictures video function. As shown in Fig. 5, the video processing circuit group carrying out the two pictures video process comprises mostly a video processing circuit for displaying a parent picture shown on the upper step in Fig. 5, that is, the first picture and a video processing circuit for displaying a son picture shown on the lower step in Fig. 5, that is, the second picture. The video processing circuit shown on the lower step is generally a son picture video processing circuit for producing the second picture in the main first picture, compressing the second picture video signal at a predetermined compressing rate and reproducing it as synchronized with the first picture. The video processing circuit on the upper step is formed of substantially the same components as of the video processing circuit shown, for example, in Fig. 3. The difference is that a 1/2 compressing circuit 53 compressing the time axis at a compressing rate of 1/2 is provided and is characterized by being connected in parallel with a 3/4 compressing circuit 54. In the drawing, to explain first from the first picture video processing circuit on the upper step, the reference numeral 50 represents an input terminal in which a broadcast signal of an NTSC system is to be input and the video signal input from this input terminal 51 is fed to a video signal processing circuit 51 formed of at least video intermediate frequency amplifying and video detecting circuits (not illustrated), is converted to an intermediate frequency signal, is taken out and is then separated into a luminance signal Y (which shall be abbreviated as a Y signal hereinafter) and a chroma signal and the chroma signal is demodulated to color difference signals (R-Y, B-Y). The Y signal and color difference signals demodulated by the video processing circuit 51 are fed to an A/D converting circuit 52 and here the Y signal and color difference signals as analogue signals are converted to digital signals. The output signals of this A/D converting circuit 52 are fed to a time axis 1/2 compressing circuit 53 compressing the input signals at a compressing rate of 1/2 and the digital signals are compressed here at a compressing rate of 1/2 and are fed to the D/A converting circuit 55. On the other hand, the output terminal of the A/D converting circuit 52 is connected to a time axis 3/4 compressing circuit 54 compressing the time axis at a compressing rate of 3/4 and the input digital signals are compressed at a compressing rate of 3/4 and are fed to the D/A converting circuit 55. Here, the output signals of the 1/2 compressing circuit 53 and 3/4 compressing circuit 54 are switched by a switching means not illustrated. For example, the picture of 4:3 of the NTSC can be selected to be of a mode of displaying a picture of 4:3 or of a mode of displaying two pictures. The switching means (not illustrated) is operated by a control signal from a controlling means not illustrated. The digital signals compressed by the 1/2 compressing circuit 53 or 3/4 compressing circuit 54 are converted to analogue signals by this converting circuit 55 and are fed to the video processing circuit 56. Thereafter, the video signal compressed in the time axis is video-processed by this video processing circuit 56 as in the ordinary television receiver. And, has the respective color difference signals and Y signal are added to each other by using a matrix circuit 57 are and fed to an adding means 58. On the other hand, in the video processing circuit for displaying the son picture shown on the lower step, that is, the second picture, the video signal input from the two pictures video signal input terminal 59 is operated the same as in the video signal processing circuit and the digital signal of the second picture video is fed to a digital processing circuit 62 through a video processing circuit 60 and A/D converting circuit 61 and is temporarily memorized in a digital memory 63. In the digital processing circuit 62, a clock pulse is produced from a synchronizing signals, for example, of the first picture and second picture and, for example, signals are written into or read out of the digital memory 63 by the timing of this clock pulse, that is to say, they are read out by synchronizing the the video signal of the second picture with the video signal of the first picture and 1/2 compressing and are output. The output signal of the digital processing circuit 62 is converted to an analogue signal from the digital signal by a D/A converting circuit 64 and is fed to the adding means 58 through the video processing circuit 65 and RGB matrix circuit 66 the same as is mentioned above. Therefore, in case, for example, two pictures are displayed, in the first picture video processing circuit shown on the upper step, the 1/2 compressing circuit will be selected, the video signal compressed in the time axis at a 1/2 compressing rate in this 1/2 compressing circuit will be fed to the adding means 58 and, at the same time, on the other hand, the synchronization with the video signal of the first picture will lag by 1H/2 from the second picture video processing circuit shown on the lower step, the 1/2 compressed second video signal will be fed to the adding means 58, the first video signal and second video signal will be added to each other by this adding means 58, this added synthetic video signal will be driven to a CRT 67 of an aspect ratio of 16:9 and, thereby, the two pictures video shown, for example, in Fig. 6 (a) will be displayed in the CRT 67. However, in this state, as shown in Fig. 6 (a), the displayed pictures obtained by dividing this displayed picture of 16:9 into two parts, that is, the first and second pictures of an aspect ratio of 8:9 will be displayed in the picture of the CRT 67 of an aspect ratio of 16:9 and respective vertically long videos will be displayed. Therefore, when a synchronous signal is detected by the video processing circuit 51 and is adjusted by a deflecting means (not illustrated) which adjusts the vertical amplitude on the basis of this synchronous signal, the video in such state will be made a normal video, that is, the first and second displayed pictures will be of an aspect ratio of 4:3. For example, in the case, when the vertical amplitude is compressed to be 2/3 time as large, such normal two pictures display as is shown in Fig. 6 (b), that is, the first and second pictures of an aspect ratio of 4:3 will be able to be displayed in the CRT 67. However, even if the ordinary picture of an NTSC (4:3) or two pictures can be displayed in the CRT of an aspect ratio of 16:9 as mentioned above, in the conventional wide aspect television provided with a two pictures video processing circuit, there will be a disadvantage that the two pictures will be able to be displayed by only the video signal of an aspect ratio of 4:3 of the NTSC system in the current broadcast. That is to say, there will be a problem that the two pictures formed of the video signal of an aspect ratio of 4:3 of the NTSC,etc. and the video signal of an aspect ratio of 16:9 as of the hi-vision broadcast,etc. will not be able to be displayed. WO 91/19384 discloses a wide screen television apparatus including a memory which stores lines of video of an asymmetrically compressed picture, and a video signal processor for combining portions of lines of video in a first video signal with the stored lines of video of the asymmetrically, compressed picture for simultaneous display of the first and second pictures. An asymmetrically, compressed second picture is displayed without aspect ratio distortion and can form an inset within the first picture. Summary of the Invention An object of the present invention is to provide a 2-picture video processing circuit wherein a first picture of a first aspect ratio and a second picture of a second aspect ratio wider than the first aspect ratio can be simultaneously arranged and displayed in a wide aspect picture displaying part , comprising: a video signal input means including a first video signal generating means and a second video signal generating means ; a first digital converting means converting a first video signal from said first video signal generating means to a first digital signal; a second digital converting means converting a second video signal from said second video signal generating means to a second digital signal; a first compressing means which is a means wherein said first digital signal from said first digital converting means is input, is compressed in the horizontal time axis and is output, includes a series arrangement of a first compressing circuit having a first compressing rate and a second compressing circuit having a second compressing rate and can output said input digital signal compressed in at least one compressing circuit of said first and second compressing circuits; a first analogue converting means converting the compressed digital signal from said first compressing means to an analogue signal; In the formation of the present invention, in the case where a video signal of an aspect ratio, for example, of 4:3 is fed by the first video signal generating means and a video signal of an aspect ratio, for example, of 16:9 is fed by the second video signal generating means, when a mode of displaying two pictures at such aspect ratios is directed by controlling means, by using the first and second compressing circuits, the digitalized first video signal will be compressed in the time axis at a compressing rate, for example, of 3/8 and the second video signal digitalized simultaneously with it will be written into a memory and will be read out by the timing lagged in the synchronization by 3H/8 from the first picture and, by the controlling means, the video signal of the second picture will be controlled to be compressed in the time axis at a compressing rate, for example, of 5/8. Thereafter, the first compressed video signal and the second compressed video signal will be converted as analogue signals, then will be synthesized in the synthesizing circuit and then will be fed to a cathode ray tube of an aspect ratio of 16:9 so that a two pictures display may be displayed. When the vertical deflecting current fed to the cathode ray tube is controlled to control the vertical amplitude by means of the deflecting means and controlling means,the two pictures display having obtained the optimum aspect ratios of the aspect ratio of 4:3 of the first picture and the aspect ratio of 16:9 of the second picture will be able to be realized. Brief Description of the Drawings Fig. 1 is a block diagram showing an embodiment of a two pictures video processing circuit according to the present invention. Fig. 2 (a) to (c) are views showing the output displaying pictures of a CRT in case the two pictures video processing circuit shown in Fig. 1 is used. Fig. 2 (a) is a view showing the state when having compressed in the horizontal direction the picture of a video signal of an aspect ratio of 4:3 and the picture of a video signal of an aspect ratio of 16:9 respectivelyat compressing rates of 3/8 and 5/8. Fig. 2 (b) is a view showing the state when having compressed a vertical amplitude from the state of Fig. 2 (a) at a compressing rate of 1/2. Fig. 2 (c) is a view showing the state when having compressed a vertical amplitude from the state of Fig. 2 (a) at a compressing rate of 62.5%. Fig. 3 is a block diagram showing an example of a video processing circuit of a conventional wide aspect television. Fig. 4 (a) and (b) are views showing the output displaying pictures of the CRT using the video processing circuit shown in Fig. 3. Fig. 4 (a) is a view showing the state when having displayed a video signal of an aspect ratio of 4:3 to the CRT of an aspect ratio of 16:9. Fig. 4 (b) is a view showing the state when having compressed horizontally the video picture from the state of Fig. 4 (a) at a compressing rate of 3/4. Fig. 5 is a block diagram showing an example of a wide aspect television having a conventional two pictures displaying function. Fig. 6 (a) and (b) are views showing the output displaying pictures in case the picture is displayed by means of the two pictures displaying function shown in Fig. 5. Fig. 6 (a) is a view showing the state when having displayed a video signal of an aspect ratio of 4:3 to the CRT of an aspect ratio of 16:9 by means of two pictures display. Fig. 6 (b) is a view showing the state when having compressed a vertical amplitude of the video picture from the state of Fig. 6 (a) at a compressing rate of 2/3. Detailed Description of the Preferred Embodiments The embodiments shall be explained with reference to the drawings. Fig. 1 is a block diagram showing an embodiment of a two pictures video processing circuit according to the present invention. The wide aspect television of this embodiment shown in Fig. 1 is a wide aspect television having a two pictures displaying function, characterized particularly in that a video signal of an aspect ratio of 4:3 of the current broadcast and a video signal of an aspect ratio of 16:9 as of the hi-vision,etc. broadcast are used to be able to display pictures of respectively different aspect ratios in a CRT of an aspect ratio of 16:9. As shown in Fig. 1, the two pictures video processing circuit group comprises mostly a video processing circuit shown on the upper step for displaying a parent picture, that is, the first picture and a video processing circuit shown on the lower step for displaying a son picture, that is, the second picture. The video processing circuit shown on the lower step is generally a son picture video processing circuit for producing the second picture in the main first picture, compresses the second picture video signal at a predetermined compressing rate and reproduces it as synchronized with the first picture. The video processing circuit formed on the upper step is formed of substantially the same components as of the video processing circuit shown, for example, in Fig. 5. The differences are that the 1/2 compressing circuit 4 compressing in the time axis at a compressing rate of 1/2 and the 3/4 compressing circuit 5 are provided in series and the first switch SW1 and second switch SW2 switched on/off by the switching controlling signal from the controlling means 21 are connected to the respective output terminals. In the drawings, first, the first picture video processing circuit on the upper step shall be explained. The reference numeral 1 represents an input terminal in which a broadcast signal, for example, of an NTSC system is input. The video signal input from this input terminal 1 is fed to a video processing circuit 2 comprising at least a video intermediate frequency amplifier, video wave detecting circuit and synchronizing separating circuit (not illustrated), is converted to an intermediate frequency signal and is taken out. Then, this video signal is separated into a luminance signal Y (which shall be abbreviated as a Y signal hereinafter) and a chroma signal. The chroma signal is demodulated to color difference signals (R-Y, B-Y). The synchronous signal is taken out of the video signal and is fed, for example, to a deflecting means 18 adjusting the vertical amplitude of the CRT 20. This deflecting means 18 generates a vertical deflecting current responding to the switching signal fed from the vertical amplitude switching signal generating means on the basis of the synchronous signal from the video processing circuit 2 and feeds it to a deflecting yoke of the cathode ray tube 20 (which shall be mentioned as a CRT hereinafter) to adjust the vertical amplitude. Therefore, this deflecting means 18 is controlled by the controlling means 21. The Y signal and color difference signals demodulated by the video processing circuit 2 are fed to the A/D converting circuit 3. Here, the Y signal and color difference signals as analogue signals are converted to digital signals. The output signal of this A/D converting circuit 3 is fed to the time axis 1/2 compressing circuit 4 compressing the input signal at a compressing rate of 1/2. The output terminal of the A/D converting circuit 3 is in contact with the first switch SW1. The 1/2 compressing circuit 4 compresses digital signals at a compressing rate of 1/2 and is switched on/off by the switch SW1 so that the case that the output signal of the 1/2 compressing circuit 3 is output and the case that the circuit 3 is by-passed may be selected. The switch SW1 is connected to the 3/4 compressing circuit 5 compressing in the time axis at a compressing rate of 3/4 and the second switch SW2. By switching the switch SW2 on/off, the case that the output signal of the 3/4 compressing circuit 5 is output and the case that the circuit 5 is by-passed can be selected. The switch SW2 is connected to the D/A converting circuit 6 by which the input digital signal is converted to an analogue signal and is fed to the video processing circuit 7. By the way, the switches SW1 and SW2 are operated by the switching controlling signal from the controlling means 21. By using these switches SW1 and SW2, the input digital signal compressing rate can be varied, that is to say, so that a mode that the picture of an aspect ratio of 4:3 of the NTSC system is displayed by the controlling means 21, a mode that an ordinary two pictures display is made and a mode that thetwo pictures display of the picture of an aspect ratio of 4:3 and the picture of an aspect ratio of 16:9 characterized in this embodiment is made may be selected. Then, the video signal compressed in the time axis is processed in the video processing circuit 7 as in an ordinary television receiver and RGB signals are produced by adding the respective color difference signals and Y signal by means of the matrix circuit 8 and are fed to the adding means 9. On the other hand, in the video processing circuit shown on the lower step for displaying the son picture, that is, the second picture, for example, a hi-vision signal (which shall be mentioned as a MUSE signal hereinafter) by a hi-vision broadcast is demodulated by a MUSE decoder not illustrated and is input in the video signal input terminal 10. Or, a wide aspect of broadcast signal of HD-MAC or PAL Plus, etc. is demodulated and is input in the video signal input terminal 10. That is to say, the video signal of an aspect ratio of 16:9 is input in the video signal input terminal 10. By the way, in case the video of an ordinary aspect ratio of 4:3 is displayed as the second picture, naturally, a video signal of the NTSC system will be input. The video signal input from the input terminal 10 operates the same as the video signal processing circuit shown, for example, on the lower step in Fig. 5 and the digital signal of the video of the second picture is fed to the digital processing circuit 13 through the video processing circuit 11 and A/D converting circuit 12 and is temporarily memorized in the digital memory 14. A clock pulse is produced from the synchronized signal, for example, of the first picture and second picture in the digital processing circuit 13 and, for example, the digital memory 14 is written in or read out by the timing of this clock pulse. That is to say, in the case of reading out, the video signal of the second picture will be synchronized with the video signal of the first picture, in case the picture is displayed as the second picture of an ordinary NTSC, this video signal will be 1/2 compressed and, in case the video signal of 16:9 of the wide aspect broadcast is displayed as the second picture, it will be compressed at a compressing rate of 5/8 and output. By the way, this digital processing circuit 13 can easily vary the compressing rate and output the video. The variability of the compressing rate of the digital processing circuit is controlled by the controlling means 21. The output signal of the digital processing circuit 13 is converted from the digital signal to an analogue signal and is fed to the adding means 9 through the video processing circuit 16 and RGB matrix circuit 17. The first video signal and second video signal are added to each other by this adding means 9. When this added synthetic video signal is driven to the CRT 20 of an aspect ratio of 16:9, for example, the video of two pictures shown, for example, in Fig. 2 (a) will be able to be displayed in the picture. The operation of the two pictures video processing circuit of such formation shall be explained in detail in the following with reference to Fig. 2. First of all, in a wide aspect television provided with the two pictures video processing circuit in this embodiment, in case a picture of an aspect ratio of 4:3 of an ordinary NTSC system is displayed in the picture in the CRT 20, for example, of an aspect ratio of 16:9, it will be selected by using the switches SW1 and SW2 shown in Fig. 1 to compress the input video signal at a compressing rate of 3/4, that is to say, the switch SW1 will be switched off and the switch SW2 will be switched on. As a result, the input video signal will by-pass the 1/2 compressing circuit 4, will be fed to the 3/4 compressing circuit 5, will be compressed at a compressing rate of 3/4 in this 3/4 compressing circuit 5 and will be processed in the D/A converting circuit 6, video processing circuit 7 and RGB matrix circuit 9 and thereby a video of an aspect ratio of 4:3 will be able to be displayed in the picture in the CRT 20. By the way, even in this case, when the vertical amplitude is adjusted by using the deflecting means 18 the same as in the conventional art, a normal video of an aspect ratio of 4:3 will be displayed in the picture. Also, in case the two pictures display of an aspect ratio of 4:3 of an ordinary NTSC system is made, it will be selected by using the switches SW1 and SW2 shown in Fig. 1 to compress the first picture input video signal at a compressing rate of 1/2, that is to say, the switch SW1 will be switched on and the switch SW2 will be switched off. As a result, the input video signal will be fed to the 1/2 compressing circuit 4, will be compressed at a compressing rate of 1/2 in this 1/2 compressing circuit 4, will by-pass the 3/4 compressing circuit, will be processed as a signal in the D/A converting circuit 6, video processing circuit 7 and RGB matrix circuit 8 and will be fed to the adding means 9. On the other hand, a video signal of an aspect ratio of 4:3 of an ordinary NTSC system is input into the two pictures video processing circuit shown on the lower step in Fig. 1 and operates the same as in the conventional art shown in Fig. 5. That is to say, the video is made to lag by 1H/2 in the synchronization from the first picture video signal by using the digital processing circuit 13 and digital memory 14, is compressed at a compressing rate of 1/2 and is fed to the adding means 9 through the D/A converting circuit 15, video processing circuit 16 and RGB matrix circuit 17. Then, the first picture video signal and second picture video signal are added together by this adding means 9, this synthetic video signal is driven to the CRT 20 and the vertical amplitude is adjusted by means of the deflecting means 18 so that such two pictures video of a normal aspect ratio of 4:3 as is shown in Fig. 6 (b) may be displayed in the picture. Now, in case the two pictures display of the picture of an aspect ratio of 4:3 and the picture of an aspect ratio of 16:9 characterized in this embodiment is made, a video signal of an ordinary aspect ratio of 4:3 will be input into the input terminal 1 of the first picture video processing circuit on the upper step shown in Fig. 1 and a video signal of a wide aspect ratio of 16:9 will be input into the input terminal 10 of the second picture video processing circuit shown on the lower step. In the first picture video processing circuit shown on the upper step, it will be selected by using the switches SW1 and SW2 shown in Fig. 1 to compress the first picture input video signal, for example, at a compressing rate of (1/2) × (3/4)=3/8, that is to say, the switch SW1 will be switched on and the switch SW2 will be also switched on. As a result, the input video signal will be fed to the 1/2 compressing circuit 4, the video signal compressed at a compressing rate of 1/2 in this 1/2 compressing circuit 4 will be fed to the 3/4 compressing circuit 5 and the output compressed signal of the 1/2 compressing circuit 4 will be again compressed at a compressing rate of 3/4. That is to say, the input video signal will be compressed at a compressing rate of 3/8 and will be output. Then, the 3/8 compressed video signal will be processed in the D/A converter 6, video processing circuit 7 and RGB matrix circuit 8 and will be fed to the adding means 9. On the other hand, in the two pictures video processing circuit shown on the lower step in Fig. 1, the input video signal of an aspect ratio of 16:9 is processed in the video processing circuit 11, is converted to be digital by means of the A/D converting circuit 12 and is fed to the digital signal processing circuit 13. There, the video signal is made to lag in the synchronization by 3H/8 from the first picture by means of the digital processing circuit 13 and digital memory 14, is compressed at a compressing rate of 5/8 by the control of the controlling means 21 and is fed to the adding means 9 through the D/A converting circuit 15, video processing circuit 16 and RGB matrix circuit 17. Then, the first picture video signal and second picture video signal are added together by means of this adding means 9. When this synthetic video signal is driven to the CRT 20, such two pictures display as is shown, for example, in Fig. 2 (a), two pictures, for example, of the first picture 20a of an aspect ratio of 6:9 and second picture 20b of an aspect ratio of 10:9 will be able to be obtained. Therefore, while such horizontal axis ratio of 6:10 of the first picture 20a and second picture 20b as is mentioned above is held in the picture of an aspect ratio of 16:9 in the CRT 20, when the vertical amplitude is adjusted by using the deflecting means 18 on the basis of the switching signal from the vertical amplitude switching signal generating means 19 for the synchronous signal from the video processing circuit 2, the aspect ratio of the first picture 20a and second picture 20b will be obtained as the optimum aspect ratio. For example, in order that the first picture 20a may be a picture of a normal aspect ratio of 4:3 on which a video is to be displayed, the vertical amplitude by the deflecting means 18 is made 1/2. As a result, for example, as shown in Fig. 2 (b), the aspect ratio of the first picture 20a will be a normal aspect ratio of 4:3 and the aspect ratio of the second picture 20b on this step will be 16:7.2, that is, the second picture 20b will be a somewhat horizontally long picture. Also, in order that the second picture 20b may be a picture of a normal aspect ratio of 16:9 on which a video is to be displayed, the vertical amplitude by the deflecting means 18 is made 62.5%. As a result, the aspect ratio of the second picture 20b will be a normal aspect ratio of 16:9, for example, as shown in Fig. 2 (c). On the other hand, the aspect ratio of the first picture 20a on this step will be 4:3.75. That is to say, the first picture 20a will be a more or less vertically long picture. That is to say, if the vertical amplitude is adjusted, for example, by the deflecting means 18 to be 50 to 62.5%, a two pictures display having the optimum aspect ratio which the aspect ratio of the first picture approaches to 4:3 and the aspect ratio of the second picture approaches to 16:9 will be able to be made. Therefore, according to this embodiment, in order to dissolve the problems in the conventional arts, the two pictures display formed of the current broadcast signal of the aspect ratio of 4:3 and the wide aspect broadcast signal is possible. By the way, in this embodiment, as an example, it has been described that the signal obtained by demodulating the broadcast signal of the high vision broad cast by using a MUSE decoder is input into the input terminal of the second picture producing video signal processing circuit. However, the MUSE decoder may be provided within the video processing circuit of the present invention. Also, in this embodiment, it has been explained that the two pictures display is made at the respective aspect ratios by using the ordinary broadcast signal and the MUSE signal of the hi-vision broadcast. However, in the wide aspect television provided with the two pictures video processing circuit of the present invention, needless to say, this invention is not limited to the MUSE signal, other wide aspect broadcast signal than the MUSE signal can be received. It is evident that the users can select such various modes as a picture of an aspect ratio of 16:9, a picture of an aspect ratio of 4:3 and two pictures of 4:3 and 16:9 with satisfaction. Further, in this embodiment, the controlling means may be controlled to have the mode instantly changed, for example, by the key operation of a key remote controlling transmitter and may be formed so that various picture displays conforming to the objects of the users may be made. According to this invention described above, with a simple formation, signals can be processed by using the video signals of the ordinary aspect ratio and the wide aspect ratio and the respective pictures of aspect ratios of 4:3 and 16:9 can be simultaneously displayed. Thereby, in the wide aspect television provided with this two pictures video processing circuit, various picture displaying modes can be provided and videos satisfactory to the users can be supplied. It is needless to say that the present invention can be easily practised with such simple formation as is mentioned above and can obtain the effect of the low cost. By the way, the present invention is not limited to only the above described embodiments but can be variously modified and worked without deviating from the subject matter of the invention.

Claims: A 2-picture video processing circuit wherein a first picture of a first aspect ratio and a second picture of a second aspect ratio wider than the first aspect ratio can be simultaneously arranged and displayed in a wide aspect picture displaying part (20), comprising: a video signal input means (2) including a first video signal generating means and a second video signal generating means (11); a first digital converting means (3) converting a first video signal from said first video signal generating means (2) to a first digital signal; a second digital converting means (12) converting a second video signal from said second video signal generating means (11) to a second digital signal; a first compressing means which is a means wherein said first digital signal from said first digital converting means (3) is input, is compressed in the horizontal time axis and is output, includes a series arrangement of a first compressing circuit (4) having a first compressing rate and a second compressing circuit (5) having a second compressing rate and can output said input digital signal compressed in at least one compressing circuit of said first and second compressing circuits; a first analogue converting means (6) converting the compressed digital signal from said first compressing means to an analogue signal; a second compressing means (13) which is a means wherein said second digital signal from said second digital converting means (12) is input, is compressed in the horizontal time axis and is output, includes a memory (14), writes said second digital signal into the memory and reads out by a timing signal produced from a synchronized signal of said first video signal and outputs a compressed signal; a second analogue converting means (15) converting a digital signal compressed from said second compressing means (13) to an analogue signal. a synthesizing means (9) synthesizing analogue signals from said first analogue converting means (6) and second analogue converting means (15) and feeding them to said picture displaying part (20); characterised by comprising: a controlling means (21) wherein, in the case where the aspect ratio of both said first video signal and said second video signal approximate said first aspect ratio, a signal compressed in the first compressing circuit (4) will be output from said first compressing means, and in the case where said first video signal approximates the first aspect ratio and said second video signal approximates the second aspect ratio, said first compressing means will be controlled to further compress in said second compressing circuit (5) the signal compressed in said first compressing circuit (4) and output it from said first compressing means and said second compressing means will be controlled to vary the compressing rate of said second compressing means (13) in response to the aspect ratios of said first and second video signals; and a vertical amplitude variable means (19) which can vary the amplitude in the vertical direction of the picture displayed in said picture displaying part (20). A 2-picture video processing circuit according to claim 1 characterized in that, when said first aspect ratio is 4:3 and said second aspect ratio is 16:9, the compressing rate of said first compressing circuit (4) of said first compressing means will be 1/2 and the compressing rate of said second compressing circuit (5) will be 3/4. A 2-picture video processing circuit according to claim 1 characterized in that the vertical amplitude variation by said vertical amplitude variable means (19) is switched as interlocked in response to the aspect ratios of said first and second video signals. A 2-picture video processing circuit according to claim 1 wherein said first and second video generating means generate first and second picture video signals, and wherein said first video signal input means comprises a first demodulating means (2) whereby the first picture video signal from the first picture video signal generating means is demodulated to a luminance signal and color difference signals and a synchronous signal is reproduced; said first compressing circuit is a 1/2 compressing circuit (4), wherein the time axis of the horizontal direction of this digital signal is compressed at a compressing rate of 1/2, and said second compressing circuit is a 3/4 compressing circuit (5), wherein the compression is made at a compressing rate of 3/4, at least one of said compressing circuits being conducted by first and second switching switches (SW1, SW2) provided at the output terminals of these compressing circuits (4,5) to output compressed digital signals; the apparatus further comprising: a first matrix means (7, 8) whereby the first picture video signal from the first analogue converting means (6) is processed and a luminance signal and color difference signals are synthesized and are output as RGB signals; a second demodulating means (11) whereby the second picture video signal from the second picture video signal generating means is demodulated to a luminance signal and color difference signals and a synchronous signal is output; a digital processing circuit (13) wherein the digital signal from the second digital converting means (12) is input, this input digital signal is written into a memory (14) by a timing signal produced from synchronous signals respectively for the first picture and second picture, is read out by the timing corresponding to the first picture and is compressed at a predetermined compressing rate corresponding to the compressing means and the digital signal of the second picture is output; a second matrix means (16, 17) whereby the second picture video signal from the second analogue converting means (15) is processed and the luminance signal and color difference signals are synthesized and are output as RGB signals; an adding means (9) whereby the output RGB signals from the first matrix means (7, 8) and the output RGB signals from the second matrix means (16, 17) are added together and are output; a cathode ray tube (20) wherein the RGB signals output by the adding means (9) are displayed in the picture at an aspect ratio of at least 16:9; a deflecting means (18) whereby a vertical deflecting electric current is fed to the deflecting yoke of the cathode ray tube (20) on the basis of the synchronous signals from the first demodulating means (2) and the vertical amplitude can be varied by controlling the amplitude of the vertical deflecting current; and a controlling means (21) whereby the first and second switching switches (SW1, SW2) of the compressing means, the compressing rate of the digital processing circuit (13) and the vertical deflecting current of the deflecting means (18) are optionally controlled in response to a plurality of picture displaying modes displaying in the cathode ray tube (20). A 2-picture video processing circuit according to claim 4 characterized in that, in the case where a video signal of an aspect ratio of 4:3 is fed by the first picture generating means and a video signal of an aspect ratio of 16:9 is fed by the second picture generating means, the first and second switching switches (SW1, SW2) associated with first and second compressing circuits (4,5) will be switched on in response to a controlling signal from the controlling means (21), and the compressing rate of the digital processing circuit (13) will be made 5/8 A 2-picture video processing circuit according to claim 5 characterized in that, in the case where the vertical amplitude is not adjusted by the deflecting means (18), the two pictures will be displayed by dividing the horizontal dimension of the cathode ray tube in a ratio of 6:10 for displaying the first and second picture. A 2-picture video processing circuit according to claim 5 wherein, when the vertical amplitude is adjusted by the deflecting means (18), the respective aspect ratios of the first picture and second picture will be able to be adjusted to the optimum ratios. A 2-picture video processing circuit according to claim 4 characterized in that, in the case where only the video signal from the first picture video signal generating means is displayed in the picture, the controlling means (21) will switch on only the second switching switch (SW2) of the controlling means (21) such that a signal is output from the second compressing means (5).

Inventors: ABE HIROTOSHI, ABE, HIROTOSHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H04N5
IPC codes: H04N5, G09G5