SiCr THIN FILM RESISTORS HAVING IMPROVED TEMPERATURE COEFFICIENTS OF RESISTANCE AND SHEET RESISTANCE

Abstract: The temperature coefficient of resistance and sheet resistance of SiCr thin film resistors are substantially enhanced by rapidly annealing the SiCr thin film at a temperature in the range of about 550 to about 650 DEG C in a nitrogen atmosphere.

Description: SiCr THIN FILM RESISTORS HAVING IMPROVED TEMPERATURE COEFFICIENTS OF RESISTANCE AND SHEET RESISTANCE Background of th Invention 1. Field of the Invention The present invention relates to thin film resistors, and more particularly but not by way of limitation, to Silicon Chromium (SiCr) thin film resistors having improved temperature coefficients. In one aspect, the present invention relates to a process for producing SiCr thin film resistors having improved temperature coefficients of resistance and enhanced sheet resistance values. 2. Description of the Prior Art SiCr thin film resistors and processes for fabricating such resistors have heretofore been known. Generally, SiCr thin film resistors have been fabricated by forming a thin film of SiCr on a substrate utilizing a DC or rf sputtering process. The SiCr film formed on a substrate using either a DC or rf sputtering process inherently possesses a high temperature coefficient of resistance and the maximum obtainable sheet resistance for such a film is limited. Temperature coefficient of resistance is a measure of the ability of a film's sheet resistance to change the least when the temperature of the film is increased and decreased. For resistors, the temperature coefficient of resistance is determined by measuring resistance at different temperatures and thereafter computing the rate of resistance change per degree of temperature. This parameter, which is expressed in parts per million per degrees Celsius (ppm/°C) and is generally a function of the film material, film composition and deposition conditions, is extremely difficult to control and can be negative (when the resistance decreases as the temperature increases) or positive (when the resistance increases as the temperature increases). The sheet resistance of a SiCr film can be enhanced by alloying a deposited film in a nitrogen and oxygen environment. The sheet resistance of the SiCr alloy film can be increased approximately 280% by producing an alloy at a temperature of 475 degrees Celsius for 30 minutes. After the first 30 minutes of alloying, further increases in the sheet resistance of the film is dependent on the alloy temperature. However, increasing the alloy temperature for a SiCr film over 480°C in an effort to further increase the sheet resistance of the SiCr film is not desirable because the SiCr film decomposes at temperatures greater than 480 degrees Celsius and is thus destroyed. It has also been proposed to enhance the sheet resistance of a thin film by thinning of the film, that is, to deposit a thinner film on the substrate. However, when one attempts to thin down the film the quality of the film degrades and the film becomes more sensitive to downstream processing steps. SiCr resistors currently available generally possess a temperature coefficient of resistance which is too high. This renders such resistors unacceptable for many of the new circuit designs. New and improved processes for fabricating SiCr resistors can substantially lower temperature coefficients of resistance, while at the same time enhancing the sheet resistance of the SiCr film. The present invention is directed to such a process. Summary of the Invention According to the present invention, the temperature coefficient of resistance and sheet resistance of a SiCr thin film resistor is enhanced by rapidly heating the SiCr thin film at a temperature of from about 550°C to about 650°C in a nitrogen atmosphere for a period of time effective to anneal the SiCr thin film. More specifically, the temperature coefficient of resistance and sheet resistance of a SiCr resistor can be enhanced when the resistor is fabricated in accordance with the process of the present invention which includes the steps of: (a) sputtering a silicon/chrome alloy from a silicon chrome target onto a phosphorous doped low temperature silicon dioxide wafer so as to provide a SiCr thin film on the wafer; (b) rapidly heating the wafer to a temperature of from about 550 to about 650 °C in a nitrogen atmosphere for a period of time effective to anneal the SiCr thin film; (c) masking the wafer with a first resist mask so as to define resistor bar regions; (d) etching the masked wafer so as to form resistor bars in the resistor bar regions; (e) removing the first resist mask from the wafer; (f) depositing a blanket of aluminum on the wafer to cover the SiCr thin film and the resistor bars; (g) masking the wafer with a second resist mask so that the end portions of the resistor bars are mask and leads to an area in the field are defined; (h) etching the wafer so as to expose the field oxide and body portions of the resistor bars; (i) removing the second resist mask so as to provide aluminum contacts to the resistor bars; (j) heating the wafer to a temperature of about 475 °C in a hydrogen/nitrogen atmosphere for a period of time effective to alloy the SiCr and the aluminum contacts and provide a resistor; (k) passivating the alloyed wafer; (1) masking the alloyed wafer with a third resist mask to provide windows defining metal lines; and (m) removing the third resist mask so that electrical contact can be made to the resistor. An object of the present invention is to provide an improved SiCr resistor having an improved temperature coefficient of resistance and an enhanced sheet resistance. Another object of the present invention, while achieving the before-stated object, is to provide an improved process for fabricating the SiCr resistor having an improved temperature coefficient of resistance and an enhanced sheet resistance. Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the drawings and appended claims. Brief Description of the Drawing FIG. 1 is a cross-sectional representation of a portion of a SiCr resistor fabricated in accordance with the process of the present invention. Detailed Description The present invention relates to a SiCr thin film resistor having an improved temperature coefficient of resistance and enhanced sheet resistance; and to a process for fabricating a SiCr thin film resistor having an improved temperature coefficient of resistance and enhanced sheet resistance. Referring now to FIG. 1, a portion of a SiCr thin film resistor 10 constructed in accordance with the present invention is pictorially illustrated. The SiCr thin film resistor 10, which is also sometimes referred to herein simply as a resistor, comprises a phosphorous doped low temperature silicon dioxide wafer 12, a SiCr thin film 14, aluminum contacts 16 for interconnecting the resistors, a phosphorous doped oxide layer 18 and a nitride layer 20. It should be noted that the components of the resistor 10 appear to be similar to the components of a conventional SiCr thin film resistor. However, as will be shown hereinafter, the SiCr thin film resistor 10 fabricated by the process of the present invention differs from a conventional SiCr thin film resistor of the prior art in that the resistor 10 has improved characteristics as to temperamre coefficient of resistance and sheet resistance. In the fabrication of the resistor 10, a silicon substrate 22 is thermally oxidized to form a layer of silicon dioxide on an upper surface of the silicon substrate 22; a phosphorus doped low temperamre silicon film is chemically formed on the silicon dioxide layer. A silicon/chrome alloy is then sputtered from a silicon chrome target onto the phosphorous doped low temperature silicon dioxide wafer 12 so as to provide the SiCr thin film 14 on an upper surface of the phosphorous doped low temperamre silicon dioxide wafer 12. The silicon/chromium target employed in the fabrication of the SiCr thin film resistor 10 has a purity of about 99.5%; and the target has a composition of about 72% silicon and about 28% chromium, based on atomic weight. The deposition of SiCr thin film 14 on the silicon substrate 22 is carried out using a conventional DC of rf sputtering system such as Balzers LLS801 system with DC power. After the formation of the SiCr thin film 14 on the silicon substrate 22, the wafer 12 is rapidly heated from room temperatore to an annealing temperature in a nitrogen atmosphere and maintained at the annealing temperature for a period of time effective to anneal the SiCr thin film. Any suitable heat source capable of rapidly heating the wafer 12 to the desired annealing temperatore can be employed. However, desirable results have been obtained when halogen lamps are used as the heat source. In order to enable one to more fully appreciate the inventive concept disclosed herein, it is believed desirable that certain terms employed in the description of the invention be defined. Thus, the following definitions are set forth. "Rapidly heated" is the ramp up time from room temperature to the annealing temperature of the SiCr thin film and is a period of time of from about 5 to about 10 seconds. "Annealing temperatore" is the temperatore at which the SiCr thin film is annealed. The annealing temperatore for the SiCr thin film in accordance with the present invention is from about 550 to about 650°C, and more desirably about 650°C. The period of time effective to anneal the SiCr thin film 14 using the rapid thermal anneal concept of the present invention is from about 50 to 85 seconds. As will be set forth hereinafter, the rapid thermal annealing of the SiCr thin film 14 (which, including ramp up time, is from about 60 to 90 seconds) is important in the fabrication of the SiCr thin film resistors 10 of the present invention. After the rapid thermal annealing of the SiCr thin film, the wafer 12 is allowed to cool by heat dissipation. A first resist mask is then applied to the annealed SiCr thin film of the wafer 12 so as to define resistor bar regions. It should be noted that a resistor constructed in accordance with the present invention will generally include rectangularly shaped bars in which the length to width ratio of the bars is dependent upon the desired resistance of the resistor. Thus, the resistor bar regions defined by the first resist mask will conform to the shape and size of the resistor bars to be formed on the wafer 12. The wafer 12 is then etched to define the resistor bars. Any etching procedure can be employed to define the resistor bars, such as a conventional dry etching procedure. After the wafer 12 has been etched so as to define the resistor bars, the first resist mask is removed by any well known conventional procedure, such as by exposure to an oxygen plasma. After the resistor bars have been formed, a blanket of aluminum is deposited on the wafer 12 so as to cover or blanket the SiCr thin film 14 and the resistor bars. A second resist mask is then applied to selected regions of the aluminum blanketed wafer so that the end portions of the resistor bars are masked and leads to an area in the field are defined. The masking of the wafer 12 with the second resist mask defines leads to an area in the field so that electrical testing of the resistor can be carried out when the fabrication process of the resistor is completed. The aluminum blanketed wafer 12 is then etched so as to remove unmasked aluminum and thereby expose the oxide field and the body portions of the resistor bars. Any conventional wet etching procedure well known in the fabrication of wafers can be employed to remove the unmasked aluminum. However, desirable results have been obtained when a conventional aluminum wet etching process employing nitric acid and phosphoric acid is used. After wet etching of the aluminum blanketed substrate is completed, the second resist mask is removed with an oxygen plasma so as to provide leads to the area in the field and aluminum contacts on the ends of the resistor bars. After removal of the second resist mask from the wafer 12, the wafer 12 is heated to a temperatore of about 475 °C in a hydrogen/nitrogen atmosphere for a period of time effective to alloy the SiCr and the aluminum contacts and provide a resistor. The time required to alloy the SiCr and aluminum contacts can vary, but generally such alloying is accomplished in about 30 minutes. Once the alloying of the SiCr and aluminum contacts has been carried out, the wafer is passivated to protect the resistor formed thereon. Any suitable passivation technique can be employed to passivate the wafer, such as application of a phosphorous doped oxide, i.e., a vapor over metal (VOM) passivation, or a phosphorous doped oxide covered with a nitride layer. The passivated wafer 12 is then masked with a third resist mask to provide windows defining metal lines; and the masked alloyed wafer is etched to open the metal lines so that electrical contacts can be made to the resistors. The third resist mask is then removed using an oxygen plasma and the SiCr resistor prepared in accordance with the present invention was recovered and tested to determine its temperatore coefficient of resistance and sheet resistance. In order to further illustrate the present invention the following example is set forth. However, it is to be understood that the example is for illustrative purposes only and is not to be construed as limiting the scope of the present invention. Example A series of experiments were conducted to compare the characteristics of resistors formed employing conventional SiCr thin films annealing techniques (hereinafter referred to as control resistors) with resistors formed employing rapid thermal annealing techniques of the present invention. The process employed in the formation of the control and the resistors of the present invention were substantially the same except that in the preparation of the resistors of the present invention the SiCr thin films were annealed using a rapid thermal anneal procedure and the SiCr thin films of the control resistors were annealed using standard anneal procedures performed by horizontal furnaces. In the preparation of resistors using the rapid thermal annealing techniques in accordance with the present invention, a 1000 ohms/sq. SiCr thin film was deposited on the wafer and flien the rapid thermal annealing of the SiCr thin film was carried out using halogen lamps and a nitrogen environment. The SiCr thin films were subjected to rapid thermal annealing was 60 seconds, including ramp up time. The rapid thermal annealing temperatore was varied to determine what effect, if any, the temperatore had on the temperatore coefficient of resistance and the sheet resistance. The rapid thermal annealing temperatures studied were 550°C, 600°C, and 650°C. The effect of passivation of the wafers was also studied to determine what effect, if any, variations in the passivation procedures would have on the temperatore coefficient of resistance and die sheet resistance. The results of the Experiments are set forth as follows: (1) The control resistors exhibited a temperature coefficient of resistance of 43 to -210 ppm/°C over a temperatore range of -60°C to 130°C and a sheet resistance of 980 ohms/sq. (2) The control resistors prepared by employing the passivation technique using phosphorous doped oxide (VOM) exhibited a temperatore coefficient of resistance of 9 to -231 and a sheet resistance of 1000 Ω / □. (3) The resistors prepared in accordance witii the process of the present invention wherein the rapid thermal annealing temperatore was 550°C and the passivation technique employed was phosphorous doped oxide (VOM) exhibited a temperatore coefficient of resistance of -5 to -191 ppm/°C over a temperatore range of -60°C to 130°C and a sheet resistance of 990 ohms/sq. (4) The resistors prepared in accordance with the process of the present invention wherein the rapid thermal annealing temperatore was 550°C and the passivation technique employed was phosphorous doped oxide (VOM) covered with a nitride layer exhibited a temperatore coefficient of resistance of -41 to -250 ppm/°C over a temperatore range of -60°C to 130°C and a sheet resistance of 1060 ohms/sq. (5) The resistors prepared in accordance with the process of the present invention wherein the rapid ti ermal annealing temperatore was 600 °C and the passivation technique employed was phosphorous doped oxide (VOM) exhibited a temperatore coefficient of resistance of 19 to -140°C over a temperatore range of -60°C to 130°C and a sheet resistance of 1090 ohms/sq. (6) The resistors prepared in accordance with the process of the present invention wherein the rapid thermal annealing temperature was 600 °C and the passivation technique employed was phosphorous doped oxide covered with a nitride layer exhibited a temperatore coefficient of resistance of 23 to -137 ppm/°C over a temperatore range of -60 °C to 130°C and a sheet resistance of 1090 ohms/sq. (7) The resistors prepared in accordance with the process of the present invention wherein the rapid thermal annealing temperatore was 650°C and the passivation technique employed was phosphorous doped oxide (VOM) exhibited a temperature coefficient of resistance of 82 to -48 ppm/°C over a temperatore range of -60°C to 130°C and a sheet resistance of 1410 ohms/sq. (8) The resistors prepared in accordance with the process of the present invention wherein the rapid thermal annealing temperatore was 650 °C and the passivation technique employed was phosphorous doped oxide covered with a nitride layer exhibited a temperatore coefficient of resistance of 54 to -43 °C over a temperatore range of -60°C to 130°C and a sheet resistance of 1450 ohms/sq. The above data clearly indicate tiiat resistors prepared in accordance with the process of the present invention exhibit improved temperatore coefficients of resistance and sheet resistance when compared with resistors prepared using conventional annealing techniques. That is, the data obtained from the experiments set forth above clearly indicate: (a) the temperatore coefficients of resistance for the control resistors start in the positive regime and move the negative regime as the temperatore is increased; (b) the temperature coefficients of resistance for the resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 550 °C start in the negative regime and remain in the negative regime as the temperatore is increased; (c) die temperatore coefficients of resistance for the resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 600 °C start in the positive regime and go to -130 as the temperature is increased; (d) the temperature coefficients of resistance for the resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 650 °C start in the positive regime and go to below -50 as the temperatore is increased; (e) with the exception of the resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 600 °C, the wafers passivated with phosphorous doped oxide covered with a nitride layer exhibit lower starting temperatore coefficients of resistance, and rapid thermal annealing of the SiCr thin films improves the temperatore coefficients of resistance for wafer passivated with either phosphorous doped oxide or a phosphorous doped oxide covered with a nitride layer; (f) the most desirable results as to temperatore coefficients of resistance are obtained wherein the resistors are prepared using a rapid thermal annealing temperatore of 650°C; (g) the average temperatore coefficients of resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 600 °C are negative in the range from -30°C to 130°C while having lower absolute values than the prior art. Note that this implies the resistance value may be monotonically increasing or montonically increasing; (h) the average temperatore coefficients of resistors prepared in accordance with the process of the present invention at a rapid thermal annealing temperatore of 650°C are in the range from 28 ρρm/°C to -31 ppm/°C from -30°C to 90°C; (i) the average temperatore coefficient of resistors prepared in accordance with the process of the present invention at a rapid tiiermal annealing temperature of 650 °C measured from 25 °C to 60°C is -1.0 ppm/°C, although with a standard deviation of 5.7 ppm/°C; and (j) the greatest enhanced sheet resistance and the greatest enhanced temperatore coefficients of resistance both occur at the same rapid thermal annealing temperatore of 650°C. Among other things, this implies that larger resistors than currently possible with the present art may be made with lower temperatore coefficients than are possible with the present art. It is clear that the present invention is well adapted to carry out the objects and attain the ends and advantages mentioned herein. While presently preferred embodiments of the invention have been described for purposes of this disclosure, numerous changes may be made which will readily suggest themselves to those skilled in me art and which are encompassed within the spirit of the invention disclosed and as defined in the appended claims.

Claims: What is claimed is: 1. A process for enhancing the temperature coefficient of resistance and sheet resistance of a resistor having a thin film of SiCr deposited on a silicon wafer, the process comprising: rapidly annealing the SiCr thin film at a temperatore of from about 550 to about 650°C in a nitrogen atmosphere for a period of time effective to anneal the SiCr thin film. 2. The process of claim 1 wherein the thin film of SiCr is deposited on the wafer by sputtering a silicon/chrome alloy from a silicon chrome target onto the wafer, the wafer is a phosphorous doped low temperatore silicon dioxide wafer, and the period of time effective to anneal the SiCr thin film is from about 50 to about 85 seconds. 3. The process of claim 2 wherein the period of time effective to anneal the SiCr thin film includes a ramp up time from room temperature to the annealing temperatore of from about 5 to about 10 seconds. 4. The process of claim 3 wherein the annealing temperatore is about 650 °C and the annealing period, including ramp up time, is about 60 seconds. 5. A process for enhancing the temperatore coefficient of resistance and sheet resistance of SiCr thin film resistors, the process comprising the steps of: (a) sputtering a silicon/chrome alloy from a silicone/chrome target onto a phosphorous doped low temperatore silicon dioxide wafer so as to provide a SiCr thin film on the wafer; (b) rapidly heating the wafer to a temperature of from about 550 to about 650°C in a nitrogen atmosphere for a period of time to anneal the SiCr thin film; (c) masking the wafer with a first resist mask so as to define resistor bar regions; (d) etching the masked wafer so as to form resistor bars in the resistor bar regions; (e) removing the first resist mask from the wafer; (f) depositing a blanket of aluminum on the wafer to cover the SiCr thin film and the resistor bars; (g) masking the wafer with a second resist mask so that the end portions of the resistor bars are masked and leads to an area in the field are defined; (h) etching the wafer so as to expose the field oxide and body portions of resistor bars; (i) removing the second resist mask so as to provide aluminum contacts to the resistor bars; (j) heating the wafer to a temperatore of about 475 °C in a hydrogen/nitrogen atmosphere for a period of time effective to alloy the SiCr and the aluminum contacts and provide a resistor; (k) passivating the alloyed wafer; (1) masking the alloyed wafer with a third resist mask to provide windows defining metal lines; and (m) removing the third resist mask. 6. The process of claim 5 wherein the period of time effective to anneal the SiCr thin film is from about 50 to about 85 seconds. 7. The process of claim 6 wherein the period of time effective to anneal the SiCr thin film includes a ramp up time from room temperatore to the annealing temperature of from about 5 to about 10 seconds. 8. The process of claim 7 wherein the annealing temperatore is about 650°C and the annealing period, including ramp up time, is about 60 seconds. 9. The process of claim 5 wherein the silicon/chromium target has a purity of about 99.5%, and the target has a composition of about 72% silicon and about 28% chromium, based on atomic weight. 10. The process of claim 9 wherein the period of time effective to anneal the SiCr thin film is from about 50 to about 85 seconds. 11. The process of claim 10 wherein the period of time effective to anneal the SiCr thin film includes a ramp up time from room temperatore to the annealing temperatore of from about 5 to about 10 seconds. 12. The process of claim 11 wherein the annealing temperatore is about 650°C and the annealing period, including ramp up time, is about 60 seconds.

Inventors: MAGHSOUDNIA PIROUZ, MAGHSOUDNIA, PIROUZ
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1994
Main classification: H01C7
IPC codes: H01C7, H01L21