SEMICONDUCTOR STRUCTURE, AND METHOD OF MANUFACTURING SAME

Abstract: A semiconductor structure (10) comprises a layer of semiconducting material (106) having first and second opposing surfaces (108, 110), an electrical device (116) at least a portion of which is adjacent the first surface (108), and an isolating barrier (112) for the electrical device extending through the semiconducting material towards the second surface (110), there being an isolating region (118) to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium. A method of fabricating the semiconductor structure is also disclosed, as well as an alternative embodiment of structure.

Description: SEMICONDUCTOR STRUCTURE. AND METHOD OF MANUFACTURING SAME This Invention relates to semiconductor structures in general, and more particularly to such a structure incorporating electrical devices such as Complementary Metal Oxide Silicon ( CMOS) transistors in which each device 1s electrically isolated from other such devices. The invention also relates to a method of manufacturing such a structure. Semiconductor structures incorporating electrical devices ( integrated circuits) are of course very well known. Such structures typically comprise an epitaxial layer of Silicon covering a substrate of bulk Silicon, with a number of electrical devices formed adjacent the upper surface of the epitaxial layer. These structures can suffer from the very significant problem of electrical latch-up caused by the activation of various paras1tics 1n the structure, typically those between the electrical devices themselves and those between each electrical device and the bulk Silicon substrate. For Very Large Scale Integrated (VLSI) circuits, latch-up can give rise to catastrophic failure. This problem has been solved by so-called Silicon-On- Insulator (SOI) technology, a useful overview of which 1s given in the IEEE Circuits and Devices Magazine, Vol. 3, Nos. 4 and 6 (July and November 1987). As described in these articles, various SOI techniques have been developed, such as the Si11con-On-Sapphire (SOS), Separation by Implanted Oxygen (SIMOX) and the Wafer Bonding techniques, the common feature to all these techniques being the formation of the electrical devices in a Silicon layer located above an insulating layer. Referring now more particularly to the Wafer Bonding technique, this technique is described, for example, in the paper by Maszara, W.P. entitled "Silicon-On-Insulator by Wafer Bonding: A Review" (J. Electrochem. Soc, Vol. 138, No. 1, 1991). Basically, the technique comprises forming a Silicon dioxide isolating layer on a Silicon substrate, preparing a separate single-crystal Silicon wafer, and then bonding the wafer to the substrate. The wafer is then ground down using a precision- controlled lapping machine from an initial thickness of perhaps 500 μ to an ultimate thickness of possibly only 1 or 2 μ . The electrical devices are formed in this 1 or 2 μm thick single- crystal Silicon semiconductor layer. Whilst the basic Wafer Bonding technique as described above provides electrical isolation beneath the electrical devices (between each device and the Silicon substrate), it does not provide isolation between the electrical devices themselves. An article by Watanabe, . e_t ___.. entitled "A Bonded-SOI Bipolar Process Technology" (Proc. 1st Symposium on Silicon Wafer Bonding, Electrochemical Society, U.S.A., 1991, p. 443) provides the solution to this problem In the form of shallow isolating grooves extending from the top surface of the semiconductor layer through to the Silicon dioxide Isolating layer, thus forming a semiconductor island which is completely isolated from other such islands (except possibly for purpose-built electrical connections). US-A-4070230 and US-A-4072982 describe techniques which use an etch stop and require a support. Wide isolation channels are formed and this gives rise to an imprecise etch stop. Furthermore p-n junction isolation is used. The present invention allows an isolated layer to be fabricated, which can be very much thinner than the layers described in either of the aforementioned US Patents. Sub-micron isolation is possible with low leakage dielectrics. In both the aforementioned US Patents a polyi ide layer on top of the metallization, serves as a support so that back etching can be performed. No dielectric isolation between the "plate like" semiconductor islands is achieved, which is one of the advantageous features of the present invention. Selective etching of the n+ provides only limited selectivity between n+ and n etching. Thin uniform layers cannot be obtained by this technique over a substantial area of a slice and it is almost impossible to obtain sub-micron thick layers using either technique, in contrast to the present invention. Patent Abstracts of Japan Vol 8 No. 176 (E-260) (1613) 14th August 1984 describes a technique of selective etching of an n+ layer. This does not provide enough selectivity to form thin isolation layers between devices by diffusion. However, in the present invention precise etch stop, with very high selectivity is used; as is dielectric isolation. Whilst the Wafer Bonding technique has achieved some commercial success, it suffers from the drawbacks firstly that the precision lapping required to reduce the wafer from, say, 500 to lμm is a complex, difficult and expensive task, and secondly that the bond between the substrate and wafer is difficult to make and may not be perfect. Bonding needs to be carried out in exceptionally clean and contaminant free conditions in order to avoid voids and unbonded areas. Such conditions can be expensive and difficult to maintain. An alternative technique for forming completely dielectrically isolated islands of semiconductor material is disclosed in a PhD. thesis by Barth, P.W. entitled "Dielectric Isolation Technology for Bipolar and MOS Integrated Circuits" (Stanford University, Stanford, CA, March 1980). Barth's work is in turn discussed in a review paper by Lee, .C., entitled "The Fabrication of Thin, Freestanding, Single-Crystal, Semiconductor Membranes" (J. Electrochem. Soc, Vol. 137, No. 8, August 1990). Barth proposes the use of a preferential etching technique commonly used in the fabrication of thin semiconductor membranes to fabricate a device comprising, in sequence, a Poly-Si 1 ^ con substrate, a layer of Silicon dioxide, and a layer of eoitaxially grown single-crystal Silicon. The epitaxial layer is processed by preferential etching of a starting material comprising a heavily doped Silicon wafer and the lightly doped epitaxial layer, thus leaving the epitaxial layer. Complete dielectric isolation is afforded by layers of Silicon dioxide extending from the main Silicon dioxide layer upwardly and outwardly to the upper surface of the epitaxial layer. The technique proposed by Barth suffers from the drawbacks that it is complicated and time consuming (many process steps being involved) and that it is a necessary feature of the technique that the epitaxial layer is doped throughout its entire thickness, which may be problematical for certain applications, especially those involving CMOS devices. Furthermore, the preferential etching technique employed 1s not sufficiently selective to provide thin epitaxial layers. The present invention seeks to overcome the problems both of the Wafer Bonding and of the Barth techniques. According to the present invention, there is provided a semiconductor structure comprising a layer of semiconducting material having first and second opposing surfaces, an electrical device at least a portion of which is adjacent the first surface, and an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, there being an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium. As used herein, the term "surface" includes both external surfaces (faces ) of the structure and also internal surfaces (boundaries between different portions of the structure). As an example, the second surface may be at the boundary between the semiconducting material and a layer of insulating material. The term "electrical device" includes any kind of active or passive device, including a simple strip of conductor. The term "region" may refer, for instance, both to a two-dimensional area and to a three-dimensional portion of the structure (one having finite thickness) . By providing an isolating barrier for the electrical device extending to an isolating region, the structure of the present invention can provide complete electrical isolation for the electrical device. Furthermore, since the isolating region of the present Invention is in direct contact with the ambient medium, manufacturing of the structure can be greatly simplified. Either isolation can be provided in the isolating region by the ambient medium itself, thus completely obviating the need for any insulating material, or else any insulating material which is applied in this region can be applied at a late stage of manufacture, when it need not interfere with the other manufacturing steps. It appears from an analysis of the Wafer Bonding and Barth techniques which has been carried out pursuant to the present invention that the manufacturing complexity of these techniques is caused at least partly by the requirement that the insulating material is sandwiched between other layers in the structure. This in turn requires that the insulating material be introduced at a comparatively early stage in the manufacturing process. An additional advantage of the present invention is that it can obviate the need to carry out any removal of semiconducting material from above the structure to form the first surface, adjacent which the electrical device is fabricated. Such removal in the known techniques is necessary to the formation of a thin, isolated layer of semiconducting material, but is, however, disadvantageous. In the Wafer Bonding technique, the removal is effected by a precision lapping process, whose disadvantages have already been discussed. In the Barth technique, the removal is effected by selective etching up to a doped epitaxial layer. As discussed previously, doping of the epitaxial layer can cause problems, and the selective etching technique is in any case not sufficiently selective to provide a suitably thin epitaxial layer. The present invention can obviate such problems by allowing that any removal which may be necessary to the formatio of a thin, isolated layer of semiconducting material can be carried out underneath the structure, usually up to or adjacent the second surface. This is rendered possible by having the isolating region in direct contact with the ambient medium. rather than internal to the structure (which latter would effectively prevent processing of the structure from underneath). The isolating barrier suitably takes the form of one or more possibly criss-crossing, isolating trenches of considerable depth (typically more than 5 μm) and preferably extending right from the first surface to the second surface. The isolating barrier may extend directly to the ambient medium (which would often be air), so that the electrical device may be isolated from neighbouring devices by a combination of the barrier and the ambient medium. Alternatively, the barrier may extend to a layer of electrically insulating material in the isolating region, so that the electrical device may be isolated from neighbouring devices by a combination of the barrier, the insulating material and, beyond that, the ambient medium. The insulating material suitably has a very high resistivity (above, and preferably one or indeed many (for example, 5 or 10) orders of magnitude above, that of pure undoped single or poly- crystalline Silicon). The insulating material preferably has a chemical formula which is related to that of a semiconductor material, and is more preferably a compound of, even more preferably an oxide or nitride of, Silicon. Most preferably, it is Silicon dioxide or Silicon nitride. Particularly if the layer of insulating material is formed from a compound of Silicon and the layer of semiconducting material is formed from Silicon, this can render the manufacturing process cheaper and simpler than if the isolating material were a material such as Sapphire (as is the case in the known Silicon-on-Sapphire (SOS) technique). It can also obviate the problems encountered using the SOS technique of crystal imperfections arising in the Silicon due tc incompatibilities between the crystal structures of the two materials and of a mismatch between their thermal expansion coefficients. Thus a related preferred feature of the invention is that the semiconducting material is substantially free from crystallographic defects, for optimal performance of the electrical device. By way of contrast, in the known Silicon-On-Sapphire (SOS) technique the semiconducting layer, which is grown epitaxially from the Sapphire substrate, is replete with crystallographic defects due to the poor lattice match between the Sapphire and Silicon crystals, and thus affords relatively poor electrical performance. Preferably, the thickness of any material in the isolating region beyond the layer of semiconducting material is less than the thickness of the layer of semiconducting material, more preferably less than half the thickness of the layer of semiconducting material. It will be appreciated that usually either such material will be insulating material in direct contact with the ambient medium, or else no material will be present at all, only the ambient medium. By only having a small amount of material beyond the layer of semiconducting material, the structure can be fabricated as a thin membrane and access to the rear of the structure can be afforded. This offers several concomitant advantages. Firstly, the structure can easily be cooled by one of several means such as conduits bearing coolant. This can be particularly important if the structure constitutes a VLSI circuit for use in, for example, a supercomputer. Cooling can be particularly effective because the structure can have minimal thermal resistance due to its small thickness. A corollary of this, secondly, is that because of the minimal thermal resistance of the structure it can be used as a thermally sensitive device. Thirdly, a further related advantage is that the structure can be fabricated sufficiently thin to be largely stress-relieved. Thicker structures may suffer from high internal stresses. Fourthly, the structure can be sufficiently thin that it can be used as a force, pressure, acceleration or radiation sensitive device, optionally with a CMOS circuit actually on the diaphragm. Fifthly, the structure could be rendered photo- or electro-luminescent by forming a light emitter on the back (second) surface of the semiconductor layer. Sixthly, an important advantage (especially if the structure as a whole is relatively thin, for example less than 10 μm) , is that the electrical device or devices on the structure can be optically addressed from the rear, via the second surface. Such addressing could, for instance, be utilised for controlling the electrical device. Finally, since the structure can be fabricated as a relatively thin membrane, it can be rendered resistant to radiation. If the electrical device is located on a relatively thin portion of the structure (that is, on a thin membrane), the structure preferably includes a relatively thick portion supporting the relatively thin portion. In one preferred embodiment, the relatively thick portion supports the relatively thin portion around substantially its entire periphery. This embodiment can be appropriate for a fabrication process in which back-etching is employed for forming the thin membrane. In an alternative preferred embodiment, the relatively thin portion is elongate and is supported by the relatively thick portion adjacent at least one of its ends. This embodiment can be appropriate for a fabrication process in which the thin membrane is etched from in front, by etching around the sides of the thin, elongate portion and then under-cutting it. Front etching can be advantageous over back etching fcr the following reasons. Firstly, back etching reαuires r-ec.se back-alignment of the etch mask. This requires an inf-a-rec viewer to observe and align the mask on the back surface in relation to the pattern on the front surface, which can be difficult and time-consuming. Secondly, typically back etching requires the removal of relatively large amounts of material (typically a depth of 500μm may need to be removed). This can be very time consuming. Front etching, by contrast, requires the removal of only relatively small amounts of material (typically a depth of less than 30μm). Front etching can also provide a more robust structure than can be provided by back etching. The thin, elongate portion may be supported adjacent both of its ends, in which case it forms a beam, or it may be supported adjacent only one of its ends, in which case it forms a cantilever. The cantilever can be used, for example, for stress or acceleration sensing. If front etching is employed, preferably at least one cavity is formed in the semiconductor structure extending from the first surface to the second surface. This cavity will have been employed to afford the etchant access to undercut the second surface. Preferably, the semiconductor structure includes a layer of etch stop material adjacent the second surface. The advantages of this etch stop layer will become apparent from the ensuing description of the manufacturing method. Whilst the electrical device may take many forms, it is preferably a CMOS device. Usually several thousands or even hundreds of thousands of such devices would be provided, each with its own isolating barrier. The invention extends to a method of manufacturing a semiconductor structure, comprising providing a layer of semiconducting material having first and second opposing surfaces, fabricating an electrical device, at least a portion of the device being adjacent the first surface, providing an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, and Dro icir.c an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium. It will be appreciated that the method steps may take place in any appropriate order. For example, the* provision of semiconducting material in the form of a layer having the aforementioned first and second surfaces may (and in the preferred embodiment does) take place after the fabrication of the electrical device. In putting the invention into practice, a member incorporating the semiconducting material is preferably provided, and a portion of this member removed to form the second surface. This enables a layer of thin and electrically good quality semiconducting material to be produced, without the problems of the Wafer Bonding and Barth techniques associated with removal of material to form the first surface being encountered. In one preferred embodiment, the portion is removed from beyond the second surface towards the second surface. Thus the removal is suitably by back-etching. In another preferred embodiment, the portion is removed progressing from a region of the first surface towards the second surface and then progressing behind the second surface so as to undercut the second surface. Thus here the removal is suitably by front-etching. The region may be defined by a boundary arrangement (suitably an etch boundary arrangement) extending from the first surface to the second surface. If the barrier extends to a layer of electrically insulating material in the isolating region, this layer is preferably provided subsequent to the removal step. Providing the layer of insulating material after the removal step (and hence at a relatively late stage in the manufacturing process) can considerably simplify manufacture, as suggested previously. If the above removal step is employed, the isolating barrier is preferably provided before the removal step, whilst the member is in its thicker and hence stronger and more stable state. This can be an important feature in assuring the structural integrity of the final semiconductor structure. Again, to avoid damaging the structure, the electrical device may be fabricated before the removal step. To help prevent environmental contamination, the second surface may be passivated subsequent to the removal step. This passivated surface may then be in direct contact with the ambient medium, or may be covered with a further layer of insulating material itself in direct contact with the ambient medium. The portion of the member may be removed to form the second surface by a low damage lapping technique such as chemical-mechanical (Syton - trade mark) polishing. However, for manufacturing simplicity and economy, and to provide a semiconducting layer of relatively uniform thickness, the portion is preferably removed either by etching alone, or by a combination first of lapping and then of etching. The etching is preferably effected up to an etch stop layer defining the second surface, again for manufacturing simplicity. In the preferred embodiment, the step of providing a layer of semiconducting material includes providing a substrate, forming an etch stop layer on a surface of the substrate, and covering (preferably by epitaxy) the etch stop layer with semiconducting material. This technique can be utilised to provide good quality semiconducting material on which the electrical device may be fabricated. Preferably, at least a portion of the layer of semiconducting material is grown epitaxially from a substrate to which the epitaxially grown material is lattice-matched; more preferably, the material of the epitaxially grown portion is substantially the same as that from which the substrate is formed. By this arrangement, the portion of semiconducting material can have good electrical properties. By contrast, in the known Silicon-On- Sapphire (SOS) technique, lattice mis-match between the Silicon and the Sapphire can produce serious crystallographic defects which can impair the electrical properties of the Silicon. All the features of the semiconductor structure ma be applied in analogous fashion to the method of manufacturing that structure, and vice versa. Preferred features of the invention are now described, by way of example, with reference to the accompanying drawings, in which: Figures 1 are schematic diagrams showing the stages of production of a semiconductor structure according to the present invention; Figures 2 are similar schematic diagrams illustrating a specific process for producing the semiconductor structure; Figure 3 is a schematic perspective view of an alternative embodiment of semiconductor structure according to the present invention; and Figures 4 are schematic diagrams showing the stages of production of the alternative embodiment of semiconductor structure. The stages of production of a semiconductor structure 10 are first illustrated in general with reference to Figures 1. Referring to Figure 1(a), the production process commences with the diffusion of a Boron etch stop layer 100 into the surface of a single crystal Silicon slice 102. The stop layer in this embodiment is between 0.5 and 1 μm thick, but may be as thick as 2μm. The Silicon slice has a <100> crystal orientation, and may be either p- or n- type. As an alternative to diffusion, the etch stop layer 100 may be grown epitaxially on the Silicon slice 102. Next (see Figure Kb)) an epitaxial layer 104 of single crystal Silicon is grown on top of the Boron etch stop layer 100 using a Chemical Vapour Deposition (CVD) technique. The epitaxial layer is undoped. Autodoping from the etch stop layer is restricted by growing the epitaxial layer at low temperature (800°C) and low pressure (in the millitorr range), and by keeping the doping to within well controlled limits. This can provide an epitaxial layer which is substantially free from crystal lographic defects, while providing the necessary etch stoD characteristics. The epitaxial layer is typically about 2μm thick, but may be, for example, as thin as 0.5μm, or indeed thicker than 3μm, depending upon requirements. The stop layer 100 and epitaxial layer 104 together form a semiconductor layer 106 having an upper surface 108 and a lower surface 110 defined by the lower extent of the stop layer 100. It will be appreciated that the term "surface" is used to include reference to any internal surface (or boundary) of the structure. Next (see Figure 1(c)) isolating trenches 112 are etched in the structure using a Chlorine chemistry anisotropic plasma etching technique. Other techniques, possibly involving Chlorine and Silicon tetrachloride in a Nitrogen plasma, are also feasible. The trenches 112 are refilled with successive layers of low temperature Silicon dioxide, Poly-SiHcon and Silicon nitride so as to form an electrically insulating barrier. The quality of the refilling needs to be good since the strength of the eventual structure depends on it. The trenches 112 extend downwardly from the upper surface 108 of the semiconductor layer 106 through the stop layer 100 and the lower surface 110 and project downwardly somewhat from this surface. Thus the trenches are typically 3.5μm deep. To avoid using up space on the semiconductor layer, and to avoid weakening the structure excessively, the trenches are as thin as possible (about 1 to 2 μ ). They are etched in a criss-cross pattern to form islands 114 of semiconductor material completely encircled by the isolating trenches. Only some of the trenches are apparent in Figures 1 (which are cross- sectional views of the structure). During refilling of the trenches, material is deposited on the upper surface 108. This is removed by etching. Next (see Figure 1(d)) Complementary Metal Oxide Silicon (CMOS) devices 116 are fabricated in the islands 114, individual components of each device being formed at or near the upper surface 108 and also possibly further down in each island "■ , & . The CMOS devices may be of an suitable type: indeed, otne * " electrical devices may be fabricated to suit requirements. SJCP devices may, for example, be other types of transistors, resistive devices to sense pressure or strain in the semiconductor structure, or thermally sensitive devices. If CMOS devices are fabricated, they may be alternately p- and n- channel devices in alternate islands. As discussed later, the present invention can ensure that these devices are electrically isolated from each other. Next, a protective coating 115 is formed on top of the CMOS devices 116. The coating is made of Low Temperature (200 to 350 β C) plasma enhanced Silicon Oxide. A low temperature is chosen in order to prevent heat damage to the CMOS devices and metallisation. Finally (see Figure 1(e)), using double sided alignment the semiconductor structure 10 is back-etched up to the Boron etch stop layer 100 using a Potassium hydroxide (KOH) wet etch or any suitable anisotropic etch such that the etch stops at the stop layer. The exposed etch stop layer is then back surface passivated by depositing an insulating layer 117 of Silicon dioxide or Silicon dioxide plus nitride. This gives the lower surface 110 of the semiconductor layer 106 immunity against environmental attack. Although the insulating layer 117 could be grown, it is usually deposited at low temperature in order to avoid degradation of the electrical device. Hence an isolating region 118 is provided beneath the lower surface 110 at an external boundary of the semiconductor structure which is free from any conducting or semiconducting material (although it will be understood that there may be other regions beneath the lower surface which may contain electrical components or perhaps conducting strips connecting adjacent islands). Thus the islands 114 are generally completely isolated from each other, first by the isolating trenches 112 and secondly by a combination of the insulating layer 117 and the non-conducting ambient medium (usually air). The areas 120 of the structure 10, peripheral of the isolating region 118, which have not been etched are used ^or bonding the structure to a header (not shown). Circuit bond pads 122 are located on the upper surface 108 of the thicker periphery of the semiconductor layer 106. Cooling channels 124 for conveying coolant to the structure are formed in the peripheral areas 120. It will be understood that a number of alternative cooling means may be employed. For example, metallic (for instance lead) columnar or nodal cooling fins may be deposited on the back of the structure, care being taken to ensure that the electric isolation of the islands is not impaired. As another example, a dendritic coating of a noble metal might be employed, or Silicon could be anodised to form a porous layer on the back of the structure. It can be seen from Figure 1(e) that the semiconductor structure 10 in its eventual form constitutes a Silicon chip Integrated circuit having electrical devices formed on a thin (roughly 3.5μm) Silicon membrane. Whilst Figures 1 show schematically only a small number of electrical devices, the invention would typically be used to form VLSI circuits comprising many thousands or hundreds of thousands of electrical devices. A specific process for producing the semiconductor structure 10 is now described with reference to Figures 2. In these figures, like parts to those in Figures 1 are designated by like reference numerals, except that the reference numerals begin with the digit "2" instead of the digit "1". The process steps are as follows:- 1. (Figure 2(a)) Provide a single-crystal Silicon slice 202. 2. (Figure 2(a)) Deposit a Boron etch stop layer 200 at a temperature of 1150°C for 3 hours. 3. (Figure 2(a)) Deglaze the structure in buffered hydrofluoric acid for 30 minutes. 4. (Figure 2(b)) Form a p-type epitaxial layer 204 of 2μm thickness and having a resistivity of 3 ohm.cm. 5. (Figure 2(b)) Deposit a protective coating 205 of Low Temperature Silicon Oxide (LT0) on both surfaces of the structure to a thickness of 600 nm. 6. (Figure 2(b)) Density the protective coating 205 at 900°C in wet oxygen for 30 minutes. 7. (Figure 2(b)) Photodefine a trench etch mask in the protective coating 205. 8. (Figure 2(b)) Reactive ion etch the protective coating 205 to form channels 207. 9. (Figure 2(c)) Etch isolating trenches 212 in Silicon to a depth of 3.5μm, anisotropically, (for example, by using a Chlorine chemistry anlsotropic plasma etching technique). 10. (Figure 2(d)) Grow a pad of Silicon dioxide 40nm thick in the bottom and sides of the trenches 212. 11. (Figure 2(d)) Deposit Silicon nitride to a thickness of 160nm in the bottom and sides of the trenches 212 on top of the Silicon dioxide (note that the Silicon dioxide forms a buffer between the Silicon and the Silicon nitride to prevent cracking). 12. (Figure 2(d)) Fill the trenches 212 with Low Temperature Oxide and/or Poly-Silicon (in either order). 13. (Figure 2(e)) Spin thick photoresist on the upper surface 208. 14. (Figure 2(e)) Etch back the upper surface layers to expose the original epitaxial layer 204 (note that steps 13 and 14 serve to planarise the upper surface 208 of the epitaxial layer 204). 15. (Figure 2(e)) Fabricate CMOS circuits (not shown for clarity), and coat with a protective coating 215 of plasma enhanced Low Temperature Silicon Oxide deposited at 350°C. 16. (Figure 2(e)) Backlap to semiconductor structure 10 from back surface 211 by mechanical means to a given thickness. 17. (Figure 2(e)) Syton (trade mark) polish the back surface 211. 18. (Figure 2(e)) Clean in fuming nitric acid. 19. (Figure 2(e)) Deposit a Silicon nitride layer 219a 160nm thick. 20. (Figure 2(e)) Deposit a Low Temperature Silicon Oxide layer 219b lμm thick on the layer 219a. 21. (Figure 2(e)) Form a back-etch mask on the back surface 211 aligned to the patterns on the upper surface 208. 22. (Figure 2(e)) Protect the upper surface 208 with thick photoresist. 23. (Figure 2(e)) Selectively etch the Low Temperature Silicon Oxide layer 219b on the back surface 211. 24. (Figure 2(e)) Selectively etch the Silicon nitride layer 219a on the back surface 211. 25. (Figure 2(f)) Anisotropically etch the Silicon slice 202 from the back surface 211, stopping at the Boron etch stop layer 200, using a 40% aqueous solution of Potassium Hydroxide at 78°C. 26. (Figure 2(f)) Deposit a Silicon nitride layer 217 on the back surface 211 for passlvating; deposit at low temperature, using plasma enhanced deposition. 27. (Figure 2(f)) Strip the protective coating 215 of Low Temperature Silicon Oxide on the upper surface 208 where appropriate to expose bonding pads. 28. Probe and bond good devices. It will be appreciated that the foregoing process is employed for the mass production of complete electrical components. During the process, it may be necessary to incorporate various testing steps, to ensure that the quality of the structure is sufficiently high. An alternative embodiment of semiconductor structure according to the invention is now described with reference to Figures 3 and 4. Again, in these figures, like parts to those in Figures 1 are designated by like reference numerals, except that the reference numerals begin with the digit "3" instead of the digit "1". Referring first in particular to Figure 3, the alternative embodiment of semiconductor structure comprises generally a Silicon slice 302 made of <100> oriented Silicon, there being a hollow 303 formed in the top of the slice, and three beams 307 of semiconductor material spanning the hollow and constituting the semiconductor layer 306. Because the beams 307 are supported at both ends, they can be made thinner than in the original embodiment of semiconductor structure, shown in Figure 1; a typical thickness for the beams is lμm or less. Bonding pads (not shown) and the like are formed on the Silicon slice. The alternative embodiment of semiconductor structure cannot achieve quite the same packing density as the original embodiment because clearance is required between each beam 307, and because the structure which supports the beams takes up space. However, as is now described in relation to Figures 4, it affords significant fabrication advantages over the original embodiment. Referring now to Figures 4, the stages of production of the alternative embodiment of semiconductor structure are generally similar to those shown in Figures 1. It should be noted that, whilst Figures 4(a) to 4(e) are schematic cross-sections taken along a longitudinal axis x-x of a beam 307, Figure 4(f) (which is not on the same scale as Figures 4(a) to 4(e)) is a schematic cross-section taken along axis y-y (and showing only two beams 307). The production process commences (see Figure 4(a)) with the diffusion of a Boron etch stop layer 300 into the surface of a Silicon slice 302, which has a <100> crystal orientation and may be p- or n- type. Next (see Figure 4(b)) the additional step of etching and refilling a wide, deep perimeter trench 309 is employed. The trench 309 is etched and refilled by the same techniques as described earlier In relation to Figures 1. The perimeter trench is rectangular 1n plan view. It serves not only to provide dielectric isolation but also as an etch boundary, as is explained later. Next (see Figure 4(c)) an epitaxial layer 304 is grown on top of the etch stop layer 300 in the same way as described previously in relation to Figures 1. It is to be noted that the bulk of the epitaxial layer comprises single crystal silicon. However, that portion of the layer above the perimeter trench 309 is of Poly- crystalline Silicon because of the influence of the material of the trench on the epitaxial growth process. Next (see Figure 4(d)) a protective coating 305 of Low Temperature Silicon Oxide is formed on the upper surface 308 of the structure 10. Next (see Figure 4(e)) isolating trenches 312 are etched -p the structure and then refilled, and CMOS devices 316 are fabricated in the islands 314 formed by the refilled isolating trenches. The trench fabrication and CMOS device fabrication is carried out as described in relation to Figures 1(c) and Kd). The CMOS devices 316 are then coated with a protective layer 315, again in the manner described in relation to Figures 1. Next (see Figure 4(f)) trenches 317 parallel to the perimeter trench 309, adjacent but interior to that trench, are etched away from the upper surface 308 to, or somewhat beyond, the depth of the Boron etch stop layer 300 to define the sides of each beam 307. Note that, for clarity, only two beams are shown in Figure 4(f). Etching 1s carried out by means of a Chlorine chemistry anisotropic plasma etching technique. Then etch boundaries 319 are fabricated by passivating the sides of the beams 307 using Silicon nitride. Further etching is then carried out, to undercut the beam 307 completely. This etching is carried out using an anisotropic alkali etch such as Potassium Hydroxide, or possibly Ethylene Diamine, Pyrocathecol and Pyrazine, or other anisotropic etchants. The etch boundary arrangement formed by the etch boundary 319 and perimeter trench 309 limits the lateral extent of this further etching. Finally, and optionally, (see Figure 4(f)) the Boron etch stop layer 300 may be stripped away using an appropriate etchant. It will be appreciated that the manufacturing method described above in relation to the alternative embodiment can be carried out entirely from the upper surface of the structure, and therefore affords a simpler fabrication process than that described in relation to Figures 1 and 2, which requires operations to be carried out on the back surface 311 as well. It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be made with the scope of the invention. For example, in the alternative embodiment of semiconductor structure, instead of the semiconductor layer 306 being in the form of one or more beams 307, it could be in the form of one or more cantilevers (supported at only one end instead of both). The cantilevers could be used, with appropriate electrical devices, to measure strain or acceleration.

Claims: CLAIMS 1. A semi onductor structure comprising a layer of semiconducting material having first and second opposing surfaces, an electrical device at least a portion of which is adjacent the first surface, and an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, there being an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium. 2. A semiconductor structure according to Claim 1 wherein the barrier extends directly to the ambient medium. 3. A semiconductor structure according to Claim 1 wherein the barrier extends to a layer of electrically insulating material in the isolating region. 4. A semiconductor structure according to Claim 3 wherein the insulating material has a resistivity greater than five times that of undoped Silicon. 5. A semiconductor structure according to Claim 3 or Claim 4 wherein the insulating material has a chemical formula which is related to that of a semiconductor material. 6. A semiconductor structure according to Claim 5 wherein the insulating material is a chemical compound of, preferably an oxide or nitride of, Silicon. 7. A semiconductor structure according to any of the preceding claims wherein the layer of semiconducting material is substantially free from crystallographic defects. 8. A semiconductor structure according to any of the preceding claims wherein the layer of semiconducting material contains substantially no Sapphire. 9. A semiconductor structure according to any of the preceding claims wherein the thickness of any material in the isolating region beyond the layer of semiconducting material is less than the thickness of the layer of semiconducting material. 10. A semiconductor structure according to any of the preceding claims wherein the electrical device is located on a relatively thin portion of the structure, and the structure includes a relatively thick portion supporting the relatively thin portion. 11. A semiconductor structure according to Claim 10 wherein the relatively thick portion supports the relatively thin portion around substantially its entire periphery. 12. A semiconductor structure according to Claim 10 wherein the relatively thin portion is elongate and is supported by the relatively thick portion adjacent at least one of its ends. 13. A semiconductor structure according to any of the preceding claims wherein at least one cavity is formed in the semiconductor structure extending from the first surface to the second surface. 14. A semiconductor structure according to any of the preceding claims wherein the electrical device is a Complementary Metal Oxide Silicon device. 15. A semiconductor structure according to any of the preceding claims including a conduit for coolant. 16. A semiconductor structure according to Claim 15 wherein the conduit is located in a region beyond the second surface and distinct from the isolating region. 17. A method of manufacturing a semiconductor structure, comprising providing a layer of semiconducting material having first and second opposing surfaces, fabricating an electrical device, at least a portion of the device being adjacent the first surface, providing an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, and providing an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direcT contact with the ambient medium. 18. A method according to Claim 17 wherein a member incorporating the semiconducting material is provided, and a portion of this member is removed to form the second surface. 19. A method according to Claim 18 wherein the portion is removed progressing from beyond the second surface towards the second surface. 20. A method according to Claim 18 wherein the portion is removed progressing from a region of the first surface towards the second surface and then progressing behind the second surface so as to undercut the second surface. 21. A method according to Claim 20 wherein said region is defined by a boundary arrangement extending from the first surface to the second surface. 22. A method according to any of Claims 18 to 21 wherein the isolating barrier extends to a layer of electrically insulating material in the isolating region, this layer being provided subsequent to the removal step. 23. A method according to any of Claims 18 to 22 wherein the isolating barrier 1s provided before the removal step. 24. A method according to any of Claims 18 to 23 wherein the electrical device Is fabricated before the removal step. 25. A method according to any of Claims 18 to 24 wherein the second surface is passivated subsequent to the removal step. 26. A method according to any of Claims 18 to 25 wherein the portion of the member is removed by etching. 27. A method according to Claim 26 wherein the etching is effected up to an etch stop layer defining the second surface. 28. A method according to any of Claims 17 to 27 wherein the step of providing a layer of semiconducting material includes providing a substrate, forming an etch stop layer on a surface of the substrate, and covering the etch stop layer with semiconducting material. 29. A method according to any of Claims 17 to 28 wherein at least a portion of the layer of semiconducting material is grown epitaxially from a substrate to which the epitaxially grown material is lattice-matched. 30. A method according to Claim 29 wherein the material of the epitaxially grown portion is substantially the same as that from which the substrate is formed. 31. A method according to any of Claims 17 to 30 wherein the isolating barrier extends to a layer of electrically insulating material forming the Isolating region. 32. A method according to any of Claims 17 to 31 wherein the isolating barrier is provided before the isolating region is provided. 33. A semiconductor structure substantially as herein described with reference to and as illustrated 1n Figures 1 and 2 or Figures 3 and 4 of the drawings. 34. A method of manufacturing a semiconductor structure substantially as herein described with reference to Figures 1 and 2 or Figures 3 and 4 of the drawings.

Inventors: EVANS ALAN GORDON ROBERT, FAROOQUI MOHAMMAD MATEEN, EVANS, ALAN, GORDON, ROBERT, FAROOQUI, MOHAMMAD, MATEEN
Applicants: BRITISH TECH GROUP, EVANS ALAN GORDON ROBERT, FAROOQUI MOHAMMAD MATEEN, BRITISH TECHNOLOGY GROUP LIMITED, EVANS, ALAN, GORDON, ROBERT, FAROOQUI, MOHAMMAD, MATEEN
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29