Method of and apparatus for data compression during monitor refresh operations

Abstract: The present invention discloses a method and apparatus for performing data compression during monitor refresh operations. In one embodiment, it is envisioned that the compression functions would be performed in a refresh buffer (10) and the de-compression functions would be performed in a RAMDAC (14), thereby requiring only the transfer of compressed data between the refresh buffer (10) and the RAMDAC (14). In an alternative embodiment, it is envisioned that both the compression and de-compression functions would be performed in the refresh buffer (10). Regardless of implementation, a "critical fill" level is determined during compression and a "critical fill" interrupt is generated during decompression to gain control of the frame buffer (12) before the compressed digital data is fully depleted.

Description: This invention relates in general to computer input/output (I/O) device interfaces, and in particular to a video subsystem for a computer. The use of computers to display high resolution color images and video is well known in the art. The volume of data required to display high resolution color images and video has led to the development of data compression and coding techniques, including the PEG, MPG, and P*64 standards. Such techniques are often used when storing graphics/video data on disks or when transmitting graphics/video data between computers. However, few designers have considered the effects of transferring large volumes of uncompressed graphics/video data between a CPU and a video subsystem in a PC or workstation. Typically, the video subsystem will receive de-compressed graphics/video data from the CPU, store the data in a frame buffer, and then transmit the graphics/video data to a Random Access Memory Digital to Analog Converter (RAMDAC) for conversion into analog form to control the operation of the monitor. Thereafter, the video subsystem must generate a "refresh" data stream at a fixed rate to re-draw every pixel of the image displayed on the monitor. Refresh operations must be performed at a rate high enough to eliminate image flicker on the monitor. Currently, most monitors require that refresh operations be performed at a rate of 72 Hz or higher. For high resolution and/or high color depth monitors, such refresh operations involve the transfer of huge amounts of uncompressed data. Moreover, the demands of the refresh operation at high resolution (e.g., greater than 1024 x 768 pixels), high color depth (e.g., greater than 32,000 colors), and high refresh rate (e.g., greater than 70 Hz) on a frame buffer is significant. For example, a monitor capable of displaying 1024 x 768 pixels using 256 colors and having a refresh rate of 72 Hz would require the transfer of 56.6 million bytes of uncompressed data every second for the refresh operations. A monitor capable of displaying 1280 x 1024 pixels using 16 million colors and having a refresh rate of 72 Hz refresh rate would require the transfer of 283.1 million bytes of uncompressed data every second for the refresh operations. Thus, refresh operations can consume a large percentage of the available bandwidth of the frame buffer, e.g., greater than 50%. However, refresh operations cannot be ignored or given a low priority, since failure to perform the refresh operations produces immediately perceptible visual artifacts on the monitor. Trends in video subsystem design are also increasing the demand for sharing frame buffer ownership between multiple masters, for example, the CPU, a local graphics accelerator, and one or more video controllers. All of these devices compete for bandwidth of the frame buffer, and thus cause scheduling and performance problems. This is true even when the frame buffer is constructed as a double buffer, since the address, control, and data paths are commonly shared between devices. The access contention for the frame buffer and the collisions arising therefrom have a direct effect on graphics/video performance. One common method of reducing collisions is to increase the amount of memory within each device. The device then signals a priority requirement for control of the frame buffer before its internal memory is fully depleted. If more memory can be used within the device, then it will less frequently require access to the frame buffer. Consequently, there would be greater latitude in scheduling requests for the frame buffer among various devices, thereby resulting in more efficient utilization of idle times. An additional factor is the miss/hit ratio associated with the operation of the frame buffer. Current memory organizations often require that a miss cycle be performed to open a page of memory in the frame buffer. The miss cycle requires significantly longer access delay (3x or 4x) than a corresponding hit cycle. When multiple devices access the frame buffer, they often access different regions of memory and therefore generate a higher number of new page accesses resulting in a higher number of miss cycles. In addition, when inadequate buffer levels exist, there is a corresponding increase in the number of miss cycles. Any increase in miss cycles will decrease the total available bandwidth from the frame buffer. Refresh operations have the additional constraint that the data must be output to the monitor in analog form. This is usually through some form of RAMDAC. The RAMDAC receives the pixel data in predefined bit widths (pixel port width) at a fixed frequency (pixel clock), and then translates the data through color palette RAMS that drive a set of DACs to convert the digital signals to the appropriate analog color levels. As resolution, color depth and refresh rates increase, the demands on the interface between the frame buffer and the RAMDAC becomes significant. The impact of these factors is often translated into a wide pixel port operating at high frequency. For example, to operate a monitor capable of displaying 1280 x 1024 pixels using 16 million colors and having a refresh rate of 72 Hz refresh rate would require a 48 bit wide data path interface between a frame buffer and a RAMDAC operating at 65 MHz, or alternatively, a 24 bit data path interface between a frame buffer and a RAMDAC operating at 130 Mhz. If address, control, and power pins are factored in, the interface may require between 50 and 100 package pins on an ASIC operating at between 65 Mhz and 130 Mhz. An object of the present invention is to permit higher resolution, increased color depth, and more frequent rates for monitors without increasing the demands on frame buffers. In "High Performance Display System for Dynamic Image Generation" presented at the Second International conference on cCmputers and Applications, 23 June 1987 at Beijing pages 336 to 343 Staudhammer, Huang and Lui disclosed an arrangement in which a run-length decoder produces the moving parts of an image, a background generator (a frame buffer) produces the static parts of an image, and the signals are combined in an arbitrator, but the only data compression is the use of run-length encoding. European Patent Application 0 522 697 A1, Thompson, discloses a video memory interface which controls processor access to video memory, based on a buffer, but compression techniques are not applied. According to a first aspect of the present invention there is provided a video subsystem for a computer, comprising: (a) a frame buffer for storing digital data to be displayed on a monitor and a digital-to-analog converter for converting digital data into analog signals to control said monitor; characterized by (b) a refresh buffer, coupled to the frame buffer, for retrieving the digital data from the frame buffer, for compressing the digital data and for storing the compressed data; and by said digital-to-analog converter being coupled to the refresh buffer and arranged to, retrieve the compressed digital data from the refresh buffer, de-compress the compressed digital data, and convert the de-compressed digital data into said analog signals for the control of said monitor. According to a second aspect of the present invention there is provided a data compression method for a video subsystem of a computer, comprising the steps of: (a) storing digital data in a frame buffer; (b) retrieving the digital data from the frame buffer, compressing the digital data, and storing the compressed digital data in a refresh buffer; and (c) retrieving the compressed digital data from the refresh buffer, de-compressing the compressed digital data in a digital-to-analog converter, and converting the de-compressed digital data into analog signals to control the monitor using the digital-to-analog converter. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a block diagram illustrating an exemplary method and apparatus for performing data compression during refresh operations in accordance with the present invention; Fig. 2 is a flowchart describing the fill operation performed by the present invention; Fig. 3 is a flowchart describing the drain operation performed by the present invention; and Fig. 4 is a block diagram illustrating a second exemplary method and apparatus for performing data compression during refresh operations in accordance with the present invention. Figure 1 is a block diagram illustrating an exemplary method and apparatus for performing data compression during refresh operations in accordance with the present invention. The refresh compaction device 10 is placed in the data path between a frame buffer 12 and a RAMDAC 14. In one embodiment, it is envisioned that the compression functions would be performed in the refresh compaction device 10 and the de-compression functions would be performed in the RAMDAC 14, thereby requiring only the transfer of compressed data between the refresh compaction device 10 and the RAMDAC 14. In an alternative embodiment, it is envisioned that both the compression and the de-compression functions would be performed in the refresh compaction device 10. Those skilled in the art will recognize that other alternative embodiments could also be used. Moreover, the present application is intended to describe the general functions of the invention without mandating that any function be located in a particular device. In addition, regardless of implementation, a "critical fill" level is determined during compression and a "critical fill" interrupt is generated during de-compression to gain control of the frame buffer 12 before the compressed digital data is fully depleted from the refresh compaction device 10. The frame buffer 12 stores data for the monitor in the form of frame buffer 12 lines that typically comprise a plurality of pixels representing by bytes or words or other groupings of bits. One aspect of the present invention is the ability to perform data compression on frame buffer 12 lines at the frame buffer 12 line rate. It can be shown that data can be compressed using the logic of Figure 1 within the line cycle time of the frame buffer 12. This is a function of the logic stages required, which in the preferred embodiment comprises three stages. As a result, data can be processed through the logic with less than 5 nanoseconds of transmission delay in a 0.8 micron ASIC. Of course, the delay would be even less with 0.5 micron or 0.35 micron ASIC. In the present invention, a line from the frame buffer 12 is read and stored into a Data Storage Register (DSR) 16. At initialization, and whenever the contents of the frame buffer 12 line stored into the DSR 16 changes, the frame buffer 12 line is also stored in a Holding Compare Register (HCR) 18. A plurality of XOR/NOR blocks 20 are provided to compare each pixel stored in the HCR 18 to the corresponding pixel stored in the DSR 16. The results of these tests are combined by AND gate 22 and input into control logic 24. The refresh compaction device 10 also comprises a refresh buffer comprised of a plurality of storage cells 26, which storage cells 26 are addressed by address generation logic 28. Each of the storage cells 26 is large enough to store one frame buffer 12 line from the DSR 16. Associated with each storage cell 26 is a Count(m) register 30 to record the number of sequential frame buffer 12 lines having identical contents (i.e., run-length coding). Upon readout, each storage cell 26 is selected in turn, and its contents are stored in a pixel shift register 32. The contents of the associated Count(m) register 30 are stored in an m-bit down counter 34. Thereafter, the contents of the pixel shift register 32 are shifted out multiple times, according to the m-bit down counter 34, to provide the correct number of identical frame buffer 12 lines in the correct sequence. Although the shift register 32 and the m-bit down counter 34 are shown outside the RAMDAC 14, it is envisioned that these components could be incorporated into the RAMDAC 14, as mentioned above. Because the refresh compaction device 10 shares the bandwidth of the frame buffer 12 with other devices, it must signal a priority requirement for control of the frame buffer 12 before the storage cells 26 are fully depleted by a drain operation. This occurs when a "critical fill" level is reached during the drain operation, i.e., if the drain operation reaches a particular storage cell 26, then the fill operation needs to be set to a "critical" state. The critical fill level is programmable and its value is stored in a critical count register 36. Those skilled in the art will recognize that several different methods may be used to signal the critical fill event. In the preferred embodiment, the fill operation loads the critical fill count from the critical count register 36 into a Decrement register 38, and decrements the Decrement register 38 for every frame buffer 12 line. When the Decrement register 38 decrements to 0, a Critical Fill (CF) bit 40 at the currently addressed storage cell 26 is set to signal the critical fill condition and the address generation logic 28 increments to the next storage cell 26 to continue the fill operation. Of course, the CF bit 40 could be set when the Count(m) register 30 has a value of 0, or 1, or any value up to 15. Regardless of when the CF bit 40 is set, there are no further accumulation of Count(m) register 30 values for that storage cell (e.g., the remaining values for the Count(m) register 30 go unused). In this way, the critical fill condition occurs as soon as the marked line is reached in the drain operation. This reduces the overall storage capacity of the refresh compaction device 10, but has the positive effect of being very simple to implement. Those skilled in the art will recognize that there are number of ways to implement the CF bit 40 marking without departing from the scope of the present invention. During drain operations, the critical fill count is again loaded from the critical count register 36 into a Decrement register 38, which is decremented for every frame buffer 12 line read from the storage cells 26 and transmitted to the RAMDAC 14. When the Decrement register 38 decrements to 0, the CF bit 40 at the currently addressed storage cell 26 is examined. If the CF bit 40 is set, then the refresh compaction device 10 signals a priority interrupt for control of the frame buffer 12. Figure 2 is a flowchart describing the fill operation performed by the present invention. The fill operation is initiated by a critical fill request or a normal fill request. Block 40 represents an initial state wherein all Count(m) registers 30 are set to zero, all storage cells 26 contain invalid or unknown data, the address generation logic 28 is set to the first storage cell 26, the critical fill count is loaded from the critical count register 36 into the Decrement register 38, all CF bits 40 are reset, and the marking (i.e., setting) of CF bits 40 is enabled. Block 42 reads the next (e.g., first) frame buffer 12 line into the DSR 16. Block 44 loads the contents of the DSR 16 into the first storage cell 26 and increments the associated Count(m) register 30. Block 46 loads the contents of the DSR 16 into the HCR 18. Block 48 sets a Compare flag (not shown) in the control logic 24. Block 50 increments the address generation logic 28 to the next storage cell 26. Block 52 reads the next frame buffer 12 line into the DSR 16. Block 54 is a decision block that determines whether the DSR 16 and HCR 18 contain the same frame buffer 12 lines. If not, block 56 resets the Compare flag; otherwise, block 58 increments the Count(m) register 30 for the storage cell 26 containing the frame buffer 12 line. From either block 56 or 58, control transfers to block 60, which decrements the critical fill count in the Decrement register 38. Block 62 is a decision block that determines whether the Decrement register 38 is equal to zero. If so, control transfers to block 64, which sets the CF bit 40 for the current storage cell 26 containing the frame buffer 12 line, loads the contents of the HCR 18 into the next storage cell 26, and increments the address generation logic 28 to the following storage cell 26. Control then transfers to block 64, which is a decision block that determines whether the fill operation is complete. If so, the process terminates; otherwise, control transfers to block 68. Block 68 is a decision block that determines whether the Compare flag is set, which signifies that the current contents of the DSR 16 and HCR 18 are identical. If not, control transfers to block 42; otherwise, control transfers to block 52. Those skilled in the art will recognize that there are many alternative methods may be used in performing the fill operation and that the present invention is not restricted to the particular method illustrated above. Figure 3 is a flowchart describing the drain operation performed by the present invention. The drain operation is initiated by an idle RAMDAC 14 condition or a normal drain request from the RAMDAC 14. Block 70 represents an initial state wherein the address generation logic 28 is set to the first storage cell 26 and the critical fill count is loaded from the critical count register 36 into the Decrement register 38. Block 72 loads the contents of the currently addressed storage cell 26 into the shift register 32. Block 74 stores the contents of the associated Count(m) register 30 into the m-bit down counter 34. Block 76 is a decision block that determines whether the m-bit down counter 34 has been decremented to 0. If so, block 78 increments the current storage cell 26 address to the next storage cell 26 and transfers control to block 72; otherwise, block 80 shifts the frame buffer 12 line out of the shift register 32 to the RAMDAC 14, block 82 decrements the m-bit down counter 34, and block 84 decrements the critical fill count in the Decrement register 38. Block 86 is a decision block that determines whether the critical fill count has been decremented to 0. If not, control transfers to block 76; otherwise, control transfers to block 88. Block 88 is a decision block that determines whether the CF bit 40 is set for the currently addressed storage cell 26. If so, control transfers to block 90, which issues a critical fill request to the frame buffer 12 and then transfers control to block 76. Once all storage cells 26 have been drained to the RAMDAC, block 92 terminates the process. Those skilled in the art will recognize that there are many alternative methods may be used in performing the drain operation and that the present invention is not restricted to the particular method illustrated above. Figure 4 is a block diagram illustrating a second exemplary method and apparatus for performing data compression during refresh operations according to the present invention. Figure 4 contains all the components of Figure 1, except that it uses two sets of storage cells 26 labelled as "A" and "B", as well as additional logic in 24 and 28 to control the "ping pong" operation of the two sets of storage cells 26. Figure 4 is also different from Figure 1 in that it includes a multiplexor 94 to select the correct set of storage cells 26 for the drain operation. Using the structure of Figure 4, the fill and drain operations can occur simultaneously, as well as at different rates according to the bandwidth of the frame buffer 12 and RAMDAC 14.

Claims: A video subsystem for a computer, comprising: (a) a frame buffer (12) for storing digital data to be displayed on a monitor and a digital-to-analog converter (14) for converting digital data into analog signals to control said monitor; characterized by (b) a refresh buffer (10), coupled to the frame buffer (12), for retrieving the digital data from the frame buffer (12), for compressing the digital data, and for storing the compressed data; and by said digital-to-analog converter (14) being coupled to the refresh buffer (10) and arranged to retrieve the compressed digital data from the refresh buffer (10), to de-compress the compressed digital data, and to convert the de-compressed digital data into said analog signals for the control of said monitor. A video subsystem according to claim 1 characterized in that the refresh buffer (10) comprises means for compressing the digital data at a line rate of said frame buffer (12). A video subsystem according to claim 1 or claim 2, characterized in that said refresh buffer (10) comprises means (36)for signalling a priority requirement for control of said frame buffer (12) before said refresh buffer (10) is fully depleted of the compressed digital data. A video subsystem according to claim 3, characterized in that said means (36) for signalling comprises means for determining when an amount of the compressed digital data stored in said refresh buffer (10) has dropped to a critical fill level. A video subsystem according to claim 3, characterized in that said means (36) for signalling comprises means (38) for determining when an amount of the de-compressed digital data retrieved by said digital-to-analog converter (14) has reached a critical fill level. A video system according to any one of the preceding claims, characterized in that said refresh buffer (10) comprises an internal buffer comprised of a plurality of memory locations having a storage cell (26) portion and a counter portion, and means for storing the digital data in the storage cell portions and means (28) for recording a run-length coding of the digital data having in the counter portions. A video subsystem according to claim 6, characterized by means for accumulating the run-length coding for the compressed digital data retrieved by said digital-to-analog converter (14), for comparing the accumulated run-length coding with a predetermined critical fill level, and for signalling a priority requirement for control of the frame buffer (12) when the accumulated run-length coding matches the pre-determined critical fill level. A video subsystem according to claim 6, characterized in that said digital-to-analog converter (14) comprises means for retrieving the compressed digital data from said storage cell portion (26), means for retrieving the run-length coding from said counter portion (28), means for de-compressing the compressed digital data by generating a repetitive stream of the digital data as indicated by the run-length coding, and means for converting the repetitive stream of the digital data into analog signals to control said monitor. A data compression method for a video subsystem of a computer, comprising the steps of: (a) storing digital data in a frame buffer (12); (b) retrieving the digital data from said frame buffer (12), compressing the digital data, and storing the compressed digital data in a refresh buffer (12); and (c) retrieving the compressed digital data from said refresh buffer (10), de-compressing the compressed digital data in a digital-to-analog converter (14), and converting the de-compressed digital data into analog signals to control a monitor using said digital-to-analog converter (14). A method according to claim 9, characterized in that the retrieving step (c) comprises the step of signalling a priority requirement for control of said frame buffer (12) before said refresh buffer (10) is fully depleted of the compressed digital data.

Inventors: PARSONS DONALD H, PARSONS, DONALD H.
Applicants: NCR INT INC, NCR INTERNATIONAL, INC.
Application year: 1994
Main classification: G09G5
IPC codes: G09G5, H03M7, G06T9, H04N5, H04N7