HIGH SATURATION CURRENT, LOW LEAKAGE CURRENT FERMI THRESHOLD FIELD EFFECT TRANSISTOR

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300 ANGSTROM are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600 ANGSTROM , the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively. A Fermi-FET having a gate insulator thickness of less than 120 ANGSTROM , and a channel length of less than about 1 mu m can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts.

Description: HIGH SATURATION CURRENT, LOW LEAKAGE CURRENT FERMI THRESHOLD FIELD EFFECT TRANSISTOR Field of the Invention This invention relates to field effect transistor devices and more particularly to integrated circuit field effect transistors which are capable of producing high currents and low leakage currents. Background of the Invention Field effect transistors (FET) have become the dominant active device for very large scale integration (VLSI) and ultra large scale integration (ULSI) applications, such as logic devices, memory devices and microprocessors, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving the speed and integration density of FETs, and on lowering the power consumption thereof . A high speed, high performance field effect transistor is described in U.S. Patents 4,984,043 and 4,990,974, both by coinventor Albert . Vinal, both entitled Fermi Threshold Field Effect Transistor and both assigned to the assignee of the present invention. These patents describe a metal oxide semiconductor field effect transistor (MOSFET) which operates in the enhancement mode without requiring inversion, by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. As is well known to those having skill in the art, Fermi potential is defined as that potential for which an energy state in a semiconductor material has a probability of one-half of being occupied by an electron. As described in the above mentioned Vinal patents, when the threshold voltage is set to twice the Fermi potential, the dependence of the threshold voltage on oxide thickness, channel length, drain voltage and substrate doping is substantially eliminated. Moreover, when the threshold voltage is set to twice the Fermi potential, the vertical electric field at the substrate face between the oxide and channel is minimized, and is in fact substantially zero. Carrier mobility in the channel is thereby maximized, leading to a high speed device with greatly reduced hot electron effects. Device performance is substantially independent of device dimensions. Notwithstanding the vast improvement of the Fermi threshold FET compared to known FET devices, there was a need to lower the capacitance of the Fermi- FET device. Accordingly, in U.S. Patent Application Serial No. 07/826,939, now U.S. Patent 5,194,923, and Application Serial No. 07/977,689, both by coinventor Albert . Vinal, and both entitled Fermi Threshold Field Effect Transistor Wi th Reduced Gate and Diffusion Capaci tance, a Fermi-FET device is described which allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction. Accordingly, the average depth of the channel charge requires inclusion of the permittivity of the substrate as part of the gate capacitance. Gate capacitance is thereby substantially reduced. As described in the aforesaid patent and patent application, the low capacitance Fermi-FET is preferably implemented using a Fermi-tub region having a predetermined depth and a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source. The Fermi- tub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub within the tub boundaries. The Fermi-tub forms a unijunction transistor, in which the source, drain, channel and Fermi-tub are all doped the same conductivity type, but at different doping concentrations. A low capacitance Fermi-FET is thereby provided. The low capacitance Fermi-FET including the Fermi-tub will be referred to herein as a "low capacitance Fermi-FET" or a "Tub-FET" . Notwithstanding the vast improvement of the Fermi-FET and the low capacitance Fermi-FET compared to known FET devices, there is a continuing need to increase the saturation current per unit channel width which is produced by the Fermi-FET device. Higher current Fermi-FET devices will allow even greater integration density, and/or much higher speeds for logic devices, memory devices, microprocessors and other integrated circuit devices. However, saturation current must not be obtained at the expense of high leakage current . High leakage current dramatically increases the idle power consumption of the device. Finally, as portable and laptop computers proliferate, it is desirable to lower the threshold voltage of a Fermi-FET transistor, without adversely impacting operation thereof. Lower threshold voltage devices are better able to operate with 3 volt or lower power supplies, which are increasingly being used for portable and other energy conscious applications. Summary of the Invention It is therefore an object of the invention to provide an improved Fermi threshold field effect transistor (Fermi-FET) . It is another object of the invention to provide a Fermi-FET which is capable of producing very high current per unit channel width. It is yet another object of the invention to provide a Fermi-FET which is capable of producing very high current per unit channel width, with very low leakage current . These and other objects are provided, according to the present invention by a Fermi-FET wherein the source and drain regions are doped the second conductivity type at a predetermined concentration facing the channel which is sufficiently high to maximize the saturation current of the Fermi- FET. It has been found that stored free charge at the source/drain-channel interface limits the amount of saturation current of the Fermi-FET. Accordingly, a predetermined minimum doping concentration of the source and drain facing the channel is provided, according to the present invention, to maximize the saturation current of the field effect transistor. Doping beyond this predetermined concentration will not significantly increase the saturation current of the field effect transistor. The predetermined concentration N n of the source and/or drain which maximizes the saturation current is given by: e s e iLo [ V max-V t ) jV , = — α°mιn 2 e s φ x g ^ (Se^+δe,) Where : E s = Permittivity of substrate φ x = Flat band voltage between source/drain diffusion doping and channel doping q = 1.6xl0 ~19 coulomb e ± = Permittivity of the gate insulator L 0 = Channel length V gmax = Maximum gate voltage anticipated V t = Threshold voltage. Y f = Depth of the Fermi-channel adjacent the source and drain regions T ox = Insulator thickness δ = Flow depth of excess carriers in the channel A source doping gradient region and preferably a drain doping gradient region are also provided between the source region and the channel and between the drain region and the channel, respectively. The doping gradient regions are doped at a doping gradient which decreases from the source/drain doping concentration adjacent the source/drain regions to the channel doping concentration adjacent the channel. The source/drain doping gradient regions preferably surround the source and drain regions respectively. It has been found that a source and drain doping gradient region thickness of at least 300A is required in order to support the high saturation currents described above. Also, in order to supply the high saturation current described above, the gate insulating layer and gate electrodes preferably extend over the source/drain doping gradient regions. Finally, the substrate doping concentration is greater than the tub doping concentration, preferably by a factor of at least four, to minimize substrate doping concentration from effecting the criteria required for Tub depth and doping to achieve zero perpendicular field across the Fermi-channel . A Fermi-FET according to the present invention provides high saturation currents without adversely increasing the leakage current of the Fermi- FET. For example, a Fermi-FET having a gate insulator thickness of less than 120 Angstroms and a channel length of less than about 1 micron can provide a P- channel saturation current of at least 4 amperes per centimeter and an N-channel saturation current of at least 7 amperes per centimeter, with a leakage current of less than 10 picoamperes per micron using power supplies of between 0 and 5 volts. This performance cannot be achieved by a conventional MOSFET, of surface channel or buried channel type, wherein significant static electric field is produced in the channel perpendicular to the substrate surface. According to another aspect of the invention, the threshold voltage of a Fermi-FET may be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by maintaining a predetermined channel depth, preferably about 600 Angstroms, and increasing the doping concentration of the channel to lower the threshold voltage to below twice the Fermi potential. The channel doping may be lowered to produce a desired threshold voltage according to the following relationship: Where: ΔV T = Change in threshold voltage from twice the Fermi potential of the substrate q = 1.6xl0 "19 coulomb T ox = Oxide insulator thickness N ch = Impurity concentration in the channel Y f = Depth of the Fermi-channel adjacent the source and drain regions e E = Permittivity of substrate e ± = Permittivity of the gate insulator The channel concentration should be maintained at less than about 5xl0 16 so as to prevent carrier mobility from dropping and thereby lowering saturation current . The above described aspects of the present invention may be used in combination in order to obtain a Fermi-FET with independently controlled saturation current and threshold voltage. In particular, for a given channel depth, preferably on the order of 600 Angstroms, the source/drain doping concentration may be varied to independently control the maximum saturation current of the device, while the channel doping concentration may be varied to independently control the threshold voltage of the device. Thus, independent control of saturation current and threshold voltage in a Fermi-FET may be obtained. As described above, a high current Fermi-FET according to the present invention is capable of producing a drain saturation current of at least 4 amperes per centimeter of channel width (P-channel) and 7 amperes per centimeter of channel width (N-channel) at a leakage current of less than 10 picoamperes per micron of channel width for channel lengths less than 1 micron and gate insulating layer thicknesses of less than about 120 Angstroms. These values cannot be achieved in a conventional MOSFET which includes electric fields which are oriented perpendicular to the channel carrier flow direction. A detailed comparison of a Fermi-FET and a conventional MOSFET has revealed that saturation velocity is a vector quantity which is governed by the electric field parallel to the substrate, in the carrier flow direction, and also the electric field which is perpendicular to the substrate and perpendicular to the carrier flow direction. Since the Fermi-FET eliminates the vertical (perpendicular) component, saturation current is maximized compared to a conventional MOSFET. In a conventional MOSFET, saturation current can be increased, but at the expense of unacceptably high leakage current. Only the Fermi- FET can produce a Fermi-FET transistor with high saturation current and acceptably low leakage current. According to another aspect of the present invention, a Fermi-FET includes an injector region of the same conductivity type as the Fermi-tub region and the source region, adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate to the relatively low doping concentration of the Fermi-tub and the relatively high doping concentration of the source. The injector region controls the depth of the carriers injected into the channel and enhances injection of carriers in the channel, at a predetermined depth below the gate. Preferably, the source injector region is a source injector tub region which surrounds the source region. In other words, the source injector tub region is formed within the Fermi-tub region, and the source is preferably formed within the source injector tub region. Similarly, a drain injector tub region is also formed within the Fermi-tub region and the drain region is preferably formed within the drain injector tub. The source region and drain regions may also extend deeper into the substrate than the respective source injector tub region and drain injector tub region. The source injector tub region and drain injector tub region are of the same conductivity type as the source, drain and Fermi-tub, and are preferably doped at a concentration which is intermediate to that of the Fermi-tub and the source and drain regions. According to another aspect of the invention, lower pinch-off voltage and increased saturation current are obtained by providing a gate sidewall spacer which extends from adjacent the source injector region to adjacent the gate electrode of the Fermi-FET. The gate sidewall spacer preferably comprises an insulator having permittivity which is greater than the permittivity of the gate insulating layer. For example, in typical field effect transistor devices, where the gate insulator is silicon dioxide, the gate sidewall spacer is preferably silicon nitride. The gate sidewall spacer also preferably extends from adjacent the drain injector region to adjacent the gate electrode. The gate sidewall spacer typically surrounds the gate electrode on the sidewall thereof. The gate electrode of a Fermi-FET preferably includes a polycrystalline silicon (polysilicon) layer on the gate insulating layer, and a conductor layer such as metal on the polysilicon layer. The polysilicon layer is preferably of opposite conductivity type from the source, drain and tub regions of the Fermi-FET. The gate sidewall spacer extends from the sidewall of the polysilicon layer onto the source and drain injection tubs. The gate sidewall spacer lowers the pinch-off voltage of the device and increases the saturation current of the device. The source and drain injector regions may be used in the Tub-FET structure to provide a high current Fermi-FET device. The source and drain injector regions are preferably used in combination with the gate sidewall spacer to provide a high current device with low pinch-off voltage. When short channel FETs, for example FETs with channel length of about 0.5μm or less, are fabricated, bottom leakage current increases as a result of the drain field terminating in the source depletion region, to cause drain induced injection. According to another aspect of the invention, bottom leakage current is reduced by extending the source and drain injector regions to the depth of the Fermi-tub. Alternatively, a bottom leakage control region of the same conductivity type as the substrate may be provided. The bottom leakage control region is doped at a high concentration relative to the substrate and extends across the substrate from between an extension of the facing ends of the source and drain regions or source and drain injector regions, and extends to both sides of the Fermi-tub/substrate junction. High current, short channel devices with low pinch-off voltage and low leakage current are thereby provided. It will be understood by those having skill in the art that the bottom leakage control region or extended injector regions may also be used in Tub-FETs having channel length which is greater than about 0.5μm. The bottom leakage current control region can also be used in a Tub-FET which does not include injector regions. The Fermi-tub depth is also preferably bounded between a maximum tub depth and a minimum tub depth. In particular, the Fermi-tub depth is sufficiently deep to allow complete depletion of the Fermi-tub region by the substrate-tub junction at the threshold voltage of the field effect transistor, but is also sufficiently shallow to allow a closed inversion injection barrier between the source region and the drain region below the threshold voltage of the Fermi-FET. High saturation current and low leakage current are thereby produced simultaneously. In particular, a field effect transistor according to the present invention includes a semiconductor substrate of first conductivity type which is doped at a first doping concentration N sub , has a permittivity e B and a Fermi-potential e f at temperature T° Kelvin. A Fermi-tub region of second conductivity type is formed in the substrate at a surface thereof, and is doped at a second doping concentration N tub which a factor α. times N sub . Spaced apart source and drain regions of second conductivity type are formed in the Fermi-tub region at the substrate surface. A gate insulating layer is formed on the substrate at the substrate surface between the spaced apart source and drain regions. Source, drain and gate electrodes electrically contact the source and drain regions and the gate insulating layer, respectively. According to the invention, the Fermi-tub region extends into the substrate a predetermined depth from the substrate surface, where the predetermined depth is greater than (2e s ø s N sub /qN tub (N tub +N sub ) ) ^ and is less than (2e s V t /qN tub ) ", where q is 1.6xl0 ~19 coulombs, V t is the threshold voltage of the Fermi-FET, φ s is 2φ f + (KT/q) lnα, and K is 1.38 x IO "23 Joules/°Kelvin. By confining Fermi-tub to between this minimum and maximum depth, a high saturation current, low leakage current Fermi-FET is provided. Brief Description of the Drawings Figure 1 illustrates a cross-sectional view of an N-channel high current Fermi-FET. Figures 2A-2C graphically illustrate preferred doping profiles and geometries for the high current Fermi-FET of Figure 1 having a 0.8μm channel. Figure 3 illustrates an enlarged cross- sectional view of a portion of the high current Fermi- FET of Figure 1. Figures 4A and 4B graphically illustrate simulated drain saturation current for N-channel and P- channel Fermi-FETs respectively, as a function of channel length and gate insulating layer thickness. Figure 4C graphically illustrates simulated gate capacitance versus gate insulating layer thickness for a Fermi-FET. Figure 5A graphically illustrates simulated transistor drain current characteristics of a conventional 0.8μm N-channel MOSFET. Figures 5B and 5C graphically illustrate simulated transistor drain current characteristics of a 0.8μm N-channel high current Fermi-FET. Figures 6A and 6B graphically illustrate simulated bottom current and subthreshold leakage behavior for N-channel and P-channel high current Fermi-FETs respectively. Figure 7 graphically illustrates simulated worst case comparisons of drain current versus drain bias for different sidewall spacer structures in a high current Fermi-FET. Figures 8A-8C illustrate enlarged cross- sections of the sidewall spacer structures which are graphically illustrated in Figure 7. Figure 9A illustrates a cross-sectional view of a first embodiment of a short channel low leakage current Fermi-FET. Figure 9B illustrates a cross-sectional view of a second embodiment of a short channel low leakage current Fermi-FET. Figures 10A and 10B graphically illustrate preferred doping profiles and geometries for designing a 0.5μm channel low leakage current Fermi-FET of Figure 9A. Figures IOC and 10D graphically illustrate preferred doping profiles and geometries for designing a 0.5μm channel low leakage current Fermi-FET of Figure 9B. Figure 11 graphically illustrates basic sub- threshold voltage-current behavior of a field effect transistor. Figures 12A and 12B are enlarged cross- sectional views of a field effect transistor illustrating drain induced injection. Figure 13 illustrates a cross-sectional view of an N-channel, high current, low leakage current Fermi-FET according to the invention. Figure 14 graphically illustrates accumulated free charge which is stored in the source and/or drain diffusion injection area facing the channel in the transistor of Figure 13. Figure 15 graphically illustrates an equivalent volume of excess carriers that is free to be accumulated into the channel of the transistor of Figure 13. Figures 16A-16B graphically illustrate a gate capacitance factor as a function of source/drain diffusion concentration for various channel lengths. Figure 17 graphically illustrates an electric field diagram for the transistor of Figure 13 at threshold. Figure 18 graphically illustrates lowering of threshold voltage by increasing the doping concentration in the channel, of the transistor of Figure 13. Figure 19 graphically illustrates saturation velocity in a field effect transistor as a vector quantity. Figures 20A and 20B graphically illustrate maximum lateral velocity for electrons and holes, respectively. Figures 21A and 21B illustrate the cosine factor for the conditions of Figures 20A and 20B respectively. Figure 22A illustrates a cross-sectional view of an N-channel MOS device with lightly doped diffusions. Figure 22B is a perpendicular electric field diagram for the device of Figure 22A. Figure 23A is a cross-sectional view of a buried channel MOS device with lightly doped diffusions. Figure 23B is a perpendicular electric field diagram for the device of Figure 23A. Figure 24 graphically illustrates a perpendicular electric field diagram for the Fermi-FET transistor of Figure 13. Figures 25A-25C graphically illustrate NMOS and N-Fermi-FET drain saturation current as a function of gate function and channel length. Figures 26A-26C graphically illustrate PMOS and P-Fermi-FET drain saturation current as a function of gate function and channel length. Figure 27 illustrates a cross-sectional view of a second embodiment of an N-channel, high current, low leakage current, Fermi-FET according to the invention. Figure 28 illustrates an enlarged cross- sectional view of a portion of the Fermi-FET of Figure 27. Figure 29 graphically illustrates the total undepleted reservoir of distributed charge adjacent the source region of the Fermi-FET of Figure 27. Figure 30 graphically illustrates saturation current as a function of doping gradient region thickness for the Fermi-FET of Figure 27. Figure 31 graphically illustrates saturation current as a function of source/drain doping concentration for the Fermi-FET of Figure 27. Figure 32 graphically illustrates doping gradient region distance versus source/drain diffusion depth for the Fermi-FET of Figure 27. Figures 33A and 33B illustrate a cross- sectional view of a portion of the Fermi-FET of Figure 1 and a corresponding electric field diagram, respectively. Figure 34A graphically illustrates a simulation of a completely enclosed inversion region. Figure 34B graphically illustrates a simulation of a failure of an inversion injection barrier to close. Figure 35 graphically illustrates maximum and minimum values of Fermi-tub depth. Figure 36 graphically illustrates Fermi- channel depth as a function of Fermi-tub doping concentration and substrate concentration. Figure 37 graphically illustrates threshold voltage as a function of tub doping concentration and polysilicon gate concentration. Detailed Description of Preferred Embodiments The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Before describing the high saturation current, low leakage current Fermi threshold field effect transistor of the present invention, the Fermi threshold field effect transistor with reduced gate and diffusion capacitance of Application Serial Nos. 07/826,939 and 07/977,689 (also referenced as the "low capacitance Fermi-FET" or the "Tub-FET") will first be described. A more complete description may be found in these applications, the disclosures of which are hereby incorporated herein by reference. After describing the low capacitance Fermi- FET, a Fermi-FET including the injector regions, gate sidewall spacer regions, and bottom leakage control region will then be described. Then, control of saturation current by controlling doping of the source/drain diffusions facing the channel will be described. Control of threshold voltage will then be described. A theoretical comparison between a conventional MOSFET and a Fermi-FET will be provided, and it will be shown that a conventional MOSFET cannot produce the desired combination of high saturation current and low leakage current of the Fermi-FET. Then, the bounded tub Fermi- FET will be described. Fermi-FET With Reduced Gate and Diffusion Capacitance The following summarizes the low capacitance Fermi-FET including the Fermi-tub. Additional details may be found in Application Serial Nos. 07/826,939 and 07/977,689. Conventional MOSFET devices require an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction. The depth of the inversion layer is typically 100A or less. Under these circumstances gate capacitance is essentially the permittivity of the gate insulator layer divided by its thickness. In other words, the channel charge is so close to the surface that effects of the dielectric properties of the substrate are insignificant in determining gate capacitance. Gate capacitance can be lowered if conduction carriers are confined within a channel region below the gate, where the average depth of the channel charge requires inclusion of the permittivity of the substrate to calculate gate capacitance. In general, the gate capacitance of the low capacitance Fermi-FET is described by the following equation: (1) βe £ e i Where Y f is the depth of the conduction channel called the Fermi channel, e s is the permittivity of the substrate, and β is the factor that determines the average depth of the charge flowing within the Fermi channel below the surface. β depends on the depth dependant profile of carriers injected from the source into the channel. For the low capacitance Fermi-FET, β ° ~2 . T ox is the thickness of the gate oxide layer and e ± is its permittivity. The low capacitance Fermi-FET includes a Fermi-tub region of predetermined depth, having conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source regions. The Fermi-tub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub region within the Fermi-tub boundaries. The preferred Fermi-tub depth is the sum of the Fermi channel depth Y f and depletion depth Y 0 . A Fermi channel region with predetermined depth Y f and width Z, extends between the source and drain diffusions. The conductivity of the Fermi channel is controlled by the voltage applied to the gate electrode. The gate capacitance is primarily determined by the depth of the Fermi channel and the carrier distribution in the Fermi channel, and is relatively independent of the thickness of the gate oxide layer. The diffusion capacitance is inversely dependant on the difference between [the sum of the depth of the Fermi- tub and the depletion depth Y 0 in the substrate] and the depth of the diffusions X d . The diffusion depth is preferably the same depth as the Fermi channel . For deeper configurations, diffusion depth is less than the depth of the Fermi-tub, Y^. The dopant concentration for the Fermi-tub region is preferably chosen to allow the depth of the Fermi channel to be greater than three times the depth of an inversion layer within a MOSFET. Accordingly, the low capacitance Fermi-FET includes a semiconductor substrate of first conductivity type having a first surface, a Fermi-tub region of second conductivity type in the substrate at the first surface, spaced apart source and drain regions of the second conductivity type in the Fermi- tub region at the first surface, and a channel of the second conductivity type in the Fermi-tub region at the first surface between the spaced apart source and drain regions . The channel extends a first predetermined depth (Y f ) from the first surface and the tub extends a second predetermined depth (Y 0 ) from the channel . A gate insulating layer is provided on the substrate at the first surface between the spaced apart source and drain regions. Source, drain and gate electrodes are provided for electrically contacting the source and drain regions and the gate insulating layer respectively. At least the first and second predetermined depths are selected to produce zero static electric field perpendicular to the first surface at the first depth, upon application of the threshold voltage of the field effect transistor to the gate electrode. The first and second predetermined depths are also selected to allow carriers of the second conductivity type to flow from the source to the drain in the channel, extending from the first predetermined depth toward the first surface upon application of the voltage to the gate electrode beyond the threshold voltage of the field effect transistor. The carriers flow from the source to the drain region beneath the first surface without creating an inversion layer in the Fermi-tub region. The first and second predetermined depths are also selected to produce a voltage at the substrate surface, to achieve a value twice the Fermi potential of the substrate adjacent the gate insulating layer. The sum of the voltages between the substrate contact and the substrate and between the polysilicon gate and the gate electrode are essentially zero. When the substrate is doped at a doping density N s , has an intrinsic carrier concentration N, at temperature T degrees Kelvin and a permittivity e s , and the field effect transistor includes a substrate contact for electrically contacting the substrate, and the channel extends a first predetermined depth Y f from the surface of the substrate and the Fermi-tub region extends a second predetermined depth Y 0 from the .. - channel, and the Fermi-tub region is doped at a doping density which is a factor a times N s , and the gate electrode includes a polysilicon layer of the first conductivity type and which is doped at a doping density N p , the first predetermined depth (Y f ) is equal to: 2 ~ s KT Yf = gN Ξ a q In (2. N, where q is 1 . 6xl0 "19 coulombs and K is 1 . 38xl0 "23 Joules/ 0 Kelvin . The second predetermined depth (Y 0 ) is equal to : where φ s is equal to 2φ f +KT/q lnα, and φ f is the Fermi potential of the semiconductor substrate . High Current Fermi-FET Structure Referring now to Figure 1, an N-channel high current Fermi-FET according to the invention is illustrated. It will be understood by those having skill in the art that a P-channel Fermi-FET may be obtained by reversing the conductivities of the N and P regions. As illustrated in Figure 1, high current Fermi-FET 20 is fabricated in a semiconductor substrate 21 having first conductivity type, here P-type, and including a substrate surface 21a. A Fermi-tub region 22 of second conductivity type, here N-type, is formed in the substrate 21 at the surface 21a. Spaced apart source and drain regions 23 and 24, respectively, of the second conductivity type, here N-type, are formed in the Fermi-tub region 22 at the surface 21a. It will be understood by those having skill in the art that the source and drain regions may also be formed in a trench in the surface 21a. A gate insulating layer 26 is formed on the substrate 21 at the surface 21a between the spaced apart source and drain regions 23 and 24, respectively. As is well known to those having skill in the art, the gate insulating layer is typically silicon dioxide. However, silicon nitride and other insulators may be used. A gate electrode is formed on gate insulating layer 26, opposite the substrate 21. The gate electrode preferably includes a polycrystalline silicon (polysilicon) gate electrode layer 28 of first conductivity type, here P-type. A conductor gate electrode layer, typically a metal gate electrode layer 29, is formed on polysilicon gate electrode 28 opposite gate insulating layer 26. Source electrode 31 and drain electrode 32, typically metal, are also formed on source region 23 and drain region 24, respectively. A substrate contact 33 of first conductivity type, here P-type, is also formed in substrate 21, either inside Fermi-tub 22 as shown or outside tub 22. As shown, substrate contact 33 is doped first conductivity type, here P-type, and may include a relatively heavily doped region 33a and a relatively lightly doped region 33b. A substrate electrode 34 establishes electrical contact to the substrate. The structure heretofore described with respect to Figure 1 corresponds to the low capacitance Fermi-FET structure of Application Serial Nos. 07/977,689 and 07/826,939. As already described in these applications, a channel 36 is created between the source and drain regions 23 and 24. The depth of the channel from the surface 21a, designated at Y f in Figure 1, and the depth from the bottom of the channel to the bottom of the Fermi-tub 22, designated as Y 0 in Figure 1, along with the doping levels of the substrate 21, tub region 22, and polysilicon gate electrode 28 are selected to provide a high performance, low capacitance field effect transistor using the relationships of Equations (2) and (3) above. Still referring to Figure 1, according to the present invention, a source injector region 37a of second conductivity type, here N-type, is provided adjacent the source region 23 and facing the drain region. As will be described below, the source injector region provides a high current, Fermi-FET by controlling the depth at which carriers are injected into channel 36. The source injector region 37a may only extend between the source region 23 and the drain region 24. The source injector region preferably surrounds source region 23 to form a source injector tub region 37, as illustrated in Figure 1. Source region 23 may be fully surrounded by the source injector tub region 37, on the side and bottom surface. Alternatively, source region 23 may be surrounded by the source injector tub region 37 on the side, but may protrude through the source injector tub region 37 at the bottom. Still alternatively, source injector region 37a may extend into substrate 21, to the junction between Fermi-tub 22 and substrate 21. A drain injector region 38a, preferably a drain injector tub region 38 surrounding drain region 24, is also preferably provided. Source injector region 37a and drain injector region 38a or source injector tub region 37 and drain injector tub region 38, are preferably doped the second conductivity type, here N-type, at a doping level which is intermediate the relatively low doping level of Fermi-tub 22 and the relatively high doping level of source 23 and drain 24. Accordingly, as illustrated in Figure 1, Fermi-tub 22 is designated as being N, source and drain injector tub regions 37, 38 are designated as N+ and source and drain regions 23, 24 are designated as N++. A unijunction transistor is thereby formed. The high current Fermi-FET of the present invention provides drive currents that are about four times that of state of the art FETs. Gate capacitance is about half that of a conventional FET device. The doping concentration of the source injector tub region 37 controls the depth of carriers injected into the channel region 36, typically to about 1000A. The source injector tub region 37 doping concentration is typically 2E18, and preferably has a depth at least as great as the desired maximum depth of injected majority carriers. Alternatively, it may extend as deep as the Fermi-tub region 22 to minimize subthreshold leakage current, as will be described below. It will be shown that the carrier concentration injected into the channel 36 cannot exceed the doping concentration of the source injector region 37a facing the drain. The width of the portion of source injector region 37a facing the drain is typically in the range of 0.05- 0.15μm. The doping concentration of the source and drain regions 23 and 24 respectively, is typically 1E19 or greater. The depth (Y f +Y 0 ) of the Fermi-tub 22 is approximately 2200A with a doping concentration of approximately 1.8E16. As illustrated in Figure 1, the high current Fermi-FET 20 also includes a gate sidewall spacer 41 on the substrate surface 21a, which extends from adjacent the source injector region 37a to adjacent the polysilicon gate electrode 28. Gate sidewall spacer 41 also preferably extends from adjacent the drain injector region 38a to adjacent the polysilicon gate electrode 28. In particular, as shown in Figure 1, gate sidewall spacer 41 extends from the polysilicon gate electrode sidewall 28a and overlies the source and drain injector regions 37a and 38a respectively. Preferably the gate sidewall spacer 41 surrounds the polysilicon gate electrode 28. Also preferably, and as will be discussed in detail below, the gate insulating layer 26 extends onto the source injector region 37a and the drain injector region 38a at the substrate face 21a and the gate sidewall spacer 41 also extends onto the source injector region 37 and drain injector region 38. The gate sidewall spacer 41 lowers the pinch- off voltage of the Fermi-FET 20 and increases its saturation current in a manner in which will be described in detail below. Preferably, the gate sidewall spacer is an insulator having a permittivity which is greater than the permittivity of the gate insulating layer 26. Thus, for example, if the gate insulating layer 26 is silicon dioxide, the gate sidewall spacer is preferably silicon nitride. If the gate insulating layer 26 is silicon nitride, the gate sidewall spacer is preferably an insulator which has permittivity greater than silicon nitride. As shown in Figure 1, the gate sidewall spacer 41 may also extend onto source and drain regions 23 and 24 respectively, and the source and drain electrodes 31 and 32 respectively may be formed in the extension of the gate sidewall spacer region. Conventional field oxide or other insulator 42 regions separate the source, drain and substrate contacts. It will also be understood by those having skill in the art that although the outer surface 41a of gate sidewall spacer 41 is illustrated as being curved in cross section, other shapes may be used, such as a linear outer surface to produce a triangular cross section or orthogonal outer surfaces to produce a rectangular cross section. Design of 0.8um High Current Fermi-FET Referring now to Figures 2A-2C, preferred doping profiles and geometries for designing a 0.8μm channel high current Fermi-FET as illustrated in Figure 1 will now be described. It will be understood by those having skill in the art that both N and P channel FETs are fabricated in a similar fashion. Figures 2A- 2C are simulation results which graphically illustrate N-channel high current Fermi-FET doping profiles to produce a 0.8μm channel length device leading to the drain current properties illustrated in Figures 5B and 5C. It is well known to those having skill in the art how to achieve these doping profiles, using many well known techniques. In the examples of Figures 2A-2C, the P-type doping concentration of the polysilicon gate electrode 28 is 2E19 for either P- or N-channel FETs. The Si0 2 gate insulating layer 26 is 140A thick. The thickness of the polysilicon gate electrode 28 is 3000A. The height of the gate sidewall spacer 41 is also 3000A, and the gate sidewall spacer 41 is fabricated of silicon nitride. The width of the source injector tub region portion 37a facing the drain is about 0.lμm and the gate insulating layer 26 overlaps this region by about 0.05μm. Referring now to Figure 2A, a vertical doping profile along the line 2A-2A' of Figure 1, perpendicular to the face 21a and centered about the source 23 is described. The region to which the profile applies is also labeled at the top of the horizontal axis of Figure 2A. As shown, the gate sidewall spacer region 41 has a thickness of about 140A and the source region 23 has a depth of about 2000A from the face 21a. Source injector tub region 37 has a depth of about 2000A from face 21a and Fermi-tub 22 has a depth (Y f +Y 0 ) of 2200A from the face 21a. The thickness of substrate 21 is about lμm. The source injector tub 37 doping concentration is about 2E18 and the source region 23 doping is about 2.5E19. Figure 2B is a doping profile taken along line 2B-2B' in Figure 1. As shown in Figure 2B, the Fermi-tub 22 has been implanted using a double implantation process which produces a double hump. However, it will be understood by those having skill in the art that multiple implants or other techniques may be used to produce a more uniform doping profile for the Fermi-tub if desired. . The Fermi-tub 22 depth is shown to be about 2200A with an average concentration in the flat region of 1.8E16. The effective humpback substrate doping concentration is about 1E17. Figure 2C illustrates a doping profile along lines 2C-2C of Figure 1. In other words, it is a doping profile from the middle of source region 23 through source injector region 37a through channel 36 and through drain injector region 38a and to the middle of drain 24. These regions are denoted in the Figure 2C as well. Operation of the Injector and Gate Sidewall Spacer Regions Referring now to Figure 3, an enlarged cross section of the area between source 23 and polysilicon gate electrode 28 is illustrated, in order to explain the operation of source injector region 37a and gate sidewall spacer region 41. When gate voltage exceeds source voltage, an electric field E ±i terminates at interface 39 between the injector region 37a and the spacer 41. This field E ±i is produced by the potential difference between the polysilicon gate electrode 28 and the surface of the injector region 37a at interface 39. This electric field creates charge accumulation within depth δ at the surface of the injector 37a, as illustrated in Figure 3. From boundary conditions at the injector-insulator interface 39 and use of the divergence theorem, the following conditions prevail: e s E s =e u E Un (4) where e s is the permittivity of the substrate 21, E s is the electric field in injector 37a at interface 39, e ±i is the permittivity of the spacer region 41 and E iin is the electric field in spacer region 41 at the interface 39. Therefore, the electric field at the surface of the silicon E s is expressed in terms of the different permittivities at the interface and the electric field in the injector insulator, E iin : ■ Eiin (5) When the source 23 is at ground potential and the polysilicon gate electrode 28 is at gate voltage V g above ground (N-channel) , the injector insulator field E iin is expressed as the difference between gate and injector surface potential φ s divided by the effective spacer region insulator thickness jδT in , where V t is the threshold voltage: ( V a ~V t ) - s E„ = β r (6) ιιπ Fringe field factor β is generally greater than one and is due to the length of the fringe field path from the sidewall 28a of the polysilicon gate electrode 28 and the interface 39, as illustrated in Figure 3. For long channel devices β approaches 1.0. For short channel devices 3>1.0. The difference is due to the depth of the charge accumulation layer in the polysilicon gate electrode layer 28 above the insulator interface. For short channel devices this depth increases tending to increase fringe factor β . The gate sidewall spacer 41 may be the same material as the gate insulating layer 26. However in general the permittivity e of the sidewall spacer 41 should be higher than the permittivity e gi of the gate insulating layer 26. Preferably the ratio e ±i /e gi should be at least equal to fringe factor β . If β=l , the increased permittivity acts to lower subthreshold leakage current. A good choice of materials is silicon dioxide (Si0 2 ) for the gate insulator 26 and silicon nitride (Si3N 4 ) for the gate sidewall spacer 41. Based on Equations (5) and (6) the surface electric field E s is: e, , ( ( V -V r t c) -φ TSA σ δ r „ , . . , .. (7) XLjN ac (y) dy βl 'ε o where δ is the depth of the accumulation region, q is the electron charge, and N ac (y) is the depth dependent concentration of the accumulation charge at the surface of the injector. Since Fermi-FET conduction depends on accumulation rather than inversion, a similar expression can be written for the equivalent total accumulation of majority carriers under the gate electrode with low drain voltage. The actual flow depth δ of this charge is controlled by the injection profile. The expression is: A fundamental relationship between surface potential ø s and surface field E s will now be derived. The total charge in the channel region 36 when drain voltage is close to zero, is: δ Q=Z L 0 q j N ch (y) dy (9) O Where N ch (y) is the volume density of channel charge measured in the vertical direction, and δ is the depth of flow charge at the source end of the channel . Using the divergence theorem, the vertical electrical field intensity E s in silicon at the insulator-silicon interface 39 at the source end of the channel is: Comparing Equations (9) and (10) , surface field E s is independent of charge distribution within the depth direction of the channel and only depends on total charge per unit gate area Q* . Thus : E S --^— - 1 (ID s Z L D e s e s The surface potential at the source end of the channel due to this same channel charge distribution is now determined. Using Poisson' s equation, surface potential φ s under the injector insulator at the source end of the channel is : ό y Φ.--2-J fN ch (y) dydy (12) 0 0 It will be shown subsequently that gate induced injection of excess charge into a Fermi channel region at the source - channel interface is quite uniform in flow depth depending on the character of the source injector region 37a. Under these circumstances it is reasonable to assume N ch (y) = N do within flow depth δ. For this condition Equation (12) reduces to: Therefore, from Equation (9), the condition, N ch (y) = N do , leads to the following fundamental relationship between surface potential φ s and surface field E s : s =^E s (14) 2 Stated in words, surface potential near the source end of the channel is the product of half the flow channel depth δ and surface field E s . Equation (14) is substituted into Equation (8) and solved for surface field E s to obtain: Factor δ in (15) corresponds to effective flow depth of carriers in the Tub-FET channel, as shown in Figure 3. Since effective gate capacitance C * , F/cm 2 is given by: Equation (15) can be used to predict drain saturation current and its dependence on structure: Stated in words, saturation current depends on the product of effective gate capacitance C * , channel width Z, carrier velocity V, and gate drive voltage V g -V t . Channel length L 0 does not appear directly in Equation (17) . To reveal the role of channel length, an expression for carrier velocity V in Equation (17) is developed. Equation (17) is rewritten in terms of the product of carrier mobility μ and lateral field E x : I satn =c;zV( V g -V t ) =c Zμ n E- ( V g -V t ) (18) For electrons (19b) 1 L 2L„ V. E_. sat (19c) E- _ ( V g -V t ) μ_ (19d) E„ 2L 0 V sat Substituting Equations (19a) - (19d) into Equation (17) a fundamental solution for drain saturation current is obtained: where Cg* is given by Equation (16) . A similar expression for a P-Channel device is given by: For short N-channel devices and large gate drive, saturation current reduces to a simple equation independent of channel length and carrier mobility: I sat - ' g ZV sa t ( V -V t ) (22) Accordingly, channel length L 0 below about one micron, plays only a minor role in determining drain saturation current of the Fermi-FET. The most fundamental control of saturation current is injector and insulator thickness, their relative permittivities, and effective flow depth δ. The injector tub doping concentration and depth are chosen such that flow depth δ is adjusted to be greater than 200A. Figures 4A and 4B are plots of simulated drain saturation current for N and P-channel Tub-FET's as a function of channel length L 0 and gate insulating layer thickness T gιn . Note the relative insensitivity to N-channel length compared to insulator thickness. P-channel devices are more sensitive to channel length due to lateral field effects on hole velocity. Figure 4C is a plot of simulated gate capacitance versus gate insulating layer thickness for δ = 200A. When the following equation is satisfied in the design of a Tub-FET, the lowest pinch-off voltage with maximum saturation current and the least subthreshold bottom current are obtained for a given injector tub depth. This equation relates the permittivity of the injector 37, spacer 41 and gate insulator 26: From Equation (18) the following is also one of the Tub-FET design considerations: If T iin = T gin then -^i ≥β ( 25 ) e gi For practical high current Fermi-FET designs, one can use silicon nitride (Si 3 N 4 ) for the gate sidewall spacer 41 and silicon dioxide (Si0 2 ) for the gate insulator 26. The permittivity of silicon nitride is 7E-13 F/cm, and silicon dioxide is 3.45E-13 F/cm. The ratio is greater than β~- . S . It will be shown subsequently that very high drive current Fermi-FET' s, 1.6 ma/micron N-channel and 0.8ma/micron P-channel devices, preferably use a 100A silicon nitride gate insulator. Unlike silicon dioxide insulators, silicon nitride insulators have high field strength, 1E7 V/cm, and therefore can be thin while maintaining high gate breakdown voltage while improving insulation integrity with time. For Fermi-FET devices that use a nitride gate insulator, the spacer and injector insulator can be nitride, but an injector and side-wall insulator material with twice the permittivity is preferred. It will also be understood by those having skill in the art that .gate sidewall spacer 41 need not extend directly onto face 21a, but that a thin insulating layer, of a material other than that of the sidewall spacer 41, may be formed at interface 39 between injector 37 and sidewall spacer 41. Figures 5B and Figure 5C are simulations of the drain current performance of 0.8 micron N-Channel high current Fermi-FET devices. Figure 5A is a similar simulation for a state of the art 0.8 micron MOS N- Channel device. Figure 5A depicts 5 Volt MOS technology with a 150A Si0 2 gate insulator. Figure 5B is a simulation of high current Fermi-FET performance with a 140A Si0 2 gate insulator. Figure 5C is a simulation of high current Fermi-FET performed with a 100A silicon nitride gate insulator. In both cases, the drain current and pinch-off properties of high current Fermi-FET devices are far superior to MOS or buried channel technology. Similar dramatic improvement occurs for P-channel high current Fermi-FET devices compared to MOS or buried channel technology. P-channel saturation current is typically half N- channel saturation current, and pinch-off voltage is about twice the N-channel value. Typical bottom current and sub-threshold leakage behavior for the high current Fermi-FET devices of Figures 5B and 4C, are illustrated in Figures 6A and 6B. N-Channel high current Fermi-FET behavior is shown in Figure 6A, and P-channel behavior in Figure 6B. These figures illustrate N-channel current for an 0.8μm transistor per μm width, and P-channel current for an 0.8μm transistor per μm width, respectively. Bottom current is typically 2E-13 A/μm at 5 Volt drain bias at room temperature. This can be lowered to 2E-15 A/μm using the short channel techniques described below. Figure 7 illustrates a worst case simulated comparison plot of 5 Volt N-channel high current Fermi- FET drain current with different side-wall spacer structures 41 (Figure 1) . In all plots, the Si0 2 gate insulator 28 thickness is 132A. The different structures are illustrated in Figures 8A-8C. Figure 8A illustrates Case 1 where the gate sidewall spacer 41 is silicon nitride, while the gate insulator 26 is silicon dioxide. The gate insulator 26 is also shown to slightly overlap the tip of the injector 37a at interface 39. Case 2, Figure 8B, illustrates the gate sidewall spacer 43 as silicon nitride and the gate insulator 26 as silicon dioxide. In this case, the gate insulator 26 does not overlap the source injector region 37a at interface 39, but is contiguous with its edge. Case 3, Figure 8C, illustrates both gate sidewall spacer 41a and gate insulator 43, of silicon dioxide. This structure is also constructed such that the edge of the polysilicon gate 28 slightly overlaps the source injector region 37a at interface 39. In all cases, the effective channel length was 0.71μm. As shown in Figure 7, Case 1 produces the greatest drain saturation current with the least pinch- off voltage. It has also been found that Case 1 yields the lowest sub-threshold bottom current for any drain voltage. Case 1 also satisfies the conditions specified by Equations (24) and (25) . Accordingly, Case 1 is preferred, so that the gate insulating region 26 extends partially over source injector region 37a at interface 39, and the gate sidewall spacer region 41 has greater permittivity than gate insulating region 26. Low Leakage Current Fermi Threshold Field Effect Transistor Referring now to Figures 9A and 9B, Fermi- FETs which have short channels yet produce low leakage current according to the present invention, will now be described. These devices will hereinafter be referred to as "low leakage current Fermi-FETs". The low leakage current Fermi-FET 50 of Figure 9A includes a bottom leakage current control region 51 of first conductivity type, here P conductivity type, and doped at a high concentration relative to the substrate 21. Accordingly, it is designated as P+ in Figure 9A. The low leakage current Fermi-FET 60 of Figure 9B includes extended source and drain injector regions 37a, 38a, which preferably extend to the depth of the Fermi-tub 22. Referring now to Figure 9A, bottom leakage current control region 51 extends across the substrate 21 from between an extension of the facing ends of the source and drain regions 23 and 24, and extends into the substrate from above the depth of the Fermi-tub 22 to below the depth of the Fermi-tub. Preferably, it is located below, and in alignment with the Fermi-channel 36. For consistency with the equations previously described, the depth from the Fermi-channel 36 to the top of the bottom current leakage current control region 51 has been labeled Y 0 . The remainder of the Fermi-FET transistor of Figure 9A is identical with that described in Figure 1, except that a shorter channel is illustrated. It will be understood by those having skill in the art that injector regions 37a and 38a and/or injector tubs 37 and 38 may be omitted, as may the gate sidewall spacer region 41, to provide a low leakage current low capacitance, short channel Fermi-FET without the high current properties of the device of Figure 9A.- The bottom leakage current control region 51 minimizes drain induced injection in short channel Fermi field effect transistors, i.e. those field effect transistors having a channel length of approximately 0.5 μm or less, while maintaining low diffusion depletion capacitance. For example, at 5 volts, leakage current of 3E-13A or less may be maintained. The bottom leakage current control region may be designed using Equation (2) where Y 0 is the depth from the channel to the top of the bottom leakage control region as shown in Figure 9. Factor a is the ratio between the P+ doping of the bottom leakage current control region 51 and the N doping of the Fermi-tub 22. Preferably a is set to about 0.15 within the bottom leakage control region, i.e. below the gate 28. Below the source and drain regions 23 and 24, α is set to about 1.0 to minimize diffusion depletion capacitance. In other words, the doping concentrations of substrate 21 and Fermi-tub 22 are about equal in the regions below the source and drain. Accordingly, for the design parameters described above, and for a channel width of 0.5 micron, the doping concentration in the bottom leakage control region 51 is approximately 5E17 and is deep enough to support partial depletion at the tub-junction region given 5 volt drain or source diffusion potential . Referring now to Figure 9B, an alternate design for bottom leakage control extends the depth of source injector region 37a and drain injector region 38a, preferably to the depth of the Fermi-tub (Y f + Y 0 ) . As shown in Figure 9B, the depth of the entire source injector tub 37 and drain injector tub 38 may be extended, preferably to the depth of the Fermi-tub. The separation distance between the bottom of the injector tubs 37 and 38 and the bottom of the Fermi-tub 22 is preferably less than half the channel length and preferably approaches zero. Under these conditions, injector tubs 37 and 38 have doping concentration of about 1.5E18/cm 3 . The depth of substrate contact region 33b also preferably is extended to approach the Fermi- tub depth. The remainder of the Fermi-FET transistor 60 of Figure 9B is identical with that described in Figure 1, except that a shorter channel is illustrated. Design of 0.5 ym Low Leakage Current Fermi-FET Referring now to Figures 10A-10B, preferred doping profiles and geometries for designing a 0.5μm channel low leakage current Fermi-FET as illustrated in Figure 9A will now be described. It will be understood by those having skill in the art that both N and P channel FETs are fabricated in a similar fashion. All geometries and doping profiles are identical to those described in Figures 2A-2C, except that the length of channel region 36, between facing surfaces of injector regions 37a and 38a, is 0.5μm rather than 0.8μm, and the bottom leakage control current control region 51 is added as already described. It is well known to those having skill in the art how to achieve these doping profiles, using many well known techniques. Figure 10A illustrates a vertical doping profile along line 10A-10A' of Figure 9A and centered about the channel 36. The region to which the profile applies is also labelled at the top of the horizontal axis of Figure 10A. As shown, bottom current leakage current control region 51 extends from 1950A to 4000A in depth from the top face 21a of substrate 21. Accordingly, it is centered about the interface between Fermi-Tub 22 and substrate 21. Doping concentration is 5E17. In contrast with Figures 2A-2C, the substrate 21 is doped at 1E17. Figure 10B illustrates a doping profile along line 10B-10B' of Figure 9A. As shown, bottom leakage current control region 51 extends horizontally between source injector region 37a and drain injection region 38a for about the same length as the channel length, i.e. about 0.5μm. Referring now to Figures 10C-10D, preferred doping profiles and geometries for designing a 0.5μm channel low leakage current Fermi-FET as illustrated in Figure 9B will now be described. It will be understood by those having skill in the art that both N and P channel FETs are fabricated in a similar fashion. All geometries and doping profiles are identical to those described in Figures 2A-2C except that the depths of source injector region 37, drain injector region 38 and substrate contact 33b have been extended to the tub depth of about 2000A, and the length of channel region 36, between facing surfaces of injector regions 37a and 38a, is 0.5μm rather than 0.8μm. Figure IOC illustrates a vertical doping profile along line 10C-10C of Figure 9B and centered about the channel 36. As shown, substrate concentration is about 1E18. Figure 10D illustrates a doping profile along line 10D-10D' of Figure 9B. As shown, the source injector tub 37 extends to the depth of the Fermi-tub. Operation of the Bottom Leakage Current Control Region The operational theory of the bottom leakage current control region 51 of Figure 9A, and the deep injection regions of Figure 9B, to lower leakage current in short channel devices, will now be described. Subthreshold considerations will first be described to define the terms which apply to bottom leakage current. A discussion of how injector tub depth influences bottom leakage current will then be provided as well as a discussion of drain induced injection and drain field threshold lowering. In solving the equations that describe the sub-threshold behavior of the Fermi-FET, some new definitions are needed. Figure 11 graphically illustrates basic behavior. There are four primary features of sub-threshold current behavior. These behavior regions are labeled A, B, and C and D FTL in Figure 11. Point A defines "sub-threshold threshold, V stt . Point B defines normal conduction threshold. Point C defines "bottom leakage current" as influenced by drain voltage. Finally, the arrows for D FTL defines "drain field threshold lowering". Sub-threshold threshold occurs when the injecting gate field is zero. Referring again to Figures 9A and 9B, bottom leakage current dependence on drain voltage is a result of a drain field component that terminates on the source injector diffusion 37a facing the channel 36. This source terminated drain field causes carrier injection into the channel 36. This sub-threshold effect is called "drain induced injection", DII. DII is a characteristic property of majority carrier Fermi-FET and buried channel field effect devices. Below threshold, the majority carrier channel 36 and Fermi-tub region 22 do not contain charge sites that prevent the drain field from extending across the channel region. As a consequence, the drain field can terminate in the source depletion region facing the channel and cause injection. In contrast, minority carrier MOS devices require the substrate region to intercede between the source and drain. Drain field is therefore terminated by ionizing the substrate region adjacent the drain diffusion facing the channel. If the substrate region is completely depleted between the source and drain diffusions, the well known punch-through phenomenon occurs leading to abrupt and high injection current. In summary, MOS device design is troubled by punch-through and threshold problems. Buried channel devices are troubled by both punch-through and DII. However, Fermi-FET devices are troubled only by DII conditions, which can be substantially reduced by the bottom leakage current control region or by increasing the depth of the injector regions 37 and 38. The significant current and speed advantages of the Fermi- FET compared to MOS and buried channel devices far outweigh the design constraints needed to control DII in the former as opposed to eliminating punch-through and threshold troubles in the latter. Both problems become more significant as channel length is shortened. The following analysis describes the impact of injector depth Y d on diverting drain field contour lines in majority carrier Fermi-FET devices. The bottom leakage current control region 51 of Figure 9A or the deep injector tubs of. Figure 9B virtually eliminate DII. Figure 12A illustrates field contour lines that occur when Drain Induced Injection becomes a problem in a low capacitance Fermi-FET, including a Fermi-tub 22 and injectors 37, 38 and no sidewall spacer 41. Specifically, the bottom corner region of the injector tubs contribute to excessive DII due to field crowding there. Figure 12B illustrates proper corrective measures that minimize the effect, by moving the bottom edge of the substrate depletion region 21 closer to the bottom of the source and drain injector tubs 37, 38. The bottom current leakage control region 51 of Figure 9A also accomplishes this result. There exists some depth Y L at the drain injector 38 facing the channel 36 at which the contour integral of the drain electric field terminating on poly gate surface 28 equals the contour integral of the drain field terminating in the substrate region 21. At that point, drain field can terminate at the source 23, facing the channel region. There is an injector tub depth that minimizes the number of field lines that can terminate on the source injector 38. This requirement suggests that α. be less than 1. Typically, α<Lo/2. When designing Fermi-FET devices, Equation (31) derived below, should be considered. Predicted depth Y L should not exceed the depth of the injector, otherwise considerable bottom leakage current will flow from the bottom and corners of the diffusions in the sub- threshold regime. Equation (32) derived below, produces minimum bottom current. Equation (32) also predicts the basic design criteria for the original Fermi-FET as defined by U.S. Patents 4,990,974 and 4,984,043. Specifically, when γ tι _ b = γ o and Y 0 =Y P , then α=l and Y L =Y 0 . In other words, for that case, the diffusion depth Y d should be the same as the Fermi channel depth Y 0 . Y p is the depletion depth in the substrate region. Equation (32) will now be derived. Let ^ be an effective radius for the field lines that terminate on the polysilicon gate electrode 28. Let R 2 be an effective radius for the field lines that terminate in the substrate region 21. Let E d be the drain field along these field lines. The electric field between diffusions is nearly uniform in the sub threshold region as compared to the electric field that terminates in the substrate region below the diffusions. - R 2 E εd = d v w ( 27 ) R 2 - Y tub + Y p~ Y L (28) R = Y L (29) Using Equations (26) - (29) the following expression is obtained: where V w = well potential KT/q ln(N A /Ns) , and V pj = polysilicon gate electrode junction potential KT/q ln(N"/N poly ) If V w =V pj , then: 2 e s tub +γ ~ τ p πe 1, ox (31) γ ιX - Equation (31) is independent of field strength E d . Substrate depletion depth Y p should be small by design. Punch-through is a serious problem for short channel MOS and buried channel devices. High substrate doping is required to minimize the effect. In all FET structures, a second drain induced phenomenon occurs: "drain field threshold lowering", DFTL. Simply explained, DFTL is the result of insulator potential developed near the source end of the channel as a result of the electric field produced by drain voltage that is terminated by the gate when gate voltage is below drain voltage. This drain induced insulator potential is always in a direction to reduce threshold voltage. Punch-through is eliminated by the low capacitance Fermi-FET, however DFTL remains. An expression for r.he change in threshold voltage ΔVt due to DFTL is given below and only applies when drain voltage is greater than gate voltage: where L 0 is channel length and X d is diffusion depth. The effects of DFTL increase by the amount drain voltage exceeds gate voltage and is more pronounced at low gate voltage as channel length is shortened. Thinning down gate insulator thickness proportionately reduces the effect. A method of experimentally measuring the effects of DFTL is to plot sub-threshold behavior of the device. See Figures 6A and 6B. DFTL accounts for the left voltage translation of the rising curve, Log 10 I ch , with increasing drain voltage V d . High Saturation Current Fermi-FET Referring now to Figure 13, a high saturation current Fermi-FET according to the present invention is illustrated. The high saturation current Fermi-FET 200 is similar to Fermi-FET 20 of Figure 1 except that source tub regions 37 and drain tub regions 38 are not present. However, it will be understood by those having skill in the art that these regions may be used as described previously. Also, gate electrode layer 28 includes a first layer 28b of first conductivity type, here P type and a second layer 28c of second conductivity type, here N++ type according to application Serial No. 08/087,509 entitled Field Effect Transistor Having Poly crystalline Silicon Gate Junction to inventors Vinal and Dennen, and assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. However, it will be understood by those having skill in the art that the source and drain tub regions 37 and 38 and/or a single layer gate 28 may also be used. According to the invention, the second conductivity doping (here N++) of the source region 23 adjacent channel 36 is maintained at a minimum which is sufficiently high to maximize the saturation current of the field effect transistor. Preferably, the doping of the source region 23 and the drain region 24 facing channel 36 is maintained at this minimum doping, and most preferably the doping of the entire source and drain regions 23 and 24 respectively are maintained at this minimum doping. Of course, greater doping levels may be used, but will do little to enhance the saturation current of the transistor. The concentration in the channel region 36 may be greater than or less than that of the tub region 22, and is less than that of the source and drain regions 23 and 24. The ends of the channel region 36 preferably abut the source and drain diffusions 23 and 24, or the source and drain tubs if present. The source and drain regions are at least as deep as the channel 36 and preferably less than the depth of the tub 22. The substrate region 21 is the same conductivity tape as the doped polycrystalline silicon gate 28b adjacent the gate insulator 26. The substrate 21 has a doping concentration which is higher than, and preferably at least four times higher than, the tub 22 doping concentration. It will now be shown that the drain saturation current of the Fermi-FET transistor 200 is controlled by the diffusion doping concentration of the source 23 and drain 24 adjacent the channel 36. The highest drain saturation current is reached, for a given doping concentration, when no perpendicular electric field is allowed to cross the channel 36. Thus, for a given channel length, the diffusion concentration has a minimum value beyond which drain saturation current ceases to increase. Accordingly, it is not necessary to fabricate very short channel Tub-FETs to achieve high drive current. For example, if a Tub-FET with 0.8 micron channel length is optimized for maximum drive current, the fabrication of devices with a shorter channel does little to increase drive current. Drain saturation currents of 16 amperes per centimeter and 9 amperes per centimeter for N and P channel devices, respectively, can be achieved from Tub-FET device designs using power supply voltages of magnitude value between 0 and 5 volts. To achieve these current levels, gate insulator layer 26 thickness of 100A Silicon Nitride or 50A Silicon Dioxide or other gate insulating materials with equivalent gate capacitance effects, is required. Gate capacitance of T-FETs depends on mobile channel charge Q ch per unit gate voltage (Vg-Vt) . Gate capacitance is therefore proportional to accumulation efficiency. It has been demonstrated according to the invention that high accumulation efficiency can occur if excess charge can be stored in the source and/or drain diffusion injection area facing the channel. Thus, Where φ x is the flat band potential between the source/drain diffusions and the channel, KT/q = 26 mV at room temperature, N do is the source doping concentration and preferably also the drain doping concentration, facing channel 36, and N ch is the doping concentration of channel 36. This is graphically illustrated in Figure 14. The minimum depth X d of the diffusion depletion region is approximated below. The accumulation free charge is identical in value, and opposite in sign, to the total charge in the diffusion depletion region facing the channel : Where e s is the permittivity of the substrate and q is 1.6xl0 ~19 coulombs. Figure 15 illustrates an equivalent volume of excess carriers available within the reservoir volume that is free to be accumulated into the channel region. In Figure 15, Y f is the depth of channel 36 and Z is the width of channel 36. The following discussion ignores free charge. This component of free charge is discussed subsequently. The maximum reservoir of free accumulatable charge Q r , is: Q r =qN do X d Y f Z (35) Substituting Equation (34) for X d one obtains Where φ x is given by Equation (33) . Equation (36) defines the available excess charge for injection. When maximum gate voltage V^ x is applied, above the threshold value, this total available charge must be capable of filling up the channel. When both the source and drain regions are at ground potential, each accumulation reservoir must be capable of filling up half of the channel. As free charge flows into the channel, carriers diffuse across the N++/N ch junction to replace them. The effective channel volume V ch that is filled per diffusion is: Therefore the charge transferred to the channel is : where N chex = Channel excess carrier concentration δ = flow depth of excess carriers. L 0 = Channel length Z = channel width It can be shown that channel charge is also related to gate capacitance and gate drive voltage (Vg- Vt) . The following equality exists: C;ZL 0 ( V g -V t ) =qN cheχ δZL σ (39 ) Therefore ^ che ^= ~ ; {v -v t ) =Q c * h (4o; where Q c * h is the charge per unit volume. A basic expression for channel saturation current I sat can be written as follows: I sat = ~ g * ( V g -V t ) ZV L (41) where V L is the lateral velocity. The conditions that control lateral velocity V L are discussed below. Substituting Equation (40) into Equation (38) , an important expression that defines accumulated channel charge due to the source diffusion is found: Q ch -^-ZL 0 ( V g - Vt ) ( 42 ) Equating Equation (36) to the available channel charge in Equation (42) : VV g --VV t . )) (43 ) Equation (43 ) can be solved for actual gate capacitance C g in terms of the diffusion impurity concentration N do and the depth Y f of the channel region : 2 Y^2 e s φ x qN ^ where: Y f = Depth of the Fermi channel adjacent the source and drain diffusions N do = Average diffusion impurity concentration in depth from the substrate-insulator interface 21a to the bottom of the Fermi channel. L 0 = Channel length e s = Permittivity of substrate φ x = Given by Equation (33) v gma χ = Maximum gate voltage anticipated V t = Threshold voltage Gate capacitance has a maximum value as determined by independent analysis and is given below: 2e i e s c 'grmax T • O o X x ι , δ -> 2e s εr o o x x+δ e i (451 ® 2 e s The ratio of Equation (44) to Equation (45) provides an expression for gate capacitance factor G f : According to Equation (41) , maximum saturation current occurs for a given lateral velocity, when gate capacitance factor G f = 1.0. Figures 16A and 16B graphically illustrate Equation (46) as a function of source/drain diffusion concentration N do for different channel lengths L 0 , given Y f - 600A, gmax = 5V, V t = 0.8V, flow depth δ = 120A, and T ox = 100A for Figure 16A and 140A for Figure 16B. Figures 16A and 16B reveal that there is a critical concentration N do that is required to achieve maximum saturation current and this value is different for different channel lengths L 0 . This maximum occurs when gate capacitance factor G f = 1.0. this maximum depends primarily on channel length L 0 and insulator thickness T ox . The following expression defines this criticality. 2e s M When designing Fermi Tub-FETs, Equation (47) should be applied to the longest channel L 0 possible. Under these circumstances, Tub-FETs with shorter channel length will have essentially the same drain saturation current for the same gate voltage. Very little is to be gained in terms of drive current by making short channel devices. Fermi Tub-FETs designed with 0.8 micron channel length or less have much higher drive current for a given gate voltage than MOS or MOS buried channel device designs at any channel length. Referring now to Figure 27, a second embodiment of a high saturation current Fermi-FET according to the present invention is illustrated. The high saturation current Fermi-FET 300 of Figure 27 is similar to Fermi-FET 200 of Figure 13 except that source doping gradient region 50a, and preferably drain doping gradient region 50b, are added between the source region 23 and the channel 36 and between the drain region 24 and the channel 36, respectively. The source doping gradient region 50a, and preferably the drain doping gradient region.50b, are doped at a doping gradient which decreases from the relatively high source/drain doping concentration adjacent the source and drain regions to the relatively low doping concentration of channel 36 adjacent channel 36. It has been found, according to the invention, that the source doping gradient region 50a, and the drain doping region 50b, preferably have a thickness S of at least 300A in order to support high saturation current in the Tub-FET 300. Also preferably, as shown in Figure 27, the gate insulating region 26 and the gate electrode 28, overlap the source and drain doping gradient regions 50a and 50b. As also shown in Figure 27, source doping gradient region 50a and drain doping gradient region 50b preferably surround source 23 and drain 24, respectively. The theoretical reasons as to why high saturation currents are provided when the source and drain gradient regions 50a and 50b respectively, exceed 300A in thickness will now be described. It will also be shown that when used with a source and drain gradient region, a minimum source and drain doping level is as already described in Equation (47) with a substitution of the source and drain depth X_ rather than the Fermi channel depth Y f , when the source and drain are deeper than the Fermi channel; i.e. when X is greater than Y f . It has already been shown that high accumulation efficiency occurs with proper access to free charge stored in the diffusion gradient facing the Fermi-Tub channel region 36 between source and drain diffusions 23 and 24 respectively. At threshold, the Fermi-Tub region 22 may be completely depleted from the bottom to the substrate surface 21a facing the gate insulator as a result of the P-N junction between the Fermi-Tub 22 and substrate 21. Depleting the Fermi-Tub in this manner, eliminates any junction electric field from crossing the surface channel region 36 during majority carrier conduction. The source/drain diffusion concentration N do and gradient depth S required to provide an adequate reservoir of charge at the edge of the diffusion in the depletion environment will now be determined. Given maximum gate voltage above threshold, an adequate charge reservoir will fill half the channel volume of length L 0 with sufficient majority carriers to achieve the limiting gate capacitance value C * , where C g is defined as : c; ~ - Σ≡ + . e i 2e s Where ; T ox = gate insulator 26 thickness δ = carrier flow depth e s = substrate 21 permittivity e ± = insulator 26 permittivity Referring to Figure 27, when the gate electrode 29 is at threshold or below, the substrate-Tub junction completely depletes the Fermi-Tub region up to the gate insulator 26 and a portion of the perimeter of the doping gradient regions 50a, 50b facing the Fermi-Tub. The diffusion impurity concentration N do and gradient thickness S must be sufficient to prevent the entire diffusion gradient thickness S from being consumed during depletion. The following analysis develops a fundamental expression that defines the requirements for diffusion design to achieve maximum drain saturation current from the Fermi FET for a given maximum gate voltage. . Figure 28 illustrates a diffusion perimeter whose concentration decreases discretely in steps from higher to lower concentration. This discrete model is useful in obtaining an expression for the diffusion design. Figure 28 illustrates that a dipole charge configuration occurs at each step. Bound positive charge is due to depletion in the diffusion region, and that free negative charge is lightly bound to the step junction. Charge neutrality must be observed at each step junction. The gate 28 overlaps the doping gradient regions 50a, 50b as shown in the Figure 28. As a result of the Tub-substrate junction, the depletion penetration distance into the doping gradient distance S is defined as X in the Figure 28. When depletion occurs, penetration distance X must be less than distance S. All free charge in distance X is unavailable for accumulation due to carrier diffusion across the substrate junction that is required to satisfy charge neutrality requirements there. Free charge is available in interval S-X to be accumulated within the surface channel when gate voltage is above threshold. The total undepleted reservoir of distributed charge can be calculated from an abrupt junction between the Tub and diffusion is shown in Figure 29 Qtotal =qN do X j ZY d (48) Where; X j = depth of the source/drain diffusion 23/24 Y d = depletion depth in the diffusion Z = channel width N d0 = maximum source/drain diffusion 23/24 concentration The total potential developed across the N d0 -N tub junction is: Where; E ( 0) =qN do Y do /e (50) Free charge is assumed to occupy the same depth Y d . Combining Equations (49) and (50) produces: Solving for Y do : Thus, the maximum available reservoir charge Q r is: This total charge is distributed along thickness S of the doping gradient region. Therefore free charge density N fc =Y do N do /S exists along the doping gradient region thickness S. When the doping gradient is depleted by distance X, Figure 28, as a result of depletion within the Tub from the Tub-substrate P-N j unction, the reservoir of free charge Q r left available to fill half of the Fermi channel is : Where ; N FwrC d-*-x<*-= Y J. d r oN-"_ do /; Based on the definition of free charge density within the doping gradient, free charge Q r is: Q^qN^ZX j Y^-^L (55) Substituting Equation (52) into Equation (55) a fundamental expression for the reservoir of free charge available to fill half the Fermi-channel may be found. Note that when drain and source voltage are both zero, the free charge in each doping gradient region of depth X- j fills half the channel volume when gate voltage is above threshold. One should not depend on free charge at the bottom of the diffusion to fill the channel because of transit time considerations. Equating the reservoir of free charge Q r to that required to fill half of the channel L 0 /2 given (Vg-Vt) at the maximum value, yields: (57) Solving Equation (57) for gate capacitance per square cm C * , a fundamental expression that defines gate capacitance is obtained: Next, penetration distance X into the doping gradient region thickness S as a result of depletion by the Tub- substrate P-N Junction will be determined. During the depletion process, charge must be conserved: For purposes of this analysis, the doping gradient region is assumed to be linear in X i.e. : N d (x) N do~ N tub X+N, tub .60 ) and Substitution of Equation (60) into Equation (59) produces : ( 62 ) The solution yields a quadratic in x: The solution for Equation (63) is Xdo ~ Ntub χ2 +χ _ 2 e _W. N d. o =o ( 63 ) 2SN, tub N Q N ub Ndo + a ( 64 ) Thus, Equation (64) is the solution for depletion penetration depth X into the doping gradient region. Note that X is a factor in Equation (58) . Equation (64) is used in combination with Equation (58) to determine gate capacitance C * , and therefore defines drain saturation current for the maximum anticipated gate voltage V^-.. The proper source drain design is realized for a given channel length L 0 when Equation (58) reaches maximum gate capacitance C^,^ . It may be seen from this analysis that gate capacitance C g and drain saturation current I sat are very low if inadequate channel charge is available for a given gate voltage V g above threshold voltage V t . This follows since Q c * h =C g * ( V g -V t ) and I sat =C * ( V g -V t ) V L Z . Figure 30 illustrates saturation current for an 0.8 micron N-Channel Fermi-FET with 50A silicon dioxide or 100A silicon nitride gate insulator thickness plotted as a function of doping gradient region thickness S in Angstrom units. Source/drain doping concentration N do is the running parameter with 1500A source/drain depth in all cases. It is significant to note that saturation current is virtually independent of gradient distance S greater than 300A, irrespective of the concentration N do of the diffusion. It is also shown that saturation current increases as diffusion concentration increases. Figure 31 illustrates saturation current for the same structure plotted as a function of source/drain doping concentration given doping gradient region thickness S=300A or greater. Channel length L 0 is running parameter in Figure 31. It is shown that saturation current reaches a maximum value of about 17 A/cm given a gate voltage of 5 volts and a threshold voltage of 0.8 volts. Source/drain doping concentration above a critical value does not increase saturation current since the maximum value for gate capacitance C g has been achieved. Thin gate insulators place the highest demands on source/drain doping concentration to achieve maximum saturation current consistent with the chosen insulator thickness . Shortening the channel length of Fermi-FET devices relaxes the source/drain doping concentration requirements for the same maximum current . There is no other significant reason to shorten the channel length of a Fermi-FET. Equation (58) is identical to Equation (47) with the exception that diffusion depth X j takes the place of Fermi depth Y f and (S-X) /S = 0.95 if S>300A. See Equation (32) . Therefore, the minimum diffusion concentration required to reach maximum current is identical to Equation (47) with X j substituted for Y f . Diffusion depth X j may be used in place of Fermi depth Y f for all cases where X j >Y f . Fermi-FET with Reduced Threshold Voltage Referring again to Figure 13, channel 36 of Fermi-FET 200 has depth Y £ , typically about 600A-700A, and a doping concentration N ch per cubic centimeter. Figure 17 illustrates the perpendicular electric field diagram for the structure of Figure 13. The Tub depth Y tub is defined by the following equation: γ tu = Y o + Y f (65) where; where N s, ub Substrate impurity concentration N, tub = Tub impurity concentration N ± = Intrinsic carrier concentration e s = Permittivity of substrate material KT/q 26 millivolts at room temperature The depth Y p of the depletion region in the substrate 21 is expressed as: Referring to Figure 17, at threshold, the channel region Y f is depleted when gate voltage V g =V t . At excess carrier threshold, V g >V t , the channel is charge neutral and the perpendicular electric field from the substrate-Tub junction remains zero across the channel region independent of the density of excess conduction carriers accumulated there as gate voltage increases above the excess carrier threshold V tec . The expression that defines excess carrier threshold V tec is : Where, N pol is the doping concentration in the polysilicon gate 28b at the polysilicon gate - insulator interface. Threshold voltage V t is defined as follows: where compensation voltage V corap is the sum of the surface potential loss φ s , the shaded triangle Figure 17, and a potential developed across the gate insulator V„ Φ_ ^rj ; and (71) 2 e„ f V v ox =^_ * Yf f T ■ * ■ ox (72.: Thus, the final expression for threshold voltage can be written as : Equation (73) shows that threshold voltage can be modified from the basic term V tec , Equation (52) , by the depth Y f of the channel and channel impurity concentration N ch . Insulator thickness has a secondary effect . Note the basic threshold voltage term V tec can be controlled by the doping concentration N P0L in the polycrystalline silicon gate. Thus Where: A V t = the change in threshold voltage from twice the Fermi potential It is appropriate to confine the channel depth Y f to a fixed value, approximately 600A, independent of the implanted impurity concentration N ch . It has been shown in the previous section that channel depth Y f is also one factor that determines drain saturation current. Fixing the value of channel depth Y f allows independent control of saturation current and threshold voltage. In order to achieve very high drive currents, the doping concentration N ch in the Fermi- channel Y f , should be less than 5E16/cm 3 . Otherwise carrier mobility rapidly decreases below the value required to support high drive current at 5V. Figure 18 is a plot of Equation (73) for T ox = 100A, N pol = 2E19, and N tub =2E16. The abscissa is channel concentration. The ordinate is threshold voltage. The three running parameters are channel depth, 600A, 700A, and 800A. From Equation (73) , threshold voltage is independent of substrate concentration N sub . However, the depth of the Tub does depend on substrate concentration as per Equation (66) , and threshold, twice the Fermi potential of the substrate, is set when the product N^- N Poly equal N sub 2 . Thus, as illustrated in Figure 18, threshold voltage can be lowered by increasing the doping concentration in the channel, or conversely, increased by lowering channel concentration. Lowering threshold voltage may be desirable if operation is contemplated at 3.3 Volts or less. Sub-threshold threshold differs from threshold voltage by twice the Fermi potential of the channel, 2 KT/q [In(N^/N ] . This is the voltage difference between points A and B of Figure 11. Leakage current is very sensitive to threshold voltage. A typical sub-threshold slope is 90mV per decade. For minimum sub-threshold leakage current, sub-threshold threshold should occur when gate voltage is zero or slightly positive. Sub micron channel length FET devices suffer in the sub-threshold region (zero gate volt region) . The voltage difference between sub-threshold threshold and threshold conditions is typically 790mV. If a short channel device requires a 400mV threshold voltage, for example, the zero gate voltage leakage will be about 5 decades above IE-13 A/micron or about IE-8 A/micron in value. This leakage current is too high to be acceptable for VLSI technology. Accordingly, the threshold voltage of a Fermi-FET may be lowered, while still maintaining zero static electric field perpendicular to the substrate surface at the depth of the Fermi channel, by choosing a channel and tub depth which provides zero perpendicular static electric field and by providing a channel doping concentration which is greater than that specified in Equation (73) . It will be understood by those having skill in the art that channel doping concentration cannot be increased indefinitely. In particular, at channel concentrations above about 5xl0 16 , carrier mobility begins to drop and the saturation current of the device begins to drop. However, channel doping concentration may be increased from that doping concentration which produces a threshold voltage which is twice the Fermi potential up to about a concentration of 5xl0 16 , to lower the threshold voltage of the Fermi-FET device when this is deemed necessary or desirable. It will also be understood by those having skill in the art that for a given Fermi channel depth, such as 600A, the threshold voltage and the saturation current may be adjusted independently. Saturation current may be adjusted by increasing the doping concentration of the source and drain diffusions adjacent the channel as described in the previous section. Threshold voltage may be adjusted independently by increasing the doping concentration of the channel. Thus, independent control is provided. Comparison of MOSFET and Fermi-FET In any prior art FET device, with the exception of the Fermi-FET technology, there is a perpendicular field in addition to the lateral field that traverses the channel . The lateral electric field E λ is due to drain to source potential directed along the channel between the source and drain. The perpendicular field in MOS devices originates from immobile charge developed in the depleted substrate region below the gate insulator when gate voltage reaches the threshold value. This perpendicular electric field crosses the inverted minority carrier MOS channel region and is a consequence of creating the inversion layer. The Fermi-FET technology transports majority carriers in a Fermi-channel whose doping type is the same as the Fermi-Tub and the source and drain regions. Fermi-FET design precludes any perpendicular electric field from crossing the channel during excess majority carrier flow between the source and drain, other than that produced by the majority carriers themselves. This section describes a closed form expression for FET drain saturation current that includes the influence of both lateral and intrinsic perpendicular electric fields. It will be demonstrated that large values of drain saturation current, greater than 7A/cm for N-channel devices and 4A/cm for P- channel devices, while maintaining low leakage current of about IE-13 A/micron or less, can only be achieved by Fermi-FET designs that eliminate the perpendicular electric field component. A Fermi-FET conducts by accumulation and is shut off by inversion. A MOSFET conducts by inversion and is shut off by accumulation. The difference in potential between inversion and accumulation is twice the Fermi potential of the channel region in both cases. It has been shown in Equation (41) that saturation current of any FET device can be described by the following fundamental equation: I βat =C; ( V g -V t ) V L ZCOSβ (74) Where; C g = Gate capacitance/cm 2 due to mobile charge V g = Gate voltage V t = Threshold voltage V L = Lateral Velocity Z = Channel width θ = Angle between the vector field and lateral direction of carrier flow. Equation (74) does not explicitly reveal the effects of channel length L 0 . Equation (74) was derived with the benefit of a first principle notion that charge is the product of capacitance and Voltage i.e. Q=CV, and that current is dQ/dt. There are three fundamental parameters in Equation (74) , other than gate voltage Vg and threshold voltage Vt, that determine the magnitude of current flow. These parameters are gate capacitance C * , lateral velocity V L and angle θ. The lateral velocity term accounts for the roles of carrier mobility U x , channel length L 0 , saturation velocity V sat and gate voltage V g in determining the transconductance character of drain saturation current. The perpendicular electric field regulates angle θ. The gate capacitance term C g applies only to mobile charge and accounts for the effects of insulator thickness and carrier flow depth that control the maximum amount of charge that can flow in the channel per unit gate voltage. In MOSFETs, there is a substantial immobile charge below the gate when gate voltage reaches threshold. This charge resides in the depleted substrate region below the gate and is necessary to create the minority carrier inversion layer. There is a gate capacitance C go =Q im / V t associated with this immobile charge Q im . There is also a gate capacitance factor C gmax that accounts for mobile charge flowing in the channel : (75) where; T ox = Depth of the gate insulator δ = Mobile carrier flow depth e__ = Permittivity of the gate insulator e s = Permittivity of the semiconductor For a given gate voltage above threshold, the total charge supported by the MOS gate is: Where C go ~e i / { 2 Tox) , and Mobile charge is the second term of Equation (76) . Total gate capacitance for the Fermi-FET is only C^,^ when gate voltage is above threshold. Only mobile charge is in the channel region. The rate of change of gate capacitance for the MOS device is positive for gate voltage rising from ground to threshold voltage while negative for the Fermi-FET. This property of the Fermi-FET provides for excellent noise rejection in high speed digital systems. A closed form expression for lateral mobility that includes the influence of the perpendicular electric field E p will now be derived. The expression is based upon the realization that saturation velocity is a vector quantity. This fundamental realization suggests that drift velocity can only reach the thermal saturation value in the vector field direction. Since there cannot be a net perpendicular component of velocity in the FET channel, other than hot electrons, the effects of the perpendicular field produce a dampening effect on the lateral component of velocity. The damping factor is Cosd where θ is the angle between the vector field direction and the channel flow direction. Lateral velocity, that gives rise to drain current in FET devices, is thus ViCosθ where θ is the angle between the vector field and the lateral field component. This is illustrated by Figure 19. Lateral mobile dependence on lateral field effects is known. Equation (77a) defines lateral mobility of excess electrons and Equation (77b) defines lateral mobility for holes. Lateral velocity is the product of lateral field E λ and lateral mobility μ . E λ is the lateral drain field, at the source end of the channel in an excess carrier environment, due to pinch-off voltage, and E c is the critical lateral field where for example, hole mobility is half its low field value. Thus, E =∑≡l- (78) Where μ 0 is the low field mobility of the doped semiconductor; and V sat is thermal saturation velocity at temperature T. Equation (78) is true in the vector direction as well as the lateral direction. Equations (77a) and (77b) must be modified to reflect true lateral mobility in the channel by including the effects of the perpendicular field crossing the channel. The lateral component of mobility and velocity is simply the value in the vector direction multiplied by cosθ . Using the following definitions: and Tanβ=E /E 1 , (80: Cosθ has the following solution in terms of the perpendicular and horizontal electric field components in the channel region: Using Equation (78) we can modify Equations (77a) and (77b) to reflect true lateral mobility in the channel: Since lateral velocity is the product of lateral field and lateral mobility, general expressions for lateral velocity for both holes and electrons may be written as follows : In general, lateral velocity for holes and electrons can be expressed as: μ po E Cθsθ V LP- - E ~ -. ' ( 84d) c ) Where V -V E, -— -—- is the lateral field due to drain 1 2L„ pinch-off; Φf Q Nεub E P~ is the perpendicular field required to support MOS inversion; V s. atp _ 'cp • po E h = V dd /L 0 is the lateral field due to drain voltage; N sub = Substrate concentration, N ± for Fermi FET; Φ_ KT I, Jn N t εub Fermi Potential; β = τan -- \ - ; J~ . L 0 = Channel length V dd = Supply voltage Using Equations (84a) and (84b) , Figures 20A and 2OB are plots of maximum lateral velocity for electrons and holes, respectively. Velocity in both cases is plotted as a function of drain voltage, (electric field = V d /L 0 ) , and substrate concentration N sub in the range 2E16 to 2E17 for the MOS device and N sub = N ± for the Fermi FET. As shown, that lateral electron velocity reaches almost the saturation value for the Fermi-FET when gate voltage is 5 Volts. All excess carrier flow is below the surface and therefore the perpendicular field produced by the MOS device has nearly the maximum value E p across the carrier flow depth δ. In both Figures 20A and 2OB, lateral majority carrier velocity in the Tub-FET reaches the maximum value and is the result of no perpendicular electric field across the channel . The other curves correspond to MOS devices with substrate doping concentrations in the range of 2E16 to 2E17 that produce perpendicular electric field at threshold and above. For the minority carrier MOS structure, the perpendicular field is needed to create the inversion mechanism. Angle θ is affected by drain voltage, not pinch-off voltage. It is for this reason that MOS device drain saturation current is less than half the Tub-FET value. Figures 21A and 21B illustrate the factor Cosθ for the conditions given above. Channel length L 0 is 0.8 micron for Figure 21A and is 0.5 micron for Figure 21B. In both cases Cosθ has a maximum value of 1.0 only for the Fermi FET. Since drain saturation current I εat =C * ( V g -V t ) V-Z Cosθ, the Fermi FET realizes the maximum drive current capabilities. For MOS devices, there is a relationship between perpendicular field E p and threshold voltage V t . Both quantities involve substrate doping concentration. This relationship will now be derived so that drain saturation current for the MOS device can be compared with the Fermi-FET value. The sum of potential taken along a contour from the center of the gate electrode to the substrate contact of an N-channel MOS device is given below: ( N ε m u ι b h N *p, oly -DFTL ( 85 ] g where : Φs is the rise in potential in the perpendicular direction across the substrate region below the gate; N s, ub substrate concentration; N p°iy " doping concentration in the polygate; DFTL = potential drop across the gate insulator at the source end of the channel due to the perpendicular component of the drain field; V 0 potential developed across the gate insulator due to a perpendicular electric field. If a P-type polycrystalline silicon gate is used, the solution for a P-channel device is identical to Equation (85) , except for polarity of terms. Using the divergence theorem and Poisson's equation, expressions for V ox and φ s are given below: ( 86a) where E s , is the perpendicular surface electric field in the substrate below the insulator. qN c E- "cJ h δ QXεub Y i ( 86b) and N tc is the volume density of trapped charge in the gate insulator. The positive sign in Equation (86a) applies to trapped electrons. Substitution gives: +gN sui _r i± gN tc r ox ] (87! where C ± = insulator capacitance e ± /T ox . δ = carrier flow depth Yi = Substrate depletion depth under the gate The factors qN ch δ, qN sub Y ± and qN tc T ox can be written in terms of charge density as follows. QN ch δ = Q c * h , Channel charge density qN sub Y i =Q sUb , Substrate depletion charge density qN tc T oie =Q tc , Density of trapped charge in gate insulator. Substituting these expressions into Equation (87) and collecting terms yields the following expression for oxide potential drop V ox : Surface potential φ s has the following expression: *--°^ 2 . *o: ~-iτ. ■ (89 ) Based on the above definitions for V ox and φ , the expression for gate voltage, Equation (85) can be expanded: KT ln ( NsubNpoly -DFTL oo: Q The first voltage term in Equation (90) is due to mobile charge. The second and third terms are due to immobile charge in the substrate and trapped charge in the gate insulator respectively. The final terms are flat-band voltage and a voltage developed across the insulator due to a perpendicular component of the drain field. This effect is called DFTL, Drain Field Threshold Lowering. From Equation (90) threshold voltage is: When hard inversion occurs, the depth of the depletion region below the insulator is : Aφ f fe σ s (92) Y X qNsuj Using Equation (92) and the definition for charge density, the following expression defines threshold voltage: QN t t c cT t v t ~^ f ' ^sub +2φ. -^ ox C Since , substitution yields : ( 94 ) The trapped oxide charge term in Equation (94) will now be discussed. If trapped charge is negative, the positive sign applies. If trapped charge is positive, the negative sign applies. The contribution to threshold voltage due to trapped charge depends on the square of the gate insulator thickness, qN t t c„T^ o, x V, tc - (95) The volume and area density of trapped charge that is required to alter threshold voltage by lOOmv given Tox- 100A is --2 . 15E17/cm 3 or 3 .6Ell/cm z It is clear from Equation (95) that substantial trapped charge is required before threshold voltage can be significantly altered. From this analysis of threshold voltage and its dependence on trapped charge, it is possible to deduce the actual mechanism responsible for the so called "hot electron" problem with MOS devices. The perpendicular electric field at the insulator-substrate interface produced by the depleted substrate region in MOS devices greatly influences the probability of electron trapping in the gate insulator, thereby producing "hot electrons". Returning to the determination of threshold voltage for a MOSFET, the expression for threshold voltage, Equation (94) is modified by extracting the log term and defining a net threshold voltage v tnet = v t +κτ / Q ln (N poly /N εub ) . Thus , Equation ( 94 ) reduces to : In order to find a fundamental expression for the perpendicular field Ep, Equation (96) is solved for substrate concentration N sub . E p at the source end of the channel is given as follows in terms of substrate doping concentration N sub : Thus solving Equation ( 96 ) for N sub : Substituting Equation (98) into Equation (97) we obtain the expression for the perpendicular electric field E p for the MOS device: ( 99 ] It can be seen that the trapped charge expression appears in the perpendicular field equation and that the drain field threshold term does not. The negative sign corresponds to electron trapping. Thus, electron trapping lowers the perpendicular MOS electric field. In other words, trapped charge can influence drain saturation current by influencing Cos . The perpendicular field in a typical MOS device required to achieve inversion is in the order of 1E5 Volts/cm, large enough to support charge trapping in the insulator. The trapped charge can easily modify this value by 10%. Equation (99) must be used in determining MOS drain saturation current. The value for threshold voltage must not be less than twice the Fermi potential of the channel region, otherwise leakage current will increase one decade for each threshold increment of 80mV below 2Φ f . Equation (99) implies an appropriate value for substrate concentration. It can be shown that Equation (99) can be used without fear of violating MOS punchthrough conditions for all channel lengths down to 0.15 micron. In summary, Equation (99) is very revealing. In its simplest form, the intensity of the MOS perpendicular field varies directly with threshold voltage and inversely with gate insulator thickness . MOS scaling theory would suggest holding the ratio V t /T ox constant. However, this condition fails because sub-threshold leakage current will increase one decade for each increment of 80mV of threshold voltage-below twice the Fermi potential. Saturation current is predicted by Equation (99) to increase by lowering threshold voltage V t . However leakage current will dramatically increase. Figure 22A is a cross-section of a typical N- channel MOS device with "lightly doped" diffusions, LDD. Light doping for MOS devices is in the order of 1E19 impurity ions/cm 3 . The perpendicular electric field diagram for this MOS device at threshold is shown in Figure 22B. Y defines the depth of the depleted region below the MOS gate at the threshold. Also shown is a flow depth δ below the insulator-substrate junction, called the inversion depth. Excess injected carriers flowing within this depth experience a substantial perpendicular electric field component with the consequence of lowering lateral carrier velocity. Figure 23A is a cross-section of a typical P type "buried channel" MOS device with lightly doped diffusions. The perpendicular electric field diagram shown in Figure 23B for a typical buried channel deice is drawn for threshold conditions. The depth of the depleted substrate region below the gate insulator corresponds to gate voltage at threshold. The buried channel modifies threshold voltage by lowering the perpendicular field crossing the insulator. Figure 24 illustrates a perpendicular electric field diagram for the Fermi-FET of Figure 13. For all gate voltages above threshold no perpendicular electric field is allowed to traverse the entire depth of the Fermi channel, labeled Y f in Figure 24. Consequently, accumulated excess majority carriers flowing in this region have maximum lateral mobility. Furthermore, excess carrier threshold voltage is independent of gate insulator thickness. This fact is due to the absence of any static perpendicular field near threshold. Therefore, Fermi-FET drive current capabilities can be chosen by oxide thickness and diffusion concentration without consideration or modification of other structural design considerations Fermi Tub-FET saturation current for an N- channel device is : For a P-channel device For all of the above equations, the following definitions apply: , maximum gate capacitance, F/cm 2 δ = Flow depth of excess injected carriers T Gate insulator thickness e s = Permittivity of silicon e± = Permittivity of the gate insulator V sa t : Thermal saturation velocity v t = Threshold voltage Lo = Channel length Z - Channel width β∞ = Low field mobility of species x N sub : Substrate doping concentration Figures 25A-25C compare N-MOS and N-Fermi-FET drain saturation current as a function of gate voltage V g and channel length L 0 as a running parameter. Figures 26A-26C are for P-channel technology. In all plots, threshold voltage is twice the Fermi potential or about 0.8V. This threshold voltage guarantees minimum leakage current i.e. less than 1E-13 Amps per micron when gate voltage is at ground potential. Gate insulator thickness is 14OA of Si0 2 in Figures 25A and 26A, 100A in Figures 25B and 26B and 50A in Figures 25C and 26C. In Figures 25C and 26C, drain supply voltage is 3 Volts rather than 5 Volts as is in the other figures. It is clear from the figures that only the Fermi FET can produce saturation currents in excess of 7 A/cm for N-channel devices and 4A/cm or greater for P-channel devices. These large currents are attributed to no perpendicular field crossing the flow channel; i.e. Cosθ approaches a unity value. Bounded Tub Fermi-FET Referring now to Figures 33A and 33B, a cross-sectional view of a portion of the Fermi-FET 20 of Figure 1 and a corresponding electric field diagram are shown. Like numbers refer to like elements of Figure 1. It will be understood that Figure 33A does not illustrate source and drain regions 23 and 24 respectively. It will also be understood by those having skill in the art that the bounded Fermi-FET may not include source and drain injector regions 37, 38, or sidewall spacer 41. According to the invention, Fermi-Tub depth and doping concentration are bounded to achieve optimum high drive and low leakage current Fermi-FET performance. These boundary conditions are typically more critical for P-channel than N-channel devices, because hole mobility is lower than N-channel devices and therefore P-channel saturation current is not completely independent of mobility. However, the bounded-tub is preferably used in both N-channel and P- channel devices. For a given Fermi-tub and effective substrate doping concentration, deep Fermi-tub design leads to high drain leakage current. For shallow Fermi-tub depth, leakage current is quire low, 1E-15 A/cm, however saturation current is about 15% below nominal. If Fermi-tub depth is too shallow, the Fermi-Channel is eliminated, leading to a steady state vertical electric field in the tub region close to the insulator-tub interface. This vertical electric field component significantly lowers majority carrier mobility with the consequence of lowering channel saturation current. As heretofore described, one of the basic criterion for Fermi-FETs is that no steady state vertical electric field should exist at the insulator-tub interface for any gate voltage at or above threshold, other than the electric field component produced by excess carriers themselves. Figure 33B illustrates an appropriate electric field diagram below the gate contact of the device of Figure 33A corresponding to proper N-channel Fermi-FET behavior when gate voltage is at threshold. Starting at the gate electrode, the contour potential along a line perpendicular to the Fermi-channel is given below from the gate to the substrate contact : v t = v pσl - v ox - φ ch + φ surf - V sub ( 101 ) Where ; ( 102a) N m. V ox = Q-~ T ox Y f ( 102b) NsubNtub Φsurf = F ln ( 102d) Nf Expanding Equation (101) in view of Equations (102a) through (102e) and simplifying produces: V t = (103) As already described: C ^g* = β e s Therefore Equation (103) becomes The last term in Equation (104) is typically 50mV and will be ignored in subsequent analysis. Simplifying Equation (104) in view of the above, the following expression for threshold voltage is obtained: As gate voltage is lowered below threshold to ground potential (N-Channel device) an inversion condition is created in the Fermi-tub region between the drain and source diffusions. Simulations indicate that this inversion mechanism creates a unique injection barrier between source and drain that extends down from the gate interface to the tub-substrate junction. This injection barrier has a specific shape and is located close to the source. Figure 34A is a simulation of a completely closed inversion region acting as an injection barrier, with 5 Volts on the drain 32 and zero Volts on the gate 28 and source 31, and Fermi-FETs with a channel length of O.δμm. Minimum inversion concentration lines illustrated are 1E12 per cubic cm. The equation that describes this closed inversion injection barrier condition is given below: Therefore: 2 e s∑t (107) ■ fc *~_u_i_ ιv '^\l ~ g r N Λ, c 'tub Equation (107) defines the maximum depth for the Fermi- tub. Deeper tub depths will not allow the inversion injection barrier to close at zero volts on the gate. See Figure 34B. Consequently, increased drain leakage current will be the result. Minimum Fermi-tub depth is defined as Y 0 , the tub depth that permits complete depletion of the tub by the substrate-tub junction at threshold conditions specified by Equation (105) . (108) ^N tub (N tub+ N εub ) Fermi-tub depths that are shallower than the minimum value of Equation (108) will result in a steady state vertical electric field near the insulator-tub surface that will cause a substantial reduction in majority carrier mobility. The end result is to lower saturation current and increase pinch-off voltage. Leakage current however will be in the order of IE-15 A/cm. Figure 35 graphically illustrates the high- performance maximum and minimum values of Fermi-tub depth as a function of tub doping concentration, N tub . Figure 35 is based on Equations (107) and (108) . The running parameter for maximum tub depth is polysilicon gate 28 doping concentration N pol within the range of 5E18 to 2E19. The running parameter for minimum tub depth is substrate concentration N sub in the range of 5E16 to 1E17. The minimum tub depth depends on substrate doping concentration N sub while the maximum tub depth depends on polysilicon gate doping concentration. High performance Fermi-tub depth design lies within the bounded range between the maximum and minimum values to achieve maximum saturation and minimum leakage current. It is also desired to operate 0.8μm devices at light tub doping concentration, for example about 1.5E16, in order to maximize carrier mobility. Tub concentration near 2.5E16 is better suited for Fermi-FETs with channel length's of 0.5μm. An expression for Fermi-channel depth Y f within the bounded range is defined as Y tub - -Y 0 : (109) A plot of Fermi-channel depth Y f is illustrated in Figure 36. This plot shows Fermi channel depth Y f in Angstroms as a function of Fermi-tub doping concentration N tub along the abscissa and substrate concentration N sub as the running parameter. Surface potential φ s is given by Equation (102d) . A Fermi- channel depth of about 350A is desired. Figure 37 graphically illustrates threshold voltage as a function of tub doping concentration with poly concentration N pol in the range 5E18 to 2E19 as a running parameter. Very stable threshold voltage is achieved by the high performance Fermi-FET. Although the preceding description is based on N-channel devices, the same equations apply to P- channel devices. All concentrations may be the same. However, doping types are changed from N to P and P to N. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims: THAT WHICH IS CLAIMED: 1. A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a source injector region of said second conductivity type, adjacent said source region and facing said drain region; a channel of said second conductivity type in said tub region at said substrate surface, between said spaced apart source and drain regions, wherein said channel extends a first predetermined depth from said substrate surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce zero static electric field perpendicular to said substrate surface at said first predetermined depth; a gate insulating layer on said substrate at said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 2. The field effect transistor of Claim 1 wherein said tub region is doped said second conductivity type at a relatively low doping concentration, wherein said source region is doped said second conductivity type at a relatively high doping concentration, and wherein said source injector region is doped said second conductivity type at an intermediate doping concentration between that of said tub region and said source region. 3. The field effect transistor of Claim 1 further comprising a gate sidewall spacer on said substrate surface, extending from adjacent said source injector region to adjacent said gate electrode. 4. The field effect transistor of Claim 3 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 5. The field effect transistor of Claim 4 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 6. The field effect transistor of Claim 3 wherein said gate electrode includes a polysilicon gate electrode layer of said first conductivity type on said gate insulating layer opposite said substrate surface, said polysilicon gate electrode layer including a polysilicon sidewall, and wherein said gate sidewall spacer extends from adjacent said source injector region to adjacent said polysilicon sidewall. 7. The field effect transistor of Claim 6 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 8. The field effect transistor of Claim 7 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 9. The field effect transistor of Claim 3 wherein said source injector region extends to said substrate surface, wherein said gate insulating layer extends onto said source injector region at said substrate surface, and wherein said gate sidewall spacer also extends onto said source injector region at said substrate surface. 10. The field effect transistor of Claim 9 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 11. The field effect transistor of Claim 10 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 12. The field effect transistor of Claim 1 wherein said tub region extends into said substrate a third predetermined depth from said substrate surface, said field effect transistor further comprising a bottom leakage controlling region of said first conductivity type in said substrate, extending across said substrate between extensions of said source and drain regions, and extending into said substrate from a fourth depth which is less than said third depth, to a fifth depth which is greater than said first depth. 13. The field effect transistor of Claim 12 wherein said substrate is doped said first conductivity type at a relatively low doping concentration and wherein said bottom leakage control region is doped said first conductivity type at relatively high doping concentration. 14. The field effect transistor of Claim 1 further comprising a substrate contact region of said first conductivity type in said tub region at said . substrate surface. 15. The field effect transistor of Claim 1 wherein said tub region extends into said substrate a third predetermined depth from said substrate surface; wherein said source region extends into said substrate a fourth predetermined depth from said substrate surface; and wherein said source injector region extends into said substrate a fifth predetermined depth which is between said fourth predetermined depth and said third predetermined depth. 16. The field effect transistor of Claim 1 wherein said tub extends into said substrate a third predetermined depth from said substrate surface and wherein said source injector region also extends into said substrate to said third predetermined depth. 17. The field effect transistor of Claim 1 wherein said tub region extends a third predetermined depth from said substrate surface, at least said third predetermined depth being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate. 18. The field effect transistor of Claim 1 wherein said tub region extends a third predetermined depth from said substrate surface, at least said third predetermined depth being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said tub region, extending from a fourth predetermined depth between said third predetermined depth and said substrate surface towards said substrate surface, upon application of voltage to said gate electrode beyond the threshold voltage of said field effect transistor. 19. The field effect transistor of Claim 1 wherein said tub region extends a third predetermined depth from said substrate surface, at least said third predetermined depth being selected to allow carriers of said second conductivity type to flow within said tub region, from said source region to said drain region and beneath said substrate surface, without creating an inversion layer in said tub region. 20. The field effect transistor of Claim 1 wherein said tub region extends a third predetermined depth from said substrate surface, at least said third predetermined depth being selected to produce a first gate capacitance upon biasing said gate electrode from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate electrode from above said threshold voltage to said threshold voltage. 21. The field effect transistor of Claim 1 further comprising a substrate contact for electrically contacting said substrate; wherein said tub region extends a third predetermined depth from said substrate surface, wherein said gate electrode includes a polysilicon layer of said first conductivity type and a conductive electrode on said polysilicon layer opposite said gate insulating layer; at least said third predetermined depth being selected to produce a voltage at said substrate surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said conductive electrode. 22. The field effect transistor of Claim 1 wherein said gate insulating layer is of predetermined thickness, and wherein said tub region extends a third predetermined depth from said substrate surface, at least said third predetermined depth being selected to produce a threshold voltage for said field effect transistor which is independent of said predetermined thickness, and current for said field effect transistor which increases inversely to said predetermined thickness. 23. A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a source injector region of said second conductivity type, adjacent said source region and facing said drain region; wherein said tub region extends a predetermined depth from said substrate surface, at least said predetermined depth being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said tub region, extending from a second predetermined depth between said predetermined depth and said substrate surface towards said substrate surface, upon application of voltage to said gate electrode beyond the threshold voltage of said field effect transistor; a gate insulating layer on said substrate at said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 24. The field effect transistor of Claim 23 wherein said tub region is doped said second conductivity type at a relatively low doping concentration, wherein said source region is doped said second conductivity type at a relatively high doping concentration, and wherein said source injector region is doped said second conductivity type at an intermediate doping concentration between that of said tub region and said source region. 25. The field effect transistor of Claim 23 further comprising a gate sidewall spacer on said substrate surface, extending from adjacent said source injector region to adjacent said gate electrode. 26. The field effect transistor of Claim 25 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 27. the field effect transistor of Claim 26 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 28. The field effect transistor of Claim 25 wherein said gate electrode includes a polysilicon gate electrode layer of said first conductivity type on said gate insulating layer opposite said substrate surface, said polysilicon gate electrode layer including a polysilicon sidewall, and wherein said gate sidewall spacer extends from adjacent said source injector region to adjacent said polysilicon sidewall. 29. The field effect transistor of Claim 28 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 30. The field effect transistor of Claim 29 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 31. The field effect transistor of Claim 25 wherein said source injector region extends to said substrate surface, wherein said gate insulating layer extends onto said source injector region at said substrate surface, and wherein said gate sidewall spacer also extends onto said source injector region at said substrate surface. 32. The field effect transistor of Claim 31 wherein said gate sidewall spacer comprises an insulator having permittivity which is greater than the permittivity of said gate insulating layer. 33. The field effect transistor of Claim 32 wherein said gate insulating layer comprises silicon dioxide and wherein said gate sidewall spacer comprises silicon nitride. 34. The field effect transistor of Claim 23 further comprising a bottom leakage controlling region of said first conductivity type in said substrate, extending across said substrate between extensions of said source and drain regions, and extending into said substrate from a second depth which is less than said predetermined depth, to a third depth which is greater than said predetermined depth. 35. The field effect transistor of Claim 34 wherein said substrate is doped said first conductivity type at a relatively low doping concentration and wherein said bottom leakage control region is doped said first conductivity type at relatively high doping concentration. 36. The field effect transistor of Claim 23 further comprising a substrate contact region of said first conductivity type in said tub region at said substrate surface. 37. The field effect transistor of Claim 23 wherein said source region extends into said substrate a second predetermined depth from said substrate surface; and wherein said source injector region extends into said substrate a third predetermined depth which is between said second predetermined depth and said predetermined depth. 38. The field effect transistor of Claim 23 wherein said source injector region also extends into said substrate to said predetermined depth. 39. The field effect transistor of Claim 23 further comprising a channel of said second conductivity type in said tub region at said substrate surface, between said spaced apart source and drain regions; wherein said channel extends a first predetermined depth from said substrate surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce zero static electric field perpendicular to said substrate surface at said first predetermined depth. 40. The field effect transistor of Claim 23 wherein at least said predetermined depth is further selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate. 41. The field effect transistor of Claim 23 wherein at least said predetermined depth is further selected to allow carriers of said second conductivity type to flow within said tub region, from said source region to said drain region and beneath said substrate surface, without creating an inversion layer in said tub region. 42. The field effect transistor of Claim 23 wherein at least said predetermined depth is further selected to produce a first gate capacitance upon biasing said gate electrode from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate electrode from above said threshold voltage to said threshold voltage. 43. The field effect transistor of Claim 23 further comprising a substrate contact for electrically contacting said substrate; wherein said gate electrode includes a polysilicon layer of said first conductivity type and a conductive electrode on said polysilicon layer opposite said gate insulating layer; at least said predetermined depth being further selected to produce a voltage at said substrate surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode. 44. The field effect transistor of Claim 23 wherein said gate insulating layer is of predetermined thickness, and wherein at least said predetermined depth is further selected to produce a threshold voltage for said field effect transistor which is independent of said predetermined thickness, and current for said field effect transistor which increases inversely to said predetermined thickness. 45. A field effect transistor comprising: a semiconductor substrate of first conductivity type and which is doped at a first doping concentration N sub , has permittivity e s , and a Fermi- potential φ f .at temperature T degrees Kelvin; a tub region of second conductivity type in said substrate at a surface thereof, and which is doped at a second doping concentration N tub which is a factor of times N sub ; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a gate insulating layer on said substrate at said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes electrically contacting said source and drain regions and said gate insulating layer, respectively; said tub region extending into said substrate a predetermined depth from said substrate surface , said predetermined depth being greater than (2e s φ s N sub /qN tub (N tub +N sub ) ) ^ and being less than (2e s V t /qN tub ) "; where q is 1.6xl0 "19 coulombs , V t is the threshold volr.age of said field effect transistor, and φ s is 2φ f + (KT/q) Inc. , and K is 1.38xl0" 23 Joules/ 0 Kelvin . 51. The field effect transistor of Claim 47 wherein said source injector region extends to said substrate surface, wherein said gate insulating layer extends onto said source injector region at said substrate surface, and wherein said gate sidewall spacer also extends onto said source injector region at said substrate surface. 52. The field effect transistor of Claim 45 further comprising a bottom leakage controlling region of said first conductivity type in said substrate, extending across said substrate between extensions of said source and drain regions, and extending ' into said substrate from a second depth from said substrate surface, which is less than said predetermined depth from said substrate surface, to a third depth from said substrate surface which is greater than said predetermined depth from said substrate surface. 53. The field effect transistor of Claim 45 further comprising a channel of said second conductivity type in said tub region at said substrate surface, between said spaced apart source and drain regions; wherein said channel extends a second predetermined depth from said substrate surface and said tub region extends a third predetermined depth from said channel, at least one of said second and third predetermined depths being selected to produce zero static electric field perpendicular to said substrate surface at said second predetermined depth. 54. The field effect transistor of Claim 45 wherein at least said predetermined depth is selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate. 55. A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof, and extending a first depth from said substrate surface; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a channel of said second conductivity type in said tub region, between said spaced apart source and drain regions, and extending a second depth from said substrate surface, wherein said second depth is less than said first depth, at least one of said first and second depths being selected to produce zero static electric field perpendicular to said substrate surface, from said substrate surface to said second depth, and at least one of said source and drain regions being doped said second conductivity type at a doping concentration facing said channel which is sufficiently high to maximize the saturation current of said field effect transistor; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 56. The field effect transistor of Claim 55 wherein the doping concentration of at least one of said source and drain regions is at least: where : E s = Permittivity of substrate φ x = Flat band voltage between said at least one of said source and drain regions and said channel q = 1.6xl0 ~19 coulomb ei = Permittivity of the gate insulating layer L 0 = Channel length V gmax = Maximum gate voltage anticipated V t = Threshold voltage Y f = Depth of the channel adjacent the source and drain regions T ox = Gate insulating layer thickness δ = Flow depth of excess carriers in the channel 57. The field, effect transistor of Claim 55 wherein at least one of said first and second depths are selected to produce a threshold voltage for said field effect transistor which is twice the Fermi- potential of said semiconductor substrate. 58. The field effect transistor of Claim 55 wherein at least one of said first and second depths are selected to produce a threshold voltage for said field effect transistor which is less than twice the Fermi-potential of said semiconductor substrate. 59. The field effect transistor of Claim 55 wherein at least one of said first and second depths are selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said second depth toward said substrate surface upon application of voltage to said gate electrode beyond the said threshold voltage of said field effect transistor. 60. The field effect transistor of Claim 55 wherein said at least one of said first and second depths are selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said substrate surface, without creating an inversion layer in said channel. 61. The field effect transistor of Claim 56 wherein said channel is doped said second conductivity type at a concentration of less than 5xl0 16 cm "3 . 62. The field effect transistor of Claim 55 wherein said substrate is doped at a first doping concentration of said first conductivity type; wherein said tub region is doped at a second doping concentration of said second conductivity type; and wherein said first doping concentration is greater than said second doping concentration. 63. The field effect transistor of Claim 62 wherein said first doping concentration is at least four times greater than said second doping concentration. 64. The field effect transistor of Claim 55 wherein said channel is doped at a second doping concentration which is less than the source doping concentration, said field effect transistor further comprising: a source doping gradient region of said second conductivity type between said source region and said channel, and being doped at a doping gradient which decreases from said source doping concentration adjacent said source region to said second doping concentration adjacent said channel, said source doping gradient region having thickness greater than 300 Angstroms. 65. The field effect transistor of Claim 64 further comprising: a drain doping gradient region of said second conductivity type between said drain region and said channel, and being doped at a doping gradient which decreases from said drain doping concentration adjacent said drain region to said second doping concentration adjacent said channel, said drain doping gradient region having thickness greater than 300 Angstroms. 66. The field effect transistor of Claim 64 wherein said gate insulating layer and said gate electrodes extend over said source doping gradient region. 67. The field effect transistor of Claim 65 wherein said gate insulating layer and said gate electrode extend over said drain doping gradient region. 68. A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof, and extending a first depth from said substrate surface; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a channel of said second conductivity type in said tub region, between said spaced apart source and drain regions, and extending a second depth from said substrate surface, wherein said second depth is less than said first depth, at least one of said first and second depths being selected to produce zero static electric field perpendicular to said substrate surface, from said substrate surface to said second depth, said channel being doped said second conductivity type at a channel doping concentration which is sufficiently high to lower the threshold voltage of said field effect transistor to below twice the Fermi potential of said semiconductor substrate; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 69. The field effect transistor of Claim 68 wherein said channel doping concentration (N oh ) is greater than: A V τ --qN eh Yji ^- + ^ e s e i where: Δv τ = Change in threshold voltage from twice the Fermi potential of the substrate q = 1.6xl0 "19 coulomb T ox = Gate insulating layer thickness Y f = Depth of the Fermi-channel adjacent the source and drain regions e s = Permittivity of substrate e ± = Permittivity of the gate insulating layer 70. The field effect transistor of Claim 68 wherein at least one of said source and drain regions are doped said second conductivity type at a doping concentration facing said channel which is sufficiently high to maximize the saturation current of said field effect transistor. 71. The field effect transistor of Claim 68 wherein at least one of said first and second depths are selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said second depth toward said substrate surface upon application of voltage to said gate electrode beyond the said threshold voltage of said field effect transistor. 72. The field effect transistor of Claim 68 wherein said at least one of said first and second depths are selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said substrate surface, without creating an inversion layer in said channel. 73. The field effect transistor of Claim 68 wherein said channel is doped said second conductivity type at a concentration of less than 5xl0 16 cm 3 . 74. The field effect transistor of Claim 68 wherein said substrate is doped at a first doping concentration of said first conductivity type; wherein said tub region is doped at a second doping concentration of said second conductivity type; and wherein said first doping concentration is greater than said second doping concentration. 75. The field effect transistor of Claim 74 wherein said first doping concentration is at least four times greater than said second doping concentration. 76. The field effect transistor of Claim 68 wherein said channel is doped at a second doping concentration which is less than the source doping concentration, said field effect transistor further comprising: a source doping gradient region of said second conductivity type between said source region and said channel, and being doped at a doping gradient which decreases from said source doping concentration adjacent said source region to said second doping concentration adjacent said channel, said source doping gradient region having thickness greater than 300 Angstroms. 77. The field effect transistor of Claim 76 further comprising: a drain doping gradient region of said second conductivity type between said drain region and said channel, and being doped at a doping gradient which decreases from the drain doping concentration adjacent said drain region to said second doping concentration adjacent said channel, said drain doping gradient region having thickness greater than 300 Angstroms. 78. The field effect transistor of Claim 76 wherein said gate insulating layer and said gate electrodes extend over said source doping gradient region. 79. The field effect transistor of Claim 77 wherein said gate insulating layer and said gate electrode extend over said drain doping gradient region. 80. A P-channel field effect transistor comprising: an N-type semiconductor substrate; spaced apart P-type source and drain regions in said semiconductor substrate at a surface thereof; a P-type channel in said semiconductor substrate between said spaced apart source and drain regions, said P-type channel being less than about one micron long; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions, said gate insulating layer being less than about one hundred twenty Angstroms thick; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively, said source, drain and gate electrodes applying voltages to said source, drain and gate insulating layer respectively, of magnitude between about zero and five volts, to produce a drain saturation current in said field effect transistor of at least four Amperes per centimeter of channel width and a leakage current in said field effect transistor of less than ten picoAmperes per micron of channel width. 81. The P-channel field effect transistor of Claim 80 wherein said channel extends a channel depth from said substrate surface, at least said channel depth being selected to produce zero static electric field perpendicular to said substrate surface at said substrate surface. 82. The P-channel field effect transistor of Claim 81 further comprising a P-type tub region in said semiconductor region at said substrate surface, surrounding said source region, said drain region and said channel region, and extending a second depth from said substrate surface which is greater than said channel depth, at least said channel depth and said second depth being selected to produce zero static electric field perpendicular to said substrate surface from said substrate surface to said channel depth. 83. An N-channel field effect transistor comprising: a P-type semiconductor substrate; electric field perpendicular to said substrate surface from said substrate surface to said channel depth. 86. A field effect transistor comprising: a semiconductor substrate having a first doping concentration of first conductivity type; a tub region having a second doping concentration of second conductivity type in said substrate at a surface thereof, and extending a first depth from said substrate surface; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a channel of said second conductivity type in said tub region, between said spaced apart source and drain regions, and extending a second depth from said substrate surface, wherein said second depth is less than said first depth, and wherein said first doping concentration is greater than said second doping concentration; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 87. The field effect transistor of Claim 86 wherein said first doping concentration is at least four times greater than said second doping concentration. 88. The field effect transistor of Claim 86 wherein at least one of said first and said second depths are selected to produce zero static electric field perpendicular to said substrate surface from said substrate surface to said second depth. 89. A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof, and extending a first depth from said substrate surface; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface, and doped at a first doping concentration; a channel of said second conductivity type in said tub region, between said spaced apart source and drain regions, and extending a second depth from said substrate surface, and doped at a second doping concentration which is less than said first doping concentration, wherein said second depth is less than said first depth, at least one of said first and second depths being selected to produce zero static electric field perpendicular to said substrate surface from said substrate surface to said second depth; a source doping gradient region of said second conductivity type between said source region and said channel, and being doped at a doping gradient which decreases from said first doping concentration adjacent said source region to said second doping concentration adjacent said channel, said source doping gradient region having thickness greater than 300 Angstroms; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively. 90. The field effect transistor of Claim 89 further comprising: a drain doping gradient region of said second conductivity type between said drain region and said channel, and being doped at a doping gradient which decreases from said first doping concentration adjacent said drain region to said second doping concentration adjacent said channel, said drain doping gradient region having thickness greater than 300 Angstroms. 91. The field effect transistor of Claim 89 wherein said gate insulating layer and said gate electrodes extend over said source doping gradient region. 92. The field effect transistor of Claim 91 wherein said gate insulating layer and said gate electrode extend over said drain doping gradient region. 93. The field effect transistor of Claim 89 wherein said source doping gradient region surrounds said source region. 94. The field effect transistor of Claim 90 wherein said drain doping gradient region surrounds said drain region. 95. The field effect transistor of Claim 89 wherein said first doping concentration is sufficiently high to maximize saturation current of said field effect transistor. 96. The field effect transistor of Claim 95 wherein said first doping concentration is at least Where : E s = Permittivity of substrate φ x - Flat band voltage between said at least one of said source and drain regions and said channel q = 1.6xl0 "19 coulomb e i = Permittivity of the gate insulating layer L 0 = Channel length V gjna -,. = Maximum gate voltage anticipated V t = Threshold voltage X j = Depth of the source region T ox = Gate insulating layer thickness δ = Flow depth of excess carriers in the channel

Inventors: DENNEN MICHAEL W, VINAL ALBERT W, DENNEN, MICHAEL, W., VINAL, ALBERT, W.
Applicants: DENNEN MICHAEL W, THUNDERBIRD TECH INC, VINAL ALBERT W, DENNEN, MICHAEL, W., THUNDERBIRD TECHNOLOGIES, INC., VINAL, ALBERT, W.
Application year: 1994
Main classification: H01L29
IPC codes: H01L21, H01L29