Horizontal synchronizing apparatus

Abstract: A horizontal synchronizing apparatus includes a horizontal synch. signal source (11) for providing a horizontal synch. signal (a1), a horizontal deflection circuit (12,13) for generating a deflection current which has scanning intervals and blanking intervals repetitively successing in response to driving pulses and also retrace pulses which delay from the driving pulses as a function of a load on the horizontal deflection circuit (12,13), a phase locked loop (20) having an input (21), an output (e1) and a first feedback path (d1), for producing from the output a substantial bi-level signal synchronized to the horizontal synch. signal (a1) applied to the input (21), and a phase controlled loop (30) having an input (31), an output (h1) and a second feedback path, for maintaining the retrace pulses in synchronous with the bi-level signals. In the horizontal synchronizing apparatus as constructed as above, the phase controlled loop (30) is provided with a phase detection circuit (32) having a first input connected to the output of the phase locked loop (20) and a second input connected to the deflection circuit (12,13), for producing a first polarity current in response to the bi-level signal when the retrace pulses being a first state or a second polarity current in response to the bi-level signal when the retrace pulses being a second state, a filter (33) connected to the phase detection circuit (32) for producing a control signal by filtering out undesired components of the first and second polarity signals, and a phase controllable device (34) having a control input coupled to the output of the filter (33) for producing the driving pulse which maintains the retrace pulses in synchronous with the bi-level signals.

Description: The present invention generally relates to a horizontal synchronizing apparatus for use in a television receiver or a monitoring display, and more particularly, to a horizontal synchronizing apparatus capable of preventing distortions of picture images. Generally when a television receiver displays images processed from a television broadcasting signal on a screen, a video signal representing image to be displayed is formed by repetitively scanning the display screen of a picture tube by an electron beam, and the same time by modulating the intensity of the electron beam with a video signal component of a composite video signal generated from the television broadcasting signal. The television receiver controls a deflection circuit of the horizontal synchronizing apparatus to synchronize with a sync. signal of the composite video signal, so as to make the trace of the electron beam synchronize with the video signal component. Here, the composite video signal tends to include distortions due to an electronic noise or a thermal noise, when the television broadcasting signal is received by the television receiver. Accordingly although horizontal sync. pulses of the horizontal sync. signal are carefully controlled to repeat at a highly stable period at a broadcasting station, the horizontal sync. pulses become irregular and indistinct by the noise when received by the television receiver. Therefore it is conventionally performed to synchronize the horizontal synchronizing apparatus which use an oscillator for generating the horizontal sync. signal under the control of synchronization by a phase locked loop. So, even if the horizontal sync. pulses becomes indistinct due to the noise, the oscillating frequency generated from the oscillator remains constant by using the horizontal synchronizing apparatus. Thus it becomes able to continuously produce retrace pulses for regularly controlling deflections. Here, the horizontal synchronizing apparatus generates high voltage pulses to perform a relatively quick repetitive scanning when the television receiver operates normally. It is common that an anode high voltage for activating a television picture tube is produced by rectifying and smoothing the high voltage pulses. The horizontal synchronizing apparatus often drives a low voltage power supply source for use in circuits other than the television receiver, but it happens that timings of the retrace pulses generated by the horizontal synchronizing apparatus changes in accordance with a load change of the horizontal synchronizing apparatus (e.g., a brightness change of a picture image displayed on the picture tube), so that the picture image thus displayed is distorted by the timing change of the retrace pulses. In order to overcome the above problems, Japanese Patent Tokko-Sho 58-54545, which corresponds to the U.S. Patent 4,327,376, discloses a horizontal synchronizing apparatus wherein a phase control loop is coupled to an output of a phase locked loop. The phase control loop has a phase detector which connects the first input to output of the phase locked loop, the second input to deflection circuit. The phase control loop makes the phase detector to operate according to the retrace loop. The phase control loop generates the first current when a bi-level signal output from the phase locked loop is in a first condition. and also generates a second polarity current when the bi-level signal is in a second condition. And the phase control loop further includes a filter for removing an undesired component of the first and second polarity current connected to an output of the phase detector to produce a control signal. The phase control loop further includes a phase controllable means which has a control input coupled to the filter for keeping the retrace pulse in synchronous with the bi-level signal by generating the driving pulse. However, the conventional horizontal synchronizing apparatus have defects as described hereinafter. The waveform of the retrace pulse (using a flyback pulse obtained from a flyback transformer on the common television receiver) bend by the brightness change of the picture image because the phase detector of the second phase control loop operates in accordance with the retrace pulse. As a result the second phase control loop operates as according the central phase of changed retrace pulse with the bi-level signal output from the phase locked loop when a pulse width of the retrace pulse input to the second input of phase detector of phase locked loop change. Accordingly a phase error occurs between actual retrace pulse and the bi-level signal, so that the picture image displayed on image of picture tube distorts. In the conventional horizontal synchronizing apparatus as described above, the phase error occurs between the retrace pulse and bi-level from the phase locked loop and the picture image displayed on image of picture tube bend in the case the pulse width of retrace pulse change. A horizontal synchronizating apparatus is disclosed in US 3,891,800, which apparatus comprises a phase controlled loop coupled to a phase locked loop and a horizontal deflection pulse generating circuit. The phase controlled loop consists of a phase comparator, which compares the output signal of the phase locked loop with a signal derived from the horizontal deflection pulse; a filter to filter the output from the phase comparator; and a voltage controlled oscillator controlled by the output from the filter. This specification discloses an arrangement in which a signal derived from the horizontal deflection pulse is also applied to the phase comparator of the phase locked loop, in order to reduce error in the phase of the horizontal synchronising pulse caused by variations in the luminosity of the picture. It is, therefore, an object of the present invention to provide a horizontal synchronizing apparatus which is able to remove the above mentioned problems of the prior arts. Another object of the present invention is to provide a horizontal synchronizing apparatus which is able to prevent a phase error between a retrace pulse and a bi-level signal from a phase locked loop when a pulse width of the retrace pulse varies. According to the present invention, there is provided a horizontal synchronizing apparatus for use in a television receiver to display images on a display device, the apparatus comprising: a horizontal synch. signal source for providing a horizontal synch. signal; a phase locked loop, having an input connected to the horizontal synch. signal source, for producing a pulse signal synchronized to the horizontal synch. signal applied to the input; a phase controlled loop comprising: a phase detection circuit, having a first input connected to the output of the phase locked loop and a second input, for outputting a signal based on the signals input at the first and second inputs; filter means connected to the phase detection circuit for producing a control signal by filtering out undesired components of the signal output from the phase detection circuit; and phase controllable means, having a control input coupled to the output of the filter means, for producing the driving pulse in response to the control signal received at the control input; and a horizontal deflection circuit for generating a deflection signal in response to driving pulses, and also retrace pulses which delay from the driving pulses as a function of a load on the horizontal deflection circuit and which are coupled to the second input of the phase detection circuit (32) as a retrace signal; characterised in that the phase detection circuit operates such that no signal is output when the pulse signal output from the phase locked loop is at a first level; a signal having a first polarity is output when the pulse signal output from the phase locked loop is at a second level and the retrace signal is in a first state; and a signal having a second polarity is generated when the pulse signal output from the phase locked loop is at a second level and the retrace signal is in a second state. According to the horizontal synchronizing apparatus as constructed above, the phase detection circuit operates only in response to one level of the pulse signal from the phase locked loop and, if the pulse signal is at that one level, outputs the first polarity detection signal when the retrace pulse from the horizontal output circuit is in the first state or outputs the second polarity detection signal when the retrace pulse from the horizontal output circuit is in the second state, so that phase errors occurring between the retrace pulse and the bi-level signal from the phase locked loop when the pulse width of the retrace pulse varies are prevented. Additional objects and advantages of the present invention will be apparent to persons skilled in the art from a study of the following description and the accompanying drawings, which are hereby incorporated in and constitute a part of this specification. For a better understanding of the present invention and many of the attendant advantages thereof, reference will now be made by way of example to the accompanying drawings, wherein: FIGURE 1 is a block diagram showing a first embodiment of the horizontal synchronizing apparatus according to the present invention; FIGURE 2 is a waveform-timing chart showing the normal operation of the horizontal synchronizing apparatus of FIGURE 1; FIGURE 3 is a waveform-timing chart showing the operation of the horizontal synchronizing apparatus of FIGURE 1, when the retrace pulse had delayed; FIGURE 4 is a waveform-timing chart showing the operation of the horizontal synchronizing apparatus of FIGURE 1, when the retrace pulse had varied; FIGURE 5 is a block diagram showing a second embodiment of the horizontal synchronizing apparatus according to the present invention; FIGURE 6 is waveform-timing chart showing the operation of the horizontal synchronizing apparatus of FIGURE 5; and FIGURE 7 is a block diagram showing a third embodiment of the horizontal synchronizing apparatus according to the present invention. The present invention will be described in detail with reference to the FIGURES 1 through 7. Throughout the drawings, like or equivalent reference numerals or letters will be used to designate like or equivalent elements for simplicity of explanation. Referring now to FIGURES 1 through 4, a first embodiment of the horizontal synchronizing apparatus according to the present invention will be described in detail. FIGURE 1 denotes a block diagram showing the first embodiment of the horizontal synchronizing apparatus to the present invention. In FIGURE 1 the numeral 11 denotes an input terminal for receiving a horizontal sync. signal al. the horizontal sync. signal al on the input terminal 11 is applied to an input terminal 21 of a phase locked loop 20. The phase locked loop 20 consists of a phase detection circuit 22, a filter 23, and an oscillating circuit 24. The horizontal sync. signal a1 on the input terminal 21 is supplied to the first input terminal of the phase detection circuit 22. A reference horizontal pulse signal output from the oscillating circuit 24 is supplied to the second input terminal of the phase detection circuit 22. The phase detection circuit 22 detects a phase error between the horizontal sync. signal a1 and a reference horizontal pulse signal d1 by comparing them, and generates a detected output current b1 resulted by the comparison and supply it to the filter 23. The filter 23 generates a control voltage c1 and supplies it to the oscillating circuit 24 by removing undesired components by passing the detected output current b1 from the phase detection circuit 22 through a low pass filter. The oscillating circuit 24 supplies the reference horizontal pulse signal d1 which controls the phase based on the control voltage c1 from the filter 23 to the second input terminal of the phase detection circuit 22, and simultaneously generates a horizontal frequency bi-level signal e1 which is phase-controlled based on the control voltage c1 and transmits it to the first input terminal 31 of a phase controlled loop 30. The bi-level signal e1 in this case becomes a high level in pulse periods, while becomes a low level in intervals other than the pulse periods. A retrace pulse signal j1 from a horizontal output circuit 13 is to be applied to the second input terminal 35 of the phase controlled loop 30. The phase controlled loop 30 consists of a phase detection circuit 32, a filter 33, and an oscillating circuit 34. The bi-level signal e1 and the retrace pulse signal j1 applied to the input terminals 31, 35 are supplied to the first and second input terminals of the phase detection circuit 32, respectively. The phase detection circuit 32 operates by being turned on under a control of the bi-level signal e1, and supplies a negative one of detected output currents f1 to the filter 33 when the retrace pulse signal j1 is in a low level and supplies a positive detected output current f1 to the filter 33 in the case the retrace pulse signal j1 is high level. While positive one of the becomes zero when the phase detection circuit 32 is turned off under a control of the bi-level signal e1. The filter 33 generates a control signal g1 by removing undesired components from the detected output currents f1, and supplies the control signal g1 to the oscillating circuit 34, by passing the detected output current f1 from the phase detection circuit 32 through a low pass filter. The oscillating circuit 34 supplies a phase controlled horizontal driving pulse signal h1 to a horizontal driving circuit 12 based on the control signal g1 from the filter 33. In this case, the oscillating circuit 34 is so set up as to delay the phase of the horizontal driving pulse signal h1 when the control signal g1 from the filter 33 increases, and to advance the phase of the horizontal driving pulse signal h1 when the control signal g1 decreases. The horizontal driving circuit 12 amplifies and shapes the horizontal driving pulse signal h1 from the oscillating circuit 34, and then supply it as a horizontal driving pulse i1 to the horizontal output circuit 13. The horizontal output circuit 13 generates the retrace pulse signal j1 by performing a switching operation, and supplies it to both a horizontal deflection coil and the second input terminal of the phase controlled loop 30. FIGURE 2 is a waveform-timing chart showing the normal operation of the first embodiment of the horizontal synchronization apparatus according to the present invention. FIGURE 2(a) denotes the horizontal sync, signal a1. FIGURE 2(b) denotes the reference horizontal pulse signal d1. FIGURE 2(c) denotes the bi-level signal e1. FIGURE 2(d) denotes the retrace pulse signal j1. FIGURE 2(e) denotes the detected output current f1. FIGURE 2(f) denotes the control signal g1. However, both the period of the horizontal sync. signal a1 shown in FIGURE 2(a) and the period of the reference horizontal pulse signal d1 shown in FIGURE 2 (b) are one horizontal period (1H), the pulse width of reference horizontal pulse of the reference horizontal pulse signal d1 is wider than the pulse width of horizontal sync. pulse of the horizontal sync. signal a1. The phase detection circuit 22 detects a phase error between the horizontal sync. signal a1 and a reference horizontal pulse signal d1 for matching the timings of the center of the horizontal sync. pulse of the horizontal sync. signal a1 as shown in FIGURE 2(a) and the leading edge of the reference horizontal pulse as shown in FIGURE 2(b), and supplies a current b1 representing the detected phase error to the filter 23. So, the oscillating circuit 24 is supplied with the control voltage c1 which is set to match the timings of the center of the horizontal sync. pulse of the horizontal sync. signal a1 as shown in FIGURE 2(a) with the leading edge of the reference horizontal pulse. The oscillating circuit 24 then generates the bi-level signal d1 as shown in FIGURE 2(c) and transmits it to the first input terminal 31 of the phase controlled loop 30. In this case, the pulse width of the bi-level signal e1 is nearly the same with the pulse width of the horizontal sync. pulse of the horizontal sync. signal a1. The bi-level signal e1 is the pulse signal having a period equal to the one horizontal period (1H), but taking a response time into account the phase of the bi-level signal e1 is advanced for predetermined time compared to the horizontal sync. signal a1. Further the bi-level signal e1 goes to a high level in the pulse period, while goes to a low level in period other than the pulse period. On the other hand, the retrace pulse signal j1 from the horizontal output circuit 13 is the pulse signal having the one horizontal period (1H) as shown in FIGURE 2(d). When the phase detection circuit 32 is in a suspension state, the detected output current f1 as shown in FIGURE 2(e) is zero. The phase detection circuit 32 is operated by the pulses of the bi-level signal e1 to supply the negative (-) detected output current f1 to the filter 33 when the retrace pulse signal j1 is low level (L), or to supply the positive (+) detected output current f1 to the filter 33 when the retrace pulse signal j1 is high level (H). The filter 33 passes the detected output current f1 from the phase detection circuit 32 though a LPF. So, the control signal g1 from the filter 33 as shown in FIGURE 2(f) becomes zero when the detected output current f1 is zero, and it lowers at a prescribed rate when the detected output current f1 is negative (-), but rises at a prescribed rate when the detected output current f1 is positive (+). The oscillation circuit 34 controls to delay the phase of horizontal driving pulse signal h1 when the control signal g1 rises, while the oscillation circuit 34 controls to advance the phase of horizontal driving pulse signal h1 when the control signal g1 lowers. So, the retrace pulse signal j1 from the horizontal output circuit 13 is controlled to be matched the timings of its pulse leading edge with the center phase of the bi-level signal e1. FIGURE 3 is a waveform-timing chart showing the operation of the retrace pulse signal j1 in the first embodiment as shown in FIGURE 1 when the retrace pulse delays. FIGURE 3(a) denotes the bi-level signal e1. FIGURE 3(b) denotes the retrace pulse signal j1. FIGURE 3(c) denotes the detected output current f1. And FIGURE 3(d) denotes the control signal g1. The solid line graphs of the bi-level signal e1, the retrace pulse signal j1, the detected output current f1, and control signal g1 shown in FIGURE 3(a) through FIGURE 3(d) coincide with the bi-level signal e1, the retrace pulse signal j1, the detected output current f1, and the control signal g1 as shown in FIGURE 2(c) through FIGURE 2(f). As to the retrace pulse signal j1 as shown in FIGURE 3(b), the phase detection circuit 32 supplies the negative (-) detected output current f1 as shown in FIGURE 3(c) to filter 33 till the pulse period of the bi-level signal e1 as shown in FIGURE 3(a) will terminate when the phase of the retrace pulse as shown by the broken line has delayed after the pulse of the bi-level signal e1 as shown in FIGURE 3(a). So, the control signal g1 from the filter 33 as shown in FIGURE 3(d) lowers to a level -A till the pulse period of the bi-level signal e1 will terminate as shown by the broken line. After that the state of the control signal g1 will continue till the bi-level signal e1 advances to the next pulse period. So, the oscillation circuit 34 controls to advance the phase of the horizontal driving pulse signal h1. So, the retrace pulse signal j1 from the horizontal output circuit 13 is controlled to be hastened the timings of its pulse leading edge so as that the timing matches with the pulse center phase of the bi-level signal e1. FIGURE 4 is a waveform-timing chart showing the operation of the retrace pulse signal j1 in the fist period as shown in FIGURE 1 when the pulse width of the retrace pulse has changed. FIGURE 4(a) denotes the bi-level signal e1. FIGURE 4(b) denotes the retrace pulse signal j1. FIGURE 4(c) denotes the detected output current f1. And FIGURE 4(d) denotes the control signal g1. The solid lines, in FIGURE 4(a) through FIGURE 4(d), representing parts of the bi-level signal e1, the retrace pulse signal j1, the detected output current f1, and the control signal g1 coincide with the bi-level signal e1, the retrace pulse signal j1, the detected output current f1, and the control signal g1 as shown in FIGURE 2(c) through FIGURE 2(f). In the retrace pulse signal j1 as shown in FIGURE 4(b), the pulse width of the retrace pulse signal j1 becomes wide when the leading edge of the retrace pulse signal j1 as shown by the solid line does not delay from the pulse of the bi-level signals e1 as shown in FIGURE 4(a), but the trailing edge of the retrace pulse delays after the pulse of the bi-level signals e1 as shown by the broken line. However as the pulse period of the bi-level signal e1 had terminated at the trailing edge of the retrace pulse signal j1, the detected output current f1 of the phase detection circuit 32 as shown in FIGURE 4(c) becomes the state as shown in FIGURE 2(e) independently of the pulse width of the retrace pulse signal j1. Also the control signal g1 from the filter 33 as shown in FIGURE 4(d) becomes the state as shown in FIGURE 2(f). According to the first period as described above, the retrace pulse signal j1 has the pulse wider than the pulse of the bi-level signal e1. The phase detection circuit 32 is operated by the bi-level signal e1 to supply the positive detection output current f1 to the filter 33 when the retrace pulse signal j1 is in the high level. Thus if the pulse width had varied due to brightness changes of images, the retrace pulse signal j1 does not cause any phase error from the bi-level signal c1. Therefor the first embodiment of the horizontal synchronization apparatus can prevent distortions in the images. Thus the first embodiment can make a good impression on viewers. FIGURE 5 is a block diagram showing a second embodiment of the horizontal synchronizing apparatus according to the present invention. In FIGURE 5, the same components as the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1 are omitted from following explanations by using the same references. The second embodiment of the horizontal synchronization apparatus as shown in FIGURE 5 is different from the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1, by that an oscillating circuit 44 of a phase locked loop 40 supplies a delayed bi-level signal k1 to a pulse generating circuit 41, and the pulse generating circuit 41 generates a pulse signal m1 based on the delayed bi-level signal k1 and a retrace pulse signal j1 to supply the pulse signal m1 to a second input terminal 35 of a phase controlled loop 30. When explaining the second embodiment of the horizontal synchronization apparatus in more detail, the oscillating circuit 44 of the phase locked loop 40 not only supplies a reference horizontal pulse signal d1 to the second input terminal of the phase detection circuit 22 likely to the oscillating circuit 24 in FIGURE 1, but also produces a bi-level signal e1 with the horizontal frequency to transmit the bi-level signal e1 to the first input terminal 31 of the phase controlled loop 30. Further the oscillating circuit 44 generates another bi-level signal k1 with the horizontal frequency but delayed its phase by nearly a half wave-length from the bi-level signal e1 to transmit the bi-level signal k1 to the pulse generating circuit 41. The pulse generating circuit 41 comprises a flip-flop for generating the pulse signal m1 which becomes to a high level for a time period extending from the leading edge of the retrace pulse signal j1 to the high level to the leading edge of the delayed bi-level signal k1 to the high level, but becomes to a low level for a time period extending from the leading edge of the delayed bi-level k1 to the high level to the leading edge of the retrace pulse signal j1 to the high level thus for transmitting the pulse signal m1 to the second input terminal 35 of the phase controlled loop 30. The pulse signal m1 on the second input terminal 35 is supplied to the second input terminal of the phase detection circuit 32. Except the above the second embodiment of the horizontal synchronization apparatus as shown in FIGURE 5 has the same construction as the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1. FIGURE 6 is a waveform-timing chart showing the operation of the second embodiment of the horizontal synchronization apparatus as shown in FIGURE 5. FIGURE 6(a) denotes the bi-level signal e1. FIGURE 6(b) denotes the delayed bi-level signal k1. FIGURE 6(c) denotes the retrace pulse signal j1. FIGURE 6(d) denotes the pulse signal m1. FIGURE 6(e) denotes the detected output current f1. And FIGURE 6(f) denotes the control signal g1. The oscillating circuit 44 generates the bi-level signal e1 shown in FIGURE 6(a) and the delayed bi-level signal k1 shown in FIGURE 6(b) based on the control signal c1 to transmit them to the first input terminal 31 of the phase controlled loop 30 and the pulse oscillating circuit 41, respectively. In this case the bi-level signal e1 becomes the same as the bi-level signal e1 shown in FIGURE 2(c). The delayed bi-level signal k1 becomes a pulse signal having the 1H period but delayed by nearly a half wave-length from the bi-level signal e1. On the other hand, the retrace pulse signal j1 from the horizontal output circuit 13 is the pulse signal having the 1H period as shown in FIGURE 6(c). Accordingly the pulse signal m1 from the pulse oscillating circuit 41 shown in FIGURE 6(d) becomes to a high level for a time period extending from the leading edge of the retrace pulse signal j1 to the high level to the leading edge of the delayed bi-level signal k1 to the high level, but becomes to a low level (L) for a time period extending from the leading edge of the delayed bi-level signal k1 to the high level to the leading edge of the retrace pulse signal j1. When the phase detection circuit 32 is in a suspension state, the detected output current f1 as shown in FIGURE 6(e) is zero. The phase detection circuit 32 is operated by the pulses of the bi-level signal e1 to supply the negative (-) detected output current f1 to the filter 33 when the retrace pulse m1 as shown in FIGURE 6(d) is low level (L), or to supply the positive (+) detected output current f1 to the filter 33 when the retrace pulse m1 is high level (H). The control signal g1 from the filter 33, as shown in FIGURE 6(f), becomes zero when the detected output current f1 is zero. The control signal g1 lowers at a prescribed rate when the detected output current f1 is negative (-) and rises at a prescribed rate when the detected output current f1 is positive. The oscillating circuit 34 controls for delaying the phase of the horizontal driving pulse signal h1 when the control signal g1 rises, or for advancing the phase of the horizontal driving pulse signal h1 when the control signal g1 lowers. So, the retrace pulse signal j1 from the horizontal output circuit 13 is controlled so as that the timing of the pulse leading edge of the retrace pulse signal j1 matches with the pulse center phase of the bi-level signal e1. According to the second embodiment of the horizontal synchronization apparatus as shown in FIGURE 5, the period that the pulse signal m1 remains at the high level does not vary if the pulse width of the retrace signal j1 varies due to the brightness change of images. Thus the retrace pulse signal j1 does not cause any phase error from the bi-level signal e1. This second embodiment of the horizontal synchronization apparatus thus effects in similar to the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1. And because the pulse signal m1 is set to have a pulse duty close to 50%, this second embodiment of the horizontal synchronization apparatus has further effects that it will be possible to shorten and to stabilize the pull-in time of the phase controlled loop 30. FIGURE 7 is a block diagram showing a third embodiment of the horizontal synchronizing apparatus according to the present invention. In FIGURE 7, the same components as the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1 are omitted from following explanations by using the same references. The third embodiment of the horizontal synchronization apparatus as shown in FIGURE 7 is different from the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1, by that a horizontal sawtooth-wave generating circuit 51 is inserted between the horizontal output circuit 13 and the second input terminal 35 of the phase controlled loop 30. The horizontal sawtooth-wave generating circuit 51 generates a sawtooth-wave signal n1 which sharply rises by the phase retrace pulse signal j1 from the horizontal output circuit 13, but slowly lowers in the period out of the retrace pulse signal j1 to transmit the sawtooth-wave signal n1 to the second input terminal 35 of the phase controlled loop 30. The horizontal sawtooth-wave generating circuit 51 is able to supply a signal which becomes to a high level (i.e., a reference level for determining the retrace pulse signal j1) at any given phase in the pulse period of the retrace pulse signal j1 to the second input terminal 35 of the phase controlled loop 30 by shaping the sawtooth wave signal n1 to a given waveform. According to the third embodiment of the horizontal synchronization apparatus as shown in FIGURE 7, the period of the high level of the sawtooth wave signal n1 can be made wider than the pulse width of the bi-level signal e1. Thus the third embodiment of the horizontal synchronization apparatus as shown in FIGURE 7 has effects similar to the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1. Further in this third embodiment of the horizontal synchronization apparatus as shown in FIGURE 7, as the saw-tooth wave signal n1 which becomes to the high level at any given phase in the pulse period of the retrace pulse signal j1, it is possible to fine-adjust the phase of the retrace pulse signal j1 so as to advance the phase more than that of the first embodiment of the horizontal synchronization apparatus as shown in FIGURE 1. Thus the third embodiment of the horizontal synchronization apparatus as shown in FIGURE 7 is able to perform a very exact horizontal scanning of images. Further, in the embodiments of the horizontal synchronization apparatus as shown in FIGURE 1, 5 and 7, the oscillating circuits 24, 44 generate the reference horizontal pulse signal d1 and the bi-level signal e1, respectively, by processes of shaping ramp signals from ramp signal oscillators to produce pulses at any given phase position, or by processes of dividing a clock signal with a frequency n times the horizontal frequency by using counters (n: any given natural number), and then generates the horizontal frequency pulse of proper phase by using signals on the output terminals and the clock signal. As described above, the present invention can provide an extremely preferable horizontal synchronizing apparatus, which prevents phase errors between retrace pulses and bi-level signals from phase locked loops, when pulse widths of the retrace pulses have varied. Accordingly distortions of images on screens of picture tubes due to brightness changes etc. are effectively prevented so that it is able to give a good impression on viewers. While there have been illustrated and described what are at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the central scope thereof. Therefor, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments falling within the scope of the appended claims.

Claims: A horizontal synchronizing apparatus for use in a television receiver to display images on a display device, the apparatus comprising: a horizontal synchronizing signal source (11) for providing a horizontal synchronizing signal (a1); a phase locked loop (20, 40), having an input (21) connected to the horizontal synchronizing signal source (11), for producing and outputting a pulse signal synchronized to the horizontal synchronizing signal (a1) applied to the input (21); a phase controlled loop (30) comprising: a phase detection circuit (32), having a first input (31) connected to the output of the phase locked loop (20, 40) and a second input (35), for outputting a signal based on the signals input at the first and second inputs; filter means (33) connected to the phase detection circuit (32) for producing and outputting a control signal (g1) by filtering out undesired components of the signal output from the phase detection circuit; and phase controllable means (34), having a control input (g1) coupled to the output of the filter means (33), for producing driving pulses in response to the control signal received at the control input; and a horizontal deflection circuit (12, 13) for generating a deflection signal in response to said driving pulses, and also retrace pulses which are delayed from the driving pulses (i1) as a function of a load on the horizontal deflection circuit (12, 13) and which are coupled to the second input of the phase detection circuit (32) as a retrace signal; characterised in that the phase detection circuit (32) is adapted to operate such that no signal is output when the pulse signal output from the phase locked loop is at a first level; a signal having a first polarity is output when the pulse signal output from the phase locked loop is at a second level and the retrace signal is in a first state; and a signal having a second polarity is generated when the pulse signal output from the phase locked loop is at a second level and the retrace signal is in a second state. A horizontal synchronising apparatus for use in a television receiver to display images on a display device as claimed in claim 1, wherein the retrace pulses are coupled to the second input of the phase detection circuit by way of a pulse generating circuit (41) for generating the retrace signal based on the retrace pulses. A horizontal synchronising apparatus as claimed in claim 2, wherein the pulse generating circuit (41) receives a delayed output signal from the phase locked loop, and generates the retrace signal such that, during each period of the retrace pulse, the first state of the retrace signal is generated at the start of the retrace pulse, and continues until the second state of the retrace signal is generated at a subsequent point in the scanning period in response to the output signal received from the phase locked loop (40). A horizontal synchronising apparatus as claimed in claim 2, wherein the pulse generating circuit (41) further includes means (51) for converting the retrace pulses to a sawtooth-wave signal, and, during each period of the retrace pulse, the first state of the retrace signal is generated at a predetermined phase in the saw-tooth waveform, and continues until the second state of the retrace signal is generated at a subsequent predetermined point in the scanning period.

Inventors: SUMIYOSHI HAJIME, SUMIYOSHI, HAJIME                              V., SUMIYOSHI, HAJIME, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA AVE KK, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA AVE CO., LTD
Application year: 1994
Main classification: H04N5
IPC codes: H04N5