Threshold voltage extracting method and circuit using the same

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least one first (M1) and one second (M2) transistor of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT), b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents, c) a first (VDD) and a second (GND) potential reference, and d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals. The control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) and second (E2) end terminals respectively to said first (VDD) and second (GND) potential references. The output (OT) is coupled to one (E1) of said end terminals.

Description: The present invention relates to a transistor threshold voltage extraction method in accordance with the preamble of claim 1 and a circuit in accordance with the preamble of claim 4. Threshold extraction finds various applications in the field of the characterisation of electronic devices, level translation, absolute or relative temperature measurement, temperature compensation, and compensation of process parameters. A specific panorama of this subject is set forth in the article by Zhenhua Wang, "Automatic Vt Extractors... and Their Applications", in IEEE Journal of Solid-State Circuits, Vol. 27 No. 9 pages 1277-1285, September 1992. This article makes known the circuit shown in FIG. 1 annexed hereto. It comprises two n-channel MOS transistors M1 and M2 having the same threshold voltage and a current mirror MC having an input terminal IM and an output terminal OM. It has an input IT and an output OT. The source terminals S1 and S2 of the transistors M1 and M2 are connected to a ground terminal GND, their drain terminals D1 and D2 are respectively connected to the terminals IM and OM, and their gate terminals G1 and G2 are respectively connected to the input IT and output OT. In addition the gate and drain terminals of the transistor M2 are connected together. The potential at the output OT is given by a linear combination of the input potential IT and the threshold voltage of the transistors M1 and M2. This depends only on geometric parameters with the exception however of the potential at the input IT. Again, said article proposes a variation of the circuit mentioned above in which by selecting the W:L ratio of the transistor M1 equal to one fourth of the W:L ratio of the transistor M2 and connecting to the output of the above circuit an amplifier with gain of two, there is achieved at the output a potential equal to the sum of the potential at the input IT and the threshold voltage of the transistors M1 and M2. Said circuits have the advantage of extracting the threshold voltage free from body effect since the source terminal of the n-channel transistors is connected to the substrate (in the case of N-well process) or to the process well (in the case of P-well process). Other circuits require having separate wells in which to insert the transistors which are desired free of body effect, or limitation of threshold extraction to transistors of a single polarity. A further prior art solution is disclosed in the patent application No. GB-A-2071955 which relates to a current stabilizer comprising a first and a second parallel current path being coupled to each other via a first and a second current coupling circuit. However, this document relates substantially to a differential amplifier which measures the source-gate voltage of a transistor and applies such a measured voltage, attenuated by a k factor, to the gate electrode of a further transistor. The purpose of the present invention is to supply an alternative circuit to that of the prior art. Said purpose is achieved by means of the method having the functions set forth in claim 1 and by means of the circuit having the characteristics set forth in claim 4 while additional advantageous aspects of the present invention are set forth in the dependent claims. By using a voltage divider and an appropriate bias network for feedback of the transistor connected to the extractor circuit output, there are achieved the same advantages as those of the circuit of the prior art but with extreme simplicity and effectiveness. In addition, two alternative solutions have been found to reduce the contribution of the potential at the input of the circuit on the extracted threshold. The first consists of connecting in cascade several extractor circuits in accordance with the prior art but using transistors all having essentially the same threshold. The second consists of supplying at the input of the circuit a predetermined potential and subtracting said potential from the output while making the potential practically equal. These two solutions are of course applicable both to the extractor circuit in accordance with the present invention and to those in accordance with the prior art. The present invention also relates to a circuitry system using and comprising a circuit in accordance with the present invention for operation independently of the temperature and/or dispersion of the process parameters and having the characteristic set forth in claim 11. The present invention is disclosed by the description given below considered together with the annexed drawings in which: FIG. 1 shows a circuit in accordance with the prior art, FIG. 2 shows a first circuit in accordance with the present invention, FIG. 3 shows a second circuit in accordance with the present invention, and FIG. 4 shows a third circuit in accordance with the present invention. The circuit of FIG. 2 comprises two n-channel MOS transistors M1 and M2 having essentially the same threshold voltage and a current mirror MC having an input terminal IM and an output terminal OM. It has an input IT and an output OT. The source terminals S1 and S2 of the transistors M1 and M2 are connected to a ground terminal GND while their drain terminals D1 and D2 are connected respectively to the terminals IM and OM and their gate terminal G1 is connected to the input IT. The circuit also comprises a transistor M3 having its drain terminal D3 connected to a power supply terminal VDD, a gate terminal G3 connected to the terminal D2 and a source terminal S3 connected to the output OT and also comprises a voltage divider VD having an intermediate tap E3 and two end terminals E1 and E2. The tap E3 is connected to the terminal G2, the first terminal E1 is connected to the output OT and the second terminal E2 is connected to a ground terminal GND. As may be seen, the output section of the circuit comprises a feedback loop. The terminals VDD and GND could be replaced by two generic potential references without changing essentially the operation of the circuit. The divider VD is generally provided by means of two two terminal elements connected in series. It is also possible to not connect the tap E3 directly to the terminal G2 but to place between them a third two terminal element even analogous to the first two. A very simple manner to provided the three two terminal elements is by means of resistors whose reciprocal value can be well-controlled during production. Alternatively at least the first two two terminal elements can be provided by means of two diode-connected MOS transistors or in many other different manners. In the general case of using three two terminal elements, e.g. three resistors, their value should be chosen by the designer on the basis of the requirements of the system in which the circuit is to be inserted. It is not excluded that the value of one of them could be null. The potential at the output OT is given by a linear combination of the potential at the input IT and the threshold voltage of the transistors M1 and M2. This depends only on geometric parameters excepting the potential at the input IT. The simplest case and hence the most advantageous is to use as divider VD a divider by two and consequently a mirror MC having current gain between input and output equal to four, i.e. the square of the reciprocal of the division ratio (naturally the true values depend on the manufacturing tolerances). In this manner the potential at the output OT is given by the sum of the potential at the input IT and the threshold voltage. In the circuit of FIG. 2 the transistors are operated in saturation conditions to take advantage of the fact that in this manner the current in the transistors does not depend (in a first approximation) on the voltage VDS. The operating principle of the output part of the circuit is as follows. The potentials of the circuit are stabilised at a value such that there are no currents flowing in the gate terminals of the transistors M2 and M3. Since the current flowing in the transistor M3 and in the divider VD is free to take any value, it stabilises at a value such as to hold in balance said divider. If the divider is made up of two equal two terminal elements, the potential at the output OT corresponds to twice the potential at the terminal G2. A second circuit in accordance with the present invention is shown in FIG. 3. It consists of a threshold extractor circuit TE like the one just described and also, for example, the one of the prior art shown in FIG. 1, and of a stage having one input connected to the output OT and having an output of its own UT1. This stage is identical to the extractor circuit of the prior art shown in FIG. 1. It comprises two n-channel MOS transistors M4 and M5 having the same threshold voltage as that of the transistors M1 and M2 and another current mirror MC2 having an input terminal IM2 and an output terminal OM2. It has an input connected to the output OT and an output of its own UT1. The source terminals S4 and S5 of the transistors M4 and M5 are connected to the ground terminal GND, their drain terminals D4 and D5 are respectively connected to the terminals IM2 and OM2, their gate terminals G4 and G5 are respectively connected to the output OT and the output UT1. In addition the gate and drain terminals of the transistor M5 are connected together. If the circuit of FIG. 2 is used as the extractor circuit with a division ratio of 1:2 and current gain of the mirror MC equal to 4 and choosing e.g. the gain of the mirror MC2 approximately unitary and indicating by K4, K5 the W:L ratio respectively of M4, M5, the potential at the output UT1 is given by the sum of the threshold voltage (only one for the four transistors) and the potential of the terminal IT multiplied by a constant having the value: K4 K5 This new constant depends only on geometric parameters and can thus be controlled and made either much greater or much smaller than the old constant depending on requirements. Naturally one or more of such stages could be connected in cascade depending on the value of the desired constant. A third circuit in accordance with the present invention is shown in FIG. 4 and exhibits an output UT2. This is based on a threshold extractor circuit TE like the one described above or even like e.g. the one of the prior art shown in FIG. 1 which supplies to the output OT a potential corresponding to the sum of the threshold and the potential at the input IT. It also comprises two essentially identical two terminal elements and a bias network connected to the two two terminal elements and such as to supply to them an essentially identical bias current. In the embodiment of FIG. 4 the two two terminal elements correspond to two essentially identical p-channel MOS transistors M6 and M7. The transistor M6 exhibits the gate terminal G6 and the drain terminal D6 connected together to ground and exhibits the source terminal S6 and the bulk terminal B6 connected together to the input IT. The transistor M7 exhibits the gate terminal G7 and the drain terminal D7 connected together to the output UT2 and exhibits the source terminal S7 and the bulk terminal B7 connected together to the output OT. The source and bulk terminals of the two transistors M6 and M7 are connected together to avoid body effect on their VDS. This connection requires two separate wells for said transistors. The bias network comprises two current mirrors MC3 and MC4 having input terminals IM3 and IM4 and output terminals OM3 and OM4 respectively. The input IM3 is connected to the transistor M6 and specifically to the source terminal S6 to supply it the bias current. The terminal OM3 is connected to the terminal IM4. The terminal OM4 is connected to the transistor M7 and specifically to the terminal D7 to supply it the bias current. The current flowing in the transistor M6 must therefore be equal to the current flowing in the transistor M7. This happens e.g. if the current gain in both mirrors MC3 and MC4 is unitary. For correct operation of this circuit it is important that the potential at the output OT of the circuit TE not be influenced by the supplied current. In other words, the output resistance of the circuit TE must be quite low. The two two terminal elements can also be provided e.g. by means of two resistors equal or having a given ratio provided the voltage drop at their ends at steady state is equal. More generally, if there is used as the circuit TE a circuit supplying at output a linear combination of the potential at the input and the threshold, the voltage drops at the ends of the two resistors should not be equal but in a ratio corresponding to the coefficient of the linear combination. Two variables influence said voltage drops, namely the value of the resistors and the currents supplied to them by the mirrors. In the foregoing description reference is often made to direct connections between the various circuit elements but it will be clear to those skilled in the art that fairly often indirect connections, i.e. with other, intermediate, circuit elements, which can also be referred to as "couplings", could be used without impairing the operation of the associated circuits. The above described circuits serve to extract the threshold of n-channel MOS transistors. To extract the threshold of p-channel transistors it would be necessary to use dual circuits. Some examples of said duality are that the ground terminals GND must be replaced by power supply terminals VDD, the power supply terminals VDD by ground terminals GND, the n-channel transistors by p-channel transistors, the p-channel transistors by n-channel transistors, etc. It is also possible to use, instead of the MOS transistors, other types of transistors, e.g. the BJT type. In this case however the threshold concept is less accurate and could correspond to that voltage established between base and emitter. The embodiments described above can be brought back to an instruction of the methodological type which consists essentially of using a circuit of the type shown in FIG. 1 and in the use of a voltage divider and an appropriate bias network to feedback the transistor connected to the output of said circuit. The simplest case and hence the most advantageous of said instruction is to use a divider by two and consequently a mirror having current gain between input and output equal to four. Naturally the true values depend on the manufacturing tolerances. In accordance with another aspect the contribution of the constant potential to the input of the extractor circuit is reduced by subtracting said constant potential at output totally or partially. Lastly, as mentioned above, the present invention finds advantageous application in a circuit system for operation independently of temperature and/or dispersion of process parameters. Such a system comprises: a)an operating circuit block, b)at least one threshold extraction circuit in accordance with the above description and having an output, and c)at least one bias network connected at input to said output and connected at output to said block to supply bias currents and/or voltages. The purpose of such a bias network is to generate a bias current or voltage linked to the threshold of a reference element. Assuming that the threshold has a value which depends on a physical parameter and assuming that block operation also has an analogous dependence on the same parameter, by acting on the bias currents and/or voltages applied to the block in relation to the value of said threshold it is possible to compensate for the variations of said parameter (in time or from device to device) to achieve constant block operation. These types of bias networks are well known in the literature and in any case within the capability of those skilled in the art. An example of a voltage supply circuit is found in the article of M. Sasaki and F. Ueno, "A Novel Implementation of Fuzzy Logic Controller Using New Meet Operation", in Proceedings of the THIRD IEEE INTERNATIONAL CONFERENCE ON FUZZY SYSTEMS, Vol. III, pages 1676-1681, 26-29 June 1994.

Claims: Method for determining a threshold voltage of a transistor using a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM), at least one first (M1) and one second (M2) transistor of the same type and having respectively two control terminals (G1,G2) and having essentially the same threshold voltage to be determined by the method and in which said mirror (MC) supplies to said first (M1) and second (M2) transistors respectively through said input (IM) and output (OM) terminals the bias currents with the control terminal (G1) of said first transistor (M1) being connected to a constant potential node (IT) and characterised by the following steps: providing a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals; coupling the control terminal (G2) of said second transistor (M2) to said tap (E3); and, biasing said divider (VD) by coupling said first (E1) end terminalto a first (VDD) potential reference through a third transistor (M3), having its control terminal (G3) coupled to the output (OM) of the current mirror, and said second (E2) end terminal to a second (GND) potential reference so that the potential at one end terminal (E1) of said divider (VD) is indicative of the threshold voltage of the first and second transistors (M1, M2). Method in accordance with claim 1 in which the dimensions of said first and second transistors (M1,M2) are equal and in which the current gain of said mirror (MC) corresponds to the square of the reciprocal of the division ratio of said divider (VD) and in particular corresponds to approximately four. Method in accordance with claim 1 in which the the potential on said end terminal (E1) is given by a linear combination of the constant potential on said constant potential node (IT) and the threshold voltage of the first and second transistors (M1, M2). A transistor threshold voltage extraction circuit having an output (OT) and comprising: a) at least one first (M1) and one second (M2) transistors of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold voltage with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT), b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents, and characterised in that it comprises: c) a first (VDD) and a second (GND) potential reference, and d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals, and in that the control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) end terminal to said first (VDD) potential reference through a third transistor (M3) and said second (E2) end terminal to said second (GND) potential reference; and wherein the output (OM) of the current mirror is coupled to the control terminal (G3) of said third transistor (M3) to provide on one (E1) of said end terminals an output potential which is indicative of the threshold voltage of the first and second transistors (M1, M2). Circuit in accordance with claim 4 in which the dimensions of said transistors (M1,M2) are equal and in which the current gain of said mirror (MC) corresponds to the square of the reciprocal of the division ratio of said divider (VD) and in particular corresponds to approximately 4. Circuit in accordance with claim 4, characterized in that said third transistor (M3) has its main conduction terminals (D3,S3) coupled to said first potential reference (VDD) and to said first end terminal (E1) and in which said second end terminal (E2) is directly connected to said second potential reference (GND). Circuit in accordance with claim 4 and provided by means of MOS transistors operated in saturation condition. Circuit in accordance with claim 4 in which said divider is the resistive type. Circuit in accordance with claim 4 and comprising in addition: a) a first (M6) and a second (M7) two terminal element preferably identical, and b) a bias network (MC3,MC4) connected to said two terminal elements (M6,M7) and designed to supply to them a preferably identical bias current, and in which one terminal (S6) of said first two terminal element (M6) corresponds to said node (IT) and in which said second two terminal element (M7) is connected between said output (UT2) and one (OT) of said end terminals. Circuit in accordance with claim 4 and comprising in addition: a) at least one third (M4) and one fourth (M5) transistor of the type having respectively two control terminals (G4,G5) and having a threshold voltage essentially equal to said first (M1) and second (M2) transistors with the control terminal (G4) of said third transistor (M4) coupled to one (OT) of said end terminals, and b) another current mirror (MC2) having at least one input terminal (IM2) and one output terminal (OM2) coupled respectively to said third (M4) and fourth (M5) transistors so as to supply them the bias currents, and in which the circuit output (UT1) is coupled to the connection of the control terminal (G5) of said fourth transistor (M5) and of the output terminal (OM2) of said other current mirror (MC2). Circuitry system comprising: a) an operating circuit block, b) at least one threshold voltage extraction circuit in accordance with one of claims 4 to 10 and having one output, and c) at least one bias network (MC3,MC4) having an input connected to said output of the threshold voltage extraction circuit and having an output connected to said operating circuit block to supply bias currents and/or voltages.

Inventors: BRUNO DARIO, FRANCHI ELEONORA, GIACALONE BIAGIO, MANARESI NICOLO, BRUNO, DARIO, FRANCHI, ELEONORA, GIACALONE, BIAGIO, MANARESI, NICOLO, Manaresi, Nicolò
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME.
Application year: 1994
Main classification: G05F3
IPC codes: G05F3