ARRANGEMENT FOR READING INFORMATION FROM A TRACK ON A RECORD CARRIER COMPRISING A FAST SETTLING READ AMPLIFIER FOR MAGNETO-RESISTIVE HEADS

Abstract: An arrangement for reading out an information signal from a magnetic record carrier is disclosed. The arrangement comprises a read head having a magneto-resistive (MR) element (Rm1) with a first terminal (3) connected to a first point (13) of constant potential and with a second terminal (4), a bias-current generator (2) having an output (5) for supplying a bias-current to the MR element and an amplifier circuit (1) having a first terminal (6) coupled to the output (5) of the bias-current generator (2) and a second terminal (7) coupled to the second terminal (4) of the magneto-resistive head (Rm1) so as to form a series arrangement of the bias-current generator, the amplifier circuit and the magneto-resistive element. At an output terminal (8) the information signal is available. The amplifier circuit (1) comprises a MOS transistor (T1) coupled between the output terminal (8) and the second terminal (7). A feedback circuit having a low cut-off frequency (R1, C1) provides a bias voltage to the gate of the MOS transistor (T1) and forces the bias current of the bias current generator (2) to flow through the MR element. Fast settling of the arrangement is possible by short-circuiting (S1) the resistor (R1), the high charge current for capacitor (C1) being supplied by a buffer amplifier (310). The buffer amplifier (310), the resistor (R1) and the switch (S1) provide fast settling without generating undesired off-set.

Description: Arrangement for reading information from a track on a record carrier comprising a fast settling read amplifier for magneto-resistive heads The invention relates to an arrangement for reading out an information signal from a magnetic record carrier, comprising: a read head having a magneto-resistive element with a first terminal connected to a first point of constant potential, and with a second terminal, a bias-current means for supplying a bias-current, an amplifier circuit comprising an output terminal for supplying the information signal, a first terminal coupled to the bias-current means and to the output terminal, a second terminal coupled to the second terminal of the magneto-resistive head so as to form a series arrangement of the bias-current means, the amplifier circuit and the magneto-resistive element between a second point of constant potential and said first point of constant potential, the amplifier circuit further comprising a first transistor, a feedback circuit having an input terminal coupled to the output terminal of the amplifier circuit and having an output terminal, a load impedance and a capacitor element, a first main flow terminal of the first transistor being connected to the second terminal of the amplifier circuit, a second main flow terminal of the first transistor being coupled to the first terminal of the amplifier circuit, a control terminal of the first transistor being coupled to the output terminal of the feedback circuit, the control terminal being further coupled to the first point of constant potential via at least the capacitor element, the load impedance being coupled to the output terminal of the amplifier circuit. Such an arrangement is known from United States Patent No. 5,270,882. In this known arrangement current biasing and current sensing of the magneto-resistive (MR) element is combined, thereby providing a low-noise amplification. Read heads with MR elements and thin film inductive write heads, mounted on arms, are used in mass storage devices such as disk drives. Disk drives are equipped with multiple platters, each side of which is used for writing and reading the information. In modern systems servo patterns are embedded in radial patterns between the data on the disk. Writing of data is interchanged with reading to remain on track. Read-to-write and write-to-read transient times should be as short as possible. The capacitor element and the feedback circuit in the arrangement provide a low bandwidth and therefore the transient response time is intrinsically long. An approach to realize short transient times is to leave the read amplifier powered during writing. This, however, costs extra power. Moreover, crosstalk from the write drivers to the read amplifiers will influence the DC settings of the read amplifiers. The DC-offset caused by the crosstalk is amplified in the read amplifier and may overload the output stages thereof. Similar problems are encountered when the information on the platters is arranged in "cylin¬ ders". During reading the system switches from platter to platter without mechanical delay introduced by repositioning of the armstack. To avoid electrical delays head switching should be fast. Powering a read amplifier for each read head is not attractive, in particular in battery operated portable equipment. A second option is to use only one read amplifier and to switch the individual read heads in circuit connection with the read amplifier. Applying this technique to the known arrangement would seriously limit the speed of switching between the different MR elements. MR elements have large spread in resistance and bias current settings. After each head change the capacitor element in the amplifier circuit has to be charged or discharged to the new desired voltage. However, in order to obtain a sufficiently low cut-off frequency of the feedback circuit, the DC resistance of the feedback circuit should be high. A typical cut-off frequency is 10 KHz. In the known arrangement the feedback circuit is a transconductance stage having a low transconductance Gm. The maximum output current of such a transconductance stage severely limits the speed of charging and discharging of the capacitor element and gives rise to transients with a duration of hundreds of microseconds. This is too long for fast mass storage devices. In the known arrangement the transconductance Gm of the transconductance stage is temporarily increased by increasing its bias current. This, however, causes unacceptable errors because of increased offset of the transconductance stage. It is an object of the invention to provide a fast settling feedback circuit for use in the known arrangement. In accordance with an aspect of the invention, the known arrangement is characterized in that the feedback means comprises: voltage buffer means having an input coupled to the input terminal of the feedback circuit and having an output; a first series resistor connected between the output of the voltage buffer means and the output terminal of the feedback circuit; and a switch connected in parallel with the first series resistor and operable in response of a control signal. The voltage buffer means provide the high currents needed to charge or discharge the capacitor element when the series resistor is short circuited by the switch connected in parallel to the series resistor. Only a passive element, that is a bias current free element, is short circuited and no offset is created by the short circuiting. In this way a very fast settling is possible without loosing the desired accuracy in settling of the read amplifier. A first fast settling arrangement is characterized in that the voltage buffer means comprises a first current source and a second current source, a diode connected second transistor and a third transistor, a first main flow terminal of the second transistor and a first main flow terminal of the third transistor being interconnected and coupled to the first point of constant potential via the first current source, a second main flow terminal of the second transistor being coupled to the second point of constant potential via the second current source and forming the output of the voltage buffer means, a second main flow terminal of the third transistor being coupled to the second point of constant potential, and a control terminal of the third transistor forming the input of the voltage buffer means and being coupled to the input terminal of the feedback circuit. The voltage buffer means provide a voltage drop across the first and second terminals of the amplifier which is as small as possible and accurately known. As a consequence the voltage drop across the bias-current generator can be made as large as possible within the available supply voltage. This provides the possibility to design a bias- current source having low noise. The current that can be sunk by the first current source limits the discharging time of the capacitor element. To improve the settling speed, the arrangement may be further characterized in that the voltage buffer means further comprises a third current source connected between the second main flow terminal of the third transistor and the second point of constant potential and in that the first current source comprises a diode arrangement, a bias resistor and a fourth transistor having a first main flow terminal connected to the first point, a second main flow terminal connected to first main flow terminals of the second and third transistors and a control terminal coupled to the second main flow terminal of the third transistor via the diode arrangement and to the first point via the bias resistor. The fourth transistor can sink currents which are up to two orders of magnitude larger than the current through the third current source. The charging time of the capacitor element can be shortened in an arrangement which is characterized in that the voltage buffer means further comprises a fifth and a diode element, a control terminal and a second main flow terminal of the fifth transistor being interconnected and being coupled to the third current source via the diode element, a first main flow terminal of the fifth transistor being connected to the first main flow terminal of the second transistor, and a sixth transistor having a first main flow terminal coupled to the second main flow terminal of the second transistor, a second main flow terminal coupled to the second point and a control terminal coupled to the second main flow terminal of the fifth transistor via the diode element. The additional components provide a class A/B low-ohmic high-current output buffer circuit for quickly charging the capacitor element via the sixth transistor during settling. Another preferred fast settling arrangement is characterized in that the first terminal is coupled to the output terminal of the amplifier circuit via a second transistor having a first main flow terminal connected to the first terminal and a second main flow terminal coupled to the output terminal of the amplifier circuit; and in that the voltage buffer means comprises: a current mirror having an input terminal and an output terminal, a third transistor having a conductivity opposite to the conductivity of the second transistor and having a first main flow terminal coupled to the output terminal of the current mirror and a control terminal connected to receive a reference voltage, a second series resistor connected between the first main flow terminal of the third transistor and the output terminal of the amplifier circuit, a diode connected fourth transistor of the same type as the first transistor, and having a first main flow terminal connected to the first main flow terminal of the first transistor and a second main flow terminal coupled to a second main flow terminal of the third transistor, a fifth transistor of the same type as the first transistor having a control terminal and a first main flow terminal connected to the corresponding terminals of the first transistor and having a second main flow terminal coupled to the input terminal of the current mirror; and a buffer amplifier having an input connected to the control terminal of the fourth transistor and an output connected to the first series resistor. In order to obtain low noise, the first transistor should be large. By cascoding this large transistor with the second transistor the following advantages are obtained. The large first transistor and the bias current generator can have a low output impedance, since they feed their respective currents into a very low-ohmic first main flow terminal of the second transistor. The capacitance between the second main flow terminal and the control terminal of the large first transistor is not Millered. The bias current generator provides lower bias current and a corresponding lower noise because part of the total bias current for the magneto-resistive element is provided by the parallel arranged second transistor. The bias current generator feeds current to a low voltage node, so that a maximum voltage range is available for the bias-current source, so as to enable the bias-current generator to be optimal for low noise. After settling, the current through the second series resistor is zero and the current through the second transistor can be adjusted by means of a voltage applied to the control terminal of the third transistor. The inaccuracy which is left is caused by charge injection of the switch which short-circuits the first series resistor. After settling is finished the switch is opened and some capacitive charge is extracted from the capacitor element. This charge is about equal to half the charge in the channel of the switching transistor. This charge extraction can be compensated conventionally by switching a small capacitor which is connected to the capacitor element to the second point of constant potential. However, this causes crosstalk from the power supply voltage to the capacitor element. To avoid these problems the arrangement is characterized in that the switch comprises: first and second switching transistors of a first coductivity type, a first main flow terminal of the first switching transistor being connected to a second main flow terminal of the second switching transistor, a second main flow terminal of the first switching transistor being connected to a first main flow terminal of the second switching transistor; first and second driver transistors of a second conductivity type having first main flow terminals connected to a supply voltage terminal and having control terminals connected to a control input for receiving the control signal, a second main flow terminal of the first driver transistor being connected to the control terminal of the first switching transistor, a second main flow terminal of the second driver transistor being connected to the control terminal of the second switching transistor; third and fourth driver transistors of the first conductivity type having control terminals connected to the control input, a first main flow terminal of the third driver transistor being connected to the second main flow terminal of the first switching transistor, a first main flow terminal of the fourth driver transistor being connected to the second main flow terminal of the second switching transistor, a second main flow terminal of the third driver transistor being connected to the second main flow terminal of the first driver transistor, a second main flow terminal of the fourth driver transistor being connected to the second main flow terminal of the second driver transistor. This switch arrangement feeds half of the total channel charge of the first and second switching transistors back to the capacitor element and compensates the extraction of charge from the capacitor element. All embodiments may be used in dual construction in combination with one or two MR elements. In the latter case two elements read the same data track from the record carrier and the non-linearities of the MR elements cancel each other. In the case of two MR elements the noise contribution of the first transistors can be reduced further by coupling the capacitor element of the amplifier circuit of the first arrangement to the second terminal of the amplifier circuit of the second arrangement and the capacitor element of the amplifier circuit of the second arrangement being coupled to the second terminal of the amplifier circuit of the first arrangement. The capacitor elements are cross-coupled to the second terminals of the individual amplifiers instead of to ground. The cross-coupling causes a shunting of the noise resistances of the first transistors and effects a reduced noise voltage contribution of the first transistors. The above and other features and advantages of the invention will be apparent from the following description of exemplary embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 shows a known arrangement for reading information from a track on a record carrier, Figures 2A, 2B, 2C show versions of a feedback circuit for use in the arrangement of Figure 1, Figures 3A, 3B, 4A, 4B and 5 show versions of an amplifier circuit for use in the arrangement of Figure 1, Figure 6 shows a balanced arrangement according to the invention, Figure 7 shows an arrangement having shielding means provided over the electrical connection between the MR element and the amplifier circuit, Figure 8 shows the reading of information from a track on a disk shaped record carrier, Figure 9A and 9B show circuit parts that can be coupled together so as to realize a multiplexed read out by means of two or more separate MR elements, Figure 10 shows the circuit part for realizing a multiplexed read out by means of two or more separate heads, each head having two MR elements, Figure 11 shows an arrangement according to the invention, Figure 12 shoes a voltage follower for use in the arrangement of Figure 11, Figure 13 shows a transistor switch for use in an arrangement according to the invention, and Figure 14 shows an embodiment of a balanced arrangement according to the invention. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Figure 1 shows the basic circuit construction of the arrangement known from US patent 5,270,882, which comprises a read head (not shown) having a magneto-resistive (MR) element R^, a bias-current generator 2 for generating a bias-current I bl , and an amplifier circuit 1. A first terminal 3 of the magneto-resistive element R ml is connected to a first point of constant potential 13, which is ground potential. An output 5 of the bias-current generator 2 is coupled to a first terminal 6 of the amplifier circuit 1. A second terminal of the bias-current generator 2 is coupled to a point of constant potential 12 (the positive supply voltage, denoted by +). A second terminal 7 of the amplifier circuit 1 is coupled to a second terminal 4 of the magneto-resistive element R ml . An output terminal 8,8' is available for supplying the information signal read out. The amplifier circuit 1 comprises a transistor T l 5 a feedback circuit F j and a capacitor element C 1 . The transistor T j is in the form of a MOSFET or a jFET. Its source terminal is coupled to the second terminal 7 of the amplifier circuit 1. Its drain terminal is coupled to the first terminal 6 of the amplifier circuit 1. Its gate terminal is coupled to the first point of constant potential 13, via the capacitor element C j . Further, the feedback circuit F 1 is coupled between the gate of the transistor T j and the terminal 6 of the amplifier circuit 1. The drain terminal of the transistor T j is further coupled to a reference point 10 via a load impedance R j . At the reference point 10 a voltage V ref is available, which needs not be a constant potential, but may vary, as will be explained later. At output terminal 8,8' the voltage occurring over the load impedance R ] is present. The bias-current generator 2, the amplifier circuit 1, more specifically the transistor T j in the amplifier circuit 1, and the MR element R ml form a series arrangement between the terminals 3 and 12. As can be seen from the figure, the MR element R ml is connected to ground via its terminal 3. Further, when used in an arrangement for reading an information signal from a disk shaped record carrier (not shown), the disk is also preferably electrically connected to ground. This limits the possibility that a voltage difference can be built up between the head and the disk. This avoids electrical discharges that could otherwise occur between head and disk, which discharges could damage the head. The MR element R ml , the amplifier 1 and the bias-current generator 2 form a series arrangement between the two (supply) terminals 3 and 12. Thus, the current supplied by the bias-current generator 2 is fed to the MR element R. n l so as to bias the MR element, as well as to the amplifier circuit 1. This bias current through the amplifier circuit results in a certain noise contribution, which is lower when the current through the amplifier circuit is higher. If the amplifier circuit would be in parallel to the MR element and the bias-current generator, a larger current would be needed to bias the MR element and to supply the input stage of the amplifier circuit with the current needed to obtain a low noise contribution in the amplifier circuit. Thus the arrangement of Figure 1 produces less noise and requires less bias current, with is a major advantage in the case of battery powered supply voltages. When the amplifier circuit has only one transistor, such as in the embodiment of Figure 1 , instead of two in the case of a long-tailed pair, the amplifier circuit has a lower noise contribution. Variations in the magnetic field detected by the MR element R ml lead to variations in the resistance value of the MR element. The gate of transistor T l is coupled to ground for AC signals by means of the capacitor C^ This means that for AC signals, the terminal 4 of the MR element R ml lies virtually to ground. As a result of this, variations in the resistance value of the MR element can only lead to variations in the current through the series arrangement. These current variations are fed via the load impedance R n to the terminal 10, and lead to a voltage variation across the load impedance R . This voltage variation is detected at the terminals 8,8' as the output signal of the amplifier circuit. The feedback circuit F j realizes a low cut-off frequency. In order to enable integration of the capacitor C ls the resistance value of F j should be high. This results in the transistor Tj acting like a diode for DC signals, so that the bias-current I bl can be fed to the MR element R^. The feedback circuit F- is an impedance network. In its most simple form, the feedback circuit can be a resistor. In order to make the arrangement suitable for use at low supply voltages applied to the terminals 3 and 12, it is necessary to make the voltage drop between the terminals 4 and 6 as small as possible, so that a maximum voltage range is available for the bias-current source (2), so as to enable the bias-current source to be optimal for low noise. Figure 2A shows a further-elaborated version of the feedback circuit F j , so as to make it high ohmic and to realize a voltage drop across the transistor T 1 which is as small as possible. The feedback circuit F j comprises a transistor T 3 , which is a MOS transistor, a bipolar transistor T 4 and a resistor R 2 . Both transistors T j and T 3 are of the same type, MOSfet or jFET. The gate terminal of the transistor T, is coupled to the terminal t j of the feedback circuit. The terminal t λ is coupled to the gate terminal of the third transistor T 3 via the resistor R { . The source terminal of the third transistor T 3 is coupled to the emitter terminal of the fourth transistor T 4 . The base terminal of the transistor T 4 is coupled to the terminal t 2 of the feedback circuit, which terminal is coupled to the terminal 6 of the amplifier circuit. The gate and drain terminal of the transistor T 3 are interconnected so as to form a diode. Further, the interconnected gate and drain terminals are coupled to the point 12 of constant potential via a current source 21. The emitter of the transistor T 4 is coupled to the first point of constant potential 13 via a current source 24. Further, the collector of the transistor T 4 is coupled to the second point of constant potential 12. The current sources provide current supply for the transistors T 3 and T 4 . By means of the feedback part of Figure 2 A, a voltage shift of -V^ + V d is obtained between the terminals t j and t 2 , where V Λ is the threshold voltage of a MOS transistor, such as the transistors T j and T 3 , and V d is the voltage across a bipolar diode. As a result, the voltage difference between the terminals 6 and 7 of the amplifier circuit of Figure 1, is roughly V d , or substantially 0.7 V. More specifically, the voltage difference between the terminals 6 and 7 is V d + V chl " ch2> where V chl and V ch2 are the channel voltages of the transistors T j and T 3 respectively, which are dependent of the drain current through those transistors (V ch = V gs - Vtø, where V gs is the gate-source voltage and V^ the threshold voltage of a transistor). Further, the impedance formed by the feedback circuit between the terminals t t and t 2 is high-ohmic so as to obtain the desired low value for the cut-off frequency of the lower band edge of the frequency characteristic of the amplifier circuit. The circuit of Figure 2 A has current sources coupled to both the positive (12) as the negative (13) supply voltage terminal. Figure 2B shows a further elaborated version of the feedback circuit of Figure 2A, which has current sources connected to the positive supply terminal only. The circuit of Figure 2B further comprises a diode arrangement 25 of one or more diodes, a bipolar transistor T 24 , a current source 22 and a resistor R 24 . The current source 22 is coupled between the point 12 of constant potential and the collector of the transistor T 4 , and is further coupled via the diode arrangement 25 to the base terminal of the transistor T 24 . The base terminal of the said transistor is also coupled to the point 13 of constant potential via the resistor R 24 . The emitter of the transistor T 24 is coupled to the point 13 of constant potential, and its collector is coupled to the interconnected emitter and source of the transistors T 4 and T 3 respectively. The circuit part formed by the elements 22, 25, R 24 and T 24 effectively replaces the current source 24 in Figure 2A. The circuits of the Figures 2 A and 2B further show a switch S j connected in parallel to the resistor Ri . When activating the amplifier circuit of Figure 1, or when the current value through the MR element should be changed, the capacitor C 1 must initially be charged (or discharged) so that the amplifier circuit can settle to the new situation. In order to settle fast, the resistor R λ is short-circuited by the switch S 2 under the influence of a switching signal applied to the control signal input 100, so that the current for charging the capacitor C 1 can be supplied by the current source 21, or discharging can take place via the current source 24. The charging time of the capacitor C { is thus limited by the maximum current that can be supplied by the current source 21, and the discharging time is limited by the maximum current that can be received by the current source 24. Replacing the current source 24 of Figure 2 A by the elements 22, 25, R 24 and T 24 in Figure 2B already offers a shortening of the discharge time, as the transistor T 24 can sink currents which are up to two orders of magnitude larger than the current through the current source 22. Figure 2C shows a feedback circuit in which the charging time of the capacitor Ci can be shortened. The circuit of Figure 2C further comprises a MOS transistor T 5 , a bipolar transistor T 6 and a bipolar diode element 40. The gate and drain terminals of the transistor T 5 are interconnected and both coupled to the current source 21 and to a base terminal of the transistor T 6 via the diode element 40. The source terminals of the transistors T 3 and T 5 are interconnected. A collector terminal of the transistor T 6 is coupled to point 12 of constant potential. An emitter terminal of the transistor T 6 is coupled to the interconnected gate and drain terminals of the transistor T 3 . The circuit comprising the transistors T 3 , T 6 and T 5 and the diode element 40 form a class-A/B circuit and provides a quicker charging of the capacitor element C j during initialisation of the arrangement by means of current supplied by the transistor T 6 . Figure 3A shows a further-elaborated version of the amplifier circuit 1 of Figure 1. The circuit of Figure 3 A comprises a bipolar transistor T 8 , which has its base terminal coupled to the source terminal of the transistor T l 5 its collector to the point 13 of constant potential, and its emitter coupled to the reference point 10. Further a current source 36 is coupled between the reference point 10 and the second point 12 of constant potential. This circuit has the advantage that the DC voltage present at the reference point 10 follows the DC voltage present at the terminal 7 of the amplifier circuit. This means that voltage variations occurring across the MR element R^ do not appear across the load resistor R n . The voltage difference between the terminals 7 and 10 is equal to V d . If F j is one of the circuits of the Figures 2A, 2B or 2C, the voltage difference between the terminals 6 and 7 equals V d + V chl - V ch2 , see above, so that the DC offset across the load resistor R 11 is low (V chl - V ch2 ). Only voltage variations in the transistor T 1 ; resulting from the current variations through the transistor T j , still appear across the load resistor R n . A further improvement of the amplifier circuit of Figure 3A is disclosed in Figure 3B. The amplifier circuit 1 further has a MOS transistor T 10 and a bipolar transistor T n . The gate of transistor T 10 is connected to the gate of the transistor T 1 ? the drain is coupled to the point 12 of constant potential via a current source 54, as well as coupled to the base of the transistor T π via a diode arrangement 44 consisting of one or more series connected diodes. The source of the transistor T 10 is coupled to the collector of the transistor T π as well as to the base of the transistor T 8 . The emitter of the transistor T n is coupled to the point 13 of constant potential. The voltage difference between the gate of the transistor T : and the terminal 10 equals V gs - V d , where V gs is the gate-source voltage of the transistor T 10 . If F j is again one of the circuits of the Figures 2A, 2B or 2C, the voltage difference between the gate of the transistor T j and terminal 6 equals V gs ' - V d , where V ' is the gate-source voltage of the transistor T 3 . The voltage across the load resistor R n now equals V gs ' - V gs . If the current through transistor T 10 is made equal to the current through the transistor T 3 , and further the transistors T 10 and T 3 have equal dimensions, the said voltage becomes practically zero, independent of the value of the MR bias current. It will be clear that, instead of the combination of the current source 54, the diode arrangement 44 and the transistor T π , a current source could have been coupled between the emitter of the transistor T π and ground potential. Figure 4A shows a further improvement of the amplifier circuit of Figure 3A. The amplifier circuit comprises a bipolar transistor T 7 which is coupled between the drain terminal of the transistor T l and the terminal 6. Its base terminal is coupled to the point 12 of constant potential via the current source 36, and to the point 10 via a resistor R 5 . By means of the transistor T 7 , the transistor T j is cascoded in order to get a higher output impedance at the terminal 6 and to prevent the Millering of the drain-gate capacitance of transistor T j . Figure 4B shows an alternative of the amplifier circuit of Figure 4A. It additionally comprises a transistor T 9 , resistors R 2 , R 3 and R 4 and a current source 31. The base terminal of the transistor T 7 is connected to an emitter terminal of the transistor T 9 , a base terminal of which is coupled to the source terminal of the transistor T τ via the resistor R 2 . The collector of the transistor T 9 is coupled to the point 13 of constant potential. The emitter of the transistor T 9 is further coupled to the point 12 of constant potential via the current source 31. The base of the transistor T 9 is coupled to the emitter of the transistor T 8 via the resistor R 3 , and to the reference point 10 via the resistors R 3 and R 4 . Further, the construction of the transistors T 7 and T 9 provides a voltage at the interconnection node 32 of the emitter of transistor T 7 and the drain of transistor T ls which is roughly half way between the voltages present on the terminals 7 and 6. This means that a voltage difference of V d /2 is present between the node 32 and the terminal 7, and between the nodes 32 and the terminal 6, as the voltage difference between the terminals 6 and 7 is V d , as explained previously. It should be noted that Figure 4 A and Figure 4B are derived from Figure 3 A by adding the cascode transistor T 7 , using different biasing schemes. The same cascode principles can be added to the circuit of Figure 3B. Figure 5 shows another embodiment of the amplifier circuit. The amplifier circuit of Figure 5 is a further elaboration of the circuit of Figure 3B. Also in this case cascoding can be applied. The amplifier circuit of Figure 5 differs from the amplifier circuit of Figure 3B in that it further comprises an impedance network 71. Further, diode 46 and a capacitor element C 3 are present. An emitter terminal of the transistor T 8 is coupled to the first terminal 6 of the amplifier circuit via the impedance network 71 , as well as to an output terminal of the current source 36. The collector terminal of the transistor T 8 is coupled to a terminal of the load impedance R n '. From the Figure, it appears that the reference point 10 in Figure 3B has now become the reference point 10', which has the same potential as the first point 13 of constant potential, that is ground. The base terminal of the transistor T π is coupled via the diode 46 to the point 13 of constant potential. The base terminal of the transistor T 8 is coupled to the first point 13 of constant potential via the capacitor element C 3 . Signal currents I s generated by the MR element R^ flow from the MR element to the terminal 7, via the transistor T 1} the impedance network 71 and the transistor T 8 to the load impedance R 11 ? the terminals 48,48' now forming the output terminal of the arrangement. The capacitor element C 3 filters out a noise component that would otherwise be present in the output signal at the output terminal 48,48'. It should be noted that the embodiments of the Figures 3A, 3B, 4A and 4B, where the output 8,8' of the amplifier circuit is connected to the terminals of the load impedance R n , are particularly suitable for use in an arrangement provided with only one MR element R^. The embodiment of Figure 5, where the output of the amplifier circuit is formed by the terminals 48,48' is particularly useful in an arrangement having two MR elements R^R^. It should be further noted that likewise the circuits of the Figures 3A, 3B, 4A and 4B could have been provided with a load impedance R π ' coupled between the collector of the transistor T 8 and the point 13 of constant potential, which is preferred for an arrangement having two MR elements. In such arrangements provided with two MR elements R mi and R m2 , see also the arrangement of Figure 6, each MR element is coupled to an amplifier circuit of a type as described above. The output of such an arrangement is then formed by the terminals 48 of each of the two amplifier circuits. Figure 6 shows an embodiment of an arrangement which is in the form of a balanced circuit, and comprises two MR elements. The arrangement comprises a read head having a first and a second magneto-resistive element R^ and R m2 respectively. Both MR elements R ml and R^ of the head scan the same track (not shown), so that they read the same signal from the track. The left hand part of the circuit shown in Figure 6 is largely identical to the circuit diagram shown in Figure 1. A first terminal 63 of the MR element R m2 is connected to the first point 13 of constant potential (ground). Further, a second bias- current generator 62 is available, having an output for supplying a second bias current (I b2 ). Another terminal of the bias-current generator 62 is coupled to the terminal 12, on which the positive supply voltage is available. The amplifier circuit 61 has a first terminal 66 coupled to the output of the second bias-current generator 62 and a second terminal 67 coupled to the second terminal 64 of the second magneto-resistive head R m2 . The second bias-current generator 62, the second amplifier circuit 61 and the second magneto-resistive element R m2 form a series arrangement between the terminals 12 and 13. The second amplifier circuit 61 comprises a transistor T 2 , which is in the form of a MOS transistor, a load impedance R 12 , a feedback circuit F 2 and a capacitor element C 2 . The source terminal of the transistor T 2 is coupled to the second terminal 67 of the amplifier circuit 61. The drain terminal of the transistor T 2 is coupled to the first terminal 66 of the amplifier circuit 61. The gate terminal of the transistor T 2 is coupled to the first terminal 66 of the amplifier circuit 61, via the feedback circuit F 2 . Further, the gate terminal of the transistor T 2 is coupled to the source terminal of the transistor T j via the second capacitor element C 2 . Moreover, the gate terminal of the transistor T j is coupled to the source terminal of the transistor T 2 via the capacitor element C j . It is however also possible to couple both capacitor elements to the point 13 of constant potential (ground). However the cross-coupled connection of the capacitor elements, as shown in Figure 6, is preferred as it reduces the noise. A load impedance R 12 is coupled between the terminal 66 of the amplifier circuit 61 and a reference point 10", on which point a reference voltage V ref2 is available. The voltage V ref2 may differ from the voltage V refl , as the DC voltages across the MR elements R ml and R^ can be different owing to mismatch of the resistance of the MR elements and/or unequal MR bias currents I bl and I b2 . Constructions similar to the feedback circuits of the Figures 2A, 2B or 2C can be used for the feedback circuit F 2 of Figure 6. It will further be clear that the amplifier circuits as shown in the Figures 3A, 3B, 4A, 4B and 5 can be used for the amplifier circuit 61 of Figure 6. It has been said previously that the two MR elements read a signal from the same track. When the two output signals V lout and V 2out are added, an output signal which is the sum of both signals will appear, and systematic DC offset in both amplifier circuits 1 and 61 will cancel. This systematic DC offset is for example the term V chl -V ch2 between the nodes 6 and 10 (Figure 3A), discussed previously, or the DC voltage across the grounded load resistors, such as R n ' in Figure 5. Figure 7 shows a further improvement of the arrangement having only one MR element. Figure 7 shows the provision of an electro-magnetic shielding 75 over the electrical connection 76 connecting the terminal 4 of the MR element R,^ with the terminal 7 of the amplifier circuit 1. The shielding 75 is connected to ground via the electrical connection 77. This shielding prevents electro-magnetic stray fields from disturbing the signals read out by means of the head. The shielding can be realized by means of a kind of coaxial cable. However, also simpler constructions can be used for the shielding means, for instance by wrapping the ground conductor around the signal carrying conductor. Figure 8 shows a top view of the reading out of information from a track on the disk shaped record carrier 80, by means of a read head having two MR elements. Both MR elements R ml and R m2 are coupled together via an insulating layer 90 and both read the full width of the same track 81. The arrangements disclosed are preferably intended for hard disk applications, for low supply voltages, such as 3.3 V + 10% and 5.0 V + 10%. The bias current can be kept low, as the bias current is practically only needed for the MR element. A low-noise amplification of the signals read out can be obtained. The record carrier is preferably connected to ground via an electrical connection. Figures 9A and 9B show units that can be coupled together in order to realize a multiplexed read out of information from a track on a record carrier by means of two or more MR elements. Figure 9A shows the circuit part which is common to all MR elements and Figure 9B shows the circuit part for each MR element. Only one such circuit part for the MR element R mi is shown. For other MR elements the circuit part of Figure 9B should be copied. The common circuit part of Figure 9A shows at the left side of the vertical broken line a circuit part indicated by the reference numeral 100, which circuit part is largely resembles the feedback circuit of Figure 2C. It lacks the resistor R j and the switch S 1? which are included in the circuit part shown in Figure 9B. At the right hand side of the broken line, the circuit part 101 largely resembles the amplifier circuits of Figure 4A and 5. Two or more of the circuits of Figure 9B can be coupled to the common circuit of Figure 9A by interconnecting the terminal k j ' of the common circuit of Figure 9A with the terminals k j of the two or more circuit parts of Figure 9B. In the same way the terminals k 2 and k 2 ', k 3 and k 3 ', and k 4 and k 4 ' are interconnected. Multiplexing is realized by means of the switches S 2 in each of the circuits of Figure 9B. One of the switches S 2 of one of the circuits of Figure 9B coupled to the common circuit of Figure 9A, is opened and the switches S 2 of the other circuits of Figure 9B are closed. In that situation, all of the MR elements R ml are switched off except one, so that the signal read by that MR element is applied to and amplified by the circuit part of Figure 9A. Figure 10 shows the circuit part of a balanced version of the head, comprising two MR elements R ml and R^, in a fashion as shown in Figure 6, where multiplexing is made possible. Figure 10 shows the circuit part including the two MR elements that is separate for each of the heads comprising two MR elements. The circuit part is largely mirror symmetrical, where the left hand part, left from the vertical broken line in Figure 10, is the same as the circuit part of Figure 9B. The circuit part of the transistors T 2 and T 2 and the capacitors C λ and C 2 is identical to the corresponding circuit part of those elements in Figure 6. The circuit part of Figure 9 A is doubled, so as to obtain the common circuit part for each of the heads. The circuit part of Figure 9 A is thus coupled to the left hand part of the circuit of Figure 10, as has been explained above for the interconnection between the circuits of Figure 9 A and 9B. The right hand circuit part of Figure 10 is coupled to a circuit part identical to the circuit part of Figure 10A. Switching the head of Figure 10 into the circuit means that both switches S 2 and S 3 are in the open position as shown. Consequently, the corresponding switches S 2 and S 3 of the other heads coupled to the common circuit are in their closed position. Switching the head off is realized by closing both switches S 2 and S 3 . Figure 11 shows an alternative further-elaborated version of the amplifier circuit 1 of Figure 1. The first terminal 6 of the amplifier circuit 1 is directly connected to the output 5 of the bias current generator 2. However, in contradistinction to Figure 1, the terminal 8, which interconnects the load impedance R u and the feedback circuit F 2 , is connected to the drain of the transistor T j via the collector-emitter path of a NPN transistor T 31 . The emitter of transistor T 31 is connected to the drain of transistor T 1 } the base is connected to a reference point 308 which supplies a reference voltage V ref4 and the collector is coupled to the load impedance R n . The transistors T 2 and T 31 form a cascoded output stage. The collector of transistor T 31 may be connected to the load impedance R n via the collector-emitter path of an optional further NPN cascode transistor (not shown). The feedback circuit F j between the terminals t 2 , which is connected to the output terminal 8, and the terminal t 1 ; which is connected to the gate of transistor T 1 ( comprises a current mirror 300; a PNP transistor T 30 , having its emitter coupled to an output terminal 304 of the current mirror 300 and having its base connected to a reference voltage terminal 306 to receive a reference voltage V ref3 ; a series resistor R a connected between the emitter of the transistor T 30 and the output terminal 8 of the amplifier circuit 1 ; a diode connected transistor T 32 of the same type as transistor T 1 ? having its source connected to the source of transistor T j and its drain coupled to the collector of transistor T 30 ; a transistor T 33 , also of the same type as transistor T l 5 having its gate and source connected to the gate and source of the transistor T λ and having its drain coupled to an input terminal 302 of the current mirror 300; a voltage following buffer amplifier 310 having an input connected to the gate of transistor T 32 ; a high-ohmic series resistor R j connected between an output of the buffer amplifier 310 and the gate of transistor T j ; and a controllable switch S j connected in parallel with the series resistor R 1 # The resistance of resistor R 2 is typically 1 MOhm, the capacitance of the capacitor C j is typically 200 pF, values that can be integrated. The bias current generator 2 can be implemented with a programmable current output digital to analog converter (IDAC) for supplying the bias current of the magneto-resistive element R ml . In the arrangement of Figure 11 the IDAC supplies the variable part of the MR element's bias current, for instance 0 mA to 15.5 mA in steps of 0.5 mA, whereas a fixed current, for example 5 mA, is provided by the low-ohmic cascode output stage T 31 . In order to obtain low noise, transistor T j should be large. The advantages of the cascoding arrangement are: (1) the large low-noise MOS transistor T 2 and the IDAC can have a low output impedance, since they feed their respective currents into a very low-ohmic emitter of the cascode transistor T 31 ; (2) the drain- to-gate capacitance of the large transistor T j is not Millered; (3) the IDAC provides lower bias current and a corresponding lower noise; and (4) the IDAC feeds its current to a low voltage node, which permits a high voltage drop across the IDAC which results in a further reduction of noise. The transistors T 32 and T 33 are small in respect of transistor T j , but are of the same type. The gate-source voltage of transistor T j is copied to transistor T 32 by means of transistor T 33 and current mirror 300. Therefore on both sides of resistor R 2 the DC voltages with respect to ground are substantially equal. During settling, a suitable control signal closes the switch S 2 across resistor R 2 and buffer amplifier 310 provides the high charge or discharge current for recharging capacitor C j . Only passive components, i.e. the resistor R 1 ? are short circuited during settling. After settling the current in resistor R j is zero. The current in resistor R a is zero as well, because any current through resistor R a is counteracted by an increased or decreased current through transistor T j until the current through resistor R a is zero. The voltage at the output terminal 8 is equal to the reference voltage V ref3 at the base of transistor T 30 plus the base-emitter voltage V be of transistor T 30 . The voltage drop across the load resistor R π is thus equal to V cc -D-V ref3 . This means that the fixed part of the bias current through the MR element can be adjusted by means of the reference voltage V ref3 . Figure 12 shows an example of a voltage follower 310 for use in the arrangement of Figure 11. The input 400 of the follower 310 is connected to the base of a PNP transistor T 41 . The emitter of this transistor is coupled to the point 12 of constant potential via the series arrangement of a resistor 402 and a bias current source 404. The collector of transistor T 41 is connected to point 13 (ground) via a series arrangement of a diode connected PNP transistor T 42 and a resistor 406. The resistors 402 and 406 have equal resistances. The transistors T 41 and T 42 have equal emitter areas. So in steady state the voltage drop U j caused by current source 404 across the series arrangement of the base- emitter junction of transistor T 41 and resistor 402 is equal to the voltage drop across the series arrangement of the diode connected transistor T 42 and resistor 406. The interconnection node of the current source 404 and the resistor 402 is connected to the base of a NPN transistor T 43 . The collector of this transistor is coupled to point 12 and the emitter is connected to the output 408 of the follower 310 via a resistor 410. The interconnection node of collector of transistor T 42 and the series connection of transistor T 42 and resistor 406 is connected to the base of a NPN transistor T 44 , the collector of which is connected to the output 408 and the emitter of which is connected to ground via a resistor 412. The resistors 410 and 412 have equal resistances and the transistors T 43 and T^ have equal dimensions. In steady state the voltage drop U j across the series arrangement of the base-emitter junction of transistor T^ and resistor 412 is equal to the voltage drop across the series arrangement of the base-emitter junction of transistor T 43 and resistor 410. After settling, when no current flows any more in the output 408, the voltage difference between the input 400 and the output 408 is zero. During settling high charge currents can be provided to the output 408 by transistor T 43 or high discharge currents by transistor T^ by selecting suitable low resistance values for the resistors 410 and 412. The voltage follower of Figure 12 therefore enables fast and accurate settling as it provides high recharge currents during settling and low offset between input and output after settling. The switch S j in the arrangement shown in Figure 11 can be implemented conventionally with a MOS transistor. The main inaccuracy which is still left then is caused by charge injection of the switch S j into the capacitor C j . After fast settling is finished, the switch S j is opened and some capacitive charge is extracted from capacitor C j . This charge is about equal to half the charge in the channel of the MOS transistor. This charge extraction would be normally compensated by switching a small additional capacitor which is connected between capacitor C j and point 12. However, this causes crosstalk from the supply voltage to the capacitor C j . Figure 13 shows a MOS switching arrangement S j which feeds half of the channel charge back to capacitor C j and compensates the charge extraction from capacitor C j . The switch S j is composed of first, ST 1 ; and second, ST 2 , NMOS switching transistors. The source of the first switching transistor ST j is connected to the drain of the second switching transistor ST 2 , and the drain of the first switching transistor ST j is connected to the source of the second switching transistor ST 2 . The switching transistors ST j and ST 2 are driven by first, DT j , and second, DT 2 , PMOS driver transistors. These PMOS transistors have sources connected to the point 12 and have gates connected to the control input 100 for receiving a control signal. The drain of the first driver transistor DT j is connected to the gate of the first switching transistor ST j , and the drain of the second driver transistor DT 2 is connected to the gate of the second switching transistor ST 2 . Further, third DT 3 and fourth DT 4 NMOS driver transistors are provided. These NMOS driver transistors have their gates connected to the control input 100, whereas the source of the third driver transistor DT 3 is connected to the drain of the first switching transistor ST j , the source of the fourth driver transistor DT 4 to the drain of the second switching transistor ST 2 , the drain of the third driver transistor DT 3 to the drain of the first driver transistor DT j , and the drain of the fourth driver transistor DT 4 to the drain of the second driver transistor DT 2 . If the control signal at control terminal 100 is low (ground), then the PMOS driver transistors DT and DT 2 are conductive and switch on the switching transistors STj and ST 2 and resistor R is short-circuited for fast settling. The settling is finished by applying a high voltage at the control terminal 100. In that case the PMOS driver transistors DT j and DT 2 are cut off and the NMOS driver transistors DT 3 and DT 4 are made conductive. The conductive driver transistor DT 3 provides a conduction path from the gate of the switching transistor ST j to the capacitor C j and allows half the channel charge of switching transistor ST j to flow into the capacitor C 1( thereby cancelling the half of the channel charge of switching transistor ST 2 which is extracted from the capacitor C j . The other half of the channel charge of switching transistor ST 2 is conducted by driver transistor DT 4 to the low-ohmic output of buffer 310, which also absorbs the other half of the channel charge of switching transistor ST j . It will be clear that the switching arrangement of Figure 12 can also be employed in the above mentioned embodiments. Figure 14 shows a balanced version of the arrangement of Figure 11. The two amplifiers 1 and 61, in particular the capacitors C j and the corresponding capacitor C 2 of the second amplifier 61, are interconnected in a similar fashion as shown in Figure 6. At high frequencies the capacitors C j and C 2 form a short circuit and shunt the two individual equivalent source noise resistors R n of the MOS transistors T j and T 2 . R n is about equal to R 0 , R 0 being the inverse of the transconductance of the transistors T and T 2 . The total effective noise resistance in the first amplifier 1 of the arrangement of Figure 12 is R ml +R n /2 instead of R jjjj +R jj of the first amplifier 1 of the arrangement of Figure 11. The balanced version thus provides a reduction of noise. One of the MR elements R ml or R m2 may be omitted when using single stripe MR read heads. In that case terminal 7 or 67 is coupled to ground 13. The input terminals of the current mirrors may be advantageously interconnected to cancel signal components. In order to enable switching of heads, two further switches are provided in each half of the balanced arrangement. One further switch S 2 for connecting the gate of transistor T j to ground and a second parallel-operated further switch S 3 for connecting the gate of transistor T 32 to ground. In the other amplifier 61 similar switches are provided which are operated simultaneously with switches S 2 and S 3 . Elements which have to be duplicated for each dual read head are enclosed by a dashed line. The remainder of the balanced arrangement is common to all dual read heads. A dual read head is disabled by closing the switches S 3 and S 4 in both parts of the balanced arrangement. Fast settling is obtained by closing the switches S j temporarily. In the embodiments shown in the Figures certain transistors, for example the transistors T 1; T 2 , T 3 , T 5 and T 10 are preferably unipolar MOS transistors; other transistors such as the transistors T 4 , T 24 , T 6 , T 7 , T 8 , T 9 , T π and T 31 , are preferably bipolar transistors. It is, however, possible to use bipolar transistors instead of unipolar transistors and vice versa, or to use only bipolar or only unipolar transistors. The first main flow terminal, the second main flow terminal and the control terminal of a transistor correspond to, respectively, the source terminal, the drain terminal and gate terminal of an unipolar transistor and to, respectively, the emitter terminal, the collector terminal and base terminal of a bipolar transistor.

Claims: Claims 1. Arrangement for reading out an information signal from a magnetic record carrier, comprising: a read head having a magneto-resistive element (R m ι) with a first terminal (3) connected to a first point (13) of constant potential, and with a second terminal (4), a bias-current means (2; T 30 ,T 31 ) for supplying a bias-current, an amplifier circuit (1) comprising an output terminal (8) for supplying the information signal (V out ), a first terminal (6) coupled to the bias-current means (2; T 30 ,T 31 ) and to the output terminal (8), a second terminal (7) coupled to the second terminal (4) of the magneto- resistive head (R^ j ) so as to form a series arrangement of the bias-current means (2; T 30 ,T 31 ), the amplifier circuit (1) and the magneto-resistive element (R mi ) between a second point (12) of constant potential and said first point (13) of constant potential, the amplifier circuit (1) further comprising a first transistor (T j ), a feedback circuit (F j ) having an input terminal (t 2 ) coupled to the output terminal (8) of the amplifier circuit (1) and having an output terminal (t j ), a load impedance (R n ) and a capacitor element (C j ), a first main flow terminal of the first transistor (T j ) being connected to the second terminal (7) of the amplifier circuit (1), a second main flow terminal of the first transistor (T j ) being coupled to the first terminal (6) of the amplifier circuit (1), a control terminal of the first transistor (T j ) being coupled to the output terminal (t j ) of the feedback circuit (F j ), the control terminal being further coupled to the first point (13) of constant potential via at least the capacitor element (C j ), the load impedance (R u ) being coupled to the output terminal (8) of the amplifier circuit (1), characterized in that the feedback means comprises: voltage buffer means having an input coupled to the input terminal (t 2 ) of the feedback circuit (F j ) and having an output; a first series resistor (R ) connected between the output of the voltage buffer means and the output terminal (t j ) of the feedback circuit (F j ); and a switch (S j ) connected in parallel with the first series resistor (R j ) and operable in response of a control signal. 2. Arrangement as claimed in claim 1 , characterized in that the voltage buffer means comprises a first current source (24) and a second current source (21), a diode connected second (T 3 ) transistor and a third transistor (T 4 ), a first main flow terminal of the second transistor (T 3 ) and a first main flow terminal of the third transistor (T 4 ) being interconnected and coupled to the first point (13) of constant potential via the first current source (24), a second main flow terminal of the second transistor (T 3 ) being coupled to the second point (12) of constant potential via the second current source (21) and forming the output of the voltage buffer means, a second main flow terminal of the third transistor being coupled to the second point (12) of constant potential, and a control terminal of the third transistor (T 4 ) forming the input of the voltage buffer means and being coupled to the input terminal (t 2 ) of the feedback circuit (Fj). 3. Arrangement as claimed in claim 2, characterized in that the voltage buffer means further comprises a third current source (22) connected between the second main flow terminal of the third transistor (T 4 ) and the second point (12) of constant potential and in that the first current source (2) comprises a diode arrangement (25), a bias resistor (R 24 ) and a fourth transistor (T 24 ) having a first main flow terminal connected to the first point (13), a second main flow terminal connected to first main flow terminals of the second (T 3 ) and third (T 4 ) transistors and a control terminal coupled to the second main flow terminal of the third transistor (T 4 ) via the diode arrangement (25) and to the first point (13) via the bias resistor (R 24 ). 4. Arrangement as claimed in claim 3, characterized in that the voltage buffer means further comprises a fifth (T 5 ) and a diode element (40), a control terminal and a second main flow terminal of the fifth transistor (T 5 ) being interconnected and being coupled to the third current source (21) via the diode element (40), a first main flow terminal of the fifth transistor (T 5 ) being connected to the first main flow terminal of the second transistor (T 3 ), and a sixth transistor (T 6 ) having a first main flow terminal coupled to the second main flow terminal of the second transistor (T 3 ), a second main flow terminal coupled to the second point (12) and a control terminal coupled to the second main flow terminal of the fifth transistor (T 5 ) via the diode element (40). 5. Arrangement as claimed in claim 1, 2, 3 or 4, characterized in that the amplifier circuit comprises a seventh transistor (T 7 ) having a first main flow terminal connected to the second main flow terminal of the first transistor (T j ) and a second main flow terminal coupled to the first terminal (6) of the amplifier circuit (1). 6. Arrangement as claimed in claim 1 , 2, 3, 4 or 5, characterized in that the amplifier circuit (1) comprises an eighth transistor (T 8 ) having a control terminal coupled to the second terminal (7) of the amplifier circuit (1), a first main flow terminal coupled to the second point (12) of constant potential via a bias current source (36), and a second main flow terminal coupled to the first point (13) of constant potential, the load impedance (R u ) being coupled between the output terminal (8) of the amplifier circuit (1) and the first main flow terminal of the eighth transistor (T 8 ). 7. Arrangement as claimed in claim 6, characterized in that the amplifier circuit (1) further comprises a ninth transistor (T 9 ) having a first main flow terminal coupled to a control terminal of the seventh transistor (T 7 ) and a control terminal coupled to the first main flow terminal of the eighth transistor (T 8 ). 8. Arrangement as claimed in claim 7, characterized in that the amplifier circuit (1) further comprises a tenth transistor (T 10 ) having a control terminal coupled to the control terminal of the first transistor (T j ) and having a first main flow terminal coupled to the control terminal of the eighth transistor (T 8 ). 9. Arrangement as claimed in claim 6, 7 or 8, characterized in that the second main flow terminal of the eighth transistor (T 8 ) is coupled to the first point (13) of constant potential via a further load impedance (Ru') for providing the information signal. 10. Arrangement as claimed in claim 1, characterized in that the first terminal (6) is coupled to the output terminal (8) of the amplifier circuit (1) via a second transistor (T 31 ) having a first main flow terminal connected to the first terminal (6) and a second main flow terminal coupled to the output terminal (8) of the amplifier circuit (1); and in that the voltage buffer means comprises: a current mirror (300) having an input terminal (302) and an output terminal (304), a third transistor (T 30 ) having a conductivity opposite to the conductivity of the second transistor (T 31 ) and having a first main flow terminal coupled to the output terminal (304) of the current mirror (300) and a control terminal connected to receive a reference voltage, a second series resistor (R a ) connected between the first main flow terminal of the third transistor (T 30 ) and the output terminal (8) of the amplifier circuit (1), a diode connected fourth transistor (T 32 ) of the same type as the first transistor (T j ), and having a first main flow terminal connected to the first main flow terminal of the first transistor (T j ) and a second main flow terminal coupled to a second main flow terminal of the third transistor (T 30 ), a fifth transistor (T 33 ) of the same type as the first transistor (T j ) having a control terminal and a first main flow terminal connected to the corresponding terminals of the first transistor (T j ) and having a second main flow terminal coupled to the input terminal (302) of the current mirror (300); and a buffer amplifier (310) having an input connected to the control terminal of the fourth transistor (T 32 ) and an output connected to the first series resistor (R j ). 11. Arrangement as claimed in claim 10, characterized in that the bias current means comprises a bias current generator (2) having an output (5) connected to the first terminal (6) of the amplifier circuit (1). 12. Arrangement as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, characterized in that the switch (S j ) comprises: first (ST j ) and second (ST^ switching transistors of a first coductivity type, a first main flow terminal of the first switching transistor (ST j ) being connected to a second main flow terminal of the second switching transistor (ST 2 ), a second main flow terminal of the first switching transistor (ST j ) being connected to a first main flow terminal of the second switching transistor (ST 2 ); first (DT j ) and second (DT 2 ) driver transistors of a second conductivity type having first main flow terminals connected to a supply voltage terminal (12) and having control terminals connected to a control input (100) for receiving the control signal, a second main flow terminal of the first driver transistor (DT j ) being connected to the control terminal of the first switching transistor (ST j ), a second main flow terminal of the second driver transistor (DT 2 ) being connected to the control terminal of the second switching transistor (ST 2 ); third (DT 3 ) and fourth (DT 4 ) driver transistors of the first conductivity type having control terminals connected to the control input (100), a first main flow terminal of the third driver transistor (DT 3 ) being connected to the second main flow terminal of the first switching transistor (ST j ), a first main flow terminal of the fourth driver transistor (DT 4 ) being connected to the second main flow terminal of the second switching transistor (ST 2 ), a second main flow terminal of the third driver transistor (DT 3 ) being connected to the second main flow terminal of the first driver transistor (DT j ), a second main flow terminal of the fourth driver transistor (DT 4 ) being connected to the second main flow terminal of the second driver transistor (DT 2 ). 13. An arrangement as claimed in any of the preceding claims, further comprising a second arrangement, substantially identical to the first mentioned arrangement, the capacitor element (C j ) of the amplifier circuit (1) of the first arrangement being coupled to the second terminal (67) of the amplifier circuit (61) of the second arrangement and the capacitor element (C 2 ) of the amplifier circuit (61) of the second arrangement being coupled to the second terminal (7) of the amplifier circuit (1) of the first arrangement.

Inventors: VILA LOBOS RAMALHO JOAO NUNO, VOORMAN JOHANNES OTTO, VILA LOBOS RAMALHO, JOAO, NUNO, VOORMAN, JOHANNES, OTTO
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1994
Main classification: G01R33
IPC codes: G01R33, G11B5, G11B19, H03F3