Manufacturing method of an opto-electric semiconductor device

Abstract: To selectively grow a P type silicon layer and a Si/Ge x Si 1-x superlattice layer (7) under low temperature conditions in the area encircled with a groove (4), at least the side walls of which consist of silicon oxide film, which is formed in the silicon substrate. Thereby, the leak at the side of the superlattice layer can be reduced. Furthermore, by burying a metal film in the groove, the loss of light at the side of the superlattice layer (7) can be suppressed to the minimum. Thus a light receiver having silicon/germanium·silicon-mixed-crystal layer is stably formed in a silicon semiconductor substrate and optical absorption efficiency can be improved.

Description: The present invention relates to a manufacturing method of a semiconductor device having Si/GeSi superlattice structure selectively formed on a silicon substrate, which is useful as an optoelectric integrated circuit (OEIC) receiver. The first example of a prior art relative to a photodetector is, as shown in Fig.1, made by the following method. On a P + silicon substrate 18, a Si/Ge x Si 1-x superlattice layer 7 having superlattice structure of alternate layers of approximately 3 nm (30Å) of Ge 0.8 Si 0.4 and approximately 29 nm (290Å) of Si is formed by MBE (molecular beam epitaxy) method to the total thickness of 600 nm (6000Å). Next, on said Si/Ge x Si 1-x superlattice layer 7, a P type silicon layer 6 is formed by BE method and on the silicon layer 6, a N + type silicon layer 19 is formed. Then, as shown in the Fig.1, the N + type silicon layer 19 is made to mesa type by etching. A silicon oxide film 9 is deposited on the silicon layer 6 by CVD method and an opening 9a is made in the oxide film 9 by selectively removing a part of the silicon oxide film 9 above the silicon layer 19. Then, aluminum electrodes 11 are attached to the base and top faces of the substrate (IEEE ELECTRON DEVICE LETTERS VOL. EDL-7, NO. 5, 1986 pp 330-332). As a second example of a prior art, a manufacturing method of a superlattice element as shown in Japanese Provisional Publication (hereinafter referred as TOKKAI) HEI 3-53567 is explained in order of its process steps. As shown in Fig.2A, a 2 µm thick clad layer 21 made of Al x Ga 1-x As is formed on a GaAs substrate 20 by MBE method, and then, a superlattice layer 22 of 64 nm (640Å) thickness consisting of 4 cycles of a 8 nm (80Å) GaAs layer and a 8 nm (80Å) Al x Ga 1-x As is formed and an upper clad layer 23 of 1µm thickness made of Al x Ga 1-x As is formed. Next, as shown in Fig.2B, a ridge structure of 2µm width and 12µm height is formed by using photolithographic technic and RIE technic. Then, a silicon oxide layer 24 is formed on the surface of the ridge by plasma CVD method. Then, as shown in Fig.2C, while the surface where a silicon oxide layer 24 is formed and another GaAs wafer (not shown) are put together, heat treatment is performed under hydrogen atmosphere to have partially mixed crystallization take place in the superlattice layer 28 from the sides contacting silicon oxide layer 24 in transverse direction so as to have a superlattice structure retained in the central parts only of the ridge structure and a mixed crystal layer 25 on the both sides of the superlattice structure. In this example of a prior art, although the sides are protected by the ridge structure and with the silicon oxide layers 24, the side walls are made to a mixed crystal layer 25 so that any adverse effects due to damages on the treated surfaces can be avoided. Another example of a combination of an OEIC receiver having a Ge 1-x Si x mixed crystal layer and a device is described in TOKKAI SHO 63-122285. A sectional view of the MOS type image sensor is shown in Fig.3. A buffer layer 26 which comprises gradient ratio of Si to Ge 0.85 Si 0.15 mixed crystal in the direction of the thickness is formed on a Si substrate 1 by, for example, MBE method. Then, an N type Ge 0.85 Si 0.16 layer 27 is formed by MBE method, a P + drain region 29 and a P + source region 30 are formed on the surface of the substrate 1, a silicon oxide film 28, a drain electrode 31 and a gate electrode 32 are formed and then an OEIC receiver element and a MOS type image sensor are simultaneously formed on the Si substrate. There are, however, weak points in all said prior technologies, which will be explained below; The photodetector in the first example is composed of a so-called superlattice structure with a multiple layer structure of Si layers and Ge 1-x Si x layers in order to enhance optical receiving efficiency. Although this is to attempt to improve the efficiency covering the small optical absorption coefficient of silicon, there is a limitation in this attempt because it is difficult to make the thickness of the layers of the superlattice any more than 600 nm (6000Å) due to a problem of crystallization. Therefore, in order to improve the optical receiving efficiency, it is necessary to minimize the loss at the end face of the regions other than the thickness of the light absorption layer. In this first example, the side walls of the Si/Ge 1-x Si x superlattice is either as they were cut out or in a structure covered with a silicon oxide film in a mesa structure. Therefore, it is difficult to improve the absorption efficiency because of the loss of the incident light from the transverse direction at the side walls of the above mentioned structure. Although this structure enables the distance for absorption to be adjusted by the transverse distance of the Si/Ge 1-x Si x superlattice when the incident angle of the light is transverse to the substrate, it is difficult to have the light precisely incident upon the Si/Ge 1-x Si x end face by fixing an optical fiber which is the source of the incident light. There are other weak points with the prior arts 1 and 2; that is, if the end face of the superlattice is etched to form mesa structure, the end faces are apt to be damaged. Also there is a reliability problem due to energy level in the oxide film which covers the superlattice. In the prior art 2, a method to protect the etching side by mixed crystallization from the end face is adopted in order to solve the problem. While this method can be applied to a GaAs substrate, it can not be applied to a Si substrate, According to the prior art 3, an element to receive incident light from the top surface is formed, which is combined with other elements. However, in this method, it is necessary to make the area of the light receiving part large in order to improve optical receiving efficiency. Also, because the Si/Ge x Si 1-x superlattice layer is formed on the entire face, combination with other elements is difficult and adoption of Si device is impossible. Therefore, it is difficult to incorporate a large scale integrated circuit because the ratio of the area occupied by the light receiving region of the chip becomes large due to the large area of light receiving element. Furthermore, as discussed before, because a Si/GeSi layer is formed on the entire face of the substrate, simultaneous formation of a bipolar device is difficult in the case of the prior art 3. The object of the present invention is to provide a manufacturing method for a semiconductor device whereby stable formation of a photodetector and improvement of the optical absorption efficiency can be accomplished. This object is achieved by a method as defined in claim 1; the dependent claims are related to further developments of the invention. According to the presen invention, within a region on the Si substrate surrounded by grooves, at least side walls of which are made of silicon oxide film, a Si/Ge x Si 1-x superlattice layer is formed by applying UHVCVD method which enables selective growth under low temperature conditions. Thus, the leak current component in the Si/Ge x Si 1-x superlattice due to etching of side walls and damages of the side walls caused by mesa growth and interfacial energy level etc., which have so far been an unsolved problem, can be suppressed. With this method of the present invention, it has now become possible to reduce the leak level from the conventional level around 10 -6 A to less than 10 -7 A, taking a figure down more than one place. Further, according to the resent invention, a metal layer is formed so as to surround the Si/Ge x Si 1-x superlattice having the light projected from optical fiber protected from being lost from the side walls of the Si/Ge x Si 1-x superlattice and making it possible to obtain higher light intensity than before by more than 20% by confining the light by reflection, thus it is possible to convert optical signals to electric signals more efficiently. Also, according to the present invention, as for the placement of the optical fiber which is the incident source of the optical signals to the Si/Ge x Si 1-x superlattice, by placing the optical fiber in the groove made on the Si substrate in a way to make the height of the center of the optical fiber corresponded to that of the Si/Ge x Si 1-x superlattice, it is possible to easily improve the precision of the alignment of the optical fiber, which has so far been an unsolved problem for the incident light from a transverse direction. Also, as another method, by utilizing reflection and refraction at the side of the V-shaped grooves formed transversely on the Si/Ge x Si 1-x superlattice, the signals from optical fibers can be input from either the top surface or the base of the chip. Because of the above, although the conventional methods made it difficult to place the fiber from the side due to packaging reasons, it is now possible to place the fiber from either top or base face, and furthermore, although the conventional methods required to make the area of a photodetector large because the optical signals were entered directly to the Si/Ge x Si 1-x only from the top surface, the method of the present invention is effective to improve the freedom and efficiency of the layout because it makes it possible to introduce optical signals transversely to the Si/Ge x Si 1-x superlattice even if the optical signals are projected from the top. The method of the present invention also makes it possible to form a photodetector with Si/Ge x Si 1-x superlattice selectively in the silicon substrate and also makes it possible to form it on the same chip as for other Si devices because a UHVCVD method can be applied at low temperature. Although the conventional technology allowed to use limited devices such as CCD to form a photodetector in a common chip together with other elements, it did not allow superlattice structure to be used. However, the present invention makes it possible to forme it on the same chip as other Si devices, therefore, a photodetector can be formed on the same chip where other elements such as a vertical bipolar device have been formed prior to the formation of the photodetector. Thus, an element which required two chips with the conventional method can now be made with one chip. Furthermore, because of the possibility of the formation of an optical receiver at low temperature, it is now possible to make it in one unit within an OEIC with high performance bipolar devices. Therefore, the method of the present invention not only makes it possible to make one package instead of two packages required by conventional methods, but also makes it possible to form a compact and high performance OEIC by simultaneously solving problems of loss and reduced speed due to connection between the packages. Fig.1 is a cross sectional view showing a prior art 1 of the conventional method; Fig.2A - 2C are cross sectional views showing a prior art 2 of another conventional method in order of the manufacturing process steps; Fig.3 is a cross sectional view showing a prior art 3 of another conventional method; Fig.4 is a cross sectional view showing a first embodiment (embodiment 1) of the present invention; Fig.5 is another cross sectional view showing the embodiment 1 of the present invention viewed from a different angle; Fig.6 is a plane view showing the embodiment 1 of the present invention; Fig.7A - 7F are cross sectional views showing a second embodiment (embodiment 2) of the present invention in the order of the manufacturing process steps; Fig.8A - 8C are cross sectional views showing a third embodiment (embodiment 3) of the present invention in the order of the manufacturing process steps; Fig.9 is a diagram showing a fourth embodiment (embodiment 4) of the present invention illustrating the formation of the circuit. The present invention will be further described referring to the drawings as follows. Fig.4 is a cross sectional view of a semiconductor chip of the first embodiment (embodiment 1) of the present invention. To make the chip, first, a buried layer 2 is formed by doping N type impurity atoms such as arsenic atoms in P type silicon substrate 1 at a concentration of 10 19 cm -3 to 10 21 cm -3 . An epitaxial layer 3, of 0.8µm thickness for example, is formed on the substrate 1. Grooves 4 in which silicon oxide films are buried, are formed to a depth reaching the N + buried layer 2. The epitaxial layer 3 is removed within the area encircled by the grooves 4. In the area where the epitaxial layer 3 is removed, a P type silicon layer 6, which has been added with boron atoms at a concentration of 10 16 cm -3 to 10 20 cm -3 , is formed to 200 nm (2000Å) thickness by epitaxial growth method. On the P type silicon layer 6, a Si/Ge x Si 1-x superlattice layer 7 is selectively formed at a total thickness of 100 nm (1000Å) to 600 nm (6000Å) by alternately growing, for Example, 10 nm (100Å) to 20 nm (200Å) of silicon layers and 5 nm (50Å) to 10 nm (100Å) of Ge x Si 1-x layers by UHVCVD (Ultra High Vacuum CVD) method. On top of the Si/Ge x Si 1-x superlattice layer 7, a P + silicon layer 8, which has been added with boron atoms, is selectively grown. Openings 9a are formed on the silicon oxide film 9 which is formed on the surface of the silicon substrate 1 and aluminum electrodes 11 are formed. N + buried layers 4 are connected to aluminum electrodes via an N + diffused layer 12 which has been formed in the epitaxial layer 3. Preferably, the profile of the boron atom in the P type diffusion layer 6 is made at lower concentration at the bottom side where it contacts the N + buried layer and at higher concentration such as 10 19 cm -3 to 10 20 cm -3 where it contacts the Si/Ge x Si 1-x superlattice layer so that the electric field of the Si/Ge x Si 1-x superlattice layer 7 is lowered and leak current is reduced. Fig.5 is a cross sectional view of the optical receiver of the embodiment 1 of the present invention which is viewed from different angle. If the diameter of an optical fiber, which is the light incident source of optical signals, is 20µm, for example, this light receiver is selectively etched down to the depth of 10µm at its terminal side where the light is entered through the P + type silicon layer 8, the Si/Ge x Si 1-x superlattice layer 7, the P type silicon layer 6, the N + buried layer 2 and the silicon substrate 1. The optical fiber 14 is adhered to the etched region using an adhesive such as polyimide,and the center of the optical fiber is positioned to the center of the Si/Ge x Si 1-x layer, which acts as the light absorption layer. By so doing, the optical signals from the optical fiber 14 can be entered into the Si/Ge x Si 1-x superlattice layer most efficiently and stably. Although in this embodiment of the present invention, only a structure whose terminal side of the Si/Ge x Si 1-x at the side toward the projected light is exposed is shown, the structure whose end face is covered with an insulation film such as oxide film after etching the groove for connection of the optical fiber is preferred from the reliability stand point. Also, in this embodiment, only a case where the Si/Ge x Si 1-x superlattice layer 7 is etched is shown, but a method to form a groove for connection of the optical fiber by leaving the groove encircling the Si/Ge x Si 1-x superlattice layer 7 and by etching the epitaxial layer 3, the N + buried layer 2 and the silicon substrate 1 which are outside the groove can be applied to make the formation most reliable. The oxide film in the groove is not considered as a loss because the wave length of the optical fiber is within the infrared area. If the terminal end of the optical fiber is processed so as to better condense the incident light to the Si/Ge x Si 1-x superlattice layer 7, the efficiency can be further improved. Fig.6 is a top view of the embodiment 1 of the present invention. The cross sectional view along the line A - A' corresponds to Fig.4 and the cross sectional view along the line B - B' to Fig.5. The Si/Ge x Si 1-x superlattice layer 7 is placed at the center of the second groove for connection of the optical fiber 14 so that the structure of the optical receiver including the optical fiber can be made most efficiently and precisely. Next, a second embodiment (embodiment 2) of the present invention will be described as follows; Fig.7A - 7F are cross sectional views of the example 2 of the present invention in order of the manufacturing process steps. First, as shown in Fig. 7A, arsenic atoms are added to a P type silicon substrate 1 by, for example, an ion implantation method, then a N + buried layer 2 is formed at a concentration of approximately 10 19 cm -3 to the depth of 2µm, and finally an epitaxial layer 3 is formed at a thickness of 0.5µm to 1.5µm by an epitaxial growth method. Next, as shown in Fig.7B, grooves 4 reaching the N + buried layer 2 are opened by an anisotropic etching method, a silicon oxide film or BPSG (boron phosphorus silicated glass) film is deposited by CVD method and embedding the grooves with the silicon oxide film or BPSG film by etching it back, and a 500 nm (5000Å) thick silicon oxide film 5 is deposited by CVD method. Next, as shown in Fig.7C, the silicon oxide film is selectively removed and the epitaxial layer is selectively removed by using silicon oxide film as a mask for etching. Next, as shown in Fig.7D, a P type silicon layer 6 is formed by having silicon selectively grown to 200 nm (2000Å) to 600 nm (6000Å) thickness with boron concentration of 10 16 cm -3 and further grown to 100 nm (1000Å) thickness with 10 19 cm -3 of boron concentration. Next, a Si/Ge x Si 1-x superlattice layer 7 is formed to 100 nm (1000Å) to 600 nm (6000Å) thickness by alternately growing 10 nm (100Å) to 20 nm (200Å) thickness Si and 5 nm (50Å) to 10 nm (100Å) thickness Ge x Si 1-x layers. Then a P + type silicon layer 8 having 10 19 cm -3 to 10 20 cm -3 boron is grown. Next, after removing silicon oxide film 5, as shown in Fig.7E, silicon oxide film 9 is formed at approximately 200 nm (2000Å) thickness by a CVD method and grooves deeper than Si/Ge x Si 1-x layer 7 are opened in the silicon oxide film 9 and the grooves 4 by a photographic etching method. Further, an opening is made in the silicon oxide film on top of the P + type silicon layer 8. Next, as shown in Fig.7F, metal layers 10 made of a refractory metal such as tungsten is deposited by a sputter method or a CVD method so as to fill up the grooves, aluminum is deposited by a sputter method to a thickness of 0.5µm and an aluminum electrode 11 is formed by a photographic etching method. Then the metal layers 10 are etched at the same time as aluminum electrode 11 so as to remain only in the grooves. With this method, because a metal layer 10 which acts as a light reflecting layer in the grooves 4 encircling the light receiving layer which is Si/Ge x Si 1-x superlattice layer, the optical signals entered through the incident inlet are reflected by the metal layer 10 resulting in minimizing its loss from the side walls, thus enabling the efficiency to be further improved. Although the metal layer 10 may be placed on the three side faces of the Si/Ge x Si 1-x superlattice layer 7, except the face toward the projection inlet, the effect is achieved even if it is placed at only one side face, either incident inlet or its opposite side. Next, a third embodiment (embodiment 3) of the present invention will be described as follows; Fig.8A to 8C are cross sectional views of the example 3 in order of the manufacturing process steps. Up to the process step illustrated in Fig.7D, the same steps are applied. As shown in Fig.8A, an opening 5b is formed in a silicon oxide film 5a after removing the silicon oxide film 5, then a 200 nm (2000Å) thick silicon oxide film 5a is formed by a CVD method. Next, the epitaxial growth layer which is exposed in the opening 5b is etched by using alkaline solution such as KOH. With this method, a V-shaped groove as shown in Fig.8A is obtained because the etching stops at the (111) face. Next, as shown in Fig.8B, the silicon oxide film 9 is removed and a silicon oxide film 9 is newly formed by CVD method to a thickness of 200 nm (2000Å). Then an opening is made in the silicon oxide film 9 so that it goes through to the P + type silicon layer 8. Next, as shown in Fig.8C, a metal layer 10 is formed, aluminum is formed by a sputter method and an aluminum electrode 11 is formed by a photolithographic etching method. When the aluminum is etched, the metal 10 is formed at the lower layer and the metal layer 10 is selectively etched by a photolithographic etching method. With this method, because the optical signals from the optical fiber can be entered from the top surface of the chip, the fiber can be placed easily. In this embodiment, only the method where the incident light is entered from the top surface of the chip is described. However, it is also possible to have the incident light from the bottom surface of the chip by placing the metal layer 10 on the side of the V-shaped groove closer to the Si/Ge x Si 1-x superlattice layer. Next, a fourth embodiment (embodiment 4) of the present invention will be described as follows. Fig.9 shows the embodiment 4 of the present invention which is applied to an OEIC 17. As shown in the Fig.9, the structure includes the Si/Ge x Si 1-x superlattice layer formed in silicon as a photodetector 16 which is described in a part of a chip of an OEIC working as an analog to digital converter. In this embodiment, first, as shown in Fig.7A, after forming a N + buried layer 2 and an epitaxial growth layer 3 on the silicon substrate 1, a bipolar transistor is formed by a known method up to the stage before a contact for an electrode is formed. Then, by performing process steps after those described in Fig.7B, a photodetector 16 is formed and by forming electrodes at the photo-detector 16 and the bipolar transistor, an optical receiver circuit can be formed. Thus, according to the present invention, because the Si/Ge x Si 1-x superlattice layer is formed in the Si substrate under growth conditions of less than 700°C, a potential change in the profile of the bipolar area can be minimized and this makes it possible to form a chip which contains a high performance bipolar element. Although the embodiments of the present invention mentioned here are related to the ones where a P/N junction is formed on the lower surface of the Si/Ge x Si 1-x superlattice layer, it can be on the top face.

Claims: A manufacturing method of a semiconductor device characterized by comprising the steps of; forming a first conductivity type silicon substrate (1), a second conductivity type buried layer (2) and a second conductivity type silicon layer (3); forming a first groove (4) in said second conductivity type silicon layer (3) extending into said buried layer (2), at least side walls of said first groove being covered with silicon oxide; removing said second conductivity type silicon layer (3) which is surrounded by said groove down to a predetermined depth; selectively forming a first silicon layer (6) of first conductivity type on said second conductivity type silicon layer (3) which remains or said second conductivity type buried layer (2) which is exposed; forming a silicon/germanium·silicon-mixed-crystal layer (7) through alternate growth of more than one or two times of a silicon layer and a germanium silicon mixed crystal layer on said first silicon layer (6) of first conductivity type, whereby a photodetector comprising a Si/Ge x Si 1-x superlattice structure is manufactured; and forming a second silicon layer (8) of first conductivity type on said silicon/germanium·silicon-mixed-crystal layer (7). The manufacturing method of a semiconductor device according to claim 1, characterized by further comprising the steps of: forming an opening in said first groove (4), the opening being deeper than said silicon/germanium·silicion-mixed-crystal layer (7) and positioned at least at one side of said silicon/germanium·silicon-mixed-crystal layer (7); and burying a metal layer (10) in said opening. The manufacturing method of a semiconductor device according to claim 1 or 2, characterized by further comprising the steps of forming a second groove in the silicon substrate located transversely adjacent to said silicon/germanium. silicon-mixed-crystal layer (7), the depth of said second groove measured from said silicon/germanium·silicon-mixed-crystal layer (7) being 1/2 of the diameter of an optical fiber to be coupled therewith; and fixing said optical fiber (14) in said groove. The manufacturing method of a semiconductor device according to claim 3, characterized by further comprising the steps of: fixing said optical fiber in a way that its center line enters said silicon/germanium·silicon-mixed-crystal layer. The manufacturing method of a semicondutor device according to claim 1 or 2, characterized by further comprising the steps of: forming a V-shaped groove in the silicon substrate located transversely adjacent to said silicon/germanium. silicon-mixed-crystal layer; and fixing an optical fiber in a way that the light enters said V shape groove. Method of manufacturing an optoelectronic integrated circuit including an analog-digital signal converter comprising a bipolar type transistor and a photodetector, the photodetector (16) comprising a silicon/germanium·silicon-mixed-crystal superlattice, characterized in that the photodetector (16) is manufactured according to the method of claim 1. The manufacturing method of a semiconductor device according to one of claims 1 to 6, characterized in that said silicon/germanium·silicon-mixed-crystal layer (7) is selectively grown at a temperature below 800°C.

Inventors: TAKEMURA HISASHI, TASHIRO TSUTOMU, TAKEMURA HISASHI C/O NEC CORPORATION, TASHIRO TSUTOMU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H01L31
IPC codes: H01L31, H01L27