Process for making an electrostatic discharge protect diode for silicon-on-insulator technology

Abstract: A method of providing electrostatic discharge protection for SOI technology is described. A diode (24, 18) is formed in a trench region that extends to the SOI substrate (18). During normal processing a dopant opposite the substrate type is implanted into the trench. The trench must have gradually sloping sidewalls to prevent sidewall masking and provide good step coverage.

Description: BACKGROUND OF THE INVENTION This invention relates to a method of fabricating electrostatic discharge protection for semiconductor devices, formed on silicon-on-insulator substrates. This size of semiconductor devices has shrunk and circuit layouts have become more complex. As a result, semiconductor devices in circuits are more susceptible to burn-out by electrostatic discharge (ESD) events. Various approaches for minimizing ESD burn-out have been presented. The known approaches are based on reverse-biased diodes formed in the substrate of the semiconductor material. In silicon-on-insulator (SOI) wafers, however, the devices are electrically insulated from the substrate by a layer of silicon dioxide. In thin film SOI wafers, the silicon film is too thin to form large area vertical diodes. What is needed, is a method for forming a structure to allow electrostatic discharge protection for SOI transistors. It is mentioned that EP-A-0490437 discloses a reverse voltage diode for maximum depletion region under high voltage devices. Therein, said diode is manufactured in a late stage of IC processing but before MOSFET gate oxide growth. The formation of the diode involves a special ion implantation step additional to the implantation of the silicon-on-insulator layer. JP-A-62005662 discloses (in its English abstract) a drain of a SOI-MOSFET having Ohmic contact to a N+/P- diode in the substrate. Said buried diode is formed with its own special diffusion step and before gate oxide growth. US-A-4889829 shows a process for formation of bulk elements and SOI elements on the same chip to avoid a double LOCOS technology. FR-A-2145460 shows a gate of a conventional MOSFET connected to a lateral Zener diode, both on a sapphire substrate. In a special case, the Zener diode is placed on an oxide layer common with the MOSFET gate, on a silicon substrate. SUMMARY OF THE INVENTION The present invention intends to provide a simple and effective method to produce an ESD protect diode for MOSFET devices. This is achieved by means of a method according to Claim 1. In accordance with the present invention, a new photolithography level is inserted following transistor gate oxide growth. At this new photolithographic level, the area in which a diode is to be fabricated is defined. A dry etch tool is then used to etch a trench through the gate oxide, the silicon film and the buried oxide of the SOI wafer stopping at the silicon substrate. During a source/drain doping procedure, the exposed substrate surface is doped opposite the wafer dopant type. Standard processing then continues. It is desired that the slope of the trench wall be controlled so that it is not excessively vertical. A vertical trench wall would facilitate the formation of polysilicon or nitride or oxide spacers as part of a side wall masking. The spacers would block a dopant implant causing the electrostatic discharge diode to leaky. A second requirement is that the trench should be much wider than the sum of its depth plus the thickness of the passivation oxide. This avoids step coverage with the passivation oxide and the subsequent first metal layer. The process steps are: gate oxide growth; defining the ESD diode area with photoresist; etching the gate oxide in exposed areas; etching the silicon film in exposed area; etching the buried oxide in exposed areas; stripping the resist; and continuing normal device processing. For a p-type substrate, during N+ source/drain photo definition the ESD diode trench should be opened to allow the N+ source/drain implant. During any P+ implant the trench should be covered with resist. Other than these steps, normal semiconductor processing is used. In an alternative embodiment, the electrostatic protect method may be employed during mesa/trench isolation of the SOI structures not forming part of the claimed invention. In this embodiment, the process steps are as follows: gate oxide growth; defining ESD diode area with photoresist; etching through the buried oxide; stripping the resist and continuing processing the same as in LOCOS device fabrication. BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will be more fully understood with reference to the description of the best mode and the drawings wherein; Figure 1 is cross-sectional area of a SOI wafer having gate oxide grown. Figure 2 is a cross-section of an isolation etched SOI wafer. Figure 3 is a cross-section of the wafer during source/drain implant. Figure 4 is a cross-section area of an alternative embodiment of the present invention using mesa/trench isolation. Figure 5 shows a result after etching in an alternative embodiment. Figure 6 shows a completed electrostatic discharge protection diode on a SOI wafer. DESCRIPTION OF THE BEST MODE FOR CARRYING OUT THE INVENTION The present invention employs an additional photolithographic level in standard semiconductor device processing. This level is inserted after gate oxide growth. As can be seen in Figure 1, this photolithographic level defines an area 10 in which a diode is to be fabricated. A dry etch tool is then used to etch a trench through the grown gate oxide 12, silicon film 14 and the silicon dioxide layer 16 down to the silicon substrate 18. After photoresist 20 removal, the SOI device wafer looks as shown in Figure 2. During a source/drain doping procedure, the EDS diode trench is opened up and doped with N+ implantation as shown in Figure 3. The trench is covered during any P+ doping processes to prevent implantation into the diode area. When using an N-type silicon substrate, the trench can be opened up during any P+ source/drain implantation process. When using a mesa or trench isolation technique on SOI wafers, the process steps are nearly the same. As shown in Figure 4, the photoresist 20 can be used after the growth of gate oxide to define the EDS diode area 10. Next, the buried oxide is etched to the silicon substrate, the photoresist is striped to form the device structure as shown in Figure 5. From then on, the device processing is the same as for the LOCOS device processing technique. Shown in Figure 6, is a cross-section of an ESD protect diode for SOI. Shown is a substrate 18 having a buried oxide 16 and a silicon film 14, in which semiconductor transistor devices are formed. A low temperature glass 22 is conformably deposited into the trench region on which the diode is formed. The diode is formed from the N+ doped region 24 with the salicide contact 26 on which the first metal layer 28 is deposited. In addition to being used for ESD protection, the diode can be forward biased and used to check if a test probe is making proper contact with a pad this not forming part of the claimed invention. Each input and output path would have its own ESD protection associated therewith.

Claims: A method of fabricating an electrostatic discharge (ESD) diode (24, 18) in a silicon-on-insulator (SOI) material (18, 16, 14) having at least a silicon layer (14) for MOSFET device fabrication, an insulating layer (16) thereunder and a semiconducting substrate (18) under the insulating layer (16), the substrate (18) having a dopant type, comprising in the following order the steps of: growing a MOSFET gate oxide (12) on the silicon layer; defining a trench region (10) on the surface (12) of the SOI substrate (18, 16, 14) before normal semiconductor device processing; etching the gate oxide (12) and the SOI layers (16, 14) down to the semiconducting substrate (18) to form the trench; removing any trench defining material and continuing with normal device processing; opening up the trench (10) and ion implantating a dopant species of the opposite type as the semiconducting substrate (18) during processing of the MOSFET devices; depositing metal (28) in portions of the trench region (10) during normal device processing to form a diode (24, 18), the diode metallization (28) being connected to devices formed in the said silicon layer (14) of the SOI material (16, 14) thereby providing ESD protection to the devices. A method according to Claim 1 or 2, wherein before said metal (28) deposition step a low temperature glass (22) is conformably deposited into said trench (10) leaving open an area in said trench (10) for contacting said diode (24, 18).

Inventors: BRADY FREDERICK T, EDENFELD ARTHUR, HADDAD NADIM F, BRADY, FREDERICK T., EDENFELD, ARTHUR, HADDAD, NADIM F.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1994
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21