Line impedance synthesis circuit

Abstract: A line impedance synthesis circuit for a telecommunication line circuit is described which is coupled to line terminals (AW,BW) of a telecommunication line and fed from first (GND) and second (VBAT) terminals of a voltage supply source. The line terminals (AW,BW) are coupled to these supply terminals via respective first and second impedance means which include a main path (A-B) of a first transistor circuit (K1A/K1B) shunted by the series connection of a resistance circuit (TRA/TRB) and a main path (A-B) of a second transistor circuit (K2A/K2B), control electrodes (CT) of the first (K1A/K1B) and second (K2A/K2B) transistor circuits being coupled to a same control output of a control circuit (AMPA,SUMA/AMPB,SUMB).

Description: The present invention relates to a line impedance synthesis circuit for a telecommunication line circuit and which is coupled to line terminals of a telecommunication line and fed from first and second terminals of a voltage supply source. Such a line impedance synthesis circuit is used to provide an adequate termination impedance for the telecommunication line, i.e. a termination impedance which seen from this telecommunication line has a value prescribed by a national Telecommunications administration and which may thus differ from country to country. A generic line impedance synthesis circuit should therefore allow for an easy modification of the value of the termination impedance. A line impedance synthesis circuit as described above is already known in the art, e.g. from the published European patent application with publication number EP 0046588 A1. Therein, the telecommunication line is equivalent to a line or loop impedance ZL and the line or loop current IL flowing through it is provided by an output of a feedback loop a feedback path of which includes an amplifier sensing the line current and applying a voltage proportional to the line current to one input of a summing point of the feedback loop. The latter voltage also constitutes an output voltage which may be processed in further parts of the telecommunication line circuit. A voltage vi is furthermore applied to another input of the summing point whose output then provides a voltage which is differentially amplified, the resulting differential voltage being applied across the line impedance ZL via two identical resistors, thus providing the line current IL. In this way, the voltage vi determines both the line current IL and the impedance Ze = Vdiff IL -ZL 1+2×A seen from the telecommunication line, wherein Vdiff is the differential voltage and A is the loop gain. Thus, the value of Ze depends upon the voltage vi via parameters which are not accurately known, Ze thereby being difficult to control. An object of the present invention is to provide a line impedance synthesis circuit of the above known type, but which allows to easily and efficiently choose the value of the impedance. According to the invention, this object is achieved due to the fact that said line terminals are coupled to said first and second supply terminals via respective first and second impedance means at least one of which includes a main path of a first transistor circuit shunted by the series connection of a resistance circuit and a main path of a second transistor circuit, control electrodes of said first and second transistor circuits being coupled to a same control output of a control circuit. In this way, the value of the impedance seen from the telecommunication line is equal to the sum of the impedance values of the respective first and second impedance means. The impedance value of the at least one impedance means is equal to R / 1+RAT, wherein R is the resistance value of the resistance circuit and RAT is the ratio of currents flowing through the main paths of the first and second transistor circuits. Since the control electrodes of both the first and second transistor circuits are controlled from the same control output to which a same bias voltage is applied, this ratio RAT only depends on design parameters of these first and second transistor circuits, whereas the absolute value of the currents through the respective main paths is also determined by the value of this same voltage. Thus, by adequately designing the first and second transistor circuits, the value of the impedance seen from the telecommunication line may be easily and efficiently chosen. Another characteristic feature of the present invention is that said first and second impedance means are alike and controlled by respective first and second said control circuits. Thus, the impedance value of both the first and the second impedance means may be chosen in the same way, and when chosen equal perfect symmetry is obtained. A further characteristic feature of the present invention is that each of said impedance means includes a third transistor circuit whose control electrode is coupled via a resistance to said control output of the corresponding one of said first and second control circuits and whose main path is coupled in parallel with said main path of said first or second transistor circuit, said control electrodes of said third transistor circuits of both said first and second impedance means being intercoupled via a capacitance. In this way, the AC value of the impedance may be chosen different from its DC value. Indeed, for this AC value the above formula holds since, the control electrodes of both third transistor circuits then being biased at a same voltage because of the capacitor, this third transistor circuit is not active for AC line currents. On the other hand, the DC value of the impedance is now equal to R / 1 + RAT1 + RAT2 when the third transistor circuit is coupled in parallel with the first transistor circuit, i.e. the DC value is then lower than the AC value, and to R × (1 + RAT2) / 1 + RAT1 + RAT2 when it is coupled in parallel with the second transistor circuit, i.e. the DC value is then higher than the AC value. Herein, RAT1 is the ratio of the currents flowing through the main paths of the first and second transistor circuits, and RAT2 is the ratio of the currents flowing through the main paths of the third and second transistor circuits. Still a further characteristic feature of the present invention is that said impedance means includes a switch adapted to connect said main path of said third transistor circuit in parallel either with said main path of said first transistor circuit or with said main path of said second transistor circuit under the control of a switch control signal supplied at a switch control terminal of a switch control circuit. In this way, the value of the switch control signal determines whether the impedance has a DC value which is higher or lower than its AC value. Yet a further characteristic feature of the present invention is that it further includes between said first and second supply terminals the series connection of a fourth transistor circuit, a load impedance and a fifth transistor circuit, control electrodes of said fourth and fifth transistor circuits being coupled to said control outputs of said first and second control circuits. In this way, a current proportional to the current flowing through the main path of the second transistor circuit and therefore proportional to the line current flowing through the telecommunication line, flows through the load impedance, whereby a voltage is generated across this impedance which is proportional to this line current and from which a signal superposed thereon may hence be derived. An even further characteristic feature of the present invention is that said load impedance includes a double-ended operational amplifier whose positive and negative outputs are coupled via respective feedback resistances to its negative and positive inputs, respectively, which in their turn are coupled via respective load resistances to said fifth and fourth transistor circuits, respectively. Thereby, the value of the load impedance is equal to the sum of the values of the respective load resistances, and the voltage provided across the outputs of the double-ended operational amplifier is proportional to the current flowing through the fourth and fifth transistor circuits. Indeed, in a first approximation the input voltage of the double-ended operational amplifier may be neglected so that the voltage across the load impedance is divided across the respective load resistances whereby the value of the load impedance is equal to the sum thereof. On the other hand, the input current of the double-ended operational amplifier being negligible in a first approximation, the current flowing through the fourth and fifth transistor circuits also flows through the respective feedback resistors, whereby the voltage across the outputs of the double-ended operational amplifier is equal to the product of this current and the sum of the respective feedback resistors. A yet other characteristic feature of the present invention is that each of said first, second, third and fourth transistor circuits includes a field effect transistor whose gate electrode constitutes said control electrode coupled to said control output of said control circuit. Thereby, the value of the current flowing through the transistor circuit is determined by the value of the voltage at the gate of the field effect transistor as provided by the control circuit. Furthermore, no current needs be supplied by this control circuit to the transistor circuit as the field effect transistor does not require an input current. In a further embodiment of the present invention, said transistor circuit further includes second and third field effect transistors and a current source, the series connection of source-to-drain paths of said first mentioned and second field effect transistors constituting said main path of said transistor circuit, the series connection of a source-to-drain path of said third field effect transistor and said current source being connected between said first/second and second/first supply terminals of said voltage supply source, a gate electrode of said second field effect transistor being coupled to the junction point of said drain-to-source path of said third field effect transistor and said current source, and a gate electrode of said third field effect transistor being coupled to the junction point of said drain-to-source paths of said first and second field effect transistors. Thus, when the voltage at the control electrode of the transistor circuit changes in the direction of the voltage at the first/second supply terminal, henceforth referred to as first direction, the first field effect transistor becomes less conductive and the voltage at the gate of the third field effect transistor changes in a second direction opposite to the first one. Thereby, the voltage at the gate of the second field effect transistor changes in the first direction so that this second field effect transistor becomes less conductive and the voltage at the gate of the third field effect transistor slightly rises again. Thus, a negative feedback loop is providing resulting in a stable operation. A still further feature of the present invention is that said transistor circuit further includes a fourth field effect transistor whose source-to-drain path is coupled in parallel to said source-to-drain path of said third field effect transistor and whose gate electrode is coupled to said gate electrode of said first field effect transistor. Thus, when the voltage supplied by the control circuit at the control electrode of the transistor circuit is such that a current flows through its main path, i.e. that the first and second field effect transistors are conductive, then the fourth field effect transistor is also conductive whereby part of the current provided by the current source flows through this fourth field effect transistor instead of through the third one. The more conductive the first and second field effect transistors become, the more conductive the fourth field effect transistor becomes, so that finally nearly all the current provided by the current source flows therethrough. As a consequence, the voltage at the gate of the second field effect transistor is pulled to the voltage at the first/second supply terminal whereby it becomes less conductive. Thus, the current through the transistor circuit is limited. In an even further embodiment of the present invention, said transistor circuit further includes a fifth field effect transistor whose source-to-drain path is coupled between said first/second supply terminal of said voltage supply source and said source-to-drain path of said first field effect transistor, and whose gate electrode constitutes a second control electrode of said transistor circuit. Thus, the voltage supplied to the second control electrode determines the conductivity of the drain-to-source path of the fifth field effect transistor, thereby slightly influencing the current through the main path of the transistor circuit. In another embodiment of the present invention, the current provided by said current source is controlled by a control signal provided by a current control circuit. By so controlling the current provided by the current source, the voltage at the gate of the second field effect transistor and thereby the conductivity of its drain-to-source path, is controlled. A further feature of the present invention is that said impedance means further includes further transistor circuits coupled in parallel to either of said first, second or third transistor circuits and the current of whose current source may be cut off by said control signal. Thus, the above ratio of the currents flowing through the impedance means, and thereby the impedance seen from the telecommunication line, may be modified by controlling the currents provided by the current sources of the transistor circuits. Indeed, when this current is cut off then the voltage at the gate of the second field effect transistor is pulled in the first direction by the third field effect transistor so that this second field effect transistor is no longer conductive and the transistor circuit is cut off. In another embodiment of the present invention, said first and second line terminals are further coupled to said second and first supply terminals via like said impedance means. Thus, the first and second line terminals may, via the impedance means, be connected to either the first and second supply terminals, respectively, or to the second and first supply terminals, respectively, so that a reversely biased operation on the telecommunication line is also possible. Either the connection to the first and second, or the one to the second and first supply terminals must then be disabled by cutting off the current provided by the respective current sources. Still another characteristic of the present invention is that said first transistor circuit is coupled to a corresponding one of said first and second line terminals via a source-to-drain path of a sixth field effect transistor whose gate electrode is coupled to said first/second supply terminal via a bias voltage source. In this way, the impedance means may be so designed that the current flowing through the telecommunication line, flows largely via series connection of the sixth field effect transistor and the first transistor circuit. Thus, when this series connection is so designed that the voltage across it falls largely across the sixth field effect transistor, then most of the power dissipated by the impedance means is dissipated in the sixth field effect transistor so that this is the only power component of the line impedance synthesis circuit. As a consequence, the impedance means may be fully integrated except for this sixth field effect transistor. Yet another characteristic feature of the present invention is that said control circuit includes a comparator circuit a first input of which is coupled to the junction point of said resistance circuit and said main path of said second transistor circuit to a second input of which a correction voltage is applied, and an output of which constitutes said control output of said control circuit. Thus, the voltage supplied at the control output of the control circuit is such that the voltage at the junction point of the resistance circuit and the second transistor circuit is equal to the correction voltage. Indeed, when the voltage at this junction point is higher than this correction voltage then the voltage at the control output is high whereby the second transistor circuit becomes less/more conductive - less for the impedance means coupled to the first supply terminal, and more for the impedance means coupled to the second supply terminal - and the voltage at the junction point drops. In this way a negative feedback loop and thereby a stable operation is obtained. A further feature of the present invention is that said comparator circuit includes an operational amplifier. Thus, a simple implementation of the comparator circuit is given. An even still further characteristic feature of the present invention is that said control circuit further includes a summing circuit to a first input of which a reactance voltage is applied proportional to the reactance component of said impedance associated to said telecommunication line circuit, to a second input of which a signal voltage proportional to an AC signal on said telecommunication line is applied, to a third input of which a bias voltage providing bias for said impedance means is applied, and an output of which provides said correction voltage. In this way, the voltage at the junction point between the resistance circuit and the second transistor circuit is equal to the sum of the reactance voltage, the signal voltage and the bias voltage. The reactance voltage being proportional to the reactance component of the impedance, the voltage across the resistance circuit has a part which is proportional to this reactance component whereby the impedance seen from the telecommunication line is proportional to this reactance component. The signal voltage being proportional to the AC signal on the telecommunication line, the voltage across the resistance circuit and thereby the value of the impedance seen from the telecommunication line is independent from this AC signal. The bias voltage provides a bias for the impedance means. A yet further feature of the present invention is that it further includes the cascaded connection of a high pass filter and a gain circuit inputs of said high pass filter being coupled across said outputs of said load impedance and outputs of said gain circuit providing said reactance voltage. Thus, the synthesis of the above reactance component is only performed for frequencies above a cut-off frequency of the high pass filter, and its value is determined by the gain of the gain circuit. Still another feature of the present invention is that said gain circuit includes, coupled across said load impedance via said high pass filter, the series connection of an amplifier section, and a gain resistance and a gain capacitance whose junction point provides said reactance voltage. Thereby, the reactance voltage is proportional to 1 / 1 + s × RG × CG, where s is the complex Laplace variable, RG is the value of the gain resistor and CG is the value of the gain capacitance. Thus, by appropriately choosing these values, the reactance component of the impedance may be chosen as wanted. An even other feature of the present invention is that said gain circuit further includes a gain amplifier, between an input and an output of which said gain capacitance is coupled. In this way, the value CG of the gain capacitance used in the above formula is substantially proportional to the gain provided by the gain amplifier. Indeed, a voltage VC provided at the junction point of the gain resistor and the gain capacitance is amplified by the gain amplifier with its gain AG so that a voltage (1+AG)×VC is provided across the gain capacitor which thus virtually has a value equal to (1+AG)×CG. To be noted that. this effect is comparable to the so-called Miller effect occurring in bipolar transistors. In yet another embodiment of the present invention, said resistance circuit is constituted by the main path of a seventh field effect transistor whose gate electrode is coupled to a resistance control output of a resistance control circuit. Thus, the voltage provided at the resistance control output of the resistance control circuit determines the resistance value of the resistance circuit, i.e. of the drain-to-source path of the seventh field effect transistor. In a still further embodiment of the present invention, said resistance control circuit includes the series connection of second and third resistances between first and second bias terminals, the series connection of a main path of an eighth field effect transistor and a fourth resistance between said first and a third bias terminal, and an operational amplifier whose inputs are coupled to the junction point of said main path of said eighth field effect transistor and said fourth resistance, and to the junction point of said second and third resistances, respectively, and whose output is coupled to a gate electrode of said eighth field effect transistor and constitutes said resistance control output, a bias voltage being applied across said first and second bias terminals, and said second and third bias terminals being biased at a same voltage. In this way, the seventh field effect transistor is controlled by a same voltage as the eighth field effect transistor so that the resistance values of their respective drain-to-source paths are proportional to each other. This resistance value of the eighth field effect transistor is equal to the ratio of the values of the second and third resistors multiplied by the value of the fourth resistor. Indeed, the second and third bias terminals being biased at the same voltage and the inputs of the operational amplifier being coupled to both mentioned junction points which are thereby kept at substantially the same voltage, the drain-to-source path of the eighth field effect transistor constitutes a branch of a resistive bridge which is comparable to a so-called Wheatstone bridge in balanced condition. An even further characteristic of the present invention is that said resistance control circuit further includes a fifth resistance between said second and a fourth bias terminal, a main path of a ninth field effect transistor between said third and fourth bias terminals, and a second operational amplifier whose inputs are coupled between said second and third bias terminals and whose output is coupled to a gate electrode of said ninth field effect transistor, a second bias voltage being applied across said first and fourth bias terminals. In this way, the resistance value of the main path of the eighth/ninth field effect transistor, and therefore of the corresponding seventh field effect transistor, is equal to the product of the ratio of the fourth and third resistors, with the second/fifth resistor. A still further feature of the present invention is that said supply voltage supplied by said voltage supply source across said first and second supply terminals is at least equal to the sum of said second bias voltage and twice a bias voltage value. Thus, the supply voltage provides the second bias voltage increased with the bias voltage value needed to provide biasing for the impedance means. Yet a further characteristic feature of the present invention is that said second and fifth resistances have a same value, that said third resistance is constituted by the series connection of two resistances with a same value and whose junction point is coupled to said second control electrode of said first transistor circuit and to a negative input of a summing circuit, first and second positive inputs of which are coupled to said first and second line terminals, respectively, and an output of which is coupled to said second control electrode of both said second transistor circuits. Thus, the voltage at the junction point of the two series connected resistors constitutes a reference voltage supplied to the second control electrodes of the first transistor circuit. When the voltage at the first and second line terminals is not centred around this reference voltage then the voltage provided to the second control electrodes of the second transistor circuits is such that the voltage at the first and second line terminals becomes again centred around the reference voltage. Indeed, the voltage supplied to the second control electrodes of the second transistor circuits is equal to the sum of the voltages at the first and second line terminals minus the reference voltage and in an ideal case is thus equal to this reference voltage so that the voltage supplied to the second control electrodes of the second transistor circuits is equal to that supplied to the second control electrodes of the first transistor circuits. However, when the voltage supplied to the second control electrodes of the second transistor circuits is higher than the reference voltage then the second transistor circuits are thus controlled that the symmetry of the voltages at the first and second line terminals around the reference voltage is at least partly reestablished. A final characteristic feature of the present invention is that said resistance control circuit is implemented as an integrated circuit except for said fourth resistance which, is a precision resistance external to said integrated circuit, and said sixth field effect transistor. Thus, the resistance value of the resistance circuit may be precisely chosen. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein : Fig 1 shows a line impedance synthesis circuit according to the invention for use in a telecommunication line circuit; Fig 2 represents a transistor circuit K as used in the line impedance synthesis circuit of Fig 1; and Fig 3 depicts the series connection of a load impedance ZCO and a reactance synthesis circuit SYN used in the line impedance synthesis circuit of Fig 1. The line impedance synthesis circuit shown in Fig 1 forms part of a telecommunication line circuit interfacing between a two-wire telecommunication line with line terminals AW and BW and a subscriber station (not shown) and provides a matched impedance for the line. It includes between positive first and negative second supply terminals GND and VBAT, respectively, of a voltage supply source, the series connection of a main path AB of a transistor circuit K4A, the load impedance ZCO and a main path BA of a transistor circuit K4B. The junction point between the load impedance ZCO and the transistor circuit K4A is connected to a control electrode CR1 of K4B as well as to a control electrode CR2 of K4A, whereas the junction point between the load impedance ZCO and the transistor circuit K4B is connected to a control electrode CR1 of K4A as well as to a control electrode CR2 of K4B. Outputs of the load impedance ZCO are furthermore connected to inputs of the reactance synthesis circuit SYN which in its turn has outputs providing reactance voltages ZCOP and ZCON as will be described later with reference to Fig 3. The respective junction points between ZCO and on the one hand K4A, on the other hand K4B, constitute respective outputs OUTA or ZCOA and OUTB or ZCOB of the line impedance synthesis circuit. The line impedance synthesis circuit furthermore includes between supply terminal GND and line terminal AW the series connection of a main path AB of a transistor circuit K1A and a source-to-drain path of a p-channel MOS field effect transistor TEXA whose gate is coupled to a negative pole of a DC bias voltage source VBA a positive pole of which is connected to GND, as well as the series connection of a main path AB of a transistor circuit K2A and a resistance circuit constituted by a source-to-drain path of a p-channel MOS field effect transistor TRA. The junction point of K2A and TRA is connected to a positive input of a comparator circuit constituted by an operational amplifier AMPA whose negative input is connected to an output of a summing circuit SUMA to whose positive inputs a signal voltage RXP, the reactance voltage ZCOP and a bias voltage -VBIAS are applied. An output of the operational amplifier AMPA is connected to control electrodes CT of transistor circuits K1A, K2A and K4A. Further control electrodes CR of K1A and K2A are connected to outputs CENTER and COMMON, respectively, of a resistance control circuit as will be described later. Likewise, the line impedance synthesis circuit includes between the supply terminal VBAT and line terminal BW the series connection of a main path AB of a transistor circuit K1B and a source-to-drain path of a n-channel MOS field effect transistor TEXB whose gate is coupled to a positive pole of a DC bias voltage source VBB, a negative pole of which is connected to VBAT, as well as the series connection of a main path AB of a transistor circuit K2B and a source-to-drain path of a n-channel MOS field effect transistor TRB. The junction point of K2B and TRB is connected to a positive input of an operational amplifier AMPB whose negative input is connected to an output of a summing circuit SUMB to whose positive inputs a signal voltage RXN, the reactance voltage ZCON and a bias voltage - VFEED - VBIAS are applied. An output of AMPB is connected to control electrodes CT of transistor circuits K1B, K2B and K4B. Control electrodes CR of K1B and K2B are connected to the outputs CENTER and COMMON of the above mentioned resistance control circuit, respectively. The line impedance synthesis circuit moreover includes a transistor circuit K3A whose main path AB is coupled between the supply terminal GND and a switch S1A via which it may be connected either to the source or to the drain of TRA under the control of a switch control signal supplied at a switch control terminal of a switch control circuit SCM. Likewise, a main path AB of a transistor circuit K3B is coupled between the supply terminal VBAT and a switch S1B via which it may be connected either to the source or to the drain of TRB under the control of a second switch control signal supplied by SCM. Control electrodes CT of K3A and K3B are coupled to the output of AMPA and AMPB via resistors RCA and RCB, respectively, and are intercoupled via a capacitor C. Control electrodes CR of K3A and K3B are via switches S2A and S2B, respectively, coupled either to the output COMMON of the resistance control circuit or to the output CENTER thereof under the control of the above second switch control signal supplied by SCM. The resistance control circuit includes between bias terminals -VBIAS and -VFEED - VBIAS, respectively, to which the above like named bias voltages are supplied, the series connection of resistors R1, R2, R3 and R4, and the series connection of a source-to-drain path of a p-channel MOS field effect transistor FEA, a resistor R5 and a drain-to-source path of a n-channel MOS field effect transistor FEB. It further includes an operational amplifier OA1 whose positive input is connected to the drain electrode of FEA, whose negative input is connected to the junction point of R1 and R2, and whose output is connected to the gate of FEA as well as the gate of TRA, and an operational amplifier OA2 whose positive input is connected to the drain electrode of FEB, whose negative input is connected to the junction point of R3 and R4, and whose output is connected to the gate of FEB as well as the gate of TRB. The junction point of R2 and R3 constitutes the output CENTER connected to the control electrodes CR of K2A and K2B as mentioned above, and also to a negative input of a summing circuit SUMC whose positive inputs are connected to the line terminals AW and BW, respectively, and whose output constitutes the output COMMON of the resistance control circuit. Each of the transistor circuits K1A, K2A, K3A and K4A is of the same type as the transistor circuit K shown in Fig 2. It includes between terminals A and B the series connection of source-to-drain paths of p-channel MOS field effect transistors FE5, FE1 and FE2, and between terminal A and a terminal TCS the parallel connection of source-to-drain paths of p-channel MOS field effect transistors FE3 and FE4 in series with a current source CS. The gate electrode of FE2 is connected to the drain electrode of FE3, whereas the gate electrode of FE3 is connected to the drain electrode of FE1. The gate electrode of FE1 constitutes the control electrode CT of K whereas the gate electrode of FE4 constitutes a control electrode CTx of K. The latter control electrode CTx is connected to the junction point of resistor RCA and capacitor C shown in Fig 1, this connection being not shown in either of Figs 1 or 2 so as not to overload these Figures. The gate electrode of FE5 constitutes the control electrode CR of K. The terminal TCS is connected to the supply terminal VBAT which is not shown in Fig 1. The transistor circuit K4A includes a further p-channel MOS field effect transistor (not shown) whose source-to-drain path is connected in parallel to that of FE5. The gate electrodes of this not shown transistor and of FE5 constitute the respective control electrodes CR1 and CR2 of K4A. To be noted that transistor circuits K1B, K2B, K3B and K4B are similarly built from n-channel MOS fields effect transistors. In this case the terminal TCS is connected to the supply terminal GND and the terminal CTx is connected to the junction point of RCB and capacitor C. The load impedance ZCO shown in Fig 3 includes a double-ended operational amplifier DOA whose positive input is coupled to the transistor circuit K4A via a load resistor RA1, and to its negative output via a feedback resistor RB1. Likewise, a negative input of DOA is coupled to the transistor circuit K4B via a load resistor RA2, and to its positive output via a feedback resistor RB2. The outputs of DOA are furthermore connected to the reactance synthesis circuit SYN also shown in Fig 3 and including the series connection of high pass filter HPF and a gain circuit. This gain circuit includes an operational amplifier SOA whose positive input is coupled to an output of HPF via a resistor RD2, and to supply terminal GND via a resistor RE2. A negative input of SOA is furthermore coupled to a second output of HPF via a resistor RD1, and to its output via a resistor RE1. The output of SOA is coupled to a gain resistor RG in series with the parallel connection of a gain capacitor CG and a gain amplifier AMPC. The junction point of RG and CG is connected to inputs of positive and negative unity gain amplifiers BUFP and BUFN, respectively, whose outputs constitute output terminals ZCOP and ZCON, respectively, providing the above like named reactance voltages. It should be noted that the line impedance synthesis circuit is implemented as an integrated circuit except for transistors TEXA and TEXB and resistor R5, whereby respective transistor parameters, e.g. the hole and electron mobilities µn and µp, respectively, and gate oxide capacitance Cox, are assumed to be the same for all transistors used. The operation of the line impedance synthesis circuit is now described hereinafter. As already mentioned, the line impedance synthesis circuit is used in a telecommunication line circuit interfacing between the two-wire telecommunications line and a subscriber unit, and provides a matched impedance for this line. The telecommunication line being part of a national telephone system, the value to be provided for this matched impedance is prescribed by the respective national Telecommunications administration exploiting the telephone system. This prescribed value has a DC and an AC component. The DC component measured without an AC signal present on the telecommunication line is the so-called feed resistance Rfeed, and the AC component, which is the value for an AC signal on the telecommunication line with a frequency spectrum extending from approximately 300 Hz on upwards, has a resistive component RZCO and a reactive component XZCO. As follows from Fig 1, the impedance seen from the telecommunication line connected to line terminals AW and BW has a first component between line terminal AW and supply terminal GND which is due to transistor circuits K1A, K2A, K3A and transistor TRA, and a second component between line terminal BW and supply terminal VBAT which is due to transistor circuits K1B, K2B, K3B and transistor TRB. For the subsequently following derivation of formulas for the respective above components Rfeed, RZCO and XZCO of the impedance, these transistor circuits are assumed to be operating as field effect transistors, i.e. the effects incurred by transistors FE2, FE3, FE4 and FE5 are initially neglected but will be described later. In DC, i.e. for calculating Rfeed, the above first component of the impedance is caused by K1A, K2A, K3A and TRA. Without taking the effect of K3A into account, Rfeed may be calculated as follows. The resistance value RTRA of the source-to-drain path of TRA, which is assumed to be operating in triode region, depends largely on its gate-to-source voltage VGS and only slightly on its drain-to-source voltage VDS, and is given by: RTRA = 1 µp×Cox× W L VGS - VT - VDS 2 -1 Herein, µp is the mobility of holes in the channel, i.e. the drain-to-source path, of TRA, Cox is the capacitance value of the gate oxide of TRA, W / L is the width-to-length ratio of the channel of TRA, and VT is the so-called threshold voltage of TRA. Since the voltages between the control electrodes CT and terminals A of K1A and K2A are the same, both K1A and K2A being assumed to operate in their saturation region, the ratio of the currents through the main paths AB of K1A and K2A is equal to the ratio of their W / L ratios. Hence, when a current I flows through the main path AB of K2A, a current I × WL1 WL2 flows through the main path AB of K1A, wherein WL1 is the W / L ratio of K1A, whereas WL2 is the W / L ratio of K2A. Hence, Rfeed = RTRA × WL2 WL1+WL2 . To be noted that this formula gives a first approximation wherein the effect of a voltage drop over the main path AB of K2A is neglected. A more exact formula is the following one which also takes the effect of K3A into account. Herein, VAW is the voltage at line terminal AW, GND is the voltage at the like named supply terminal, WL3 is the W / L ratio of K3A, and α is the voltage at the junction point of TRA and K2A, i.e. α = -VBIAS + RXP + ZCOP. Since both RXP and ZCOP constitute AC voltages, α becomes equal to -VBIAS for calculating Rfeed. When K3A is connected to the source of TRA, R is multiplied with the upper factor between the two braces { and }, whereas the lower factor, viz. 1 , applies when K3A is connected to the drain of TRA. Assuming now that the line impedance synthesis circuit is symmetrical so that a same impedance is seen from line terminal BW to supply terminal VBAT as from AW to GND, then Rfeed is twice the above calculated value. For AC frequencies higher than the above mentioned 300 Hz, capacitor C short-circuits the control electrodes of K3A and K3B, whereby for the AC components RZCO and XZCO of the impedance both these transistor circuits no longer come into account. The resistive component RZCO may then be simply determined from the above analysis and is given by the following formula wherein a factor 2 is used to also take the impedance from BW to VBAT into account. Herein, α = -VBIAS + RXP + ZCOP. Comparing now the formulas for Rfeed and RZCO, it may be easily verified that when K3A/K3B is connected to the source of TRA/TRB, Rfeed is higher than RZCO, whereas when K3A/K3B is connected to the drain of TRA/TRB, Rfeed is lower than RZCO. Whether K3A/K3B is connected to the source or the drain of TRA/TRB is determined by the switch control signal provided by the switch control circuit SCM. The reactive part XZCO of the AC component of the impedance is synthesized by way of the voltages ZCOP and ZCON derived from a current flowing through K4A, ZCO and K4B. This current is equal to I × WL4 WL2 , wherein I is the current through K2A and WL4 is the W / L ratio of K4A. This current I flows through the load resistors RA1 and RA2 of DOA, and through its feedback resistors RB1 and RB2. Since the input voltage between the positive and negative input terminals of DOA may be assumed negligibly small, the resistance value between terminals ZCOA and ZCOB is equal to RA1 + RA2, wherein RA1 and RA2 are the values of the respective like named resistors. Assuming RB1 / RA1 = RB2 / RA2, wherein RB1 and RB2 are the values of the respective like named resistors, the output voltage of DOA is then equal to - RB1 / RA1 × VZCO, wherein VZCO is the voltage across terminals ZCOA and ZCOB of the load impedance ZCO, i.e. VZCO = I × WL4 WL2 × (RA1+RA2). The latter voltage is filtered by HPF which has a lower 3dB frequency equal to the already mentioned 300 kHz, and is thereupon applied to SOA via resistors RD1 and RD2. Assuming RD1 / RE1 = RD2 / RE2 wherein RD1, RD2, RE1 and RE2 are the values of the respective like named resistors, the voltage at the output of SOA, i.e. across the series connection of RG and CG, is equal to RE1 / RD1 × RB1 / RA1 × VZCO. Thus, the voltage at the junction point of RG and CG, i.e. the voltages ZCOP and -ZCON, is given by the following formula. ZCOP = I × WL4 WL2 × (RA1 +RA2) × RB1 RA1 × RE1 RD1 × 1 1 + s × CG' × RG = -ZCON Herein, RG is the value of the like named resistor and CG' is the capacitance value between the junction point of RG and CG and supply terminal GND. In the absence of the operational amplifier AMPC this value CG' is equal to CG. However, by amplifying the voltage at the junction point of RG and CG by a factor Aampc and applying the thus amplified voltage to the terminal of CG not connected to RG, CG' becomes equal to (1+Aampc)×CG. To be noted that AMPC should have a low output impedance. In order to now determine the reactive part XZCO of the AC component of the impedance, the value for ZCOP is introduced in the factor a of the formula for RZCO, which thus provides both the resistive and the reactive parts RZCO and XZCO. Herein, β = WL4 WL2 × (RA1 + RA2) × RB1 RA1 × RE1 RD1 and γ = RXP I - VBIAS I - GND I . Thus, except for y, the AC component of the impedance is equivalent with a resistor with value 2 × WL2 / WL1 + WL2 × R in series with the parallel connection of a resistor with a value 2 × WL2 / WL1 + WL2 × β and a capacitor with a value CG'×RG 2 × WL2 WL1+WL2 × β . To be noted that this series connection is equivalent to the parallel connection of a resistor with the series connection of another resistor and a capacitor as may be easily verified and as the AC component of the impedance is often prescribed by the national Telecommunications administrations. Thus, a full synthesis of the impedance has been obtained. It should also be remarked that the bias voltage VBIAS is needed for the operation of the respective transistor circuits, and that hence the supply voltage applied across terminals GND and VBAT must at least be equal to VFEED+2×VBIAS. The operation of the resistance control circuit is now described and the resistance value RTRA/RTRB of the source-to-drain path of transistor TRA/TRB is calculated. This resistance control circuit is constituted by a Wheatstone-like bridge wherein the voltages at the junction points of R1 and R2 and of FEA and R5, and the voltages at the junction points of R3 and R4 and of FEB and R5 are kept equal by the operational amplifier OA1 and OA2, respectively. Indeed, when e.g. the voltage at the junction point of FEA and R5 exceeds the voltage at the junction point of R1 and R2, the output voltage of OA1 becomes more positive, whereby the source-to-drain path of FEA becomes less conductive, i.e. its resistance increases, and the voltage at the junction point of FEA and R5 decreases. As a result, RFEA / R1 = R5 / R2 + R3 = RFEB / R4, wherein RFEA and RFEB are the resistance values of the source-to-drain paths of transistors FEA and FEB, respectively. Thus, when for resistor R5 a precision resistor is used with an accurate and stable absolute value, then the values of RFEA and RFEB are also accurate and stable when the latter ratio's are accurate and stable, which may be easily obtained when the resistance control circuit is implemented as an integrated circuit. Since, except for the AC signals RXP/RXN and the reactance voltages ZCOP/ZCON, the gate-to-source voltages VGS of FEA and FEB are equal to those of TRA and TRB, respectively, in a first approximation the resistance values of their respective source-to-drain paths stand in relation as their W / L ratios, more exactly and taking the drain-to-source voltages VDSFEA and VDSTRA of FEA and TRA, respectively, into account, which are however assumed to be small, RTRA RFEA = WLFEA WLTRA × VGS - VT - VDSFEA 2 VGS - VT - VDSTRA 2 , wherein WLFEA and WLTRA are the W / L ratios of FEA and TRA, respectively, VT is the threshold voltage of TRA and of FEA which is assumed to be the same. As a result, RTRA = WLFEA WLTRA × R1 × R5 R2 + R3 . To be noted that this value RTRA may be electronically modified for instance by connecting further transistors in parallel to FEA or TRA thereby changing the respective W / L ratio. The resistance control circuit furthermore provides at the output CENTER a like named voltage which, R1 + R2 being assumed to be equal to R3 + R4, is equal to - VFEED / 2 - VBIAS, and constitutes a reference voltage around which the voltages VA and VB at the line terminals AW and BW, respectively, should be centered. At the output COMMON the like named voltage equal to VA+VB-CENTER is supplied. Thus; when VA and VB are centered around CENTER, COMMON is equal to CENTER. These voltages COMMON and CENTER are applied to transistor circuits K1A, K2A, K3A, K1B, K2B and K3B as described above and cause the voltages VA and VB to be centered around CENTER. This will become clear from the following operation of these transistor circuits. Not considering in a first instance the effects of transistors FE4 and FE5, a voltage VCT applied between control electrode CT and terminal A is assumed to have such a value that the source-to-gate voltage -VGS of FE1 is larger than the absolute value of its threshold voltage but smaller than the sum of its source-to-drain voltage and this absolute value, i.e. that FE1 operates in saturation. As a consequence, when the current source CS provides a current to the source-to-drain path of FE3, then a current flows through the source-to-drain paths of FE1 and FE2 which is equal to µp × Cox × W 2 × L (VGS - VT) 2 . Indeed, the gate of FE1 being biased by VCT, its source-to-drain path becomes conductive whereby the voltage at its drain rises, i.e. is pulled towards the voltage at terminal A. Thereby, since the current provided by CS causes the voltage at the drain of FE3 to decrease, FE2 becomes conductive whereby the voltage at its source reaches a value low enough to ensure the source-to-drain path of FE3 to become conductive in order to provide a path for the current of CS to GND. On the other hand, when CS no longer provides a current then, FE3 still being conductive, the voltage at its drain is pulled towards the voltage at terminal A, whereby FE2 is no longer conductive and the current through the main path AB of the transistor circuit K is cut off. In this way, the transistor circuit K may be made active or inactive by controlling the current provided by the current source CS, so that the W / L ratio of either of the transistor circuits K1A to K4B may be modified by connecting several such transistor circuits in parallel and selectively making them active or inactive. In a similar way, FE4 ensures that the DC part of the current flowing through the main path AB of K does not exceed a predetermined threshold value due to too high an absolute value of the control voltage applied between CTx and A. Indeed, the higher this absolute value, the larger part of the current provided by CS flows to terminal A via the drain-to-source path of FE4. Thereby, the voltage at the drain of FE3 rises and finally becomes so high that FE2 is no longer conductive and the current through the main path AB of K is cut off. Thus, a DC current limitation is obtained by means of transistor FE4. Transistor FE5 is assumed to operate in its triode region, i.e. the voltage applied between terminal A and the second control electrode CR is assumed to be larger than the absolute value of the threshold voltage of FE5 and larger than the sum of its source-to-drain voltage and this absolute value. Thus, the source-to-drain path of FE5 constitutes a resistance with a value given by a formula similar to the one already given for RTRA and which increases with increasing value of the voltage at CR, i.e. with decreasing absolute value of the voltage applied between A and CR. In this way the voltages CENTER and COMMON provided by the resistance control circuit lead to an improved centering of the voltages VA and VB at line terminals AW and BW around CENTER. Indeed, when for instance VA + VB is larger than twice CENTER, then COMMON is larger than CENTER so that the resistance value of the source-to-drain path of FE5 of transistor circuit K1A is larger than that of transistor circuit K2A, whereas the resistance value of the source-to-drain path of FE5 of transistor circuit K1B is lower than that of transistor circuit K2B. As a consequence, the currents flowing through the main paths AB of K1A and K3A decrease slightly, thus causing the part of the impedance seen from AW to GND to increase and the voltage at line terminal AW to decrease, whereas the current flowing through the main path AB of K1B increases slightly, thus causing the part of the impedance seen from BW to VBAT to decrease and the voltage at line terminal BW to decrease. Hence, VA + VB decreases and VA and VB become centered around CENTER. To be noted that a similar reasoning applies when VA + VB is lower than twice CENTER. To be noted also that for DC signals the current flowing through K3A/K3B should be added to either that flowing through K1A/K1B or that flowing through K2A/K2B depending on to which side of transistor TRA/TRB it is connected, which however does not alter the above reasoning. The voltages VOUTA and VOUTB at the output terminals OUTA and OUTB, respectively, being applied to the respective control electrodes CR1 and CR2 of K4A and K4B has the effect of centering VOUTA and VOUTB around CENTER. Indeed, when VOUTA + VOUTB increases above CENTER then the resistance value of the source-to-drain paths of FES and the above mentioned not shown transistor of K4A increases whereas that of K4B decreases, whereby VOUTA + VOUTB decreases again and VOUTA and VOUTB are centered around CENTER. To be noted that VOUTA and VOUTB constitute output voltages of the circuit which may be further processed and from which the signal voltages RXP and RXN may easily be derived. It should also be noted that the current flowing through the telecommunication line largely flows through TEXA and K1A on the one hand, and through TEXB and K1B on the other hand, and that, when designed properly, the power dissipation which is due to this current and voltage standing between AW and GND, and between BW and VBAT, occurs for the largest part in TEXA and TEXB. Therefore, these transistors TEXA and TEXB are implemented as external power components, so that as a result the whole line impedance synthesis circuit may be integrated except for TEXA, TEXB and the precision resistor R5. The line impedance synthesis circuit may further include a similar circuit as depicted in Fig 1 but wherein AW is connected to VBAT and BW to via respective impedance means, whereby a reverse operation on the telecommunication line may be obtained. One of the two circuits as depicted in Fig 1 must then be disabled by cutting off the current provided by the current sources CS of the respective transistor circuit. To be noted that a same load impedance ZCO and a same resistance control circuit may be used for both the latter similar circuits. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: Line impedance synthesis circuit for a telecommunication line circuit and which is coupled to line terminals (AW,BW) of a telecommunication line and fed from first (GND) and second (VBAT) terminals of a voltage supply source, characterized in that said line terminals (AW,BW) are coupled to said first (GND) and second (VBAT) supply terminals via respective first and second impedance means at least one of which includes a main path (A-B) of a first transistor circuit (K1A/K1B) shunted by the series connection of a resistance circuit (TRA/TRB) and a main path (A-B) of a second transistor circuit (K2A/K2B), control electrodes (CT) of said first (K1A/K1B) and second (K2A/K2B) transistor circuits being coupled to a same control output of a control circuit (AMPA,SUMA/AMPB,SUMB). Line impedance synthesis circuit according to claim 1, wherein said first and second impedance means are alike and controlled by respective first (AMPA,SUMA) and second (AMPB,SUMB) control circuits. Line impedance synthesis circuit according to claim 2, wherein each of said impedance means includes a third transistor circuit (K3A/K3B) whose control electrode (CT) is coupled via a resistance (RCA/RCB) to said control output of the corresponding one of said first and second control circuits (AMPA,SUMA/AMPB,SUMB), and whose main path (A-B) is coupled in parallel with said main path (A-B) of said first (K1A/K2A) or second (K1B/K2B) transistor circuit, said control electrodes (CT) of said third transistor circuits (K3A,K3B) of both said first and second impedance means being intercoupled via a capacitance (C). Line impedance synthesis circuit according to claim 3, wherein said impedance means includes a switch (S1A/S1B) adapted to connect said main path of said third transistor circuit (K3A/K3B) in parallel either with said main path of said first transistor circuit (K1A/K1B) or with said main path of said second transistor circuit (K2A/K2B) under the control of a switch control signal supplied at a switch control terminal of a switch control circuit (SCM). Line impedance synthesis circuit according to claim 2, further comprising between said first (GND) and second (VBAT) supply terminals the series connection of a fourth transistor circuit (K4A), a load impedance (ZCO) and a fifth transistor circuit (K4B), control electrodes (CT) of said fourth (K4A) and fifth (K4B) transistor circuits being coupled to said control outputs of said first and second control circuits (AMPA,SUMA/AMPB,SUMB). Line impedance synthesis circuit according to claim 5, wherein said load impedance (ZCO) includes a double-ended operational amplifier (DOA) whose positive and negative outputs are coupled via respective feedback resistances (RB1,RB2) to its negative and positive inputs, respectively, which in their turn are coupled via respective load resistances (RA1,RA2) to said fifth (K4B) and fourth (K4A) transistor circuits, respectively. Line impedance synthesis circuit according to either of claims 1, 2, 3 or 5, wherein each of said first, second, third and fourth transistor circuits (K;K1A,K2A,K3A,K4A/K1B,K2B,K3B,K4B) includes a field effect transistor (FE1) whose gate electrode constitutes said control electrode (CT) coupled to said control output of said control circuit (AMPA,SUMA/AMPB,SUMB). Line impedance synthesis circuit according to claim 7, wherein said transistor circuit (K) further includes second (FE2) and third (FE3) field effect transistors and a current source (CS), the series connection of source-to-drain paths of said first mentioned (FE1) and second (FE2) field effect transistors constituting said main path of said transistor circuit (K), the series connection of a source-to-drain path of said third field effect transistor (FE3) and said current source (CS) being connected between said first/second (GND/VBAT) and second/first (VBAT/GND) supply terminals of said voltage supply source, a gate electrode of said second field effect transistor (FE2) being coupled to the junction point of said drain-to-source path of said third field effect transistor (FE3) and said current source (CS), and a gate electrode of said third field effect transistor (FE3) being coupled to the junction point of said drain-to-source paths of said first (FE1) and second (FE2) field effect transistors. Line impedance synthesis circuit according to claim 8, wherein said transistor circuit (K) further includes a fourth field effect transistor (FE4) whose source-to-drain path is coupled in parallel to said source-to-drain path of said third field effect transistor (FE3) and whose gate electrode is coupled to said gate electrode of said first field effect transistor (FE1). Line impedance synthesis circuit according to claim 8, wherein said transistor circuit (K) further includes a fifth field effect transistor (FE5) whose source-to-drain path is coupled between said first/second supply terminal (GND/VBAT) of said voltage supply source and said source-to-drain path of said first field effect transistor (FE1), and whose gate electrode constitutes a second control electrode (CR) of said transistor circuit (K). Line impedance synthesis circuit according to claim 8, wherein the current provided by said current source (CS) is controlled by a control signal provided by a current control circuit. Line impedance synthesis circuit according to claim 11, wherein said impedance means further includes further transistor circuits coupled in parallel to either of said first (K1A/K1B), second (K2A/K2B) or third (K3A/K3B) transistor circuits and the current of whose current source (CS) may be cut off by said control signal. Line impedance synthesis circuit according to claims 2 and 11, wherein said first (AW) and second (BW) line terminals are further coupled to said second (VBAT) and first (GND) supply terminals via like said impedance means. Line impedance synthesis circuit according to claim 1, wherein said first transistor circuit (K1A/K1B) is coupled to a corresponding one of said first (AW) and second (BW) line terminals via a source-to-drain path of a sixth field effect transistor (TEXA/TEXB) whose gate electrode is coupled to said first/second supply terminal (GND/VBAT) via a bias voltage source (VBA/VBB). Line impedance synthesis circuit according to claim 1, wherein said control circuit (AMPA, SUMA/AMPB,SUMB) includes a comparator circuit (AMPA/AMPB) a first input of which is coupled to the junction point of said resistance circuit (TRA/TRB) and said main path of said second transistor circuit (K2A/K2B), to a second input of which a correction voltage (RXP+ZCOP-VBIAS/RXN+ZCON-VFEED-VBIAS) is applied, and an output of which constitutes said control output of said control circuit (AMPA,SUMA/AMPB,SUMB). Line impedance synthesis circuit according to claim 15, wherein said comparator circuit (AMPA/AMPB) includes an operational amplifier. Line impedance synthesis circuit according to claim 15, wherein said control circuit (AMPA, SUMA/AMPB,SUMB) further includes a summing circuit (SUMA/SUMB) to a first input of which a reactance voltage (ZCOP/ZCON) is applied proportional to the reactance component of said impedance associated to said telecommunication line circuit, to a second input of which a signal voltage (RXP/RXN) proportional to an AC signal on said telecommunication line is applied, to a third input of which a bias voltage (-VBIAS/-VFEED-VBIAS) providing bias for said impedance means is applied, and an output of which provides said correction voltage (RXP+ZCOP-VBIAS/RXN+ZCON-VFEED-VBIAS). Line impedance synthesis circuit according to claims 6 and 17, further comprising the cascaded connection of a high pass filter (HPF) and a gain circuit (RD1,RD2,RE1,RE2,SOA,RG,CG,AMPC,BUFP,BUFN), inputs of said high pass filter (HPF) being coupled across said outputs of said load impedance (ZCO) and outputs of said gain circuit (RD1,RD2,RE1,RE2,SOA,RG,CG,AMPC,BUFP,BUFN) providing said reactance voltage (ZCOP/ZCON). Line impedance synthesis circuit according to claim 18, wherein said gain circuit (RD1,RD2, RE1,RE2,SOA,RG,CG,AMPC,BUFP,BUFN) includes, coupled across said load impedance (ZCO) via said high pass filter (HPF), the series connection of an amplifier section (RD1,RD2,RE1, RE2,SOA), and a gain resistance (RG) and a gain capacitance (CG) whose junction point provides said reactance voltage (ZCOP/ZCON). Line impedance synthesis circuit according to claim 19, wherein said gain circuit (RD1,RD2, RE1,RE2,SOA,RG,CG,AMPC,BUFP,BUFN) further includes a gain amplifier (AMPC), between an input and an output of which said gain capacitance (CG) is coupled. Line impedance synthesis circuit according to claim 1, wherein said resistance circuit (TRA/TRB) is constituted by the main path of a seventh field effect transistor whose gate electrode is coupled to a resistance control output of a resistance control circuit. Line impedance synthesis circuit according to claim 21, wherein said resistance control circuit includes the series connection of second (R1/R4) and third (R2,R3) resistances between first (-VBIAS/-VFEED-VBIAS) and second bias terminals, the series connection of a main path of an eighth field effect transistor (FEA/FEB) and a fourth resistance (R5) between said first (-VBIAS/-VFEED-VBIAS) and a third bias terminal, and an operational amplifier (OA1/OA2) whose inputs are coupled to the junction point of said main path of said eighth field effect transistor (FEA/FEB) and said fourth resistance (R5), and to the junction point of said second (R1/R4) and third (R2,R3) resistances, respectively, and whose output is coupled to a gate electrode of said eighth field effect transistor (FEA/FEB) and constitutes said resistance control output, a bias voltage being applied across said first (-VBIAS/-VFEED-VBIAS) and second bias terminals, and said second and third bias terminals being biased at a same voltage. Line impedance synthesis circuit according to claims 2 and 22, wherein said resistance control circuit further includes a fifth resistance (R4) between said second and a fourth (-VFEED-VBIAS) bias terminal, a main path of a ninth field effect transistor (FEB) between said third and fourth (-VFEED-VBIAS) bias terminals, and a second operational amplifier (OA2) whose inputs are coupled between said second and third bias terminals and whose output is coupled to a gate electrode of said ninth field effect transistor (FEB), a second bias voltage (VFEED) being applied across said first (-VBIAS) and fourth (-VFEED-VBIAS) bias terminals. Line impedance synthesis circuit according to claim 23, wherein said supply voltage supplied by said voltage supply source across said first (GND) and second (VBAT) supply terminals is at least equal to the sum of said second bias voltage (VFEED) and twice a bias voltage value (VBIAS). Line impedance synthesis circuit according to claims 10 and 24, wherein said second (R1) and fifth (R4) resistances have a same value, that said third resistance (R2,R3) is constituted by the series connection of two resistances with a same value and whose junction point (CENTER) is coupled to said second control electrode (CR) of said first transistor circuit (K1A/K1B) and to a negative input of a summing circuit (SUMC), first and second positive inputs of which are coupled to said first and second line terminals (AW/BW), respectively, and an output (COMMON) of which is coupled to said second control electrode (CR) of both said second transistor circuits (K1A/K1B). Line impedance synthesis circuit according to claim 22, wherein said resistance control circuit is implemented as an integrated circuit except for said fourth resistance (R5), which is a precision resistance external to said integrated circuit, and said sixth field effect transistor (TEXA, TEXB). Line impedance synthesis circuit according to claim 3, wherein said capacitance (C) presents a negligible impedance for telecommunication speech signals.

Inventors: SALLAERTS DANIEL, SEVENHANS JOANNES MATHILDA JOS, SALLAERTS, DANIEL, SEVENHANS, JOANNES MATHILDA JOSEPHUS
Applicants: ST MICROELECTRONICS NV, STMICROELECTRONICS N.V.
Application year: 1994
Main classification: H04M19
IPC codes: H04M19