Power inverting apparatus

Abstract: The present invention provides a power inverting apparatus capable of coping with an abrupt change in phase of input voltage within a certain range and operating in a stable manner continuously. According to the first aspect of the present invention, a power inverting apparatus comprises a converter unit (D) for changing ac voltage supplied by an ac voltage source (7) into dc voltage, an inverter unit (C) for changing the voltage supplied by the converter unit into ac voltage, and an input voltage control unit (17) that when the polarity of ac voltage supplied by the ac voltage source is inconsistent with the one of ac voltage supplied by the inverter unit, cuts off ac voltage to be supplied to the converter unit.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION: The present invention relates to a power inverting apparatus for changing ac voltage into dc voltage and back into ac voltage according to the preamble of claim 1. An apparatus of this kind is known from JP 2 231 965. DESCRIPTION OF THE RELATED ART: To begin with, a basic configuration and operation of major circuits of a power inverting apparatus will be described in conjunction with the first prior art shown in Figs. 33 and 34. Fig. 33 is a block diagram showing a constant-voltage/constant-frequency power supply disclosed in, for example, Japanese Patent Laid-Open No.2-231965. Fig. 34 is an explanatory diagram showing the operation of the power supply. In Fig. 33. A denotes a converter made by connecting diodes 1 and 2 serving as rectifying elements in series with each other. A dc output terminal of the converter A is connected to a smoothing capacitor 12. Reference alphabet B denotes a selector. C denotes an inverter. The selector B or inverter C consists of two switching circuits 3 and 4 or 5 and 6. The switching circuit 3 is composed of a switching element 3t that is, for example, a transistor or a field-effect transistor (hereinafter, FET), and a flywheel diode 3d connected in parallel with but in the opposite direction of the switching element 3t. The same applies to the switching circuits 4, 5, and 6. The input and output terminals of the converter A, smoothing capacitor 12, selector B, and inverter C are connected in parallel with one another over connection lines 10 and 11. Reference numeral 7 denotes an ac voltage source for supplying an input voltage Vs. One of the terminals of the ac voltage source 7 is connected to a middle point of the converter A via a connection line 8. The other terminal thereof is linked with the connection line 9. 14 denotes a loading circuit, one of whose terminals is connected to a middle point of the inverter circuit C; that is, one ac output terminal via the connection line 13. The other terminal of the loading circuit 14 is connected to a middle point of the selector B: that is, the other ac output terminal via the connection line 9. Next, the operation of the foregoing conventional power supply will be described. Figs. 34a to 34e show various states of switching elements and current flows. First, when the converter operates, current flows as indicated in Fig. 34b within a range defined with a wave A of voltage shown in Fig. 34a or during a positive half cycle thereof. Within a range defined with a wave B of the voltage shown in Fig. 34a or during a negative half cycle thereof, current flows as indicated in Fig. 34d. Thus, the smoothing capacitor 12 is charged with the peak-to-peak value of the input voltage. A dc voltage V D shown in Fig. 35 is provided as a product of the square root of 2 multiplied by Vs. The inverter circuit C operates as described below. For outputting the positive voltage (range A) shown in Fig. 34a, the switching elements 4t and 5t shown in Fig. 34c are turned on. For outputting the negative voltage (range B) shown in Fig. 34a, the switching elements 3t and 6t are turned on. Thus, both the positive and negative voltages can be supplied. If pulse-width modulation (PWM) is controlled at either of the switching elements in each of Figs. 34c and 34e, voltage having a sine wave is made available. To provide the positive voltage within a hatched range in Fig. 35, the switching element 4t in the selector B must be conducting and the switching element 5t in the inverter C must control pulse-width modulation according to a sine-wave command. To provide the negative voltage within a hatched range in Fig. 35, the switching element 3t in the selector B must be conducting and the switching element 6t in the inverter C must control pulse-width modulation according to a sine-wave command. Under the foregoing switching control, when an inverter output voltage V INV , which is not shown, is passed through a filter circuit. a sine wave voltage like a negative voltage V L shown in Fig. 35 is made available. Herein, the input voltage Vs and output voltage V L may be different in waveform from each other but must be in phase with each other (their zero points must coincide with one another). Next, a constant-voltage/constant-frequency power supply of the second prior art will be described concerning mainly a control relationship using Fig. 36. The second prior art adopts a converter D instead of the converter A in Fig. 33. The converter D is made by connecting switching circuits 1 and 2 in series with each other. The switching circuit 1 or 2 consists of a switching element 1t or 2t that is a transistor or an FET, and a diode 1d or 2d. Reference numeral 15 denotes an ac reactor. One terminal of the ac reactor 15 is connected to a middle point of the converter D via a connection line 8, and the other terminal thereof is connected to the ac voltage source 7 via a connection line 16. Reference numeral 30 denotes a control circuit for controlling switching elements 1t to 6t included in the converter D, selector B, and inverter C. 100 denotes a converter voltage command generator for actuating the converter with a high power factor. 101 denotes a carrier generator. 102 denotes an inverter voltage command generator for use in reshaping load voltage in the form of a sine wave. 103 denotes a comparator for comparing an output V CMD1 of the converter voltage command generator 100 with an output CAR of the carrier generator 101. 104 denotes a comparator for comparing an output V CMD2 of the inverter voltage command generator 102 with an output CAR of the carrier generator 101. 105 denotes a zero-crossing detector for detecting a zero crossing by analyzing an output of the inverter voltage command generator 102. 106 denotes a switching pattern generator for generating switching signals T 1 to T 6 using the outputs of the comparators 103 and 104 and the zero-crossing detector 105. Fig. 37 shows a circuitry of the switching pattern generator 106. 107 to 109 denote reversing circuits. 110, 111, 113, and 114 denote AND circuits. 112 and 115 denote OR circuits. 116 and 117 denote reversing circuits. Other circuit elements except the foregoing ones are identical to those in the first prior art described previously. Next, the operation of the second conventional power supply will be described with reference to the timing chart of Fig. 38. The comparator 103 compares the converter voltage command V CMD1 provided by the converter voltage command generator 100 with the carrier CAR provided by the carrier generator 101. When the carrier CAR is smaller, the comparator 103 outputs a converter PWM signal Ta having a high logic level. Likewise, the comparator 104 compares the inverter voltage command V CMD2 provided by the inverter voltage command generator 102 with the carrier CAR, and then outputs an Inverter PWM signal Tb. When the inverter voltage command V CMD2 is positive, the zero-crossing detector 105 outputs a polarity signal Tc having a high logic level. In Fig. 37, the polarity signal Tc is used as a switching signal T4, and a signal that is the polarity signal Tc reversed in polarity by the reversing circuit 107 is used as a switching signal T3. The AND circuits 110 and 111 and the OR circuit 112 constitute a selector. When the polarity signal Tc is high, the OR circuit 112 serving as the output terminal of the selector outputs the converter PWM signal Ta. When the polarity signal Tc is low, a signal that is the converter PWM signal Ta reversed polarity by the reversing circuit 108 is output. The output signal is used as a switching signal T1, and a signal that is opposite in polarity to the switching signal T1 and provided by the reversing circuit 116 is used as a switching signal T2. Likewise, the AND circuits 113 and 114 and the OR circuit 115 constitute a selector. When the polarity signal Tc is high, the OR circuit 115 serving as the output terminal of the selector outputs the Inverter PWM signal Tb. When the polarity signal Tc is low, the OR circuit 115 outputs a signal that is opposite in polarity to the inverter PWM signal Tb and provided by the reversing circuit 109. The output signal is used as a switching signal T5, and a signal that is opposite in polarity to the switching signal T5 and provided by the reversing circuit 117 is used as a switching signal T6. When two circuits of the converter D and selector B are discussed together, it will be understood that the circuits acts as a typical converter for changing ac voltage supplied by the ac voltage source 7 into dc voltage to charge the smoothing capacitor 12. The switching pattern of the converter D is consistent with the waveform of the converter PWM signal such as the one indicated as T1 or T2 in Fig. 68. Assuming that the converter voltage command is substantially in phase with the inverter voltage command, the switching pattern of the selector B becomes consistent with the waveform of the converter command V CMD1 . Consequently, the converter output voltage V CNV shown in Fig. 38 is provided. When two circuits of the inverter C and selector B are discussed together, it will be understood that the circuits act as a typical inverter for changing dc voltage existent at the smoothing capacitor 12 into ac voltage and then outputting the ac voltage. At this time, the switching pattern of the inverter C is consistent with the waveform of the Inverter PWM signal such as the one indicated as T5 or T6 in Fig. 38. The switching pattern of the selector B is consistent with the waveform of the polarity signal Tc for the inverter voltage command V CMD2 . Consequently, the inverter output voltage V INV shown in Fig. 38 is provided. The conventional constant-voltage/constant-frequency power supplies are configured as mentioned above. That is to say, the selector B is shared between a converter and an inverter. The selector B can therefore operate only under the condition that both the converter D and inverter C operate with the same polarity. For supplying stable voltage to a load, since the switching pattern of the inverter C cannot be altered, the selector B cannot help adopting a switching pattern dedicated to an inverter. If input voltage is abruptly reversed in polarity, the converter D fails to operate correctly. For example, when an uninterruptible power supply (CVCF) is concerned, a generator may be included in an input system. In this case, an abrupt phase change may occur due to switching between the power supply and generator. When the inverter C outputs positive voltage, if the input voltage is reversed 180° to be negative, since the selector B shown in Fig. 36 turns on the switching element 4t in order to provide inverter output voltage of positive polarity. the reactor 15 alone is connected from the ac voltage source 7 to the selector B via the switching element 4t and the diode 2d of the switching circuit 2 in the converter D. If this state continues for more than several milliseconds, overcurrent flows internally. The switching element 4t is therefore turned off forcibly. A desired inverter voltage cannot be output. SUMMARY OF THE INVENTION An object of the present invention is to solve the aforesaid problems and to provide a power inverting apparatus capable of coping with an abrupt change in phase of input voltage within a certain range and of operating in a stable manner continuously. This object is solved as characterized in claim 1. According to the present invention, a power inverting apparatus comprises a converter means for changing ac voltage supplied by an ac voltage source into dc voltage, an inverter means for changing dc voltage supplied by the converter means into ac voltage, and an input voltage control means that when the polarity of ac voltage supplied by the ac voltage source is inconsistent with the one of ac voltage supplied by the inverter means, cuts off ac voltage to be supplied to the converter means. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a power inverting apparatus of the first embodiment of the present invention: Fig. 2 shows waveforms representing the operation of the first embodiment; Fig. 3 is a block diagram showing a power inverting apparatus of the second embodiment; Figs. 4a and 4b are explanatory diagrams showing the operation of the second embodiment; Fig. 5 is a block diagram showing a power inverting apparatus of the third embodiment; Figs. 6a and 6b are explanatory diagrams showing the operation of the third embodiment; Fig. 7 shows a configuration of a power inverting apparatus of the fourth embodiment; Fig. 8 shows an error detector and gate circuits in the fourth embodiment; Fig. 9 shows waveforms representing the operation of the fourth embodiment; Fig. 10 shows a configuration of a power inverting apparatus of the fifth embodiment; Fig. 11 shows an error detector in the fifth embodiment; Fig. 12 shows waveforms representing the operation of the fifth embodiment; Fig. 13 shows a current flow occurring with the gates in the fourth or fifth embodiment blocked; Figs. 14 and 15 show current flows occurring with the gates in the sixth embodiment blocked; Fig. 16 shows a configuration of a power inverting apparatus of the sixth embodiment; Fig. 17 shows gate circuits and a polarity detector in the sixth embodiment; Fig. 18 shows waveforms representing the operation of the sixth embodiment; Fig. 19 shows a configuration of a power inverting apparatus of the seventh embodiment; Fig. 20 shows a polarity detector and an error detector in the seventh embodiment; Fig. 21 shows waveforms representing the operation of the seventh embodiment; Fig. 22 shows a configuration of a power inverting apparatus of the eighth embodiment; Fig. 23 shows an error detector in the eighth embodiment; Fig. 24 shows waveforms representing the eighth embodiment; Fig. 25 shows a configuration of a power inverting apparatus of the ninth embodiment; Fig. 26 shows a polarity detector, polarity reverse detector, and an error detector in the ninth embodiment; Fig. 27 shows waveforms representing the operation of the ninth embodiment; Fig. 28 shows a configuration of a power inverting apparatus of the tenth embodiment; Fig. 29 shows an error detector in the tenth embodiment; Fig. 30 shows waveforms representing the operation of the tenth embodiment; Fig. 31 shows input current commands in the eleventh embodiment; Fig. 32 shows a voltage difference error predictable and detectable range and the operating domains of an inverter and a converter in the twelfth embodiment; Fig. 33 is a block diagram showing a power inverting circuit of the first prior art; Figs. 34a to 34e are explanatory diagrams showing the operation of the first prior art; Fig. 35 shows waveforms of input/output voltages in the first prior art; Fig. 36 is a block diagram of a power inverting apparatus of the second prior art; Fig. 37 is a circuit diagram showing a switching pattern generator in the second prior art; and Fig. 38 shows waveforms representing the second prior art. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment The first embodiment of the present invention will be described in conjunction with the drawings. Figs. 1 and 2 show the first embodiment of the present invention. Fig. 1 shows the configuration. In Fig. 1, 17 denotes an input voltage control circuit serving as a bidirectional switching circuit made by connecting switching elements 17a and 17b for controlling unidirectional switching: such as, thyristors in parallel with each other but in the opposite directions. One terminal of the input voltage control circuit is connected to an ac voltage source 7 via a connection line 16, and the other terminal thereof is connected to a reactor 15 via a connection line 18. 1 to 16, and 30 denote the same circuit elements as those in a prior art, of which description will be omitted. Fig. 2 shows waveforms representing the operation of the input voltage control circuit 17. Vsa and Vsb denote waves of voltages supplied by the ac voltage source 7. As described later, the voltage Vsa indicated with a bold line fluctuates abruptly at a time instant t1 and assumes the waveform of the voltage Vsa indicated with another bold line. A switching signal T17a is equivalent to the switching signal T4 serving as a polarity signal for an inverter output voltage V INV . A switching signal T17b is equivalent to the switching signal T3. Vsc denotes an output voltage of the input voltage control circuit 17. Next, the operation of the input voltage control circuit 17 playing a pivotal role in the present invention will be described with reference to Fig. 2. Assume that the output voltage supplied by the ac voltage source 7 assumes the same waveform as the voltage Vsa until the time instant t1 and changes the waveform into that of the voltage Vsb instantaneously. At this time, the switching element 17a in the input voltage control circuit 17 is turned on with the switching signal T17a synchronous with the polarity signal for inverter output voltage and the switching element 17b therein is turned off with the switching signal T17b. The output voltage Vsc of the input voltage control circuit 17 assumes the same waveform as the voltage Vsa until the time instant t1. After the time instant t1, when the voltage Vsb is negative, the output voltage Vsc is zero voltage. At a time instant t2, the logical states of the switching elements 17a and 17b are changed over. When the output voltage Vsb of the ac voltage source 7 is positive, the voltage Vsc is zero voltage. Due to the foregoing operation of the input voltage control circuit 17, a voltage that is opposite in polarity to the inverter output voltage is fed to the converter D serving as the first switch. This solves a problem lying in prior arts or avoids a phenomenon that a switching element is turned off due to continuous overcurrent and thus an inverter stops outputting voltage. If an output of a phase-locked loop, which is not shown, in the inverter C serving as the third switch tracks in phase the output voltage Vsb of the ac voltage source 7 at a slow pace acceptable to a load, the output voltage Vsc of the input voltage control circuit 17 would have a perfect sine wave. Furthermore, the input voltage of the converter D is controllable, making it possible to control dc voltage within a range defined with values smaller than a wave height of the voltage Vs supplied by the ac voltage source 7. Second Embodiment Next, the second embodiment of the present invention will be described in conjunction with the drawings. In Fig. 3, E denotes a converter serving as the first switch. The converter E is made by connecting switching elements le and 2e for controlling unidirectional switching; such as, thyristors in series with each other. When the inverter output voltage V INV is positive, the switching element le is on. When the inverter output voltage V INV is negative, the switching element le is off. The switching element 2e acts in contrast with the switching element le. 3 to 16 and 30 denote the same circuit elements as those in prior arts. Figs. 4a and 4b are explanatory diagrams for the second embodiment, showing the operation performed when the output voltage of the ac voltage source 7 abruptly fluctuates in phase to have the opposite polarity. Fig. 4a shows current flowing through the converter E when the output voltage of the ac voltage source 7 and inverter output voltage V INV are phased positively. The switching elements 1e, 4t, and 5t are on, whereby current flows into the loading circuit 14 through the capacitor 12 or switching element 5t via the reactor 15 in the converter E. Immediately after the converter E is placed in the state shown in Fig. 4a, if the voltage supplied by the ac voltage source 7 is reversed in polarity, the converter E enters the state shown in Fig. 4b. In Fig. 4b, the same switching elements as those in Fig. 4a are on. In the converter E, current therefore flows through the switching element 4t and attempts to flow into the switching element 2e. However, since the switching element 2e is off, the current does not flow through the switching element 2e. When the voltage Vs supplied by the ac voltage source 7 and the inverter output voltage V INV are not mutually consistent in polarity, no converter current flows. Therefore, even if the input voltage Vs fluctuates in phase, no problem occurs. The capacitor 12 is no longer charged with the peak-to-peak value of the output voltage of the ac voltage source 7, whereby dc voltage can be controlled to be any value starting with zero. Third Embodiment Next, the third embodiment of the present invention will be described in conjunction with the drawings. In Fig. 5, F denotes a converter serving as the first switch. The converter F consists of bidirectional control circuits 1 and 2. The bidirectional control circuit 1 is made by connecting a switching circuit composed of a switching element 1ta that is a transistor, an IGBT, or an FET, and a flywheel diode 1da, and a switching circuit composed of a switching element 1tb that is a transistor, an IG3T, or an FET, and a flywheel diode 1db, in series with each other but in the opposite directions. Similarly to the switching circuit 1, the bidirectional control circuit 2 is made by connecting switching elements 2ta and 2tb and flywheel diodes 2da and 2db. The other circuit elements and connections are identical to those in prior arts. The operation will be described in conjunction with Figs. 6a and 6b. Fig. 6a shows current flowing through the converter F when the output voltage of the ac voltage source 7 and the inverter output voltage V INV are phased positively. In Fig. 6a, two switching elements in each of the bidirectional control circuits 1 and 2 in the converter F always operates according to the same switching pattern. The switching pattern is identical to that in the second prior art. That is to say, current flows through the switching element 1tb and diode 1da in the switching circuit 1 and through the diode 4d in the switching circuit 4, and then charges the capacitor 12. At this time, as shown in Fig, 6b, if the voltage supplied by the ac voltage source 7 is reversed in polarity, since the switching element 4t is on, current attempts to flow through the switching element 4t and diode 2da. However, since the converter F controls bidirectional switching, when the switching element 2tb is off, the current is cut off. Even when the output voltage of the ac voltage source 7 fluctuates, a short circuit shunting the reactor 15 will not occur. Furthermore, since bidirectional switching can be controlled, power for producing dc voltage can be regenerated by the ac voltage source in a normal control mode. Even for a load that regenerates energy of a motor or the like, dc voltage can be held constant. The aforesaid embodiments 1 to 3 utilize the actions and characteristics of switching elements in order to prevent abrupt reverse in polarity of input voltage, thus solving problems caused by the abrupt change in phase of voltage supplied by the ac voltage source 7. Fourth Embodiment Next, the fourth embodiment will be described in conjunction with the drawings. Fig. 7 is a block diagram showing a configuration of a power inverting apparatus of the fourth embodiment. In Fig. 7, the reference numerals identical to those in Fig. 1 denote the same circuit elements as those in the first embodiment. The description of the circuit elements will be omitted. 240 denotes a voltage detecting means for detecting a voltage V SW across the input voltage control circuit 17 serving as a bidirectional switching circuit. 242 denotes a current detecting means for detecting an input current I R to be fed from the ac voltage source 7 to the converter D. 304 denotes an error detector for detecting that the input current has grown to be overcurrent. After the inverter and converter are suspended, the error detector 304 analyzes the voltage V SW across the input voltage control circuit 17 detected by the voltage detecting means 240 and then determines conditions under which the inverter and converter can be restarted. 223 denotes a gate circuit. Fig. 8 shows an example of a configuration of the error detector 304 and gate circuit 223. In Fig. 8, 300 denotes an absolute value circuit for identifying an absolute value of the input current I R . 301 denotes a comparator that when an output signal I RA of the absolute value circuit exceeds a value I R_ 1mt of overcurrent, outputs a high-level output signal 300_out. 302 denotes a comparator that when the voltage V SW across the input voltage control circuit 17 exceeds a reference voltage V_1mt of given level, outputs a high-level output signal 302_out. 303 denotes a D flip-flop. 212 to 219 denote AND circuits for blocking gates. Next, the operation will be described with reference to the waveforms representing the actions of circuit elements shown in Fig. 9. In Fig. 7, the input current I R to be fed from the ac voltage source 7 to the converter D is detected by the current detecting means 242, fed to the error detector 304, processed to calculate an absolute value through the absolute value circuit 300 in the error detector 304, and then fed to the comparator 301. At a time instant t1 in Fig. 9, the output 300_out of the absolute value circuit 300 exceeds the value I R_ 1mt of overcurrent. The output signal 301_out of the comparator 301 then goes high. The D flip-flop 303 changes states from the state defined with a low-level signal to the one defined with a high-level signal. This causes the output signal ERR_L of the D flip-flop 303 to go low. All the output signals T1' to T6', T17a', and T17b' of the AND circuits 212 to 219 are driven low. Consequently, gate blocking is effected. Next, at a time instant t2, the voltage V SW across the input voltage control circuit 17 detected by the voltage detecting means 240 exceeds the reference voltage V_1mt set for the comparator 302. The output signal 302_out of the comparator 302 then goes low. The output signal ERR_L of the D flip-flop 303 is driven high forcibly. The gate blocking is then released. When the gate blocking is released, the input voltage control circuit 17 restarts switching. The voltage across the input voltage control circuit 17 becomes zero. The output signal 302_out of the comparator 302 goes high. A normal control mode is re-set. According to the fourth embodiment, when it is detected that the input current I R to be fed from the ac voltage source 7 to the converter D has grown to be overcurrent, all switching commands can be specified to turn off the switching elements in the inverter C and converter D as well as the switching elements in the input voltage control circuit 17. The input current I R therefore charges the smoothing capacitor 12 to be zero, which prevents occurrence of a drawback resulting from excessive input current. After the abnormal state that excessive input current flows is avoided, the converter and inverter are restarted. This results in stable power inversion. Fifth Embodiment Next, the fifth embodiment will be described in conjunction with the drawings. Fig. 10 is a block diagram showing a configuration of a power inverting apparatus of the fifth embodiment. In Fig. 10, a circuit element different from the one in the fourth embodiment shown in Fig. 7 is the error detector 305 in the control circuit 30. The error detector 305 detects that the input current detected by the current detecting means 242 has grown to be overcurrent. After the inverter and converter are suspended, the error detector 305 analyzes the input current I R detected by the current detecting means 242 and then determines conditions under which the inverter and converter can be restarted. The other circuit elements are identical to those in the fourth embodiment, of which description will be omitted. Fig. 11 shows a circuitry of the error detector 305. In Fig. 11, 306 denotes a comparator that when the output signal 300_out of the absolute value circuit 300 for detecting an absolute value of the input current I R becomes zero. provides a low-level output signal 306_out. The other circuit elements of the error detector 305 are identical to those in the fourth embodiment shown in Fig. 8, of which description will therefore be omitted. Next, the operation will be described with reference tu the waveforms representing the actions of circuit elements in Fig. 12. In Fig. 10, the input current I R to be fed from the ac voltage source 7 to the converter D is detected by the current detecting means 242, fed to the error detector 305. processed to calculate an absolute value by means of the absolute value circuit 300 in the error detector 305, and then fed to the comparator 301. At the time instant t1 in Fig. 12, the output signal 300_out of the absolute value circuit 300 exceeds the value I R_ 1mt of overcurrent. The output signal 301_out of the comparator 301 then goes high. The D flip-flop 303 changes states from the state defined with a low level to the one defined with a high level. This causes the output signal ERR_L of the D flip-flop 303 to go low. Similarly to the fourth embodiment, the output signal ERR_L causes all the output signals of the gate circuit 223 to go low. Thus, gate blocking is effected. Next, at the time instant t2, the input current I R reaches zero. The output signal 306_out of the comparator 306 then goes low. The output signal ERR_L of the D flip-flop 303 is driven high forcibly. The gate blocking is then released. When the gate blocking is released, the input voltage control circuit 17 restarts switching. The output signal 306_out of the comparator 306 is then driven high. A normal control mode is then re-set. According to the fifth embodiment, when it is detected that the input current I R to be fed from the ac voltage source 7 to the converter D has grown to be overcurrent, switching commands are specified to turn off all the switching elements in the inverter C and converter D as well as those in the input voltage control circuit 17. The input current I R charges the smoothing capacitor 12 to be zero, which prevents occurrence of a drawback resulting from excessive input current. Once the abnormal state that excessive input current flows is avoided, the converter and inverter are restarted. This results in stable power inversion. Furthermore, since the switching elements in the input voltage control circuit 17 are turned off according to the input current I R . even if the switching elements are, for example, thyristors incapable of suppressing arcing by themselves, the switching elements can be turned off reliably. Unlike the fourth embodiment, the voltage detecting means for detecting the voltage across the input voltage control unit 17 is unnecessary. This results in a low-cost power inverting apparatus. Sixth Embodiment Next, the sixth embodiment will be described in conjunction with the drawings. In the aforesaid fourth or fifth embodiment, when the error detector 304 or 305 detects that the input current I R flowing from the ac voltage source 7 into the converter D has grown to be overcurrent, the gate circuit 223 is controlled to provide commands specifying that all switching elements should be turned off. In Fig. 13, assume that the input voltage supplied by the ac voltage source 7 is of negative polarity and the output voltage command of the inverter C is of positive polarity. Also assume that an output current I L of the inverter C is flowing in the arrow direction in Fig. 13. In this situation, when the error detector operates to detect an abnormal state, gate blocking is effected. The output current IL flows along the route indicated with a dashed line in Fig. 13. Specifically, the output current I L flows along a line LINE_COM, through a diode 3d, a point P, the smoothing capacitor 12, a point N, and a diode 6d, and then along a line LINE_I. The input current I R flow along the line LINE_COM, and through the diode 3d, point P, smoothing capacitor 12, point N, diode 2d, and reactor 15. In the meantime, the input current I R charges the smoothing capacitor to decay. The voltage at the point P is induced in the line LINE_COM and the voltage at the point N is induced in the line LINE_I. The voltage V L induced in an output terminal of the inverter C is dc voltage of negative polarity. However, since the output voltage command destined for the inverter C is of positive polarity. The output voltage V L is therefore opposite in polarity to the output voltage command. Eventually, the voltage to be applied to a load may become negative. Thus, the influence of the output voltage V L upon the load is not negligible. To alleviate the above influence, as shown in Fig. 14, switching elements 3t and 5t are turned on so that the inverter C provides a zero output. The output current I L is circulated as shown in Fig. 14. Specifically. the output current I L flows along the line LINE_COM, through the diode 3d, switching element 5t, and then along the line LINE_I. The input current I R flows along the line LINE_COM, through the diode 3d, point P, smoothing capacitor 12, point N, and diode 2d, into the reactor 15. In the meantime, the input current I R charges the smoothing capacitor to decay. For allowing the inverter C to provide a zero output, as shown in Fig. 15, switching elements 4t and 6t may be turned on. In this case, the input current I R follows a dashed line in Fig. 15; that is, flows along the line LINE_COM, through the switching element 4t, point N, and diode 2d. into the reactor 15. The input current I R glows further. Consequently, the inverter C is not allowed to provide a zero output. When the input current I R is reversed in polarity, the switching elements 4t and 6t are turned on so that the output voltage of the inverter C will be zero. The subsequent actions of circuit elements are the same as those described above, of which description will be omitted. Fig. 16 is a block diagram showing a configuration of a power inverting apparatus of the sixth embodiment. In Fig. 16, the reference numerals identical to those in Fig. 10 denote the same circuit elements as those in the sixth embodiment. 247 denotes a gate circuit with a built-in polarity detector residing in the control circuit 30. 1 to 17, 100 to 106. 242. 305. and B to D denote the same circuit elements as those in the fifth embodiment, of which description will therefore be omitted. Fig. 17 shows a circuitry of the gate circuit 247. 248 denotes a polarity detector for detecting the polarity of the input current IR. 249 and 250 denote NOT circuits. 251 and 252 denote AND circuits serving as selectors. 253 to 260 denote AND circuits serving as gate blocking circuits. 261 to 264 denote OR circuits. Fig. 18 shows the waveforms of, from above to below, the input current I R , Error Detected signal ERR_L, output signal I R_ pole of the polarity detector 248. output signal 249_out of the NOT circuit 249, output signal 250_out of the NOT circuit 250, output signal 251_out of the AND circuit 251, output signal 252_out of the AND circuit 252, and gate signals T3' to T6'. Next, the operation will be described. When it is detected that the input current has grown to be overcurrent, the Error Detected sinal ERR_L goes low at the time instant t1. This causes the AND circuits 253 to 260 to provide low-level gate signals. The output signal 250_out of the NOT circuit 250 goes from low to high. Since the polarity signal I R_ pole for the input current I R is high. the output signal 251_out of the AND circuit 251 goes high. Since the output signal 249_out of the NOT circuit 249 is low, the output signal 252_out of the AND circuit 252 goes low. Since the output signal 251_out is high, the output signal T3' of the OR circuit 261 and the output signal T5' of the OR circuit 263 are driven high forcibly. The output signal T4' of the OR circuit 262 and the output signal T6' of the OR circuit 264 are fixed to zero. According to the sixth embodiment, the input current does not grow but charges the smoothing capacitor 12 to decay. Since the output voltage of the inverter C is zero, no negative voltage is applied to the output voltage of the inverter C. Thus, the influence of the output voltage upon a load is alleviated. Seventh Embodiment Next, the seventh embodiment will be described in conjunction with the drawings. In Fig. 19, 329 denotes a polarity detector for detecting the polarities of an output voltage of the ac voltage source 7 and of an inverter output voltage command. 330 denotes an error detector for detecting an error by analyzing two polarity signals provided by the polarity detector 329. 1 to 17, 30, 100 to 106, 223, and B to D denote the same circuit elements as those in the fourth embodiment. 220 denotes exactly the same circuitry as that in the fifth embodiment, of which description will be omitted. Fig. 20 shows an example of circuitries of the polarity detector 329 and error detector 330. In Fig. 20, 322 denotes a polarity detector for detecting the polarity of the input voltage V R . 323 denotes a polarity detector for detecting the polarity of the output voltage command V CMD2 destined for the inverter C. 324 denotes an exclusive-OR circuit for checking if the output signals 322_out and 323_out of the two polarity detectors are mutually consistent in polarity. 325 denotes a leading edge detector for detecting a leading edge of the output signal 324_out of the OR circuit 324. 326 denotes a trailing edge detector for detecting a trailing edge of the output signal 325_out of the trailing edge detector 325. 327 denotes a NOT circuit. 328 denotes a D flip-flop. Fig. 21 shows the waveforms of, from above to below, the output voltage command V CMD2 destined for the inverter C, voltage V R supplied by the ac voltage source. input current I R flowing from the ac voltage source into the converter, output signal 323_out of the polarity detector 323, output signal 322_out of the polarity detector 322, output signal 324_out of the exclusive-OR circuit 324, output signal 325_out, output signal 326_out of the trailing edge detector 326, output signal 327_out of the NOT circuit 327, and output signal ERR_L of the D flip-flop 328. Next, the operation will be described. At the time instant t1, an error occurs in the voltage V R of the ac voltage source 7. At the time instant t2, the exclusive-OR circuit 324 analyzes the signal 323_out representing the polarity of the output voltage command V CMD2 destined for the inverter C and the signal 322_out representing the polarity of the voltage supplied by the ac voltage source 7, and thus detects that the polarities are mutually inconsistent. The output signal 324_out goes high. At this time, the D flip-flop 328 changes states from the state defined with a low level to the one defined with a high level. This causes the output signal ERR_L of the D flip-flop 328 to go low. The signal ERR_L is then fed to the gate circuit 223, whereby gate blocking is effected. The signal 324_out is fed to the leading edge detector 325. The signal 325_out remains high from a time instant t3 until a given time instant t4 for a period of time required for the input current I R to be zero. At the time instant t4, the signal 325_out goes low. The trailing edge detector 326 detects the trailing edge of the signal 325_out. The signal 326_out remains high until a time instant t5. The output signal 327_out of the NOT circuit 327 is then driven low, and the D flip-flop is reset forcibly. The output signal ERR_L is driven high again, whereby gate blocking is released. The inverter and converter are restarted. According to the foregoing operation, gate blocking is effected to suspend the inverter and converter for at least a period of time during which the input current flowing from the ac voltage source 7 reaches zero. Therefore, when the polarities of the voltage supplied by the ac voltage source 7 and output voltage command destined for the inverter C are mutually inconsistent, even if the input current is present, the input voltage control circuit 17 can be turned off. The input current therefore charges the capacitor 12 to be zero but does not grow to be overcurrent. which prevents occurrence of a drawback resulting from excessive input current. Furthermore, since the inverter and converter are restarted, stable power inversion is realized. Eighth Embodiment Next, the eighth embodiment will be described in conjunction with the drawings. In Fig. 22, 332 denotes an error detector for detecting an error by analyzing two polarity signals or outputs of the polarity detector 329. 1 to 17, 30, 100 to 106, 223, 242, 329, and B to D denote the same circuit elements as those in the seventh embodiment, of which description will therefore be omitted. Fig. 23 shows an example of a circuitry of the error detector 332. Reference numeral 324 denotes an exclusive-OR circuit for determining whether the polarities of the output signals 322_out and 323_out of the polarity detector 329 are mutually consistent. 300 denotes an absolute value circuit for detecting an absolute value of the input current I R . 306 denotes a comparator for comparing the output of the absolute value circuit 300 with a zero level I0_lmt. 331 denotes a D flip-flop. Fig. 24 shows the waveforms of, from above to below, the output voltage command V CMD2 destined for the inverter C, voltage V R supplied by the ac voltage source 7. input current I R , output signal 323_out of the polarity detector 323, output signal 322_out of the polarity detector 322, output signal 324_out of the exclusive-OR circuit 324, output 300_out of the absolute value circuit 300, output signal 306_out of the comparator 306, and output signal ERR_L of the D flip-flop 331. Next, the operation will be described. At the time instant t1, an error occurs in the voltage V R supplied by the ac voltage source 7 as shown in Fig. 24. At the time instant t2, the exclusive-OR circuit 324 analyzes the signal 323_out representing the polarity of the output voltage command V CMD2 destined for the inverter C and the signal 322_out representing the polarity of the voltage supplied by the ac voltage source, and thus detects that the polarities are mutually inconsistent. the output signal 324_out is then driven high. At this time, the D flip-flop 331 changes states from the state defined with a low level to the one defined with a high level. This causes the output signal ERR_L of the D flip-flop 331 to go low. The output signal ERR_L is then fed to the gate circuit 223, whereby gate blocking is effected. At the time instant t3, the input current I R becomes zero. This causes the output signal 306_out of the comparator 306 to go low. The output signal ERR_L of the D flip-flop 331 is driven high forcibly. The gate blocking is released. The inverter and converter are restarted. According to the foregoing operation, gate blocking is performed to suspend the inverter and converter, so that even when the polarities of the voltage supplied by the ac voltage source 7 and inverter output voltage command signal are mutually inconsistent, even if the input current flowing from the ac voltage source is present, the input voltage control circuit 17 can be turned off. The input current therefore charges the capacitor to be zero but does not grow to be overcurrent, which prevents occurrence of a drawback resulting from excessive input current. Furthermore, the inverter and converter are restarted as soon as it has actually been confirmed that the input current is zero. Therefore, even if excessive input current flows, the stop time of the inverter and converter can be minimized. This results in stable power inversion. Ninth Embodiment Next, the ninth embodiment will be described in conjunction with the drawings. In Fig. 25, 226 denotes a polarity detector for detecting the polarity of the voltage V R supplied by the ac voltage source 7 and the polarity of the output voltage command V CMD2 destined for the inverter C. 225 denotes a polarity reverse detector for determining whether the polarity of the output voltage command V CMD2 destined for the inverter C is reversed. 224 denotes an error detector that analyzes the output signal of the polarity reverse detector 225 and thus determines that the polarity of the voltage V R is abnormal according to the timing that the polarity of the the output voltage command V CMD2 destined for the inverter C is reversed. 1 to 17, 30, 100 to 106, 223, 242, and B to D denote the same circuit elements as those in the seventh embodiment, of which description will therefore be omitted. Fig. 26 shows an example of circuitries of the error detector 224, polarity reverse detector 225, and polarity detector 226. In Fig. 26, 227 denotes a polarity detector for detecting the polarity of the output voltage command V CMD2 destined for the inverter C. 228 denotes a polarity detector for detecting the polarity of the voltage V R supplied by the ac voltage source 7. 229 denotes a leading edge detector. 230 denotes a trailing edge detector. 231 denotes a NOT circuit. 232 and 233 denote AND circuits serving as selectors. 234 denotes an OR circuit. 235 denotes a D flip-flop for outputting an Input Error Detected signal ERR_L. 300 and 306 denote the same circuit elements as those in the eighth embodiment, of which description will therefore be omitted. Fig. 27 shows the waveforms of, from above to below, the output voltage command V CMD2 destined for the inverter C, voltage V R supplied by the ac voltage source 7, input current I R , output signal V CMD2_ pole of the polarity detector 227, output signal V R_ pole of the polarity detector 228, output signal 229_out of the leading edge detector 229, output signal 230_out of the trailing edge detector 230, output signal 231_out of the NOT circuit 231, output signal 232_out of the AND circuit 232, output signal 233_out of the AND circuit 233, output signal 234_out of the OR circuit, output signal 300_out of the absolute value circuit 300, output signal 306_out of the comparator 306, and output signal ERR_L of the D flip-flop 235. Next, the operation will be described. At the time instant t1, the voltage V R supplied by the ac voltage source 7 fluctuates as shown in Fig. 27. At the time instant t2, the output voltage command V CMD2 destined for the inverter C is reversed from positive polarity to negative polarity. This causes the output signal V CMD2_ pole to go from low to high. The output signal 229_out of the leading edge detector 229 is driven high for a given period of time from the time instant t2 to t3. Since the signal V R_ pole is low, the output signal 231_out of the NOT circuit 231 is high. The output signal 232_out of the AND circuit 232 is driven high at the time instant t2. The output signal 233 out remains low. When the output signal 232_out is driven high, the output signal 234_out of the OR circuit 234 goes from low to high. A rise signal is then fed to the D flip-flop 235. With the rise signal, the output signal ERR_L of the D flip-flop 235 goes from high to low. When the output signal ERR_L goes low, occurrence of an error is detected. The output signal ERR_L of low level is fed to the gate circuit 232, whereby gate blocking is effected. At the time instant t4. the input current I R becomes zero. The output signal 306_out of the comparator 306 goes low. The output signal ERR_L of the D flip-flop 235 is driven high forcibly. The gate blocking is released. The inverter and converter are restarted. According to the foregoing operation, gate blocking is effected to suspend the inverter and converter, so that every time the output voltage command destined for the inverter C is reversed in polarity, error detection can be performed and the input voltage control circuit 17 can be turned off. Herein, when the output voltage command destined for the inverter C is reversed in polarity, the polarities of the voltage supplied by the ac voltage source 7 and output voltage command destined for the inverter C are mutually inconsistent and the switching elements in the input voltage control circuit 17 are disabled from cutting off the input voltage VR of opposite polarity, The input current therefore charges the smoothing capacitor 12 to be zero but does not grow to be overcurrent. A drawback resulting from excessive input current can therefore be avoided. Furthermore, the inverter and converter are restarted as soon as it has actually been confirmed that the input current is zero. Therefore. even if excessive input current flows, the stop time of the inverter and converter can be minimized. This results in stable power inversion. Tenth Embodiment Next, the tenth embodiment will be described. In Fig. 28, 347 denotes an error detector for detecting an error by analyzing input current flowing from the ac voltage source 7 to the converter and an input current command I R* . 1 to 17, 100 to 106, 223, and B to D denote the same circuit elements as those in the fourth embodiment, of which description will be omitted. Fig. 29 shows an example of a circuitry of the error detector 347. In Fig. 29, 345 denotes a current difference detector for detecting a difference between the input current I R and input current command I R* . 346 denotes a D flip-flop for outputting an Error Detected signal ERR_L. 300 and 306 denote the same circuit elements as those in the eighth embodiment shown in Fig. 23, of which description will be omitted. Fig. 30 shows the waveforms of, from above to below, the input current I R and input current command I R* , output signal 345_out of the current difference detector 345, output signal 300_out of the absolute value circuit 300, output signal 306_out of the comparator 306, and output signal ERR_L of the D flip-flop 346. Next, the operation will be described. When the difference between the input current I R and input current command I R* exceeds a given value, the output signal 345_out of the current difference detector 345 goes from low to high. A rise signal or a signal that goes from low to high is fed to the D flip-flop 346. This causes the output signal ERR_L to go from high to low. The gate circuit 223 effects gate blocking. At the time instant t2, the input current I R becomes zero. The output signal 306_out of the comparator 306 then goes low. The output signal ERR_L of the D flip-flop 346 is driven high forcibly. The gate blocking is then released. The inverter and converter are restarted. According to the foregoing operation, gate blocking is effected to suspend the inverter and converter, so that when the difference between the input current I R and the input current command I R* exceeds the given value, the current difference detector 345 can detect occurrence of an error, and the input voltage control circuit 17 can be turned off. The input current I R therefore charges the smoothing capacitor to be zero but does not grow to be overcurrent, which prevents occurrence of a drawback resulting from excessive input current. Furthermore, the inverter and converter are restarted as soon as it has actually been confirmed that the input current is zero. Therefore, even if excessive input current flows, the stop time of the inverter and converter can be minimized. Moreover, since a voltage detector is unnecessary, stable power inversion can be realized at low cost. Eleventh Embodiment Next, the eleventh embodiment will be described in conjunction with the drawings. In the configuration of the first embodiment shown in Fig. 1, on the assumption that the converter is controlled with a high power factor, a current command issued by the converter voltage command generator 100 shall be, as shown in Fig. 31, a signal having a sine wave phased with the voltage supplied by the ac voltage source 7. In part of controlling the input current I R , the current command signal is set to zero around the time instant when the input current originating from the ac voltage source have a zero crossing. Around the time instant when the switching elements 17a and 17b in the input voltage control circuit 17 are turned on or off, the currents flowing through the switching elements 17a and 17b reach zero without fail. The switching elements 17a and 17b can therefore be turned on or off as specified in a command. Even if an error occurs in the input voltage V R supplied by the ac voltage source 7, the input voltage V R can be cut off reliably. Stable power supply can be realized all the time. When thyristors that cannot suppress arcing by themselves are employed for the input voltage control circuit 17, the input voltage supplied by the ac voltage source 7 may fluctuate abruptly. In this case, the input voltage is opposite in polarity to the inverter output voltage command. If a thyristor cannot be turned off as specified in the command but remains on, the input current originating from the ac voltage source grows abruptly. This results in a broken circuit element. However, once the current command is set to zero around the time instant when the input current has a zero crossing, the currents flowing through the switching elements 17a and 17b in the input voltage control circuit 17 reach zero without fail around the time instant when the switching elements 17a and 17b are turned on or off. Thus, the above drawback can be overcome. Twelfth Embodiment Next, the twelfth embodiment will be described. A power inverting apparatus of the twenty-second embodiment has the same configuration as that shown in Fig. 22. When the voltage difference error predictor detector 349 detects an error in the voltage supplied by the ac voltage source, the output signal PRE_ERR of the voltage difference error predictor detector 349 becomes active, and then enters the converter voltage command generator 100. When the signal PRE_ERR is fed to the converter voltage command generator 100, the converter voltage command generator steps up the dc voltage command destined for the capacitor 12 to boost the dc voltage at the capacitor 12 by the given value γ. At this time, the operating domains of the inverter and converter expand by a hatched area in Fig. 32. The operable range of the power inverting apparatus becomes larger accordingly. Only when an error occurs in input voltage, the voltage at the smoothing capacitor 12 can be boosted without causing the inverter and converter to stop. An increase in power dissipation caused by switching in the inverter and converter can therefore be restricted to an event of an input voltage error. Furthermore, since a simple circuitry will do, stable power supply can be realized at low cost. In the aforesaid first to twelfth embodiments, each switching element is formed with a single thyristor. Depending on the current and voltage ratings for a power inverting apparatus, a plurality of thyristors may be connected in parallel or series with one another. The number of switching circuits constituting each switch and being connected in series with one another may be set to any value. An expression described in claims in this specification, for example, "a second switch having the same circuit elements as a first switch" does not necessarily stipulate that the number of switching elements or switching circuits connected in series with one another is the same between the first and second switches.

Claims: A power inverting apparatus, comprising: a converter means (D) for changing AC voltage supplied by an AC voltage source into DC voltage; an inverter means (C) for changing DC voltage provided by said converter means into AC voltage, said inverter means (C) comprising a pair of PWM controlled switches connected in series with each other; a selector (B) for selecting the output polarity of said inverter means (C), said selector (B) being connected in parallel with said converter means (D) and comprising a pair of series connected switches (3, 4) and having a middle point adapted to be connected to a terminal of the AC voltage source (7); an input voltage control means (30); characterized in that said input voltage control means (30) is adapted to cut off AC voltage to be supplied to said converter means (D) when the polarity of the AC voltage supplied by said AC voltage source (7) differs from the polarity of said AC voltage provided by said inverter means. A power inverting apparatus according to claim 1, wherein said input voltage control means (30), said converter means (D), and said inverter means (C) include: a bidirectional switching circuit connected between one terminal of said AC voltage source (7) and said converter means (D); a converter consisting of first and second switching circuits (1, 2) connected in series with each other and having a junction between said first and second switching circuits connected to an output terminal of said input voltage control means (30); a smoothing capacitor (12) connected in series with said converter (D); said selector (B) consisting of third and fourth switching circuits (3, 4) ... connected in series with each other, and having a junction between said third and fourth switching circuits connected to the other terminal of said ac voltage source (7); an inverter (C) being connected in parallel with said converter (D), and consisting of fifth and sixth switching circuits (5, 6) connected in series with each other; a converter voltage command generator (100) for generating a converter voltage command representing an output voltage of said converter; an inverter voltage command generator (102) for generating an inverter voltage command representing an output voltage of said inverter; and a switching control circuit (106) for turning on or off said bidirectional switching circuit and said first to sixth switching circuits on the basis of a converter voltage command and an inverter voltage command according to given timing. A power inverting apparatus according to claim 2, wherein said bidirectional switching circuit includes a pair of unidirectional switching elements connected in parallel with each other but in the opposite directions. A power inverting apparatus according to claim 2, wherein each of said first to sixth switching circuits (1-6) includes a unidirectional switching element and a diode that are connected in parallel with each other but in the opposite directions. A power inverting apparatus according to claim 1, further comprising a reactor (12) connected between said input voltage control means and said converter means. A power inverting apparatus according to claim 2, further comprising: a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; an error recognizing means (304, 305) that when an input current detected by said current detecting means (242) exceeds a given value, recognizes occurrence of an error; and an error control means (247) that when said error recognizing means recognizes occurrence of an error, stops said switching control circuit to turn off said bidirectional switching circuit and said first to sixth switching circuits. A power inverting apparatus according to claim 6. wherein after said switching control circuit is stopped, when an input current detected by said current detecting means becomes zero, said error control means re-actuates said switching control circuit. A power inverting apparatus according to claim 6, further comprising a voltage detecting means (240) for detecting a voltage across said bidirectional switching circuit (17), wherein: after said switching control circuit (106) is stopped, when said voltage detecting means (240) detects that voltage has been developed across said bidirectional switching circuit (17), said error control means (304, 305) re-actuates said switching control circuit (106). A power inverting apparatus according to claim 2, further comprising: a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; an error recognizing means (304, 305) that when an input current detected by said current detecting means exceeds a given value, recognizes occurrence of an error; and an error control means (223) that when said error recognizing means recognizes occurrence of an error, turns off said bidirectional switching circuit (17), allows said fifth and sixth switching circuits to perform switching according to a switching pattern for preventing an input current detected by said current detecting means from growing, so that an output voltage of said inverter will be zero, and turns off said first and second switching circuits to suspend said converter, and that when said current detecting means (242) detects that a detected input current is zero, actuates said switching control circuit (106) normally. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source; a polarity detecting means (329) for detecting the polarities of voltage supplied by said ac voltage source (7) and of output voltage of said inverter; and an error control means (223) that when the polarities detected by said polarity detecting means are mutually inconsistent, controls said switching control circuit (106) so that said converter and said inverter will be suspended. A power inverting apparatus according to claim 10, wherein said error control means (223) controls said switching control circuit so that after said converter and said inverter are suspended, when a given period of time elapses, said converter and said inverter will be restarted. A power inverting apparatus according to claim 10, further comprising a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter, wherein: said error control means (223) controls said switching control circuit so that after said converter and said inverter are suspended, when it is detected that an input current detected by said current detecting means is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source; a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; a polarity detecting means (226) for detecting the polarities of voltage supplied by said ac voltage source (7) and of output voltage of said inverter: and an error control means (223) for controlling said switching control circuit so that when the polarities detected by said polarity detecting means are mutually inconsistent around the time instant when the polarity of output voltage of said inverter detected by said polarity detecting means is reversed, said converter and said inverter will be suspended, and so that when it is detected that an input current detected by said current detecting means (242) is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source (7); a current detecting means (242) for detecting an input current flowing from said ac voltage source (7) into said converter; a voltage difference detecting means (329) for detecting a difference between a voltage detected by said voltage detecting means (220) and an inverter voltage command generated by said inverter voltage command generator; and an error control means (223) for controlling said switching control circuit so that when a voltage difference detected by said voltage difference detecting means (329) is larger than a converter voltage command generated by said converter voltage command circuit, said converter and said inverter will be suspended, and that when it is detected that an input current detected by said current detecting means is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied at said ac voltage source; a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; a voltage difference detecting means (226, 329) for detecting a difference between a voltage detected by said voltage detecting means and an inverter voltage command (V CMD2 ) generated by said inverter voltage command generator (102); a polarity detecting means for detecting the polarities of voltage supplied by said ac voltage source (7) and of input current flowing from said ac voltage source (7) into said converter; and an error control means (223) for controlling said switching control circuit so that when a voltage difference detected by said voltage difference detecting means is larger than a converter voltage command generated by said converter voltage command generator, if the polarity of voltage supplied by said ac voltage source, which is detected by said polarity detecting means, is consistent with the one of input current flowing from said ac voltage source (7) to said converter, said converter and said inverter will be suspended, and so that when it is detected that an input current detected by said current detecting means (242) is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source; a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; a voltage difference detecting means (226, 329) for detecting a difference between a voltage detected by said voltage detecting means (220) and an inverter voltage command (V CMD2 ) generated by said inverter voltage command generator (102); a polarity detecting means for detecting the polarities of voltage supplied by said ac voltage source and of input current flowing from said ac voltage source into said converter; and an error control means (223) for controlling said switching control circuit so that when a voltage difference detected by said voltage difference detecting means is larger than a converter voltage command generated by said converter voltage command generator, if the polarity of voltage supplied by said ac voltage source (7), which is detected by said polarity detecting means, is consistent with the one of input current flowing from said ac voltage source (7) into said converter, and if an input current flowing into said converter exceeds a given value, said converter and said inverter will be suspended, and so that when it is detected that an input current detected by said current detecting means (242) is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: an input current command generator (100) for outputting a command (I R* ) representing an input current flowing from said ac voltage source (7) into said converter (D); a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; a current difference detecting means (347) for detecting a difference between an input current detected by said current detecting means and an input current command generated by said input current command generator; and an error control means (223) for controlling said switching control circuit so that when a current difference detected by said current difference detecting means (347) exceeds a given value, said converter and said inverter will be suspended, and so that when it is detected that an input current detected by said current detecting means is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source; a current detecting means (242) for detecting an input current flowing from said ac voltage source into said converter; a phase difference detecting means for detecting a phase difference between a voltage detected by said voltage detecting means and an inverter voltage command generated by said inverter voltage command generator; and an error control means (223) for controlling said switching control circuit (106) so that when a phase difference detected by said phase difference detecting means exceeds a given value, said converter and said inverter will be suspended, and so that when it is detected that an input current detected by said current detecting means (242) is zero, said converter and said inverter will be restarted. A power inverting apparatus according to claim 2, further comprising: an input current command generator (100) for outputting a command (I R *) representing an input current flowing from said ac voltage source (7) into said converter; and a control means that when the logical states of said bidirectional switching circuit are changed over, sets an input current command provided by said input current command generator to zero. A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source (7); an input current command generator (100) for outputting a command (I R* ) representing an input current flowing from said ac voltage source (7) into said converter; a voltage difference detecting means (226, 329) for detecting a difference between a voltage detected by said voltage detecting means (220) and an inverter voltage command (V CMD2 ) generated by said inverter voltage command generator (102); and an error control means (223) that when an absolute value of a voltage difference detected by said voltage difference detecting means is smaller by a given value than a converter voltage command generated by said converter voltage command generator, sets an input current command provided by said input current command generator to zero. A power inverting apparatus according to claim 2, further comprising: a chopper (B) connected in parallel with said smoothing capacitor (12); a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source; an input current command generator (100) for outputting a command (I R* ) representing an input current flowing from said ac voltage source (7) into said converter; a voltage difference detecting means for detecting a difference between a voltage detected by said voltage detecting means and an inverter voltage command generated by said inverter voltage command generator; and an error control means (223) that when an absolute value of a voltage difference detected by said voltage difference detecting means is smaller by a given value than a converter voltage command generated by said converter voltage command generator (102), allows said chopper to boost a voltage at said smoothing capacitor (12). A power inverting apparatus according to claim 2, further comprising: a voltage detecting means (220) for detecting a voltage supplied by said ac voltage source (7); a voltage difference detecting means (226, 329) for detecting a difference between a voltage detected by said voltage detecting means (220) and an inverter voltage command (V CMD2 ) generated by said inverter voltage command generator (102); and an error control means (223) that when an absolute value of a voltage difference detected by said voltage difference detecting means is smaller by a given value than a converter voltage command generated by said converter voltage command generator, boosts a converter voltage command generated by said converter voltage command generator. A power inverting apparatus according to claim 22, further comprising an output terminal of said power inverting apparatus connected to said inverter (C), a first switch means connected between said inverter and said output terminal, and a second switch means connected between a junction between said ac voltage source and said bidirectional switching circuit (17), and said output terminal, wherein: when an absolute value of a voltage difference detected by said voltage difference detecting means is smaller by a given value than a converter voltage command generated by said converter voltage command generator, said error control means stops said inverter, turns off and on said first and second switch means respectively in order to bypass said output terminal to said ac voltage source, allows said converter to boost a dc voltage at said smoothing capacitor, then actuates said inverter, and turns on and off said first and second switch means respectively in order to release the bypassing. A power inverting apparatus according to claim 1, wherein said input voltage control means, said converter means, and said inverter means include: a converter (D) consisting of seventh and eighth switching circuits connected in series with each other and having a junction between said seventh and eighth switching circuits connected to one terminal of said ac voltage source; a smoothing capacitor connected in parallel with said converter; a selector (B) being connected in parallel with said converter, consisting of third and fourth switching circuits connected in series with each other, and having a junction between said third and fourth switching circuits connected to the other terminal of said ac voltage source; an inverter(C) being connected in parallel with said converter, and consisting of fifth and sixth switching circuits (5, 6) connected in series with each other; and a switching control circuit (106) for turning on or off said third to eighth switching circuits according to given timing. A power inverting apparatus according to claim 24, wherein each of said seventh and eighth switching circuits (1, 2) includes unidirectional switching elements. A power inverting apparatus according to claim 24, wherein each of said seventh and eighth switching circuits (1, 2) is formed with a bidirectional switching circuit. A power inverting apparatus according to claim 24, wherein each of said seventh and eighth switching circuits (1, 2) includes a unidirectional switching element (1t, 2t) and a diode (1d, 2d) connected in parallel with each other but in the opposite directions.

Inventors: AZUMA SATOSHI, SANADA KAZUNORI, AZUMA, SATOSHI, SANADA, KAZUNORI, AZUMA, SATOSHI, C/O MITSUBISHI DENKI K. K., SANADA, KAZUNORI, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H02M5
IPC codes: H02M5, H02M7