DC control circuit in bursted data receivers

Abstract: Of the type of receivers that performs direct current decoupling by capacitor, in order to isolate the input receiver of following stages. Applicable to digital burst transmission systems in optical fibre subscriber loops. The receiver comprises a line receiver (1) that converts the signal received over a transmission medium into an electrical signal (S), a direct current decoupling circuit (C,R1) and a first amplifier (A1). It is characterised in that it also includes a control circuit (2) that measures the DC component at the input node of the first amplifier (A1) during the frame instants when no signal is being received, and a current generator (I) that supplies this node with a current having a value determined by the control circuit (2), in such a way that it compensates for the increase in voltage produced on the decoupling capacitor.

Description: OBJECT OF THE INVENTION This invention concerns a circuit that restores the variations in DC level present in the signal received by a bursted data receiver, in such a way that the increases in this level resulting from the reception of the data bursts are eliminated. It is of special application in bursted data optical receivers. BACKGROUND TO THE INVENTION Optical receivers contain an opto-electrical transducer based generally on a PINFET and an amplifier that produces at its output an electrical signal with an amplitude proportional to the optical power received over an optical fibre. These components generate at their output signals that have a DC component, in the absence of received optical power, that basically depends on the PINFET bias current and on the amplifier bias currents This DC component therefore, is subject to serious drifts that depend heavily on other uncontrollable factors such as temperature, ageing, etc. This means that DC coupling between the opto-electical transducer and the following blocks is not possible unless these drift effects are allowed for. For this reason it is common practice to insert a direct current decoupling capacitor at the output of the transducer mentioned and thereby overcome this inconvenience. The document GB-A-2 162 010 discloses an amplifier including such a capacitor. Nevertheless, in systems like that described here, there is the additional drawback that the received bursts have a major low frequency component, meaning that the time constant of the circuit formed by this capacitor and the equivalent input resistance of the amplifier must be high in order to permit the lowest frequencies in the signal to pass. This situation means that the direct current decoupling capacitor alters its charge at the end of each burst by an amount that depends on the amplitude of the high logic level ( hereafter "1"), on the number of bursts, and on the ratio between the number of bits with value "1" and with value "0" in each burst. As a result of the foregoing it can happen that the value of the capacitor charge, after a few frames, is sufficiently large to prevent the detector circuit from correctly recovering the burst as the "0" logic level has shifted for the burst in question by an unknown amount; this could lead to the setting of an erroneous detection threshold or, at least, one that is not optimum. TECHNICAL PROBLEM TO BE OVERCOME As a result the technical problem to be overcome consists in compensating the variations in the DC component that appear on the direct current decoupling capacitor in data burst transmission systems. CHARACTERISATION OF THE INVENTION This invention which makes use of a line receiver to perform the conversion of data signals of any type received over a determined communication medium to signals of an electrical type, of a direct current decoupling circuit to isolate the DC component from the line receiver and of a first amplifier to boost the electrical signal level present after the decoupling circuit, is characterised in that it comprises a control circuit that measures the DC component present at the input of the first amplifier in a cyclic manner, during the frame instants when no signal is being received. The invention is also characterised in that it also comprises a current generator, which supplies the input node of the first amplifier with a current the value of which is determined by the control circuit in such a way the charge on the capacitor of the direct current decoupling circuit is altered in the sense of compensating the increase of the DC component on the extremities of this capacitor as a consequence of data burst reception. In this way the DC component of the input signal to the first amplifier, generated as a result of charge building up on the capacitor and due to the form of the received data, is compensated by the current delivered by the current generator so that in the event of receiving bursts with a determined minimum amplitude, the "0" logic level of this burst is close to zero volts. BRIEF FOOTNOTES TO THE FIGURES A more detailed explanation of the invention is made based on the following figures, in which: figure 1 shows a general circuit for performing the DC control in accordance with the invention, figure 2 shows an implementation of the DC control circuit according to the invention, and figure 3 shows the evolution with time of the signals present at various points of the circuit over the period of several frames. DESCRIPTION OF THE INVENTION This invention, in a recommended implementation, has been conceived for an optical fibre transmission system consisting of a line receiver 1, comprising, in turn, a PINFET diode and an amplifier (not shown), that performs the conversion of the data signals received over an optical fibre into electrical signals S. The output of this line receiver 1 is connected to a direct current decoupling circuit, formed, in turn, by a capacitor C and a resistor R1, such that the DC component at the output of the line receiver 1 (the value of which varies widely depending on parameters such as temperature, ageing, etc.) is perfectly decoupled. Due to the high bit rate employed in optical fibre transmission, it could be imagined that the time constant need not necessarily be high. However, for various reasons, it is necessary that this time constant be high with respect to the bit period. Thus, for example, in this case, with values of C=47 µF and R=600 Ω, the time constant is 28 ms, which is very large compared to the bit period which is about 20 ns. Figure 3-a) shows the signal S present at the output of the line receiver 1 where the received data correspond to a series of complete frames of consecutive ones, the length of each frame being approximately 500 µs. Figure 3-b) shows the development of the voltage across the capacitor C of the direct current decoupling circuit C,R1. Figure 3-c) shows the development of the signal at the output of the direct current decoupling circuit C,R1, in which it can be seen how the increase in capacitor charge produced by the first burst is gradually compensated in tile following bursts until the same voltage is obtained on both capacitor terminals. This increase is measured by the control circuit 2 which generates a first control voltage Vc1 that is applied to a current generator I which, in turn, provides a suitable current to compensate the preceding increase in voltage. This control circuit consists of a sample and hold means 3 that samples the signal at its input in a periodic manner according to a frame clock 4 at the frame instants when no signal is being received. The output signal from this sample and hold means 3 is a second control signal Vc2 that is applied to a direct current adapting circuit 5 which converts this second control signal Vc2 into the first control signal Vc1 the value of which is suitable to make the current generated by the current generator I compensate the initial voltage increase. To achieve this, the direct current adapting circuit 5 is made up of a first inverter amplifier R3,R4,A2 that amplifies and inverts the second control signal Vc2 and a second inverter amplifier R5,R6,A3 that amplifies and inverts the difference between the signal coming from the first inverter amplifier R3,R4,A2 and a second reference voltage V2, producing in this way the first control signal Vc1. The current generator I has been designed with a PNP bipolar transistor T, the base of which receives the first control signal Vc1 and whose emitter is connected to another reference voltage V1 through a resistor R2, whereby the collector output current tends to bring the input voltage of the amplifier A1 to a value close to zero volts (reference value when no received signal), using for this the necessary number of frames.

Claims: BURSTED DATA RECEIVER WITH DC CONTROL which comprises a line receiver (1) for performing the conversion of data signals received over a communication medium into signals of an electrical nature (S), a direct current decoupling circuit (C,R1) and a first amplifier (A1) to boost the level of the received electrical signal, characterised in that it also comprises: a control circuit (2) for performing the measurement of the DC component present at the input of the first amplifier (A1) in a cyclic manner during the frame instants when no signal is being received, and a current generator (I) that supplies the input node of the first amplifier (A1) with a current whose value is determined by the control circuit (2), in such a way that the charge on the capacitor (C) is altered in the sense of compensating the increase in the DC component across this capacitor (C) produced as a result of the number of data bursts received, of the amplitude of the bit with value "1" and of the ratio between the number of bits of value "1" and of value "0" in each burst. RECEIVER according to claim 1, characterised in that the current generator (I) comprises a bipolar PNP transistor (T) to the base of which is applied a first control signal (Vc1) coming from the control circuit (2), whose emitter is connected to one extremity of a second resistor (R2) and whose collector is connected to the input node of the first amplifier (A1) such that it supplies a direct compensating current, the other extremity of the second resistor (R2) being connected to a first reference voltage (V1). RECEIVER according to claim 1, characterised in that the control circuit (2) comprises sample and hold means (3) of its input signal, these sample and hold means receiving a clock signal coming from a clock circuit (4) in order to perform the sampling process during the frame instants when no signal is being received and the holding process during the rest of the time, and to generate at its output a second control signal (Vc2) that is applied to a direct current adapting circuit (5) which, in turn, generates the first control signal (Vc1), whereby the current supplied by the current generator (I) tends to compensate the DC component measured at the input of the sample and hold means (3). RECEIVER according to claim 3, characterised in that the direct current adapting circuit (5) comprises a first inverter amplifier (R3,R4,A2) that amplifies and inverts the second control signal (Vc2) coming from the sample and hold means (3), and a second inverter amplifier (R5,R6,A3) that amplifies and inverts the difference between the signal coming from the first inverter amplifier (R3,R4,A2) and a second reference voltage (V2), in order to generate in this way the first control signal (Vc1).

Inventors: ELDERING CHARLES A, MARTIN GOMEZ RAQUEL, ELDERING, CHARLES A., MARTIN GOMEZ, RAQUEL
Applicants: ALCATEL NV, ALCATEL N.V.
Application year: 1994
Main classification: H03F1
IPC codes: H03F1