CIRCUIT FOR DECODING VARIABLE-LENGTH CODE, AND SYSTEM FOR DECODING VARIABLE-LENGTH CODE WHICH USES THE CIRCUIT

Abstract: A circuit comprising a pair of a CAM cell (10) for storing variable-length codes and a RAM cell (20) for storing data used for mask processing. This circuit further has an NMOS (30) which is connected between the CAM cell (10) and a match line ML, and cuts off the CAM cell (10) from the match line ML by use of the output of the RAM cell (20). The CAM cell (10) checks a code applied from the outside with the code stored in it. If these codes are agreed with each other, the CAM cell (10) outputs an H level signal which represents the agreement to the match line ML. If disagreed, it outputs an L level signal which represents the disagreement to the match line ML. If the CAM cell does not engage in the checking operation, the corresponding RAM cell (20) outputs an L level signal to turn off the NMOS (30). When the NMOS is turned off, the output from the CAM cell (10) is not transmitted to the match line ML.

Description: The present invention relates to a variable-length code decoding system for decoding a compressed image, etc. There is the following literature disclosing a technique for decoding a variable-length code. Literature: IEEE 1992 Custom Integrated Circuits Conference, "A Video-Rate, JPEG Chip Set" p. 26. 2. 1-26. 2. 4., authored by Daniel A. Luthi, Po Tong, Peter A. Ruetz. This literature discloses the technique using a variable-length code as a means for compressing an image data or for restoring and decoding the compressed image data. The variable-length code means a code which is allocated in response to frequency of occurrence of parameters after the image data has been subjected to an arithmetic operation such as a Discrete Cosine Transform (hereinafter referred to as DCT) operation and a quantisation operation. That is, a short code is allocated to a parameter which frequently occurs while a long code is allocated to a parameter which less occurs. By varying the length of the code as mentioned above, the number of codes can be reduced as a whole, thereby realising improvement in compression rate of the image data. Since an image display rate on a display of a TV set or a monitor must be kept at a given value when restoring a dynamic image, the variable length code as set forth above is always required to be restored at a constant rate. It is practically preferable to decode one variable-length code in one clock cycle. Since an image data is required to be processed at high speed in recent years, an improvement of a decoding speed of the variable-length code is important as one means for realising a high speed processing speed of the image data. US-A-5,173,695 discloses a variable-length decoder for use in a data transmission system. The decoder uses a lookup table to decode the sequentially occurring bits in the received data signal. A memory stores information associated with each possible input word, including word length and a fixed-length codeword. In response to a control signal, a barrel shifter shifts its decoding window across the sequence of input bits as each codeword is detected. The window is shifted after each word is decoded by a shift length corresponding to the length of the just-decoded word. It is an object of the invention to provide a variable-length code decoding system for realising a high operation speed. In accordance with the present invention, there is provided a variable-length code decoding system comprising:- an input node to which is applied a variable-length code string containing a plurality of variable-length codes; a variable-length code decoding part for detecting one of the variable-length codes within said variable-length code string and outputting a first data representing the code length of said detected variable-length code; a first latch circuit for latching a second data representing the positions of the variable-length codes within said variable-length code string in response to a clock signal, and outputting the latched second data; and a regulating circuit coupled to said input node for shifting the positions of said variable-length codes within said variable-length code string; said decoding system being characterised by a second latch circuit for latching the output of said regulating circuit in response to said clock signal and outputting the latched output to said variable-length code decoding part, and in that said regulating circuit comprises:- a first shifter for shifting said variable-length code string by a shift amount represented by said second data, and outputting said shifted variable-length code string as a first shift data; and a second shifter for shifting said first shift data by a shift amount represented by said first data and outputting said shifted first shift data to said second latch circuit as a second shift data, so that the variable-length code to be decoded by said variable-length code decoding part becomes the leading code of said variable-length code string. In an embodiment, the system further comprises an adder for adding said first data to said latched second data and wherein the output of said adder is outputted to said first latch circuit as said second data. In order that the invention may be better understood, an embodiment thereof will now be described by way of example only and with reference to the accompanying drawings, in which: - Figure 1 is a circuit diagram showing a main part of a preferred embodiment of a variable-length code decoding circuit for use in the variable length decoding system of the invention; Figure 2 is a circuit diagram of a preferred embodiment of a variable-length code decoding circuit for use in the decoding system of the invention; Fig. 3 shows a variable-length code table of the variable-length code decoding circuit in Fig. 2; Fig. 4 is a circuit diagram of a variable-length code decoding system according to a preferred embodiment of the invention; Fig. 5 is a timing chart showing an operation of the variable-length code decoding system in Fig. 4; and Figs. 6(A) and 6 (B) are schematic views showing the variable-length code decoding circuit and the variable-length code decoding system according to the present invention. A general image data is processed in accordance with a flow chart, for example, as shown in Fig. 6(A). That is, an input image data Din is subjected to a DCT operation and thereafter it is subjected to a quantization operation. The resultant quantizized image data is supplied to a variable-length code coding circuit 601. The variable-length code coding circuit 601 subjects the quantizized image data to a coding operation and outputs a compressed data D detail of which is shown in Fig. 6(B). The compressed data D is subjected to a reverse quantization operation after it was decoded by a variable-length code decoding circuit 603 and it is subjected to a reverse DCT operation, and thereafter it is output as an output image data Dout. The present invention described hereinafter in detail relates to an arrangement corresponding to the variable-length code decoding circuit 603 as shown in Fig. 6(A). The present invention will be described hereinafter in detail. Fig. 1 is a circuit diagram showing a main part of a variable-length code decoding circuit according to a preferred embodiment of the invention. The variable-length code decoding circuit comprises a Content Addressable Memory (hereinafter referred to as a CAM) cell 10 provided at an intersection between a bit line pair (BL1 and an inverse BL1 (hereinafter referred to as ( BL1 )) and a word line WL and a Random Access Memory (RAM) cell 20 provided at an intersection between a bit line pair (BL2 and an inverse BL2 (hereinafter referred to as ( BL2 )) and the word line WL, and a switch (MOS transistor) 30 which permits the CAM cell 10 and a match line ML to be conductive in response to an output of the RAM cell 20. The CAM cell 10 comprises a data memory part for storing a code constituting a variable-length code and a data collating part for outputting a result of collation between a code applied from the bit line pair and the code as stored in the data memory part. The data memory part comprises a flip-flop 11 (latch circuit) for storing the code constituting the variable-length code, an NMOS 12 having a gate which is controlled by the potential of the word line WL for electrically coupling one node of the flip-flop 11 and the bit line BL1 to each other and an NMOS 13 having a gate which is controlled by the potential of the word line WL for electrically coupling the other node of the flip-flop 11 to the inverse bit line BL1 to each other. The data collating part comprises an NMOS 14, an NMOS 15, an NMOS 16 and an NMOS 17 which are coupled in series between the bit line BL1 and the inverse bit line BL1 . Gates of the NMOSs 14 and 17 are commonly coupled to a match enable line MEL while a gate of the NMOS 15 is coupled to one node of the flip-flop 11 and a gate of the NMOS 16 is coupled to the other node of the flip-flop 11. The NMOS 15 and the NMOS 16 are commonly coupled to a collating result output node N1. The RAM cell 20 comprises a flip-flop 21 (latch circuit) serving as a data memory means for storing a mask data, an NMOS 22 having a gate which is controlled by the potential of the word line WL for coupling one node of the flip-flop 21 and the inverse bit line BL2 to each other, and an NMOS 23 having a gate which is controlled by the potential of the word line WL for coupling the other node of the flip-flop 21 and the inverse bit line BL2 to each other. There is provided an NMOS 30 between the collating result output node N1 of the CAM cell 10 and the match line ML wherein the NMOS 30 has a gate which is controlled by the potential appearing on one node of the flip-flop 21 for electrically coupling the collating result output node N1 and the match line ML to each other. An operation of the main part of the variable-length code decoding circuit having the arrangement as set forth above will be described hereinafter. (An operation of the RAM cell 20) When the word line WL is changed to H level (e.g., VCC level), the NMOSs 22 and 23 are ON. At this time, suppose that H level is applied to the bit line BL2 and L level is applied to the inverse bit line BL2 . (Supposing that a data "1" is applied to the bit line pair coupled to the RAM cell), the potential of H level of the bit line BL2 is applied to one node of the flip-flop 21 by way of the NMOS 22 while the potential of H level of the inverse bit line BL2 is applied to the other node of the flip-flop 21 by way of the NMOS 23. That is, it means that the flip-flop 21 stores the data "1". Meanwhile, suppose that L level is applied to the bit line BL2 and H level is applied to the inverse bit line BL2 , (Supposing that a data "0" is applied to the bit line pair coupled to the RAM cell), the potential of L level of the bit line BL2 is applied to one node of the flip-flop 21 by way of the NMOS 22 while the potential of H level of the inverse bit line BL2 is applied to the other node of the flip-flop 21 by way of the NMOS 23. That is, it means that the flip-flop 21 stores the data "0", contrary to the previous case. (An operation of CAM cell 10) A data storage part of the CAM cell 10 (the flip-flop 11, the NMOS 12 and the NMOS 13) operates in the same manner as the RAM cell 20. The CAM cell 10 is different from the RAM cell 20 in respect that the former includes a data collating part. Suppose that the data storage part stores the data "1". Suppose that when the potential of the word line WL is changed to H level, a code data "1" constituting a variable-length code is applied to the bit line pair coupled to the CAM cell 10, and at the same time the potential of the match enable line MEL is H level. Since a node N3 which is an output node of the data storage part is H level, the NMOS 15 is ON. Since the potential of the match enable line MEL is H level, the NMOS 14 is also ON. Accordingly, the potential of H level of the bit line BL1 is applied to the collating result output node N1 by way of the NMOS 14 and the NMOS 15. On the other hand, since the other potential of the flip-flop 11 is L level, the NMOS 16 is OFF. Accordingly, the potential of L level of the inverse bit line BL1 is not applied to the collating result output node N1. Suppose that a code data "0" constituting the variable-length code is applied to the bit line pair coupled to the CAM cell 10. Since the node N3 serving as the output node of the data storage part is H level, the NMOS 15 is ON. Further, since the potential of the match enable line MEL is H level, the NMOS 14 is also ON. Accordingly, the potential of L level of the bit line BL1 is applied to the collating result output node N1 by way of the NMOS 14 and the NMOS 15. Whereupon, since the other potential of the flip-flop 11 is L level, the NMOS 16 is OFF. Accordingly, the potential of H level of the inverse bit line BL1 is applied to the collating result output node N1. Supposing that the potential of one node of the flip-flop 21 which is an output node N2 of the RAM cell 20 is H level (i. e., data stored in the RAM cell 20 is "1"), the NMOS 30 is ON so that the potential applied to the collating result output node N1 is applied to the match line ML. If the code data "1" is applied to the bit line pair coupled to the CAM cell 10, the potential of the match line ML is changed to H level by the potential of H level of the collating result output node N1. Whereupon, if the code data "0" is applied to the bit line pair coupled to the CAM cell 10, the potential of the match line ML is changed to L level by the potential of L level of the collating result output node N1. That is, the CAM cell 10 outputs H level from the collating result output node N1 when the data applied to the bit line pair coupled to the CAM cell 10 matches the data stored in the CAM cell 10 while it outputs L level when the data applied to the bit line pair coupled to the CAM cell 10 does not match the data stored in the CAM cell 10. The RAM cell 20 stores the data "1" beforehand if there is necessity of transmission of the result of the operation of the CAM cell 10 to the match line ML, while it stores the data "0" if there is non-necessity of transmission of such result. The necessity or non-necessity of transmission of the result of operation of the CAM cell 10 is decided when the code data is stored in the CAM cell 10. This will described later more in detail. An embodiment of the variable-length code decoding circuit will be described hereinafter with reference to Fig. 2. Fig. 2 is a view showing the variable-length code decoding circuit according to the embodiment of the present invention. The variable-length code decoding circuit comprises a plurality of memory cell selecting word lines WL (0) to WL (m-1), a plurality of match lines ML (0) to ML (m-1), a plurality of match enable lines MEL (0) to MEL (m-1) and bit line pairs BL1 (0) to BL1 (n-1) and BL2 (0) to BL2 (n-1) which are arranged at intersections between these word lines, match lines and match enable lines. (In Fig. 2, although each of the bit line pairs is illustrated by one line for facilitating the explanation, the bit line is paired practically as shown in Fig. 1.) A plurality of groups of CAM cells 10 (0, 0) to 10 (m-1, m-1) and a plurality of groups of RAM cells 20 (0, 0) to 20 (m-1, n-1) are paired and arranged at intersections between these lines. MOS transistors 30 (0, 0) to 30 (m-1, n-1) serving as switches which are controlled by outputs of the RAM cells are coupled between each of the CAM cells and the match lines. The arrangement of the CAM cells and the RAM cells in Fig. 2 are the one where the arrangement of the CAM cell and the RAM cell in Fig. 1 are arranged in plural and in array. Code data constituting the variable-length code is stored in each CAM cell. One variable-length code comprises a plurality of code data which are stored in a plurality of CAM cells corresponding to the same word lines. Data as stored in each RAM cell is differentiated as to whether the corresponding CAM cell needs or does not need the collating operation. Fig. 3 shows a table of the variable-length code decoding circuit in Fig. 2. In Fig. 3, each bit position shows a position where each CAM cell (RAM cell) as shown in Fig. 2 is positioned. A bit position where "0" is described represents that the code data "0" is stored in the CAM cell while a bit position where "1" is described represents that the code data "1" is stored in the CAM cell. A bit position where "X" is described represents that the data "0" is stored in the RAM cell. That is, it means that a collating result output of the corresponding CAM cell is not applied to the match line ML regardless of the code data described in the corresponding CAM cell. For example, since a variable-length code "00001" as stored in a first word comprises five bits, it is not necessary to perform a collating operation for a sixth bit or succeeding bits. That is, the first word is a word where the variable-length code "00001" is subjected to the collating operation. Accordingly, it is meaningless even if the sixth bit or succeeding bits are subjected to the collating operation. As a result, the RAM cell which is positioned at bits following the sixth bit invalidates an output of the corresponding CAM cell. (It means that the collating operation per se may be performed but the collating result must not be output to the match line ML.) A variable-length code "10" as stored in a second word comprises two bits so that a third bit and succeeding bits are not necessary to be subjected to a collating operation. That is, since the second word is a word where the variable-length code "10" is subjected to the collating operation, it is meaningless even if the third bit and succeeding bits are subjected to the collating operation. Accordingly, the RAM cell which is positioned at the bits following the third bit invalidates the output of the corresponding CAM cell. (It means that the collating operation may be performed but the collating result must not be output to the match line ML.) Since the variable-length code "1111111110011011" as stored in the fourth word comprises 16 bits, the data "1" is stored in all the corresponding RAM cells so as to validate the outputs of the CAM cells to the match lines. The collating result output node N1 of each CAM cell is coupled to the match lines ML (0) to ML (m-1) by way of the NMOSs 30 (0, 0) to 30 (m1, n-1). The NMOSs 30 (0, 0) to 30 (m-1, n-1) are subjected to ON-OFF control in response to the corresponding outputs of the RAM cells. A plurality of NMOSs 30 (0, 0) to 30 (m-1, n-1) corresponding to the same word lines WL (0) are subjected to a wired OR to a single match line ML (0) corresponding to the same word line WL (0) and are coupled to a match line output circuit 80 (0). This is applied same to the couplings between match lines ML and match line output circuits of the other NMOSs. A plurality of word lines WL (0) to WL (m-1) are selected by an address decoder 40 which decodes an address signal Ai. The address decoder 40 has an inverse output enable terminal OE/ for receiving a match enable signal EB. Each of the bit line pairs BL1 (0) to BL1 (n-1), BL2 (0) to BL2 (n-1) is coupled to input/output circuits (hereinafter referred to as I/O circuits) 50 (0) to 50 (n-1) each having a selection circuit for selecting one of bit line pairs coupled to a write circuit, a read circuit and the CAM cell or the bit line pairs coupled to the RAM cell. Further, a power supply potential VCC is applied to these bit line pairs by way of loading NMOSs 61 (0) to 61 (n-1) and NMOSs 62 (0) to 62 (n-1). The loading NMOSs are set to be small in their driving capacity. Accordingly, the potential of the bit line pair is not varied by the loading NMOSs in case of writing data in the write circuit or reading data from the read circuit. Each of the I/O circuits 50 (0) to 50 (n-1) is coupled to input/output terminals (hereinafter referred to as I/O terminals) IO (0) to IO (n-1) for performing a data input/output operation and to a control terminal CS to which a control signal CS for controlling the data input/output operation is applied. The match enable lines MEL (0) to MEL (m-1) are commonly coupled to a match enable terminal EB to which a match enable signal EB is applied. The match lines ML (0) to ML (m-1) receives the power supply potential VCC at one end thereof by way of NMOSs 70 (0, 0) to 70 (m-1, n-1) while it is coupled to match output terminals OUT (0) to OUT (m-1) at the other end thereof by way of match line output circuits 80 (0) to 80 (m-1). An operation of the variable-length code decoding circuit having the arrangement as set forth above will be described hereinafter in detail with reference to Figs. 2 and 3. The operation of the variable-length code decoding circuit comprises (1) a variable-length code writing operation for writing the variable-length code as shown in Fig. 3 in each of the CAM cells and RAM cells and at the same time invalidating outputs of the CAM cells positioned in remaining bit positions where the variable-length code is not written (what is called a mask processing) and (2) a matching or collating operation for collating the variable-length code with the variable-length code as stored in the CAM cell. 1. Variable-length Code Writing Operation: The match enable signal EB is first changed to "L" level. The match enable lines MEL (0) to MEL (m-1) are changed to "L" level so that a plurality of NMOSs 14 and 17 are OFF. When each of the NMOSs 14 and 17 are OFF, the operation of a data collating part in each CAM cell is inhibited. Accordingly, each CAM cell operates as a normal RAM which does not perform a data collating operation. When the match enable signal EB is changed to "L" level, the address decoder 40 is enabled. The enabled address decoder 40 permits the potential of a single word line WL alone to be "H" level in response to the address signal Ai. (the single word line WL alone is selected.) Next, when the control signal CS is changed to "L" level, a write circuit, not shown, in the I/O circuits 50 (0) to 50 (n-1) is enabled. When a selector circuit, not shown, in the I/O circuits 50 (0) to 50 (n-1) is operated so as to select bit line pairs BL1 (0) to BL1 (n-1) which are coupled to the CAM cells, the CAM cells are ready for receiving the variable-length code. For example, suppose that the address decoder 40 sets the address signal Ai so as to select the word line WL (1) so that the data "1" is applied to the I/O terminal IO (0) and the data "0" is applied to the I/O terminal IO (1). As a result, the code data "1" is written in the CAM cell 10 (0, 0) and the code data "0" is written in the CAM cell 10 (0, 1). Next, when the selector circuit, not shown, in the I/O circuits 50 (0) to 50 (n-1) is operated so as to select bit line pairs BL2 (0) to BL2 (n-1) which are coupled to the RAM cells, the RAM cells are ready for receiving the mask data. For example, suppose that the address decoder 40 sets the address signal Ai so as to select the word line WL (1) so that a mask data "1" is applied to each of the I/O terminals IO (0) to IO (1) and the mask data "0" is applied to each of the I/O terminals IO (2) to IO (15). As a result, the mask data "0" is written in the RAM cell 10 (0, 0) to the RAM cell 10 (0, 1) and the mask data "1" is written in the RAM cell 10 (0, 2) to the RAM cell 10 (0, 15). The aforementioned operations mean that the variable-length code which is stored in the second word is "10" and its code length is "2 bits" (16 bits - a bit where the mask data "1" is stored). A memory such as the RAM is coupled to the match output terminal OUT (1) wherein the variable-length code "10" having the code length of "2 bits" is stored in this memory at a position of the word corresponding to the match output terminal OUT (1). The aforementioned operations correspond to the second word in Fig. 3. Likewise, the variable-length code and the mask data are written in each word. 2. Matching operation: The match enable signal EB is first changed to "H" level. Then, the address decoder 40 is changed to an operation inhibiting state so that all the word lines WL (0) to WL (m-1) coupled to the address decoder 40 are changed to "L" level. At the same time, the bit line pairs BL1 (0) to BL1 (n-1), BL2 (0) to BL2 (n-1) are changed to "H" level. When the control signal CS is changed to "L" level, the write circuit, not shown, in the I/O circuits 50 (0) to 50 (n-1) are enabled. When the selector circuit, not shown, in the I/O circuits 50 (0) to 50 (n-1) is operated so as to select the bit line pairs BL1 (0) to BL1 (n-1) coupled to the CAM cells, the CAM cells are ready for receiving the variable-length code to be decoded. Whereupon, for example, suppose that a variable-length code data Di of an infinite array which is to be decoded and shown in Fig. 6 (B) is applied to the I/O terminals IO (0) to IO (15). The variable-length code decoding circuit according to the present embodiment can decode the variable-length code having code length of 16 bits at maximum. Accordingly, the variable-length code data Di extending from the leading bit to the sixteenth bit is once input to the I/O terminals IO (0) to IO (15). When the data Di having 16 bit length is applied to the I/O terminals IO (0) to IO (15), the data Di is applied to the bit line pairs BL1 (0) to BL1 (n-1). Since all the CAM cells are coupled to the bit line pairs BL1 (0) to BL1 (n-1), all the CAM cells start the collating operation with the data Di having 16 bit length at the same time. When the code data as stored in the CAM cell matches the data input thereto, "H" level is output to a corresponding match line while when the former does not match the latter, "L" level is output to the corresponding match line. In the same word, when it is detected that even one code data as stored in the CAM cell does not match the data input thereto, the match line ML is changed to "L" level. Since the CAM cell corresponding to the RAM cell which stores the mask data "0" is electrically disconnected from the match line ML, the CAM cell which practically outputs the collating output is the CAM cell alone corresponding to the RAM cell which stores the mask data "1". Referring to the variable-length code table in Fig. 3, it is evident that a first data "0001" of the data Di having 16 bit length matches the data of sixth word of the same table. Since the CAM cells 10 (5, 0) to 10 (5, 3) corresponding to the sixth word of the variable-length code decoding circuit output "H" level to each collating result output node, the match line ML (5) is changed to "H" level. As to other words, since any one of the CAM cells which are positioned at the same word outputs "L" level, all the match lines ML are changed to "L" level. The match line output circuit 80 (5) outputs a detection signal which informs the output terminal OUT (5) that the match line ML (5) is changed to "H" level. The RAM, not shown, coupled to the output terminal OUT (5) informs an external circuit, described later, that the variable-length code "0001" having the code length of 4 bits when receiving the detection signal output from the output terminal OUT (5). To decode the variable-length code which follows the variable-length code "0001", the external circuit discards the first data which has been already decoded. As a means for rounding down the first data, the external circuit shifts the data Di to the left by the code length (4 bits) of the first data and applies this shifted data again to the I/O terminals IO (0) to IO (15) of the variable-length code decoding circuit. When this data Di is applied to the I/O terminals IO (0) to IO (15), the data Di is applied to the bit line pairs BL1 (0) to BL1 (n-1) like the previous case. Since all the CAM cells are coupled to the bit line pairs BL1 (0) to BL1 (n-1), they start the collating operation with this data Di at the same time. Referring to the variable-length code table in Fig. 3, it is evident that a second data "010" of the data Di matches the data of third word of the same table. Since the CAM cells 10 (2, 0) to 10 (2, 1) corresponding to the third word of the variable-length code decoding circuit output "H" level to each collating result output node, the match line ML (2) is changed to "H" level. As to other words, since any one of the CAM cells which are positioned at the same word outputs "L" level, all the match lines ML are changed to "L" level. The match line output circuit 80 (2) outputs a detection signal which informs the output terminal OUT (2) that the match line ML (2) is changed to "H" level. The RAM, not shown, coupled to the output terminal OUT (2) informs an external circuit, described later, that the variable-length code "010" having the code length of "3 bits" when receiving the detection signal output from the output terminal OUT (2). The aforementioned operations are repeated so that the variable-length code decoding circuit decodes the variable-length code of the infinite array and the code length thereof. There are two points to be noted especially in the aforementioned operations. Since all the storage circuits for storing the variable-length code in the collating operation are coupled to the corresponding bit lines, the collating speed is constant regardless of the position of the word of the storage circuit where the variable-length code corresponding to the variable-length code to be input thereto is stored. That is, in the collating operation of the variable-length code to be input, the variable-length code decoding circuit of the present invention is quicker than the circuit wherein the collating operation is performed sequentially from the storage circuit positioned at the first word to the storage circuit positioned at the last word. Another point to be noted is that the code length can be also detected at the same time with the collating operation since the control circuit for inhibiting the output operation of the storage circuit which stores the variable-length code is provided in correspondence with each storage memory. The fact that the code length can be detected at the same time with the collating operation dispenses with the application of the length code of the data to each data of the variable-length code to be inputted. Accordingly, compression of the image data is more facilitated, which results in the expectation of performing the image processing at high speed. Further, the variable-length code which has been already collated can be discarded at high speed, which results in the expectation of performing the decoding of the variable-length code at high speed. An embodiment of the variable-length code decoding system of the present invention will be described hereinafter with reference to Figs. 4 and 5. Fig. 4 is a circuit diagram of a variable-length code decoding system according to an embodiment of the invention. In Fig. 4, a variable-length code decoding circuit 417 is the aforementioned variable-length code decoding circuit and a RAM 415 coupled to an output of the variable-length code decoding circuit 417 is a RAM which was explained as the aforementioned RAM, not shown. The variable-length code decoding system of the present invention comprises a variable-length code decoding part 413, first and second shifters 401 and 403 for shifting and outputting stored data in response to a shift signal (instruction) to be input to a shift terminal S, latch circuits 405 and 411 for latching the data in response to a clock signal, an adder 407 for adding a shift instruction S415 to be output from the variable-length code decoding part 413 and a shift instruction output from the latch circuit 411 and a reset circuit 409. For example, the variable-length code data Di having 16 bit length is applied to the first shifter 401. The first shifter 401 shifts the variable-length code data Di in response to a shift amount represented by a shift instruction S411. The first shifter 401 further outputs the shifted variable-length code data Di to the second shifter 403 as a data S401. The data S401 which is output from the first shifter 401 is applied to the second shifter 403. The second shifter 403 shifts the data S401 in response to a shift amount (in response to an output S409 of the reset circuit 409 at the initialization) represented by the shift instruction S415. The second shifter 403 outputs the shifted data to the latch circuit 405 as a data S403. The latch circuit 405 latches the data S403 which is output from the second shifter 403 in response to the clock signal and outputs this latched data to an I/O terminal of the variable-length code decoding circuit 417 as a data S405. The RAM 415 detects the aforementioned collated variable-length code and its code length. In the variable-length code decoding system, the RAM 415 outputs the length of the collated variable-length code as the shift instruction S415. The latch circuit 411 latches a shift instruction S407 which is output from the adder 407 in response to the clock signal and outputs this latched instruction to the first shifter 401 as the shift instruction S411. Fig. 5 (A) shows the variable-length code data Di to be input. Fig. 5 (B) is a timing chart showing an operation of the variable-length code decoding system. The operation of the variable-length code decoding system as shown in Fig. 4 will be described hereinafter with reference to Figs. 5 (A) and 5 (B). In the initial state, since the latch circuit 411 is reset, the shift instruction S411 as its output is 0. (The latch circuit 411 applies an instruction to shift the data by 0 bit to the first shifter 401.) The reset circuit 409 outputs in its initial state the shift instruction S409 being 0. Accordingly, the shift amount of the first shifter 401 and the second shifter 403 is 0. Further, since the collation of the variable-length code is not performed, we describe further supposing that the shift instruction S415 is also 0. In the initial state as mentioned above, the variable-length code string (the first data of 4 bits, the second data of 3 bits, ···) as shown in Fig. 5 (A) is applied to the first shifter 401. When the clock signal rises, the first shifter 401 shifts the variable-length code string by the amount (0 bit) which is specified by the shift instruction S411. Accordingly, the first shifter 401 outputs the shift data S401 (0001010···) to the second shifter 403. The data S401 of the first shifter 401 does not vary unless the shift instruction S411 varies. On the other hand, the shift instruction S411 varies only when the clock signal rises. Accordingly, the output S401 does not vary during a cycle T1. In the early stage of the cycle T1, the second shifter 403 shifts the data S401 by the amount specified by the shift instruction S415 (in the initial state since the reset signal is output from the reset circuit 409, the shift amount is 0 bit) and outputs the shifted data S403 (0001010···) to the latch circuit 405. The latch circuit 405 latches the data S403 in response to the rising of the clock signal and outputs this latched data S403 as the latch circuit 405 (0001010···) to the variable-length code decoding part 413. The latch circuit 405 updates the data S405 in response to the rising of the clock signal. Accordingly, the data S405 does not vary during the cycle T1. The variable-length code decoding part 413 performs the aforementioned collating operation upon reception of the data S405. (Matching and detecting time). The variable-length code decoding part 413 outputs the shift instruction S415 representing the code length of the variable-length code as a collating result at the portion near the center of the cycle T1. During the cycle T1, the variable-length code decoding part 413 detected the variable-length code "0001" having the length code of "4 bits". The shift instruction S415 to shift the data by 4 bits is applied to an input terminal A of the adder 407 and a shift input terminal S of the second shifter 403. (Since the operation of the reset circuit 409 has been already cleared, the shift instruction S415 is applied to the shift input terminal S of the second shifter 403 by way of the reset circuit 409). The second shifter 403 outputs the data S403 (010100...), which is produced by shifting the data (0001010···) output during the early stage of the cycle T1 by 4 bits, to the latch circuit 405 in response to the shift instruction S415. At the portion near the center of the cycle T1, the shift instruction S407 which is output from the adder 407 is changed from the instruction to shift by 0 bit to the instruction to shift by 4 bits. During the cycle T1, the output S401 of the first shifter 401 represents the variable-length code string (0001···) wherein the presently decoded variable-length code (first data) leads and the output S405 of the latch circuit 405 represents the variable-length code string (0001···) wherein the presently decoded variable-length code (first data) leads, and the output S411 of the latch circuit 411 represents a leading position of the presently decoded variable length code (0th bit counting from the initial state). In the latter stage of the cycle T1, the output S403 of the second shifter 403 represents the variable-length code string (01···) wherein the presently decoded variable-length code (second data) leads. Described hereinafter is an operation of the variable-length code decoding system when a cycle T2 following the cycle T1 starts. When the clock signal rises, the latch circuit 411 latches the shift instruction S407 (instruction to shift by 4 bits). The latch circuit 411 outputs the shift instruction S411 to shift by 4 bits to the first shifter 401. The first shifter 401 shifts the variable-length code string by 4 bits in response to the shift instruction S411. Accordingly, the first shifter 401 outputs the shifted data S401 (010100···) to the second shifter 403. When the clock signal rises, the latch circuit 405 latches the data S403 (010100···). The latch circuit 405 outputs this latched data (010100···) to the variable-length code decoding part 413 as the data S405. The variable-length code decoding part 413 performs the collating operation upon reception of the data S405. (Matching and detecting time). The variable-length code decoding part 413 outputs the shift instruction S415 representing the code length of the variable-length code as a collating result at the portion near the center of the cycle T2. During the cycle T2, the variable-length code decoding part 413 detected the variable-length code "010" having the code length of "3 bits". The shift instruction S415 to shift the data 3 bits is applied to the input terminal A of the adder 407 and the shift input terminal S of the second shifter 403. The second shifter 403 outputs the data S403 (100000···), which is produced by shifting the data (010100···) output during the early stage of the cycle T2 by 3 bits, to the latch circuit 405 in response to the shift instruction S415. At the portion near the center of the cycle T2, the adder 407 adds an instruction to shift by 4 bits which is applied to an input terminal B and an instruction to shift by 3 bits which is applied to the input terminal A and it outputs the shift instruction S407 to shift by 7 bits to the latch circuit 411. During the cycle T2, the output S401 of the first shifter 401 represents the variable-length code string (010···) wherein the presently decoded variable-length code (second data) leads and the output S405 of the latch circuit 405 represents the variable-length code string (010···) wherein the presently decoded variable-length code (second data) leads, and the output S411 of the latch circuit 411 represents a leading position of the presently decoded variable length code (4th bit counting from the initial state). In the latter stage of the cycle T2, the output S403 of the second shifter represents the variable-length code string (10···) wherein the presently decoded variable-length code (third data) to be decoded in the next cycle leads. Described hereinafter is an operation of the variable-length code decoding system when a cycle T3 following the cycle T2 starts. When the clock signal rises, the latch circuit 411 latches the shift instruction S407 (instruction to shift by 7 bits). The latch circuit 411 outputs the shift instruction S411 to shift by 7 bits to the first shifter 401. The first shifter 401 shifts the variable-length code string by 7 bits alone in response to the shift instruction S411. Accordingly, the first shifter 401 outputs the shifted data S401 (100000···) to the second shifter 403. When the clock signal rises, the latch circuit 405 latches the data S403 (100000···). The latch circuit 405 outputs this latched data (100000···) to the variable-length code decoding part 413 as the data S405. The variable-length code decoding part 413 performs the collating operation upon reception of the data S405. (Matching and detecting time). The variable-length code decoding part 413 outputs the shift instruction S415 representing the code length of the variable-length code as a collating result at the portion near the center of the cycle T3. During the cycle T3, the variable-length code decoding part 413 detected the variable-length code "10" having the length code of "2 bits". The shift instruction S415 to shift the data by 2 bits is applied to the input terminal A of the adder 407 and the shift input terminal S of the second shifter 403. The second shifter 403 outputs the data S403 (000001···), which is produced by shifting the data (100000···) output during the early stage of the cycle T3 by 2 bits, to the latch circuit 405 in response to the shift instruction S415. At the portion near the center of the cycle T3, the adder 407 adds an instruction to shift by 7 bits which is applied to the input terminal B and an instruction to shift by 2 bits which is applied to the input terminal A and it outputs the shift instruction S407 to shift by 9 bits to the latch circuit 411. During the cycle T3, the output S401 of the first shifter 401 represents the variable-length code string (10···) wherein the presently decoded variable-length code (third data) leads and the output S405 of the latch circuit 405 represents the variable-length code string (10···) wherein the presently decoded variable-length code (third data) leads, and the output S411 of the latch circuit 411 represents a leading position of the presently decoded variable length code (7th bit counting from the initial state). In the latter stage of the cycle T3, the output S403 of the second shifter 403 represents the variable-length code string (000001···) wherein the presently decoded variable-length code (fourth data) leads. According to the variable-length code decoding system, the input variable-length code string is decoded by repeating the aforementioned operations. As mentioned above, according to the variable-length code decoding system, the variable-length code can be decoded always during one cycle since the variable-length code string is shifted so that the variable-length code to be decoded in the next cycle leads before the appearance of the next cycle. Accordingly, it is possible to satisfy the image display rate on the display of the TV set or the monitor which displays the image when restoring the image. That is, it is possible to display the correct image on the display. As a result, the image processing can be performed at higher speed. According to the variable-length code decoding circuit, the content of the data to be input and the length of the data can be detected at higher speed. According to the variable-length code decoding circuit, the content of the data to be input and the length of the data can be detected at higher speed even in the case where the sequence of the data to be input and the length of the data are undefined. According to the variable-length code decoding system, it is possible to decode the data which is always input during one cycle. Accordingly, the image processing can be performed at higher speed.

Claims: A variable-length code decoding system comprising:- an input node to which is applied a variable-length code string containing a plurality of variable-length codes; a variable-length code decoding part (413) for detecting one of the variable-length codes within said variable-length code string and outputting a first data (S415) representing the code length of said detected variable-length code; a first latch circuit (411) for latching a second data (S407) representing the positions of the variable-length codes within said variable-length code string in response to a clock signal (CK), and outputting the latched second data (S411); and a regulating circuit coupled to said input node for shifting the positions of said variable-length codes within said variable-length code string; said decoding system being characterised by a second latch circuit (405) for latching the output (S403) of said regulating circuit in response to said clock signal (CK) and outputting the latched output (S405) to said variable-length code decoding part (413), and in that said regulating circuit comprises:- a first shifter (401) for shifting said variable-length code string (Di) by a shift amount represented by said second data (S411), and outputting said shifted variable-length code string as a first shift data (S401); and a second shifter (403) for shifting said first shift data (S401) by a shift amount represented by said first data (S415) and outputting said shifted first shift data to said second latch circuit (405) as a second shift data (S403), so that the variable-length code to be decoded by said variable-length code decoding part (413) becomes the leading code of said variable-length code string. A variable-length code decoding system according to claim 1 wherein said variable-length code decoding part (413) stores a plurality of variable-length codes to be decoded, each corresponding to said input variable-length code and each code length of said variable-length code to be decoded, said variable-length code decoding part (413) collating said variable-length codes with a plurality of objective variable-length codes to be decoded and outputting the code length of one variable-length code to be decoded which matches said variable-length code. A variable-length code decoding system according to either one of claims 1 or 2 further comprising an adder (407) for adding said first data (S415) to said latched second data (S411) and wherein the output of said adder (407) is outputted to said first latch circuit (411) as said second data (S407). A variable-length code decoding system according to any one of the preceding claims wherein said regulating circuit further comprises a reset circuit (409) for outputting a reset signal to the shift input (S) of said second shifter (403).

Inventors: KOMOTO EIJI, NAKAMURA TAKAO, KOMOTO, EIJI, NAKAMURA, TAKAO, KOMOTO, EIJI, OKI ELECTRIC INDUSTRY CO., LTD., NAKAMURA, TAKAO, OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1994
Main classification: G11C15
IPC codes: G11C15, G11C11, H03M7