Fast charging MOS capacitor structure for high magnitude voltage of either positive or negative polarity

Abstract: Depletion layer depth and semiconductor real estate occupation area shortcomings of MOS capacitor architectures that are fanned on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions (31,33), both of which are directly contiguous with the lightly doped lower plate layer (21,23,41) that underlies the capacitor's dielectric layer (15), and connecting both of these auxiliary heavily doped regions (31,33) to a common capacitor electrode terminal (39) for the lower plate of the capacitor. If a high negative charge is applied to the upper plate (17) overlying the thin dielectric layer (15), holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate (17), electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. An application of the MOS capacitor structure is its use in a single event upset immune memory cell formed on an insulating substrata.

Description: The present invention relates in general to integrated circuit architectures and is particularly directed to a novel MOS capacitor structure formed of a lightly doped semiconductor layer and having a very fast charging time for voltages of both positive and negative polarities. There are a number of integrated circuit architectures which require a capacitor having a very short charging time (e.g. of the order of a nanosecond or less), with a high magnitude bias voltage of either polarity. Such a capacitor may have a surface (e.g. silicon-on-sapphire (SOS)) structure, in which a surface insulator (e.g. oxide layer) forms the capacitor dielectric between a topside plate (e.g. doped polysilicon or metal) layer and an underlying plate layer (e.g. a doped silicon region). In many silicon-on-sapphire processes having a (epitaxial) silicon layer formed atop a sapphire support structure, it is possible to dope the epitaxial silicon layer at a sufficiently high impurity concentration, such that the depth of any depletion region formed in the silicon layer underlying the surface dielectric (oxide) is small relative to the thickness of the surface oxide. The capacitance of the resulting MOS capacitor structure is near its maximum attainable value under all bias conditions and the charging time is extremely small. Some manufacturing processes, however, do not readily accommodate doping that portion of the semiconductor layer underlying the thin oxide at a high impurity concentration, so that the lower plate of an MOS capacitor must be formed by way of a lightly doped region. In such a capacitor structure, the lightly doped region will go into a deep depletion condition in response to the application of a high charge of a polarity corresponding to that of the doped material (high negative charge for a lightly doped N semiconductor layer and high positive charge for a lightly doped P- semiconductor layer) . For such a lightly doped structure, the depletion depth is typically an order of magnitude greater than the oxide thickness, which significantly reduces the transient capacitance. One possible solution to such a deep depletion recovery problem would be to incorporate two such capacitors into the circuit and connect the capacitors in parallel, one capacitor having lightly doped N-material, contiguous with a more heavily doped N+ contact region, and another capacitor having lightly doped P- material, that is contiguous with a more heavily doped P+ contact region. Such a circuit configuration would ensure that the total capacitance of the capacitor pair is never below the dielectric (oxide) capacitance of either capacitor, Unfortunately, providing a pair of such capacitors means that the amount of semiconductor real estate used to form a single capacitor must be doubled for the two capacitor case. In prior art document US-A-4704625, a MOS capacitive structure is described which comprises a low doped substrate of a first conductivity type, a first doped region of the first conductivity type contacting the substrate, a second doped region of opposite conductivity type contacting said substrate, a dielectric layer over a region of the substrate adjacent the first and second regions and a conductive layer or said dielectric layer. In prior art document EP-A-0357980 a compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor used in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The capacitor in its preferred embodiment is a MOS capacitor with both n + and p + connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages. In prior art document US-A-4833644, a memory cell circuit is described, which has a pair of inverters and a means, such as gate-drain coupled capacitors, for providing a greater voltage difference at MOS transistor gates during radiation than an initial value. This is stated to tend to preserve the latch logic state and thus prevent a change in logic state during radiation. The said prior art document claims a memory cell circuit comprising: first and second cross-coupled inverters, each inverter having first and second complementary MOS series coupled transistors, each of said transistors having a pair of conduction electrodes and a gate input electrode, one of said conduction electrodes being an output electrode coupled to the output electrode of the respective complementary transistor; and a first capacitor coupled between said gate input electrodes of said first and second transistors of said first inverter, and the conduction output electrodes of said first inverter transistors, and a second capacitor coupled between said gate input electrodes of said first and second transistors of said second inverter, and the conduction output electrodes of said second inverter transistors. A semiconductor capacitance device in accordance with the present invention, is defined in claim 1. Conveniently, if a high negative, charge is applied to the upper plate (gate electrode) overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. If a high positive charge is applied to the upper plate electrons are readily supplied by the auxiliary N+ region. Namely, by connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. Moreover, since both P+ and N+ contacts are tied together, the tendency of an inversion layer to float (as occurs in a standard MOS capacitor, because the deep depletion layer forms a barrier between the inversion layer and a contact) is prevented. Also, the time required to charge the MOS capacitor is limited only by the mobility of the carriers in the semiconductor layer. Preferably, a useful application of the improved MOS capacitor structure according to the present invention is in a single event upset (SEU) immune memory cell formed on an insulating substrate (e.g. sapphire or oxide) using CMOS technology. In such a circuit structure, a pair of the MOS capacitors of the present invention are employed. Each capacitor is coupled between the input and output nodes of a respective one of the inverters of a cross-coupled inverter pair of which the memory is formed. Should a high energy particle pass through the channel region of an off transistor of one of the inverters, a large amount of charge is rapidly generated. Most of the charge is accumulated and swept across the 'OFF' MOS transistor's depletion region, which tends to change the voltage at the output of the inverter that has been hit by the particle. This voltage can change sufficiently to cause the other inverter of the cross-coupled inverter pair to switch, thus altering the state of the memory cell. One technique to minimize the effect of the particle hit is to add capacitance to sensitive nodes in the memory cell. In a bulk CMOS process, the capacitance is formed from a specific node to ground. As noted above, however, in the memory cell application of the present invention, because of the insulating substrata upon which the capacitor is formed, the capacitors are added between the output nodes of each inverter and their respective input nodes, In such a configuration, the capacitor across a respective inverter is able to quickly absorb positive charge from its positive channel MOSFET or negative charge from its associated negative channel MOSFET. In a conventional MOS capacitor structure, the same large signal capacitance would have to be achieved with a respective capacitor of each polarity and each with its own respective occupation area. In contrast, the dual polarity capacitance structure of the present invention allows the memory cell to be made smaller than comparable CMOS processes to achieve the same tolerance to high energy particles. The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 diagrammatically illustrates a sectional view of a silicon-on-sapphire capacitor MOS capacitor architecture in accordance with the present invention, in which a pair of auxiliary heavily doped contact regions are disposed at respective opposite end portions of the lower silicon plate layer of the capacitor; Figure 2 diagrammatically illustrates a sectional view of a silicon-on-sapphire capacitor MOS capacitor architecture which is not in accordance with the present invention, in which the lower plate contains only a single lightly doped semiconductor region; Figure 3 diagrammatically illustrates a top view of a silicon-on-sapphire capacitor MOS capacitor architecture which is not in accordance with the present invention, in which a pair of auxiliary heavily doped contact regions are contiguous with a common side portion of the lower silicon plate layer of the capacitor; and Figure 4 shows a memory circuit structure employing a pair of MOS capacitors in accordance with the present invention coupled between the input and output nodes of respective inverters of a cross-coupled inverter pair. A MOS capacitor structure in accordance with the present invention successfully addresses the depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor structures by augmenting the lightly doped, lower silicon plate layer of the MOS capacitor structure with a pair of auxiliary, opposite conductivity type, (P+ and N+) high impurity concentration regions. Both of the auxiliary regions are formed such that they are directly contiguous with the lower plate silicon layer that underlies the capacitor's surface oxide. The auxiliary regions are connected to a common capacitor electrode terminal for the lower plate of the capacitor. With this structure, if a high negative charge is applied to the top plate (gate electrode) overlying the capacitor's thin dielectric layer, holes are readily supplied by the auxiliary P+ region. If a high positive charge is applied to the gate electrode, electrons are readily supplied by the auxiliary N+ region. By connecting both auxiliary N+ and P+ regions together, a deep depletion rendition is prevented for either polarity of the applied voltage, Moreover, since both auxiliary P+ and N+ contacts are tied together, there is no tendency of an inversion layer to float, which occurs in a conventional MOS capacitor structure, since the deep depletion layer forms a barrier between the inversion layer and a capacitor contact. A non-limitative example of an MOS capacitor architecture in accordance with a first embodiment of the present invention is diagrammatically illustrated in the cross-sectional view of Figure 1 as comprising a silicon on-sapphire structure having a support (sapphire) substrate 11, upon which a very thin (having a thickness on the order of from 1000 to 10,000 Angstroms) silicon layer 13 is formed (e.g. by liquid phase epitaxy). Although the illustrated example is an SoS architecture, other materials, such as a layer of insulator material (e.g. oxide) or semiconductor (e.g. silicon) may be employed for the support layer. Disposed upon a first portion of thin semiconductor layer 13 is a thin insulator layer 15, which forms the dielectric field layer of the MOS capacitor. Insulator layer 15 may comprise a thin oxide layer having a thickness on the order of from 50 - 1000 Angstroms). Situated atop thin insulator layer 15 is layer 17 of conductive material, such as metal or (doped or undoped) polysilicon, which forms a first contact, top plate layer of the capacitor, to which a terminal 19 is connected. Directly underlying insulator layer 15, semiconductor layer 13 contains at least one lightly doped semiconductor region, shown in Figure 1, as a first (P-) semiconductor region 21 and a second (N-) semiconductor region 23, so that a capacitor structure is formed by the top plate layer 17, thin oxide layer 15 and a lower plate layer comprised of lightly doped silicon, here a pair of lightly and oppositely doped regions 21 and 23. By 'lightly doped' is meant a concentration C such that C*ToX*Area (where ToX is the oxide thickness of layer 15) is small compared to, or on the order of, the total charge that needs to be absorbed. As an example, the impurity concentration of lightly doped regions may be in a range up to a concentration on the order of 10 18 atoms/cm3. Semiconductor layer 13 further contains a first auxiliary (contact) semiconductor region 31 of a first (P+) conductivity type, having an impurity concentration on the order of 10 20 atoms/cm3, which is substantially higher than that of the lightly doped lower plate layer containing underlying regions 21 and 23. In the illustrated embodiment, the first (P+) contact semiconductor region 31 is directly contiguous with or contacts (P-) a first end 32 of lightly doped semiconductor region 21 of the capacitor's lower plate. In the embodiment of the present example, the lower plate of the MOS capacitor is also directly contiguous with a second contact semiconductor region 33 of a second (N+) conductivity type having an impurity concentration higher than that of regions 21 and 23 and being directly contiguous with or contacting an end 34 of (N-) doped region 23, which is opposite to the end 32 of the lower plate contacted by first (P+) contact region 31. Formed on contact regions 31 and 33 are respective layers 36, 38 of conductive material (e.g. metal) which are connected together and provide a second (lower plate) terminal 39 for the capacitor. Figure 2 illustrates a capacitor wherein the lower plate of the MOS capacitor structure contains only a single lightly doped semiconductor region 41 of a either P- or N- conductivity type, as known from US-A-4704625. A MOS capacitor wherein the contact to the lower plate is provided by way of opposite conductivity type, heavily doped regions, each of which is directly contiguous with a common side portion 51 of the lower plate of the capacitor, as known from EP-A-0357980 is diagrammatically illustrated in the plan view of Figure 3. One application of the improved MOS capacitor structure according to the present invention is its use in a single event upset (SEU) immune memory cell that is formed on an insulating substrata (for example, the sapphire substrate 11 of Figure 1). In such a memory circuit structure, schematically illustrated in Figure 4, a pair of MOS capacitors 61, 63, having a structural configuration in accordance with the present invention described above, are coupled between input and output nodes 71, 73 and 81, 83 of respective MOSFET inverters 70, 80 that comprise the memory cell's cross-coupled MOSFET inverter pair. Should a high energy particle pass through the channel region of an off transistor of one of the inverters 70, 80, a large amount of charge is rapidly generated. Most of the charge is accumulated and swept across the 'OFF' MOS transistor's depletion region, which tends to change the voltage at the output of the inverter taking the hit. This voltage can change sufficiently to cause the other inverter of the cross-coupled MOSFET inverter pair of the memory cell to switch to its opposite state (from a '1' to a '0' or from a '0' to a '1'). The coupling of MOS capacitors 61, 63 configured in accordance with the present invention to include the auxiliary high impurity concentration regions that contact the lower lightly doped plate of the capacitor minimises the effect of the particle hit, as each MOS capacitor that is connected across its associated inverter is able to quickly absorb positive charge from its positive channel MOSFET or negative charge from its associated negative channel MOSFET. As noted above, in a conventional MOS capacitor structure, the same large signal capacitance would have to be achieved with a respective capacitor of each polarity and each with its own respective occupation area. The depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are effectively obviated in accordance with the present invention by augmenting the MOS capacitor structure with a pair of auxiliary, opposite conductivity type, (P+ and N+) high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor, Should a high negative charge be applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. Moreover, since both P+ and N+ contacts are tied together, the tendency of an inversion layer to float (as occurs in a standard MOS capacitor, because the deep depletion layer forms a barrier between the inversion layer and a contact) is prevented. Further, the time required to charge the MOS capacitor is limited only by the mobility of the carriers in the thin epitasial semiconductor layer in which the capacitor's lower plate structure is formed. Depletion layer depth and semiconductor real estate occupation area shortcomings of MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. An application of the MOS capacitor structure is its use in a single event upset immune memory cell formed on an insulating substrata.

Claims: A semiconductor capacitor device comprising a semiconductor layer (13) containing a first lightly doped semiconductor region (21) of a first conductivity type and a second lightly doped semiconductor region (23) of a second conductivity type contiguous with said first semiconductor region, and forming a plate of said semiconductor capacitor device , an insulator layer (15) disposed upon said semiconductor regions (21,23) of said semiconductor layer; a conductive layer (17) disposed upon said insulator layer and providing a first contact for said capacitor device, so that a capacitor is formed between said conductive layer that is disposed atop said insulator layer and said semiconductor regions underlying said insulator layer; said semiconductor layer further containing a first contact semiconductor region (31) of a first conductivity type and having an impurity concentration higher than that of said semiconductor regions (21,23), said first contact semiconductor region (31) contacting a first portion of said first semiconductor region (21); said semiconductor layer further containing a second contact semiconductor region (33) of a second conductivity type and having an impurity concentration higher than that of said semiconductor regions (21,23), said second contact semiconductor region (33) contacting a second portion of said second semiconductor region (23), and conductive material (36,38) contacting said first and second contact semiconductor regions and providing a second contact for said capacitor device. A semiconductor capacitor structure as claimed in claim 1, wherein said semiconductor layer is disposed upon a support substrate which comprises insulator material. A semiconductor capacitor structure as claimed in claim 1, wherein said semiconductor layer is disposed upon a support substrate which comprises sapphire. An MOS memory cell structure comprising; a semiconductor layer containing a pair of crosscoupled MOSFET inverters having respective input and output modes, a first MOS capacitor coupled between the input and output nodes of a first inverter of said pair of cross-coupled MOSFET inverters, a second MOS capacitor coupled between the input and output nodes of a second inverter of said pair of cross-coupled MOSFET inverters, wherein each of said first and second MOS semiconductor capacitor is in accordance with claim 1 and comprises a respective portion of said semiconductor layer containing conductivity type determining impurities, said semiconductor layer being disposed upon a substrate which comprises insulator material, or semiconductor material.

Inventors: LOWTHER REX E, YOUNG DENNIS C, LOWTHER, REX E., YOUNG, DENNIS C.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1994
Main classification: H01L29
IPC codes: H01L27, H01L29