An integrated control circuit with a level shifter for switching an electronic switch

Abstract: A circuit for controlling a power transistor connected between two supply terminals (ground, V H ) is described, in series with a load (L) and comprising a control logic circuit (LG) which produces a signal at two levels with respect to a reference terminal (ground), a level shifter (LS1) connected between the control circuit (LG) and the power transistor (T1), and which produces a signal at two levels referred to the node (S1) between the power transistor (T1) and the load (L). The level shifter (LS1) includes a flip-flop (RS) the output of which controls the power transistor (T1) as well as two transistors (M10, M9) driven by the control logic circuit (LG) to switch alternatively and provide switchin signals on the "set" and "reset" inputs (S,R) of the flip-flop (RS) via two resistors (R4, R3). Two parasitic current generators (Tp1, Tp2) inject current into the two resistors (R4, R3) during the phase in which the power transistor (T1) is cut off. To prevent this current from causing unwanted switching of the flip-flop a resistor (R4) connected to the "set" terminal (S) of the flip-flop has a lower resistance than that of the other resistor (R3).

Description: The present invention relates to switching control circuits for electronic power switches and, more particularly, to a circuit of this type including a control signal level shifter. One known application of electronic power switches is in forming bridge circuits for the actuation of motors. These circuits include pairs of electronic switches connected in series between the poles of a high voltage power supply. The load, in this case a winding of the motor, is connected between the connection points of the switches of the pairs. The switches of each pair are controlled in such a way that at any instant at most one of the two is closed. That is to say it cannot happen that both switches of a pair are simultaneously closed. The electronic switches are controlled by low voltage logic circuits which produce control signals at two levels referred to a reference voltage which, normally, is also the earth terminal of the circuit arrangement. For controlling the switches of the bridge connected to the positive pole of the power supply the level of the logic circuit signals is shifted by means of suitable level shifter circuits. A typical structure of a control circuit with a level shifter is schematically represented in Figure 1 of the attached drawings. Four power transistors, for example field effect transistors (FET) of n channel DMOS type, indicated T1, T2, T3 and T4 are connected in series in pairs between the terminals, indicated with the earth symbol and V H , of a relatively high voltage DC power supply, for example 300 volts. A load L, for example a winding of a motor not further shown, is connected between the connection nodes of the switches of the two pairs. A control logic circuit, indicated LG, produces control signals at two voltage levels, for example the ground level, or zero, and a relatively low supply voltage level V LL , typically five volts. These signals, available on the outputs of the logic circuit LG are applied to the control terminals, that is to say the gate electrodes both of the "lower" transistors T2, T4 through respective driving circuits, and the "upper" transistors T1, T3, through respective level shifting and driving circuits, to switch the transistors on or off (conduction or cut-off) according to the sequence determined by the logic circuit LG. For simplicity of the drawing only the driving circuits DR1 and DR2 for the transistors T1 and T2 and only the level shifter LS1 relating to the transistor T1 are shown; it is understood that similar circuits are provided for control of the transistors T3 and T4. The driving circuit (DR2) of the transistor T2 is supplied with a relatively low voltage V L , for example 12 volts, sufficient to raise the gate electrode of T2 to a voltage, with respect to its source terminal (which is connected to ground) greater than the conduction threshold. The driving circuit DR1 of the transistor T1 is supplied with a voltage V C the value of which is substantially equal to V L provided by a "buffer" capacitor C connected between the connection node S1 (between the two transistors T1 and T2) and a charging circuit, not shown, the function of which is to maintain the capacitor C charged to the voltage V C . The level shifter LS1 includes two substantially identical circuit branches each constituted by an n channel MOS transistor M1, M2 the source terminal of which is connected to the ground terminal and the drain terminal of which is connected to the supply terminal V C via the parallel connection of a resistor R1, R2 and a zener diode D1, D2. The gate terminals of the transistors M1 and M2 are connected to an output of the logic circuit LG, one directly and the other through an inverter INV1, such that the control signals which arrive at the two transistors are always complementary to one another. The level shifter LS1 also includes a bistable (flip-flop) circuit, indicated RS, supplied with the voltage V C , and having "set" and "reset" terminals S, R respectively, connected via respective inverters INV2 and INV3 to the drain electrodes, respectively, of transistors M1 and M2, and an output terminal Q connected to the input of the driving circuit DR1 of transistor T1. In operation the two transistors M1 and M2 are alternatively brought to a conduction state by signals generated by the logic circuit LG. The current pulses which form in succession in the two resistors R1 and R2 produce the "set" and "reset" signals at the inputs S and R of the flip-flop RS and, consequently, the output signal Q from the flip-flop, which is referred to the voltage level of the node S1 (which varies substantially between 0 and V H in dependence on the state of conduction of the transistors of the bridge), causes the driving circuit DR1 to apply a voltage signal between the gate and source electrodes of the transistor T1, a voltage signal which switches on or off the transistor T1. The circuit described above can be improved, in a manner which will be illustrated hereinbelow, to ensure that during switching of the node S1 between 0 and V H , both the inputs of the flip-flop are at low level. However, both the circuit of Figure 1 and the thus-improved circuit are subject, when forming part of a monolithic integrated circuit, to possible spurious switching such that they cannot be utilised when it is essential to achieve absolute security in operation of the transistor bridge. Spurious switching is due to the structure capacitances associated with the transistors M1 and M2. These capacitances, generally indicated C1 and C2 in Figure 1, are the sum of the capacitances between drain and source and between drain and substrate. In certain conditions, as will be explained in more detail hereinbelow in relation to a particular circuit, during discharge of these capacitances, which takes place in part through the zener diodes, D1 and D2 and in part through the resistors R1 and R2, the conduction of parasitic components is triggered due to the structure of the integrated circuit in which the various components of the switching control circuit are formed, which can lead to switching signals at the flip-flop which are not those caused by the control signal and which can therefore cause very serious malfunctions. The object of the present invention is to provide a switching control circuit with a level shifter for an electronic power switch in which spurious switching is not possible in any case. This object is achieved according to the invention by a circuit as defined and characterised in general in the first and second of the claims which follow the present description. The invention will be better understood from the following detailed description of an exemplary, and therefore non-limitative embodiment in relation to the attached drawings, in which: Figure 1, already described, is a diagram of a known switching control circuit applied to a transistor bridge; Figure 2 is a diagram of a switching control circuit to which the invention is applied; Figure 3 is a detail of the diagram of Figure 2 in which parasitic components not shown in Figure 2 are indicated; and Figure 4 schematically shows the relative arrangement of some components of the integrated circuit. The circuit of Figure 2, in which parts which are the same as or correspond to those of Figure 1 are indicated with the same reference symbols, is different from that of Figure 1 substantially in that the input terminals S and R of the flip-flop RS are not connected to the drain electrodes of the transistors M1 and M2 through inverters, but through a coupling stage which comprises two p channel MOSFETs, indicated M9 and M10. These are each connected with a respective series resistor R3 and R4 between the drains of the transistors M2 and M1 and the node S1, and have their gate electrodes connected to the source electrode of the other transistor of the pair. The current injected alternately into the resistors R1 and R2 during conduction of the transistors M1 and M2 respectively, causes conduction of the transistors M9 or M10 respectively such that across the resistors R3 or R4 there is a voltage drop which gives rise to the "reset" or "set" signals on the flip-flop RS. This circuit offers the advantage over the circuit of Figure 1 of maintaining the condition of low level signals S=0, R=0 on both inputs of the flip-flop during switching of the node S1. This is important in particular when the node S1 switches to a high voltage level, that is to say varies from 0 to V H . However, discharge of the capacitances C1 and C2 can cause spurious signals. In particular, if the circuit of Figure 2 is made as an integrated circuit using the usual fabrication techniques, parasitic bipolar transistors of pnp type are formed which constitute parasitic current generators associated with the p channel MOSFET transistors M10 and M9, and the effect of which can be evaluated by examining the equivalent diagram of Figure 3. As is seen, this shows two double collector transistors indicated Tp1 and Tp2, each having its emitter region in common with the source region of a respective p channel MOSFET transistor M10 and M9, its base region connected to the supply terminal V C and two collector regions in common with the drain regions of M10 and M9 connected to the input terminals S and R of the flip-flop. In the discharge phase of the capacitances C1 and C2 the two transistors Tp1 and Tp2 inject a current into the resistors R3 and R4. This takes place, in particular, in the switching phase of the node S1 from the higher level to the lower level when the power transistors T1 and T2 are, respectively, off and on. In this phase both the inputs of the flip-flop are at the higher level, that is to say in a state which does not in general correspond to a well defined output state of the flip-flop. To prevent this condition from causing an output of the flip-flop corresponding to a switching on of the power transistor T1, it is advisable to utilise a flip-flop of the "dominant reset" type, that is to say which has a low output level when the inputs are both at high level. However, even in this case, at the end of the transition of the node S1 from V H to 0 with the transistor T1 in the cut-off state, there is the risk that the flip-flop will enter the input condition which would take the transistor T1 back into conduction during the conduction of the lower transistor T2, this situation being highly undesirable. In fact, the voltage levels on the inputs S and R of the flip-flop, once the parasitic injection has ceased, tend to fall to the level of the node S1 gradually so that the capacitances associated with the two terminals S and R discharge through the resistors R4 and R3 until the so-called memory state (S=O, R=O) of the flip-flop is reached. In this condition the output state Q will be determined by that of the two levels which falls fastest. For example, in the case of a more rapid fall of the input R there would be the unwanted condition S=1, R=0 which would take the power transistor T1 into conduction. According to the invention, in order to prevent this from happening the resistor R3, connected to the "reset" input (R) has a greater resistance than that of the resistor R4 connected to the "set" input (S). Thus, with the same charge injected by the parasitic generators into the resistors R3 and R4, the level of the "set" terminal falls more rapidly than that of the "reset" terminal by the effect of the smaller time constant, so that at the end the output Q always corresponds to the state S=0, R=1. In another embodiment of the invention the layout of the integrated circuit, that is to say the arrangement of the circuit components, is chosen in such a way that, during switching, the overall currents injected by the two parasitic current generators into one resistor and into the other resistor are not equal to one another but such that the overall current injected into the resistor connected to the "reset" input (R) is greater than that injected into the other resistor. In this case, even if the resistors R3 and R4 are equal, the level of the "set" terminal falls more rapidly than that of the "reset" terminal because the charge of the capacitance associated with the "set" terminal will be less than that of the capacitance associated with the "reset" terminal. One way of obtaining this result is to dispose the transistors M10 and M9 at a different distance from the centre of the areas in which the associated diodes D1 and D2 are formed. For example, as is shown in Figure 4, the distance d1 between M10 and the diodes D1 and D2 is greater than the distance d2 between M9 and the same pair of diodes. This exploits the fact that, with the usual fabrication processes for this type of integrated circuit, the gain of the parasitic pnp transistors Tp1, Tp2 is strongly influenced by these distances d1 and d2. Naturally, the two above-described arrangements, that is to say that relating to the dimensioning of the two resistors R3 and R4 and the topological arrangement relating to the mutual disposition of the transistors M10, M9 and the diodes D1 and D2, can be utilised contemporaneously thus increasing the security of operation of the circuit. As can be easily established, the object of the invention is fully achieved in that the risk of spurious switching is entirely avoided. It is noted moreover that this effect is obtained without additional circuit components, but simply by dimensioning and/or suitably arranging some already existing components.

Claims: An integrated control circuit for switching an electronic power switch (T1) connected in series with a load (L) between first and second supply terminals (ground, V H ) comprising a control logic circuit (LG) adapted to produce an output signal having two voltage levels referred to the voltage level of a reference terminal (ground), a level shift circuit (LS1) the input of which is connected to the output of the control logic circuit (LG) and an output of which is connected to the control terminal of the electronic switch (T1), and adapted to produce at its output a signal having two voltage levels, corresponding to the signals from the control logic circuit, referred to the voltage level of the connection node (S1) between the electronic switch (T1) and the load (L), this level shift circuit (LS1) comprising a bistable stage (RS) having a "set" input (S), a "reset" input (R) and an output (Q) which is the output from the level shift circuit, first and second circuit branches connected between the said connection node (S1) and a third supply terminal (V C ), respectively comprising a first transistor (M10) and a second transistor (M9) connected to the control logic circuit (LG) to be switched alternatively, a first resistor (R4) and a second resistor (R3) connected between the connection node (S1) and, respectively, the first transistor (M10) and the second transistor (M9), the first resistor (R4) being connected to the "set" input (S) and the second resistor (R3) being connected to the "reset" input (R) of the bistable stage (RS), and first and second parasitic current generators (Tp1, Tp2), respectively associated with the first and second transistors (M10, M9) and adapted to inject substantially the same current into the first and second resistors (R4, R3) respectively, whereby the first resistor (R4) has a smaller resistance than that of the second resistor (R3). An integrated circuit for controlling the switching of an electronic power switch (T1) connected in series with a load (L) between first and second supply terminals (ground, V H ) comprising: a control logic circuit (LG) adapted to produce an output signal at two voltage levels referred to the voltage level of a reference terminal (ground), a level shift circuit (LS1) the input of which is connected to the output of the control logic circuit (LG) and the output of which is connected to the control terminal of the electronic switch (T1) and which is adapted to produce at its output a signal at two voltage levels corresponding to the control logic circuit signal, referred to the voltage level of the connection node (S1) between the electronic switch (T1) and the load (L), this level shift circuit (LS1) comprising a bistable stage (RS) having a "set" input (S), a "reset" input (R) and an output (Q) which is the output from the level shift circuit, first and second circuit branches connected between the said connection node (S1) and a third supply terminal (V C ), respectively comprising first and second transistors (M10, M9) connected to the control logic circuit (LG) to be switched alternatively, first and second resistors (R4, R3) connected between the connection node (S1) and the first and second transistor (M10, M9) respectively, the first resistor (R4) being connected to the "set" input (S) and the second resistor (R3) being connected to the "reset" input (R) of the bistable stage (RS), and first and second (Tp1, Tp2) parasitic current generators, associated, respectively, with the first transistor (M10) and the second transistor (M9) and adapted to inject current into the first resistor (R4) and the second resistor (R3), whereby the arrangement of circuit components is chosen in such a way that the overall current injected, during switching, by the first and second current generators, (Tp1, Tp2) into the second resistor (R3) is greater than that injected by the same generators into the first resistor (R4). An integrated circuit according to Claim 2, in which the first and second transistors (M10, M9) are p channel MOSFET transistors the drain terminals of which are connected to the first and second resistors (R4, R3) respectively, in which the first and second circuit branches include respective first and second diodes (D1, D2) connected between the source terminals of the first and second transistors (M10, M9) respectively and the third supply terminal (V C ), and in which the first and second current generators are parasitic bipolar transistors (Tp1, Tp2) of pnp type having their emitter regions in common with the respective source region of the first and second transistors (M10, M9), a base region connected to the third supply terminal (V C ), and each having two collector regions which are in common with respective drain regions of the first and second transistors (M10, M9), the first transistor (M10) being formed in an integrated circuit zone which is located at a distance from the centre of the zones in which said first and second diodes (D1, D2) of the level shift circuit are formed which is greater than the distance between the zone in which the second transistor (M9) is formed and the centre itself.

Inventors: DIAZZI CLAUDIO, MARTIGNONI FABRIZIO, TARANTOLA MARIO, DIAZZI, CLAUDIO, MARTIGNONI, FABRIZIO, TARANTOLA, MARIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H03K17
IPC codes: H02P7, H03K17