Voltage-to-current conversion circuit

Abstract: A voltage-to-current conversion circuit is disclosed which includes a MOS transistor of a source-grounded type having a gate connected to an input terminal, an output circuit producing an output current at an output terminal in response to a drain current of the transistor, and a control circuit maintaining the drain voltage of the transistor to such a value that has the transistor operates in a non-saturation (triode) region.

Description: BACKGROUND OF THE INVENTION The present invention relates to a voltage-to-current conversion circuit and, more particularly, to such a circuit as utilizing insulated gate field effect (MOS) transistors. A voltage-to-current conversion circuit is essential to a signal processing circuit handling an analog signal and thus is widely employed therein. This circuit fundamentally uses a current mirror circuit composed of transistors. There are two types in such a circuit, a bipolar type and a MOS type. The voltage-to-current conversion circuit of the bipolar type is typically disclosed in US-A-4 560 920. The basic circuit construction thereof is shown in Fig. 3 attached herewith (and corresponds to Fig. 5 of the above patent No.). Specifically, this circuit includes a current mirror circuit composed of PNP bipolar transistors 20 and 22, an input resistor 60, a constant current source composed of an NPN bipolar transistor 21, a resistor 61 and a constant voltage source 80, and an operational amplifier 40 which are connected as shown. The amplifier 40 cooperates with the transistor 20 to form a strong negative feedback loop. Accordingly, the current flowing through the resistor 60 in response to an input signal voltage supplied to an input terminal 90 is determined by the resistance value of the resistor 60 and the voltage amplitude of the input signal voltage. This current is supplied to the transistor 20 and thus derived from an output terminal 91 through the transistor 22 as the mirror current. The voltage-to-current conversion is thus attained. This circuit can handle a relatively large input voltage and further operate under a relatively low power voltage (1.8 V). The conversion circuit of the MOS type shown in Fig. 4 is also known in the art. This circuit also includes a current mirror circuit composed of P-channel MOS transistors 30 and 32 and an operational amplifier 41. However, this circuit converts the input signal voltage into the current by an N-channel MOS transistor 31, a resistor 62 and the amplifier 41 and then produces the converted current through the current mirror circuit. Specifically, the negative feedback loop composed of the transistor 31 and the amplifier 41 causes the input signal voltage to appear across the resistor 62. The current determined by the resistance value of the resistor 62 and the voltage amplitude is thereby derived from the output terminal 91 through the transistor 31 and the current mirror circuit. This prior art circuit is advantageous in having a high input impedance due to the operational amplifier 41 receiving the input voltage. Referring again to Fig. 3, the bipolar transistors constituting this circuit can be replaced by MOS transistors. However, the circuit thus replaced requires a power supply voltage larger than that applied to the circuit of Fig. 3. This is because the threshold voltage and the saturated voltage of the MOS transistors are higher than those of the bipolar transistors. Therefore, the conversion circuit of Fig. 3 is preferable for use in a low power voltage system. However, the input impedance is determined by the resistor 60 and thus cannot be enhanced. A source follower circuit is, for example, required to enhance the input impedance, so that the amplitude of the input voltage is restricted. On the other hand, the circuit shown in Fig. 4 has a high input impedance, as described hereinbefore. However, the source voltage of the transistor 31 is increased in accordance with an increase in the voltage of the input signal. For this reason, a relatively high drain voltage is needed. Thus, the power supply voltage is required to be high, or else the voltage of the input signal voltage is restricted. IEEE Journal of Solid-State Circuits, Vol 25 no 1, February 1990, New York, United States, pages 289-298 describes a regulated cascade circuit comprising a transistor T 1 , having a gate for receiving an input voltage and a source connected to circuit ground. The transistor converts the input voltage into a drain current which flows through the drain-source path of transistor T 2 to an output terminal. The drain-source voltage of the transistor T 1 is regulated to a fixed value by a feedback loop consisting of an amplifier and transistor T 2 as a follower. In the circuit described in European Transactions on Telecommunications and Related Technologies, vol 2, no. 4, July 1991, Milan, pages 441-446, an input transistor M1 is operated in the triode region with an adjustable constant drain-to-source voltage. The drain-source voltage of transistor M 1 is shifted upwards by a transistor M 4 and applied to the input of an inverter which acts as an active load. The present invention provides a voltage-to-current conversion circuit comprising a first transistor operated in a non-saturation region having a gate connected to a voltage input terminal and a source connected to a reference voltage line, output means coupled to a drain of said first transistor for leading a drain current of said transistor to an output terminal, and a second transistor having a source connected to the reference voltage line, characterised in that said voltage-to-current conversion circuit further comprises: control means coupled to a gate and a drain of said second transistor to control said second transistor such that said second transistor operates in a non-saturation region, bias means coupled between the drain of said first transistor and the drain of said second transistor to bias the drain of said first transistor by a predetermined voltage relative to a drain voltage of said second transistor to cause said first transistor to operate in the non-saturation region. Thus, the first and second transistors operate with a source connected to a reference voltage line, such as circuit ground, and in the non-saturation region. Accordingly, the transistors can handle large input voltage with a low power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrative of a first embodiment according to the present invention; Fig. 2 is a circuit diagram illustrative of a second embodiment according to the present invention; Fig. 3 is a circuit diagram illustrative of a prior art; and Fig. 4 is a circuit diagram illustrative of another prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, a voltage-to-current conversion circuit according to the first embodiment of the present invention includes seven P-channel MOS transistors 1, 2, 4, 6, 7, 11 and 12, five N-channel MOS transistors 3, 5, 8, 9 and 10, three resistors 50, 51 and 52 and a current source 70 which are connected as shown. Each of the transistors 3, 5 and 8 has its threshold voltage of about 0 V, each of the remaining transistors has its threshold voltage of 0.6 to 0.8 V. The transistors 1, 4 and 6 cooperate with one another to constitute a current mirror circuit and hence the constant current for the current source 70 is derived from the transistors 4 and 6. The current from the transistor 6 produces a constant voltage drop across the resistor 51, which voltage drop biases the transistor 5. It should be noted that although the transistor 5 could pass a current corresponding to the voltage biased by the resistor 51, the current actually flowing through the transistor 5 is the same as the current from the transistor 4. Representing the resistance value of the transistor 4, each of the drain current of the transistors 4 and 6, and the gate-source voltage of the transistor 5 as R O , I B , and V GS5 , respectively, the following equation (1) is obtained: V GS5 = R O × I B That is, the transistor 5 could pass the current corresponding to the bias voltage V GS5 indicated in (1), but the current I B flows in fact therethrough. Therefore, it becomes possible to make the transistor 5 operate in the non-saturation or triode region by designing the current I B to a value as follows: I B << µn C ox W 2L (V GS5 - V TO ) 2 wherein W and L represents the gate width and length of the transistor 5, V TO represents the threshold voltage thereof, µn represents the surface mobility of electrons and C ox represents the gate capacitance per unit. The drain voltage V x of the transistor 5 operating in the non-saturation region is represented as follows and takes a value of 0.1 to 0.2 V which is very close to zero: I B = µn C ox ( W L )(R O I B - V TO ) V x - 1 2 µn C ox ( W L )V x 2 As described hereinbefore, the threshold voltage V TO is about zero voltage and the drain voltage V x thereof is very close to zero, and therefore the equation (3) can be rewritten as follows: I B = µn C ox ( W L ) R O I B V x The drain voltage of the transistor 5 operating in the non-saturation (triode) region is converted into a current by the transistor 3 and the resistor 50, and the current thus converted is supplied to the transistor 2 and thus appears as a drain current of the transistor 7. This is because the transistors 2 and 7 form a current mirror circuit. The drain of the transistor 7 is connected to a circuit composed of the transistor 8 and the resistor 52. The transistor 10 is connected to the transistor 8 to form a negative feedback loop. Accordingly, the same current flows through the transistors 3 and 8 when the sizes of the transistors are identical with each other, the resistors 50 and 52 have the same values as each other and the current gain of the current mirror circuit composed of the transistors 2 and 7 is 1. In other words, the gate of the transistor 8 is applied with and fixed to such a voltage that makes the current flowing through the transistor 3 equal to the current flowing through the transistor 8. The gate voltage of the transistor 8 is equivalent to the drain voltage V x of the transistor 5. Since the drain of the transistor 9 is connected to the gate of the transistor 8, the drain voltage of the transistor 9 becomes to be equal to and maintained to the voltage V x . That is, the transistors 8 and 10 and the resistor 52 converts the current, which is obtained by converting the drain voltage of the transistor 5 operating in the non-saturation region, again into the voltage corresponding thereto. Thus, the transistor 9 also operates in the non-saturation (triode) region similarly to the transistor 5, and the drain current thereof is represented as follows: I D9 = µn C ox ( W L ) V x V GS9 From the equations (4) and (5), we obtain the following: I D9 = (1/R O ) × V GS9 . Since the current gain of the current mirror circuit composed of the transistors 11 and 12 is one, the output current I OUT derived from the output terminal 91 is equal to the current I D9 , and represented as follows: I OUT = (1/R O ) × V IN . wherein the input signal voltage V IN is equal to the gate-source voltage V GS9 the transistor 9. Thus, the present circuit performs the voltage-to-current conversion operation on the input signal voltage. Moreover, the conversion operation is being performed so long as the transistor 9 operates in the non-saturation region, and therefore the amplitude of the input signal is not limited. On the other hand, the minimum power supply voltage allowing the present circuit to operate is determined by the gate-source voltage of the transistor 10 and the sum of the drain-source voltages of the transistor 7 and 9 and takes a value of about 2 V. The resistors 50 and 52 are provided for the purpose of reducing the power consumption and therefore may be omitted. Turning to Fig. 2, there is shown a circuit according to a second embodiment of the present invention, wherein the same constituents as those shown in Fig. 1 are denoted by the same reference numerals to omit the further description thereof. in this circuit, all the transistors are designed to have the conventional threshold voltage, 0.6 to 0.8 V. Therefore, a diode-connected N-channel MOS transistor 13 is added in series with the resistor 51 to bias the transistor 5. Since the circuit operation of this circuit is identical with that of the circuit of Fig. 1 and thus will be omitted. Since the transistor 9 is designed to have the above threshold voltage, the present circuit converts the input signal having an amplitude from the threshold voltage to the power supply voltage, whereas the circuit of Fig. 1 handles the input signal having an amplitude from about zero to the power supply voltage. However, the present circuit is derived at lower cost than the circuit of Fig. 1 because of all the transistors having the same threshold voltage. It is apparent that the present invention is not limited to the above embodiments but may be modified and changed without departing from the scope of the invention as defined by the appended claims. For example, the current gain of each current mirror circuit can set to a desired value other one. The channel types of the respective transistors are changeable.

Claims: A voltage-to-current conversion circuit comprising a first transistor (9) operated in a non-saturation region having a gate connected to a voltage input terminal (90) and a source to a reference voltage line (GND), output means (10) coupled to a drain of said first transistor for leading drain current of said transistor to an output terminal (91), and a second transistor (5) having a source connected to the reference voltage line, characterised in that said voltage-to-current conversion circuit further comprises: control means (1, 4, 6, 51, 70) coupled to a gate and a drain of said second transistor to control said second transistor such that said second transistor operates in a non-saturation region, bias means (2, 3, 7, 8, 1()) coupled between the drain of said first transistor and the drain of said second transistor to bias the drain of said first transistor by a predetermined voltage relative to a drain voltage of said second transistor to cause said first transistor to operate in the non-saturation region. A circuit as claimed in claim 1, wherein said control means includes means (51) for supplying a bias voltage between the gate and the source of said second transistor and means (1, 4, 6, 70) for supplying said second transistor with a current that is smaller than a current which said second transistor has an ability to produce in response to said bias voltage, and said bias means includes first converting means (3) for converting the drain voltage of said second transistor into a first current, a second converting means (8,10) for converting said first current into a first voltage and means (10) for supplying said first voltage to the drain of said first transistor as said predetermined voltage. A circuit as claimed in Claim 2, wherein said first converting means includes a third transistor (3) having a gate connected to the drain of said second transistor and a source connected to the reference voltage line, and said second converting means includes a fourth transistor (8) having a gate connected to a drain of said first transistor and a source connected to the reference voltage line, said third transistor producing a drain current which is supplied to said fourth transistor as a drain current thercof. A circuit as claimed in Claim 3, wherein said bias means further includes a current mirror circuit (2,7) having an input node connected to a drain of said third transistor and an output node connected to the drain of said fourth transistor. A circuit as claimed in any of Claims 3 to 4, wherein said first converting means further includes a first resistor (50) being connected between the source of said third transistor and said reference voltage line, and a second transistor (52) being connected between the source of said fourth transistor and said reference voltage line. A circuit as claimed in any of Claims 3 to 5, wherein said third transistor has the same transistor size as said fourth transistor. A circuit as claimed in Claims 3 or 4, wherein said output means includes a fifth transistor (10) having a gate and a source connected respectively to the drain and the gate of said fourth transistor, said output current being lead through said fifth transistor. A circuit as claimed in Claim 7, wherein said output means further includes a current mirror circuit (11,12) having an input node connected to a drain of said fifth transistor and an output node connected to said output terminal. A circuit as claimed in Claim 7 or 8, wherein each of said first, second, third, and fourth transistor has a threshold voltage smaller than a threshold voltage of said fifth transistor. A circuit as claimed in any of Claims 7 to 9, wherein said first to fifth transistors have equal thresholds.

Inventors: ETOH TOSHIYUKI, ETOH, TOSHIYUKI, ETOH, TOSHIYUKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03F3
IPC codes: H03F3