Apparatus and method for achieving high-speed data read access to memory

Abstract: An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes a data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage means output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage means hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.

Description: Field of the Invention The present invention relates to an apparatus and method for achieving a high-speed data read access to contiguous areas in memory such as frame buffers, without employing burst transmission techniques. Description of the Related Art Cache memory has been commonly used in order to achieve high-speed data read access to memory. Cache memory was originally supplied to main memory to speed up its low access rate by the use of cache, but has recently been supplied, as disk cache memory, to secondary memory such as hard disk. However, some memory or memory areas are not cachable depending on their usage. For example, a frame buffer which stores display data or image data to be displayed on a display device is not cachable because the contents of these data are directly displayed on the display device. FIG. 1 shows the construction of a typical conventional apparatus for achieving high-speed data read access to noncachable memory. In the illustration, the typical conventional apparatus 61 is provided with a bus address and control signal decoder 611, a memory address and control signal generator 612, a memory data controller 613, and a bus data controller 614, thereby controlling data access from a processor (not shown) to memory 62 via a system bus 60. The bus address and control signal decoder 611 (hereinafter referred to as BA decoder 611) decodes the address and size of data sent through the system bus 60. The memory address and control signal generator 612 (hereinafter referred to as MA generator 612) generates a row address and a column address, based on the results found out by the BA decoder 611, thereby sending it to the memory 62. The memory data controller 613 (hereinafter referred to as MD controller 613) controls data input/output operations between the BD controller 614 and the memory 62. The bus data controller 614 (hereinafter referred to as BD controller 614) controls data input/output operations between the MD controller 613 and the system bus 60. The apparatus 61 provided with these components operates as follows. FIG. 2 shows a time chart depicting a data readout operation carried out by the apparatus 61. Receiving signals indicating the address and size of data to be accessed through the system bus 60, the BA decoder 611 decodes the signals. The MA generator 612 generates a row address and a column address, based on the results decoded by the BA decoder 611, thereby starting to access the memory 62. After a certain period of access time, data read out from the memory 62 are sent out to the system bus 60 through the MD controller 613 and the ED controller 614. FIG. 3 shows a time chart depicting a data readout operation when data to be accessed are larger than the memory 62 in width. This case is called burst transmission, where the MA generator 612 performs page mode access by outputting serial column addresses on end to the memory 62. This allows a plurality of data to be sent out to the system bus 60 within a short time period. As explained hereinabove, according to the conventional apparatus, control signals to the memory 62 are generated by the MA generator 612 in response to an access request sent through the system bus 60. And access to contiguous areas, which frequently occurs is controlled by page mode access, thereby achieving a high-speed data access. However, the conventional apparatus has the following drawback. Burst transmission is not requested on noncachable memory such as frame memory and VRAM, or noncachable memory area so that contiguous areas in such memory are accessed normally, demanding the same amount of time for each access. As a result, high-speed data access cannot be achieved. Examples of conventional apparatus are set out below. EP-A-0 604 139, which is only available as prior art under Article 54(3) EPC, describes a computer system including a prefetch cache. The system is specifically tailored to provide faster caching of out of sequence processor instructions such as branch instructions. EP-A-0 293 720 and IBM TECHNICAL DISCLOSURE BULLETIN vol. 31, no. 3, August 1988, NEW YORK US pages 303 - 306 'High performance micro processor system' both describe basic cached memory systems. Both systems incorporate a prefetch instruction function based on calculation of a next memory address to be accessed. EP-A-0 505 157 describes a memory access control unit which is capable of executing block memory transfers using burst transmission techniques. The control unit manipulates memory addresses in order to calculate the desired memory block to be read. SUMMARY OF THE INVENTION A first object of this invention is to provide an apparatus for achieving a high-speed data read access to contiguous areas in memory. A second object of this invention is to provide a method for achieving a high-speed data read access to contiguous areas in memory. The first object can be achieved by the following apparatus for controlling high-speed data read access to contiguous areas in a memory, in response to an access request sent through a system bus. More particularly, according to the present invention, there is provided an apparatus for controlling high-speed data read access, without employing burst transmission techniques, to contiguous areas in a memory such as a frame memory or a VRAM, in response to an access request sent through a system bus, the apparatus comprising: a data storage means for preserving data corresponding to a predetermined address; a judging means for judging whether an access address indicated by said access request matches the predetermined address and for making said data storage means output data preserved therein to the system bus when said access address has been judged to match the predetermined address, and for making said data storage means hold data corresponding to a next address subsequent to said access address when said access address has been judged not to match the predetermined address, said judging means comprising: an address storage means for preserving an address indicating said data latched by said data storage means; wherein the judging means further comprises: a validity judging means for judging whether the data preserved in said data storage means are valid or invalid; a hit judging means for judging whether said access address matches the address preserved in said address storage means and for judging that said access address does not match the address preserved in said address storage means, when said validity judging means has judged the data to be invalid; and characterised in that the judging means (42) further comprises a data size judging means for detecting whether the access data has a smaller data width than said memory and does not include a final position of the data width of said memory and for informing an address generation means (51) of a result detected by said data size judging means, and in that said judging means comprises: said address generation means for generating said next address when said access address has been judged to match the address preserved in said address storage means, for generating said access address and said next address in sequence and forwarding to said judging means when said access address has been judged not to match the address preserved in said address storage means, and for suspending generation of said next address when the result detected by said data size judging means has been received; and a latch control means for, when data corresponding to said next address has been read out from said memory, making said data storage means latch said data. The apparatus may be combined with a memory and the memory may be a non-cachable frame memory for storing image data. In the case where the above memory is a frame memory the above-mentioned next address may indicate data subsequent to data corresponding to the access address, the data indicated by the next address having the same data width as the memory. The above-mentioned data storage means may include the following means: a data latch means for latching the data outputted from the memory; and a selection means for selecting the data latched by the data latch means when the access address has been judged to match the predetermined address and for selecting data outputted from the memory when the access address has been judged not to match the predetermined address, thereby forwarding selected data to the system bus. The address generation means may include the following: a first incrementer for incrementing the access address; a first selector for selecting an output of the first incrementer when the access address has been judged to match the address preserved in the address storage means and selecting the high order address when the access address has been judged not to match the address preserved in the address storage means; a latch circuit for latching an output of the first selector; a second incrementer for incrementing the output of the first selector; and a second selector for selecting an output of the latch circuit when the access address has been judged to match the address preserved in the address storage means and for selecting the output of the latch circuit and then selecting an output of the second incrementer, thereby outputting the output of the second incrementer as an access address to the memory when the access address has been judged not to match the address preserved in the address storage means. According to the apparatus with the above-mentioned construction, high-speed access to contiguous areas in memory such as frame memory and VRAM, or memory area can be achieved without burst transmission. The second object can be achieved by the method described below for controlling data read access in an apparatus as described above. More particularly, the present invention extends to a method for controlling data read access in an apparatus described above, said method comprising: judging whether said access address matches the predetermined address in response to the access request; when said access address has been judged to match the predetermined address: outputting the data held in said data storage means to the system bus; reading the data stored at said next address of the memory; and storing the read data to said data storage means; when said access address has been judged not to match the predetermined address: reading the data stored at the access address of the memory; outputting said data corresponding to said access address; reading the data stored at said next address of the memory; and storing said data of said next address to said data storage means, wherein said judging step comprises: preserving an address indicating said data latched by said data storage means; wherein judging whether the data preserved in said data storage means are valid or invalid; judging whether said access address matches the address preserved in said address storage means; and judging whether said access address does not match the address preserved in said address storage means, when said validity judging means has judged the data to be invalid; and characterised in that the judging step further comprises detecting whether the access data has a smaller data width than said memory and does not include a final position of the data width of said memory and informing said address generation means of a result so detected; and in that said control step comprises: generating said next address when said access address has been judged to match the address preserved in said address storage means; generating said access address and said next address in sequence and forwarding the same to said judging means when said access address has been judged not to match the address preserved in said address storage means; suspending generation of said next address when the result detected by said data size judging means has been received; and making said data storage means latch said data, when data corresponding to said next address has been read out from said memory. The memory may be a frame memory for storing image data. The next address may indicate data subsequent to data corresponding to the access address, the data indicated by the next address having the same data width as the memory. The method provided with the above mentioned construction can expect the same effects as the above-mentioned apparatus. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate a specific embodiment of the invention. In the drawings: FIG. 1 shows the construction of a typical conventional apparatus for achieving high-speed data read access to noncachable memory; FIG. 2 shows a time chart depicting a data readout operation carried out by the typical conventional apparatus of FIG 1; FIG. 3 shows a time chart depicting a data readout operation when data to be accessed are larger than the memory in width; FIG. 4 shows the construction of the apparatus for achieving high-speed data read access to the memory according to an embodiment of the present invention; FIG. 5 shows the construction of the hit judging unit of FIG. 4; FIG. 6 shows all the signals used in the apparatus of FIG. 4, each of the signals is given a name implying its function; FIG. 7 shows a specific circuit of the data storage unit of FIG. 4 provided with a latch and a selector; FIG. 8 shows a specific circuit of the address generation unit of FIG. 5; FIG. 9 shows each specific circuit of an address latch unit, a validity judging unit, and a match judging unit provided in the hit detection unit of FIG. 5; FIG. 10 shows a specific circuit of the access data size determining unit of FIG. 5; FIG. 11 shows a specific circuit of the latch control unit of FIG. 5; FIG. 12 shows a specific circuit of the state control unit of FIG. 5; FIGS. 13A-13C show the input/output logic of the logical circuits 121, 123, and 125 of the state control unit of FIG. 12; FIG. 14 shows a time chart depicting a data readout operation when an access address and the address for data held in the data storage unit of FIG. 4 do not match each other; FIG. 15 shows a time chart depicting a data readout operation when an access address and the address for data held in the data storage unit of FIG. 4 match each other; FIG. 16 shows a time chart depicting a data readout operation when an access address does not match the address of data held in the data storage unit of FIG. 4 and is not the final address within the 64-bit width of the memory 62; and FIG. 17 shows a time chart depicting a data readout operation when the access address matches the address of data held in the data storage unit of FIG. 4 and is not the final address. DETAILED DESCRIPTION OF AN EMBODIMENT FIG. 4 shows the construction of the apparatus for achieving high-speed data read access to memory according to an embodiment of the present invention. In the illustration, the apparatus 40 according to this embodiment is provided with a bus address and control signal decoder 41, a hit judging unit 42, a memory address and control signal generator 43, a memory data controller 44, a data storage unit 45, and a bus data controller 46, thereby controlling data read access from a processor (not shown) to memory 62 via a system bus 60. The bus address and control signal decoder 41 (hereinafter referred to as BA decoder 41) decodes the address and size of data to be accessed (hereinafter referred to as access data) and signals sent through the system bus 60. The signals are needed for controlling data access to the memory 62. The hit judging unit 42 judges whether the address of the access data and the address of data held in the data storage unit 45 match each other. If they do, the hit judging unit 42 makes the data storage unit 45 send out the data of its own to the system bus 60, and hold the data corresponding to the address subsequent to the address for the data held in the data storage unit 45. On the other hand, if they do not match, the hit judging unit 42 makes the memory address and control signal generator 43 allow the memory 62 to transmit the access data to the system bus 60 and the data storage unit 45 hold the data corresponding to the address subsequent to the access data. The memory address and control signal generator 43 (hereinafter referred to as MA generator 43) generates a column address, a row address, and signals required for controlling data access to the memory, based on the results decoded by the BA decoder 41 and an instruction of the hit judging unit 42, thereby forwarding to the memory 62. The memory data controller 44 (hereinafter referred to as MD controller) controls data input/output operations between the memory 62 and either the data storage unit 45 or the BD controller 46. The data storage unit 45 holds data which have been read out from the memory 62, based on an instruction of the hit judging unit 42 and forwards the data to the BD controller 46. The BD controller 46 controls data input/output operations between the system bus 60 and either the MD controller 44 or the data storage unit 45. (Construction of the hit judging unit 42) FIG. 5 shows the construction of the hit judging unit 42, which is provided with an address generation unit 51, a hit detection unit 52, an access data size determining unit 56, a state control unit 57, and a latch control unit 58. The hit detection unit 52 includes an address latch unit 53, a validity judging unit 54, and a match judging unit 55. The hit detection unit 52 judges whether the address to be accessed (hereinafter referred to as access address) and the address for the data stored in the data storage unit 45 match. The address latch unit 53 latches the address of data to be held by the data storage unit 45 among all the addresses generated by the address generation unit 51. In other words, the address latch unit 53 holds the address in the memory 62 corresponding to the data held in the data storage unit 45. The validity judging unit 54 judges whether the data held in the data storage unit 45 are valid, thereby holding a valid flag indicating the judged results. The match judging unit 55 judges whether the access address and the address held in the address latch unit 53 match, thereby outputting the judged results to the address generation unit 51. The address generation unit 51 generates access addresses, according to an instruction of the match judging unit 55. More specifically, when the match judging unit 55 has judged the addresses to match, an address subsequent to the access address is generated. In contrast, when the match judging unit 55 has judged them not to match, the access address and the subsequent address are generated in sequence. The access data size determining unit 56 determines the width of access data and also determines where in the memory 62 the access data are located. For example, when the memory 62 has 64-bit width, the access data can be either 64, 32, 16, or 8 bits in the 64-bit width. The state control unit 57 determines whether the data in the data storage unit 45 should be updated, based on the valid flag of the validity judging unit 54 and the results judged by the match judging unit 55 and the access data size determining unit 56. The latch control unit 58 controls the data storage unit 45 to hold the data which have been read out from the memory 62, based on the results judged by the state control unit 57. (Detailed construction of the apparatus 40) FIG. 6 shows all the signals used in the apparatus 40, each of the signals is given a name implying its function. For example, signals from the system bus 60 to the BA decoder 41 are named MA, XMAS, and XMRW, which respectively imply "32 bit access address", "address strobe signal" and "read/write signal". FIG. 7 shows a specific circuit of the data storage unit 45 provided with a latch 71 and a selector 72. The latch 71 latches 64-bit data "vdata" read out from the memory 62, responding to a signal "dlatch" sent from the hit judging unit 42. The selector 72 selects between the data "vdata" sent from the memory 62 and data "cdata" held by the latch 71, in accordance with a signal "xcahit" sent from the hit judging unit 42. More specifically, when the data corresponding to the access address is held by the latch 71 (xcahit=0), the data "cdata" are selected and otherwise (xcahit =1), the data "vdata" are selected, thereby outputting data thus selected, as "mdata" to the BD controller 46. FIG. 8 shows a specific circuit of the address generation unit 51 provided with incrementers 81 and 84, selectors 82 and 85, and a D flip-flop 83 (hereinafter referred to as FF 83). The selector 82, when the data corresponding to the access address are held in the latch 71 (cahit=1), outputs an address outputted from the incrementer 81, the address being subsequent to the access address, and otherwise (cahit =0), outputs the access address. The FF 83 holds an address thus sent from the selector 82 in accordance with a signal "xsp" indicating the start of access to the memory 62. The selector 85 selects the address held in the FF 83 when the data corresponding to the access address are not held in the latch 71 or when a single access to the memory is needed. The selector 85 then selects, if necessary, an address sent from the incrementer 84, the address being subsequent to the access address and outputs it as an address "vadr" requesting access to the memory 62. FIG. 9 shows each specific circuit of the address latch unit 53, the validity judging unit 54, and the match judging unit 55 provided in the hit detection unit 52. (The address latch unit 53) In FIG. 9, the address latch unit 53, which is provided with an AND gate 91, a selector 92, and FFs 93, holds an address for the data held by the data storage unit 45. The AND gate 91 detects a timing for starting to write data to the data storage unit 45 and for starting to read data from the memory 62. The selector 92 selects an address "vadr" requesting read access to the memory 62 in the timing detected by the AND gate 91. In other timing, the latch address "cacheadr" of the FFs 93 is selected. The FFs 93 latch an output of the selector 92 and sends it out as the latch address "cacheadr". The validity judging unit 54, which is composed of a comparator 97, a NOR gate 98, a NAND gate 99, a logic circuit 100, and an FF 101, judges whether data held in the data storage unit 45 are valid or not. The comparator 97 compares the latch address "cacheadr" sent from the FFs 93 and the address "vadr" requesting read access, thereby judging whether they match or not. The NOR gate 98 detects write access in process. The NAND gate 99 detects the completion of write access for the latch address "cacheadr", and sends out a signal "xflush" for nullifying the data in the data storage unit 45. The logic circuit 100 judges whether data held in the data storage unit 45 are valid or not, based on the signal "xflush" and other signals. The FF 101 holds the results judged by the NAND gate 99. In other words, the FF 101 holds the bits "valid" indicating the validity or invalidity of data held in the data storage unit 45. The match judging unit 55, which is composed of a comparator 94, an AND gate 95, and an FF 96, judges whether the address of data held in the data storage unit 45 and an address to be read out from the memory 62 match each other. The comparator 94 judges whether the access address "adr" and the address "cacheadr" sent from the FFs 93 match or not. The AND gate 95, when the comparator 94 has judged these addresses are identical, checks whether the data in the data storage unit 45 are valid or not. If they are valid, then the AND gate 95 outputs a signal "cahit=1" indicating that the data corresponding to the access address are held in the latch 71 of the data storage unit 45. The FF 96 latches a logically reversed "cahit" when access to the memory 62 is started. FIG. 10 shows a specific circuit of the access data size determining unit 56 provided with a logic circuit 102, AND gates 103 and 105, an OR gate 104, and a latch 106. The access data size determining unit 56 determines the width of access data and where in the 64-bit memory 62 the data are located. The logic circuit 102 receives a 2-bit signal "dsize" indicating which of 64, 32, 16, or 8 bits the width of the access data is, and the low order 3 bits of the access address indicating where in the 64 bits the access address is located. Then, the logical circuit 102 outputs a signal "inoacc" indicating whether the access data are within 64 bits. The AND 103 and OR 104 send out a signal "xgo" indicating the start of read access when "cahit"= 1. For read access, the latch 106 latches a signal "rw" indicating read access or write access, an 8-bit signal "dmsk" inputted through the AND gate 105 indicating the byte position of read access, and the "inoacc" sent from the logic circuit 102. Then the latch 106 outputs a signal "lrw" indicating read or write, a signal "vmsk" indicating the byte position, and a signal "noacc" indicating that write access to the data storage unit 45 has been prohibited. FIG. 11 shows a specific circuit of the latch control unit 58. An EOR 111 and an ENOR 112 determine whether data should be written to the data storage unit 45, based on the signals "noacc" and "xcahit". As a result, the FF 113 sends out a signal "caccl" indicating the execution of write access to the data storage unit 45 in synchronization with the "clk", and the NOT 114 sends out a signal "dlatch" indicating read access to the data storage unit 45. FIG. 12 shows a specific circuit of the state control unit 57. Logic circuits 121, 123, and 125 judge the state of access, based on respective input signals, and respectively send out a signal "xbusy" indicating that the access is in process, a signal "xas" requesting access, and a signal "xdrdy" indicating the completion of read access through FFs 122, 124, and 126. The input/output logic of the logical circuits 121, 123, and 125 are shown in FIGS. 13A-13C. The equations in each input column are AND requirements, and when these requirements are satisfied, the values shown in each output column are sent out. For example, in FIG. 13A, when the input signals are noacc=1, xcahit=0, and xdrdy=0, then the output signal becomes xbusy=1. The apparatus 40 constructed as mentioned above operates as follows. The BA decoder 41 receives the access address "MA", the address strove signal "XMAS", and a read/write signal "MRW" through the system bus 60, and upon request, sends out decoded results to the hit judging unit 42. According to the results, the hit detection unit 52 judges whether the access address and the address for data held in the data storage unit 45 match each other. At the same time, the access data size determining unit 56 finds out whether the access data has the same width as the memory 62 and further finds out where in the 64 bits the access data are located. The read access is carried out as follows, depending on whether the access data have 64-bit width like the memory 64 or have smaller width. (1) When the access data have the same width as the memory 64 (1.1) When the access address and the address for data held in the data storage unit 45 do not match each other. The hit judgement unit 42 requests the MA generator 43 to read out the data corresponding to a designated access address and the data corresponding to the address subsequent to the access address. Receiving the request, the MA generator reads out data "Dn" and "Dn+1" shown in FIG. 14 from the memory 64, by page mode access. These data read out are sent to the MD controller 44 in sequence and forwarded to the data storage unit 45. The data storage unit 45 outputs the data corresponding to the access address to the system bus 60 through the BD controller 46 and keeps the data for the subsequent address inside, (1.2) When the access address and the address for data held in the data storage unit 45 match each other. The hit judging unit 42 informs the data storage unit 45 of their having matched and requests the MA generator to read out the address subsequent to the access address. Responding to their match, the data storage unit 45 sends out the data of its own to the system bus 60 through the BD controller 46. Receiving the request for reading out the data corresponding to the subsequent address, the MA generator 43 reads out the data from the memory 62 ("Dn+1" in FIG. 15). The data read out are sent to the MD controller 44 and forwarded to the data storage unit 45 to be kept therein. (2)When the access data have smaller width than the memory 64 Whether the access address and the address of data held in the data storage unit 45 match or not, two different operations are possible, depending on the following two cases. One case is when the access address is a final address within the 64-bit width of the memory 62. More specifically, the memory 62 has 64-bit data width so that three types of access width: 8, 16, and 32 bits can be possible. Provided that the addresses assigned per byte in the memory 62 are N, N+1, N+3, N+4, N+5, N+6, and N+7, eight addresses are possible to access 8-bit data: N, N+1, N+2, N+3, N+4, N+5, N+6, and N+7, four addresses are possible to access 16-bit data: N, N+2, N+4, and N+6, two addresses are possible to access 32-bit data: N and N+4. The above-mentioned "final address" means the address N+7 to access 8-bit data and the address N+6 to access 16-bit data, and the address N+4 to access 32-bit data. In other words, these are cases where data including final byte in the 64-bit data are accessed. The other case is that the access address is not the final address. (2.1) When the access address does not match the address of data held in the data storage unit 45 and is the final address In this case, both the data for the access address and the address subsequent to the access address are read out from the memory 62. The data corresponding to the access address are sent out to the system bus 60 and the data of the subsequent address are kept in the data storage unit 45 as shown in the time chart in FIG. 14. (2.2) When the access address does not match the address of data held in the data storage unit 45 and is not the final address With the reference to the time chart in FIG. 16, the hit judging unit 42 requests the MA generator 43 to read out the data corresponding to the access address. At the same time, the access data size determining unit 56 in the hit judging unit 42 informs the state control unit 57 that the access address is not the final address. The state control unit 57 makes the latch control unit 58 forward the access data to the data storage unit 45. Responding to the access request, the MA generator 43 reads out the data from the memory 62 ("Dn" in FIG. 16). The data read out are sent to the MD controller 44 and forwarded to the data storage unit 45. The data storage unit 45 keeps the data inside under control of the latch control unit 58 and also sends out them to the system bus 60 through the BD controller 46. (2.3) When the access address matches the address of data held in the data storage unit 45 and is the final address In this case, the operations depicted by the time chart in FIG. 15 are carried out. More precisely, the hit judging unit 42 informs the data storage unit 45 that the access address and the address of data held in the data storage unit 45 match and requests the MA generator to read out an address subsequent to the access address from the memory 62. Being informed of their match, the data storage unit 45 outputs the data of its own to the system bus 60 through the BD controller 46. Responding to the request for reading the subsequent address, the MA generator 43 reads out the data corresponding to the subsequent address from the memory 62 ("Dn+1" in FIG. 15). The data read out are sent to the MD controller 44 and forwarded to the data storage unit 45 to be kept therein. (2.4) When the access address matches the address of data held in the data storage unit 45 and is not the final address With reference to the time chart in FIG. 17, the hit judging unit 42 requests the data storage unit 45 to output the data of its own. At the same time, the access data size determining unit 56 informs the state control unit 57 that the access address is not the final address. Then the state control unit 57 makes the latch control unit 58 keep the data storage unit 45 out of updating data. Responding to the instruction from the hit judging unit 42, the data storage unit 45 sends out the data of its own to the system bus 60 through the BD controller 46. Thus, access data are sent from the data storage unit 45 to the system bus 60, which can reduce the time required for reading data out of the memory 62. Although the access address sent from the system bus 60 is sent to the hit judging unit 42 by way of the BA decoder 41 in this embodiment, it may be directly inputted to the hit judging unit 42 by connecting the hit judging unit 42 directly to the system bus 60. This construction contributes to further reduction in access time because the hit judging unit 42 operates in parallel to the BA decoder 41. However, this undesirably increases the burden of the system bus 60. Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art may be made without departure from the scope of the present invention as determined by the appended claims.

Claims: An apparatus for controlling high-speed data read access, without employing burst transmission techniques, to contiguous areas in a memory (62) such as a frame memory or a VRAM, in response to an access request sent through a system bus (60), the apparatus comprising: a data storage means (45) for preserving data corresponding to a predetermined address; a judging means (42) for judging whether an access address indicated by said access request matches the predetermined address; and for making said data storage means (45) output data preserved therein to the system bus (60) when said access address has been judged to match the predetermined address, and for making said data storage means (45) hold data corresponding to a next address subsequent to said access address when said access address has been judged not to match the predetermined address, said judging means (42) comprising: an address storage means (53) for preserving an address indicating said data latched by said data storage means (45); wherein the judging means (42) further comprises: a validity judging means (54) for judging whether the data preserved in said data storage means (45) are valid or invalid; a match judging means (55) for judging whether said access address matches the address preserved in said address storage means (53) and for judging that said access address does not match the address preserved in said address storage means (53), when said validity judging means (54) has judged the data to be invalid; and characterised in that the judging means (42) comprises a data size judging means (56) for detecting whether the access data has a smaller data width than said memory (62) and does not include a final position of the data width of said memory (62) and for informing an address generation means (51) of a result detected by said data size judging means (56), and in that said judging means (42) comprises: said address generation means (51) for generating said next address when said access address has been judged to match the address preserved in said address storage means (53), for generating said access address and said next address in sequence and forwarding to said judging means (42) when said access address has been judged not to match the address preserved in said address storage means (53), and for suspending generation of said next address when the result detected by said data size judging means (56) has been received and a latch control means (58) for, when data corresponding to said next address has been read out from said memory (62), making said data storage means (45) latch said data. The apparatus of claim 1, wherein said memory (62) is a frame memory for storing image data and said next address indicates data subsequent to data corresponding to said access address, said data indicated by said next address having a same data width as said memory (62). The apparatus of claim 1, wherein said data storage means (45) comprises: a data latch means (71) for latching said data outputted from said memory (62); and a selection means (72) for selecting said data latched by said data latch means (71) when said access address has been judged to match the predetermined address and for selecting data outputted from said memory (62) when said access address has been judged not to match the predetermined address, thereby forwarding selected data to the system bus (60). The apparatus of claim 1, wherein said address generation means (51) comprises: a first incrementer (81) for incrementing said access address; a first selector (82) for selecting an output of said first incrementer (81) when said access address has been judged to match the address preserved in said address storage means (53) and selecting said high order address when said access address has been judged not to match the address preserved in said address storage means (53); a latch circuit (83) for latching an output of said first selector (82); a second incrementer (84) for incrementing the output of said first selector (82); and a second selector (85) for selecting an output of said latch circuit (83) when said access address has been judged to match the address preserved in said address storage means (53) and for selecting said output of said latch circuit (83) and then selecting an output of said second incrementer (84), thereby outputting said output of said second incrementer (84) as an access address to said memory (62) when said access address has been judged not to match the address preserved in said address storage means (53). In combination, the apparatus of claim 1 and a memory (62). The combination of claim 5, wherein said memory (62) is a frame memory for storing image data. A method for controlling data read access in an apparatus according to claim 1, said method comprising: judging whether said access address matches the predetermined address in response to the access request; when said access address has been judged to match the predetermined address: outputting the data held in said data storage means (45) to the system bus (60); reading the data stored at said next address of the memory (62); and storing the read data to said data storage means (45); when said access address has been judged not to match the predetermined address: reading the data stored at the access address of the memory (62); outputting said data corresponding to said access address; reading the data stored at said next address of the memory (62); and storing said data of said next address to said data storage means (45), wherein said judging step comprises: preserving an address indicating said data latched by said data storage means; judging whether the data preserved in said data storage means (45) are valid or invalid; judging whether said access address matches the address preserved in said address storage means (53); and judging whether said access address does not match the address preserved in said address storage means (53), when said validity judging means (54) has judged the data to be invalid; and characterised in that the judging step further comprises detecting whether the access data has a smaller data width than said memory (62) and does not include a final position of the data width of said memory (62) and informing said address generation means (51) of a result so detected; and in that said control step comprises: generating said next address when said access address has been judged to match the address preserved in said address storage means (53); generating said access address and said next address in sequence and forwarding the same to said judging means (42) when said access address has been judged not to match the address preserved in said address storage means (53); suspending generation of said next address when the result detected by said data size judging means (56) has been received; and making said data storage means (45) latch said data, when data corresponding to said next address has been read out from said memory (62). The method of claim 7, wherein said memory (62) is a frame memory for storing image data. The method of claim 8, wherein said next address indicates data subsequent to data corresponding to said access address, said data indicated by said next address having a same data width as said memory (62).

Inventors: KITAMURA TOMOHIRO, OCHIAI TOSHIYUKI, SEKIBE TSUTOMU, KITAMURA, TOMOHIRO, OCHIAI, TOSHIYUKI, SEKIBE, TSUTOMU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: G06F12
IPC codes: G06F12