Protective diode for transistor

Abstract: To reduce the required diffusion depth of impurities in manufacturing a protective diode for protecting an insulated gate transistor from overvoltage so that the diode can be easily built in a chip of the transistor, a plurality of p-type diode layers (32) are built in by diffusion through the windows in an insulation film (31) disposed on an n-type region (2) into which a depletion layers spread when the vertical field effect transistor to be protected is turned off, and a diode terminal (A) is led out from an electrode film (34) that is in electrical contact with the diode layers (32). This configuration prevents depletion layers, spreading from the diode layers (32) into the semiconductor region (2) by the applied overvoltage, from joining with each other, and sufficiently lowers the breakdown voltage of the protective diode (30) with respect to the withstand voltage of the transistor (10 or 20) even when the diffusion depth of the diode layer (32) is one order of magnitude shallower than in the prior art.

Description: The present invention relates to a diode built in a chip of a transistor for protecting the transistor from overvoltage, and in particular to a protective diode suitable for an insulated gate transistor such as a field-effect transistor (hereinafter referred to as "FET") or an insulated gate bipolar transistor (hereinafter referred to as "IGBT"). When overvoltage is applied to a transistor from the load side and a breakdown occurs between the main terminals of the transistor, while it is driving a load for example, the transistor may be damaged or destroyed by an excessive avalanche current that flows through the transistor during the breakdown period. To avoid this, a diode that breaks down prior to breakdown of the transistor when overvoltage is applied is often connected to the transistor. A conventional method of protecting the transistor from such overvoltage is now described, with reference to Figure 3 of the accompanying drawings, according to a prior art dynamic clamping protection method suitable for an insulated gate transistor. In Figure 3(a), an FET 10 is to be protected from overvoltage. A protective diode 30 is connected between a drain and a gate terminal G in reverse polarity to a supplementary diode 50. The protective diode 30 breaks down, for example, by overvoltage applied from the load side when a source terminal S side is wounded (earthed) and a load is connected to a drain source D. When the FET 10 is turned off and the overvoltage caused by the induction or the like on the load side reaches the breakdown voltage of the protective diode 30 (which is lower than the breakdown voltage value of the FET 10), the protective diode 30 becomes conductive to increase the gate voltage of the n-channel FET 10, which then remains in the "ON" state. Consequently, the overvoltage is clamped at the breakdown voltage of the protective diode 30. When the transient overvoltage decreases, the protective diode 30 returns to a non-breakdown state to turn off the FET 10. The supplementary diode 50 is used to prevent the protective diode 30 from becoming conductive by positive gate voltage when the FET 10 is turned on. In Figure 3(b), an IGBT 20 is to be protected. In this case, the protective diode 30 is connected between the base of the IGBT 20 and the gate terminal G without using the supplementary diode 50 seen in Figure 3(a). When, for example, overvoltage is applied to a collector terminal C, connected to a load, of the "OFF" state IGBT 20 the emitter terminal of which is wounded, the protective diode 30 breaks down to clamp the voltage applied to the IGBT 20 at the breakdown voltage of the diode 30. By the associated increase of the gate voltage of the IGBT 20, the IGBT 20 is then turned on in the same way as in Figure 3(a). When the overvoltage vanishes, the IGBT 20 is turned off. In Figure 3(b), it is more advantageous to build the protective diode 30 into the chip of the transistor to be protected than to install the diode 30 externally. This invention relates to the built-in protective diode. Figure 4 is a sectional view illustrating a conventional built-in protective diode 30. The FET 10 in Figure 4(a) and the IGBT 20 in Figure 4(b) are the components to be protected, respectively. The chip of the FET 10 shown in Figure 4(a) is produced by growing an n-type epitaxial layer as a semiconductor region 2 on an n-type substrate 1. The FET 10 is built in vertically to the semiconductor region 2 by repeatedly accumulating the structure units as shown on the right hand side of the figure. The FET 10 comprises a gate 11 disposed on an oxide gate film 11a, a p-type base layer 12, and an n-type source layer 13. The source terminal S is led out from an electrode film 14 in electrical contact with the base layer 12 and the source layer 13; the drain terminal D is led out from a back electrode film 15 in electrical contact with the substrate 1; and the gate terminal G is led out from the gate 11. The protective diode 30 comprises a p-type diode layer 32 formed by diffusion from the surface area of the semiconductor region 2 surrounded by an insulation film 31; and a diode terminal A is led out from an electrode film 34 disposed on the diode layers 32. The supplementary diode 50 is connected between the diode terminal A and the gate terminal G of the FET 10. The IGBT 20 of Figure 4(b) differs from the FET 10 of Figure 4(a) in that the chip is formed by diffusing an n-type buffer layer 1a on the p-type substrate 1, and then epitaxially growing the n-type semiconductor region 2 on the buffer layer 1a. However, the IGBT 20 in Figure 4(b) is formed underneath the surface of the semiconductor region 2 in the same way as the FET 10 in Figure 4(a), and the protective diodes 30 in both Figures 4(a) and 4(b) have the same structure. As can be seen in these figures, the protective diode 30 is built in the semiconductor region 2 into which a depletion layer spreads while the FET 10 or the IGBT 20 is turned off. The supplementary diode 50 in Figure 4(a) is formed in a region on the substrate not shown in the Figure by employing polycrystalline silicon for the gate 11. Patent abstracts of Japan vol. 17, no. 178 & JP 4 332 172 A discloses a circuit for protecting elements. A transistor can be protected from overvoltage by building the protective diode 30 in a common chip with the FET 10 or the IGBT 20, without employing any external connections. However, this configuration usually requires the breakdown voltage of the protective diode 30 to be set accurately by 50 to 100 V lower than the withstand voltage value of the transistor to be protected. In addition, it takes a considerable time to diffuse in the diode layer 32, and the diffusion depth is not easily controlled. Though the diode layer 32 is built in by diffusion from the surface of the semiconductor region 2, an epitaxial layer such as the semiconductor region 2 is grown to a sufficient thickness and resistivity to facilitate expansion of the depletion layer while the FET 10 or the IGBT 20 is OFF. Therefore, the breakdown voltage of the protective diode 30 cannot be reduced to a desired value unless the diode layer 32 is diffused in deeply. It takes as long as 20 to 30 hours to diffuse in a sufficiently deep diode layer 32 even at temperatures as high as 1,100°C, which causes economic and practical disadvantages. The diffusion depth precision is deteriorated by the long period of heating. In addition to this, the diode layer 32 is subject to deformation by the high temperature used in diffusion of the base layer 12 of the FET 10 or the IGBT 20, which causes undesirable distribution of the breakdown voltage. In view of these problems, an object of the present invention is to provide a protective diode that is built easily in a chip of a transistor to be protected, and shows an accurate breakdown voltage. According to the present invention, this object is achieved by chip comprising a transistor and a protective diode for protecting the transistor from overvoltage as defined in claim 1. Embodiments of the invention will now be described in detail with reference to the accompanying drawings, in which: Figure 1 is a cross sectional view illustrating a protective diode for a transistor not covered by the present invention. Figure 2 is a cross sectional view illustrating a protective diode for a transistor according to the present invention; Figures 3(a) and 3(b) show circuit diagrams illustrating the connection of a protective diode to a transistor to be protected, Figure 3(a) showing a circuit for the protection of an FET and Figure 3(b) showing a circuit for the protection of an IGBT; and Figures 4(a) and 4(b) are cross sectional views of the conventional protective diode built in a chip of a transistor to be protected, Figure 4(a) showing an example of the FET protection and Figure 4(b) showing an example of the IGBT protection. The embodiments of the present invention are described with reference to Figures 1 and 2. Parts corresponding to parts shown in Figures 3 and 4 are designated by the same reference numerals or symbols, and the description of such parts is omitted for simplicity. In the embodiments described below, the FET 10 corresponding to the equivalent circuit in Figure 3(a) is used as an example of a component to be protected, though the protective diode according to the present invention may be used to protect various transistors including the IGBT 20 in Figure 3(b). In Figure 1, the transistor to be protected is a FET having the same structure as that seen in Figure 4. The semiconductor region 2, an n-type epitaxial layer in the chip in which the transistor 10 is built, is formed to have a thickness of 30 to 50 µm and to have a impurity concentration of, for example, 10 13 atom/cm 3 so as to obtain the desired withstand voltage. For example, the FET 10 may have a withstand voltage of 800 V and a current capacity of from several to ten-odd ampere. In this vertical FET 10, a depletion layer spreads from the base layer 12 to the semiconductor area 2 while FET 10 is OFF, as is well known. The overvoltage applied to the drain terminal D in Figure 3(a) substantially exceeds the withstand voltage and reaches, as an example, beyond 900V. In order to protect the FET 10 from such overvoltage, the breakdown voltage of the protective diode 30 is usually set at 700 to 750 V, a value lower by 50 to 100 V than the corresponding withstand voltage of FET 10. The protective diode 30 in the embodiment in Figure 1 is formed by providing an insulation film 31 on the surface of the n-type semiconductor region 2; forming a plurality of windows through the film 31 by known means such as the photo process; forming a plurality of diode layers 32 by ion implantation of p-type impurities through the windows and thermal diffusion of the implanted impurities; and disposing as a diode terminal A an aluminium electrode film 34 that is in electrical contact commonly with the diode layers 32. In correspondence to Figure 3(b), this diode terminal A is connected to the gate terminal G via the supplementary diode 50. For example, the diode layers 32, with the surface impurity concentration of 10 19 atom/cm 3 , are diffused in to a depth of 2 to 3 µm. It is advantageous to form the diode layers 32 and the base layer 12 by simultaneous diffusion for the convenience of the process. It is preferable to employ from three to several diode layers 32 as shown in Figure 1. It is also preferable to build in the supplementary diode 50 in a region other than the cross section shown in Figure 1 by employing polycrystalline silicon of which the gate 11 of the FET 10 is made. As described above, a depletion layer spreads from each of the diode layers 32 into the semiconductor region 2 while the FET 10 is OFF. Avalanche breakdown starts from the part where the electric field is most concentrated, which corresponds to the corner in the bottom of the diode layer 32 when over voltage is applied to the drain terminal D. The conventional single-diode layer 32 of Figure 4(a) requires a diffusion depth of 15 to 20 µm. However, the protective diode 30 in the first embodiment sufficiently reduces the breakdown voltage in the diode layer 32 with a diffusion depth of one-half to one-tenth of the conventional depth. In order to enhance such an effect, it is preferable to minimize the spread of the depletion layers from adjacent diode layers 32 and to suppress concentration of electric field in the curved part of the boundary of the diode layers 32. Therefore, the spacing among the plurality of diode layers 32 should preferably be set at more than 10 µm for the high withstand voltage FET 10. Figure 2 is a cross sectional view showing a preferred modification of the embodiment of Figure 1. In Figure 2, an n-type counter-doped layer 33 with higher impurity concentration than the semiconductor region 2 is formed by diffusion between the diode layers 32 beneath the surface the semiconductor region 2. The preferable impurity concentration in the counter-doped layer 33 is one order of magnitude higher than that in the semiconductor region 2, for example, 10 14 atom/cm 3 . The diffusion depth of the counter-doped layer 33 should preferably be very shallow, that is around 1 to 2 µm. In the embodiment in Figure 1 when the FET 10 is OFF, depletion layers spread also along the surface of the semiconductor region 2 underneath the insulation film 31 among the diode layers 32, while in Figure 2, the counter-doped layers 33 inhibit the transverse elongation of the depletion layers. Thus the counter-doped layers 33 prevent the depletion layers, extending from adjacent diode layers, from joining with each other and further reducing the breakdown voltage of the protective diode 30. The provision of counter-doped layers 33 allows the reduction the spacing between the diode layers 32 when the breakdown voltage need not be reduced. In the embodiment described, a plurality of diode layers with a conduction type opposite to that of the semiconductor region are formed by the diffusion process from the surface of the semiconductor region into which depletion layers spread when the transistor to be protected is turned off, so that the plurality of depletion layers may not join with each other easily. Thus, not only is the impurity diffusion depth shortened down to one order of magnitude shallower than in the prior art, thus making it possible easily and economically to manufacture a protective diode with the desired breakdown voltage lower than the withstand voltage of the transistor to be protected, but also the breakdown voltage can be controlled more accurately than in the prior art to protect the transistor to be protected from overvoltage safely and reliably. Additionally, the chip area required to build in a protective transistor can be reduced through shallow diffusion, which also prevents transverse diffusion of the dopants.

Claims: A chip comprising a transistor and a protective diode (30) for protecting the transistor (10) from overvoltage, said protective diode comprising: a number of spaced apart diode layers (32), formed in a surface of a semiconductor region (2) into which depletion layers spread when the transistor is OFF, the diode layers being of opposite conductivity type to the semiconductor region and having a depth of between 2 and 3 micrometers; a common insulation film (31) covering surfaces of the diode layers; an electrode film (34) in electrical contact with the diode layers (32) through windows formed through the insulation film (31); and a diode terminal (A) led out from the electrode film (34) and connected to the transistor (10) and including a plurality of counter-doped layers (33) formed in the surface of the semiconductor region (2) between the diode layers (32), the counter-doped layers (33) being of the same conductivity type with but of higher concentration than impurities in the semiconductor region (2), and having a depth of from 1 to 2 micrometers.

Inventors: NISHIURA AKIRA, OTSUKI MASAHITO, SAITOH RYU, NISHIURA, AKIRA, OTSUKI, MASAHITO, SAITOH, RYU, NISHIURA, AKIRA, C/O FUJI ELECTRIC CO. LTD., OTSUKI, MASAHITO, C/O FUJI ELECTRIC CO. LTD., SAITOH, RYU, C/O FUJI ELECTRIC CO. LTD.
Applicants: FUJI ELECTRIC CO LTD, FUJI ELECTRIC CO. LTD.
Application year: 1994
Main classification: H01L27
IPC codes: H01L29, H01L27