Video signal processing with arithmetic processor and interrupt

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Description: This invention relates to a video signal processor capable of performing a process-switch function by software and to its video signal processing technique. There have been demands for a television system capable of providing a high resolution. To meet such demands, a television system called the EDTV (Extended Definition Television) system was introduced and has been put to practical use. The MUSE (Multiple Sub-nyquist Sampling Encoding) system, which is one of the HDTV (High-definition Television) systems, has been proposed, and some of the MUSE systems have been put to practical use. It is expected that advanced television systems such as an EDTV II system (i.e., the second-generation EDTV) and a digital television system will come in practice in the near future. In view of these developments in the field of TV broadcasting system, video signal processors including television receivers and video tape recorders must be designed such a way that they can receive broadcasting signals of different television systems including the existing NTSC (National Television System Committee) system. A conventional TV receiver has plural different boards each of which corresponds to a respective television system. These boards are exchanged depending on the received signal. This technique is introduced as a background technique of " Scan Line Conversion LSI for Wide Screen TV Receiver", ITEJ Technical Report, vol.16, No.71, pp.19-24, BCS'92-41 (Oct., 1992) by Toshichika Satoh et al. How conventional TV receivers having a MUSE signal processing board and a NTSC signal processing board operate is described. According to the MUSE system standard, the sampling rate = 16.2 MHz; the number of pixels (per scanning line) = 480; and the number of scanning lines = 1125. On the other hand, according to the NTSC system standard, the sampling rate = 14.3 MHz; the number of pixels (per scanning line) = 910; and the number of scanning lines = 525. First, the MUSE signal is considered. The MUSE signal processing board separates a received MUSE signal into a Y signal, an R-Y signal, and a B-Y signal. In the MUSE system, in order to make high vision signals fall within the specified transmission bandwidth range, pixel data is band-compressed by making use of the fact that pixels of a previous field coincide with pixels of a current field in the case of an image without movement and the fact that the human eye has poor resolving power to an image with movement. Therefore, the MUSE processing board performs different processes depending upon the image type. An image without movement is processed according to a procedure that mainly consists of two processes; namely interpolation between specified frames (inter-frame interpolation) and interpolation between specified fields (inter-field interpolation). For the case of images without movement, each one-picture (frame) data is transmitted after it is divided into four fields, pixels contained in these fields are synthesized, and the result of the synthesis operation is output. On the other hand, an image with movement is processed according to a procedure that mainly consists of two processes; namely intra-field interpolation and frequency conversion. In the case of images with movement it is not possible to make use of data about a previous field. This means that desired pixels must be generated from data about a current field by an interpolation technique. On the other hand, the NTSC signal processing board separates a received NTSC signal into a Y signal, an R-Y signal, and a B-Y signal. An NTSC signal is fed in the form of a blend of a luminance signal Y and a chrominance signal C, and thus it is necessary to perform a Y/C separation process that is the NTSC signal processing board's main function. The signal C is a signal that makes a phase-inversion for every one scanning line and for every one frame. This makes it possible to fetch only the signal Y by adding a current pixel and a pixel one scanning line ahead thereof, and it is also possible to fetch only the signal C by means of subtraction. However, there actually exists a location difference between a pixel and a pixel one scanning line ahead thereof, which prevents the Y/C separation from being performed successfully. To deal with this problem, a pixel at the same location as a current pixel is first pseudo-found from an average of vertical lines and thereafter addition/subtraction operations are performed for the Y/C separation to be performed completely. For the case of images without movement, the complete Y/C separation can be carried out by making use of a pixel one frame ahead of a current pixel. As described above, conventional TV receivers have to contain a plurality of signal processing boards for compatibility with different types of TV broadcasting systems. This results in the increase in costs. Additionally, to catch up with new TV broadcasting systems that are expected to be put to practical use in the future, new signal processing boards corresponding to these new systems must be developed. This requires much development work, thereby increasing the development cost. The conventional TV receiver has some problems. For example, in order to perform vertical/horizontal synchronization when outputting a picture to a CRT, it is necessary to operate the entire TV receiver at different system clock signals having different frequencies depending on the input video signal type. That is, a system clock frequency of 16.2 MHz is used in the case of the MUSE system, and 14.3 MHz in the case of the NTSC system. When aiming at achieving high-speed image processing, sampling clock processing for phase lock becomes a barrier to increasing the system clock signal frequency (i.e., the processing frequency). There may be a way capable of realizing high-speed processing without increasing the system clock signal frequency such as parallel processing. This way, however, produces the problem that the amount of hardware increases. SUMMARY OF THE INVENTION It is a first object of the present invention to provide a video signal processor and a video signal processing technique in order that common hardware to different broadcasting systems and process switching functions by software are realized. It is a second object of the present invention to process a video signal at a frequency higher than a sampling rate of the video signal while maintaining input-to-output synchronization. In the Article "video signal processing for HDTV receiver" from Seki et al., published in IEEE transactions on consumer electronics, vol. 36, no. 3, August 30, 1999, pages 198 to 205 describes a video signal processor for use in a dual system TV receiver. The described TV receiver is able to decode either NTSC or HDTV broadcasting signals. The decoder comprises a plurality of components used for decoding both kinds of signals. These common components comprise an A/D converter, an inter-frame processor, a mixing circuit, a motion detector, and a D/A converter. Additionally, the decoder comprises particular circuits only used for decoding an individual one of both broadcast signals. The receiver employs a scan converter for an aspect ratio conversion of a 4:3 NTSC aspect ratio image to be displayed on a 16:9 wide screen HTDV display. An intra-field interpolation circuit is only provided for MUSE signals and an intra-field Y/C separation circuit is only used for NTSC signals. The commonly used circuits of the decoder comprise a frame memory for digitized input data, output line memories for processed video data, and HDTV display for reproducing processed images. Reference EP-A-0 529 442 relates to a television receiver which employs a DSP for signal processing. The signal processing is adapted for automatically switching between different television standards (NTSC, PAL, SECAM). Based on a detected television standard in a system discriminating circuit, a particular processing program for processing the received TV signal by the DSP is loaded into the DSP from a program memory. Particular processing functions of the DSP comprise a matrix processing structure. The image signal processed in such a matrix DSP configuration comprises luminance and chrominance components which are subjected to a multiplication and summing step. The resulting primary color components are applied to CRT output. A known image signal processing apparatus for the processing of MUSE and NTSC signals is described in reference EP-A-0 371 677. The processing apparatus uses common first and second frame memories for both signals. In addition, common movement detection circuits and moving picture processing circuits are provided. Depending on the detected movement, filtered signal components, different for NTSC and MUSE signals, are combined. Reference "A new multiplier-adder LSI for digital video processing", published by S. Iwase et al. in SMPTE Journal, September 1984, describes a multi purpose C-MOS circuit developed for digital video processing. The IC design is based on a basic operating structure of a multiplier-adder. The basic structure of a multiplier-adder may be employed for inner product operations. Such inner product operations are important for digital filtering as used for NTSC encoding or RGB-YIQ conversion. EP-A-0 444 947 describes a television receiving system employing a video processor which has a number of processing elements executing the same instruction at the same time. Each of the processing elements comprise a data input register, an arithmetic unit, and a data output register. Further, the television receiving system comprises a control unit for receiving external, signals, such as those from a remote control. These signals are decoded and transmitted to other receiver components. It is the object of the invention to provide an improved signal processor to be employed as a common hardware with different broadcasting systems. This is achieved by the teaching of claim 1. These configurations permits a single parallel sum-of-product arithmetic means to be shared between signal processing of various broadcasting systems. The provision of the input- and output-side storage means makes it possible to absorb differences between the processing speed of the processing means and the input/output rate. FIGURE 1 is a block diagram of a first TV receiver of the present invention capable of receiving both a MUSE signal and an NTSC signal. FIGURE 2 is a block diagram showing internal structures of a parallel sum-of-products arithmetic unit section, an input/output register section, and a sum-of-products factor register of FIGURE 1. FIGURE 3 is an operation flowchart of the main routine of the first TV receiver. FIGURE 4 is an operation flowchart of the interruption handling routine of the first TV receiver. FIGURE 5 is an operation flowchart of the first TV receiver that employs a polling method. FIGURE 6 shows a structure of an NTSC input pixel data received by the first TV receiver. FIGURE 7 shows a structure of a sum-of-products factor for the NTSC Y separation in the first TV receiver. FIGURE 8 shows a structure of a sum-of-products factor for the NTSC C separation in the first TV receiver. FIGURE 9 shows data setting to the input/output register section as well as to the sum-of-products factor register section when performing sum-of-products arithmetic operations for the NTSC Y separation in the first TV receiver. FIGURE 10 shows data setting to the input/output register section as well as to the sum-of-products factor register section when performing sum-of-products arithmetic operations for the NTSC C separation in the first TV receiver. FIGURE 11 shows in detail the NTSC Y/C separation procedure in the first TV receiver. FIGURE 12 shows timing of a central processing unit and the parallel sum-of-products arithmetic unit section as to the processing of "A" of FIGURE 11. FIGURE 13 shows the flow of MUSE image processing in the first TV receiver. FIGURE 14 shows data setting to the input/output register section as well as to the sum-of-products factor register section for intra-field interpolation and movement detection of FIGURE 13, and arithmetic operation result storage. FIGURE 15 shows a motion image identification process on the basis of the result of the movement detection of FIGURE 14. FIGURE 16 shows aliasing distortion deletion and aliasing distortion component extraction of FIGURE 13. FIGURE 17 shows a compare process in size between an inter-frame aliasing distortion component and an inter-field aliasing distortion component on the basis of the result of the arithmetic operation of FIGURE 16. FIGURE 18 is a flowchart showing in detail a MUSE image processing procedure in the first TV receiver. The present invention pertains to a TV receiver having the capability of receiving both a MUSE signal and an NTSC signal. Preferred embodiments of the present invention are described by making reference to the accompanying drawings. Referring now to FIGURE 1, a first TV receiver of the embodiment is described. A processor 100 of FIGURE 1 has a parallel sum-of-products arithmetic section (PSAS) 101; a comparator 102; an input/output (I/O) register section 103; a sum-of-products factor register section (SFRS) 104; a central processing unit (CPU) 105; an instruction cache 106; a data memory 107; a bus controller 108; an interruption control section 112; and a DMA controller 113. Of these components, the PSAS 101, the comparator 102, the I/O register section 103, and the SFRS 104 together form a coprocessor to the CPU 105. The CPU 105, the instruction cache 106, and the bus controller 108 are interconnected via an instruction bus 109. The coprocessor, formed by the elements 101-104. the CPU 105, and the data memory 107, and the bus controller 108 are interconnected via a data bus 110. On receipt of a MUSE signal, a MUSE sync circuit 114 performs analog-to-digital conversion of the received MUSE signal at a sampling rate of 16.2 MHz, and this converted signal is output together with a synchronizing signal. On the other hand, on receipt of an NTSC signal, an NTSC sync circuit 115 performs analog-to-digital conversion of the received NTSC signal at a sampling rate of 14.3 MHz, and this converted signal is output together with a synchronizing signal. Each of the sync circuits 114 and 115 has the capability of synchronizing the received signal and fetching a video signal of a channel selected. A selector 120 is capable of selecting between two different signals (that is, the MUSE signal and the NTSC signal) and outputting a selected signal to a frame memory 116 provided on the input side. That is, this frame memory 116 serves as a memory for storing input pixels. A frame memory 117 is provided on the output side, which stores image data for display. A CRT display control section 118 exerts control in order that data of the frame memory 117 is displayed on a CRT 131 while it (the memory 117) performs a function of changing the dimensions of the frame depending on the synchronizing signals from the MUSE sync circuit 114 and the NTSC sync circuit 115. In other words, the frame memories 116 and 117 provided on the input- and output-sides are shared between the MUSE system and the NTSC system. In the present invention, processed video information is output to the CRT 131 where it is displayed. However, such video information may be stored in, for example, a disk. A control signal input section 121 sends an interruption signal to the processor 100 in response to an external control signal given off from, for example, a TV remote controller carrying requests such as a request for channel change and a request for volume change. The control signal input section 121 has an internal register for holding a channel number set or the like. A program memory 122 stores instructions to be executed by the processor 100. An audio processing section 123 receives an audio signal from the input-side frame memory 116. Volume is set by a signal from the processor 100 to the audio processing section 123. Reference numeral 132 indicates a loudspeaker. The processor 100, the MUSE sync circuit 114, the NTSC sync circuit 115, the selector 120, the frame memory 116, the frame memory 117, the control signal input section 121, the program memory 122, and the audio processing section 123 are interconnected via a system bus 119. FIGURE 2 is a block diagram showing the PSAS 101, the I/O register section 103, and the SFRS 104 of FIGURE 1. 16 input registers 201-216 are provided. These input registers 201-216 together form a part of the I/O register section 103, and they are 8-bit registers for storing pixel data. It is possible to make the input registers 201-216 store the output of the PSAS 101 or the output of the comparator 102 fed through the data bus 110. An output register 282 forms a part of the I/O register 103. This output register 282 stores the result of the arithmetic operation performed by the PSAS 101. There are provided 16 factor registers 241-256. These factor registers 241-256 together form a part of the SFRS 104, and they are 4-bit registers for storing factors being used when performing sum-of-products arithmetic operations. There are provided 16 multipliers 221-236 that together form a part of the PSAS 101. These 16 multipliers 221-236 perform multiplication operations of data stored by the 16 input registers 201-216 and data stored by the 16 factor registers 241-256. That is, data stored by an input register is multiplied by data stored by a corresponding factor register. 15 adders 261-275 are provided which are tree-interconnected and which together form a part of the PSAS 101. These adders are used to sum products found by the multipliers 221-236. A carry look-ahead circuit (CLA) 281 is provided which forms a part of the PSAS 101. This CLA 281 has the capability of converting the result of the addition operation represented by a redundant binary number to a simpler binary number. Each of the adders 261-275 has a structure capable of directly writing the result of the arithmetic operation to the I/O register 103 through the data bus 110, without passing through the CLA 281. With reference to FIGURES 3 and 4, the operation of the first TV receiver is described. FIGURE 3 is an operation flowchart of the main routine of the first TV receiver. FIGURE 4 is an operation flowchart of the interruption handling routine of the first TV receiver. As shown in FIGURE 3, when power is turned on, a reset occurs to the processor 100 (STEP 1000). Then, the processor 100 starts running a program at the initial address of the program memory 122. This initializes all of the PSAS 101, the comparator 102, the I/O register section 103, the SFRS 104, the CPU 105, the instruction cache 106, the data memory 107, the bus controller 108, the interruption control section 112, and the DMA controller 113 (STEP 1001). Individual instructions forming the program are taken into the CPU 105 from the program memory 122 through the bus controller 108 and the instruction bus 109, while at the same time these instructions are stored in the instruction cache 106. Therefore, instruction readout can be performed at a high speed from the next time and high-speed image processing becomes possible. Next, the broadcasting system is detected depending on the channel set at initialization time (STEP 1002). Then, the program branches to a MUSE processing step (STEP 1005) or to an NTSC processing step (STEP 1004) according to the result of STEP 1003 that is a step of identifying the broadcasting system. Thereafter, each image processing goes into an endless loop until an interruption signal is applied. If a request for channel change is made during the MUSE processing (STEP 1005), this applies a control signal to the control signal input section 121. As a result, the requested channel number is set to an internal register of the control signal input section 121. Then, the control signal input section 121 outputs an interruption signal to the interruption control section 112 within the processor 100. Next, the interruption control section 112 outputs to the CPU 105 a signal of interruption level set at the initialization time. This causes an interruption (STEP 1015), and the program branches to an interruption handling routine step (STEP 1006) of FIGURE 4. Even if a request for channel change is issued during the NTSC processing (STEP 1004), this also causes an interruption (STEP 1014) so that the program branches to STEP 1006 (i.e., the interruption handling step). In the interruption handling routine of FIGURE 4, the program proceeds to a system control processing step (STEP 1007) for, for example, setting the volume. Then, the program proceeds to a channel change routine step (STEP 1008) for checking if the interruption factor is a channel setting change. From STEP 1008, the program then branches to STEP 1002. At STEP 1002, the broadcasting system is identified according to the channel number set to the internal register of the control signal input section 121. Depending upon the result of the broadcasting identification step (STEP 1003), the program branches to STEP 1005 (i.e., the MUSE processing step) or to STEP 1004 (the NTSC processing step). As described above, both the MUSE processing and the NTSC processing are an endless loop, so that the same routine is repeatedly performed until the next interruption occurs. If a request for volume change is issued during the MUSE processing (STEP 1005) or during the NTSC processing (STEP 1004), this also causes an interruption (STEPS 1015 and 1014). Then, the program branches to STEP 1006. At STEP 1006, a volume set signal is applied by STEP 1007 to the audio processing section 123. In this case, unlike the channel change, a RETURN instruction of STEP 1001 is executed because processing that is under operation at the time of the occurrence of an interruption must be continued. If the interruption factor is "switch-off", the program goes to a switch-off check step (STEP 1009). Then, end-of-processing is performed and the program is over (see FIGURE 4). The operation of the first TV receiver employing an interruption handling technique has been described. Instead of employing the interruption handling technique, a polling technique, shown in FIGURE 5, may be useful, although this is not an embodiment of the invention. In FIGURE 5, STEPS 1201 and 1200 are a control signal identification routine. In the polling technique, after STEP 1005 or STEP 1004, the CPU 105 reads an internal register of the control signal input section 121 so as to check for the application of control signals (for example, the presence or absence of a request for channel change) (STEPS 1201 and 1200). At the same time the CPU 105 proceeds with the processing. The read operation of the internal register of the control signal input section 121 is performed through the system bus 119. For example, if the control signal input section 121 receives a control signal during the MUSE processing (STEP 1005), the program branches from STEP 1201 to a system control processing step (STEP 1007). As a result of such arrangement, the same function as realized by the interruption handling method can be realized. The internal operation of the processor 100 is detailed in terms of the MUSE processing (STEP 1005) and the NTSC processing (STEP 1004) through examples. In the description of the MUSE processing, intra-field interpolation and aliasing distortion deletion are explained. In the description of the NTSC processing, Y/C separation is explained. With the help of FIGURES 6-12, Y/C separation in terms of the NTSC system is described. FIGURE 6 shows an input pixel data structure of the NTSC system. FIGURE 7 shows a structure of a sum-of-products factor for NTSC Y separation. FIGURE 8 shows a structure of a sum-of-products factor for NTSC C separation. Each pixel is sampled at a sampling rate of 4 fsc (= 14.3 MHz) (i.e., four times the chrominance subcarrier frequency). FIGURE 6 shows pixel data items p1-p5, p6-p10, and p11-p15, each group representing one scanning line. To perform a Y/C separation operation, each pixel is multiplied by a respective factor and those products are added. FIGURE 7 shows sum-of-products factor values for the luminance signal Y separation in which the center pixel data item p8 is a pixel data item subject to arithmetic operations. Other pixel data items without sum-of-products factor value indications have sum-of-products factor values of zero. This sum-of-products arithmetic operation can be written as follows: p1 + 2*p3 + p5 + 2*p6 + 4*p8 + 2*p10 + p11 + 2*p13 + p15 As a result, the Y signal separation is performed. FIGURE 8 shows sum-of-products factor values for the chrominance signal C separation. This sum-of-products arithmetic operation can be written as follows: p1 - 2*p3 + p5 - 2*p6 + 4*p8 - 2*p10 + p11 - 2*p13 + p15 As a result, the C signal separation is performed. Here, eight pixel data items locating next to the pixel data item p8 are included in the formulae (1) and (2), taking into account the continuity of the pixel data item p8 to each of its adjoining pixel data items. FIGURE 9 shows the setting of data in performing the formula (1) for the Y separation. The input registers 201-215 store respective pixel data items (i.e., p1-p15 of FIGURE 6). The factor registers 241-255 store respective sum-of-products factors (see FIGURE 7). Corresponding sum-of-products factors to the pixel data items p2, p4, p7, p9, p12, and p14 are zeros. The input register 216 that is a sixteenth input register is not used and thus its corresponding factor register (i.e., the factor register 256) is assigned a sum-of-products factor of 0. At the time when performing the formula (2) for the C separation, the contents of the factor registers 241-255 are changed to the sum-of-products factors of FIGURE 8, as shown in FIGURE 10. The procedure of the NTSC processing (i.e., STEP 1004 of FIGURE 3) by the processor 100 is detailed in the form of a problem analysis diagram (PAD) of FIGURE 11. In order that pixel data for three scanning lines is DMA-transmitted from the input-side frame memory 116 (i.e., the external memory) to the data memory 107 (i.e., the internal memory) via the bus controller 108, the CPU 105 sets a transfer start address and transfer data count to an instruction register. This initializes the data memory 107 for later processing. Termination of the transfer of data is reported by an interruption signal from the DMA controller 113 to the CPU 105 through the interruption control section 112. Further, instructions are sent to the DMA controller 113 in order that pixel data for one scanning line is DMA-transmitted from the input-side frame memory 116 to the data memory 107. Next, the CPU 105 activates the PSAS 101 that then performs arithmetic operations for the Y/C separation. That is, pixel data items are set to the input registers 201-215 of the I/O register section 103, sum-of-products factors are set to the factor registers 241-256 of the SFRS 104 (see FIGURE 9), and the PSAS 101 performs sum-of-products operations for the Y separation. Then, the sum-of-products factor setting is changed (see FIGURE 10), and the PSAS 101 performs sum-of-products operations for the C separation. Individual arithmetic operation results are read out of the I/O register section 103 and are stored in the data memory 107 (i.e., the processing "A" of FIGURE 11). This processing "A" is repeated for every pixel of a single scanning line. Upon completion of the Y/C separation for one scanning line, the CPU 105 issues an instruction to the DMA controller 113 in order that the arithmetic operation result for one scanning line is transferred from the data memory 107 to the output-side frame memory 117 (i.e., the external memory). The above-described processing is repeatedly performed for all the scanning lines of one frame. FIGURE 12 shows timing of the CPU 105 and the PSAS 101 in terms of the processing "A" of FIGURE 11. Execution of a CO exe instruction (i.e., a coprocessor activation instruction) activates the PSAS 101, and pixel data items are read out of the data memory 107 to the input registers 201-215. At the next cycle, arithmetic operations for the Y separation are performed by the PSAS 101. At the following cycle, separation arithmetic operations for the C separation are performed by the PSAS 101. While the PSAS 101 is performing these operations for the Y/C separation, the CPU 105 performs address increment by an ADD (addition) instruction and checks if pixel processing for one scanning line is completed by a BNE (conditional branch) instruction. On completion of the arithmetic operation for the Y/C separation, the CPU 105 issues an ST (store) instruction in order that the arithmetic operation result is stored in the data memory 107. By repetition of the above-described operation, high-speed NTSC Y/C separation can be realized. The Y/C separation of the present embodiment is two-dimensional; however, the present embodiment may find applications in three-dimensional Y/C separation in which intra-field arithmetic operations are performed. Next, by reference to FIGURES 13-18, a MUSE luminance signal Y process is detailed. FIGURE 13 shows the flow of MUSE image processing. To simplify the processing, an input MUSE signal is subjected to an intra-field interpolation process 601, regardless of the image type. In this case, aliasing distortion occurs to images without movement. Therefore, an aliasing distortion deletion process 602 is performed. In parallel with this aliasing distortion deletion process 602, a movement detection process 603 for identifying the image type (that is, an image with movement or an image without movement) is carried out. If the result of the movement detection process 603 is an image with movement, the result of the intra-field interpolation process 601 is selected at a later step, that is, in a synthesis process 604. If the result of the movement detection process 603 is an image without movement, the result of the aliasing distortion deletion process 602 is selected. Data setting for the intra-field interpolation process 601 and the movement detection process 603, and storage of the arithmetic operation result are shown in FIGURE 14. Here, pixel data is set only to eight input registers of the 16 input registers 201-216. The pixel p8 is located in the same place as a pixel p0 two frames ahead of the pixel p8. The following sum-of-products operations are performed. q1 = p1 + 2*p2 + p3 q4 = p7 + 2*p8 + p9 m = p0 - p8 These arithmetic operation results q1, q4, and m are stored in the three output registers 283-285 forming a part of the I/O register section 103. "q1" and "q4" are the results of the intra-field interpolation process. "m" is movement detection data. FIGURE 15 shows an image with/without movement identification process. The comparator 102 makes a comparison between an absolute value of m from the register 285 and an absolute value of m0 that is a threshold, in order to identify the image type. FIGURE 16 shows data setting for the aliasing distortion deletion process 602 and an aliasing distortion component extraction process, and storage of the arithmetic operation result. Here, data including the result of the intra-field interpolation 601 is set only to ten of the 16 input registers 201-216. The following sum-of-products arithmetic operations are performed. r1 = q1 + 2*q4 + p5 r2 = q1 + q4 s1 = -q1 + 2*q4 - p5 s2 = -q1 + q4 These results r1, r2, s1, and s2 are stored in the four output registers 287-290 forming a part of the I/O register section 103. "r1" and "r2" are the results of the aliasing distortion deletion processes (between frames and between fields). "s1" and "s2" are extracted aliasing distortion components (between frames and between fields). FIGURE 17 shows a comparison in size between an aliasing distortion component and another. More specifically, the comparator 102 makes a comparison between an absolute value of s1 from the register 289 and an absolute value of s2 from the register 290, in order to determine which one of the inter-frame aliasing distortion component and the inter-field aliasing distortion component is greater than the other. A program for the above-described MUSE processing may be written by the assembly language as follows. LD data read CO exe1 intra-field interpolation A: CO exe2 aliasing distortion deletion CO exe3 image-with/without-movement identification BL branch to C if an image with movement is detected NOP no operation CO exe4 comparison in size between aliasing distortion components BL branch to B if inter-field aliasing distortion component is greater than inter-frame aliasing distortion component LD data read STr2 storage of data less inter-frame aliasing distortion JMP branch to A CO exe1 intra-field interpolation B: STr1 storage of data less inter-field aliasing distortion JMP branch to A CO exe1 intra-field interpolation C: LD data read STr5 storage of interpolation data JMP branch to A CO exe1 intra-field interpolation The CO exe1 instruction written in a line next to the JMP instruction (i.e., an unconditional branch instruction) is executed at the time of the branch in question. FIGURE 18 shows this program in the form of a flowchart. In the first place, the CPU 105 inputs data by the LD (load) instruction (STEP 901). Next, the CPU 105 performs intra-field interpolation and movement detection of FIGURE 14 by the CO exe1 instruction (STEPS 902 and 904). Then, the CPU 105 performs aliasing distortion deletion and aliasing distortion component extraction (STEP 903) of FIGURE 16 by the CO exe2 instruction. Next, the CPU 105 performs movement detection of FIGURE 15 by the CO exe3 instruction (STEP 905). Further, based on the result of this movement detection, the CPU 105 exerts branch control by the BL instruction (i.e., the conditional branch instruction) (STEP 906). In other words, if the movement detection result is an image with movement, the program proceeds to STEP 907. On the other hand, if the movement detection result is an image without movement, this makes the program proceed to STEP 910. In the case of the detection of an image with movement, the read operation of the next data is performed by the LD instruction (STEP 907), and interpolation data of the arithmetic operation result of FIGURE 14 is written by the ST instruction into the data memory 107 (STEP 908). Then, the JMP instruction is executed to perform an intra-field interpolation process (STEP 909), after which the program returns to STEP 903. If an image without movement is detected, a comparison in size between an inter-frame aliasing distortion component and an inter-field aliasing distortion component is made by the CO exe4 instruction (STEP 910 of FIGURE 17). Making use of the result of this compare operation, branch control is exerted by the BL instruction (STEP 911). In other words, if the inter-field aliasing distortion component is greater than the inter-frame aliasing distortion component, the program proceeds to STEP 912, otherwise to STEP 915. If inter-field aliasing distortion is greater than inter-frame aliasing distortion, then the next data is input by execution of the LD instruction at a delay slot (STEP 912). Thereafter, data less inter-field aliasing distortion is written into the data memory 107 by the ST instruction (STEP 913). Then, the JMP instruction is executed to perform an intra-field interpolation process (STEP 914), after which the program returns to STEP 903. If inter-frame aliasing distortion is greater than inter-field aliasing distortion, the next data is input by execution of the LD instruction (STEP 915). Thereafter, data less inter-frame aliasing distortion is written into the data memory 107 by the ST instruction (STEP 916). Then, the JMP instruction is executed to perform an intra-field interpolation process (STEP 917), after which the program returns to STEP 903. By repeating the above-described operations, high-speed MUSE image processing can be accomplished. In this embodiment, the transfer of instructions and the transfer of data are performed through a single system bus, namely the system bus 119. The processor 100 may contain two ports to make two different buslines available. Of these two buslines one is used for the transfer of instructions and data from the program memory 122 to the CPU 105 and the other is used for the DMA transfer of data between the frame memories 116, 117 and the data memory 107. This enables high-speed control without causing mutual interference. Further, the DMA controller 113 may be eliminated, in which case the transfer of data between the frame memories 116, 117 and the data memory 107 is directly dealt with by the CPU 105. Furthermore, instead of employing the frame memories 116 and 117, line memories or FIFO memories may be useful. A ghost canceler or a waveform equalizer may be provided between one of the sync circuits 114 and 115 and the output-side frame memory 116. Additionally, a filter processing circuit may be provided between the processor 100 and the output-side frame memory 117. In the present embodiment, the Y separation and the C separation are performed by a single processor (i.e., the processor 100). A plurality of processors may be employed to perform the both in parallel. The above-described NTSC Y/C separation procedure finds applications in such TV broadcasting systems as EDTV and EDTV II requiring the Y/C separation. PAL (Phase Alternation Line) video signals may be processed by changing the program and switching the sum-of-products factor. The present invention finds application not only in TV receivers but also in video signal processors including VTR's. The PSAS 101 may be used as a filter for audio signal processing. By changing factor-setting to the SFRS 104, a variable-characteristic audio filter can be realized. Additionally, application of digital signals from digital TV's, VTR's, or CD-ROM's to the system bus 119 enables multi-media processing thereof, as in the above-described video signal processing. Further, instead of using the adders 261-275 of the PSAS 101 of a tree structure, different types of adders such as adders of a ripple carry type may be useful. In this embodiment, the input registers 201-216 and the factor registers 241-256 are of an 8-bit configuration and a 4-bit configuration respectively, which, however, is not to considered restrictive. Other bit configurations may be used for these registers.

Claims: A signal processor comprising: a plurality of. synchronous means (114, 115) for outputting broadcasting signals to be processed in synchronism with video signals or audio signals, and a selector (120) for selectively outputting a particular one of said broadcasting signals from said plurality of synchronous means (114, 115), a first frame memory (116) for storing pixel data of said selectively output broadcasting signal, a second frame memory (117) for storing a processing result as output data, output means (131, 132) for outputting data on the basis of data read out of said a second frame memory (117), a data register (103) for storing a data vector p = (p 0 , p 1 , ...p n ) made up of data read out of said a first frame memory (116), and a sum-of-products arithmetic operation result based on said data vector p, a sum-of-products factor register (104) for storing a sum-of-products factor vector a = (a 0 , a 1 , ... a n ), parallel sum-of-products arithmetic means (PSAM) (101) for performing a sum-of-products arithmetic operation to compute an inner product, denoted by p.a = a 0 *p 0 + a 1 *p 1 + ... + a n *p n , of said data vector p and said sum-of-products factor vector a and writing a sum-of-products arithmetic operation result in said data register (103), processing means (105) for controlling the operations of said plural synchronous means (114, 115) and said selector (120), setting said data vector p to said data register (103), setting said sum-of-products factor vector a to said sum-of-products factor register (104), and controlling said sum-of-products arithmetic operation of said PSAM (101), program storage means (122) for storing a program with a description of the contents of an operation to be carried out by said processing means (105), control signal input means (121) for holding an external control signal, and interrupt control means (112) for generating an interrupt signal to control the operations of said processing means (105) in response to an said external control signal received and held by said control signal input means (121), wherein said signal processor is adapted to perform the steps of: receiving pixel data for at least one scanning line from said a first frame memory (116), processing said received pixel data, and outputting said pixel data that has undergone said signal processing to said a second frame memory (117), whereby each of said steps is repeatedly performed on respective pixel data for one frame A signal processor according to claim 1, wherein said processing step is carried out by repeatedly conducting a pixel processing operation on every pixel. A signal processor according to claim 1 or claim 2, wherein said processing step includes a step of performing an image-with/without-movement identification process (603) by making a comparison between said pixel data for at least one scanning line and pixel data of a scanning line one field ahead thereof. A signal processor according to any of claims 1 to 3, wherein said processing step includes a step of selecting (604) between an intra-field process and an inter-field process according to a result of said image-with/without-movement identification process.

Inventors: HASEGAWA KATSUYA, MIYAKE JIRO, NINOMIYA KAZUKI, NISHIYAMA TAMOTSU, YOSHIOKA SHIROU, HASEGAWA, KATSUYA, MIYAKE, JIRO, NINOMIYA, KAZUKI, NISHIYAMA, TAMOTSU, YOSHIOKA, SHIROU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H04N5
IPC codes: H04N9, H04N7, H04N5