Variable length coder

Abstract: A variable length coder for converting fixed bit length data to variable bit length data has a codetable for storing codewords, said codewords means for defining the bitsequence and length of said bitsequence; a bitmap for indicating the presence of said codewords in said codewords in said codetable, said bitmap addressed by one or more bits from the fixed bit length data; an addresser for converting one or more bits from the fixed bit length data to a codetable address, said codetable address used to index said codetable.

Description: The invention relates to a variable length coder (also known as "Huffman coder" or "entropy coder") for use in digital audio/video coders and the like. In many digital video coders a lossy coding algorithm based on the discrete cosine transform (DCT) precedes a lossless encoder based on variable length coding (VLC). The transform coefficients are run-levelled and entropy coded, in which the most common run-level combinations are given the shortest codes and the less common combinations longer codes. A run-level represents a group of 1 or more transform coefficients as a number of 0 coefficients (run) followed by a single coefficient value (level). One example of run-level combination to codes is disclosed in Tables 1 to 4. For example, H.261 (see "Recommendation H.261 - Video Codec for Audio-visual Services at px64 kbits/s" by International Telegraph and Telephone Consultative Committee, Study Group XV, CCITT Subgroup XV Document, Report R 37, August 1990) and MPEG-1 (see "CD 11172 - Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbps" by international Organization for Standardization, ISO MPEG Document, ISO-IEC/JTC1/SC2/WG8, 1992) describe audio/video codecs which require variable length coders. Emerging standard HDTV codecs will also require variable length coders. The implementation of a variable length coder has typically been accomplished by the use of a look-up table (LUT) to translate the fixed length data to variable length data. The LUT is usually implemented using memory (for example RAM or PROM), or logic (for example PLA). Lei and Sun (see "An Entropy Coding System for Digital HDTV Applications", Shaw-Min Lei & Ming-Ting Sun, IEEE Transactions on Circuits and Systems for Video Technology, Vol.1, March 1991) implemented a LUT using a PLA. The PLA containes the codeword bitsequence and the length of the bitsequence. The input to the PLA is the fixed length data from a run-leveller, and the output is the codeword bitsequence and the length of the bitsequence. Vogel (see "Method and Apparatus for Bit Rate Reduction", Peter Vogel, United States Patent Number 4,901,075, Feb. 13, 1990) described an implementation which used a PROM to implement a LUT. The run-level fixed length data was applied directly to the address bus of the PROM, and the representation of the variable length bitsequence is output on the data bus. However, there are several problems which this invention solves. Due to the rapidly changing digital AN coding technology, and also due to the wide range of applications, the contents of the Huffman tables used for variable length coding may change. This results in a need for programmable variable length codetables. Contrary to programmability is the need for small implementation size so that inexpensive VLSI codecs can be made. From US-A 3 717 851 it is known to use a coder for transforming a fixed length codeword into a variable length codeword and to use a decoder for transforming a variable length codeword into a fixed length codeword. The variable length codewords are produced by directly addressing a codetable stored in an associative memory using the input fixed-length codewords. The variable length codeword is extracted from the fixed length output of the associative memory by using a shaft register. The coder generates a specified variable length code comprising a "prefix" portion and a "reminder" portion. Said "prefix" portion indicates the length of said "reminder" portion, i.e. number of bits of said "reminder" portion. Codewords which occur less frequently may be treated differently. For these codewords, a COPY code may be stored at a single location which is addressed in common by all fixed length codewords which do not match any of the addresses at which the other variable length codewords are stored. US-A-4 295 124 discloses a text compression method in which input sequences comprising two ASCII characters are converted into an address of a ROM storing the codetable by using a hasking technique. Reference US-A-4,899,149 relates to a decoding method and apparatus for Huffman of variable/length codes. The described apparatus generates a certain variable length code which comprises a prefix portion and a reminder portion. The new codeword comprises a number of leading ones as a prefix followed by the particular codeword to be transmitted. EP-A2-0 286 719 describes a text compression method and apparatus. For compressing and decompressing text, specific dictionaries are used having entries of words which are ranked in accordance with a weighted frequency of usage. The ranking of the entries is based on statistical studies of the areas of use employed. In MPEG-1 and H.262, the Huffman tables are not continuous. Not every run-level combination exists, and of the combinations which do exist, they are not necessarily contiguous. For example, a codeword for run=6, level=0, 1, 2 and 3 exist, but not for run=6, level=4, nor for run=7, level=3. This means that an implementation using conventional memory will have "holes" of unused memory, portions of memory which contain no useful information because the run-level combination has no codeword. This is a waste of VLSI chip space. Alternatively, a PLA can be used but PLAs have more limited versatility than RAM. Quite often the Huffman tables contain patterns in the variable length bit sequences which can be identified and used to shrink the codetable. For example, in MPEG-1, the longest bitsequence in the DCT coefficients Huffman table is 16 bits (disregarding the sign of the level). However, all of the longer bitsequence consist of a string of 0s, followed by several 1s. This pattern can be recognised and used to reduce the codetable size. The object of this invention is to eliminate the wastage of codetable space caused by storing redundant information in the codetable. This is achieved by the features of claim 1. For the purpose of solving the above described problems, the present variable length coder was invented. In the present invention, a codetable is used for storing codewords each of which define a codeword bitsequence and length of said bitsequence. A bitmap is used to indicate the presence of a codeword in the codetable for a particular fixed length code input. An addresser is used to convert the fixed length code input to an address which is then used to index the codetable. The bitmap and addresser are used as means to eliminate the holes in the Huffman table which occur as the result of non-contiguous codewords. A codeword translator can be used to eliminate some of the redundant information in the storage of the bitsequence codewords in the codetable. When the fixed length input data or a subset thereof is applied to the inputs of the bitmap, the resulting output from the bitmap is an indication of whether or not the codetable contains a huffman codeword for that fixed length input data. If the bitmap indicates the codeword is missing, the bitsequence output from this variable length coder is invalid. In this case an alternate method is needed to code the fixed length data, such as coding the data as a fixed length bitsequence. When the fixed length input data or a subset thereof is applied to the inputs of the addresser, the resulting output from the addresser is an address which is used to index the codetable for that fixed length input data. The addresser allows the codewords to be stored in the codetable contiguously, so that there is no wasted space in the codetable due to invalid data. If the fixed length input data was used directly to index the codetable, many of the fixed length input data words may result in invalid bitsequence outputs from this variable length coder because there is no variable length codeword for that fixed length input data. In this case there may be contiguous groups of valid codewords separated by groups of invalid codewords. Thus, the addresser removes these holes in the huffman table. If the codetable contains the variable length codeword information as encoded data, the codeword translator is used to convert the output from the codetable into a bitsequence and length of bitsequence variable length codeword. By storing encoded data instead of lengths and bitsequence, the word width of the codetable, and therefore the overall size of the codetable is reduced. Figure 1 is an example of a variable length coder. Figure 2 is an example embodiment of the invented variable length coder. Figure 3 describes the function of the sub-bitmaps in the embodiment of Figure 2. Figure 4 describes how the invention can be combined with a fixed length data encoder. Tables 1-4 represent run-level combination and corresponding codes. In Figure 1, the input 1 is fixed length data comprising a 6 bit run and an 8 bit absolute value level. An example of such data are the run-level combinations which result in a digital video encoder after the run-level coding of DCT coefficients. In this case, the run represents the number of 0 coefficients and the level represents the absolute value of the non-zero coefficient following the 0s. The bitmap input 2 are the 14 input bits of run and level. The bitmap output 3 is a single bit which is 1 if the codeword data is present in the codetable, and 0 otherwise. The bitmap 4 can be implemented using a 2 14 x 1 bit memory. The addresser 5 comprises a base table 6 and an adder 7. The base table 6 can be implemented using a 2 6 x 6 RAM whose input address lines 8 are the 6 bits of the run. The contents of the vase table 6 indicate the base address 9 of a contiguous group of codeword data with the specified run in the codetable. The offset 10 from this starting address are the 8 bits of the level. The base address 9 and offset 10 are added by the adder 7 to determine the codetable address 11 where the codeword data is located. For example, for a run=4, level=2 combination the base table 6 is indexed using the run value, 4. The result is a base address 9 which indexes the codetable at the starting location of the group of all codewords which represent inputs with run=4. The offset 10 from this base is the level value, 2. In other words, the index used to find the codeword corresponding to run=4, level=2 is calculated as the contents of base table[4] + 2. For this example embodiment the codetable 12 contains words comprising a "bitsequence" stored as 23 bits and "length of bitsequence" stored as 5 bits, for a total of 28 bits for each codetable entry. For example, to store the bitsequence "001101", the "length of bitsequence" is 6 and the "bitsequence" is "001101". Unused bits of the bitsequence are set to 0. This represents the variable length codeword 13 corresponding to the run and level fixed length input data. The maximum codelength is 23 bits. A codetable with up to 128 codewords can be implemented using a 128 x 28 bit memory. The benefit can be seen by comparing the size of memory and logic required for this embodiment with the size of memory required by a variable length coder implemented by a simple LUT. It requires a total of 2 14 x 1 + 2 6 x 6 + 128 x 28 = 20352 bits of storage plus a small amount of logic. If the variable length coder is implemented using a simple table, the size of the table would be 2 14 x 29 = 458752 bits. The input is 14 bits for run and level so there are 2 14 different input combinations. Each entry in the table would contain a bitsequence of 23 bits, a length of 5 bits and a single bit to indicate if the codeword is valid or not. Thus, each entry in the simple table would be 29 bits which include both the variable length code and the valid indicator stored in the bitmap 4 . The reason that the simple table is so much larger is because the simple table reserves space for codewords for all the run-level combinations, whereas the described variable length coder removes the space in the memory where these codewords do not exist. The effect is the huge reduction in memory storage requirements for variable length coding. An example embodiment of this invention is shown in Figure 2. The input to this example embodiment is fixed length data 14 comprising a 6 bit run and an 8 bit absolute value level. The bitmap 15 comprises of 2 sub-bitmaps 16,17, some comparators 18 and a valid logic 19. Figure 3 represents how the 2 sub-bitmaps 16,17 are used. The dotted line 36 represents the bitmap address space in 2-dimensions. The horizontal axis is the absolute value of the level ranging from 1 to 256, represented by 8 bits because the representation is (level-1), or 0 to 255. The vertical axis is the run ranging from 0 to 63, represented by 6 bits. The shaded region 20 represents those combinations of run-levels for which the codeword is present in the encoded codetable 21. In other words, for this embodiment, it is the locations in the bitmap which contain "1". The other locations contain "0". If the bitmap inside the dotted line was implemented using a memory, it could be implemented using the same bitmap as in the first embodiment, namely a 2 14 x 1 memory. However, in this embodiment the large memory space outside of sub-bitmap-1 and sub-bitmap-2 where there are no non-zero bits is not implemented using memory. Instead, only the sub-bitmap-1 region and sub-bitmap-2 region are implemented using memories. The input to sub-bitmap-1 22 for this embodiment are the 5 LSbits (Least Significant Bits) of run for an input range of 0 to 31, and the 3 LSbits of (level-1) for an effective input range of level of 1 to 8. The output 23 is a single bit hereafter called valid-map-1. Sub-bitmap-1 16 can be implemented using a 2 8 x 1 RAM. The input to sub-bitmap-2 24 for this embodiment are the 3 LSbits of run for an input range of 0 to 7, and the 6 LSbits of (level-1) for an effective input range of level of 1 to 64. The output 25 is a single bit hereafter called valid-map-2. Sub-bitmap-2 17 can be implemented using a 2 9 x 1 RAM. For this embodiment, the contents of the sub-bitmap RAMs are 1 if the run/level codeword is present in the codetable, and 0 otherwise. The selection of the bits used as inputs to the sub-bitmaps was made in order to minimize the total memory size required to cover the shaded region 20 in the bitmap address space 36. The comparators 18 for this embodiment determine whether the input to each sub-bitmap is valid or not according to the following: ( (run <= 31) && (level <= 8 ) ) --> inrange-map-1 ( (run <= 7) && (level <= 64 ) ) --> inrange-map-2 inrange-map-1 is "true" if the combination of run-level lies within sub-bitmap-1, and inrange-map-2 is "true" if the combination of run-level lies within sub-bitmap-2. For this embodiment, the valid logic 19 determines the following: ((valid-map-1 && inrange-map-1) || (valid-map-2 && inrange-map-2)) --> valid-codeword The valid-codeword output 26 is 1 if the codeword data is present in the encoded codetable 21. The addresser 27 for the embodiment of Figure 2 comprises a base table 28 and an adder 29. The base table can be implemented using a 2 5 x 6 RAM whose input address lines 30 are the 5 LSbits of the run. The contents of the base table indicate the base address 31 of a contiguous group of codeword data with the specified run in the codetable. The offset 32 from this base address are the 8 bits of the level. The base address and offset are added to determine the encoded codetable address 33 where the codeword data is located. For this example embodiment the encoded codetable contains words comprising a 4 bit "length of 0s", 4 bit "length of code", and an 8 bit "bitsequence code". The translator 34 converts these values to a bitsequence of the specified number of 0s followed by the specified number of bits of the code. The output of the translator 35 is a bitsequence and length of bitsequence. For example, the bitsequence "0000001101" is represented as 6 0s followed by a 4 bit code with a bitsequence "1101". "6" can be represented by the 4 bit " length of 0s", "4" can be represented by the 4 bit "length of code", and the "1101" can be represented by the 8 bits of "bitsequence code", where 4 of these bits are not used. The output from the translator for this example is the bitsequence length of 10 ("0000001101"is 10 bits long) represented by 5 bits, and the bitsequence "0000001101" represented by 23 bits, 10 of which are meaningful for this example. The maximum codelength for this embodiment is 23 bits because there can be up to 15 0s (the range of "length of 0s" is 0 to 15) followed by up to 8 (the range of "length of code" is 1 to 8) "bitsequence code" bits. The benefit of this embodiment for this invention can be seen by comparing the size of memory and logic required for this embodiment with the size of memory required by a variable length coder implemented by a simple LUT. The embodiment of Figure 2 requires a total of 2 8 x 1 + 2 9 x 1 + 2 5 x 6 + 128 x 16 = 3008 bits of storage plus a small amount of logic. If the variable length coder of this embodiment is implemented using a simple table, the size of the table would be 2 14 x 29 = 458752 bits, as described previously. The reason that the simple table is so much larger is because the simple table reserves space for codewords for all the run-level combinations, whereas the variable length coder of this embodiment removes the space in the memory where these codewords do not exist. Another reason is because the simple table contains a 2 14 x 1 bitmap, whereas for this embodiment the bitmap is implemented with 2 small sub-bitmaps and some logic. A further reason is because the simple table uses 28 bits to represent the codewords, whereas for this embodiment the codewords are represented by 16 bits each and the translator is used to expand them. The effect of this invention is the huge reduction in memory storage requirements for variable length coding. Figure 4 shows one way in which the previous 2 embodiments can be used in combination with a fixed length data encoder 37 to encode bitsequences of data. The valid codeword output 38 from the bitmap 39 is used by the selector 40 to select either the variable length codeword 41 or the fixed length encoded codeword 42. The output of the selector 43 is an encoded bitsequence. This arrangement can be used to encode any fixed length codeword because if a variable length code does not exist, as indicated by the valid codeword output 38, a fixed length encoded codeword will result instead. It is possible to use a different configuration of bitmaps, both in number and size, as well as different comparators and valid logic. It is also possible to change the size of the base table and codetable, and the function of the encoded codeword translator. The choice of these items will affect the size of the coder at the expense of versatility and programmability of the coder. The effect of this invention, is the dramatic decrease in size of the variable length coder, whilst maintaining significant programmability so that support of various hufman codetables is possible with the same implementation. The effect of using an addresser and bitmap is to decrease the size of the codetable by not occupying memory space for the holes in the huffman table. The effect of using sub-bitmaps plus associated comparators and some additional logic is to decrease the size of the bitmap by determining the codes presence in the codetabie for a range of the fixed length input data. The effect of using a translator is to decrease the size of the codetable by not occupying memory with redundant information common for many or all the codewords in the codetable. dct coeff first and dct coeff next variable length code run level 10 end of block 1 s 0 1 11 s 0 1 011 s 1 1 0100 s 0 2 0101 s 2 1 0010 1 s 0 3 0011 1 s 3 1 0011 0 s 4 1 0001 10 s 1 2 0001 11 s 5 1 0001 01 s 6 1 0001 00 s 7 1 0000 110 s 0 4 0000 100 s 2 2 0000 111 s 8 1 0000 101 s 9 1 0000 01 escape 0010 0110 s 0 5 0010 0001 s 0 6 0010 0101 s 1 3 0010 0100 s 3 2 0010 0111 s 10 1 0010 0011 s 11 1 0010 0010 s 12 1 0010 0000 s 13 1 0000 0010 10 s 0 7 0000 0011 00 s 1 4 0000 0010 11 s 2 3 0000 0011 11 s 4 2 0000 0010 01 s 5 2 0000 0011 10 s 14 1 0000 0011 01 s 15 1 0000 0010 00 s 16 1 dct coeff first and dct coeff next variable length code run level 0000 0001 1101 s 0 8 0000 0001 1000 s 0 9 0000 0001 0011 s 0 10 0000 0001 0000 s 0 11 0000 0001 1011 s 1 5 0000 0001 0100 s 2 4 0000 0001 1100 s 3 3 0000 0001 0010 s 4 3 0000 0001 1110 s 6 2 0000 0001 0101 s 7 2 0000 0001 0001 s 8 2 0000 0001 1111 s 17 1 0000 0001 1010 s 18 1 0000 0001 1001 s 19 1 0000 0001 0111 s 20 1 0000 0001 0110 s 21 1 0000 0000 1101 0 s 0 12 0000 0000 1100 1 s 0 13 0000 0000 1100 0 s 0 14 0000 0000 1011 1 s 0 15 0000 0000 1011 0 s 1 6 0000 0000 1010 1 s 1 7 0000 0000 1010 0 s 2 5 0000 0000 1001 1 s 3 4 0000 0000 1001 0 s 5 3 0000 0000 1000 1 s 9 2 0000 0000 1000 0 s 10 2 0000 0000 1111 1 s 22 1 0000 0000 1111 0 s 23 1 0000 0000 1110 1 s 24 1 0000 0000 1110 0 s 25 1 0000 0000 1101 1 s 26 1 dct coeff first and dct coeff next variable length code run level 0000 0000 0111 11 s 0 16 0000 0000 0111 10 s 0 17 0000 0000 0111 01 s 0 18 0000 0000 0111 00 s 0 19 0000 0000 0110 11 s 0 20 0000 0000 0110 10 s 0 21 0000 0000 0110 01 s 0 22 0000 0000 0110 00 s 0 23 0000 0000 0101 11 s 0 24 0000 0000 0101 10 s 0 25 0000 0000 0101 01 s 0 26 0000 0000 0101 00 s 0 27 0000 0000 0100 11 s 0 28 0000 0000 0100 10 s 0 29 0000 0000 0100 01 s 0 30 0000 0000 0100 00 s 0 31 0000 0000 0011 000 s 0 32 0000 0000 0010 111 s 0 33 0000 0000 0010 110 s 0 34 0000 0000 0010 101 s 0 35 0000 0000 0010 100 s 0 36 0000 0000 0010 011 s 0 37 0000 0000 0010 010 s 0 38 0000 0000 0010 001 s 0 39 0000 0000 0010 000 s 0 40 0000 0000 0011 111 s 1 8 0000 0000 0011 110 s 1 9 0000 0000 0011 101 s 1 10 0000 0000 0011 100 s 1 11 0000 0000 0011 011 s 1 12 0000 0000 0011 010 s 1 13 00000 0000 0011 001 s 1 14 dct coeff first and dct coeff next variable length code run level 0000 0000 0001 0011 s 1 15 0000 0000 0001 0010 s 1 16 0000 0000 0001 0001 s 1 17 0000 0000 0001 0000 s 1 18 0000 0000 0001 0100 s 6 3 0000 0000 0001 1010 s 11 2 0000 0000 0001 1001 s 12 2 0000 0000 0001 1000 s 13 2 0000 0000 0001 0111 s 14 2 0000 0000 0001 0110 s 15 2 0000 0000 0001 0101 s 16 2 0000 0000 0001 1111 s 27 1 0000 0000 0001 1110 s 28 1 0000 0000 0001 1101 s 29 1 0000 0000 0001 1100 s 30 1 0000 0000 0001 1011 s 31 1

Claims: A variable length coder for converting an input fixed bit length data to a variable bit length codeword, said variable length coder comprising: a codetable (12) for storing said variable length codewords, said variable length codewords are stored in said codetable (12) in an encoded form having a portion representing a length of a bit sequence code and a portion representing said bit sequence code, characterized by a binary memory (4) for indicating whether said codetable (12) contains a variable length codeword for said input fixed bit length data by outputting a binary value, an addresser (5) for converting the input fixed bit length data to a codetable address, said codetable address being used to index said stored variable length codewords of said codetable (12), an encoded codeword translator (34) for translating said encoded codeword which is further encoded by reducing a number of zeros at the beginning of said variable length codeword into a variable length bit sequence and a length of said variable length bit sequence. A variable length coder according to claim 1, characterized in that said binary memory (4) comprises: sub-bitmaps (16,17) each indicating only portions of all possible fixed bit length data, a comparator (18) for determining whether the input fixed bit length data is stored in one of the sub-bitmaps (16,17) and a valid logic (19) to indicate whether a variable bit length codeword is contained in said codetable (12) depending on the output of said sub-bitmaps (16,17) and said comparator (18). A variable length coder according to any of the preceding claims characterized in that said addresser (5) comprises: a basetable (6) for storing base addresses (9), said base addresses (9) are used to index the location of a contiguous group of one or more variable bit length codewords in said codetable (12), and an adder (7) for adding an offset (10) to said base address (9), the result (11) determining the location of a variable bit length codewords in said codetable (12), wherein said basetable (6) is addressed by one or more bits of the input fixed bit length data and the offset is formed by the remaining bits of the input fixed bit length data.

Inventors: BRENT WILSON WILLIAM, BRENT, WILSON WILLIAM
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H03M7
IPC codes: H03M7