Parity and syndrome generation for error detection and correction in digital communication systems

Abstract: A communication apparatus for decoding an encoded received word according to this invention has the following arrangement. A decoder (126) of a communication apparatus (120) includes a CPU A (130) for controlling decoding processing, and a memory (131) which stores a decoding processing program. The decoding processing program has a syndrome polynomial generating unit for generating a syndrome polynomial on the basis of the received word, a polynomial updating unit for updating an error locator polynomial and an error evaluator polynomial, which are set using the generated syndrome polynomial, on the basis of the degree of the error locator polynomial, and a decoded sequence generating unit for generating a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, thus decoding communication codes at a high speed with a minimum computational complexity.

Description: The present invention relates to a communication method, which corrects, at a receiving side, a data error caused by a communication path or a storage medium in a digital communication system and a digital storage system, and an apparatus therefor. Decoding methods of error-correcting codes can be classified into hard decision decoding methods and soft decision decoding methods. A hard decision decoding method is a method of performing error correction for a digital sequence obtained by hard-deciding a reception signal to "0" and "1". Since the arrangement of a decoder is simple, this method is widely used for various media such as a CD (Compact Disk). On the other hand, in a soft decision decoding method, an analog weight indicating a probability of a digital sequence obtained by soft-deciding a reception signal is calculated in addition to the digital sequence, and error correction is performed by utilizing the analog weight. For this reason, this method can sufficiently bring out the capability of error-correcting codes, and can improve the S/N ratio by about 2 to 3 dB as compared to the hard decision decoding method. A GMD (Generalized Minimum Distance) decoding method to be described below is one of the soft decision decoding methods, and is known as a decoding method which can almost perform maximum likelihood decoding using an analog weight. If the minimum distance of codes is represented by d, the conventional GMD decoding can correct a maximum of (d-1) errors, and can realize error correction about twice the correction capability obtained by a single hard decision decoding cycle. However, since the GMD decoding requires a maximum of (d-1)/2 hard decision decoding cycles, a larger computational complexity is required than the hard decision decoding method which requires only a single decoding cycle, resulting in a large calculation circuit scale and a long calculation time. It is known from ARAKI K. et al., "On a Recursive Form of Welch-Berlekamp Algorithm" published in IECE Transactions of Fundamentals of Electroniccs, Communications and Computer Sciences, vol.E76-A, no.1, January 1993, Tokyo, JP, pages 132-138 to apply a recursive Welch-Berlekamp algorithm to GMD decoding to improve decoding speed. The present invention has been made in consideration of the above-mentioned prior arts, and has its object to provide an improved communication method and an apparatus therefor. According to the present invention there is disclosed a decoder for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: syndrome polynomial generating means for generating a syndrome polynomial on the basis of a received word; polynomial updating means for updating an error locator polynomial and an error evaluator polynomial which are set; and decoded sequence generating means for generating a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that said polynomial updating means updates the error locator polynomial and the error evaluator polynomial using the generated syndrome polynomial, on the basis of a degree of the error locator polynomial. According to a further aspect of the present invention there is disclosed a decoder for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: syndrome polynomial generating means for generating a syndrome polynomial on the basis of a received word; polynomial updating means for updating an error locator polynomial and an error evaluator polynomial which are set; and decoded sequence generating means for generating a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that said polynomial updating means further updates a first polynomial generated based on an erasure position of the received word and a second polynomial generated based on the erasure position, and said polynomial updating means updates the error locator polynomial, the error evaluator polynomial, the first polynomial, and the second polynomial on the basis of coefficients of a predetermined degree of the first and the second polynomials. According to a further aspect of the present invention there is disclosed a decoding method for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: a syndrome polynomial generating step for generating a syndrome polynomial on the basis of a received word; a polynomial updating step for updating an error locator polynomial and an error evaluator polynomial which are set; and a decoded sequence generating step for generating a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that in said polynomial updating step, the error locator polynomial and the error evaluator polynomial are updated using the generated syndrome polynomial, on the basis of a degree of the error locator polynomial. According to a further aspect of the present invention there is disclosed a method for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: a syndrome polynomial generating step for generating a syndrom polynomial on the basis of a received word; a polynomial updating step for updating an error locator polynomial and an error evaluator polynomial which are set; and a decoded sequence generating step for generating a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that in said polynomial updating step, a first polynomial generated based on erasure position of the received word and a second polynomial generated based on the erasure position are further updated, and in said polynomial updating step, the error locator polynomial, the error evaluator polynomial, the first polynomial, and the second polynomial are updated on the basis of coefficients of a predetermined degree of the first and the second polynomials. Further aspects of the invention are set out in the appended claims. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiment of the present invention and, together with the description, serve to explain the principles of the invention by way of example only. Fig. 1 is a flow chart for explaining decoding processing according to the first embodiment of the present invention; Fig. 2 is a block diagram for explaining the arrangement of a degree calculation circuit based on a WB algorithm; Fig. 3 is a block diagram for explaining the arrangement of a degree calculation circuit of the first embodiment; Fig. 4 is a flow chart for explaining decoding processing according to the second embodiment of the present invention; Fig. 5 is a block diagram for explaining the arrangement of a degree calculation circuit based on a recursive WB algorithm; Fig. 6 is a block diagram for explaining the arrangement of a degree calculation circuit of the second embodiment; Fig. 7 is a view for explaining the procedures of decoding processing based on a WB algorithm; Fig. 8 is a flow chart for explaining parallel decoding processing according to the third embodiment of the present invention; Fig. 9 is a view for explaining parallel processing of the parallel decoding processing of the third embodiment; Fig. 10 is a view for explaining parallel processing of the parallel decoding processing of the third embodiment; Fig. 11 is a block diagram for explaining the arrangement of a parallel decoding processing circuit of the third embodiment; and Fig. 12 is a block diagram for explaining an example of the arrangement of a communication apparatus according to the fourth embodiment of the present invention. Preferred embodiments of the present invention will be described in detail in accordance with the accompanying drawings. (First Embodiment) A GMD decoding method and an apparatus therefor according to the first embodiment of the present invention will be described below. First, an outline of the GMD decoding method will be briefly described below, and thereafter, a description of the main subject will be given. [Outline of GMD Decoding Method] Analog weights which respectively represent probabilities of symbols in a received sequence R = (R 0 , R 1 ,..., R n-1 ) having a code length n are represented by  = ( 0 ,  1 ,...,  n-1 . Note that 0 ≤  i ≤ 1, and if  i >  j , a symbol R i in the received sequence R has a higher reliability than R j . A function x(a, b) is defined by: x(a, b) : 1 if a = b : -1 if a ≠ b An inner product R•C of the received sequence R = (R 0 , R 1 , ..., R n-1 ) and a code word C = (C 0 , C 1 , ..., C n-1 ) obtained by decoding the received sequence R is defined as follows: At this time, it has already been proved that a received sequence R which satisfies the following inequality can be accurately corrected. R•C > n - d where d is the minimum distance of C. When processing consisting of the following four steps is repetitively executed a finite number of times, a received sequence R which satisfies inequality (3) can be found out, and it can be accurately corrected: Step 1: A test sequence R' is generated by setting j (initial value is 0) symbols in the order from smaller analog weights in the received sequence R to be erasure symbols, and hard-decision-processing other symbols. Step 2: A code word C' is obtained by hard-decision decoding the test sequence R'. If the test sequence cannot be corrected, the control advances to step 4. Step 3: It is discriminated if the inner product R'·C' of the test sequence R' and the code word C' satisfies inequality (3). If the inequality is satisfied, the code word C is output; otherwise, the control advances to step 4. Step 4: "j = j + 2" is performed, and the control returns to step 1. If j ≥ d, since it means that an error exceeding error-correcting capability has occurred, decoding ends. In this manner, the GMD decoding can correct a maximum of (d-1) errors, and can realize error correction about twice the correction capability by a single hard decision decoding cycle. However, since the GMD decoding requires a maximum of (d-1)/2 hard decision decoding cycles, a larger computational complexity is required than the hard decision decoding method which requires only a single decoding cycle, and this method is not used often in practice. For this reason, E. R. Berlekamp proposed a remainder decoding method executed using a remainder polynomial obtained by dividing a received sequence by a generator polynomial of codes, and suggested a possibility of a great decrease in computational complexity required for the GMD decoding if the remainder decoding method was applied to the GMD decoding. Furthermore, E. R. Berlekamp proposed the following algorithm, called a Welch-Berlekamp (WB) algorithm, which efficiently executed remainder decoding. Since then, Morii, Araki, et. al. proved that a maximum of (d-1) errors could be corrected, i.e., the GMD decoding could be performed by a maximum of two cycles of the remainder decoding method, and verified the possibility of the decrease in computational complexity required for the GMD decoding suggested by E. R. Berlekamp. [WB Algorithm] 1) j = 0, V 0 (x) = 0, P 0 (x) = 0, U 0 (x) = 1, Q 0 (x) = 1 2) if j = 2N then end 3) a j = V j (x j ) - S(x j ) • U j (x j ) b j = Qj(x j ) - S(x j )•P j (x j ) if a j = 0 then b j = 1 4) if deg(a j •Q j (x)) < deg (b j •U j (x)) then V j+1 (x) = b j •V j (x) - a j •Q j (x) U j+1 (x) = b j •U j (x) - a j •P j (x) Q j+1 (x) = (x - x j )•Q j (x) P j+1 (x) = (x - x j )•P j (x) else Q j+1 (x) = b j •V j (x) - a j •Q j (x) P j+1 (x) = b j •U j (x) - a j •P j (x) V j+1 (x) = (x - x j )•V j (x) U j+1 (x) = (x - x j )•U j (x) 5) j = j + 1 goto 2) However, decoding processing based on the algorithm of the conventional GMD decoding does not consider the computational complexity for degrees. The decoding processing based on the WB algorithm requires two multipliers 30 and 31 for respectively performing multiplications with a j and b j and two degree check circuits 32 and 33 for checking the degrees of polynomials U j (x) and Q j (x), as shown in Fig. 2, so as to perform discrimination in 4). In the first embodiment, a discrimination method in the decoding processing, which can realize the above-mentioned degree check circuits of the two polynomials by a degree check circuit of a single polynomial will be described. Note that this technique can be applied to decoding processing based on a recursive WB algorithm (to be described later), and decoding processing with a minimum computational complexity as a whole can be realized. The discrimination method in the decoding processing which can be realized by a degree check circuit of a polynomial as a feature of the first embodiment will be described below. Morii & Araki, "Recursive Structure of Welch-Berlekamp Algorithm (IT91-100)" describes that the following formula is established for the WB algorithm: deg U j (x) + deg Q j (x) = j By modifying this formula, we have: deg Q j (x) = j - deg U j (x) In the conditional formula in 4), since a j and b j do not influence degrees of the polynomials if they are not 0, the conditional formula can be rewritten as: a j = 0 or deg Q j (x) < deg U j (x) When formula (4) is substituted in conditional formula (5), we have: a j = 0 or j/2 < deg U j (x) Since a j = 0 is checked at the end of 3), the computational complexity is not increased. Since the value j is checked upon updating in 5), the check required in formula (6) is the degree of the polynomial U j (x). Therefore, the computational complexity associated with the degree in the discrimination in 4) can be decreased. The decoding processing method of the first embodiment will be described below with reference to the flow chart in Fig. 1. This decoding processing method can achieve calculations at a higher speed by a smaller number of circuit components than the conventional WB algorithm since it need not check the degree of the polynomial Q j (x). Assume that a p-element Galois field is represented by GF(p). Processing procedures for decoding Reed-Solomon code using the following generator polynomial on the GF(p) will be explained below. G(x) = (x - α b )•(x - α b+1 )•••(x - α b+d-2 ) where α: primitive element on GF(p) d: minimum distance of codes b: arbitrary integer In step S1, a variable j for counting the number of times of processing is initialized, i.e., "j = 0". Also, an error locator polynomial U j (x) and an auxiliary error locator polynomial P j (x) are initialized to "0", and an error evaluator polynomial V j (x) and an auxiliary error evaluator polynomial Q j (x) are initialized to "1". In step S2, the variable j for counting the number of times of processing of first decoding processing is compared with a value twice a value N for determining the upper limit value of a predetermined number of times of processing. If j = 2N, the first decoding processing ends. Otherwise, the flow advances to step S3. Note that N means the error-correcting capability of codes. In step S3, a scalar quantity a j is calculated from the error evaluator polynomial V j (x), the error locator polynomial U j (x), and a syndrome polynomial S(x). Also, a scalar quantity b j is calculated from the auxiliary error evaluator polynomial Q j (x), the auxiliary error locator polynomial P j (x), and the syndrome polynomial S(x). Note that the syndrome polynomial S(x) is obtained by calculating the following formulas: T(x) = (x - x 0 ) • (x - x 1 )•••(x - x 2N-1 ) where R i (i = 0,..., n-1) is a received word having a code length n. x j (j = 0,..., 2N-1) is an element on the GF(p), which represents the position of a received symbol which has a low reliability level and is set to be an erasure error. Also, x j is numbered by j in the order of lower reliability levels. By substituting x j in turn in the error evaluator polynomial V j (x j ), the error locator polynomial U j (x j ), the error evaluator polynomial Q j (x j ), the error locator polynomial P j (x j ), and the syndrome polynomial S(x j ), the two scalar quantities a j and b j are calculated. Note that it is checked in step S4 if a j = 0, and if a j = 0, the flow advances to step S5 to set b j = 1. In step S6, it is checked if a j = "0" or the degree of U j (x) is larger than "j/2". If this condition is not satisfied, the flow advances to step S8 to calculate "j+1"-th degree polynomials V j+1 (x), U j+1 (x), Q j+1 (x), and P j+1 (x). In step S7, "j+1"-th degree polynomials V j+1 (x), U j+1 (x), Q j+1 (x), and P j+1 (x) are calculated from j-th degree polynomials, and a j and b j . In step S9, j is incremented by 1, and the processing from step S2 is repeated. With the above-mentioned processing, Reed-Solomon codes can be decoded by simpler calculations than in the decoding method using the conventional WB algorithm. Note that the discrimination processing in step S6 can be realized by, e.g., the circuit arrangement shown in Fig. 3. Referring to Fig. 3, a comparator 1 corresponding to "a j = 0" is a 0 detection circuit, and can be very easily realized by, e.g., an EX-OR gate. Also, an OR circuit 2 can be realized by a 1-bit OR gate. Therefore, only one degree check circuit for the polynomial U j (x) is required, and the circuit arrangement is simple as a whole. Similarly, when the processing is realized in a software manner, the degree checking can be realized with a smaller computational complexity. The superiority of this arrangement can be clearly recognized upon comparison with the circuit shown in Fig. 2. Referring to Fig. 2, since the multipliers 30 and 31 perform multiplications on the Galois field, they require a complicated circuit arrangement as compared to a multiplication of integers. Since two degree check circuits and two multipliers are required, the circuit scale is undesirably large. In contrast to this, the circuit shown in Fig. 3 does not require any multipliers, and requires only one degree check circuit 3, thus realizing a remarkably simple arrangement as compared to the circuit arrangement shown in Fig. 2. As described above, according to the first embodiment, high-speed decoding processing can be realized by simple calculations as compared to decoding processing based on the conventional WB algorithm. (Second Embodiment) In the second embodiment, a second decoding processing method which can achieve high-speed decoding by simple calculations as compared to a recursive WB algorithm obtained by modifying the WB algorithm (see Morii & Araki, "Recursive Structure of Welch-Berlekamp Algorithm (IT91-100)") will be described below. The recursive WB algorithm is as follows. Note that the recursive WB algorithm can decrease the total computational complexity as compared to the WB algorithm. [Recursive WB Algorithm] 10) j = 0, L = 0, L' = 0, 20) if j = 2N then end 30) a j = A j (x j ) b j = B j (x j ) if a j = 0 then b j = 1 40) if deg(a j •x L' ) < deg(b j •x L ) then L' = L' + 1 else 50) Δ = Y•Δ P = Y•P 60) j = j + 1 goto 20) In the decoding processing method of the second embodiment, a decrease in total computational complexity by decreasing the number of variables in calculations is the main objective. The decoding processing based on the recursive WB algorithm adopts the circuit arrangement for supporting discrimination processing in 40), as shown in Fig. 5. Referring to Fig. 5, reference numerals 47 and 48 denote registers for respectively storing temporary values of L and L'. Adders 50 and 49 respectively increment L and L' stored in the registers 47 and 48 by 1. Non-zero detection circuits 43 and 44 are circuits for respectively detecting if values a j and b j are non-zero. If these values are non-zero, the values are supplied to AND circuits 45 and 46, and are logically ANDed to the output values L and L' from the adders 50 and 49, respectively. Note that the outputs from the AND circuits 45 and 46 are values indicating the degrees of a j •x L' and b j •x L . These degrees are compared by a comparator 40, and a comparison result is output. The decoding processing method of the second embodiment can execute decoding processing based on the recursive WB algorithm at a higher speed by simpler calculations, and will be described below with reference to the flow chart in Fig. 4. In the decoding processing method of the second embodiment, a calculation associated with L' corresponding to the degree of a polynomial Q j (x) need not be performed as compared to the decoding processing based on the recursive WB algorithm. In step S10, a variable j for counting the number of times of processing is initialized, i.e., "j = 0". Also, an error locator polynomial U j (x) and an auxiliary error locator polynomial P j (x) are initialized to "0", and an error evaluator polynomial V j (x) and an auxiliary error evaluator polynomial Q j (x) are initialized to "1". Assume that P j (x), Q j (x), U j (x), and V j (x) are expressed as elements of a matrix P. L representing the degree of each of the polynomials Q j (x) and U j (x) is initialized to "0". Furthermore, the following polynomials for calculating a j and b j by substituting x j are introduced, and are expressed as elements of a matrix Δ: A j (x) = V j (x) - S(x)•U j (x) B j (x) = Q j (x) - S(x)•P j (x) Note that Δ has the following initial values by substituting the initial values of the polynomials: A 0 (x) = -S(x) B 0 (x) = 1 In step S11, the variable j for counting the number of times of processing of second decoding processing is compared with a value twice a value N for determining the upper limit value of a predetermined number of times of processing. If j = 2N, the second decoding processing ends. Otherwise, the flow advances to step S12. Note that N means the error-correcting capability of codes. In step S12, a j and b j are obtained by substituting x j in A j (x) and B j (x). Note that it is checked in step S13 if a j = 0, and if a j = 0, the flow advances to step S14 to set b j = 1. It is checked in step S15 if a j is "0" or L is larger than "j/2". If L is smaller than "j/2", the flow advances to step S16. Otherwise, the flow advances to step S17 to set a matrix Y as follows, and to increment L by 1: In step S16, the matrix Y is set as follows: In step S18, updating calculations of the matrices P and Δ are performed. In step S19, j is incremented by 1, and processing steps from step S11 are executed. Decoded data are generated based on the error locator polynomial and the error evaluator polynomial which are obtained, as described above. With the above-mentioned processing, Reed-Solomon codes can be decoded by simpler calculations than in the decoding method using the conventional recursive WB algorithm. The discrimination processing in step S15 in the second decoding processing method can be realized by, e.g., the circuit arrangement shown in Fig. 6. Referring to Fig. 6, a comparator 22 compares a j and "0", and outputs the comparison result to an OR circuit 20. A register 24 stores a temporary value L. This L is incremented by an adder 23, and is output to a comparator 21 and the register 24. The register 24 stores the incremented value L. On the other hand, the comparator 21 compares the incremented value L and "j/2", and outputs the comparison result to the OR circuit 20. The OR circuit 20 receives the outputs from the comparators 21 and 22, logically ORs these outputs, and outputs a calculation result. As can be seen from a comparison between the circuit arrangement of degree processing based on the recursive WB algorithm shown in Fig. 5, and the degree processing circuit of the second embodiment, degree processing can be realized by a smaller circuit with a smaller computational complexity. More specifically, from the circuit arrangement for degree processing based on the recursive algorithm, at least the register 48 and the adder 49 associated with L' can be omitted. Note that the technique for decreasing the computational complexity associated with the degree is effective not only for the above-mentioned WB algorithm and the recursive WB algorithm, but also for other algorithms having relations of formulas (4) and (5). In formula (4), the degree of Q j (x) is expressed by the degree of U j (x). Alternatively, the degree of U j (x) can be expressed by the degree of Q j (x) as follows: deg U j (x) = j - deg Q j (x) Therefore, the conditional formula in step S15 can also be expressed as follows: aj = 0 or j/2 > deg Q j (x) In this case, in place of the degree (L') of Q j (x), checking (calculation) of the degree (L) of U j (x) can be omitted. P j (x) and U j (x) represent error locator polynomials, and Q j (x) and V j (x) represent error evaluator polynomials. Since Q j (x) is no longer related to control of the algorithm according to the present invention, if error evaluator polynomials are not necessary like in BCH codes, Q j (x) and V j (x) themselves can be omitted, and the computational complexity can be further decreased. As described above, in the decoding processing method of the second embodiment, the computational complexity associated with the degree can be decreased, and a GMD decoding algorithm with a minimum total computational complexity can be realized. When error evaluator polynomials are not necessary like in BCH codes, Q j (x) and V j (x) need not be calculated, and the computational complexity can be further decreased. (Third Embodiment) In the third embodiment, a new decoding method which allows high-speed calculations, based on parallel processing, of the WB algorithm, which cannot be conventionally achieved by parallel processing, will be described below. It is difficult for the above-mentioned WB algorithm to parallelly calculate the j-th degree polynomials (U j (x), V j (x), P j (x), Q j (x)) and (j+1)-th degree polynomials (U j+1 (x), V j+1 (x), P j+1 (x), Q j+1 (x)). This is because calculations of the (j+1)-th degree polynomials require a j and b j , and a j and b j are calculated using all the coefficients of the j-th degree polynomials. Therefore, since a j and b j are obtained after completion of calculations of the j-th degree polynomials, the calculations of the (j+1)-th degree polynomials can only be started thereafter. Therefore, as shown in Fig. 7, in the WB algorithm, updating calculations of the polynomials are sequentially performed. Fig. 7 will be briefly described below. The time base of the calculations is plotted along an abscissa 70. Variables for decoding processing using the WB algorithm are plotted along an ordinate 71. The calculation order is as follows. First, a 0 and b 0 are calculated, and P 1 , Q 1 , U 1 , and V 1 are then calculated using these values. Then, a 1 and b 1 are calculated from P 1 , Q 1 , U 1 , and V 1 . Following the same procedures, P 2 , Q 2 , U 2 , and V 2 are calculated to calculate a 2 and b 2 ,..., and finally, P p , Q p , U p , and V p are calculated. Such recurrence calculation procedures also apply to the above-mentioned recursive WB algorithm. Therefore, the WB algorithm and its recursive WB algorithm cannot achieve high-speed processing since they cannot perform parallel processing associated with updating of j. Therefore, the third embodiment has as its object to provide a parallel decoding processing method which can realize high-speed decoding processing. The parallel decoding processing method of the third embodiment will be described in detail below. First, the following polynomials A j (x) and B j (x) are defined: A j (x) = V j (x) - S(x)•U j (x) = ΣA m •X m B j (x) = Q j (x) - S(x)•P j (x) = ΣB m •X m Therefore, a j and b j obtained in 3) in the WB algorithm are respectively given by: a j = A j (x j ) b j = B j (x j ) Also, the following polynomials Z(x,y), C(x,y), and D(x,y) are defined: (v is an arbitrary integer) Therefore, as can be seen from the above formulas, if i = m is set in formulas (14) and (15), a j and b j can be (x v •y j )-th degree coefficients of the polynomials C(x,y) and D(x,y) . On the other hand, C(x,y) and D(x,y) can be updated as follows: (a) When deg(a j •Q j (x)) < deg(b j •U j (x)) From V j+1 (x) = b j •v j (x) - a j •Q j (x) U j+1 (x) = b j •U j (x) - a j •P j (x) Q j+1 (x) = (x - x j )•Q j (x) P j+1 (x) = (x - x j )•P j (x) A j+1 (x) and B j+1 (x) are updated as follows: A j+1 (x) = b j •Aj(x) - a j •B j (x) B j+1 (x) = (x - x j )•B j (x) Therefore, in this case, C(x,y) and D(x,y) can be updated as follows: C j+1 (x,y) = A j+1 (x) • Z(x,y) = (b j •A j (x) - a j •B j (x))•Z(x,y) = b j •C j (x,y) - a j •D j (x,y) D j+1 (x,y) = B j+1 (x) • Z(x,y) = (x - x j ) • B j (x) • Z(x,y) = (x - x j )•D j (x,y) (b) When deg (a j •Q j (x)) ≥ deg (b j •U j (x)) From Q j+1 (x) = b j •V j (x) - a j •Q j (x) P j+1 (x) = b j •U j (x) - a j •P j (x) V j+1 (x) = (x - x j )•V j (x) U j+1 (x) = (x - x j )•U j (x) A j+1 (x) and B j+1 (x) are updated as follows: A j+1 (x) = (x - x j )•A j (x) B j+1 (x) = b j •A j (x) - a j •B j (x) Therefore, in this case, C(x,y) and D(x,y) can be updated as follows: C j+1 (x, y) = A j+1 (x)•Z(x,y) = (x - x j )A j (x)•Z(x,y) = (x - x j )•C j (x,y) D j+1 (x,y) = B j+1 (x)•Z(x,y) = (b j •A j (x) - a j •B j (x))•Z(x,y) = b j •C j (x,y) - a j •D j (x,y) Therefore, since a j and b j are (x v •y j )-th degree coefficients of the polynomials C j (x,y) and D j (x,y) without calculations in 3) in the WB algorithm described in the first embodiment, the WB algorithm can be modified as follows: [Decoding Algorithm of Third Embodiment] 100) j = 0, C 0 (x,y) = -S(x)•Z(x,y), D 0 (x,y) = Z(x,y) V 0 (x) = 0, P 0 (x) = 0, U 0 (x) = 1, Q 0 (x) = 1 200) if j = p then end 300) set (x v •y j )-th degree coefficient of C j (x,y) to be aj set (x v •y j )-th degree coefficient of D j (x,y) to be b j if a j = 0 then b j = 1 400) if deg (a j •Q j (x)) < deg (b j •U j (x)) then C j+1 (x,y) = b j •C j (x,y) - a j •D j (x,y) U j+1 (x) = b j •U j (x) - a j •P j (x) V j+1 (x) = b j •V j - a j •Q j (x) D j+1 (x,y) = (x - x j )•D j (x,y) P j+1 (x) = (x - x j )•P j (x) Q j+1 (x) = (x - x j )•Q j (x) else D j+1 (x,y) = b j •C j (x,y) - a j •D j (x,y) P j+1 (x) = b j •U j (x) - a j •P j (x) Q j+1 (x) = b j •V j (x) - a j •Q j (x) C j+1 (x,y) = (x - x j ) • C j (x,y) U j+1 (x) = (x - x j )•U j (x) V j+1 (x) = (x - x j )•V j (x) 500) j = j + 1 goto 200 Fig. 8 is a flow chart showing the decoding processing of the above-mentioned decoding algorithm of the third embodiment. The decoding processing will be described below with reference to this flow chart. In step S80, a variable j for counting the number of times of processing is initialized, i.e., "j = 0". Also, the polynomials C 0 (x,y), D 0 (x,y), V 0 (x), P 0 (x), U 0 (x), and Q 0 (x) are initialized. In step S81, the variable j for counting the number of times of processing is compared with a predetermined number p of times of repetition, and if j = p, the decoding processing ends. Otherwise, the flow advances to step S82. In step S82, the (x v •y j )-th degree coefficient of C j (x,y) is set to be a j . Also, the (x v •y j )-th degree coefficient of D j (x,y) is set to be b j . In step S83, it is checked if a j = 0. If a j = 0, the flow advances to step S84 to set b j = 1. In step S85, the degree of a j •Q j (x) is compared with the degree of b j •U j (x). If the degree of a j •Q j (x) is smaller than the degree of b j •U j (x), the flow advances to step S86; otherwise, the flow advances to step S87. In steps S86 and S87, the updating calculations of the polynomials described in the corresponding steps in Fig. 8 are executed. In step S88, j is incremented by 1, and the flow returns to step S81 to repeat the above processing. In the decoding method according to the third embodiment described above, parallel processing associated with j can be performed. In the decoding processing of the third embodiment, a j and b j are the (x v •y j )-th degree coefficients of C j (x,y) and D j (x,y). If C j+1 (x,y) or D j+1 (x,y) is sequentially calculated from higher degrees toward lower degrees using C j (x,y) and D j (x,y), the calculations of the (j+1)-th degree polynomials can be started when the (x v •y j )-th degree coefficients of C j (x,y) and D j (x,y) are obtained. This means that parallel calculations of j-th degree polynomials and (j+1)-th degree polynomials can be performed. Therefore, in the decoding method of the third embodiment, the calculations of the j-th degree polynomials can be parallelly executed, as shown in Fig. 9. In Fig. 9, the time base of the calculations is plotted along an abscissa 90. Also, variables for the third decoding processing are plotted along an ordinate 91. As can be seen from Fig. 9, in the decoding processing of the third embodiment, if a plurality of processing circuits for performing updating calculations of polynomials are prepared, the processing speed can be easily increased in proportion to the number of processing circuits. Even when the updating calculation of each j-th degree polynomials is performed by one clock, the calculation time requires only about p clocks, as shown in Fig. 10, and higher-speed calculations than those based on the conventional WB algorithm can be realized. Note that the time base of the calculations is plotted along an abscissa 100 in Fig. 10. In addition, variables for the third decoding processing are plotted along an ordinate 101. Therefore, the decoding processing of the third embodiment can be realized by, e.g., an apparatus shown in Fig. 11 The respective processing units will be described below. A memory 110 stores initial values and their updated values set in step S80. The memory 110 is accessed by a control circuit 112 and a polynomial calculation processing circuit 111, as needed. The control circuit 112 performs the following control. That is, a1: It is checked if j is equal to the predetermined number p of times of processing, and if j is not equal to p, the processing in step S82 is selected. a2: It is checked if a j is equal to 0, and if a j = 0, b j = 1. a3: If a j is not equal to 0, the degree discrimination in step S85 is performed, and the processing in step S86 or S87 is selected in accordance with the discrimination result. After the processing is selected, execution of the selected processing is requested for the polynomial calculation processing circuit 111. The polynomial calculation processing circuit 111 executes the selected processing in accordance with the request. The polynomial calculation processing circuit 111 executes the selected processing, i.e., calculation processing in step S86 or S87, on the basis of the processing request from the control circuit 112. Note that the control circuit 112 and the polynomial calculation processing circuit 111 need not be separated since they can be executed in a software manner using, e.g., a CPU. Since calculations required in the control circuit 112 and the polynomial calculation processing circuit 111 are simple multiplications/divisions and additions/subtractions of integers, no special processing circuit is required. Since the updating calculations of P j+1 (x), Q j+1 (x), U j+1 (x), V j+1 (x), C j+1 (x), and D j+1 (x) can be simultaneously executed, a plurality of processing circuits may be independently arranged. Alternatively, since the updating calculations of polynomials are achieved by similar processing, they can be executed by a single circuit. As can be understood from the above description, the circuit arrangement for executing the decoding processing of the third embodiment can be simplified. Note that the modification technique of the WB algorithm described in the decoding method of the third embodiment can be applied to the recursive algorithm described in "Recursive Structure of Welch-Berlekamp Algorithm (IT91-100)" described above, and high-speed parallel processing of the recursive WB algorithm can be achieved. C j (x,y) and D j (x,y) are used for calculating a j and b j as their (x v •y j )-th degree coefficients, and other coefficients are not necessary. Therefore, as described in a well-known continued fraction method (see L. R. Welch and R. A. Scholtz: "Continued fractions and Berlekamp's algorithm", IEEE Trans. Inf. Theory, IT-25, pp. 19-27, Jan 1979), calculations which are not related to the final result can be omitted, and the total computational complexity can be reduced. Note that the present invention may be applied to either a system constituted by a plurality of devices or an apparatus consisting of a single device. Also, the present invention may be applied to a case wherein the invention is achieved by supplying a program to a system or apparatus, as a matter of course. In general, a high-speed algorithm often means one with a smaller computational complexity. However, in order to realize high-speed processing, an approach which decreases the computational complexity of the algorithm and an approach which improves the degree of parallelism of the algorithm are available. This is because the processing time can be shorted by simultaneously executing a plurality of processing operations by parallel processing. A large-scale parallel processing chip can be easily realized due to the recent advance of VLSI techniques. Therefore, an algorithm with a high degree of parallelism is often suitable for high-speed processing. The third embodiment is an example of the invention made in consideration of the background that a parallel processing circuit can be realized with low cost due to the advance of the VLSI techniques. As described above, according to the decoding processing method of the third embodiment, higher-speed-processing with a higher degree of parallelism than the conventional WB algorithm can be realized. The conventional WB algorithm requires two different kinds of calculations, i.e., the updating calculations of polynomials and the substitution calculations for calculating a j and b j , while the decoding processing method of the third embodiment requires only the updating calculations of polynomials, thus realizing a simple communication apparatus which can perform high-speed decoding. (Fourth Embodiment) In the first to third embodiments, the decoding method and apparatus for communication codes have been described. In the fourth embodiment, an example of a communication apparatus which comprises these decoding method and apparatus will be described. Fig. 12 is a schematic block diagram showing the arrangement of a communication apparatus 120 according to the fourth embodiment. The communication apparatus 120 of the fourth embodiment will be described below with reference to Fig. 12. A CPU 121 controls the entire communication apparatus 120. A control program is pre-stored in a ROM 124, and the CPU 121 executes this control program. A keyboard 122 is an input terminal for inputting commands and data for the communication apparatus 120. A RAM 123 stores work data and communication data with which the CPU 121 executes various kinds of processing. A monitor 125 displays various kinds of processing results in the communication apparatus 120, communication data, input commands from the keyboard 122, and the like. An encoder 127 performs encoding processing of communication data stored in the RAM 123, and outputs encoded data onto a communication line 129. A decoder 126 decodes encoded data transmitted from an external communication apparatus via a communication line 128, and stores decoded data in the RAM 123. Note that the decoder 126 is a portion for performing decoding processing based on the decoding method of one of the first to third embodiments. The decoder 126 includes a CPU A 130 for controlling the decoding processing, and a memory 131 which stores a decoding program corresponding to the decoding method. In the communication apparatus of the fourth embodiment, received encoded data can be decoded at high speed. Note that the present invention may be applied to either a system constituted by a plurality of devices or an apparatus consisting of a single device. Also, the present invention may be applied to a case wherein the invention is achieved by supplying a program to a system or apparatus, as a matter of course. As described above, according to the present invention, communication codes can be decoded at high speed with a minimum computational complexity. According to another aspect of the present invention, communication codes can be decoded at highest speed.

Claims: A decoder for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: syndrome polynomial generating means for generating a syndrome polynomial (S(x)) on the basis of a received word (R); polynomial updating means for updating an error locator polynomial (U j (x)) and an error evaluator polynomial (V j (x)) which are set; and decoded sequence generating means for generating a decoded sequence (C) on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that said polynomial updating means is adapted to update the error locator polynomial and the error evaluator polynomial using the generated syndrome polynomial, on the basis of a degree of the error locator polynomial. The decoder according to claim 1, wherein said polynomial updating means comprises: degree calculating means (3,23,24) for calculating a degree of the error locator polynomial; and update control means (2,4,20,21) for controlling the updating of the error locator polynomial and the error evaluator polynomial on the basis of a result of comparison between the calculated degree and a predetermined threshold value. A decoder for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: syndrome polynomial generating means for generating a syndrome polynomial (S(x)) on the basis of a received word (R); polynomial updating means (111,112) for updating an error locator polynomial (U j (x)) and an error evaluator polynomial (V j (x)) which are set; and decoded sequence generating means for generating a decoded sequence (C) on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that said polynomial updating means is further adapted to update a first polynomial (D j (x,y)) generated based on a erasure position (x j ) of the received word and a second polynomial (C j (x,y)) generated based on the erasure position, and said polynomial updating means is adapted to update the error locator polynomial, the error evaluator polynomial, the first polynomial, and the second polynomial on the basis of coefficients of a predetermined degree of the first and the second polynomials. A communication apparatus (120) comprising a decoder (126) according to any of preceding claims. A decoding method for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: a syndrome polynomial generating step for generating a syndrome polynomial (S(x)) on the basis of a received word (R); a polynomial updating step (S7,S8,S16,S17,S18) for updating an error locator polynomial (U j (x)) and an error evaluator polynomial (V j (x)) which are set; and a decoded sequence generating step for generating a decoded sequence (C) on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that in said polynomial updating step, the error locator polynomial and the error evaluator polynomial are updated using the generated syndrome polynomial, on the basis of a degree of the error locator polynomial. The method according to claim 5, wherein said polynomial updating step comprises: a degree calculating step (S17) for calculating a degree of the error locator polynomial; and an update control step (S6,S15) for controlling the updating of the error locator polynomial and the error evaluator polynomial on the basis of a result of comparison between the calculated degree and a predetermined threshold value. A method for decoding an encoded received word by generalized minimum distance decoding using a remainder decoding algorithm, comprising: a syndrome polynomial generating step for generating a syndrome polynomial (S(x)) on the basis of a received word (R); a polynomial updating step (S86,S87) for updating an error locator polynomial (U j (x)) and an error evaluator polynomial (V j (x)) which are set; and a decoded sequence generating step for generating a decoded sequence (C) on the basis of the error locator polynomial and the error evaluator polynomial, characterised in that in said polynomial updating step, a first polynomial (D j (x,y)) generated based on erasure position (x j ) of the received word and a second polynomial (C j (x,y)) generated based on the erasure position are further updated, and in said polynomial updating step, the error locator polynomial, the error evaluator polynomial, the first polynomial, and the second polynomial are updated on the basis of coefficients of a predetermined degree of the first and the second polynomials. A communication method using the decoding method according to any of claims 5 to 7. A computer program comprising processor implementable instructions for causing a decoder to perform all the steps of a method according to any one of claims 5 to 7.

Inventors: IWAMURA KEIICHI, IWAMURA, KEIICHI, IWAMURA, KEIICHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: H04L1
IPC codes: H04L1, H03M13