High voltage MIS field effect transistor

Abstract: A high voltage MIS field effect transistor includes a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on an obverse surface side of said semiconductor substrate; a base layer of the first conductivity type formed in said semiconductor layer; a source layer of the second conductivity type formed in said base layer; a source electrode abutting said source layer; a gate electrode formed in such a manner as to extend from said source layer to said semiconductor layer via an insulating gate film; a drain section including a drain layer of the second conductivity type formed in said semiconductor layer; said drain section including a plurality of parallel regions and having its periphery surrounded by said gate electrode and said source electrode; a first drain pad opening portion in a first parallel region of said plurality of parallel regions; and a second drain pad opening portion in a second parallel region of said plurality of parallel regions adjacent to said first parallel region; wherein said first drain pad portion is offset outwardly in a lengthwise direction of said respective parallel regions with respect to said second drain pad opening portion, and a width of a portion of said first parallel region where said fist drain pad opening portion is not formed, is set to be smaller than a width of said first parallel region where said first drain pad opening portion is formed.

Description: BACKGROUND OF THE INVENTION The present invention relates to a configuration of a MIS (Metal Insulator Semiconductor) field effect transistor, particularly to a high voltage MIS field effect transistor aimed at withstanding a high voltage. More particularly, the present invention relates to a technique for integrating this high voltage MIS field effect transistor together with a control circuit section to a high density. Conventionally, a planar cell structure shown in Fig. 8 has been adopted to integrate a high voltage MIS field effect transistor. The high voltage MIS field effect transistor shown in Fig. 8 is an n-channel-type MOSFET, in which drain regions 702, which are output terminal regions, are juxtaposed in parallel on an n-type semiconductor layer, and the drain regions 702 are surrounded by an input terminal region 701 constituted by a source layer, gate electrodes, and the like. A drain pad opening portion 703 is formed at each of both ends of the drain region 702, and a wire is conductively connected to the drain pad opening portion 703 to control the MOSFET. With the MOSFET of the above-described configuration, however, it is necessary to secure a distance between adjacent ones of the drain regions 702 by not less than the width of the drain pad opening portion 703, so that there have been limits to attain the high integration and low on-resistance of the device. Therefore, as a device which has a higher degree of integration and permits low on-resistance, there is a device in which the input terminal region 701 and the output terminal region (drain region ) 702 are formed in an interdigitated shape, and an example of it is shown in Fig. 9. In this high voltage MOSFET, three drain regions 702a to 702c extend so as to branch off from the drain region 702 where the drain pad opening portion 703 is formed, and input terminal regions 701 a and 701b are respectively formed between adjacent ones of these drain regions 702a to 702c. With the high voltage MOSFET having the above-described configuration, it is unnecessary to form drain pads in the respective comb-teeth-shaped drain regions 702a to 702c, making it possible to form the drain regions 702a to 702c with a narrow pitch. Since the enlargement of the channel width can be attained, it is possible to attain the high integration (a large current capacity) and low on-resistance of the device. In recent years, active development has been made of power ICs in which a power MOSFET capable of withstanding several hundred voltages or more and having a high-current output of several amperes and a control circuit section operating at a low voltage of about 5 V are incorporated in a single chip. As ICs for switching power sources, there are some which have already been realized. However, in order to realize such power ICs at low cost, a reduction in the chip size is essential. Accordingly, it is an important problem to minimize the power MOSFET section which occupies a large area in the power IC. In Patent Abstracts of Japan, Vol 013, No.513 (E-A847) November 16, 1989 and JP 01207976A, it is disclosed to make the width of channel per unit area large by a factor of two or more and secure high breakdown withstanding capacity, by forming gate electrodes into a curving line like shape and further, holding drain and source electrode-contact positions alternately. Patent Abstracts of Japan, Vol 012, No. 111 (E-598) April 8, 1988 and JP 622 242365A discloses to enlarge peripheral lengths of respective transistors and to enable high density integration of MOS type output circuit element containing the transistors for driving of a large current having favourably areal efficiency by a method wherein the source diffusion layers and the drain diffusion layers of the element are so constructed as to enter mutually in the type of the teeth of combs. Summary of the Invention Accordingly, in view of the prior art disclosed by the above-mentioned patent abstracts of Japan, it is an object of the present invention to realise a high voltage MIS field effect transistor with an even higher degree of integration while maintaining the maximum curvature at a value sufficiently low to obtain a high withstand voltage. This object is solved by the high voltage MIS field effect transistor with the features of the present claim 1. In such a configuration, the width of a portion where the drain pad opening portion is not formed in the second parallel region may be set to be smaller than the width of the drain pad opening portion. Additionally, the radius of curvature of the drain pad opening portion may preferably have a withstand voltage securing length which makes it possible to secure a predetermined withstand voltage. Furthermore, it is possible to adopt a configuration in which two or more of any of the plurality of parallel regions are connected. In the above-described high voltage withstanding structure of the planar structure for high integration, the source electrode may be formed as a field plate-type source electrode, and the drain electrode may be formed as a field plate-type drain electrode. Meanwhile, as the planar construction of the element in accordance with the present invention, the drain pad opening portion in the first parallel region is formed by being offset outwardly in the lengthwise direction of parallelism with respect to the drain pad opening portion in the second parallel region adjacent to the first parallel region, and the width of a portion where the drain pad opening portion is not formed in the first parallel region is set to be smaller than the width of the drain pad opening portion. Accordingly, it becomes possible to reduce the distance between adjacent parallel regions while securing a substantial distance between drain pad opening portions, which is considered necessary for securing a targeted withstand voltage. In addition, even in a case where the distance between the parallel regions is reduced, it is possible to secure the MIS section region provided between the parallel regions. Accordingly, it becomes possible to reduce the distance between the parallel regions without deteriorating the withstand voltage, and low on-resistance due to high integration can be attained. Furthermore, in a case where the width of a portion where the drain pad opening portion is not formed in the second parallel region is set to be smaller than the width of the drain pad opening portion, it is possible to increase the channel width, so that the low on-resistance can be promoted further. Brief Description of the Drawings Fig. 1(a) is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a first embodiment; Fig. 1(b) is a cross-sectional view taken along line X - X' in Fig. 1(a); Fig. 2 is a graph illustrating dependence of the withstand voltage of a device on the radius of curvature; Fig. 3 is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a second embodiment of the present invention; Fig. 4 is a plan view illustrating a configuration of a high voltage MOSFET as a modification of the second embodiment of the present invention; Fig. 5 is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a third embodiment of the present invention; Fig. 6 is a plan view illustrating a configuration of a high voltage MOSFET as a modification of the third embodiment of the present invention; Fig. 7 is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a fourth embodiment of the present invention; Fig. 8 is a plan view illustrating a configuration of a conventional high voltage MOSFET; Fig. 9 is a plan view illustrating a configuration of a conventional high voltage MOSFET; Detailed Description of the Preferred Embodiments Referring to the accompanying drawings, preferred embodiments of the present invention will be described hereafter. [First Embodiment] Fig. 1(a) is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a first embodiment of the present invention, and Fig. 1(b) is a cross-sectional view thereof taken along line X - X' in Fig. 1(a). First, the high voltage MOSFET in accordance with this embodiment will be described with reference to the cross-sectional view shown in Fig. 1(b). An n-type well layer 602 is formed on a p-type semiconductor substrate 601 by means of diffusion formation or the like. A pair of diffusion-formed p-type semiconductor regions (offset layers) 603 are formed on the obverse surface side of the well layer 602, and an n + -type source layer 605 is formed in each of these offset layers 603. A gate electrode 604 is formed in such a manner as to extend between this pair of source layers 605 via a gate oxide film, thereby forming a MOS section 609. In addition, an n + - type drain layer 606a is formed on one side (lefthand side) of the MOS section 609, thereby forming a drain section A 610. Meanwhile, an n + - type drain layer 606b is formed on the other side (right-hand side) of the MOS section 609, thereby forming a drain section B 613. Here, a source electrode 607 is connected to the source layer 605, and this source electrode 607 has field plate portions respectively projecting over insulating films 615 toward the drain section A 610 and the drain section B 613 which will be described later. Also, drain electrodes 608 are respectively connected to the drain layer 606a of the drain section A 610 and the drain layer 606b of the drain section B 613, and the MOS section 609 side of this drain electrode 608 is formed as a field plate portion projecting over the insulating film 615. A point to be noted in the high voltage MOSFET (horizontal-type n-channel type MOSFET) in accordance with this embodiment lies in its planar structure shown in Fig. 1(a). A first point lies in that drain pad opening portions 614, which are formed at both ends of the drain section B 613, are formed by being offset outwardly with respect to drain pad opening portions 611, which are formed at both ends of the drain section A 610 adjacently confronting the drain section B 613, in the lengthwise direction of parallels formed by the drain section A 610 and the drain section B 613. A second point lies in that, in the drain section B 613, the width of its nonformation region portion where the drain pad opening portion 614 is not formed is set to be smaller than the width of its end where the drain pad opening portion 614 is formed. Here, the region width of the drain section A 610 is set to be 184 µm, whereas the region width at the end of the drain section B 613 is set to be 184 µm, and the region width at the central portion (the pad-nonformation region portion) is set to be 5 µm. In such a high voltage MOSFET, first, with respect to its cross-sectional structure, the source-drain distance is 97 µm, the thickness of the gate oxide film is 250 A, the gate length is 14 µm, the surface concentration at the semiconductor substrate 601 is 1.6 x 10 14 cm -3 , the surface concentration at the well layer 602 is 2.0 x 10 16 cm -3 , and the surface concentration at the offset layer 603 is 9.0 x 10 16 cm -3 . Accordingly, it is possible to attain a withstand voltage of 650 V by virtue of such a cross-sectional structure. Meanwhile, with respect to the planar structure, 87 µm or more is secured as the radius of curvature at the end of the drain section A 610 and the radius of curvature at the end of the drain section B 613, respectively. This value (the radius of curvature of 87 µm) is a minimum value required for attaining the withstand voltage of 650 V as shown in Fig. 2. Thus, in this high voltage MOSFET, its structure is capable of attaining the withstand voltage of 650 V in terms of its cross-sectional and planar structures, so that the targeted withstand voltage of 650 V can be attained. Furthermore, in this high voltage MOSFET, as the drain pad opening portions 614 of the drain section B 613 are formed in such a manner as to be offset outwardly in the lengthwise direction of parallels relative to drain pad opening portions 611 of the drain section A 610, even if the inter-drain pitch between the drain section A 610 and the drain section B 613 which are located adjacent to each other is reduced, the substantial spaced-apart distance between the drain pad opening portion 611 and the drain pad opening portion 614 can be secured in correspondence with a required withstand voltage. Accordingly, since the inter-drain pitch can be reduced without causing a decline in the withstand voltage, the degree of integration of the element can be increased, and a low on-resistance can be obtained. It should be noted that, in this high voltage MOSFET, the length of one side of the drain pad opening portion 611 and the length of one side of the drain pad opening portion 614 are equal and are 110 µm. In addition, in the drain section A 610, the distance between the drain pad opening portions 611 is 1000 µm, and, in the drain section B 613, the distance between the drain pad opening portions 614 is 1500 µm. [Second Embodiment] Fig. 3 is a plan view illustrating a configuration of a high voltage MOSFET in accordance with a second embodiment of the present invention. It should be noted that, in Fig. 3, portions common to those of the high voltage MOSFET in accordance with the first embodiment shown in Fig. 1 are denoted by the same reference numerals, and description thereof will be omitted. In addition, in the high voltage MOSFET in accordance with this embodiment, its cross-sectional structure is substantially identical to the cross-sectional structure shown in Fig. 1(b). In the high voltage MOSFET in accordance with this embodiment, the degree of integration of the device can be improved substantially by alternately disposing a plurality of the drain sections A 610 and the drain sections B 613. The drain section A 610 and the drain section B 613 shown in Fig. 3 are of the same size as the drain section A 610 and the drain section B 613 shown in Fig. 1(a). However, by alternately disposing two drain sections A 610 and three drain sections B 613 in the device having a size of 1.4 x 1.5 mm, the channel width can be increased by 25% as compared with the conventional high voltage MOSFET shown in Fig. 8. Accordingly, it is possible to increase the degree of integration and the low on-resistance can be promoted while maintaining a high withstand voltage. In addition, Fig. 4 is a modification of the high voltage MOSFET in accordance with the above-described second embodiment, which is a high voltage MOSFET in which the drain pad opening portion 614 is not formed on the lower side of the drain section B 613, but three drain sections B 613 are connected at their lower ends. The radius of curvature of a connecting portion 612 connecting the drain sections B 613 is 378 µm, which is sufficiently large so that the concentration of the electric field does not occur at this portion. Accordingly, in the same way as the high voltage MOSFET shown in Fig. 3, it is possible to reduce the on-resistance due to high integration while maintaining a high withstand voltage. In addition, in the high voltage MOSFET shown in Fig. 4, it is not necessary to enlarge a lower side end of the drain section B 613 on the basis of the radius of curvature at which a targeted withstand voltage is securable, and wiring is facilitated. It should be noted that the device size of the high voltage MOSFET shown in Fig. 4 is 1.4 x 1.5 mm similarly to the high voltage MOSFET shown in Fig. 3, and an increased portion of the channel width as compared with the conventional device shown in Fig. 8 is 13%. [Third Embodiment] Fig. 5 is plan view illustrating a configuration of a high voltage MOSFET in accordance with a third embodiment of the present invention. It should be noted that, in the high voltage MOSFET shown in Fig. 5, portions common to those of the high voltage MOSFET in accordance with the first embodiment shown in Fig. 1 are denoted by the same reference numerals, and description thereof will be omitted. A point to be noted in the high voltage MOSFET in accordance with this embodiment is that only the drain sections B in which the distance between the drain pad opening portions differs are juxtaposed in five rows. That is, a drain section B 613a whose distance between the drain pad opening portions is approximately 2000 µm is formed in a central portion of the device, and drain sections B 613b whose distance between the drain pad opening portions is approximately 1750 µm are formed on both sides of the drain section B 613a. Furthermore, a drain section B 613c whose distance between the drain pad opening portions is approximately 1500 µm is formed along a side of the drain section B 613b which is away from the drain section B 613a. In the high voltage MOSFET having the above-described configuration, since the inter-drain pitch between the drain pad opening portions in the adjacent drain sections can be reduced while securing a targeted withstand resistance to a degree that the targeted withstand resistance can be maintained, it is possible to reduce the on-resistance due to high integration in a state in which a high withstand voltage is being maintained. Furthermore, in the high voltage MOSFET in accordance with this embodiment, the drain section B 613a whose distance between the drain pad opening portions is the longest is formed in the center, and the drain section B 613b and the drain section B 613c are formed along each side of this drain section B 613a in such a manner that the distance between the drain pad opening portions becomes consecutively smaller. For this reason, as is apparent from the planar structure shown in Fig. 5, the size of the region of the MIS section 609 left on the side end of each of the drain sections B 613a to 613c can be set substantially equal, and since a dead space in the MIS section 609 can be reduced, the device can be operated effectively. In addition, as a modification of the high voltage MOSFET in accordance with the third embodiment shown in Fig. 5, a high voltage MOSFET having a planar structure shown in Fig. 6 is conceivable. This high voltage MOSFET is arranged such that, in the high voltage MOSFET shown in Fig. 5, the drain sections B 613b formed in two rows are connected to each other on the lower side, and the drain sections B 613c are also formed in a similar manner. The radius of curvature of a connecting portion 616 connecting the drain sections B 613b and the radius of curvature of a connecting portion 617 connecting the drain sections B 613c are respectively set to be sufficiently large, so that the electric field does not concentrate at these portions, making it possible to maintain a targeted withstand voltage. Accordingly, with this high voltage MOSFET as well, it is possible to effect high integration and low on-resistance while maintaining a high withstand voltage. [Fourth Embodiment] Fig. 7 is plan view illustrating a configuration of a high voltage MOSFET in accordance with a fourth embodiment of the present invention. It should be noted that, in the high voltage MOSFET shown in Fig. 7, portions common to those of the high voltage MOSFET in accordance with the first embodiment shown in Fig. 1 are denoted by the same reference numerals, and description thereof will be omitted. The high voltage MOSFET in accordance with this embodiment is arranged such that, in the planar structure of the high voltage MOSFET in accordance with the third embodiment shown in Fig. 5, drain sections B 613d are further formed along sides of the drain sections B 613c, respectively, thereby juxtaposing the drain sections B in seven rows. Of these drain sections B 613a to 613d, the drain sections B 613b and the drain sections B 613d are connected at their lower ends. In the high voltage MOSFET having the above-described configuration, since the radius of curvature of a connecting portion 618 connecting the drain sections B 613b and the drain sections B 613d is set to be sufficiently large, so that the concentration of the electric field does not occur at this portion, and the withstand voltage does not deteriorate. Thus, in the high voltage MOSFET in accordance with this embodiment as well, since it is possible to reduce the inter-drain pitch and increase the degree of integration of the element without deteriorating the withstand voltage in the same way as the high voltage MOSFETs in accordance with the first to third embodiments described above, low on-resistance due to high integration is attained while maintaining a withstand voltage. Accordingly, even though its device size is small, it is possible to structure a high current-capacity, high voltage withstanding device, making it possible to provide a compact and high-performance power IC. The present invention is characterized in that the drain pad opening portion in the first parallel region is formed by being offset outwardly in the lengthwise direction of parallelism with respect to the drain pad opening portion in the second parallel region adjacent to the first parallel region, and that the width of a portion where the drain pad opening portion is not formed in the first parallel region is set to be smaller than the width of the drain pad opening portion. As a result, it becomes possible to reduce the distance between adjacent parallel regions while substantially securing a distance between drain pad opening portions in the adjacent first and second parallel regions, which is considered necessary for securing a targeted withstand voltage. In addition, since it is possible to secure the MIS section region provided between the parallel regions, the distance between which is reduced, it is possible to attain low on-resistance due to high integration without deteriorating the withstand voltage. Furthermore, in a case where the width of a portion where the drain pad opening portion is not formed in the second parallel region is set to be smaller than the width of the drain pad opening portion, it is possible to increase the channel width, so that the low on-resistance can be promoted further.

Claims: A high voltage MIS field effect transistor, comprising: a semiconductor substrate (601) of a first conductivity type; a semiconductor layer (602) of a second conductivity type formed on an obverse surface side of said semiconductor substrate (601); a base layer of the first conductivity type formed in said semiconductor layer (602); a source layer (605) of the second conductivity type formed in said base layer; a source electrode (607) abutting said source layer (605); a gate electrode (604) formed in such a manner as to extend from said source layer (605) to said semiconductor layer (602) via an insulating gate film; a drain section (610, 613) including a drain layer (606a, b) of the second conductivity type formed in said semiconductor layer (602); said drain section (610, 613) including a plurality of parallel regions and having its periphery surrounded by said gate electrode (604) and said source electrode (607); a first drain pad opening portion (614) in a first parallel region of said plurality of parallel regions; and a second drain pad opening portion (611) in a second parallel region of said plurality of parallel regions adjacent to said first parallel region; wherein said first drain pad portion (614) is offset outwardly in a lengthwise direction of said respective parallel regions with respect to said second drain pad opening portion (611), characterized in that a width of a portion of said first parallel region where said first drain pad opening portion (614) is not formed, is set to be smaller than a width of said first parallel region where said first drain pad opening portion (614) is formed. A high voltage MIS field effect transistor according to claim 1, wherein a width of a portion of said second parallel region where said second drain pad opening portion (611) is not formed is set to be smaller than a width of said second parallel region where said second drain pad opening portion is formed. A high voltage MIS field effect transistor according to claims 1 or 2, wherein a radius of curvature (R DR ) of one of said first and second drain pad opening portions (614, 611) has a withstand-voltage-securing length which makes it possible to secure a predetermined withstand voltage. A high voltage MIS field effect transistor according to one of the previous claims, wherein two or more of said plurality of parallel regions are connected. A high voltage MIS field effect transistor according to one of the previous claims, wherein said source electrode (607) is a field plate-type source electrode which extends from an end of said source layer (605) toward said drain layer (606a, b) A high voltage MIS field effect transistor according to one of the previous claims, further comprising a drain electrode (608) abutting said drain layer (606a, b), said drain electrode being a field plate-type drain electrode which extends from an end of said drain layer (606a, b) toward said source layer (605).

Inventors: FUJISHIMA NAOTO, KITAMURA AKIO, FUJISHIMA, NAOTO, KITAMURA, AKIO, Fujishima, Naoto, Fuji Electric Co., Ltd., Kitamura, Akio, Fuji Electric Co., Ltd.
Applicants: FUJI ELECTRIC CO LTD, FUJI ELECTRIC CO., LTD.
Application year: 1994
Main classification: H01L29
IPC codes: H01L29