THIN FILM TRANSISTOR AND DISPLAY USING THE TRANSISTOR

Abstract: To suppress the optical leak current I off sufficiently and thereby to attain a high ratio of ON/OFF currents, at least one of the shortest distances from an arbitrary intersection of the contour lines of the gate electrode (131) and the drain electrode (141) to the intersections of the contour lines of the gate electrode (131) and the source electrode (151) is longer than the shortest distance between the part of the contour lines of the gate electrode (131) which is superposed on the drain electrode (141) and the part which is superposed on the source electrode (151).

Description: Technical Field The present invention relates to a thin-film transistor (to be abbreviated as a TFT hereinafter) and a display device such as an active matrix type liquid crystal display device, using the same. Background Art TFTs are widely used as switching elements in drive circuits of various types of devices. For example, in an active matrix type liquid crystal display device, each display pixel is selected by a TFT. Generally, a TFT has a source electrode and a drain electrode formed to be separated from each other, a semiconductor film formed to electrically contact these electrodes, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film. TFTs of this type can be classified into a staggered type TFT in which a semiconductor film, a gate insulating film, and a gate electrode are sequentially formed on the source and drain electrodes, and an inverted staggered type TFT in which a gate insulating film, a semiconductor film, and source and drain electrodes are sequentially formed on a gate electrode. In recent years, an increase in ON/OFF current ratio is requested in order to render a TFT operable in a higher frequency range. For this purpose, the length of a channel corresponding to the semiconductor film portion between the source and drain electrodes is attempted to be decreased, thereby increasing the ON/OFF current ratio. When the semiconductor film of the TFT is made of a silicide semiconductor represented by amorphous silicon (a-Si:H), photocarriers are generated in the semiconductor film upon incidence of light. Although a decrease in channel length can increase an ON current Ion, it facilitates movement of the photocarriers, thereby undesirably increasing an OFF current, i.e., a photoleakage current Ioff. As a result, the ON/OFF current ratio is not improved as expected. Especially, in an active matrix type liquid crystal display device, generation of the photoleakage current Ioff directly causes variations in potential of the pixel electrodes, leading to a degradation in visual quality of the display image. Therefore, conventionally, countermeasures have been taken such as formation of a light-shielding layer made of a metal material, e.g., chromium (Cr), on a counter substrate which is arranged to oppose an array substrate on which a plurality of pixel electrodes are formed. However, this cannot prevent the photoleakage current Ioff which is caused by the photocarrier generated in the semiconductor layer of the TFT upon incidence of light reflected by the surface of the light-shielding layer. According to another countermeasure, for example, a light-shielding layer adjacent to the upper or lower portion of the TFT may be provided on the array substrate. However, this countermeasure cannot essentially decrease the photoleakage current Ioff sufficiently. Document JP-A-62 120076 discloses a thin film transistor having a gate electrode with an increased gate width at the end of a channel region in comparison to that at the center. With this structure the OFF current of the transistor is decreased. Document JP-A-2 042763 discloses a thin film transistor device comprising a common part for a drain electrode and a gate electrode, which is smaller than a common part for a source electrode and a gate electrode. Thus, it is possible to reduce a parasitic capacitance generated between the drain electrode and the gate electrode. Document JP-A-60 189265 discloses a thin film field effect semiconductor device having source, drain and gate electrodes as well as an insulation layer the form of which is chosen to completely shield irradiated light from the outside and to reduce inferiority of layer insulation. Document EP-A-0 574 186, which represents state of the art according to Art. 54(3) EPC, discloses a thin film transistor wherein an insulating layer is formed between a semiconductor layer forming a channel and the source and drain electrodes of the transistors. The insulating layer extends over a distance which is longer than a hole-electron recombination distance from all the edges of the source and drain electrodes overlapping the semiconductor layer. Thus, leak current caused by incident light on the semiconductor layer is prevented. The present invention has been made in view of the above situations, and has as its object to provide a TFT which can reduce the photoleakage current Ioff upon incidence of light. It is another object of the present invention to provide a display device which does not cause defective display due to the photoleakage current Ioff of the TFT. It is still another object of the present invention to provide a TFT in which the photoleakage current Ioff can be reduced and a parasitic capacitance Cgs generated in the gate-source path or parasitic capacitance Cgd generated in the gate-drain path of the TFT can be reduced. It is still another object of the present invention to provide a display device which can reduce a potential drop ΔVp in pixel electrode potential at an instance during which the TFT is changed from an ON state to an OFF state due to the parasitic capacitance Cgs of the TFT and also reduce the optical leakage current Ioff, so that display defect, e.g., flicker, will not be caused. Disclosure of Invention According to the present invention, there is provided a thin-film transistor comprising an insulating substrate, a light-shielding gate electrode positioned on said insulating substrate, a gate insulating film positioned on said gate electrode, a semiconductor film positioned above said gate electrode through said gate insulating film, a source electrode and a drain electrode, said source electrode and drain electrode electrically contacting said semiconductor film at respective electrical contacts, a channel being defined in said semiconductor film between said respective electrical contacts, said channel being positioned above said gate electrode, wherein the length of said channel is less than any width of said gate electrode which width is measured in the channel length direction, and wherein said gate electrode overlaps said source and drain electrodes and has wide parts in the form of source side and drain side extensions located at the sides of said channel in the channel width direction which is perpendicular to the channel length direction, and a short part between the wide parts, the source side and drain side extensions at portions thereof respectively overlapping the source and drain electrodes to reduce light that is applied to the sides of said channel without being shielded by said source and drain electrodes. According to the present invention there is also provided a first substrate having a scanning and signal lines, a pixel electrode and a semiconductor element which is connected to said scanning and signal lines to drive said pixel electrode, a second substrate positioned to oppose said first substrate, and an optical modulating layer positioned between said first and second substrates, wherein said semiconductor element is the thin film transistor defined in claim 1. The gate electrode of the present invention has a larger light-shielding effect than a conventional gate electrode, so that the photoleakage current Ioff of the TFT is reduced, thereby obtaining an excellent ON/OFF current ratio. According to this arrangement, the gate-source path parasitic capacitance Cgs or gate-drain path parasitic capacitance Cgd of the TFT is not effectively increased. Therefore, according to the active matrix type liquid crystal display device using this TFT, an excellent ON/OFF current ratio of the TFT can be obtained. As the integration density of the active matrix type liquid crystal display device is improved, the selection period of each pixel electrode is shortened. Even in such a display device, a video signal can be sufficiently written in the pixel electrode. Furthermore, since the gate-source path parasitic capacitance Cgs or gate-drain path parasitic capacitance Cgd of the TFT is not increased, variations in potential of the pixel electrode or an increase in time constant of wirings is not caused. Brief Description of Drawings FIG. 1 is a plan view schematically showing the structure of a part of an active matrix type liquid crystal display device according to the first embodiment of the present invention; FIG. 2 is a sectional view schematically showing a sectional structure taken along the line A - A' of FIG. 1; FIG. 3 is a sectional view schematically showing a sectional structure taken along the line B - B' of FIG. 1; FIG. 4 explains a TFT provided to the active matrix type liquid crystal display device shown in FIG. 1, in which FIG. 4(a) is a plan view schematically showing the structure of the TFT, and FIG. 4(b) is a plan view schematically showing the structure of the gate electrode of the TFT; FIG. 5 is a waveform chart of signals that drive the active matrix type liquid crystal display device shown in FIG. 1; FIG. 6 is a plan view schematically showing the structure of a modification of the active matrix type liquid crystal display device shown in FIG. 1; FIG. 7 is a plan view schematically showing the main part of another modification of the active matrix type liquid crystal display device shown in FIG. 1; FIG. 8 explains an active matrix type liquid crystal display device not claimed by the present invention, in which FIG. 8(a) is a plan view schematically showing the structure of a part of this active matrix type liquid crystal display device, and FIG. 8(b) is a sectional view schematically showing a sectional structure taken along the line A - A' of FIG. 8(a); FIG. 9 explains a TFT provided to the active matrix type liquid crystal display device shown in FIG. 8, in which FIG. 9(a) is a plan view schematically showing the structure of the TFT, FIG. 9(b) is a sectional view schematically showing a sectional structure taken along the line A - A' of FIG. 9(a), FIG. 9(c) is a sectional view schematically showing a sectional structure taken along the line B - B' of FIG. 9(a), FIG. 9(d) is a plan view schematically showing the structure of the gate electrode of the TFT, and FIG. 9(e) is a plan view schematically showing the structure of a channel protection film; FIG. 10 explains a photoleakage current Ioff, in which FIG. 10(a) is a plan view schematically showing the structure of a general TFT, and FIG. 10(b) is a sectional view schematically showing a sectional structure taken along the line A - A' of FIG. 10(a); FIG. 11 is a plan view showing a modification of the TFT shown in FIG. 8; FIG. 12 is a plan view schematically showing the structure of a part of an active matrix type liquid crystal display device; FIG. 13 explains a TFT shown in FIG. 12, in which FIG. 13(a) is a plan view schematically showing the structure of a scanning line, and FIG. 13(b) is a plan view schematically showing the structure of a channel protection film; and FIG. 14 includes views showing the manufacturing steps of the active matrix type liquid crystal display device shown in FIG. 12. Best Mode of Carrying Out the Invention A light-transmission active matrix type liquid crystal display device according to the first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a schematic planar structure concerning a part of an active matrix type liquid crystal display device 301, FIG. 2 shows a schematic sectional structure along the line A - A' of FIG. 1, and FIG. 3 shows a schematic sectional structure along the line B - B' of FIG. 1. The liquid crystal display device 301 shown in FIGS. 1 to 3 has an array substrate 101, a counter substrate 201, and a liquid crystal layer 311 made of a nematic liquid crystal compound. A matrix array of a plurality of pixel electrodes 181 and a plurality of TFTs 171 connected to these pixel electrodes are formed on a glass substrate 100, thereby forming the array substrate 101. A counter electrode 211 made of ITO (Indium Tin Oxide) is formed on a glass substrate 200, thereby forming the counter substrate 201. The array substrate 101 and the counter substrate 201 oppose each other at a gap of 5 microns such that alignment films 321 and 331 respectively formed on their surfaces are on the inner sides. The liquid crystal layer 311 is held between the array substrate 101 and the counter substrate 201. As shown in FIG. 1, the array substrate 101 has n scanning lines 111 (Yj: j = 1, 2,..., n) and m signal lines 121 (Xi: i = 1, 2,..., m) formed on the glass substrate 100 along the rows and columns and rows of the pixel electrodes 181, respectively. The TFTs 171 are arranged in the vicinities of the intersections of the scanning lines 111 and the signal lines 121. Gate electrodes 131 are formed integrally with the scanning lines 111. Drain electrodes 141 are formed integrally with the signal lines 121. Source electrodes 151 are formed in contact with the pixel electrodes 181. The array substrate 101 has storage capacitor stor age lines 191 made of the same material as that of the scanning lines 111 and arranged to be substantially parallel with the scanning lines 111. The storage capacitor lines 191 are formed on the pixel electrodes 181 through a multilayered gate insulating film 133 shown in FIG. 2 which is formed by stacking a silicon oxide (SiO 2 ) film and a silicon nitride (SiN x ) film. Thus, storage capacitors Cs are formed between the storage capacitor lines 191 and the pixel electrodes 181. As shown in FIGS. 2 and 3, the counter substrate 201 has a grid-like light-shielding layer 211 formed on the glass substrate 200. The counter electrode 231 is formed on the light-shielding layer 221 through an insulating film 221. The light-shielding layer 211 is made of chromium (Cr) and shields light leaking from portions around the plurality of pixel electrodes 181 formed on the array substrate 201 side, i.e., from regions where the TFTs 171, the signal lines 121, and the scanning lines 111 are formed. The surface of the light-shielding layer 211 may be oxidized to decrease light reflection. The light-shielding layer 211 may be made of, e.g., a black resin that provides a sufficient light-shielding effect. A color filter layer may be provided between the light-shielding layer 211 and the counter electrode 231 to realize color display. The active matrix type liquid crystal display device 301 further has polarizing plates 351 and 341 formed on the surfaces of the glass substrates 100 and 200 on sides opposite to the liquid crystal layer 311. The orientations of the polarizing plates 351 and 341 are set such that their axes of polarization are perpendicular to each other. Referring to FIGS. 2 and 3, in the conventional active matrix type liquid crystal display device, although most of oblique light incident on the counter substrate 201 and directed to the TFT 171 is shielded by the light-shielding layer 211, oblique light incident on the array substrate 101, reflected by the light-shielding layer 211, and directed to the TFT 171 cannot be shielded. In this embodiment, however, the active matrix type liquid crystal display device 301 is designed to sufficiently reduce oblique light reflected by the light-shielding layer 211 and directed to the TFT 171. Therefore, the photoleakage current Ioff of the TFT 171 can be suppressed, thereby achieving a high ON/OFF current ratio. More specifically, each TFT 171 has a gate electrode 131 formed to have a shape as shown in FIG. 4(b). The gate electrode 131 is made of an Mo-Ta alloy and includes a gate region Gs having a gate width Lg1 of 14 microns. Other than the Mo-Ta alloy, e.g., an Mo-W alloy, an Mo-Ta alloy, or a multilayered film of the Mo-W alloy and aluminum (Al) can be used as the material of the gate electrode 131. As shown in FIG. 2, the TFT 171 further has a multilayered gate insulating film 133, a semiconductor film 135, a drain electrode 141, and a source electrode 151. The multilayered gate insulating film 133 is constituted by a silicon oxide (SiO 2 ) film formed on the gate electrode 131 to a thickness of 3,500Å (10Å = 1nm) and a silicon nitride (SiN x ) film formed on the silicon oxide (SiO 2 ) film to a thickness of 500Å. The semiconductor film 135 is constituted by an amorphous silicon (a-Si:H) film formed on part of the gate insulating film 133 to a thickness of 3,000Å. The drain electrode 141 and the source electrode 151 have a multilayered structure of molybdenum (Mo) and aluminum (Al) and are formed to be apart from each other. The drain electrode 141 and the source electrode 151 are formed on the semiconductor film 135 respectively through low-resistance semiconductor thin films 137 to be electrically connected to the semiconductor film 135. Each low-resistance semiconductor thin film 137 is constituted by an n + -type amorphous silicon (n + a-Si:H) film having a thickness of 500Å, and used to obtain good ohmic contact between the drain and source electrodes 141 and 151 and the semiconductor film 135. A channel length Lc of the TFT 171 is determined by the gap between the drain electrode 141 and the source electrode 151, as shown in FIG. 4(a), and is set to 4 microns in this embodiment. A channel width Wc of the TFT 171 is set to 23 microns. In this embodiment, the shortest distance between an arbitrary intersection of the outline of the gate electrode 131 and the outline of the drain electrode 141 and an intersection of the outline of the gate electrode 131 and the outline of the source electrode 151, i.e., distances between points b - b' and c - c' in FIGS. 4(a) and 4(b) are set larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and a portion of the same overlapping the source electrode 151, i.e., than a distance between points a - a'. As shown in FIGS. 4(a) and 4(b), this setting can be achieved when the gate electrode 131 has a gate region Gs having a gate width Lg1 larger than the channel length Lc, a drain-side extension region GDs extending from the gate region Gs in a direction of the gate width Lg1 for an extending length α1 of 6 microns and overlapping the drain electrode 141, and a source-side extension region GSs extending from the gate region Gs in the direction of the gate width Lg1 for an extending length α2 of 6 microns and overlapping the source electrode 151; and the source-side extension region GSs and the drain-side extension region GDs have, at portions thereof respectively overlapping the source electrode 151 and the drain electrode 141, gate electrode notched portions GSℓ and GDℓ smaller than the overlapping portions. Hence, only an effective gate width Lg2 of the gate electrode 131 is extended for the extending lengths α1 and α2 of the drain-side extension region GDs and the source-side extension region GSs without changing the channel length Lc. In this embodiment, as shown in FIG. 3, the drain-side extension region GDs and the source-side extension region GSs shield undesired oblique light reflected by the surface of the light-shielding layer 211 and directed to the semiconductor film 135. As a result, the TFT 171 of this embodiment can shield undesired oblique light more than the conventional TFT having no drain- and source-side extension regions GDs and GSs does by an increase of 80%. In this embodiment, since the drain- and source-side extension regions GDs and GSs are parts of the gate electrode 131, they can be formed in the steps of forming the gate electrode 131. If a light-shielding film is to be formed under or above the TFT 171 through an insulating film to obtain a light-shielding function similar to that of the regions GDs and GSs, the location of the light-shielding film is displaced from the TFT 171 within a predetermined allowance because such a light-shielding film is formed in accordance with forming steps independently of the steps of forming the gate electrode 131. If the size of the light-shielding film is set larger by a margin for absorbing the displacement, it decreases the degree of opening of the display device. In this embodiment, however, since the positional displacement of the light-shielding film need not be considered, a high degree of opening of the display device can be obtained. Furthermore, in this embodiment, since an undesired influence to the capacitance or potential can be neglected, unlike in a case wherein the above-mentioned insulating film is formed under or above the TFT 171 through the insulating film, no trouble occurs in the display operation. As is understood from FIGS. 2 and 3, when the effective gate width Lg2 including the respective extension regions GDs and GSs is increased more, undesired oblique light can be shielded. However, since this lowers the degree of opening of the display device 301, an increase in effective gate width Lg2 including the respective extension regions GDs and GSs is limited. According to the experiment conducted by the present inventors, it has become obvious that an effect of shielding undesired oblique light can be obtained if the effective gate width Lg2 is 20 microns or more, and preferably, 26 microns or more. For this reason, in this embodiment, the effective gate width Lg2 is set to 26 microns considering the degree of opening. Assuming the distance between the surface of the glass substrate 100 on which the gate electrode 131 is formed and the surface of the light-shielding layer 211 is defined as d microns, the effective gate width Lg2 including the extension regions GSs and GDs may be formed to 3d or more, and preferably, 4d or more. When, e.g., the light-shielding layer 211 is formed on the array substrate 201 side, a layer of the counter substrate 201 side which has the highest light reflectance may be used as the reference. A more characteristic feature is that both the source- and drain-side extension regions GSs and GDs of the gate electrode 131 have, at portions thereof respectively overlapping the source and drain electrodes 151 and 141, the gate electrode notched portions GSℓ and GDℓ smaller than the overlapping portions. As a result, even when the effective gate width Lg2 including the respective extension regions GSs and GDs is increased, an increase in gate-source path parasitic capacitance Cgs inevitably formed in the TFT 171 is prevented, thereby suppressing variations in potential of the pixel electrode 181. FIG. 5 shows the waveforms of signals that derive this active matrix type liquid crystal display device 301. Gate pulses (VYj: j = 1, 2,..., n) are sequentially supplied to the scanning lines 111 (Yj), and a TFT 171 connected to a scanning line 111 (Yj) to which a gate pulse (VYj) is input is set ON for a predetermined period of time. Video signals (VXi: i = 1, 2,..., m) are supplied to the signal lines 121 (Xi). Thus, a TFT 171 connected to a scanning line 111 (Yj) and a signal line 121 (Xi) is turned on, and a video signal (VXi) is written in a pixel electrode 181 (Xi,Yj) during the ON period of this TFT 171. The potential V(Xi,Yj) of the pixel electrode 181 (Xi,Yj) is held for, e.g., 1 field period (1 F). As is apparent from FIG. 5, when the TFTs 171 have n channels, as the gate pulse (VYj) falls, each pixel electrode potential V(Xi,Yj) is decreased to the negative side by ΔVp. The potential drop ΔVp largely depends on the gate-source path parasitic capacitance Cgs between the scanning line 111 (Yj), the gate electrode 131, the pixel electrode 181, and the source electrode 141, as indicated by the following equation (Clc: liquid crystal capacitance, Cs: storage capacitor): ΔVp = ΔVXi × Cgs/(Clc + Cs + Cgs) According to this embodiment, however, since the gate-source path parasitic capacitance Cgs between the gate electrode 131 and the source electrode 151 does not substantially change when compared to the conventional case, flicker does not occur due to the potential drop ΔVp. As described above, according to the active matrix type liquid crystal display device 301 of this embodiment, since the effective gate width Lg2 of the gate electrode 131 that functions as an incidence blocking layer against oblique light is increased without changing the channel length Lc of the TFT 171, the photoleakage current Ioff can be greatly decreased while maintaining a high ON current Ion in the same manner as in the conventional case, so that a high ON/OFF current ratio can be achieved. According to this embodiment, when compared to a conventional TFT not having source- and drain-side extension regions GSs and GDs of the gate electrode 131 and having similar channel length Lc and channel width Wc, the ON/OFF current ratio of the TFT 171 can be increased to about twice. According to this embodiment, in spite that the effective gate width Lg2 of the gate electrode 131 is increased, since the gate-source path parasitic capacitance Cgs of the TFT 171 is suppressed, the voltage drop ΔVp of the pixel electrode 181 is not increased. Also, since the effective gate width Lg2 is increased, the time constants of the scanning lines 111 (Yj) and the gate electrodes 131 can be made smaller than those of the conventional case. In a large active matrix type liquid crystal display device having a large wiring length, this solves a decrease in effective gate pulse width caused by a delay in gate pulse (VYj) and enables the write operation of the video signal (VXi) for a longer period of time. In the active matrix type liquid crystal display device 301 of this embodiment, in order to set the channels of the TFTs 171 and the scanning lines 111 (Yj) to be parallel to each other, all the gate electrodes 131 are constituted by portions extending from the trunks of the scanning lines 111 (Yj). However, this arrangement of the TFTs 171 can be changed such that the channels of the TFTs 171 and the scanning lines 111 (Yj) are perpendicular to each other, as shown in FIG. 6. In this case, a gate region Gs of each gate electrode 131 is constituted by the trunk of a corresponding scanning line 111 (Yj), and a source-side extension region GSs and a drain-side extension region GDs are constituted by portions extending from the trunk of this scanning line 111 (Yj). In FIG. 6, portions similar to those in the above embodiment are denoted by the same reference numerals. The structure shown in FIG. 6 can increase the degree of opening of the display device 301 by 5 points as compared to the embodiment having the above structure if a pixel pitch is set to, e.g., 250 × 90 µm 2 . In this specification, a "point" is used as a difference in the degree of opening (%). In the above embodiment, each pixel electrode 181 is connected to one corresponding TFT 171. For example, however, as shown in FIG. 7, each pixel electrode 181 may be connected to two TFTs 171a and 171b that are formed to be electrically parallel to each other. In the structure shown in FIG. 7, a difference in channel length Lc, which is formed between the TFTs 171a and 171b when, e.g., the pattern of source electrodes 151a and 151b and a drain electrode 141 is displaced in the direction of a scanning line 111, can be canceled. As a result, the variations in manufacturing conditions can be compensated for. An active matrix type liquid crystal display device 601 not claimed by the present invention will be described with reference to the accompanying drawings. FIG. 8(a) shows a schematic planar structure concerning part of this active matrix type liquid crystal display device 601, and FIG. 8(b) shows a schematic sectional structure along the line A - A' of FIG. 8(a). FIG. 9(a) shows the planar structure of a TFT 471 shown in FIGS. 8(a) and 8(b), FIG. 9(b) shows the sectional structure of the TFT 471 along the line A - A' of FIG. 9(a), FIG. 9(c) shows the sectional structure of the TFT 471 along the line B - B' of FIG. 9(a), FIG. 9(d) shows the detailed planar structure of a gate electrode 431 shown in FIGS. 9(a) to 9(c), and FIG. 9(e) shows the detailed planar structure of a channel protection film 439 shown in FIGS. 9(a) to 9(c). The liquid crystal display device 601 shown in FIGS. 8(a) and 8(b) has an array substrate 401, a counter substrate 501, and a liquid crystal layer 611. A matrix array of a plurality of pixel electrodes 481 and a plurality of TFTs 471 connected to these pixel electrodes 481 are formed on a glass substrate 400, thereby forming the array substrate 401. A counter electrode 531 made of ITO (Indium Tin Oxide) is formed on a glass substrate 500, thereby forming the counter substrate 501. The liquid crystal layer 611 is made of a nematic liquid crystal compound. The array substrate 401 and the counter substrate 501 oppose each other at a gap of 5 microns such that alignment films 631 and 621 respectively formed on their surfaces are on their inner sides. The liquid crystal layer 611 is held between the array substrate 401 and the counter substrate 501. The array substrate 401 has n scanning lines 411 (Yj: j = 1, 2,..., n) and m signal lines 421 (Xi: i = 1, 2,..., m) formed on the glass substrate 400 along the rows and columns of the pixel electrodes 481, respectively. The TFTs 471 are arranged in the vicinities of the intersections of the scanning lines 411 and the signal lines 421, and have a channel length Lc of 12 microns and a channel width Wc of 23 microns. Gate electrodes 431 are formed integrally with the scanning lines 411. Drain electrodes 441 are formed integrally with the signal lines 421. Source electrodes 451 are formed in contact with the pixel electrodes 481. The TFT 471 will be described in detail. The gate electrode 431 is made of an Mo-Ta alloy, and, as shown in FIG. 9(d), has a gate region Gs having a gate width Lg1 of 14 microns larger than the channel length Lc, a drain-side extension region GDs extending from the gate region Gs in a direction substantially parallel to the gate width Lg1 for an extending length α1 of 6 microns and overlapping the drain electrode 441, and a source-side extension region GSs extending from the gate region Gs in a direction substantially parallel to the gate width Lg1 for an extending length α2 of 6 microns and overlapping the source electrode 451. The TFT 471 further has a multilayered gate insulating film 433, a semiconductor film 435, a channel protection film 439, the drain electrode 441, and the source electrode 451. The multilayered gate insulating film 433 is constituted by a silicon oxide (SiO 2 ) film formed on the gate electrode 431 shown in FIGS. 9(b) and 9(c) to a thickness of 3,500Å and a silicon nitride (SiN x ) film formed on the silicon oxide (SiO 2 ) film to a thickness of 500Å. The semiconductor film 435 is constituted by an amorphous silicon (a-Si:H) film formed on the gate insulating film 433 to a thickness of 300Å. The channel protection film 439 is constituted by a silicon nitride (SiN x ) film formed on the semiconductor film 435 to a thickness of 2,000Å and determines the channel length Lc of the TFT 471. The drain electrode 441 and the source electrode 451 have a multilayered structure of molybdenum (Mo) and aluminum (Al) and are formed to be apart from each other. The drain electrode 441 and the source electrode 451 are formed on the channel protection film 439 and the semiconductor film 435 through low-resistance semiconductor thin films 437 to be electrically connected to the semiconductor film 435. Each low-resistance semiconductor thin film 437 is constituted by an n + -type amorphous silicon (n + a-Si:H) film having a thickness of 500Å, and used to obtain good ohmic contact between the drain and source electrodes 441 and a 451 and the semiconductor film 435. Although not shown, the array substrate 401 has storage capacitor lines made of the same material as that of the scanning lines 411. These storage capacitor lines are formed on the pixel electrodes 481 through the multilayered gate insulating film 433 obtained by stacking the silicon oxide (SiO 2 ) film and the silicon nitride (SiN x ) film, so that an storage capacitor Cs is formed between the storage capacitor line and the pixel electrode 481. The counter substrate 501 has a grid-like light-shielding layer 511 formed on the glass substrate 500 shown in FIG. 8(b). The counter electrode 531 is formed on the light-shielding layer 511 through an insulating film 521. The light-shielding layer 511 is made of chromium (Cr) and shields light leaking from portions around the plurality of pixel electrodes 481 formed on the array substrate 401 side, i.e., from regions where the TFTs 471, signal lines 121, and the scanning lines 411 are formed. The active matrix type liquid crystal display device 601 further has polarizing plates 651 and 641 formed on the surfaces of the glass substrates 400 and 500 on sides opposite to the liquid crystal layer 611. The orientations of the polarizing plates 651 and 641 are set such that their axes of polarization are perpendicular to each other. As shown in FIGS. 9(a) and 9(d), in the gate electrode 431 of the TFT 471, the gate region Gs has the gate width Lg1 larger than the channel length Lc. The drain-side extension region GDs extends from the gate region Gs in a direction substantially parallel to the gate width Lg1 for an extending length α1 of 6 microns, and overlaps the drain electrode 441. The source-side extension region GSs extends from the gate region Gs in the direction substantially parallel to the gate width Lg1 for an extending length α2 of 6 microns, and overlaps the source electrode 451. As shown in FIGS. 9(a) and 9(e), the channel protection film 439 is formed such that a region thereof stacked on the semiconductor film 435 is smaller than the outline of the gate electrode 431. Furthermore, the shortest distance between an arbitrary intersection of the outline of the channel protection film 439 and the outline of the drain electrode 441 and an intersection of the outline of the channel protection film 439 and the outline of the source electrode 451, i.e., distances between points b - b' and c - c' are set larger than the shortest distance between a portion of the outline of the channel protection film 439 overlapping the drain electrode 451 and a portion of the same overlapping the source electrode 441, i.e., than a distance between points a - a'. This setting can be achieved when the channel protection film 439 has a channel length determination region Is determining the channel length Lc of the TFT 471, at least a drain-side extension region IDs extending from the channel length determination region Is in a direction substantially parallel to the channel length for an extending length β1 and overlapping the drain electrode 441, and a source-side extension region extending from the channel length determination region Is in the direction substantially parallel to the channel length for an extending length β2 and partly overlapping the source electrode 451; and the extension regions IDs and ISs have channel protection film notched portions IDℓ and ISℓ respectively smaller than the drain electrode 441 and the source electrode 451. Hence, only an effective gate width Lg2 of the gate electrode 431 is extended for the extending lengths α1 and α2 of the extension regions GDs and GSs without changing the channel length Lc, and is set to 26 microns, in the same manner as in the first embodiment. In the TFT 471, the source electrode 451, the drain electrode 441, and the drain-and source-side extension regions GDs and GSs of the gate electrode 431 shield back light or oblique light incident under illumination of external light and directed to the semiconductor film 435. Thus, the TFT 471 can shield undesired oblique light more than the conventional TFT having no drain-and source-side extension regions GDs and GSs does by an increase of 80%, in the same manner as in the first embodiment. Since a portion of the channel protection film 439 multilayered on the semiconductor film 435 is formed smaller than the outline of the gate electrode 431, the photoleakage current Ioff is not increased by excitation of a photocarrier upon light irradiation to the semiconductor film 435. TFT 471 can suppress the photoleakage current Ioff to be much lower than that in the conventional case and can achieve an excellent ON/OFF current ratio based on the following reason obtained as the result of the extensive studies. The factor that causes the photoleakage current Ioff in the TFT will be explained. FIG. 10(a) shows the schematic planar structure of a general TFT 471', and FIG. 10(b) shows the schematic sectional structure of the TFT 471' taken along the line A - A' of FIG. 10(a). In FIG. 10(a), a channel region is indicated by a hatched (/) portion, and a side-channel region is indicated by a hatched (\) portion. In the TFT 471', a photoleakage current Ioff flows through a path Psc having a length equal to a side-channel length Lsc and existing in the side-channel region rather than through a path Pc having a length equal to a channel length Lc and existing in the channel region. More specifically, the amount of light incident on the side-channel region is larger than the amount of light incident on the channel region shielded by a gate electrode 431', a source electrode 451', or a drain electrode 441'. This causes a larger photoleakage current Ioff to flow in the side-channel region than in the channel region. Generally, an electric field having a higher intensity than in the channel region is generated in this side-channel region, depending on the shapes of the source electrode 451' and the drain electrode 441'. This causes an increase in photoleakage current Ioff. The TFT 471' has a structure in which the source electrode 451' and the drain electrode 441' are formed on a semiconductor film 435' and a channel protection film 439'. As shown in FIG. 10(b), the source electrode 451' and the drain electrode 441' overlap the channel region only with predetermined overlapping lengths Os and Od along the direction of the channel length Lc. Even if a carrier is generated in the channel region, almost all the carrier disappears in the region shielded by the source electrode 451' and the drain electrode 441', and they do not flow as the photoleakage current Ioff. In contrast to this, since the side-channel region does not overlap the source electrode 451' and the drain electrode 441', the carrier generated in the side-channel region flows as the photoleakage current Ioff. In the TFT 471' described above, the photoleakage current Ioff tends to be influenced more by the side-channel region than by the channel region. In contrast to this, in the TFT 471 of Fig. 9, the length of the path Psc of the photoleakage current Ioff (i.e., the side-channel length Lsc of the side-channel region shown in FIG. 9(b)) is set larger than the length of the path Pc of the optical leakage current Ioff (i.e., the channel length Lc of the channel region shown in FIG. 9(c)) by the sum of the extending lengths β1 and β2 of the channel protection film 439. Thus, the photoleakage current Ioff is reduced as a whole. Furthermore, the TFT 471 has a structure in which the source electrode 451 and the drain electrode 441 are formed on the semiconductor film 435 and the channel protection film 439. As shown in FIG. 9(c), the source electrode 451 and the drain electrode 441 overlap the channel region only with overlapping lengths Os and Od of 3 microns, respectively, along the direction of the channel length Lc. Thus, even if a carrier is generated in the channel region, it is prevented from flowing as a photoleakage current Ioff. In order to completely block the photoleakage current Ioff flowing through the path Pc in the channel region, either the overlapping length Od or Os must be set to be larger than 3 microns by considering the carrier mobility and the like. However, an effect of decreasing the photoleakage current Ioff can be obtained if the overlapping lengths Od and Os satisfy 1 micron ≤ Od, Os < 3 microns. According to the TFT 471, incidence of undesired oblique light on the semiconductor film 435 is effectively blocked, and the photoleakage current Ioff can be basically reduced by a specific structure that makes it difficult to generate the carrier by excitation with incident light. When this TFT 471 is used in the active matrix type liquid crystal display device 601, the ON/OFF current ratio is increased by 330% when compared to a case wherein the conventional TFT having similar channel length Lc and channel width Wc is used. As a result, with the active matrix type liquid crystal display device 601, a uniform display image is obtained throughout the entire display screen. The TFT 471 may be constituted such that the drain- and source-side extension regions GDs and GSs of the gate electrode 431 respectively have notched portions GDℓ and GSℓ, as shown in FIG. 11. This arrangement decreases the gate-source path parasitic capacitance Cgs of the TFT 471. Thus, the potential drop of the pixel electrode 481 which occurs immediately after the TFT 471 is turned off from the ON state can be prevented. Also, the time constants of the gate electrode 431 and the signal line 421 can be decreased. This is effective especially in a large liquid crystal display device having a large wiring length. When the channel protection film 439 is patterned by rear-surface exposure using the gate electrode 431 as the mask, the outline of the gate electrode 431 and the outline of the channel protection film 439 can be set at substantially the same positions, as shown in FIG. 11. This causes a further decrease in gate-source path parasitic capacitance Cgs and gate-drain path parasitic capacitance Cgd of the TFT 471, and solves mask misalignment (non-uniform shot) which occurs in an exposure process which is performed for each array substrate when a plurality of array substrates are to be formed from a large-sized glass substrate. Furthermore, in this embodiment, the channel protection film 439 is arranged between the low-resistance semiconductor thin films 437 and the semiconductor film 435 and made by a material different from that of the low-resistance semiconductor thin film 437. When etching is performed to pattern the low-resistance semiconductor thin films 437, this etching can be ended before the semiconductor film 435 is partially removed by utilizing a difference in etching rate between the channel protection film 439 and the low-resistance semiconductor thin films 437. Accordingly, the semiconductor film 435 need not to be formed thick considering the amount removed by etching, and the thickness of the semiconductor film 435 is set to a very small value of 300A. Since the semiconductor film 435 is made thin in this manner, the photoleakage current Ioff can be further decreased. The thinner the semiconductor film 435, the more the photoleakage current Ioff can be decreased. However, if it is considered to obtain a sufficient ON current Ion and to suppress variations in film thickness and film characteristics, the thickness of the semiconductor film 435 must fall within a range of 100Å to 500Å, and preferably a range of 100Å to 300Å. An active matrix type liquid crystal display device 1101 according to another embodiment of the present invention will be described with reference to FIGS. 12 and 13. This liquid crystal display device 1101 has a basic structure which is similar to those of the embodiments described above, and thus most of its repetitive explanation will be omitted. The liquid crystal display device 1101 has an array substrate 901 obtained by forming, on a glass substrate 900, a matrix of a plurality of pixel electrodes 981 and a plurality of TFTs 971 respectively connected to the pixel electrodes 981. The array substrate 901 has scanning lines 911 and signal lines 921 formed along the rows and columns of the plurality of pixel electrodes 981 on the glass substrate 900. The TFTs 971 are arranged in the vicinities of the intersections of the scanning lines 911 and the signal lines 921. In each TFT 971, the gate electrode is constituted by the trunk of the corresponding scanning line 911, a drain electrode 941 is formed integrally with the corresponding signal line 921, and a source electrode 951 is formed in contact with the corresponding pixel electrode 981. Although not shown, the liquid crystal display device 1101 further has a counter substrate and a liquid crystal layer. A counter electrode made of ITO (Indium Tin Oxide) is formed on a glass substrate, thereby forming the counter substrate. The liquid crystal layer is made of a nematic liquid crystal compound. The array substrate 901 and the counter substrate oppose each other such that alignment films respectively formed on their surface are on their inner sides. The liquid crystal layer is held between the array substrate 401 and the counter substrate. The counter substrate has a grid-like light-shielding layer 1011 formed on the glass substrate. The counter electrode is formed on the light-shielding layer 1011 through an insulating film. The light-shielding layer 1011 is made of chromium (Cr) and shields light leaking from portions around the plurality of pixel electrodes 981 formed on the array substrate 901 side, i.e., from regions where the TFTs 971, the signal lines 921, and the scanning lines 911 are formed. The active matrix type liquid crystal display device 1101 further has polarizing plates formed on the surfaces of the respective glass substrates on sides opposite to the liquid crystal layer. Each scanning line 911 is constituted by a multilayered structure of molybdenum (Mo) and aluminum (Al). As shown in FIGS. 12 and 13(a), a gate region Gs of the scanning line 911 that serves as the gate electrode is formed to have a gate width Lg1 of 14 microns. Each scanning line 911 has a drain-side extension region GDs extending from the gate region Gs toward the drain electrode 941 in the direction of the channel length Lc for an extending length α1 of 6 microns and overlapping the drain electrode 941. The drain-side extension region GDs has, at its region overlapping the drain electrode 941, a gate electrode notched portion GDℓ smaller than the drain electrode 941. The extending length α1 of the drain-side extension region GDs is set to 6 microns so that the scanning line width Lg2 in the vicinity of a region serving as the gate electrode of the TFT 971 is 20 microns. This is due to the following reason. In the same manner as in the embodiments described above, if the scanning line width Lg2 in the vicinity of the region serving as the gate electrode is 20 microns or more, undesired oblique light can be shielded, and a high degree of opening can be set. Apparently, also in this embodiment, the scanning line width Lg2 in the vicinity of the region serving as the gate electrode may be set to 26 microns, in the same manner as in the embodiments described above. Assume that it is considered to further shut off the undesired oblique light. On the surface of the counter substrate of the active matrix type liquid crystal display device 901 of this embodiment, since light is reflected mainly by the surface of the light-shielding layer 1011, if the distance between the surface of the light-shielding layer 1011 and the surface of the glass substrate 900 on which the scanning lines 911 are formed is defined as d microns, the scanning line width Lg2 of may be set to 3d microns or more, and preferably, 4d microns or more. When the light-shielding layer 1011 is formed on the array substrate 901 side, a layer on the counter substrate side which has the largest light reflectance may be used as the reference. A gate insulating film 933 (refer to FIG. 14) is constituted by a silicon oxide (SiO 2 ) film formed on the gate region Gs and the source-side extension region GDs to a thickness of 3,500Å and a silicon nitride (SiN x ) film formed on the silicon oxide (SiO 2 ) film to a thickness of 500Å. A semiconductor film 935 is constituted by an amorphous silicon (a-Si:H) film formed on the gate insulating film 933 to a thickness of 300Å. A channel protection film 939 is constituted by a silicon nitride (SiN x ) film formed on the semiconductor film 935 to a thickness of 2,000Å. The channel protection film 939 determines the channel length Lc of the TFT 971. As shown in FIGS. 12 and 13(b), the channel protection film 939 is arranged on the semiconductor film 935 such that the channel length Lc is 12 microns. In a region stacked on the semiconductor film 935, the channel protection film 939 has a shape conforming to the outline of the gate region Gs. More specifically, the channel protection film 939 has a channel length determination region Is determining the channel length Lc of the TFT 971, and a drain-side extension region IDs extending from the channel length determination region Is in a direction substantially parallel to the channel length Lc for an extending length (β1: β1 is substantially equal to α1) and partly overlapping the drain electrode 941. The drain-side extension region IDs has, in its region overlapping the drain electrode 941, a notched portion IDℓ smaller than the drain electrode 941. The drain electrode 941, integrally formed with the signal line 921 electrically connected to the semiconductor film 935, and the source electrode 951, electrically connected to the pixel electrode 981, are apart from each other. Low-resistance semiconductor thin films 937 (refer to FIG. 14) are provided between the semiconductor film 935 and the drain electrode 941, and between the semiconductor film 935 and the source electrode 951 to achieve good ohmic contact. Each low-resistance semiconductor thin film 937 is constituted by an n + -type amorphous silicon (n + a-Si:H) film formed to a thickness of 500Å. As described above, in the TFT 971 of this embodiment, since the effective gate width Lg2 is equal to the sum of the gate width Lg1 of the gate region Gs and the extending length α1, undesired oblique light incident on the TFT 971 can be decreased more than in a TFT having no drain-side extension region IDs by an increase of 60%. Due to the specific structure of the channel protection film 939, the side-channel length Lsc of the TFT 971 is set to be larger than the channel length Lc of the TFT 971 by the extending length β1 of the drain-side extension region IDs of the channel protection film 939. Thus, the path Psc in the side-channel region that largely influences the optical leakage current Ioff can be set large. Furthermore, since the source electrode 951 and the drain electrode 941 are formed on the channel protection film 939 to have an overlapping length of 3 µm, even if carriers are generated in the channel region, they do not form a photoleakage current Ioff. From the above reason, in the active matrix type liquid crystal display device 901 of this embodiment, when compared to an active matrix type liquid crystal display device using a TFT in which the scanning line 911 does not have a drain-side extension region GDs or notched portion GDℓ and the channel protection film 939 does not have a drain-side extension region IDs or notched portion IDℓ, the photoleakage current Ioff of the TFT 971 can be sufficiently decreased. Furthermore, in this liquid crystal display device 901, the ON/OFF current ratio of the TFT 971 can be increased by 150% due to its specific structure as well. Since the notched portion GDℓ is formed in the drain-side extension region GDs of the scanning line 911, the time constant of the scanning line 911 is decreased. This prevents distortion in waveform of the gate pulse and enables to sufficiently prolong the ON period of the TFT 971. Accordingly, a higher-quality display image can be obtained. Furthermore, in this embodiment, as shown in FIG. 12, the source electrode 951 is formed such that its electrode width Sw is substantially equal to widths Gℓw and Iℓw of the notched portion GDs of the scanning lines 911 and the notched portion IDs of the channel protection film 939, respectively, in a direction substantially perpendicular to the channel length Lc, and the drain electrode 941 is formed to have an electrode width Dw larger than the electrode width Sw of the source electrode 951. Even when notched portions GDs and IDs are formed in the scanning line 911 and the channel protection film 939, respectively, the ON current Ion is not decreased. A method of manufacturing the active matrix type liquid crystal display device 1101 according to the third embodiment will be described with reference to FIG. 14. First, as shown in FIG. 14(a), an Mo-Ta alloy is formed on a glass substrate 900 by deposition to a thickness of 3,000Å and patterned, thereby forming a plurality of scanning lines 911. Although not shown, simultaneously with formation of the scanning lines 911, storage capacitor lines are formed to be arranged substantially parallel to the scanning lines 911. Each scanning line 911 is formed to have a wiring width of 14 microns, and its gate region Gs is patterned to have a 6-micron drain-side extension region GDs having a notched portion GDℓ, as shown in FIG. 13(a). A silicon oxide (SiO 2 ) film and a silicon nitride (SiN x ) film are formed by deposition on the scanning line 911 to a thickness of 3,000Å and 500Å, respectively, to form a gate insulating film 933. Then, an amorphous silicon (A-Si:H) film 934 having a thickness of 300Å and a silicon nitride (SiN x ) film 938 having a thickness of 2,000Å are continuously formed in accordance with CVD. Thereafter, a resist is coated on the silicon nitride (SiN x ) film 938. The obtained structure is exposed from the rear surface by using the scanning line 911 as the mask and patterned. As a result, a channel protection film 939 self-aligned with the scanning line 911 and having a drain-side extension region IDs and a notched portion IDℓ is obtained, as shown in FIGS. 14(b) and 13(a). As shown in FIG. 14(c), an n + a-Si:H film 936 having a thickness of 500Å is formed on the channel protection film 939 by deposition in accordance with CVD. Then, as shown in FIG. 14(d), the amorphous silicon film 934 and n + a-Si:H film 936 excluding regions under a signal line 921 and the channel protection film 939 are removed to form a semiconductor film 935 and an island of the n + a-Si:H film 936. An ITO film is formed on the obtained structure by deposition and patterned to have a predetermined shape, thereby forming a pixel electrode 981. As shown in FIG. 14(e), molybdenum (Mo) and aluminum (Al) are formed by deposition to a thickness of 500Å and 3,000Å, respectively, thereby forming a multilayered film 961 as a prospective region of the signal line 921 (see to FIG. 12), a source electrode 951, and a drain electrode 941. As shown in FIG. 14(f), the island of the n + a-Si:H film 936 and the multilayered film 961 are patterned to form low-resistance semiconductor thin films 937, the source electrode 951, the drain electrode 941, and the signal line 921 (see to FIG. 12) integral with the drain electrode 941. Thereafter, a protection film and alignment films (not shown) are sequentially formed in accordance with a normal method, thereby obtaining an array substrate. The counter substrate and the array substrate are set to oppose each other through a spacer such that the distance between the glass substrates is 5.1 microns. The portion around the two opposing substrates is sealed with a sealing agent excluding a liquid crystal injection hole. Then, a liquid crystal composition is injected into the resultant structure from the liquid crystal injection hole, and the liquid crystal injection hole is sealed. Polarizing plates are arranged at appropriate portions, thereby completing an active matrix type liquid crystal display device 901 of this embodiment. When the active matrix type liquid crystal display device 901 is formed in the above manner, since the channel protection film 939 is formed to be self-aligned with the scanning line 911, a gate-source path parasitic capacitance Cgs and a source-drain path parasitic capacitance Cgd of the TFT 971 will not be increased. Since the channel protection film 939 protects the semiconductor film 935 during patterning of the n + a-Si:H film 936, the semiconductor film 935 can be formed to be sufficiently thin, thereby decreasing the photoleakage current Ioff. In the embodiments described above, low-resistance semiconductor films are interposed between a semi-conductor film and electrodes to achieve ohmic contact between them. However, a process, e.g., ion implantation may be executed by using the channel protection film as a mask, and low-resistance semiconductor film regions may be formed in the semiconductor film. In any of the embodiments described above, an amorphous silicon (a-Si:H) film is used as the semiconductor film. However, a poly silicon (p-Si) film, a compound semiconductor film, e.g., a Cd-Se film, or the like may be used as the semiconductor film, as a matter of course. In the embodiments described above, the liquid crystal layer is made of a nematic liquid crystal composition. Other than this, a polymer-dispersed liquid crystal (PD-LC) made of a mixture of a polymeric resin and a liquid crystal material may be used as the material of the liquid crystal layer, as a matter of course. In particular, in an active matrix type liquid crystal display device using a polymer-dispersed liquid crystal (PD-LC), since light which is scattered in the liquid crystal layer and is incident on the TFT is present, the photoleakage current Ioff is increased. According to the present invention, however, even in this active matrix type liquid crystal display device, the photoleakage current Ioff can be sufficiently decreased, thereby obtaining a high-quality display image. Industrial Applicability According to the present invention, the photoleakage current Ioff of a thin-film transistor can be sufficiently suppressed, thereby achieving a high ON/OFF current ratio. In an active matrix type liquid crystal display device formed by using such a TFT, a high-quality display image can be obtained.

Claims: A thin-film transistor comprising: an insulating substrate (100; 900); a light-shielding gate electrode (131; 911) positioned on said insulating substrate (100; 900); a gate insulating film (133; 933) positioned on said gate electrode (131; 911); a semiconductor film (135; 935) positioned above said gate electrode (131; 911) through said gate insulating film (133; 933); a source electrode (151; 951) ; and a drain electrode (141; 941), said source electrode (151; 951) and drain electrode (141; 941) electrically contacting said semiconductor film (135; 935) at respective electrical contacts (137; 937), a channel being defined in said semiconductor film (135; 935) between said respective electrical contacts (137; 937), said channel being positioned above said gate electrode (131; 911), the length of said channel being less than any width of said gate electrode (131; 911) which width is measured in the channel length direction, and said gate electrode (131; 941) overlapping said source and drain electrodes (151, 141; 951, 941); characterized in that said gate electrode (131; 941) has wide parts in the form of source side and/or drain side extensions (GSs, GDs) located at the sides of said channel in the channel width direction which is perpendicular to the channel length direction, and a short part between the wide parts, the source side and/or drain side extensions at portions thereof respectively overlapping the source and/or drain electrodes to reduce light that is applied to the sides of said channel without being shielded by said source and drain electrodes (151, 141; 951, 941). A thin-film transistor according to claim 1, characterized in that said semiconductor film (135; 935) is a silicon semiconductor film. A thin-film transistor according to claim 2, characterized in that said silicon semiconductor film (135; 935) has a thickness of not less than 10 nm and not more than 50 nm. A thin-film transistor according to claim 1, characterized by further comprising a channel protection film (939) formed on said semiconductor film (935) between said respective electrical contacts (937). A thin-film transistor according to claim 4, characterized in that said channel protection film (939) is disposed within an area corresponding to said gate electrode (911) below said source electrode (951) and said drain electrode (941). A thin-film transistor according to claim 5, characterized in that said channel protection film (939) is formed in alignment with said gate electrode (911) in a width direction of said gate electrode (911). A display device comprising: a first substrate (100; 900) having a scanning and signal lines (111, 121; 911, 921), a pixel electrode (181; 981) and a semiconductor element which is connected to said scanning and signal lines to drive said pixel electrode (181; 981), a second substrate (200) positioned to oppose said first substrate (100; 900); and an optical modulating layer (311) positioned between said first and second substrates (100, 200; 900); characterized in that said semiconductor element is the thin film transistor defined in claim 1.

Inventors: MIURA YASUNORI, SEIKI MASAHIRO, SHIBUSAWA MAKOTO, SUGAHARA ATSUSHI, MIURA, YASUNORI, SEIKI, MASAHIRO, SHIBUSAWA, MAKOTO, SUGAHARA, ATSUSHI, SUGAHARA, ATSUSHI /CREARE TOSHIBA NAMIKI NO. 506
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L29
IPC codes: H01L29, H01L21, G02F1, H01L27