Low-voltage output driving circuit

Abstract: A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S₂ of a first CMOS inverter INV C1 and the node S₁ at the gate of an MOS transistor PT₃ for active pull-up. At the same time, a reference voltage V REF and a voltage level V OUT , which corresponds to the voltage level of the output line of the signal S OUT , are compared by a comparator CMP. When the voltage V OUT is lower than the reference voltage V REF , the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV C1 is sent to the gate of the transistor PT₃ for active pull-up. The comparator CMP is installed so that when the voltage level V OUT is higher than the reference voltage V REF , the output of the first CMOS inverter INV C1 is prevented from reaching the gate of the transistor PT₃ for active pull-up. Thus, although the input and output can take on any state, the generation of leakage current which flows toward the power supply from the output side can be prevented.

Description: This invention pertains to a low-voltage output driving circuit to be applied as an interface to a mixed voltage system. BACKGROUND OF THE INVENTION Recently, the demands of higher speed and lower power consumption for digital electronic circuits to be adopted in a broad field have increased. A circuit which can meet such demands to some degree has recently been realized by a BiCMOS integrated circuit in which bipolar technology and CMOS technology are combined. Also, a further large reduction in power consumption has been realized by a low-voltage technology, and thus, a 3.3V power supply could be used instead of a 5 V power supply. For this reason, for example, the realization of a low voltage output driving circuit which can be applied to a mixed voltage system containing equipment having respective power supplies of 5 V and 3.3 V is required, and some low-voltage output driving circuits are suggested for this purpose. Figure 5 is a circuit diagram of a conventional low-voltage output driving circuit which adopts this low-voltage technology. In Figure 5, 1 is a logic device. V CC represents a 3.3 V power supply voltage, for instance. Q 1 -Q 3 are npn bipolar transistors. NT 1 -NT 3 are n channel MOS transistors (hereinafter, referred to as NMOS transistors). PT 1 -PT 3 are p channel MOS transistors (hereinafter, referred to as PMOS transistors). D 1 is a diode. Also, the diode D 1 can be a Schottky diode, for instance. The input signal S IN and the control signal C IN are input to the logic device 1. In the logic device 1, three output levels are controlled by the control signal C IN . When this low-voltage output driving circuit functions as an ordinary buffer, the input level of the signal S IN is output as is. When the outputs of the low-voltage output driving circuit functions are in three state modes, which includes a high impedance state, the first and second outputs are set to a low level, and the third output is set to a high level. The base of the bipolar transistor Q 1 is connected to the first output of the logic device 1, and the collector of the transistor Q 1 is connected to the cathode of the diode D 1 and the collector of the bipolar transistor Q 2 , and the emitter of the transistor Q 1 is connected to the base of the bipolar transistor Q 2 . The anode of the diode D 1 is connected to the power supply voltage V CC . The emitter of the bipolar transistor Q 2 is connected to the drain of the PMOS transistor PT 3 and the NMOS transistor NT 3 and to the collector of the bipolar transistor Q 3 . At the same time, the emitter of the transistor Q 2 is connected to the output line of the output signal S OUT . The drains and also the gates of the PMOS transistor PT 1 and the NMOS transistor NT 1 are connected together. At the same time, the source of the PMOS transistor PT 1 is connected to the power supply voltage V CC , and the source of the NMOS transistor NT 1 is grounded. Thus, the first CMOS invertor INV C1 is constituted. The input to the first CMOS invertor INV C1 , namely, the point of connection of the gates of the PMOS transistor PT 1 and the NMOS transistor NT 1 is connected to the second output of the logic device 1, and the output, namely, the point of connection of the drains of both transistors, is connected to the gate of the PMOS transistor PT 3 . The drains and also the gates of the PMOS transistor PT 2 and the NMOS transistor NT 2 are connected together. At the same time, the source of the PMOS transistor PT 2 is connected to the power supply voltage V CC , and the source of the NMOS transistor NT 2 is grounded. Thus, the second CMOS invertor INV C2 is constituted. The input of the second CMOS invertor INV C2 , namely, the point of connection of the gates of the PMOS transistor PT 2 and the NMOS transistor NT 2 is connected to the third output of the logic device 1, and the output, namely, the point of connection of the drains of both transistors is connected to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 . Also, the base of the bipolar transistor Q 3 and the source of the NMOS transistor NT 3 are grounded. In this constitution, when the input signal S IN is input at a high level, since the bipolar transistor Q 1 turns ON, the bipolar transistor Q 2 turns ON. Also, the output of the first CMOS invertor INV C1 goes low, and is supplied to the gate of the PMOS transistor PT 3 for active pull-up. Thus, the PMOS transistor PT 3 turns ON. The output of the second CMOS invertor goes low, and is provided to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 . Thus, the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained at the ON state. The emitter voltage of the bipolar transistor Q 2 is maintained two base-emitter voltage drops below the power supply voltage V CC because of the bipolar transistors Q 1 and Q 2 . However, since the emitter of the bipolar transistor Q 2 is connected to the drain of the p-channel MOS transistor PT 3 , the output signal S OUT is maintained to almost the power supply voltage V CC level, and is output. On the other hand, when the input signal S IN is input at a low level, the bipolar transistors Q 1 and Q 2 are kept in the OFF state, the output of the first CMOS invertor INVC C1 goes high, and the PMOS transistor PT 3 is kept in the OFF state. The output of the second CMOS invertor INV C2 goes high, and is supplied to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 . Thus, the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the ON state. As both the transistor Q 3 and the NT 3 are ON, the output signal S OUT is maintained at a ground level, and is output. Also, at a time of three state logic, the first and second outputs of the logic device 1 are set to a low level, and are supplied to the base of the bipolar transistor Q 1 and the input of the first CMOS invertor INV C1 . Thus, the bipolar transistors Q 1 and Q 2 are maintained in the OFF state, and since the output of the first CMOS invertor INV C1 goes high and is supplied to the gate of the PMOS transistor PT 3 , the PMOS transistor PT 3 is also maintained in the OFF state. On the other hand, the third output of the logic device 1 is set to a high level and is supplied to the input of the second CMOS invertor INV C2 . Thus, the output of the second CMOS invertor INV C2 goes low, and since it is supplied to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 , the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the OFF state. Therefore, the output line of the signal S OUT is maintained at the high impedance state. As mentioned previously, since the circuit of Figure 5 has the PMOS transistor PT 3 for active pull-up, the level is too low at the time of high output, and cannot be regarded as a true high level at all. Also, the output corresponding to three states can be stably obtained. However, in the above-mentioned conventional circuit, the output potential exceeds the power supply voltage V CC (3.3 V) by a composite voltage signal to be connected. For example, when it is 5 V, regardless of whether the gate level of the PMOS transistor PT 3 for active pull-up is high (V CC ) or low, the PMOS transistor PT 3 is ON, and current flows from the output side to the power supply via the PMOS transistor PT 3 . In other words, there is the problem of leakage current. It is therefore an object of this invention to provide a low-voltage output driving circuit capable of preventing the occurrence of leakage current. EP-A 0 480 201, on which the preamble of claim 1 is based, describes a driver circuit with a P-FET pull-up transistor and a N-FET pull-down transistor. A transmission gate including an N-FET transistor is provided in the control input to the pull-up ransistor, and a further P-FET transistor between that control input and the output of the driver circuit. If the pull-up and pull-down transistors are both set OFF, giving a high impedance output state, and the output is then raised to a voltage above the power supply voltage, the source to the N-well junction of the further P-FET is forward biased. Current thus flows into the well, raising the gate voltage of the pull-up transistor, which shares the common N-well,and turning the pull-up transistor OFF. The voltage at the output of the transmission gate N-FET also rises, turning that OFF. Leakage of the high voltage from the output back through the driver circuit is thus prevented. EP-A 0 546 724 describes somewhat similar circuits. The present invention provides a low-voltage output driving circuit comprising: a buffer stage comprising an input for connection to a control circuit and an output; a pull-up transistor connected between the output and a power supply voltage source, said pull-up transistor having a control terminal for rendering said pull-up transistor conductive when activated; a gate circuit having an input and an output, the input of said gate circuit coupled connected to the control circuit and the output of said gate circuit being connected to the control terminal of said pull-up transistor; a clamping transistor connected to the output and to the control terminal of said pull-up transistor at a node located in the connection between said gate circuit and said pull-up transistor, said clamping transistor having a control terminal for connection to the power supply voltage source and having respective input and output terminals, the input terminal of said clamping transistor being connected to the node between said gate circuit and the control terminal of said pull-up transistor and the output terminal of said clamping transistor being connected to the output of said buffer stage; said clamping resistor when conductive maintaining the control terminal of said pull-up transistor at the output level of said buffer stage when the output level is higher than the level of the power supply voltage; and a gate control circuit operably regulating said gate circuit for rendering said gate circuit conductive when the output level from said buffer stage is lower than the power supply voltage level and for rendering said gate circuit non-conductive when the ouput level of said buffer stage is higher than the power supply voltage level; said gate circuit including a transfer gate connected between the output of said control circuit and said node at the control terminal of said pull-up transistor whereby said transfer gate has a second input coupled to the output of the buffer stage characterised in that said transfer gate has the first control input connected to a comparator, said comparator having first and second inputs for respectively receiving a reference voltage and the output voltage from the output of said buffer stage; said comparator producing an output signal turning on said transfer gate when the voltage level corresponding to the voltage of the output line is less than the reference voltage, thereby enabling the output of said gate circuit to be provided to the control terminal of said pull-up transistor. Thus, the transfer of the output signal of a gate control circuit to the control terminal of a transistor for active pull-up is stopped. At that time, since the output level of a buffer is higher than the power supply voltage, the level of the control terminal of a transistor for active pull-up is maintained at the output level of the buffer. Therefore, the voltage level equivalent to the output level of the buffer is supplied to the control terminal of the transistor for active pull-up. For this reason, although the output level of the buffer is higher than that of the power supply voltage, the transistor for active pull-up maintains the OFF state stably. As a result, the inflow of a leakage current from the output side of a buffer to the voltage source via the transistor for active pull-up is impeded. Also, in case the output of a buffer is in the high impedance state, a transistor for active pull-up is maintained in the OFF state. Here, when the output level of the buffer is higher than the power supply voltage, a gate circuit is maintained in the nonconducting state by a gate control circuit. Thus, the transfer of the output signal of a gate control circuit to the control terminal of a transistor for active pull-up is prevented. At that time, since the output level of the buffer is higher than the power supply voltage, the level of the control terminal of a transistor for active pull-up is maintained at the output level of the buffer. Therefore, the voltage level approximately equal to the output level of the buffer is supplied to the control terminal of a transistor for active pull-up. For this reason, although the output level of the buffer is higher than the power supply voltage, a transistor for active pull-up maintains the OFF state stably. As a result, the inflow of a leakage current from the output side of the buffer to the voltage source via a transistor for active pull-up is impeded. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a first embodiment of a low-voltage output driving circuit in accordance with the invention. Figure 2 is a circuit diagram of a second embodiment of the low-voltage output driving circuit of this invention. Figure 3 is a circuit diagram of the same circuit shown in Figure 2, but showing additional circuit details. Figure 4 is a graph which shows the relationship between the voltage at the output side of the circuits of Figures 1 and 2 and the leakage current. Figure 5 is a circuit diagram of a conventional low-voltage output driving circuit. Reference numerals and symbols as shown in the drawings: 1 Logic device V CC Power supply voltage Q 1 -Q 3 npn type bipolar transistor NT 1 -NT 8 NMOS transistors PT 1 -PT 11 PMOS transistors D 1 -D 3 Diodes GT Transfer gate CMP Comparator INV C1 First CMOS inverter INV C2 Second CMOS inverter INV Inverter R 1 -R 4 Resistors DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 is a circuit diagram of a first embodiment of a low-voltage output driving circuit in accordance with the invention. Component parts of the circuit diagram of Figure 1 which are the same as those of Figure 5 which shows a conventional low-voltage output driving circuit are indicated by the same reference numerals and symbols. That is, 1 is a logic device. V CC is a power supply voltage of 3.3 V, for instance. Q 1 -Q 3 are npn-type bipolar transistors. NT 1 -NT 3 are NMOS transistors. PT 1 -PT 5 are PMOS transistors. D 1 -D 3 are diodes. Also, the diodes D 1 -D 3 can be Schottky diodes, for instance. Next, the interconnection between elements of the circuit of Figure 1 will be described, focusing on the parts different from those of the conventional circuit of Figure 5, namely, the diodes D 2 and D 3 and the PMOS transistors PT 4 and PT 5 . The anode of the diode D 2 is connected to the power supply voltage V CC , and the cathode of the diode D 2 is connected to the source of the PMOS transistor PT 1 which constitutes the first CMOS invertor INV C1 . The anode of the diode D 3 is connected to the power supply voltage V CC , and the cathode of the diode D 3 is connected to the gates of the PMOS transistors PT 1 , PT 3 , PT 4 , and PT 5 and the source of the PMOS transistor PT 5 . The source of the PMOS transistor PT 4 for clamping is connected to the node S 1 between the output of the first CMOS inverter INV C1 and the gate of the PMOS transistor PT 3 , and the drain is connected to the output line of the signal S OUT . The gate of PMOS transistor PT 5 is connected to the power supply voltage V cc and the drain is connected to the output line S OUT . When the input signal S IN is input at a high level, the bipolar transistors Q 1 and Q 2 become conductive and are maintained in the ON state. Also, since the NMOS transistor NT 1 goes ON, the output of the first CMOS inverter INV C1 is brought to ground, the low level, and is supplied to the gate of the PMOS transistor PT 3 for active pull-up. Thus, the PMOS transistor PT 3 goes ON, and the output line of the signal S OUT is pulled up to the power supply voltage V CC . At that time, in the output of the second CMOS inverter INV C2 , the NMOS transistor NT 2 goes ON, and the level of the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 are brought to ground level. Thus, the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the OFF state. The emitter voltage of the bipolar transistor Q 2 is maintained two base-emitter voltage drops below the power supply voltage V cc of the bipolar transistors Q 1 and Q 2 . However, since the emitter of the bipolar transistor Q 2 is connected to the drain of the p-channel MOS transistor PT 3 , the output signal S OUT is maintained at almost the power supply voltage V CC level, and is output. When the input signal S IN is input at a low level, the bipolar transistors Q 1 and Q 2 are maintained in the OFF state, and the output of the first CMOS inverter INV C1 goes high. The PMOS transistor PT 3 is maintained in the OFF state. The output of the second CMOS inverter INV C2 becomes a high level, and is supplied to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 . The bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the ON state. As both the transistors Q 3 and NT 3 turn ON, the output signal S OUT is maintained at the ground level and is output. Also, at the time of three-state logic, the first and second outputs of the logic device 1 are set to a low level, and are supplied to the base of the bipolar transistor Q 1 and the input of the first CMOS inverter INV C1 . Thus, the bipolar transistors Q 1 and Q 2 are maintained in the OFF state. Since the output of the first CMOS inverter INV C1 goes high and is supplied to the gate of the PMOS transistor PT 3 , the PMOS transistor PT 3 is also maintained in the OFF state. On the other hand, the third output of the logic device 1 is set to the high level, and is supplied to the input of the second CMOS inverter INV C2 . Since the output of the second CMOS invertor INV C2 becomes a low level and is provided to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 , the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the OFF state. Therefore, the output line of the signal S OUT is maintained at the high impedance state. Next, the operation when the output of this low-voltage output driving circuit is higher than the power supply voltage V CC will be explained. When the output becomes the high impedance state, all of the transistors connected to the output line go OFF, and the node S 1 is at a high level which is almost equal to the power supply voltage V CC . Here, when the output line is higher than the power supply voltage V CC , and when the voltage difference between the output line and the power supply voltage V CC is greater than the threshold voltage of the PMOS transistors PT 3 , PT 4 , and PT 5 , the PMOS transistors PT 3 , PT 4 , and PT 5 are turned ON. However, as the PMOS transistor PT 4 goes ON, since the voltage level of the node S 1 is almost equal to the voltage level of the output line, the PMOS transistor PT 3 maintains the OFF state. Therefore, the leakage current which flows from the output line to the power supply voltage V CC via the PMOS transistor PT 3 is prevented. At that time, the PMOS transistors PT 1 , PT 4 , and PT 5 are ON; however the current path between the output line via the PMOS transistors PT 1 , PT 4 , and PT 5 and the power supply voltage V CC is blocked by the diodes D 2 and D 3 . Also, since the substrates of the PMOS transistors PT 4 and PT 5 are connected to the cathode of the diode D 3 and the anode is connected to the power supply voltage V CC , there is no leakage current via the drain-substrate junction. As explained previously, according to this embodiment, when the output side is in the high impedance state, equipment with a much higher operating voltage is connected to the output side, and the leakage current from the output side to the power supply voltage V CC to be generated when the output side is higher than the power supply voltage V CC can be suppressed. Figure 2 is a circuit diagram of a second embodiment of the low-voltage output driving circuit of the invention. In the first embodiment of the circuit shown in Figure 1, when the level of the node S 1 at the gate of the transistor PT 3 for pulling up is high, the inflow of a leakage current into the power supply voltage V CC can be reliably prevented. However, when the level at node S 1 is low, and when the PMOS transistor PT 3 pulls up the output line of the signal S OUT , the PMOS transistor PT 4 turns ON, so that the level of S 1 tries to equal the level of the output line. However, since the NMOS transistor NT 1 is ON, the level of S 1 is not equal to the level of the output line, and the PMOS transistor PT 3 does not turn completely OFF. Still, the leakage current flows into the power supply voltage V CC from the output side. More specifically, in addition to the circuit make-up of Figure 1, the circuit of Figure 2 has a transfer gate GT installed between the output S 2 of the first CMOS inverter INV C1 and the node S 1 at the gate of the transistor PT 3 for active pull-up. At the same time, the preset reference voltage V REF and the voltage level V OUT which corresponds to the voltage level of the output line of the signal S OUT are compared. When the voltage level V OUT is less than the reference voltage V REF , the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV C1 is supplied to the gate of the transistor PT 3 for active pull-up. So, when the comparator CMP is installed as a gate control circuit, the voltage level V OUT is less than the reference voltage V REF , the transfer gate GT is set to the ON state, and the output of the first CMOS inverter is supplied to the gate of the transistor PT 3 for active pull-up. The transfer gate GT is provided by the NMOS transistor NT 4 and the PMOS transistor PT 6 , in which the sources and drains are connected to each other. The point of connection of the drain of the NMOS transistor NT 4 and the source of the PMOS transistor PT 6 is connected to the node S 2 between the drain of the PMOS transistor PT 1 and the drain of the NMOS transistor NT 1 , which are the outputs of the first CMOS inverter INV C1 . The point of connection of the source of the NMOS transistor NT 4 and the drain of the PMOS transistor PT 6 is connected to the node S 1 at the gate of the transistor PT 3 for active pull-up. The gate of the NMOS transistor NT 4 is connected to the output of the comparator CMP, and the gate of the PMOS transistor PT 6 is connected to the output line of the signal S OUT . Also, the substrate of the PMOS transistor PT 6 is connected to the cathode of the diode D 3 . The reference voltage V REF is set to the level in which the power supply voltage V CC is divided by the resistors R 1 and R 2 connected in series between the power supply voltage V CC and ground. The point of connection of the resistors R 3 and R 4 is connected to the inverting input (+) of the comparator CMP. The voltage level V OUT is generated as a level in which the voltage of the output line is divided by the resistors R 3 and R 4 connected in series between the output line of the signal S OUT and ground. The point of connection of the resistors R 3 and R 4 is connected to the noninverting input (-) of the comparator CMP. Figure 3 is a circuit diagram showing the comparator CMP part of the circuit of Figure 2 as comprising MOS transistors. In Figure 3, a constant current source is provided by the NMOS transistor NT 8 and the PMOS transistors PT 9 -PT 11 , and a differential amplifier is provided by the PMOS transistors PT 7 -PT 9 and the NMOS transistors NT 5 and NT 6 . An output stage is provided by the PMOS transistor PT 10 and the NMOS transistor NT 7 . The source of the PMOS transistor PT 7 is connected to the source of the PMOS transistor PT 8 and the drain of the PMOS transistor PT 9 , and the gate is connected to the node connecting the resistors R 1 and R 2 . The drain of PMOS transistor PT 7 is connected to the drain of the NMOS transistor NT 5 and the gates of the NMOS transistors NT 5 and NT 6 . The gate of the PMOS transistor PT 8 is connected to the node connecting the resistors R 3 and R 4 , and the drain is connected to the drain of the NMOS transistor NT 6 and the gate of the NMOS transistor NT 7 . Also, the source of the NMOS transistor NT 5 and the source of the NMOS transistor NT 6 are grounded. The gates of the PMOS transistors PT 9 -PT 11 are connected to each other, and each source is connected to the power supply voltage V CC . The drain of the PMOS transistor PT 10 is connected to the drain of the NMOS transistor NT 7 , and a node is the connection between the drains of the transistors PT 10 and NT 1 is connected to the input of the inverter INV. The output of the inverter INV is connected to the gate of the NMOS transistor NT 4 of the transfer gate GT. The drain of the PMOS transistor PT 11 is connected to its gate, and at the same time, to the drain and gate of the NMOS transistor NT 8 . Also, the sources of the NMOS transistors NT 7 and NT 8 are grounded. Referring to the circuit of Figure 2, at a steady state, the voltage of the output line of the signal S OUT is at a level less than or equal to the power supply voltage V CC . Therefore, the voltage level V OUT to be input into the comparator CMP becomes a level lower than the reference voltage V REF . A high-level signal is output from the comparator CMP, and is input to the gate of the NMOS transistor NT 4 of the transfer gate GT. Thus, the NMOS transistor NT 4 goes ON. In other words, the transfer gate GT is maintained at the ON state. In this state, when the input signal S IN is input at a high level, the bipolar transistors Q 1 and Q 2 go ON. Also, since the NMOS transistor NT 1 goes ON, the output of the first CMOS inverter INV C1 is brought to ground, the low level, and is provided to the gate of the PMOS transistor PT 3 for active pull-up via the transfer gate GT. Thus, the PMOS transistor PT 3 goes ON and the output line of signal S OUT is pulled up to the power supply voltage V CC . At that time, the NMOS transistor NT 2 of the second CMOS inverter INV C2 goes ON, and the level of the source of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 is brought to ground level. Thus, the bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the OFF state. The level of the emitter of the bipolar transistor Q 2 is maintained at a level in which the voltage drop due to the base-emitter junction of the bipolar transistors Q 1 and Q 2 is subtracted from the power supply voltage V CC . However, since the emitter of the bipolar transistor Q 2 is connected to the drain of the p-channel MOS transistor PT 3 , the output signal S OUT is maintained at the power supply voltage V CC level, and is output. At that time, since the gate of the PMOS transistor PT 6 of the transfer gate GT is maintained at a high level, the PMOS transistor PT 6 is maintained in the OFF state. Here, when the output level is higher than the power supply voltage V CC (3.3 V), for example, 5 V, the power supply voltage V OUT to be input to the comparator CMP is higher than the reference voltage V REF . A low-level signal from the comparator CMP is output, and is input to the gate of the NMOS transistor NT 4 of the transfer gate GT. Thus, the NMOS transistor NT 4 goes OFF. At that time, since the PMOS transistor PT 6 of the transfer gate GT is in the OFF state (since its gate is high), the transfer gate GT is maintained in the OFF state. In other words, the output signal of the first CMOS inverter INV C1 is not transferred to the gate of the transistor PT 3 for active pull-up. On the other hand, in the PMOS transistors PT 4 and PT 5 , when the voltage of the drains is higher than V CC at the gates, it exceeds the threshold voltage, and the transistors PT 4 and PT 5 then turn ON. Since the PMOS transistor PT 4 turns ON, the level of the node S 1 at the gate of the PMOS transistor PT 3 for active pull-up is almost equal to the output level. Therefore, a voltage of about 5 V equivalent to the output level is supplied to the gate of the PMOS transistor PT 3 . For this reason, although the output level is higher than the power supply voltage V CC (3.3 V), for example, 5 V, since the PMOS transistor PT 3 maintains the OFF state stably, the inflow of leakage current from the output side to the power supply voltage V CC via the PMOS transistor PT 3 is impeded. At that time, since the source of the PMOS transistor PT 4 is connected to the node S 1 , and since the source of the PMOS transistor PT 5 is connected to the cathode of the diode D 3 , there is no current leakage from the output line to the power supply voltage V CC via the PMOS transistor PT 4 or PT 5 . Also, since the substrates of the PMOS transistors PT 4 and PT 5 are connected to the cathode of the diode D 3 and the anode is connected to the power supply voltage V CC , there is no leakage current via the drain-substrate junction. At the time of three-state logic (high impedance state), when the level of an output line is about 5 V, which is higher than the power supply voltage, the PMOS transistor PT 6 and the NMOS transistor NT 4 turn OFF via the high level of an output line and the high-level output of the comparator CMP, and the transfer gate GT turns OFF. Also, since the PMOS transistor PT 4 turns ON, the level of the node S 1 is equal to the level of an output line, and the PMOS transistor PT 3 maintains the OFF state stably. Therefore, there is no leakage of current via the PMOS transistor PT 3 . Also, the operation of this embodiment (Figure 2) in this state is similar to that of the first embodiment (Figure 1). Also, when the output of the comparator CMP is high, and when the transfer gate GT is in a steady ON state, if the input signal S IN is input as a low level signal, the bipolar transistors Q 1 and Q 2 are maintained in the OFF state. The output of the first CMOS inverter INV C1 goes high, and the PMOS transistor PT 3 is maintained in the OFF state. The output of the second MOS inverter INV C2 goes high and is supplied to the base of the bipolar transistor Q 3 and the gate of the NMOS transistor NT 3 . The bipolar transistor Q 3 and the NMOS transistor NT 3 are maintained in the ON state. As both the transistors Q 3 and NT 3 turn ON, the output signal S OUT is maintained at the ground level and is output. At this time, since the gate of the PMOS transistor PT 6 of the transfer gate GT is maintained at the low level, the PMOS transistor PT 6 is maintained in the ON state. For this reason, when only the NMOS transistor NT 4 of the transfer gate GT is ON, the signal level to be transferred to the node S 1 drops to a level at which the threshold voltage V THN of the NMOS transistor NT 4 is subtracted from V cc . However, as the PMOS transistor PT 6 goes ON, the signal level to be transferred to the node S 1 is transferred at the V CC level, and the transistor PT 3 for active pull-up is stably maintained in the OFF state. Figure 4 is a graph which shows the relationship between the voltage at the output side of the circuits of Figure 1 and Figure 2 and the leakage current of the PMOS transistor PT 3 for active pull-up when the bipolar transistors Q 1 and Q 2 are ON and output a high-level signal (the output of the inverter INV C1 is low). In Figure 4, the abscissa indicates the voltage at the output side, and the ordinate indicates the leakage current. As seen from Figure 4, according to the circuit of Figure 2, when a high-level signal is output, a leakage current in the case where the voltage at the output side exceeds 3.3 V, which is the V CC level, is reduced to "0" A. As previously described, according to the embodiment of Figure 2, the transfer gate GT is installed between the output S 2 of the first CMOS inverter INV C1 and the node S 1 at the gate of the transistor PT 3 for active pull-up. At the same time, the preset reference voltage V REF and the voltage level V OUT which corresponds to the voltage level of the output line of the signal S OUT are compared. When the voltage V OUT is lower than the reference voltage V REF , the transfer gate GT turns ON, and the output of the first CMOS inverter INV C1 is supplied to the gate of the transistor PT 3 for active pull-up. When the voltage level is higher than the reference voltage V REF , since the comparator CMP stops the output of the first CMOS inverter INV C1 from reaching the gate of the transistor PT 3 for active pull-up, there is the advantage that although the voltage at the output side exceeds the power supply voltage V CC , the leakage current which may flow to the voltage source can be reliably prevented. Also, in the circuit of Figure 3, the comparator CMP part comprises MOS transistors. However, the comparator CMP could be constructed differently, such as being made of bipolar transistors, for example. In accordance with the invention, although the input and output of the low-voltage output driving circuit may be in any state, the generation of leakage current which flows toward the power supply from the output side can be reliably prevented.

Claims: A low-voltage output driving circuit comprising: a buffer stage comprising an input (S in ) for connection to a control circuit (1) and an output (S out ) ; a pull-up transistor (PT 3 ) connected between the output and a power supply voltage source, said pull-up transistor having a control terminal for rendering said pull-up transistor conductive when activated; a gate circuit (GT) having an input and an output, the input of said gate circuit being coupled to the control circuit and the output of said gate circuit being connected to the control terminal of said pull-up transistor; a clamping transistor (PT 4 ) connected to the output and to the control terminal of said pull-up transistor at a node located in the connection between said gate circuit and said pull-up transistor, said clamping transistor having a control terminal for connection to the power supply voltage source (V cc ) and having respective input and output terminals, the input terminal of said clamping transistor being connected to the node between said gate circuit and the control terminal of said pull-up transistor and the output terminal of said clamping transistor being connected to the output of said buffer stage; said clamping transistor when conductive maintaining the control terminal of said pull-up transistor at the output level of said buffer stage when the output level is higher than the level of the power supply voltage; and a gate control circuit (CMP) operably regulating said gate circuit for rendering said gate circuit conductive when the output level from said buffer stage is lower than the power supply voltage level and for rendering said gate circuit non-conductive when the output level of said buffer stage is higher than the power supply voltage level; said gate circuit including a transfer gate (GT) connected between the output of said control circuit (1) and said node at the control terminal of said pull-up transistor; whereby said transfer gate has a second control input coupled to the output of the buffer stage characterised in that said transfer gate has the first control input connected to a comparator (CMP), said comparator having first and second inputs for respectively receiving a reference voltage (V ref ) and the output voltage from the output of said buffer stage (V out ) ; said comparator producing an output signal turning on said transfer gate when the voltage level corresponding to the voltage of the output line is less than the reference voltage, thereby enabling the output of said gate circuit to be provided to the control terminal of said pull-up transistor (PT 3 ). A driving circuit as set forth in claim 1, characterised in that said gate circuit (INV c1 ) comprises an inverter defined by a pair serially connected CMOS transistors (PT 1 , NT 1 ) having their respective control terminals connected together; and the control circuit is connected to a second node in the connection between the control terminals of said pair of CMOS transistors defining said inverter. A driving circuit as set forth in claim 2, characterised by a second inverter defined by a second pair of serially connected CMOS transistors (PT 2 , NT 2 ) having their respective control terminals connected together; said control circuit being connected to a third node interposed in the connection between the control terminals of said CMOS transistors included in said second inverter; and a further bipolar transistor (Q 3 ) and an MOS transistor (NT 3 ) connected in parallel to the output of said buffer stage and to ground, each of said further bipolar transistor and said MOS transistor having a control terminal; the output of said second inverter being connected to the control terminals of said further bipolar transistor and said MOS transistor for controlling the conductivity thereof. A driving circuit as set forth in claim 2 or claim 3, characterised by a companion transistor (PT 5 ) having a control terminal and connected between the power supply voltage source and the output of said buffer stage and having a control terminal connected to the control terminal of said clamping transistor; a first blocking diode (D 2 ) interconnected between the power supply voltage source and said first inverter (PT 1 , NT 1 ) ; and a second blocking diode (D 1 ) interconnected between the power supply voltage source and said companion transistor; said first and second diodes blocking the current path between the output of said buffer stage and the power supply voltage source via the first inverter, and the companion transistor.

Inventors: GOTOH KIMIKO, GOTOH, KIMIKO, GOTOH, KIMIKO, C/O JAPAN TEXAS INSTRUMENTS CO. LTD
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1994
Main classification: H03K19
IPC codes: H03K19, H03K17