CMOS polyphase clock generation circuits

Abstract: A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

Description: BACKGROUND OF THE INVENTION The present invention relates to polyphase clock generation circuits which employ a clock driver of the Complementary Metal Oxide Semiconductor (CMOS) inverter configuration. In recent years, there has been a progressively increasing demand for high-speed operation and low-power dissipation in semiconductor integrated circuits for use in microcomputers or like electronic apparatus in which desired processing is executed in response to polyphase clocks. However, the characteristics of actual semiconductor integrated circuits cannot satisfy this demand because the power dissipation of these circuits increases as the speed of operation increases. As a conventional example of polyphase clock generation circuit used to generate polyphase clocks in such semiconductor integrated circuits, a two-phase clock generation circuit which generates from a single-phase clock  a first clock  1 and a second clock  2 of different phase is described below with reference to Fig. 1. The two-phase clock generation circuit 100 includes an inverter 101, a first NAND gate 102, a second NAND gate 103, a first delay circuit 104, a second delay circuit 105, a first clock driver 106, and a second clock driver 107. The inverter 101 inverts the polarity of the single-phase clock  to produce an inverted clock '. The first NAND gate 102 negates the logical AND between the single-phase clock  and the output signal of the second delay circuit 105. The second NAND gate 103 negates the logical AND between the inverted clock ' and the output signal of the first delay circuit 104. The first delay circuit 104 delays the output signal of the first NAND gate 102 by a predetermined first delay time dt 1 . The second delay circuit 105 delays the output signal of the second NAND gate 103 by a predetermined second delay time dt 2 . The first clock driver 106 has the configuration of a CMOS inverter formed from a first PMOS transistor M p1 and a first NMOS transistor M n1 , and inverts the polarity of the output signal of the first NAND gate 102 to produce the first clock  1 . The second driver 107 has the configuration of a CMOS inverter formed from a second PMOS transistor M p2 and a second NMOS transistor M n2 , and inverts the polarity of the output signal of the second NAND gate 103 to produce the second clock  2 . The operation of the two-phase clock generation circuit 100 is described with reference to a timing chart shown in Fig. 2. It is assumed that, as an initial state, sufficient time has passed while the single-phase clock  remains at high level and the two-phase clock generation circuit 100 is in a stable condition. In this condition, the first clock  1 is at high level while the second clock  2 is at low level, as shown at time t 0 in Fig. 2. When the single-phase clock  subsequently changes to low level at time t 1 , the output signal of the first NAND gate 102 changes to high level, and consequently, the first clock  1 changes from high level to low level after the delay of the delay time provided by the first clock driver 106. Meanwhile, at time t 1 , the inverted clock ' outputted from the inverter 101 changes to high level. However, since the output signal of the first NAND gate 102 is inputted to the second NAND gate 103 only after the delay of the delay time dt 1 of the first delay circuit 104, the output signal of the first NAND gate 102 changes from high level to low level after the delay of the first delay time dt 1 from time t 1 . As the delay time at the second clock driver 107 is substantially equal to the delay time at the first clock driver 106, the second clock  2 changes from low level to high level after the delay of the first delay time dt 1 that commences when the first clock  1 changes from high level to low level. Thereafter, when the single-phase clock  changes from low level to high level at time t 2 , the inverted clock ' outputted from the inverter 101 changes to low level. As a result, the output signal of the second NAND gate 103 changes to high level and the second clock  2 changes from high level to low level after the delay of the delay time at the second clock driver 107. Meanwhile, at time t 2 , the output signal of the second NAND gate 103 changes to high level. However, since the output signal of the second NAND gate 103 is inputted to the first NAND gate 102 after the delay of the second delay time dt 2 of the second delay circuit 105, the output signal of the first NAND gate 102 changes from high level to low level after the delay of the second delay time dt 2 from the time t 2 . As the delay time at the first clock driver 106 is substantially equal to the delay time at the second clock driver 107, the first clock  1 changes from low level to high level after the delay of the second delay time dt 2 that commences when the second clock  2 changes from high level to low level. Thereafter, the operations described above take place repetitively. Accordingly, in the two-phase clock generation circuit 100, the first and second clocks  1 and  2 do not exhibit an overlapping condition of high level thereof and repeat their level variations in synchronism with the single-phase clock . In a semiconductor integrated circuit in which processing is executed in response to polyphase clocks, it is normally necessary that active periods (periods of high level or low level) of the clocks do not overlap with each other. This is because cases in which the active periods of the clocks overlap with each other can cause malfunction of the semiconductor integrated circuit such as a direct transmission phenomenon of data in a latch of the master-slave configuration. Accordingly, a polyphase clock generation circuit must generate clocks such that the magnitude of the displacement between the timing of a level variation of one clock and the timing of a level variation of another clock (that is, a delay between the clocks) may be greater than the magnitude of the gradient of the waveform of the rising or falling edge of the one clock. However, the magnitude of the gradient of the waveform of the rising or falling edge of the clock depends upon the power source voltage for driving the polyphase clock generation circuit (that is, an application of the polyphase clock generation circuit), the weight of the load to the polyphase clock generation circuit, and various other parameters. For example, the gradient of the waveform of the rising or falling edge of the clock when the polyphase clock generation circuit is used with a system wherein the power source voltage is 3 V is higher than that when the polyphase clock generation circuit is used with another system wherein the power source voltage is 5 V, and accordingly, the delay between the clocks must be greater where the power source voltage is 3 V. However, although increasing the delay between clocks increases the margin of safety against malfunctions, increased delay also decreases the operation speed of the semiconductor integrated circuit which operates with the clocks. Accordingly, as the delay between clocks has an appropriate magnitude suitable for the application, a polyphase clock generation circuit is preferably constructed so as to allow adjustment of the delay between clocks from the outside in order to increase the applicability of the polyphase clock generation circuit to various applications. Since the first clock driver 106 shown in Fig. 1 is constructed from the inverter of the CMOS configuration formed from the first PMOS transistor M p1 and the first NMOS transistor M n1 , it has input/output characteristic such as the characteristics illustrated in Fig. 3. When the input voltage V IN to the first clock driver 106 (that is, the voltage of the output signal of the first NAND gate 102) is substantially equal to 0 V, the first PMOS transistor M p1 is ON and the first NMOS transistor M n1 is OFF, and consequently, the output voltage V OUT of the first clock driver 106 (that is, the voltage of the first clock  1 ) is substantially equal to the power source voltage V DD . On the other hand, when the input voltage V IN is substantially equal to the power source voltage V DD , the first PMOS transistor M p1 is OFF and the first NMOS transistor M n1 is ON, and consequently, the output voltage V OUT is substantially equal to 0 V. Accordingly, within a period within which the first clock driver 106 is in a stable condition, such as a period "a" or another period "c" shown in Fig. 3, at least one of the first PMOS transistor M p1 and the first NMOS transistor M n1 is OFF, and no through-current flows through the first clock driver 106. As a result, the power dissipation of the first clock driver 106 in a stable condition is very low. However, within a period of a transition condition such as a period "b" shown in Fig. 3, the first PMOS transistor M p1 and the first NMOS transistor M n1 are both ON, and through-current flows through the first clock driver 106. The through-current increases as the channel widths (that is, the conductance) of the first PMOS transistor M p1 and the first NMOS transistor M n1 increase and as the operation frequency (that is, the frequency of the single-phase clock ) increases. Accordingly, conventional polyphase clock generation circuits which include clock drivers of the CMOS inverter configuration such as the two-phase clock generation circuit 100 shown in Fig. 1 have problems in that the power dissipation is high since through-current flows upon switching of the clock drivers, that the power dissipation by the clock drivers increases as the operation frequency increases, and that power source noise or ground noise is produced. EP-A-0 348 894 discloses an output buffer circuit used for stable voltage source which is able to be conductive for maintaining the voltage sources stable, and to prevent the output inverter circuit from the concurrent on-states without any overshoot and undershoot. This circuit comprises a complementary inverter circuit and a controlling circuit which produces a pair of driving signals for shifting the complementary inverter circuit between two levels. The controlling circuit has a pull-down transistor and a pull-up transistor both shifted from the off-states to the on-states on the way between the two levels, so that the driving signals slowly swing their voltage levels in an early stage but steeply reach the two levels. EP-A-0 463 854 discloses a clocked driver circuit wherein an interval in which both first and second outputs are at low level can be prolonged by increasing an RC time constant, and which can be stably operated by preventing changes in timings of output signals due to fluctuations of characteristics of each element with an increase in RC time constant. The circuit comprises a pair of gate circuits, a pair of time constant circuits connected between an ouput terminal of one gate circuit of the pair and an input terminal of the other gate circuit of the pair, and a switching circuit for controlling the time constant of each time constant circuit. In this circuit there are only connected inverters between the output nodes or terminals and logic gates. SUMMARY OF THE INVENTION An object of the present invention is to provide a polyphase clock generation circuit which can achieve reduction of the power dissipation and prevention of production of power source noise and ground noise by suppressing production of through-current upon switching of clock drivers of the CMOS inverter configuration using a delay between clocks. Other objects of the present invention will become obvious from the following description. These objects are achieved by a polyphase clock generation circuit according to claims 1, 2 and 3. A preferred embodiment of the invention is subject-matter of dependent claim 4. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram showing a two-phase clock generation circuit which is a conventional example of a polyphase clock generation circuit; Fig. 2 is a timing chart illustrating operation of the two-phase clock generation circuit shown in Fig. 1; Fig. 3 is a graph illustrating the input/output characteristic of the first clock driver shown in Fig. 1; Fig. 4 is a circuit diagram of a two-phase clock generation circuit according to a first embodiment of a polyphase clock generation circuit of the present invention; Fig. 5 is a timing chart illustrating operation of the two-phase clock generation circuit shown in Fig. 4; Fig. 6 is a circuit diagram of a two-phase clock generation circuit according to a second embodiment of a polyphase clock generation circuit of the present invention; Fig. 7 is a timing chart illustrating operation of the two-phase clock generation circuit shown in Fig. 6; Fig. 8 is a circuit diagram of a four-phase clock generation circuit according to a third embodiment of a polyphase clock generation circuit of the present invention; Fig. 9 is a timing chart illustrating operation of the four-phase clock generation circuit shown in Fig. 8; Fig. 10 is a circuit diagram of a two-phase clock generation circuit according to a fourth embodiment of a polyphase clock generation circuit of the present invention; Fig. 11 is a timing chart illustrating operation of the two-phase clock generation circuit shown in Fig. 10 when the voltage is low; and Fig. 12 is a timing chart illustrating operation of the two-phase clock generation circuit shown in Fig. 10 when the voltage is high. DESCRIPTION OF THE PREFERRED EMBODIMENTS A two-phase clock generation circuit 10 according to the first embodiment of a polyphase clock generation circuit of the present invention includes, as shown in Fig. 4, an inverter 11, a first NAND gate 12, a first NOR gate 13, a second NAND gate 14, a second NOR gate 15, a first delay circuit 16, a second delay circuit 17, a first clock driver 18, and a second clock driver 19. The inverter 11 inverts the polarity of a single-phase clock  to produce an inverted clock '. The first NAND gate 12 negates the logical AND between the single-phase clock  and the output signal of the second delay circuit 17. The first NOR gate 13 negates the logical OR between the single-phase clock  and the output signal of the second delay circuit 17. The second NAND gate 14 negates the logical AND between the inverted clock ' and the output signal of the first delay circuit 16. The second NOR gate 15 negates the logical OR between the inverted clock ' and the output signal of the first delay circuit 16. The first delay circuit 16 delays the output signal of the first NOR gate 13 by a predetermined first delay time dt 1 . The second delay circuit 17 delays the output signal of the second NOR gate 15 by a predetermined second delay time dt 2 . The first clock driver 18 has the configuration of the CMOS inverter formed from a first PMOS transistor M p1 with a gate to which the output signal of the first NAND gate 12 is inputted and a first NMOS transistor M n1 with a gate to which the output signal of the first NOR gate 13 is inputted. The first clock driver produces a first clock  1 from the output signal of the first NAND gate 12 and the output signal of the first NOR gate 13. The second clock driver 19 has the configuration of a CMOS inverter formed from a second PMOS transistor M p2 with a gate to which the output signal of the second NAND gate 14 is inputted and a second NMOS transistor M n2 with a gate to which the output signal of the second NOR gate 15 is inputted. The second clock driver produces a second clock  2 from the output signal of the second NAND gate 14 and the output signal of the second NOR gate 15. The source of the first PMOS transistor M p1 and the source of the second PMOS transistor M p2 are both connected to a power source voltage terminal 20. The source of the first NMOS transistor M n1 and the source of the second NMOS transistor M n2 are both grounded. The drain of the first PMOS transistor M p1 and the drain of the first NMOS transistor M n1 are connected to each other. The drain of the second PMOS transistor M p2 and the drain of the second NMOS transistor M n2 are connected to each other. The operation of the two-phase clock generation circuit 10 is described with reference to the timing chart of Fig. 5. It is assumed that, as an initial stage, sufficient time has passed while the single-phase clock  is at high level and the two-phase clock generation circuit 10 is in a stable condition. In this condition, the first clock  1 is at high level and the second clock  2 is at low level, as shown at time t 0 in Fig. 5. The two input signals to the first NOR gate 13 (that is, the single-phase clock  and the output signal of the second delay circuit 17) both exhibit high level for a period of time from time t 0 to time t 1 , where t 1 represents the time at which the single-phase clock  changes from high level to low level. Consequently, the output signal of the first NOR gate 13 is at low level, and the first NMOS transistor M n1 is OFF. At this point in time, since the two input signals to the second NAND gate 14 (that is, the inverted clock ' and the output signal of the first delay circuit 16) are both at low level, the output signal of the second NAND gate 14 exhibits high level, and the second PMOS transistor M p2 is consequently OFF. Thereafter, when the single-phase clock  changes to low level at time t 1 , the output signal of the first NAND gate 12 changes to high level, and the first PMOS transistor M p1 is consequently turned OFF. At this point in time, since the inverted clock ' outputted from the inverter 11 is at high level, the output signal of the second NOR gate 15 changes to low level, and the second NMOS transistor M n2 is consequently turned OFF. Since the output signal of the second NOR gate 15 is inputted to the first NOR gate 13 by way of the second delay circuit 17, the output signal of the first NOR gate 13 changes from low level to high level after the delay of the second delay time dt 2 that commences when the output signal of the second NOR gate 15 changes to low level at time t 1 . As a result, the first NMOS transistor M n1 is turned ON, and the first clock  1 changes from high level to low level. Since the output signal of the first NOR gate 13 is inputted to the second NAND gate 14 by way of the first delay circuit 16, the output signal of the second NAND gate 14 changes from high level to low level after the delay of the first delay time dt 1 that commences when the output signal of the first NOR gate 13 changes to low level. As a result, the second PMOS transistor M p2 is turned ON, and the second clock  2 changes from low level to high level. In this manner, in the two-phase clock generation circuit 10, the first PMOS transistor M p1 constituting the first clock driver 18 and the second NMOS transistor M n2 constituting the second clock driver 19 are turned OFF in synchronism with the falling edge of the single-phase clock , and the first NMOS transistor M n1 is turned ON after the delay substantially of the second delay time dt 2 from the falling edge of the single-phase clock , and the second PMOS transistor M p2 is then turned ON after the delay of a delay time approximately equal to the sum dt 1 +dt 2 of the first delay time dt 1 and the second delay time dt 2 from the falling edge of the single-phase clock . Accordingly, before the first clock  1 changes from high level to low level, a period, shown by a period "Hi" in Fig. 5, within which the output impedance of the first clock driver 18 exhibits high level (that is, the period within which the first PMOS transistor M p1 and the first NMOS transistor M n1 both exhibit an OFF state) appears. Before the second clock  2 changes from low level to high level, a period, shown by a period "Hi" in Fig. 5, within which the output impedance of the second clock driver 19 exhibits high level (that is, the period within which the second PMOS transistor M p2 and the second NMOS transistor M n2 both exhibit an OFF state) appears. Thereafter, until the single-phase clock  changes to high level at time t 2 , the two input signals to the NAND gate 12 (that is, the single-phase clock  and the output signal of the second delay circuit 17) are both at low level, whereby the output signal of the first NAND gate 12 exhibits high level, and the first PMOS transistor M p1 is OFF. Meanwhile, since the two input signals to the second NOR gate 15 (that is, the inverted clock ' and the output signal of the first delay circuit 16) are both at high level, the output signal of the second NOR gate 15 presents low level, and the second NMOS transistor M p2 is therefore OFF. Thereafter, when the single-phase clock  changes from low level to high level at time t 2 , the output signal of the first NOR gate 13 changes to low level, whereby the first NMOS transistor M n1 is turned OFF. At this point in time, the inverted clock ' outputted from the inverter 11 changes to low level, whereby the output signal of the second NAND gate 14 changes to high level and the second PMOS transistor M p2 is turned OFF. Since the output signal of the first NOR gate 13 is inputted to the second NOR gate 15 by way of the first delay circuit 16, the output signal of the second NOR gate 15 changes from low level to high level after the delay of the first delay time dt 1 that commences when the output signal of the first NOR gate 13 changes to low level. As a result, the second NMOS transistor M n2 is turned ON, and the second clock  2 changes from high level to low level. Meanwhile, since the output signal of the second NOR gate 15 is inputted to the first NAND gate 12 by way of the second delay circuit 17, the output signal of the first NAND gate 12 changes from high level to low level after the delay of the second delay time dt 2 that commences when the output signal of the second NOR gate 15 changes to high level. As a result, the first PMOS transistor M p1 is turned ON, and the first clock  1 changes from low level to high level. In this manner, in the two-phase clock generation circuit 10, the first NMOS transistor M n1 and the second PMOS transistor M p2 are turned OFF in synchronism with the rising edge of the single-phase clock , and after the delay substantially of the first delay time dt 1 from the rising edge of the single clock , the second NMOS transistor M p2 is turned ON, following which the first PMOS transistor M p1 is turned ON after a delay time approximately equal to the slim dt 1 +dt 2 of the first delay time dt 1 and the second delay time dt 2 from the rising edge of the single-phase clock . Accordingly, before the first clock  1 changes from low level to high level, a period, shown by a period "Hi" in Fig. 5, within which the output impedance of the first clock driver 18 exhibits high level (that is, the period within which the first PMOS transistor M p1 and the first NMOS transistor M n1 are both OFF) appears. Before the second clock  2 changes from high level to low level, a period, shown by another period "Hi" in Fig. 5, within which the output impedance of the second clock driver 19 exhibits high level (that is, the period within which the second PMOS transistor M p2 and the second NMOS transistor M n2 are both OFF) appears. Thereafter, operations similar to those from time t 1 to time t 2 described above take place repetitively. Accordingly, in the two-phase clock generation circuit 10, the first clock  1 and the second clock  2 do not present an overlapping condition of high level and repeat their level variations in synchronism with the single-phase clock . In other words, the first clock  1 and the second clock  2 make two-phase clocks of active high level. As is apparent from the foregoing description of the operation, with the two-phase clock generation circuit 10, periods within which the output impedance of the first clock driver 18 exhibit high level can be produced after the rising edge and after the falling edge of the single-phase clock  by individually and independently controlling at different times the ON/OFF states of the first PMOS transistor M p1 and the first NMOS transistor M n1 that constitute the first clock driver 18, and other periods within which the output impedance of the second clock driver 19 exhibit high level can be produced after the rising edge and after the falling edge of the single-phase clock  by individually and independently controlling at different timings the ON/OFF states of the second PMOS transistor M p2 and the second NMOS transistor M n2 that constitute the second clock driver 19. Consequently, through-current which is otherwise produced upon switching of the first clock driver 18 and the second clock driver 19 can be eliminated. As a result, even if the frequency of the single-phase clock  is increased, an increase of the through-current which increases in proportion to the increase of the frequency does not occur, and reduction in power dissipation can be achieved. Since a MOS transistor having a channel width of approximately 400 µm and having a very high current supplying capacity is normally used for a system clock driver, for example, for a microcomputer, a through-current with a peak value of 15 to 20 mA flows in conventional polyphase clock generation circuits. In contrast, very little through-current flows in the polyphase clock generation circuit 10. Consequently, the two-phase clock generation circuit 10 allows construction of a system which has low power dissipation, which produces little power source noise or ground noise due to through-current, and which consequently provides highly reliable operation. A two-phase clock generation circuit 30 according to the second embodiment of a polyphase clock generation circuit of the present invention is different from the two-phase clock generation circuit 10 shown in Fig. 4 in that, as shown in Fig. 6, an output signal of a first NAND gate 32 is inputted to a first delay circuit 36 and an output signal of a second NAND gate 34 is inputted to a second delay circuit 37. The operation of the two-phase clock generation circuit 30 shown in Fig. 6 is described with reference to the timing chart shown in Fig. 7, It is assumed that, as an initial state, sufficient time has passed while the single-phase clock  is at high level and the two-phase clock generation circuit 30 is in a stable condition. In this condition, the first clock  1 exhibits high level and the second clock  2 exhibits low level as shown at time t 0 of Fig. 7. The two input signals to the first NOR gate 33 (that is, the single-phase clock  and the output signal of the second delay circuit 37) both exhibit high level for a period of time from time t 0 to time t 1 , where the time at which the single-phase clock  changes from high level to low level is represented by t 1 . Consequently, the output signal of the first NOR gate 33 is at low level, and the first NMOS transistor M n1 constituting the first clock driver 38 is OFF. At this point of time, since the two input signals to the second NAND gate 34 (that is, the inverted clock ' and the output signal of the first delay circuit 36) are both at low level, the output signal of the second NAND gate 34 exhibits high level and the second PMOS transistor M p2 constituting the second clock driver 39 is OFF. Thereafter, when the single-phase clock  changes to low level at time t 1 , the output signal of the first NAND gate 32 changes to high level and the first PMOS transistor M p1 constituting the first clock driver 38 is turned OFF. At this point of time, since the inverted clock ' outputted from the inverter 31 changes to high level, the output signal of the second NOR gate 35 changes to low level, and the second NMOS transistor M n2 constituting the second clock driver 39 is turned OFF. Since the output signal of the first NAND gate 32 is inputted to the second NOR gate 34 by way of the first delay circuit 36, the output signal of the second NAND gate 34 changes from high level to low level after the first delay time dt 1 that commences when the output signal of the first NAND gate 32 changes to low level. As a result, the second PMOS transistor M p2 is turned ON, and the second clock  2 changes from low level to high level. Further, since the output signal of the second NAND gate 34 is inputted to the first NOR gate 33 by way of the second delay circuit 37, the output signal of the first NOR gate 33 changes from low level to high level after the delay of the second delay time dt 2 that commences when the output signal of the second NAND gate 34 changes to low level at time t 1 +dt 1 . As a result, the first NMOS transistor M n1 is turned ON, and the first clock  1 changes from high level to low level. In this manner, in the two-phase clock generation circuit 30, the first PMOS transistor M p1 and the second NMOS transistor M n2 are turned OFF in synchronism with the falling edge of the single-phase clock , and the second PMOS transistor M p2 is turned ON after a delay approximately equal to the first delay time dt 1 from the falling edge of the single-phase clock , following which the first NMOS transistor M n1 is turned ON after the delay time approximately equal to the sum dt 1 +dt 2 of the first delay time dt 1 and the second delay time dt 2 from the falling edge of the single-phase clock . Accordingly, before the first clock  1 changes from high level to low level, a period appears within which the output impedance of the first clock driver 38 exhibits high level (that is, the period within which the first PMOS transistor M p1 and the first NMOS transistor M n1 both exhibit an OFF state). The period is identified in Fig. 7 as a "HI" period. Before the second clock  2 changes from low level to high level, a period appears within which the output impedance of the second clock driver 39 exhibits high level (that is, the period within which the second PMOS transistor M p2 and the second NMOS transistor M n2 both exhibit an OFF state). This period is also identified as a "HI" period in Fig. 7. Thereafter, the single-phase clock  changes to high level at time t 2 , the two input signals to the first NAND gate 32 (that is, the single-phase clock  and the output signal of the second delay circuit 37) are both at low level, and consequently, the output signal of the first NAND gate 32 exhibits high level and the first PMOS transistor M p1 is OFF. Meanwhile, since the two input signals to the second NOR gate 35 (that is, the inverted clock signal ' and the output signal of the first delay circuit 36) are both at high level, the output signal of the second NOR gate 35 presents low level, and the second NMOS transistor M p2 is OFF. Thereafter, when the single-phase clock  changes from low level to high level at time t 2 , the output signal of the first NOR gate 33 changes to low level, and the first NMOS transistor M n1 is consequently turned OFF. At this point in time, the inverted clock ' outputted from the inverter 31 changes to low level, and consequently, the output signal of the second NAND gate 34 changes to high level, and the second PMOS transistor M p2 is turned OFF. Since the output signal of the second NAND gate 34 is inputted to the first NAND gate 32 by way of the second delay circuit 37, the output signal of the first NAND gate 32 changes from low level to high level after the delay of the second delay time dt 2 that commences when the output signal of the second NAND gate 34 changes to high level. As a result, the first NMOS transistor M p1 is turned ON, and the first clock  1 changes from low level to high level. Meanwhile, since the output signal of the first NAND gate 32 is inputted to the second NOR gate 35 by way of the first delay circuit 36, the output signal of the second NOR gate 35 changes from high level to low level after the delay of the first delay time dt 1 beginning when the output signal of the first NAND gate 32 changes to low level. As a result, the second NMOS transistor M n2 is turned ON, and the second clock  2 changes from high level to low level. In this manner, in the two-phase clock generation circuit 30, the first NMOS transistor M n1 and the second PMOS transistor M p2 are turned OFF in synchronism with the rising edge of the single-phase clock , and after a delay approximately equal to the second delay time dt 2 from the rising edge of the single clock , the first PMOS transistor M p1 is turned ON, following which the second NMOS transistor M p2 is turned ON after a delay time approximately equal to the sum dt 1 +dt 2 of the first delay time dt 1 and the second delay time dt 2 from the rising edge of the single-phase clock . Accordingly, before the first clock  1 changes from low level to high level, a period within which the output impedance of the first clock driver 38 exhibits high level appears (that is, the period within which the first PMOS transistor M p1 and the first NMOS transistor M n1 are both off). This period is identified as a "HI" period in Fig. 7. Before the second clock  2 changes from high level to low level, a period within which the output impedance of the second clock driver 39 exhibits high level appears (that is, the period within which the second PMOS transistor M p2 and the second NMOS transistor M n2 are both off). This period is shown as another "HI" period in Fig. 7. Thereafter, operations similar to the above-described operations from time t 1 to time t 2 take place repetitively. Accordingly, in the two-phase clock generation circuit 30, the first clock  1 and the second clock  2 do not present an overlapping condition of high level and repeat their level variations in synchronism with the single-phase clock . In other words, the first clock  1 and the second clock  2 make two-phase clocks of active high level. In the two-phase clock generation circuit 30, periods within which the output impedance of the first clock driver 38 exhibit high level can be produced after the rising edge and after the falling edge of the single-phase clock  by individually and independently controlling at different timings the ON/OFF states of the first PMOS transistor M p1 and the first NMOS transistor M n1 that constitute the first clock driver 38, and other periods within which the output impedance of the second clock driver 39 exhibit high level can be produced after the rising edge and after the falling edge of the single-phase clock  by individually and independently controlling at different timings the ON/OFF states of the second PMOS transistor M p2 and the second NMOS transistor M n2 , which constitute the second clock driver 39. Consequently, through-current which may otherwise be produced upon switching of the first clock driver 38 and the second clock driver 39 can be eliminated. A four-phase clock generation circuit 50 according to the third embodiment of a polyphase clock generation circuit of the present invention includes, as shown in Fig. 8, an inputting section 60, a first outputting section 70 1 , a second outputting section 70 2 , a third outputting section 70 3 , and a fourth outputting section 70 4 . The inputting section 60 includes a first frequency dividing circuit 61 1 for doubling a frequency of a single-phase clock , a second frequency dividing circuit 61 2 for doubling a frequency of a carrier signal C 0 of the first frequency dividing circuit 61 1 , a first AND gate 62 1 for outputting an output signal S 1 of high level when both the output signal D 1 of the first frequency dividing circuit 61 1 and the output signal D 2 of the second frequency dividing circuit 61 2 exhibit high level, a second AND gate 62 2 for outputting an output signal S 2 of high level when the output signal D 1 of the first frequency dividing circuit 61 1 exhibits low level and the output signal D 2 of the second frequency dividing circuit 61 2 exhibits high level, a third AND gate 62 3 for outputting an output signal S 3 of high level when the output signal D 1 of the first frequency dividing circuit 61 1 exhibits high level and the output signal D 2 of the second frequency driving circuit 61 2 exhibits low level, and a fourth AND gate 62 4 for outputting an output signal S 4 of high level when both the output signal D 1 of the first frequency dividing circuit 61 1 and the output signal D 2 of the second frequency dividing circuit 61 2 exhibit low level. The first outputting section 70 1 includes a first NAND gate 71 1 , a fifth AND gate 72 1 , a first NOR gate 73 1 , a first delay circuit 74 1 to which the output signal of the first NOR gate 73 1 is inputted, and a first clock driver 75 1 formed from a first PMOS transistor M p1 and a first NMOS transistor M n1 . The output signal of the first NAND gate 71 1 is inputted to the gate of the first PMOS transistor M p1 , and the source of the first PMOS transistor M p1 is connected to a power source voltage terminal 78. The output signal of the first NOR gate 73 1 is inputted to the gate of the first NMOS transistor M n1 , and the source of the first NMOS transistor M n1 is grounded. The drain of the first NMOS transistor M n1 is connected to the drain of the first PMOS transistor M p1 , and a first clock  1 is outputted from the junction between them. The second outputting section 70 2 , the third outputting section 70 3 , and the fourth outputting section 70 4 are each constructed similarly to the first outputting section 70 1 . The first NAND gate 71 1 of the first outputting section 70 1 negates the logical AND among the output signal S 1 of the first AND circuit 62 1 , the output signal of the second delay circuit 74 2 of the second outputting section 70 2 , the output signal of the third delay circuit 74 3 of the third outputting section 70 3 , and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The fifth AND gate 72 1 of the first outputting section 70 1 logically ANDs the output signal of the second delay circuit 74 2 of the second outputting section 70 2 , the output signal of the third delay circuit 74 3 of the third outputting section 70 3 , and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The first NOR gate 73 1 of the first outputting section 70 1 negates the logical OR between the output signal S 1 of the first AND circuit 62 1 and the output signal of the fifth AND gate 72 1 . The second NAND gate 71 2 of the second outputting section 70 2 negates the logical AND among the output signal S 2 of the second AND gate 62 2 , the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the third delay circuit 74 3 of the third outputting section 70 3 and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The sixth AND gate 72 2 of the second outputting section 70 2 logically ANDs the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the third delay circuit 74 3 of the third outputting section 70 3 and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The second NOR gate 73 2 of the second outputting section 70 2 negates the logical OR between the output signal S 2 of the second AND gate 62 2 and the output signal of the sixth AND gate 72 2 . The third NAND gate 71 3 of the third outputting section 70 3 negates the logical AND among the output signal S 3 of the third AND gate 62 3 , the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the second delay circuit 74 2 of the second outputting section 70 2 and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The seventh AND gate 72 3 of the third outputting section 70 3 logically ANDs the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the second delay circuit 74 2 of the second outputting section 70 2 , and the output signal of the fourth delay circuit 74 4 of the fourth outputting section 70 4 . The third NOR gate 73 3 of the third outputting section 70 3 negates the logical AND between the output signal S 3 of the third AND gate 62 3 and the output signal of the seventh AND gate 72 3 . The fourth NAND gate 71 4 of the fourth outputting section 70 4 negates the logical AND among the output signal S 4 of the fourth AND gate 62 4 , the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the second delay circuit 74 2 of the second outputting section 70 2 and the output signal of the third delay circuit 74 3 of the third outputting section 70 3 . The eighth AND gate 72 4 of the fourth outputting section 70 4 logically ANDs the output signal of the first delay circuit 74 1 of the first outputting section 70 1 , the output signal of the second delay circuit 74 2 of the second outputting section 70 2 , and the output signal of the third delay circuit 74 3 of the third outputting section 70 3 . The fourth NOR gate 73 4 of the fourth outputting section 70 4 negates the logical OR between the output signal S 4 of the fourth AND gate 62 4 and the output signal of the eighth AND gate 72 4 . The operation of the four-phase clock generation circuit 50 is described with reference to the timing chart shown in Fig. 9. The first frequency dividing circuit 61 1 outputs the output signal D 1 synchronized with the falling edge of the single-phase clock  and outputs the carrier signal C 0 synchronized with the rising edge of the single-phase clock . The second frequency driving circuit 61 2 outputs the output signal D 2 synchronized with the falling edge of the carrier signal C 0 . The output signal D 1 of the first frequency dividing circuit 61 1 changes from low level to high level when the single-phase clock  falls at time t 1 and then changes from high level to low level when the single-phase clock  falls again at time t 3 . The output signal D 1 of the first frequency dividing circuit 61 1 repeats the level variation for each two clock pulses of the single-phase clock . The carrier signal C 0 of the first frequency dividing circuit 61 1 changes from low level to high level when the single-phase clock  rises at time t 2 , and then changes from high level to low level when the single-phase clock  falls at time t 3 . The carrier signal C 0 of the first frequency dividing circuit 61 1 repeats the level variation for each two clock pulses of the single-phase clock . The output signal D 2 of the second frequency driving circuit 61 2 changes from low level to high level when the carrier signal C 0 falls at time t 3 and then changes from low level to high level when the carrier signal C 0 falls again at time t 4 . The output signal D 2 of the second frequency driving circuit 61 2 repeats the level variation for each two clock pulses of the carrier signal C 0 , that is, for each four clock pulses of the single-phase clock . As a result, as the logical ANDs between the output signal D 1 of the first frequency dividing circuit 61 1 and the output signal D 2 of the second frequency driving circuit 61 2 are calculated individually by the first to fourth AND gates 62 1 -62 4 as described above, the output signals S 1 -S 4 which have a high-level period equal to one period of the single-phase clock  and are successively displaced from each other by one clock distance (the period of one clock pulse) of the single-phase clock  as shown in Fig. 9 are outputted. It is assumed that at time t 0 shown in Fig. 9, first to third clocks  1 - 3 all exhibit low level while the fourth clock  4 exhibits high level. When the single-phase clock  falls at time t 1 , the output signal D 1 of the first frequency dividing circuit 61 1 changes from low level to high level, whereby the output signal S 3 of the third AND gate 62 3 changes from low level to high level and the output signal S 4 of the fourth AND gate 62 4 changes from high level to low level. Nevertheless, the output signal S 1 of the first AND circuit 62 1 and the output signal S 2 of the second AND gate 62 2 remain at low level. As a result, when the output signal S 4 of the fourth AND gate 62 4 changes to low level, the output signal of the fourth NAND gate 71 4 of the fourth outputting section 70 4 changes from low level to high level, and consequently, the fourth PMOS transistor M p4 constituting the fourth clock driver 75 4 is turned OFF. At time t 1 , the three input signals to the eighth AND gate 72 4 of the fourth outputting section 70 4 , that is, the output signal of the first delay circuit 74 1 , the output signal of the second delay circuit 74 2 , and the output signal of the third delay circuit 74 3 , all exhibit high level, and consequently, the output signal of the eighth AND gate 72 4 exhibits high level. As a result, the output signal of the fourth NOR gate 73 4 exhibits low level, and the fourth NMOS transistor M n4 constituting the fourth clock driver 75 4 is OFF. However, when the output signal S 3 of the third AND gate 62 3 changes to high level at time t 1 , the output signal of the third NOR gate 73 3 of the third outputting section 70 3 changes to low level. Since the output signal of the third NOR gate 73 3 is inputted to the eighth AND gate 72 4 of the fourth outputting section 70 4 by way of the third delay circuit 74 3 , the output signal of the eighth AND gate 72 4 changes to low level after the delay time dt 3 of the third delay circuit 74 3 from time t 1 . Accordingly, at time t 1 +dt 3 , the output signal S 4 of the fourth AND gate 62 4 and the output signal of the eighth AND gate 72 4 , which are the two input signals to the fourth NOR gate 73 4 , both change to low level, and the output signal of the fourth NOR gate 73 4 consequently changes from low level to high level and the fourth NMOS transistor M n4 constituting the fourth clock driver 75 4 is turned ON. As a result, the fourth clock  4 outputted from the fourth clock driver 75 4 changes from high level to low level. Consequently, with the four-phase clock generation circuit 50, a period within which the output impedance of the fourth delay circuit 74 4 exhibits high level can be assured for the delay time dt 3 of the third delay circuit 74 3 immediately before the falling edge of the fourth clock  4 . Since the output signal of the fourth delay circuit 74 4 among the three input signals to the seventh AND gate 72 3 of the third outputting section 70 3 is at low level before time t 1 , the output signal of the seventh AND gate 72 3 is at low level. Since the output signal S 3 of the third AND gate 62 3 is also at low level, the output signal of the third NOR gate 73 3 is at high level, and the third NMOS transistor M n3 constituting the third clock driver 75 3 is ON. However, when the output signal S 3 of the third AND gate 62 3 changes to high level at time t 1 , the output signal of the third NOR gate 73 3 changes to low level, and consequently, the third NMOS transistor M n3 constituting the third clock driver 75 3 is turned OFF. On the other hand, when the output signal S 3 of the third AND gate 62 3 changes to high level at time t 1 , only the output signal of the fourth delay circuit 74 4 among the four input signals to the third NAND gate 71 3 of the third outputting section 70 3 changes to low level. Although the output signal of the fourth NOR gate 73 4 of the fourth outputting section 70 4 changes from low level to high level at time t 1 +dt 3 as described above, since the output signal of the fourth NOR gate 73 4 is inputted to the third NAND gate 71 3 by way of the fourth delay circuit 74 4 , the four input signals to the third NAND gate 71 3 all change to high level after the delay time dt 4 of the fourth delay circuit 74 4 from time t 1 +dt 3 . As a result, at time t 1 +dt 3 +dt 4 , the output signal of the third NAND gate 71 3 changes from high level to low level, the third PMOS transistor M p3 constituting the third clock driver 75 3 is turned ON, and the third clock  3 outputted from the third clock driver 75 3 changes from low level to high level. Consequently, with the four-phase clock generation circuit 50, a period within which the output impedance of the third delay circuit 74 3 exhibits high level can be assured for the delay time of the sum dt 3 +dt 4 of the delay time dt 3 of the third delay circuit 74 3 and the delay time dt 4 of the fourth delay circuit 74 4 immediately before the rising edge of the third clock  3 . Similarly, with the four-phase clock generation circuit 50, a period within which the output impedance of the third clock driver 75 3 exhibits high level can be assured for the delay time dt 2 of the second delay circuit 74 2 immediately before the falling edge of the third clock  3 as shown by slanting lines in Fig. 9; another period within which the output impedance of the second clock driver 75 2 exhibits high level can be assured for the delay time sum dt 2 +dt 3 of the delay time dt 2 of the second delay circuit 74 2 and the delay time dt 3 of the third delay circuit 74 3 immediately before the rising edge of the second clock  2 ; a further period within which the output impedance of the second clock driver 75 2 exhibits high level can be assured by the delay time dt 1 of the first delay circuit 74 1 immediately before the falling edge of the second clock  2 ; a still further period within which the output impedance of the first clock driver 75 1 exhibits high level can be assured for the delay time sum dt 1 +dt 2 of the delay time dt 1 of the first delay circuit 74 1 and the delay time dt 2 of the second delay circuit 74 2 immediately before the rising edge of the first clock  1 ; a yet further period within which the output impedance of the first clock driver 75 1 can be assured by the delay time dt 4 of the fourth delay circuit 74 4 immediately before the falling edge of the first clock  1 ; and a yet further period within which the output impedance of the fourth clock driver 75 4 exhibits high level can be assured by the delay time sum dt 4 +dt 1 of the delay time dt 4 of the fourth delay circuit 74 4 and the delay time dt 1 of the first delay circuit 74 1 immediately before the rising edge of the fourth clock  4 . It is to be noted that, while a detailed description is omitted, where the frequency dividing circuits of the inputting section are provided by three stages, an eight-phase clock signal can be generated with a similar construction to that of the four-phase clock generation circuit 50. A two-phase clock generation circuit 200 according to the fourth embodiment of a polyphase clock generation circuit of the present invention is different from the two-phase clock generation circuit 10 shown in Fig. 4 in that, as shown in Fig. 10, it includes a delay time setting section in place of the first delay circuit 16 and the second delay circuit 17. Here, the delay time setting section includes first to fourth delay circuits 231 1 -231 4 connected in series to each other, first to fourth transfer gates 232 1 -232 4 interposed between an output terminal of a first NOR gate 213 and the input terminals of the first to fourth delay circuits 231 1 -231 4 , respectively, fifth to eighth delay circuits 231 5 -231 8 connected in series to each other, fifth to eighth transfer gates 232 5 -232 8 interposed between an output terminal of a second NOR gate 215 and the input terminals of the fifth to eighth delay circuits 231 5 -231 8 , respectively, a delay controlling register 23 5 into which are stored delay control data constituted from an upper bit D 1 and a lower signal D 2 , a first delay controlling inverter 236 1 for inverting the polarity of the upper bit D 1 of the delay control data outputted from the delay controlling register 235, a second delay controlling inverter 236 2 for inverting the polarity of the lower bit D 2 of the delay control data outputted from the delay controlling register 235, and first to fourth delay controlling NOR gates 237 1 -237 4 . Here, the output signal DS 1 of the first delay circuit 231 1 is inputted to a second NAND gate 214 and a second NOR gate 215. The output signal DS 2 of the fifth delay circuit 231 5 is inputted to a first NAND gate 212 and the first NOR gate 213. Meanwhile, the first delay controlling NOR gate 237 1 turns ON the first transfer gate 232 1 and the fifth transfer gate 232 5 when both the upper bit D 1 and the lower bit D 2 of the delay control data inputted thereto from the delay controlling register 235 exhibit low level. The second delay controlling NOR gate 237 2 turns ON the second transfer gate 232 2 and the sixth transfer gate 232 6 when the upper bit D 1 of the delay control data inputted thereto from the delay controlling register 235 and an inverted signal of the lower bit D 2 of the delay control data inputted thereto from the second delay controlling inverter 236 2 both exhibit low level. The third delay controlling NOR gate 237 3 turns ON the third transfer gate 232 3 and the seventh transfer gate 232 7 when both an inverted signal of the upper bit D 1 of the delay control data inputted thereto from the first delay controlling inverter 236 1 and the lower bit D 2 of the delay control data inputted thereto from the delay controlling register 235 exhibit low level. The fourth delay controlling NOR gate 237 4 turns ON the fourth transfer gate 232 4 and the eighth transfer gate 232 8 when both the inverted signal of the upper bit D 1 of the delay control data inputted thereto from the first delay controlling inverter 236 1 and the inverted signal of the lower bit D 2 of the delay control data inputted thereto from the second delay controlling inverter 236 2 exhibit low level. The operation of the two-phase clock generation circuit 200 will next be described on the assumption that the delay times of the first to eighth delay circuits 231 1 -231 8 are all equal to "dt". In the two-phase clock generation circuit 200, when delay control data in which upper bit D 1 and lower bit D 2 both exhibit low level are stored into the delay controlling register 235, only the output signal of the first delay controlling NOR gate 237 1 changes to high level, and consequently, the first transfer gate 232 1 and the fifth transfer gate 232 5 are turned ON. As a result, the output signal DS 1 of the first delay circuit 231 1 inputted to the second NAND gate 214 and the second NOR gate 215 is a signal obtained by delaying the output signal of the first NOR gate 213 by the delay time dt since it is provided as the output signal of the first NOR gate 213 after passing the first transfer gate 232 1 and the first delay circuit 231 1 . Meanwhile, the output signal DS 2 of the fifth delay circuit 231 5 inputted to the first NAND gate 212 and the first NOR gate 213 is a signal obtained by delaying the output signal of the second NOR gate 215 by the delay time dt since it is provided as the output signal of the second NOR gate 215 after passing the fifth transfer gate 232 5 and the fifth delay circuit 231 5 . On the other hand, when delay control data wherein the upper bit D 1 has low level and the lower bit D 2 has high level are stored into the delay controlling register 235, only the output signal of the second delay controlling NOR gate 237 2 changes to high level, and consequently, the second transfer gate 232 2 and the sixth transfer gate 232 6 are turned ON. As a result, the output signal DS 1 of the first delay circuit 231 1 inputted to the second NAND gate 214 and the second NOR gate 215 is a signal obtained by delaying the output signal of the first NOR gate 213 by the delay time "2 x dt" since it is provided as the output signal of the first NOR gate 213 after passing the second transfer gate 232 2 , the second delay circuit 231 2 , and the first delay circuit 231 1 . In the meantime, the output signal DS 2 of the fifth delay circuit 231 5 inputted to the first NAND gate 212 and the first NOR gate 213 is a signal obtained by delaying the output signal of the second NOR gate 215 by the delay time "2 x dt" since it is provided as the output signal of the second NOR gate 215 signal after passing the sixth transfer gate 232 6 , the sixth delay circuit 231 6 , and the fifth delay circuit 231 5 . Further, when delay control data wherein the upper bit D 1 has high level and the lower bit D 2 has low level are stored into the delay controlling register 235, only the output signal of the third delay controlling NOR gate 237 3 changes to high level, and consequently, the third transfer gate 232 3 and the seventh transfer gate 232 7 are turned ON. As a result, the output signal DS 1 of the first delay circuit 231 1 inputted to the second NAND gate 214 and the second NOR gate 215 is a signal obtained by delaying the output signal of the first NOR gate 213 by the delay time "3 x dt" since it is provided as the output signal of the first NOR gate 213 after passing the third transfer gate 232 3 , the third delay circuit 231 3 , the second delay circuit 231 2 , and the first delay circuit 231 1 . On the other hand, the output signal DS 2 of the fifth delay circuit 231 5 inputted to the first NAND gate 212 and the first NOR gate 213 is a signal obtained by delaying the output signal of the second NOR gate 215 by the delay time "3 x dt" since it is provided as the output signal of the second NOR gate 215 after passing the seventh transfer gate 232 7 , the seventh delay circuit 231 7 , the sixth delay circuit 231 6 , and the fifth delay circuit 231 5 . Meanwhile, when delay control data wherein the upper bit D 1 and the lower bit D 2 both have high level are stored into the delay controlling register 235, only the output signal of the fourth delay controlling NOR gate 237 4 changes to high level, and consequently, the fourth transfer gate 232 4 and the eighth transfer gate 232 8 are turned ON. As a result, the output signal DS 1 of the first delay circuit 231 1 inputted to the second NAND gate 214 and the second NOR gate 215 is a signal obtained by delaying the output signal of the first NOR gate 213 by the delay time "4 x dt" since it is provided as the output signal of the first NOR gate 213 after passing the fourth transfer gate 232 4 , the fourth delay circuit 231 4 , the third delay circuit 231 3 , the second delay circuit 231 2 , and the first delay circuit 231 1 . Meanwhile, the output signal DS 2 of the fifth delay circuit 231 5 inputted to the first NAND gate 212 and the first NOR gate 213 is a signal obtained by delaying the output signal of the second NOR gate 215 by the delay time "4 x dt" since it is provided as the output signal of the second NOR gate 215 after passing the eighth delay circuit 231 8 , the seventh delay circuit 231 7 , the sixth delay circuit 231 6 , and the fifth delay circuit 231 5 . Accordingly, with the two-phase clock generation circuit 200, the delay times of the first delay circuit 16 and the second delay circuit 17 shown in Fig. 4 can be set to four different delay times. It is to be noted that, by setting the number of bits of the delay control data to be stored into the delay controlling register 235 to "n" and setting the number of stages of two sets of delay circuits to "2 n ", "2 n " different delay times can be set. For example, when the voltage is as low as, for example, 3 V (that is, in low-speed operation), the waveforms of rising edges and falling edges of the first and second clocks  1 and  2 become deformed as seen from Fig. 11 due to an influence of the capacitance of several elements beginning with first and second drivers 218 and 219. In this instance, if the delay times of the first and second delay times 16 and 17 are fixed as in the two-phase clock generation circuit 10 shown in Fig. 4, a period within which the first clock  1 and the second clock  2 are both active (that is, a period within which they are at high level) is present, and consequently, where the first and second clocks  1 and  2 are used as latching clocks for latches, for example, of the master-slave configuration, a malfunction such as direct transmission of data occurs. On the other hand, when the voltage is as high as, for example, 5 V (that is, in high-speed operation), the deformation of the waveforms of rising and falling edges of the first and second clocks  1 and  2 is limited as shown in Fig. 12. However, if the delay between clocks defined by the time from the falling edge of the second clock  2 to the rising edge of the first clock  1 or the time from the falling edge of the first clock  1 to the rising edge of the second clock  2 is set to an excessively great value, the period of high level of the first or second clock  1 or  2 then becomes excessively short, and therefore, if the first and second clocks  1 and  2 are used as latching clocks for latches of, for example, the master-slave configuration, problems such as failure to latch data may occur. However, with the two-phase clock generation circuit 200 shown in Fig. 10, the above-described problem can be prevented by changing delay control data to be stored into the delay controlling register 235 so that, when the voltage is low, the delay between clocks may be increased, but when the voltage is high, the delay between clocks may be decreased. It is to be noted that, in the two-phase clock generation circuit 200, while the delay between clocks is set in accordance with delay control data stored into the delay controlling register 235, the delay between clocks can be set otherwise by inputting delay control data from an external terminal. Further, as with the four-phase clock generation circuit 50 shown in Fig. 8, the delay between clocks can be set arbitrarily by making the delay times of the first to fourth delay circuits 74 1 to 74 4 variable. While the present invention has been described in conjunction with preferred embodiments thereof, it will now be possible for one skilled in the art to easily put the present invention into practice in various other manners, within the scope of the appended claims.

Claims: A polyphase clock generation circuit for generating first and second clock signals (Ø1 ∼ Ø2) having different phases with each other, comprising: converting means (11) for converting a single phase clock signal (Ø) inputted into first and second different phase clock signals (Ø, Ø); first and second clock driver means (18, 19) for respectively outputting one of the generated clock signals (Ø1, Ø2) and each including a pair of field effect transistors, one of a P-channel type (Mp) and one of an N-channel type (Mn), the P-channel field effect transistor (Mp) being with a source connected to a power source voltage terminal (20), and the N-channel field effect transistor (Mn) being with a source connected to a power source lower terminal (ground) and with a drain connected with a drain of said P-channel field effect transistor (Mp) and to the output terminal of each clock driver means; first and second clock driver driving means (12∼17) for respectively driving said first and second clock diver means (18, 19) to output each of the generated clock signals alternately and separately of each other, so that the clock signals of different phases may not have an ON-state simultaneously with each other, and each including a set of logical gate means (12∼15) and delay means (16, 17) for each phase of the generated clocks respectively; wherein each set of logical gate means and delay means of a clock driver driving means comprises: an NAND gate (12, 14) for performing NAND operation of one of said different phase clock signals (Ø, Ø') supplied thereto and the output signal of the delay means (17, 16) of the set of gate means and delay means of the other clock driver diving means (19, 18), and for outputting a control signal to a gate of the P-channel field effect transistor (Mp) of the respective clock driver means (18, 19); a NOR gate (13, 15) for NOR operation of the same signals as inputted to the NAND gate (12, 14) and for outputting a control signal to a gate of the N-channel field effect transistor (Mn) of the respective clock driver means (18, 19; 75s; 218, 219); said delay means (16, 17) for delaying the output signal of the NOR gate (12, 14) exclusively, and for outputting a signal to the input of both of the NAND gate and the NOR gate of the logical gate set of the other clock driver driving means. A polyphase clock generation circuit for generating first and second clock signals (Ø1 ∼ Ø2) having different phases with each other, comprising: converting means for converting a single phase clock signal (Ø) inputted into first and second different phase clock signals (Ø, Ø'); first and second clock driver means (38, 39) for respectively outputting each of the generated clock signals (Ø1, Ø2) and each including a pair of field effect transistors, one of a P-channel type (Mp) and one of an N-channel type (Mn), the P-channel field effect transistor (Mp) being with a source connected to a power source voltage terminal (40), and the N-channel field effect transistor (Mn) being with a source connected to a power source lower terminal (ground) and with a drain connected with a drain of said P-channel field effect transistor (Mp) and to the output terminal of each clock driver means; first and second clock driver driving means (32∼37) for respectively driving said first and second clock driver means (38, 39) to output each of the generated clock signals alternately and separately of each other, so that the clock signals of different phases may not have an ON-state simultaneously with each other, and each including a set of logical gate means (32-35) and delay means (36, 37) for each phase of the generated clocks respectively; wherein each set of logical gate means and delay means of a clock driver driving means comprises: an NAND gate (32, 34) for performing NAND operation of one of said different phase clock signals (Ø, Ø') supplied thereto and the output signal of the delay means (37, 36) of the set of gate means and delay means of the other clock driver driving means (39, 38), and for outputting a control signal to a gate of the P-channel field effect transistor (Mp) of the respective clock driver means (38, 39); a NOR gate (33, 35) for NOR operation of the same signals as inputted to the NAND gate (32, 34) and for outputting a control signal to a gate of the N-channel field effect transistor (Mn) of the respective clock driver means (38, 39); said delay means (36, 37) for delaying the output signal of the NAND gate (32, 34) exclusively, and for outputting a signal to the input of both of the NAND gate and the NOR gate of the logical gate sets of the other clock driver diving means. A polyphase clock generation circuit, comprising: frequency dividing means (60) for dividing a frequency of a single phase clock (Ø) to produce a plurality of divided frequency signals (S1 ∼ S4) each having a period high level which does not overlap with others; and a plurality of outputting means (70s), each of which is associated with a respective divided frequency signal (S1-S4) and includes logical NAND means (71s), logical AND means (72s), logical NOR means (73s), delay means (74s) for delaying the output signal of the logical NOR means (73s) by a specific delay time, and a clock driver (75s) having a P-channel field effect transistor (Mps) with a source connected to a terminal of power source voltage (78), and an N-channel field effect transistor (Mns) with a source connected to a second power source terminal (ground), and a drain connected to a drain of the P-channel field effect transistor (Mps) for outputting a clock signal (Ø1-Ø4); wherein, for each outputting means (70s), the output signal of the logical NAND means (71s) is inputted to a gate of the P-channel field effect transistor (Mps), and the output signal of the logical NOR means (73s) is inputted to a gate of the N-channel field effect transistor (Mns); the associated one of the divided frequency signals (Ss) generated by the frequency dividing means (60) and the output signals of the delay means (74s) included in the plurality of outputting means (70s), except for the delay means in the respective outputting means, are inputted to the logical NAND means (71s); the output signals of the delay means (74s) included in the plurality of outputting means (70s), except for the delay means in the respective outputting means are inputted to the logical AND means (72s); and the associated one of the divided frequency signals (Ss) generated by the frequency dividing means (61, 62) and the output signal of the logical AND means (72s) are inputted to the logical NOR means (73s) the one of the plurality of outputting means. A polyphase clock generation circuit as claimed in claim 3, wherein said delay means (74s) includes delay time setting means (235, 236, 237) for setting each delay time.

Inventors: HIKICHI HIROSHI, HIRATSUKA KOICHI, HIKICHI, HIROSHI, HIRATSUKA, KOICHI, HIKICHI, HIROSHI, C/O NEC CORPORATION, HIRATSUKA, KOICHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03K5
IPC codes: H03K5