BiCMOS output driver circuit

Abstract: A BiCMOS power driver circuit for interfacing to a bus comprises means (Q1) for channelling current from a power source to the base of a bipolar device (Q2) to pull the output all the way down to within a bipolar V SAT voltage drop of ground, and then uses feedback (U,M3) to turn-off the pull-down circuit to conserve power. A similar circuit functions to provide Incident Wave Switching and Glitch Suppression by monitoring the voltage level at the output and sinking current as necessary to maintain a low logic level.

Description: This invention relates to combined field effect and bipolar transistor circuits, and in particular to such circuits used as logic circuits for interfacing to another circuit, typically a bus. Such a circuit is shown in U.S. Patent 4,713,561 which shows an electronic circuit comprising means for restricting collector saturation of an output transistor. The invention relates to an electronic circuit comprising a BiCMOS driver circuit, the driver having a CMOS input device; a first bipolar transistor having a base, a collector connected to a driver output, and an emitter connected to a reference voltage node; a second bipolar transistor having a base connected to an output of the CMOS input device, an emitter connected to the base of the first bipolar transistor, and a collector coupled to a supply voltage node; means for restricting the first bipolar transistor being driven into saturation. BACKGROUND OF INVENTION Logic circuits for interfacing to a bus within a larger system, such as a CPU or a PC, are well known. As system performance has increased, the trend has been toward using combined complementary MOS (CMOS) and bipolar transistors, commonly known as BiCMOS. The major advantages are high speed and reduced power dissipation. In the typical BiCMOS circuit, CMOS devices form the input and the bipolar devices form the output. A commercially available family of such devices from Philips Components-Signetics is known as the ABT Advanced BiCMOS Interface Logic. All of the devices in this family will operate generally with a 5 volt DC supply voltage source. Usually, the circuit output is directly or indirectly connected to a bus common to a number of other circuits, and the input is derived from a part of the CPU or a peripheral device. The significant point is that, during operation, the bus voltage swings between the voltage source, typically 5 volts, and a reference voltage, such as ground, and these transitions are interpreted as signals by interface circuits connected to the bus. A traditional zero-static power BiCMOS driver creates a high-to-low transition by channelling current from the driver output into the base of a pull-down bipolar transistor. This configuration is automatically zero-static power because the pull-down transistor starts turning off as the output is pulled towards a bipolar base-emitter drop V BE above ground, but the bipolar device cannot pull the output all the way to ground. Typically, an NMOS device is added to pull the output the rest of the way down. Unless a very large NMOS device consuming valuable semiconductor real estate is used, however, the last volt or so of the high-to-low transition takes a relatively long time, which depends on the load. This is undesirable for many applications. Two attributes of desirable bus drivers are Incident Wave Switching and Glitch Suppression. Incident Wave Switching is a property of transmission lines. When the logic level on one side of a transmission line is switched, an electrical wave equal to some fraction of the total charge is launched onto the line. After some time, the line settles into the new state. Incident Wave Switching means that a valid logic level is attained with the first, or incident, electrical wave launched onto the line, thereby saving time for the bus user. Glitch Suppression is the ability of the bus driver to maintain the integrity of a logic level on the bus. This is desirable because noise on the bus may disrupt the operation of the driver. Known driver circuits allow Incident Wave Switching by sinking large bus currents quickly to ground. A problem, however, is that, with known circuits, under certain load conditions, the circuit reacts too quickly to sink large currents from the output. The undesired result of this is that ringing, or noise, is created, which can interfere with the proper operation of the driver circuit. Furthermore, these circuits generally do not have high current-sinking capability at low output voltages. SUMMARY OF INVENTION An object of the invention is an improved output driver circuit. To this end, the circuit of the invention is characterized in that means comprises a diode means for supplying a current from the base of the second bipolar transistor to the driver output, wherein the diode means comprises a pn-diode having an anode connected to the base of the second bipolar transistor and a Schottky diode having an anode connected to a cathode of the pn-diode and having a cathode connected to the driver output. The diode means serves to suppress glitches since it is turned off as soon as the output voltage increases above a predetermined level. Accordingly, the circuit of the invention is particularly advantageous when employed as a low noise BiCMOS bus interface circuit. The circuit is a low-noise BiCMOS driver with high current-sinking capability to serve as a Glitch Suppressor and to provide Incident Wave Switching of the driver circuit. Ringing is substantially prevented by monitoring a voltage node or the driver output and sinking current as necessary to maintain a low logic level at the output by draining current quickly, but not so quickly as to cause significant ringing. For a better understanding of the invention, its operating advantages and specific objects attained by its use, reference should be had to the accompanying drawings and descriptive matter in which there are illustrated and described the preferred embodiments of the invention. SUMMARY OF DRAWINGS In the drawings: Fig 1. shows a schematic of a simplified view of a conventional BiCMOS pull-down driver; Fig 2 shows a schematic of one form of zero-static-power pull-down driver; Figs. 3 and 5 each show a schematic of variant circuits in accordance with the basic circuit shown in Fig. 2; Figs. 4 and 6 show a schematic of an output driver circuit in accordance with the invention; Fig. 7 shows another output driver circuit in accordance with the invention; In the circuits described below, similar references designate similar elements. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The conventional BiCMOS pull-down circuit shown in Fig. 1 comprises a PFET M1 and an NFET M2, whose gates are connected in parallel to input IN. Their common drain-source node is connected to the base of an N-type bipolar transistor Q1, whose collector is connected to the output OUT, which is connected, directly or indirectly, to a bus (not shown here) to which other interface circuits are similarly connected, or to another stage. The operating DC power supply is also not shown. The BiCMOS pull-down circuit shown in Fig. 1, in response to an input signal, channels current from the output to the base of Q1 in order to create a high-to-low transition. As a consequence, Q1 shuts off before the output is pulled lower than a bipolar base-emitter drop V BE , typically 0.7 Volts, above ground. Typically, a small NFET (not shown here) is used in parallel with the traditional BiCMOS pull-down to "trickle" the output the rest of the way to ground. Generally, this structure guarantees a steep transition down to about a volt or so, after which the transition may slow dramatically, depending on the output load. This can result in slow propagation delays and potentially cause leakages in the next stage, by not switching subsequent circuit stages crisply. Fig. 2 shows one form of fully-powered, zero-static power pull-down driver which improves upon the traditional circuit by providing steady pull-down current throughout the high-to-low transition. This is done by channelling current from Vcc to the base of the bipolar transistor Q2, which can therefore pull the output all the way down to a bipolar voltage drop V SAT , being the saturation collector-emitter voltage, typically 0.2 Volts, above ground. The driver of Fig. 2 uses feedback designated 20 from the output to turn off the pull-down circuit after a full high-to-low transition to maintain zero-static power. This is achieved by a PFET M3 in series with M1 and M2, and connecting a gate of M3 via an inverter U1 to the output. In operation, prior to a high-to-low transition, both the input and output of the circuit are high. In this state, transistors Q1 and Q2 are off, FET M1 is off and FETS M2, M3 and M4 (which acts to pull charge from the base of Q2) are on. When the input goes active low, M2 and M4 turn off and M1 turns on, turning on the Darlington formed by Q1 and Q2. When Q2 pulls the output below the threshold of inverter U1, U1 switches, turning off M3, rendering the circuit zero-static power. Due to the propagation delay through U1 and the charge stored in the bases of Q1 and Q2, the output is pulled all the way to within a V SAT of ground. The Darlington structure is significant for two reasons: first, since Q1 can be a very small device and still drive a large Q2, it has a low base capacitance and can be turned on rapidly by even a small M1; second, Q1 will "overcharge" the base of Q2 -- the charge remaining in the base of Q2 will insure that the output is pulled all the way down to a V SAT even after M3 turns off. The circuit in Figure 2 risks driving Q2 deep into saturation, however. This could slow the recovery, or shut-off time of the circuit, and thus decrease the maximum operating frequency. There are two convenient methods of protecting the transistors from deep saturation. The first method is shown in Figure 3, where the collector of Q1 is tied to the output rather than to Vcc. As the output voltage decreases, the current channelled to Q2 from Q1 (and therefore the likelihood of Q2 saturating) also decreases. Generally, however, Q2 should still pull the output down to a bipolar V SAT . The second method, in accordance with the invention, of protecting the transistors from deep saturation is shown in Figure 4. The PN junction diode D1 and Schottky diode D2 provide a means to drain the current from the base of Q1 once the output voltage has dropped below approximately 0.2 volt. This shuts off Q1 and protects Q2 from saturating. A further description of this operation can be found below in connection with the description of Fig. 6. The circuit shown in Figure 5 can also be considered a variant of the circuit shown in Figure 2, but it lacks the advantages of the Darlington configuration. It does not provide as much gain, nor can it be guaranteed to pull the output all the way down before being shut off by the feedback 20 from the output. Figure 4 also shows one of several minor variations to the circuit; using in the feedback circuit 20' an NFET M3' instead of the P-channel/inverter combination gives the same functional result, except that M3 would turn off sooner with no delay through the inverter stage inverter. Other variations include: (1) Using Schottky clamped transistors for Q1 and Q2, and (2) Stacking inverting stages to drive M3. This increases the shut-off delay for the circuit. The foregoing circuits provided feedback from the output to a FET switch connected to the CMOS input, which has channelled current from the DC voltage source, Vcc, to turn on a bipolar transistor to pull-down the output voltage all the way to within a V SAT voltage drop from ground, in order to turn-off the FET switch to minimize power dissipation. In the next series of embodiments, similar arrangements perform other functions. Fig. 6 shows one form of circuit configuration for a current-sink-on-demand output driver circuit according to the invention. The circuit comprises a BiCMOS arrangement of CMOS input comprising a PFET M1 and an NFET M2, whose source-drain electrodes are connected in series between a DC voltage supply Vcc and ground. Input signals represented by IN are applied to the CMOS gates in parallel. The CMOS output is connected to the base electrode of an NPN bipolar transistor Q1, whose collector is connected to Vcc, and whose emitter is connected via NFET M4 to ground, with the NFET M4 gate also being driven by the input signal. Also connected to the Q1 emitter is the base of a second NPN bipolar transistor Q2, whose emitter is grounded, and whose collector is connected to the output, OUT. Also connected between the output and the Q1 base are two serial-connected diodes D1 and D2. The first, D1, is a PN junction diode; the second, D2, is a Schottky diode. Both diodes are poled with their negative terminal connected to the output. During normal operation of this circuit, the input IN will be driven low which allows the bases of Q1 and Q2 to be charged via M1. As long as the output voltage OUT is greater than 0.2 volts (V D1 + V D2 + V OUTPUT > V BE1 + V BE2 ), the diodes are effectively off and transistors Q1 and Q2 remain on. When the output voltage falls below 0.2 volts (V BE1 + V BE2 > V D1 + V D2 + V OUTPUT ), the diodes become forward biased and drain current from the base of transistor Q1, lowering its base voltage to approximately 1.2 volts (V D1 + V D2 ), so that it no longer provides current to the base of Q2, and thereby effectively disables Q2's operation. The transistors will remain off until the output voltage is forced above 0.2 volts. The circuit shown in Fig. 6 allows Incident Wave Switching by sinking large bus currents quickly to ground. The current sink may be sized to pull transmission line potentials down to 0.8 volts, the valid logic-low level, for various loads. The circuit acts as a Glitch Suppressor since any bus voltage greater than 0.2 volts will shut the diodes off, thereby re-activating the transistors Q1 and Q2, which will pull the bus voltage back down with much greater gain than traditional circuits. As long as the resistance through FET M1 is high, the static current drain necessary to operate the current sink remains low. The circuit as shown is connected to a bus 30, to which other driver circuits 31, 32 may be connected. The basic circuit shown in Figure 6 has one disadvantage. When the input is driven low the circuit is active instantly, and quickly sinks large currents from the output. The result is ringing, or noise, about ground potential. This is undesirable, because it means that the bus voltage fluctuates until the ringing stops, which will increase the bus settling time. Fig. 7 shows the same circuit but modified to reduce or eliminate the ringing. In the improved circuit, a feedback circuit referenced 40 is added in parallel with the original current sink circuit designated 41. The feedback circuit 40 comprises two serial-connected inverters U1, U2 connected between the output and the gate of a PFET M3 whose source-drain is connected in series with the source-drains of M1 and M2. A pull-down circuit 50 is used to initially draw the output voltage down. However, the circuit 50 generally has little or no current sinking ability at low voltages. The inverters, U1 and U2 keep the high-current sink circuit 41 off until the output voltage drops below the threshold V TH of U2. U2 changes to a logic high, U1 changes low, activating M3, which in turn activates the circuit 41. The hand-off between the pull-down circuit 50 and the current sink circuit 41 drains bus current quickly, but gently, thereby causing very little noise and substantially no ringing. The pull-down circuit 50 can be one of the circuits of Figs. 2-5. All of the foregoing circuits are implemented as ICs, and the addition of the added components and the feedback circuits add very little extra cost. The current-sink-on-demand output driver of Fig. 7 may be modified in two ways: (1) Using Schottky-clamped transistors Q1 and Q2. This helps keep the transistors Q1 and Q2 from saturating, which increases the operating frequency. The disadvantages of this method are the extra capacitance at the bases of the transistors, which slow the turn-on times. (2) Using some other combination of diodes to adjust the circuit's shut-off threshold. Any number of any diodes may be used to modify the actual shut-off threshold. The diodes used may include Zener, Schottky, PN-Junction, and diode-connected MOS clamps. However, the optimum operating threshold is slightly lower than the voltage drop of the transistors Q1 and Q2. As is clear, the term "CMOS" indicates any logic circuitry comprising filed effect transistors (FETs) of complementary conductivity type that function complementarily when supplied in parallel with an input signal.

Claims: An electronic circuit comprising a BiCMOS driver circuit, the driver having a CMOS input device (M1,M2); a first bipolar transistor (Q2) having a base, a collector connected to a driver output, and an emitter connected to a reference voltage node; a second bipolar transistor (Q1) having a base connected to an output of the CMOS input device, an emitter connected to the base of the first bipolar transistor (Q2), and a collector coupled to a supply voltage node; means for restricting the first bipolar transistor (Q2) being driven into saturation; characterized in that the means comprises a diode means (D1,D2) for supplying a current from the base of the second bipolar transistor (Q1) to the driver output, wherein the diode means (D1,D2) comprises a pn-diode (D1) having an anode connected to the base of the second bipolar transistor (Q1) and a Schottky diode having an anode connected to a cathode of the pn-diode (D1) and having a cathode connected to the driver output.

Inventors: MARTIN BRIAN, MARTIN, BRIAN, MARTIN, BRIAN, C/O INT. OCTROOIBUREAU B.V.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1994
Main classification: H03K19
IPC codes: H03K17, H03K19