Digital to analog converter

Abstract: A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.

Description: This invention is concerned with digital to analog converters. More particularly, it is concerned in one aspect with improving the architecture of segmented digital to analog converters and in another aspect with providing digital to analog converters having an analog output voltage which is a monotonic function of a digital input word. A digital to analog converter (DAC) having a segmented structure typically operates by dividing a digital input word into subwords which control different parts of the DAC circuit. For example, a digital input word might be divided into a more significant (MS) subword and a less significant (LS) subword, the MS subword being used to generate a first intermediate current or voltage signal that is summed with a second intermediate current or voltage signal generated responsive to the LS subword. Such segmented structures are particularly useful for reducing the number of resistive elements required to provide a DAC with high resolution (e.g., 12 bits). However, summing the intermediate signals without buffering the outputs of the signal generating circuits may subject the outputs of the signal generating circuits to excessive load conditions. On the other hand, adding such buffering to the output of each signal generating circuit typically introduces noise and adds to the cost and complexity of the DAC. Another potential problem which can be exacerbated by providing a buffer at the output of each signal generating circuit is non-monotonicity in the transfer characteristics of the DAC. In an ideal digital to analog converter (DAC), the analog output voltage should be a monotonic function of the digital input; that is, an increase in the digital input should lead to an increase in the analog output voltage, and a decrease in the digital input should lead to a decrease in the analog output voltage. Monotonicity is vital in many applications such as in control systems where non-monotonic DACs can create serious problems. In many practical cases, however, due to unavoidable component inaccuracies in the DACs, monotonicity is not always obtained. Consider, for example, a typical 4-bit DAC which uses simple binary weighting to generate an analog output voltage by adding together binary multiples of 0.5, 0.25, 0.125, and 0.0625 volts. It is well known that, with this choice of weights, an increase in the digital input will always lead to an increase in the analog output. For example, in such a DAC, a digital input string of 0111 would generate an analog output voltage of 0(0.5) + 1(0.25) + 1(0.125) + 1(0.0625) = 0.4375 volts. If the digital input is incremented to 1000, the analog output voltage increases to 1(0.5) + 0(0.25) + 0(0.125) + 0(0.0625) = 0.5 volts. Thus, as expected, an increment in the digital input results in an increase in the analog output. However, if the binary weights are inaccurate, due for example to resistive element inaccuracies, this monotonic relationship between input and output may be lost. Suppose that the weights are actually 0.47, 0.27, 0.14, and 0.07 volts instead of their ideal values given above. In this case, the analog output voltage corresponding to a digital input of 0111 is 0(0.47) + 1(0.27) + 1(0.14) + 1(0.07) = 0.48 volts. When the digital input is incremented to 1000, the analog output voltage actually decreases to 1(0.47) + 0(0.27) + 0(0.14) + 0(0.07) = 0.47 volts. Thus, the analog output voltage in this case is not a monotonic function of the digital input. The errors described above which lead to non-monotonic input/output relationships are particularly prevalent in DACs which sum together many binary weighted voltages, i.e., DACs having many bits. Yet it is precisely these devices that are required to provide accurate, monotonic digital to analog conversion. One example of a known digital to analog converter is shown in Naylor U.S. Patent No. 4,567,463, which attempts to provide improved performance by reducing and minimizing the variation in analog ground current. This results in a digital to analog converter that has a reduced variation in output signal so that a more accurate representation of the digital input signal is provided. Additional known digital to analog converter circuits are described in, for example, Hans S. Schouwenaars, et al., "A Low-Power Stereo 16-bit CMOS D/A Converter for Digital Audio," IEEE Journal of Solid-State Circuits , vol. 23, no. 6 (Dec. 1988); Ikeda U.S. Patent No. 4,973,979; and European Patent Application No. 0 329 231. These circuits, however, do not address many of the problems described above. In view of the foregoing, it would be desirable to provide a segmented DAC which is simple to implement and which provides immunity to loading problems associated with unbuffered analog summing of intermediate signals. It would further be desirable to provide a segmented DAC which does not require a separate buffer circuit between the output of each signal generating circuit and the summing circuitry of the DAC. It would also be desirable to provide a circuit for converting a digital input word into an analog output voltage in such a way that the analog output voltage is a monotonic function of the digital input word. It is an object of the present invention to provide a segmented DAC having a simple architecture and a novel summing technique immune to loading problems. It is another object of the present invention to provide a DAC in which problems in maintaining monotonicity arising from component inaccuracies are avoided. In accordance with these and other objects of the present invention, a segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential amplifier, which may be a unity-gain buffer amplifier or an amplifier having a different gain. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies. Brief Description of the Drawings The above and other objects of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: FIG. 1 is a block schematic diagram of a conventional monotonic DAC; FIG. 2 is a block schematic diagram of a conventional segmented DAC; FIG. 3 is a block schematic diagram of an embodiment a segmented DAC in which intermediate signals are summed by modulating the offset voltage of a differential amplifier in accordance with principles of the present invention; FIG. 4 is a block schematic diagram of an alternative embodiment of the present invention showing a segmented, interpolating DAC; FIG. 5 is a block schematic diagram of a preferred embodiment of the present invention showing a segmented, interpolating DAC; and FIG. 6 is a schematic diagram of an embodiment of an interpolating differential amplifier input stage implemented in accordance with principles of the present invention. Detailed Description of the Invention A typical example of a conventional N-bit DAC which provides guaranteed monotonic conversion is shown in simplified schematic form in FIG. 1. DAC 100 comprises ladder 101 of 2 N resistive elements with the junctions of the resistive elements coupled by bank 102 of 2 N switching devices to the input of unity gain buffer 109 comprising components 103 through 108. Although one particular embodiment of buffer 109 is shown, any conventional buffer could be used. Buffer 109 includes current source 107 which feeds the sources of PMOS transistors 103 and 104. The drains of transistors 103 and 104 are coupled to the drains of NMOS transistors 105 and 106. Transistors 105 and 106 form a current mirror. High-gain, inverting amplifier 108 provides negative feedback from the drain of transistor 103 to the gate of transistor 104. This feedback ensures that the drain currents of transistors 105 and 106 are substantially equal. This, in turn, ensures that the gate voltages of transistors 103 and 104 are substantially equal. Thus, the output voltage V OUT is substantially equal to V 1 , the output of switching device bank 102. Switching device bank 102 and resistive element ladder 101 are designed to provide an analog output voltage which is determined by a digital input word. In FIG. 1, ladder 101 and bank 102 are represented as conventional resistive elements and switching devices. However, they can be implemented in any convenient manner. For example, the resistive element ladder could be implemented with a variety of resistive materials available in an integrated circuit, and the switching devices could be MOS switches or transmission gates. Only one switching device in bank 102 is closed at any one time, and the particular switching device that is closed is determined by the digital input. Specifically, the number of resistive elements between the ground node and the node connected to the buffer amplifier's input is equal to the decimal equivalent k of the digital input. For example, with N = 4, and a digital input of 0000 (k = 0), the switching device nearest to ground in the ladder is closed; with a digital input of 0001 (k = 1), the next switching device in the ladder is closed; and so on until, with an input of 1111 (k = 15), the top-most switching device in the ladder is closed. To determine which switching device is closed requires decoding of the digital input word, and can this be accomplished in any conventional way. The precise way of implementing ladder 101, bank 102, and the necessary decoding do not form part of this invention. The voltage at the junction of any two resistive elements in ladder 101 is a monotonic function of the number of resistive elements between that particular junction and the ground node, and, as described above, this number of resistive elements is the decimal equivalent k of the digital input. Thus, the analog voltage at the buffer amplifier's input is a monotonic function of digital input. This monotonicity is guaranteed regardless of the actual values of the individual resistive elements. However, if all of the resistive elements have equal values, then the analog output voltage will be a linear function of the digital input given by V OUT = k V REF / 2 N . . In spite of its guaranteed monotonic behavior, the DAC of FIG. 1 is not a preferred embodiment when the number of bits N becomes high because, in this embodiment, the DAC requires too many switching devices and resistive elements. Several attempts have been made to overcome the disadvantage of using so many switching devices and resistive elements, but these attempts have resulted in DACs which are no longer guaranteed to be monotonic, or have been cumbersome and costly. FIG. 2 shows a schematic diagram of a typical conventional circuit using segmentation to reduce the number of switching devices and resistive elements in a DAC. In this circuit, the N-bit digital input word is segmented into two subwords. One subword, the most significant (MS) subword, corresponds to the M most significant bits, and the other subword, the least significant (LS) subword, corresponds to the L least significant bits, where M + L = N . The decimal equivalents of the LS and MS subwords are denoted by k L and k M respectively, and are related to the decimal equivalent of the digital input word by k = 2 L k M + k L . The MS subword is coupled to most significant DAC (MSDAC) 201. MSDAC 201 is fed by reference voltage V REF , and its output is given by V M = k M V REF / 2 M . The LS subword is coupled to least significant DAC (LSDAC) 202. LSDAC 202 is fed by reference voltage V REF / 2 M . This reference voltage is chosen so that the full-scale output of LSDAC 202 is equal to the change in V M when the input to MSDAC 201 is incremented by one bit. The output of LSDAC 202 is therefore V L = k L V REF / (2 M 2 L ) = K L V REF / 2 N where k L is the decimal equivalent of the LS subword. The outputs of MSDAC 201 and LSDAC 202 are added together by analog adder 207 to produce output voltage V OUT . Analog adder 207 includes resistive elements 203, 204, 205, and 208, and amplifier 206. If resistive elements 203, 204, 205, and 208 are substantially equal, then analog adder 207 has a gain of unity. With unity gain, V OUT is given by V OUT = k M V REF / 2 M + k L V REF / 2 N = (2 L k M + k L ) V REF / 2 N = k V REF / 2 N . Thus, the output voltage is controlled by the digital input word k, and can vary over the entire range of zero to V REF in 2 N steps. Compared to the guaranteed monotonic DAC of FIG. 1, the segmented DAC of FIG. 2 reduces the number of resistive elements and switching devices required. Assuming that MSDAC 201 and LSDAC 202 individually have the structure of the DAC in FIG. 1, then the total number of resistive elements required is 2 M + 2 L which can be considerably less than the 2 N resistive elements required by the DAC of FIG. 1. The number of switching devices required is also reduced by the same amount. However, the segmented DAC of FIG. 2 has drawbacks. For example, if resistors 203 and 204 were to be connected directly to respective switch banks, they would load the associated resistive element ladders and disturb the linearity of the DAC. This requires that a buffer, such as buffer 109 of FIG. 1, be included in each of MSDAC 201 and LSDAC 202. Such buffers introduce noise, have their own voltage offset and drift which must be compensated, and add complexity to the DAC. Further, although segmenting allows the number of resistive elements and switching devices to be reduced substantially, it does not guarantee monotonicity. Just as in the binary weighted DAC described earlier, the analog output voltage of a segmented DAC is obtained by adding together multiple analog voltages. The full-scale output of LSDAC 202 must equal each change in the output of MSDAC 201 as the MS subword is incremented. If this equality is not achieved, and specifically if the full-scale output of LSDAC 202 is greater than at least one increment of MSDAC 201, then non-monotonic behavior will occur. The present invention shows a new approach to digital to analog conversion which reduces the number of switching devices and resistive elements, and simplifies the architecture of the DAC of FIG. 2. Additional embodiments further guarantee monotonicity. In the preferred embodiment of the invention shown in FIG. 5 and discussed below, interpolation is used to provide a DAC which uses both a small number of resistive elements and switching devices, and is simultaneously guaranteed to be monotonic. FIG. 3, showing segmented DAC 300, illustrates the way in which the present invention simplifies the architecture of DAC 200. As in segmented DAC 200, DAC 300 uses two subwords. However, only one serial connection of resistive elements is used, and the total number of resistive elements required is 2 P , where P is the larger of L and M. For the purposes of this description, P will be assumed to be equal to M, but this assumption is not necessary. DAC 300 is obtained from DAC 100 by reducing the length of resistive element ladder 101 from 2 N resistive elements to 2 M resistive elements, and by introducing switching device bank 301, transistors 302 and 303, and current source 304. The MS subword controls switching device bank 102, and the LS subword controls switching device bank 301. The output of the LS switching device bank 301 is coupled to the input of least significant differential transconductance stage (LSDTS) 305 comprising current source 304 and transistors 302 and 303. The second input of differential transconductance stage 305 is grounded. The output of MS switching device bank 102 is coupled to the input of most significant differential transconductance stage (MSDTS) 306 comprising current source 107 and transistors 103 and 104. The drains of transistors 103 and 104 form respectively first and second differential current outputs of transconductance stage 306. The difference between the currents flowing from the drains of transistors 103 and 104 together comprise a differential current generated by transconductance stage 306. The second input of differential transconductance stage 306 is coupled to the output V OUT . This negative feedback path ensures that the currents flowing into the drains of transistors 105 and 106 are substantially equal. To understand the operation of the circuit, consider first its behavior with switching device bank 301, transistors 302 and 303, and current source 304 removed. The output is therefore only affected by the MS subword k M which controls switching device bank 102. In this case, DAC 300 has exactly the same form as DAC 100. Thus, the MS part of the DAC behaves monotonically, with its output voltage given by V OUT = k M V REF / 2 M . Now re-introduce switching device bank 301, transistors 302 and 303, and current source 304. If equal currents flow out of the drains of transistors 302 and 303 (the drains of the transistors 302 and 303 forming respectively the first and second differential current outputs of transconductance stage 305, and the difference between the currents flowing from these drains together comprising a differential current generated by transconductance stage 305), then, due to the action of the current mirror made up of transistors 105 and 106, the output V OUT is substantially unaffected by the presence of components 301 through 304. This equal current will flow when the gates of transistors 302 and 303 are at equal voltages, and because the gate of transistor 303 is grounded, this will occur when k L = 0 and switching device 301a is closed. If k L is not zero, the voltage supplied by switching device bank 301 to the gate of transistor 302 is V L = k L V REF / 2 M . This results in a differential current from LSDTS 305 of dI = k L V REF g mL / 2 M where g mL is the transconductance of LSDTS 305. Recall that negative feedback causes the output voltage to change in order to force the two currents flowing in the current mirror to be substantially equal. Thus, the output voltage must change by an amount dV which creates a differential current from MSDTS 306 which is equal but opposite to the differential current of LSDTS 305. Thus, the differential current of MSDTS 306 is dI = g mM dV where g mM is the transconductance of MSDTS 306. The change dV can be interpreted as a scaled offset voltage V OS created in buffer 109 by the addition of a differential current from LSDTS 305, and this differential current is determined by the LS subword. Substituting equation (3) into equation (4) and solving for the change in output voltage gives dV = (g mL / g mM ) k L V REF / 2 M . This change is added to the already present output voltage determined by the MS subword as given in equation (2). The resulting output voltage is then V OUT = k M V REF / 2 M + (g mL / g mM ) k L V REF / 2 M . The transconductance ratio g mL / g mM in the equation above is a parameter which is controlled by the geometry of transistors 103, 104, 302, and 303, and by current sources 107 and 304. A convenient transconductance ratio is obtained when transistors 103 and 104 have width to length ratios which are 2 L times greater than the width to length ratios of transistors 302 and 303, and current source 107 produces 2 L times as much current as current source 304. In this case, transistors 103 and 104 have transconductances which are 2 L times higher those of transistors 302 and 303, or g mL / g mM = 2 -L and the output voltage is given by V OUT = (k M + 2 -L k L ) V REF / 2 M = (2 L k M + k L ) V REF / 2 M+L = k V REF / 2 N . Thus, by choosing the transconductance ratio appropriately, the output voltage of DAC 300 can be made proportional to the decimal equivalent of the digital input word k. The LS subword controls the amount of voltage added to the output voltage determined by the MS subword. If the transconductance ratio is chosen properly and if the resistive elements in ladder 307 are accurately matched, the additional voltage contributed by the LS subword modifies the output voltage such that it lies between k M V REF / 2 M and (k M + 1) V REF / 2 M . DAC 300 requires only a small number of resistive elements and switching devices. However, it still has some limitations. In particular, DAC 300 does not truly interpolate voltages between two adjacent junctions (or taps) in resistive element ladder 307; i.e., the range of LSDTS 305 is not defined absolutely by the two adjacent taps on ladder 307, but by taps at the bottom of ladder 307. In addition, the range of LSDTS 305 is affected by the ratio g mL / g mM . Therefore, the monotonicity of DAC 300 depends on accurate control of voltage increments from resistive element junction to resistive element junction in ladder 307, and depends on accurate control of the transconductances of transistors 103, 104, 302, and 303. Still more specifically, if all resistive elements in ladder 307 are not substantially equal, the voltage increments from resistive element junction to resistive element junction will not be uniform (so called ladder tap errors occur). If, as is usually the case, M is greater than L, LSDTS 305 always obtains its input from the 2 L resistive elements nearest ground in ladder 307, while MSDTS 306 obtains its input over the entire extent of ladder 307. This is a disadvantage because, for monotonicity, DAC 300 relies on the fact that the voltage across these 2 L resistive elements nearest to ground is equal to 2 L times the voltage across any individual resistive element in ladder 307. This is analogous to the requirement in DAC 200 that the full-scale output of the LSDAC should equal the output increments of the MSDAC. If the voltage increments from tap to tap are not uniform, this requirement is not satisfied in DAC 300 and non-monotonic behavior may occur. Monotonic operation of DAC 300 also requires the transconductance ratio g mL / g mM to be accurately maintained at 2 -L . However, the transconductances are influenced by the common mode voltage at which LSDTS 305 and MSDTS 306 operate. Because LSDTS 305 always obtains its input from the 2 L resistive elements nearest to ground in ladder 307, while MSDTS 306 obtains its input over the entire extent of ladder 307, these common mode voltages are not always equal, and often not even similar. Thus, the transconductance ratio may vary, and non-monotonic behavior may occur. FIG. 4 illustrates a new digital to analog converter 400 which uses the principles of DAC 300 and solves the problem of sensitivity to ladder tap errors by truly interpolating the voltage between taps on a resistive element ladder; i.e., the range of the LSDTS is determined by the actual voltages of the taps that the LSDTS is attempting to span. FIG. 4 illustrates the particular case L = 2, but DAC 400 can be implemented with any values for L and M. DAC 400 does not derive the inputs to its two differential transconductance stages from two different parts of the resistive element ladder, and does not require the voltages across the resistive elements in the ladder to be uniform to ensure monotonicity. In addition, in DAC 400, transistors 302 and 303 are split into composite transistors 409 and 410 (and coupled to current source 411 to comprise LSDTS 408), each containing 2 L subtransistors, and the gates of all subtransistors are allowed to differ by V REF / 2 M at most. In FIG. 4, composite transistor 409 is shown to include four subtransistors 409 a-d, and composite transistor 410 is shown to include four subtransistors 410 a-d. Since these subtransistors all have substantially equal geometries, substantially equal drain currents, and similar gate voltages, their transconductances are all substantially the same. Resistive element ladder 401 and switching device bank 402 are now arranged to provide two analog outputs rather than one. Switching device bank 402 is controlled by the MS digital subword to provide output voltages V 1 = k M V REF / 2 M and V 2 = (k M + 1) V REF / 2 M . Switching device bank 404 is controlled by the LS digital subword. Switching devices 405, 406, and 407 are shown in their normal positions corresponding to k L = 0 in which they couple voltage V 1 to the gates of subtransistors 409b, 409c, and 409d respectively. If k L = 1, switching device 405 is thrown to its alterative position; if k L = 2, switching devices 405 and 406 are thrown to their alterative positions; and if k L = 3, switching devices 405, 406, and 407 are all thrown to their alterative positions. In general, k L of the switching devices in switching device bank 404 are in their alternative positions, and 2 L - k L are in their normal positions. In the alternative positions, switching devices 405, 406, and 407 couple voltage V 2 to the gates of subtransistors 409b, 409c, and 409d respectively. As previously stated, if k L = 0, switching devices 405, 406, and 407 are all in their normal positions. Thus, the gates of all subtransistors in LSDTS 408 are coupled to V 1 , and the currents flowing out of the drains of these transistors are substantially equal. The LS subword in this case, therefore, does not influence the output voltage. The gate of transistor 103 is coupled to V 1 , and negative feedback of the output to the gate of transistor 104 ensures that the output voltage is substantially equal to V 1 , or V OUT = k M V REF / 2 M . If k L is not zero, the gates of k L subtransistors in composite transistor 409 are coupled to V 2 and 2 L - k L gates are coupled to V 1 . The gates of composite transistor 410 are also all coupled to V 1 . In this manner, a scaled sum corresponding to k L is input to composite transistor 409 which causes LSDTS 408 to produce a modulated differential output current. If the gates of all 2 L subtransistors of transistor 409 are supplied with the same small-signal voltage, LSDTS 408 will produce a certain differential output current. The ratio of output current to input voltage is g mL , and this parameter is determined by the geometries of transistors 409 and 410, and by the value of current source 411. If the gate of any single subtransistor of composite transistor 409 is supplied with a small-signal voltage, and all other subtransistors are coupled to V 1 , the ratio of output current to input voltage will be g mL / 2 L (or g mL / 4 in the case shown in FIG. 4). Therefore, the differential output current of LSDTS 408 is dI = k L g mL (V 2 - V 1 ) / 2 L . Note that V 2 - V 1 is the voltage across each resistive element in ladder 401 and is given by V REF / 2 M , so that dI = k L g mL V REF / (2 M 2 L ) = k L g mL V REF / 2 N . Due to the negative feedback, this differential current is balanced by an output voltage change dV given by dI = g mM dV. Substituting equation (7) into equation (8) and solving for the change in output voltage gives dV = (g mL / g mM ) k L V REF / 2 N . This change is added to the existing output voltage which is determined by the MS subword and is given in equation (6). The resulting output voltage is then V OUT = k M V REF / 2 M + (g mL / g mM ) k L V REF / 2 N . As in DAC 300, the transconductance ratio g mL / g mM in the equation above is a parameter which can be controlled. With g mL / g mM = 1 , the output voltage, as defined by equation (9), becomes V OUT = (2 L k M + k L ) V REF / 2 N = k V REF / 2 N . Thus, by choosing the transconductance ratio appropriately, the output voltage of DAC 400 can be made proportional to the decimal equivalent of the digital input word k. The LS subword controls the amount of voltage added to the output voltage determined by the MS subword. If the transconductance ratio is chosen properly, the additional voltage contributed by the LS subword interpolates the output voltage such that it lies between k M V REF / 2 M and (k M + 1) V REF / 2 M . LSDTS 408 can be implemented using various alternative designs in accordance with principles of the present invention. For example, composite transistor 410 could be replaced by a single transistor of equivalent geometry. Also, each composite transistor could include more or less than 2 L subtransistors, and the subtransistors might have different geometries relative to one another. As mentioned previously, DAC 400 removes the sensitivity of the circuit to ladder tap errors, and it reduces the variation with common mode voltage of the transconductances of transistors in the differential transconductance stages. However, there is still a demand for the transconductance ratio g mL / g mM to be accurately maintained. If the transconductance ratio is not accurately maintained, non-monotonic behavior may occur. The requirement for an accurately determined transconductance ratio is removed in DAC 500 of FIG. 5 which illustrates the most preferred embodiment of the invention. This embodiment also maintains guaranteed monotonic behavior irrespective of ladder tap errors. FIG. 5 illustrates the case L = 2. Obviously, this number is arbitrary, and DAC 500 can be implemented with any value of L and M. DAC 500 makes use of the same resistive element ladder and switching device banks as DAC 400, and also uses the same composite transistors. However, DAC 500 does not have separate MS and LS differential transconductance stages. Instead DAC 500 has a single DTS which includes composite PMOS transistors 409 and 410. The sources of transistors 409 and 410 are fed by current source 411, and their drains (which respectively form first and second differential current outputs of transconductance stage 408) are coupled to the drains of NMOS transistors 105 and 106. Transistors 105 and 106 are connected in a current mirror configuration. The drain of transistor 105 is coupled to the input of high-gain inverting amplifier 108. The output of amplifier 108 is fed back to the gates of transistor 410, and supplies the output voltage V OUT of DAC 500. As in DAC 400, switching device bank 402 is controlled by the MS digital subword so that V 1 = k M V REF / 2 M and V 2 = (k M + 1) V REF / 2 M . Switching device bank 404 is controlled by the LS digital subword so that k L switching devices are switched to their alternative positions and 2 L - k L switching devices remain in their normal positions. Differential pair 409-410 can be viewed as being made up of four sub differential pairs, 409a-410a, 409b-410b, 409c-410c, and 409d-410d. If the geometries of each of the sub pairs are equal, then all sub pairs will have substantially equal transconductances, and each sub pair will have a transconductance equal to 1 / 2 L times the transconductance of the composite differential pair 409-410. Incrementing the LS subword by one causes switch bank 404 to switch one more gate of composite transistor 409 from V 1 to V 2 . If the LS subword were zero, all gates of composite transistor 409 would be coupled to V 1 , V OUT would be substantially equal to V 1 , and because V 1 = k M V REF / 2 M , V OUT would be substantially equal to k M V REF / 2 M . Alternatively, if all gates of composite transistor 409 (including, for purposes of discussion, gate 409a) were to be coupled to V 2 then V OUT would be substantially equal to V 2 , and because V 2 = (k M + 1) V REF / 2 M , V OUT would be substantially equal to (k M + 1) V REF / 2 M . Between these two extreme cases, if only one gate of composite transistor 409 is coupled to V 2 with the remaining 2 L -1 coupled to V 1 , then V OUT will be substantially equal to V 1 plus 1 / 2 L times the difference between V 1 and V 2 . That is, when the gate of one subtransistor is switched from V 1 to V 2 , V OUT will move from V 1 towards V 2 by an amount of (V 2 - V 1 ) / 2 L . Similarly, as each subsequent subtransistor gate is switched from V 1 to V 2 , V OUT will move further towards V 2 by an amount of (V 2 - V 1 ) / 2 L . If all subtransistor gates were to be switched to V 2 , V OUT would equal V 2 (in the embodiment of FIG. 4, however, gate 409a does not switch to V 2 ). In general, V OUT = V 1 + k L (V 2 - V 1 ) / 2 L . Incrementing the MS subword causes switch bank 402 to move V 1 and V 2 one tap up ladder 401. At the highest value of k L , when all but one of the gates of transistor 409 are switched to V 2 (i.e. all but gate 409a) , output voltage V OUT will be one increment below V 2 , or V OUT = V 1 + (2 L - 1) (V 2 - V 1 ) / 2 L = V 2 - (V 2 - V 1 ) / 2 L . The next higher step of the DAC output occurs when all switches of switch bank 404 return to tap V 1 and MS switches 402 move up one tap such that V 1 takes on the previous value of V 2 and V 2 moves one tap higher on the MS ladder. At this point, all gates of composite transistor 409 are switched to the new value of V 1 (the old value of V 2 ). V OUT then moves from its old value (one increment below the old value of V 2 ) to the new value of V 1 (which is now at the old value of V 2 ). Thus, as the LS subword resets and the MS subword increments, the output voltage moves up one increment of (V 2 - V 1 ) / 2 L , and monotonicity is assured. Substituting equations (10) and (11) into (12), after some manipulation leads to V OUT = (2 L k M + k L ) V REF / 2 N = k V REF / 2 N . Thus, DAC 500 provides monotonic digital to analog conversion independently of ladder tap errors, without the need for accurate transconductance ratio control, and with a small number of resistive elements and switching devices. FIG. 6 shows interpolating operational amplifier input stage 600 of the present invention, extracted from FIG. 5. This input stage may be used in applications other than digital to analog converters. Its utility arises from the fact that it can be used to provide an analog output V OUT at node 604 which can be digitally interpolated between two analog inputs, V 1 and V 2 at nodes 601 and 602. Circuit 600 can be generalized by coupling a feedback network from output node 604 to any of input nodes 601, 602, and 603. In addition, the gates of composite transistor 410 need not all be connected together as shown in FIG. 6. The circuits of FIGS. 3 to 5 (especially DAC 300) could be used as digital to analog converters with internal trimming. In such an application, the LS subword could be replaced by control bits used to correct inaccuracies in the conversion of the MS subword. In this case, the LS subword does not add more resolution, but the inaccuracy of each MS tap is corrected by applying a unique digital correction word to the LS circuitry. The particular digital correction word is determined by the correction required for the tap selected by the MS word. The digital correction word can be stored in an internal memory device (not shown) at a location determined by the MS word. The memory device can then automatically couple the appropriate digital correction word to the LS circuitry. Thus, circuits are provided for summing intermediate signals in a segmented DAC, and for converting a digital input word into an analog output voltage in such a way that the analog output voltage is a monotonic function of the digital input word, the circuit using a minimum number of switching devices and resistive elements. For example, buffer 109 and the interpolating operational amplifier in FIG. 5 may be configured with feedback from its output to its negative input to have a gain other than unity, the circuit could be extended to have any number of LS or MS bits, switches in switch bank 404 can be incremented one at a time (thermometer code) or can be switched in binary combinations (1, 2, 4, 8, etc.), the circuit could be designed with bipolar transistors and, if desired, with bias current compensation to prevent loading of the resistive element ladders, rather than MOS transistors, and the circuit could be used in analog to digital converters. Any type of DAC which can generate two adjacent steps could be used in place of resistive element ladder 401 and switch bank 402 in either of FIG. 4 or FIG. 5. Further, the operational amplifier of FIG. 6 could be used in other applications, without a DAC, to interpolate between any two voltages. Also, the current mirror formed by transistors 105 and 106 and the inverting amplifier 108, which together form a differential current to single-ended output voltage conversion stage, could be replaced by substantially any other type of differential current to voltage converter used in conventional operational amplifier designs.

Claims: A circuit for converting a digital signal to an analog output signal which is indicative of a decimal equivalent of the digital signal, the digital signal including a plurality of bits grouped into a first group of M more significant bits and a second group of L less significant bits, the circuit comprising first (102,307) and second (301,307) signal generating means for converting the first and second bit groups into corresponding first and second quantized analog signals, amplifier means coupled to the first and second signal generating means (102,301,307) and to an analog output node for producing an analog output signal at the analog output node, characterized by the amplifier means including: a first differential transconductance stage (306) which generates a first differential current responsive to a difference between the first quantized analog signal and a feedback signal from the analog output node, wherein the first differential current causes the amplifier means to produce an analog output signal having a first component substantially proportional to the decimal equivalent of the first bit group, and a second differential transconductance stage (305) which generates a second differential current responsive to a difference between the second quantized analog signal and a reference signal, the second differential current combining with the first differential current in the amplifier means to offset the analog output signal by a second component substantially proportional to the decimal equivalent of the second bit group. The circuit defined in claim 1, wherein the first signal generating means (102,307) comprises a ladder of resistive elements (307) having a plurality of voltage taps coupled to a bank of switching devices (102) for selecting one of the voltage taps to provide the first quantized analog signal. The circuit defined in claim 1, wherein the second signal generating means (301,307) comprises a ladder of resistive elements (307) having a plurality of voltage taps coupled to a bank of switching devices (301) for selecting one of the voltage taps to provide the second quantized analog signal. The circuit defined in claim 2, wherein the second signal generating means (301,307) comprises the ladder of resistive elements (307) coupled to an additional bank of switching devices (301) for selecting one of the voltage taps to provide the second quantized analog signal. The circuit defined in claim 1, wherein the first and second differential transconductance stages (306,305) have a transconductance ratio which scales the second component of the analog output signal relative to the first component. The circuit defined in claim 1, wherein the amplifier means further comprises a current mirror (105,106) and an inverting amplifier (108). The circuit defined in claim 1, wherein the first and second differential transconductance stages (306,305) respectively contribute first and second voltage components to the analog output signal, each of the first and second voltage components having a proportional relationship to the decimal equivalent of a respective one of the first and second bit groups, and wherein the proportional relationship of the second component to the decimal equivalent of the second bit group is determined at least in part by a ratio of transconductances of the first and second differential transconductance stages (306,305). The circuit defined in claim 4, wherein the first bank of switching devices (102) and the second bank of switching devices (301) are commonly controlled by the digital signal corresponding to the first bit group. The circuit defined in claim 1, wherein the first differential transconductance stage (306) has first and second differential signal inputs and corresponding first and second differential current outputs, and wherein the first quantized analog signal and a feedback signal derived from the analog output signal are coupled respectively to the first and second differential signal inputs of the first differential transconductance stage (306) and the first and second differential current outputs are coupled to a differential current to voltage conversion circuit. The circuit defined in claim 1, wherein the amplifier means further comprises an inverting amplifier (109) having an input and an output, the inverting amplifier input being coupled to a differential current output of the first differential transconductance stage (306) such that the inverting amplifier output provides the analog output signal. The circuit defined in claim 1, wherein the first and second signal generating means comprises a bank of switching devices (402) which are controlled by the digital signal corresponding to the second bit group, the bank of switching devices (402) being coupled to switch between the first and second quantized analog signals and provide outputs to the second differential transconductance stage (408). The circuit defined in claim 11, wherein the first and second signal generating means comprises a third bank of switching devices (404) which are controlled by the digital signal corresponding to the second bit group, the third bank of switching devices (404) being coupled to switch between the first bank of switching devices (402) and the second bank of switching devices (402), and to provide outputs to the second differential transconductance stage (408). The circuit defined in claim 1, wherein the first and second differential transconductance stages (306,305) respectively produce first and second differential currents which are combined in the amplifier means. The circuit defined in claim 13, wherein the second differential transconductance stage (408) comprises first and second transistors (409,410) forming a differential pair of transistors, the first transistor (409) comprising a composite transistor having a plurality of subtransistors and a plurality of inputs at least some of which are coupled to the first and second signal generating means, and wherein the second transistor (410) has at least one input coupled to the first signal generating means. The circuit defined in claim 14, wherein the first transistor (409) comprises 2 L subtransistors. The circuit defined in claim 14, wherein the first transistor (409) consists of 2 L subtransistors. The circuit defined in claim 14, wherein the first and second transistors (409,410) are both composite transistors. The circuit defined in claim 17, wherein each composite transistor comprises 2 L subtransistors. The circuit defined in claim 17, wherein each composite transistor consists of 2 L subtransistors. The circuit defined in claim 1, wherein the second differential transconductance stage (408) comprises first and second composite transistors (409,410) each having a plurality of subtransistors, and wherein one subtransistor of the first composite transistor (409) has an unswitched input coupled to receive the first quantized analog signal from the first signal generating means (401,402), the remainder of the subtransistors of the first composite transistor have switched inputs coupled to a control signal circuit (404), and the subtransistors of the second composite transistor (410) have inputs coupled to receive a feedback signal from the analog output node. The circuit of claim 1, wherein the amplifier means generates an analog output signal at its output having a value between minimum and maximum thresholds established respectively by the first and second quantized analog signals, the value being selected by signals received by the amplifier means from a set of switches (404). The circuit defined in claim 21, wherein the bank of switching devices (102) and the additional bank of switching devices (301) are commonly controlled by the digital signal corresponding to the first bit group. The circuit defined in claim 22, wherein a set of switches (404) coupled to the first and second differential transconductance stages (306,408) are controlled by the digital signal corresponding to the second bit group.

Inventors: REMPFER WILLIAM C, REMPFER, WILLIAM C.
Applicants: LINEAR TECHN INC, LINEAR TECHNOLOGY CORPORATION
Application year: 1994
Main classification: H03M1
IPC codes: H03M1, H03F3