Memory circuit having a plurality of input signals

Abstract: Disclosed is a multi-input memory circuit comprising a first input gate (20) for selecting one of a plurality of data signals, a first inverting gate (2) for receiving the output of the first input gate as an input, a first feedback gate (30), which has a structure of a vertical lamination inverter, receives a plurality of clock signals (CLK1,CLK2), inverted signals (CLK1B,CLK2B) of those clock signals and the output of the first inverting gate (2), and has its output terminal connected to the output terminal of the first input gate (20), and a second input gate (50), which has a vertical lamination inverter structure, and receives a plurality of clock signals, inverted signals of those clock signals and the output of the first input gate (20), and a second feedback gate (60), which has a horizontal lamination inverter structure, receives a plurality of clock signals, inverted signals of those clock signals and the output of the second inverting gate (3), and has its output terminal connected to the output terminal of the second input gate (50). With this structure, a system of matching the phases of control signals for the individual gates with one another is latently incorporated in the multi-input edge-trigger type memory circuit, thereby preventing data dropout.

Description: The present invention relates to a memory circuit, and, more particularly, to a multi-input memory circuit which has plural sets of clock signals and data signals and selectively uses an arbitrary set of clock and data signals to hold and output data. Fig. 1 is a circuit diagram showing an example of a conventional memory circuit of the above type. This circuit has two systems of inputs (a data signal IN1 and clock signal CLK1, and a data signal IN2 and clock signal CLK2), and fixes the clock signal of a non-selected system to a logic value 1 so as to hold and output data of the selected system in synchronism with the rising edge of the clock signal of the selected system. This circuit mainly comprises an input circuit 4 and a latch 5 which is triggered at the rising edge of a clock signal. To begin with, the one-input latch 5 will be described. This latch 5 has a first input gate 22, which receives a signal from the input circuit 4 and is enabled or disabled by an inverted signal CLKB of a clock signal CLK, a first hold circuit 12, which receives a signal from this first input gate 22, a second input gate 52, which is enabled or disabled by the clock signal CLK, a second hold circuit 42, which receives a signal from the input circuit 4 or the first hold circuit 12 via the second input gate 52, and an output circuit 1. The one-input latch 5 designed as above holds and outputs data in synchronism with the rising edge of the clock signal. The first hold circuit 12 receives the output signal of the input circuit 4 from the first input gate 22, which is controlled by the inverted signal CLKB of the clock signal CLK, and holds the inverted signal of that input signal by means of a first feedback loop, which comprises a first inverting gate 2 and a first feedback gate 32. The second hold circuit 42 receives the output of the first hold circuit 12 from the second input gate 52, which is controlled by the clock signal CLK, and holds the inverted signal of that input signal or the value of the output signal from the input circuit 4 by means of a second feedback loop, which comprises a second inverting gate 3 and a second feedback gate 62. The output circuit 1, which has an inverter 1A and an inverter 1B, drives a load (not shown) at the subsequent stage and guarantees the function of the second feedback loop. The first inverting gate 2 and second inverting gate 3 have a structure of an inverter, and the first feedback gate 32 and second feedback gate 62 have a structure of a clocked inverter. The first input gate 22 and second input gate 52 both have a structure of a clocked inverter, and the first input gate 22 is enabled and the second input gate 52 is disabled during a period in which the clock signal CLK has a logic value 0. Accordingly, while the first feedback loop (first hold circuit 12) is holding the data signal, the second feedback loop (second hold circuit 42) keeps holding and outputting data of the previous cycle. While the clock signal CLK has a logic value 1, the first input gate 22 is disabled and the second input gate 52 is enabled. Accordingly, the data signal is cut off from the memory circuit and at the same time the data held in the first feedback loop (first hold circuit 12) is sent to the second feedback loop (second hold circuit 42). The second feedback loop (second hold circuit 42) holds and outputs this received data. Through the above operation, when the clock signal CLK changes its logic value to "1" from "0", the data signal before the transition can be kept being output for one cycle after the transition. The "clocked inverter" is a logic gate, which functions as an inverter only when the control signal has a logic value 1 and whose output has a high resistance when the control signal has a logic value 0. The input circuit 4 will now be described. This input circuit 4 selects one system of data from two systems of data, and outputs it to the above-described one-input latch 5. The two systems of clock signals CLK1 and CLK2 input to this input circuit 4 are input to an AND gate, which comprises a NAND gate 301 and an inverter 302, to be converted into one system of a clock signal. The data signals IN1 and IN2 are input to a select gate, which comprises three NOR gates 303, 304 and 305, to be converted into one system of a data signal. This select gate has a structure of a multiplexer, which becomes active when the control signal has a logic value 0. For example, to use one set of the clock signal CLK1 and data signal IN1, the clock signal CLK2 is fixed to a logic value 1. In this case, the AND gate comprising the NAND gate 301 and inverter 302 always outputs the clock signal CLK1. As the clock signal CLK2 always has a logic value 1, the NOR gate 304 always outputs a logic value 0, causing the NOR gate 305 to always output the output of the NOR gate 304. That is, the clock signal CLK becomes the clock signal CLK1, and the output of the NOR gate 305 becomes the data signal IN1. Through the above operation, a memory circuit with multi-input signals can be accomplished. As the scale of semiconductor integrated circuits become larger and their designs become complex today, it becomes difficult to provide a detailed evaluation of the internal structure of an integrated circuit. The number of integrated circuits in which a self-evaluating device is incorporated is increasing. Of those circuits, a so-called scan bus system is employed in many semiconductor integrated circuits due to its relatively simple structure and its easy evaluation method. The scan bus system is a method of evaluating the internal structure of an integrated circuit by connecting latches or registers to be evaluated in a row and outputting their contents as serial data. According to this method, while the individual latches hold and output received data in synchronism with a clock signal from the system in normal operation mode, each of the latches connected in a row shifts its content to the next latch, thereby outputting their contents as serial data, in synchronism with a test clock signal in test mode. Accomplishing this function, therefore, requires a memory circuit which selectively uses the logic connection in normal operation mode or the connection of the latches for the test mode. There are several possible ways to select the normal operation or an operation in test mode. What relates to this invention is a memory circuit which is suitable particularly for the case where the normal operation or the test-mode operation is selected by the simplest system of disabling a test clock signal in normal operation mode and disabling a clock signal for the normal operation in test mode. Since the above-described conventional multi-input memory circuit requires a signal coming through a logic gate as a clock signal and uses a separate system of circuit to select data, however, it has the following shortcomings. First, the clock signal lags by delay caused by traveling through the NAND gate 301 and inverter 302, so that the delay of the clock signal is wasted every cycle, as compared with an ordinary memory circuit of a single-system type. Secondly, since the data signal and clock signal pass separate logics, it is difficult to design the timings for the setup and hold. Particularly, the skew and delay of the clock signal is always the bottleneck on the design in recent high-speed semiconductor integrated circuits, and the driver and the traveling path for the clock signal are designed very prudently. Therefore, the circuit configuration which causes the clock signal to pass through a gate and the circuit configuration which disturbs the regularity of that timing, as of the above-described conventional memory circuit, disadvantageously increase a burden on the circuit design. It is therefore a primary object of the present invention to provide an edge-trigger type multi-input memory circuit in which a system of matching the phases of control signals for individual gates with one another is latently incorporated to thereby avoid a possibility of causing dropout of data. It is another object of this invention to provide a multi-input memory circuit which reduces a burden on the circuit design. These objects are achieved by a multi-input memory circuit according to claims 1, 2 or 3. The dependent claims are related to further advantageous aspects of the present invention. The first feedback gate includes a first transistor row having a series circuit having series-connected first conductivity type MOS transistors for receiving inverted signals of the plurality of clock signals respectively as gate inputs, and a first conductivity type MOS transistor for receiving an output of the first inverting gate as a gate input, the series circuit of first conductivity type MOS transistors being connected in series to the latter first conductivity type MOS transistor, and a second transistor row having a series circuit having series-connected second conductivity type MOS transistors for receiving the plurality of clock signals respectively as gate inputs, and an second conductivity type MOS transistor for receiving the output of the first inverting gate as a gate input, the series circuit of second conductivity type MOS transistors being connected in series to the latter second conductivity type MOS transistor, a drain electrode of a first end of the first transistor row and a drain electrode of a first end of the second transistor row being connected together to be an output terminal, a source electrode of a second end of the first transistor row being fixed to a potential of a high-potential power source, and a source electrode of a second end of the second transistor row being fixed to a ground potential. According to this invention, since the control signal for the first input gate and the control signal for the second input gate work in the same phase, data dropout can be avoided. In the case where the logic value of the clock signal changes from "1" to "0", when the first input gate is enabled, the second input gate is disabled at the same time, preventing any data dropout. Even if there is a skew between the clock signal and its inverted signal, the circuit configuration of this invention will prevent data dropout. Accordingly, this invention has such an advantage as to eliminate the need for fine adjustment for preventing data dropout and the need for re-checking. Fig. 1 is a circuit diagram showing one example of a conventional memory circuit; Fig. 2 is a circuit diagram of a first embodiment of the present invention; and Fig. 3 is a circuit diagram of a second embodiment of the present invention. Preferred embodiments of the present invention will now be described. Fig. 2 presents a circuit diagram showing the first embodiment of the present invention. Like the conventional memory circuit shown in Fig. 1, this embodiment has a clock signal CLK1, an inverted signal CLK1B of this clock signal CLK and a data signal IN1 as the first input system, and a clock signal CLK2, an inverted signal CLK2B of this clock signal CLK and a data signal IN2 as the second input system. By fixing the clock signal of one system to a logic value 1, the data signal will be held and output in the other system in synchronism with the rising edge of the clock signal of this system. In the memory circuit of this embodiment, the data signals IN1 and IN2 are respectively input to clocked inverters 111 and 112 whose outputs are both input to a first hold circuit 10 and a second input gate 50. The clocked inverters 111 and 112 are respectively controlled by the inverted signals CLK1B and CLK2B of the clock signals. The output of the second input gate 50 is input to a second hold circuit 40 and an output circuit 1. This output circuit 1, like the one in Fig. 1, comprises an inverter 1A and an inverter 1B. A description will now be given of vertical lamination inverter which constitute the first hold circuit 10 and second input gate 50, and a horizontal lamination inverter which constitutes the second hold circuit 40. First, the "vertical lamination inverter" is a logic gate having such a structure as that of a first feedback gate 30 of the first hold circuit 10, which comprises six MOS transistors 131, 132, 133, 134, 135 and 136 in Fig. 2. As illustrated, the three p channel (first conductivity type) MOS transistors 131, 132 and 133 are connected in series and are arranged in a row in vertical lamination, with one end of the transistor row connected to a power source potential. The three n channel MOS (second conductivity type) transistors 134, 135 and 136 are connected in series and are arranged in a row in vertical lamination, with one end of the transistor row connected to a ground potential. Both transistor rows are connected between the power source potential and the ground potential, constituting the vertical lamination inverter. The node between the first input gate 20 and the second input gate 50 is connected to the node between the transistors 133 and 136 of the first feedback gate 30, and is also connected via an inverter 2 to the control-signal input terminals of the transistors 132 and 135. The transistors 134 and 131 are respectively controlled by the first clock signal CLK1 and its inverted signal CLK1B, and the transistors 136 and 133 are respectively controlled by the second clock signal CLK2 and its inverted signal CLK2B. Therefore, the vertical lamination inverter functions as an inverter only when the clock signals CLK1 and CLK2 both have a logic value 1, and their outputs have a high resistance otherwise. Since this vertical lamination inverter is controlled by a clock signal which is in phase with the clock signal that controls the first input gate 20 constituted of the clocked inverters 111 and 112, no data dropout will occur in this memory circuit. Likewise, the second input gate 50 comprises six MOS transistors 141, 142, 143, 144, 145 and 146, the first three being p channel MOS transistors and the second three being n channel MOS transistors, all connected between the power source potential and the ground potential. The transistors 141 and 143 are respectively controlled by the inverted clock signals CLK1B and CLK2B, while the transistors 144 and 146 are respectively controlled by the clock signals CLK1 and CLK2. The first input gate 20 is connected to the control-signal input terminals of the transistors 142 and 145, and the node between the transistors 143 and 146 is connected to the output circuit 1. The "horizontal lamination inverter" is a logic gate having such a structure as that of a second feedback gate 60 of the second hold circuit 40, which comprises six MOS transistors 161, 162, 163, 164, 165 and 166 in Fig. 2. As illustrated, the p channel MOS transistors 161 and 162 are connected in parallel and are arranged in horizontal lamination, with one end of the parallel circuit connected to the power source potential and the other end connected in series to the p channel MOS transistor 163 in vertical lamination. The n channel MOS transistors 164 and 165 are connected in parallel to be arranged in horizontal lamination, with one end of the parallel circuit connected to the ground potential with the other end connected in series to the n channel MOS transistor 166 in vertical lamination. The transistors 161-163 and the transistors 164-166 are connected between the power source potential and the ground potential, constituting a horizontal lamination inverter. The node between the second input gate 50 and the output circuit 1 is connected to the node between the transistors 163 and 166 of the second feedback gate 60, and is also connected via an inverter 3 to the control-signal input terminals of the transistors 163 and 166. The transistors 161 and 164 are respectively controlled by the first clock signal CLK1 and its inverted signal CLK1B, while the transistors 162 and 165 are respectively controlled by the second clock signal CLK2 and its inverted signal CLK2B. Therefore, the horizontal lamination inverter functions as an inverter when either one of the clock signals CLK1 and CLK2 has a logic value 1, and their outputs have a high resistance when those clock signals both have a logic value 0. This horizontal lamination inverter, like the above-described vertical lamination inverter, functions in synchronism with the control clock signal of the first input gate 20. A detailed description of the operation of this embodiment will now be given, in the case where the data holding operation is executed with respect to a set of the first clock signal CLK1 and the data signal IN1 for descriptive simplicity. That is, it is assumed that the second clock signal CLK2 always has a logic value 1 and its inverted signal CLK2B always has a logic value 0. The first input gate 20 selects one of two systems of data signals. In this case, the clocked inverter 112, which is controlled by the inverted clock signal CLK2B, is always disabled, thus blocking the second data signal IN2 from the memory circuit. In other words, the first input gate 20 becomes equivalent to a clocked inverter which receives the first data signal IN1 as an input and is controlled by the inverted signal CLK1B of the first clock signal CLK1. The first feedback loop comprises the first inverting gate 2 and the transistors 131, 132, 133, 134, 135 and 136, which constitute the first feedback gate 30, and holds the output of the first input gate (clocked inverter 111) like the first feedback loop in the conventional memory circuit shown in Fig. 1. In this case, the transistors of the first feedback gate 30, which are respectively controlled by the clock signals CLK2 and CLK2B, are both enabled. The first feedback gate 30 is therefore equivalent to a clocked inverter which receives the output of the first inverting gate 2 as an input and is controlled by the first clock signal CLK1. Thus, the first feedback loop becomes equivalent to the first feedback loop in the conventional memory circuit shown in Fig. 1. The six MOS transistors 141 to 146 constituting the second input gate 50, like the second input gate 52 in the conventional memory circuit shown in Fig. 1, transfers the output of the first input gate (inverting gate 111) to the second feedback loop. In this case, the transistors 143 and 146, which are respectively controlled by the inverted clock signals CLK2B and CLK2, are both enabled. The second input gate 50 is therefore equivalent to a clocked inverter which receives the output of the first input gate (clocked inverter 111) as an input and is controlled by the first signal CLK1. Thus, the second input gate 50 becomes equivalent to the second input gate 52 in the conventional memory circuit shown in Fig. 1. The second feedback loop comprises the second inverting gate 3 and the transistors 161 to 166, which constitute the second feedback gate 60, and holds the output of the second input gate 50 like the second feedback loop in the conventional memory circuit shown in Fig. 1. In this case, the transistors 162 and 165, which are respectively controlled by the clock signals CLK2 and CLK2B, are both disabled. The second feedback gate 60 is therefore equivalent to a clocked inverter which receives the output of the second inverting gate 3 as an input and is controlled by the first clock signal CLK1. Thus, the second feedback loop becomes equivalent to the second feedback loop in the conventional memory circuit shown in Fig. 1. The inverters 1A and 1B constitute an output buffer, and drive a load circuit at the next stage while reducing the load on the second feedback loop. As described above, when the second clock signal CLK2 has a logic value 1, this embodiment functions as an ordinary one-input memory circuit, which is triggered by the rising edge of the input, with the first data signal IN1 used as a data signal and the first clock signal CLK1 as a clock signal. Likewise, when the first clock signal CLK1 is fixed to a logic value 1, this embodiment functions as an ordinary one-input memory circuit, which is triggered by the rising edge of the input, with the second data signal IN2 used as a data signal and the second clock signal CLK2 as a clock signal. As the control signal for the first input gate 20 functions in phase with the control signal for the second input gate 50 in this embodiment, data dropout will not occur. In the case where the logic value of the clock signal changes from "1" to "0", when the first input gate is enabled, the second input gate is disabled at the same time, preventing any data dropout. Further, even if there is a skew between the clock signal and its inverted signal, the memory circuit embodying this invention will prevent data dropout. In the case where a p channel MOS transistor and an n channel MOS transistor conduct simultaneously due to the difference between their threshold values when a clock signal with a very dull waveform and its inverted signal are input, data dropout may occur. This comes to the matter of the difference in driving performances of the first feedback loop and the second input gate 50, and will not raise any problem on a practical waveform of the clock signal and the driving power of each gate. Accordingly, this embodiment will eliminate the need for fine adjustment for preventing data dropout and the need for re-checking. The second embodiment of this invention will now be described. Fig. 3 presents a circuit diagram of the second embodiment. In this embodiment, an inverting gate 6 is provided in place of the inverter 2 of the first embodiment, and a reset signal RSTB is added as an input. This embodiment performs the same function as the first embodiment when the reset signal RSTB has a logic value 1, but always outputs a logic value 0 when the reset signal RSTB has a logic value 0. In this embodiment, the first input gate 20, first feedback gate 30, second input gate 50, second inverting gate 3, second feedback gate 60 and output circuit 1 are identical to those of the first embodiment. The first inverting gate 6 receives the output of the first input gate 20 as one input and the reset signal RSTB as the other input. When the reset signal RSTB has a logic value 1, this gate 6 functions the same way as an inverter, so that this embodiment becomes an equivalent to the first embodiment. When the reset signal RSTB has a logic value 0, the first inverting gate 6 always outputs "1." Therefore, the first feedback loop always holds a logic value 1, thus allowing the second feedback loop to always hold a logic value 0. Thus, this embodiment always outputs a logic value 0. As described above, this embodiment will function as a two-input rising-edge trigger type memory circuit which can reset the output by fixing the reset signal RSTB to a logic value 0. Although the foregoing description has been given with reference to the case where two systems of clock and data signals are handled, this invention will also have the same advantages in the case where more than two systems of clock and data signals are handled. In other words, this invention can easily be adapted for a multi-system circuit by providing the vertically-laminated transistors in the vertical lamination inverter, which are controlled by the first and second control signals, in the same number of stages as the number of systems of clock signals, and providing the horizontally-laminated transistors in the horizontal lamination inverter, which are controlled by the first and second control signals, in the same number of stages as the number of systems of clock signals. Although the foregoing description of this invention has discussed a rising-edge trigger type memory circuit, a falling-edge trigger type memory circuit can easily be designed by replacing all the clock signals with their inverted signals and vice versa.

Claims: A multi-input memory circuit for receiving a plurality of clock signals (CLK1, CLK2) and a plurality of data signals (IN1, IN2) paired respectively with said plurality of clock signals and selectively using an arbitrary set of said clock and said data signals to store and output data, comprising: a first input gate (20) for receiving inverted signals (CLK1B, CLK2B) of said plurality of clock signals (CLK1, CLK2) and said plurality of data signals (IN1, IN2), and selectively outputting one of said plurality of data signals based on one of said inverted signals of said plurality of clock signals; a first feed back loop having a first inverting gate (2, 6) and a first feedback gate (30) having an input terminal connected to an output terminal of said first inverting gate (2, 6) and an output terminal connected to an input terminal thereof, said input terminal of said first inverting gate (2, 6) and said output terminal of said first feedback gate (30) being connected to an output terminal of said first input gate; a second input gate (50) for receiving a data from said first input gate (20) or said first feedback loop and outputting an inverted data of said data; and a second feedback loop having a second inverting gate (3) and a second feedback gate (60) having an input terminal connected to an output terminal of said second inverting gate (3) and an output terminal connected to an input terminal thereof, said input terminal of said second inverting gate (3) and said output terminal of said second feedback gate (60) being connected to an output terminal of said second input gate; characterized in that, said first feedback gate (30) includes a first transistor row having a series circuit having series-connected first conductivity type MOS transistors (131, 133) for receiving one of said inverted signals (CLK1B, CLK2B) of said plurality of clock signals respectively as gate inputs, and a first conductivity type MOS transistor (132) for receiving said output of said first inverting gate (2) as a gate input, said series circuit of first conductivity type MOS transistors (131, 133) being connected in series to said latter first conductivity type MOS transistor (132), and a second transistor row having a series circuit having series-connected second conductivity type MOS transistors (134, 136) for receiving one of said plurality of clock signals (CLK1, CLK2) respectively as gate inputs, and a second conductivity type MOS transistor (135) for receiving said output of said first inverting gate (2) as a gate input, said series circuit of second conductivity type MOS transistors (134, 136) being connected in series to said latter second conductivity type MOS transistor (135), a drain electrode of a first end of said first transistor row and a drain electrode of a first end of said second transistor row being connected together to be said output terminal of said first feedback gate, a source electrode of a second end of said first transistor row being fixed to a potential of a high-potential power source, and a source electrode of a second end of said second transistor row being fixed to a ground potential. A multi-input memory circuit for receiving a plurality of clock signals (CLK1, CLK2) and a plurality of data signals (IN1, IN2) paired respectively with said plurality of clock signals, and selectively using an arbitrary set of said clock and said data signals to store and ouput data, comprising: a first input gate (20) for receiving inverted signals (CLK1B, CLK2B) of said plurality of clock signals (CLK1, CLK2) and said plurality of data signals (IN1, IN2), and selectively outputting one of said plurality of data signals (IN1, IN2) based on one of said inverted signals of said plurality of clock signals; a first feedback loop having a first inverting gate (2, 6) and a first feedback gate (30) having an input terminal connected to an output terminal of said first inverting gate (2, 6) and an output terminal connected to an input terminal thereof, said input terminal of said first inverting gate (2, 6) and said output terminal of said first feedback gate (30) being connected to an output terminal of said first input gate; a second input gate (50) for receiving a data from said first input gate (20) or said first feedback loop and outputting an inverted data of said data; and a second feedback loop having a second inverting gate (3) and a second feedback gate (60) having an input terminal connected to an output terminal of said second inverting gate (3) and an output terminal connected to an input terminal thereof, said input terminal of said second inverting gate (3) and said output terminal of said second feedback gate (60) being connected to an output terminal of said second input gate; characterized in that, said second input gate (50) includes a third transistor row having a series circuit having series-connected first conductivity type MOS transistors (141, 143) for receiving one of said plurality of inverted clock signals (CLK1B, CLK2B) respectively as gate inputs, and a first conductivity type MOS transistor (142) for receiving said output of said first input gate (20) as a gate input, said series circuit of first conductivity type MOS transistors (141, 143) being connected in series to said latter first conductivity type MOS transistor (142), and a fourth transistor row having a series circuit having series-connected second conductivity type MOS transistors (144, 146) for receiving one of said signals (CLK1, CLK2) of said plurality of clock signals respectively as gate inputs, and a second conductivity type MOS transistor (145) for receiving said output of said first input gate (20) or said first feedback loop as a gate input, said series circuit of second conductivity type MOS transistors (144, 146) being connected in series to said latter second conductivity type MOS transistor (145), a drain electrode of a first end of said third transistor row and a drain electrode of a first end of said fourth transistor row being connected together to be said output terminal of said second input gate, a source electrode of a second end of said third transistor row being fixed to said potential of said high-potential power source, and a source electrode of a second end of said fourth transistor row being fixed to said ground potential. A multi-input memory circuit for receiving a plurality of clock signals (CLK1, CLK2) and a plurality of data signals (IN1, IN2) paired respectively with said plurality of clock signals and selectively using an arbitrary set of said clock and said data signals to store and output data, comprising: a first input gate (20) for receiving inverted signals (CLK1B, CLK2B) of said plurality of clock signals (CLBK1, CLBK2) and said plurality of data signals (IN1, IN2), and selectively outputting one of said plurality of data signals based on one of said inverted signals of said plurality of clock signals; a first feedback loop having a first inverting gate (2) and a first feedback gate (30) having an input terminal connected to an output terminal of said first inverting gate (2) and an output terminal connected to an input terminal thereof, said input terminal of said first inverting gate (2) and said output terminal of said first feedback gate (30) being connected to an output terminal of said first input gate; a second input gate (50) for receiving a data from said first input gate (20) or said first feedback loop and outputting an inverted data of said data; and a second feedback loop having a second inverting gate (3) and a second feedback gate (60) having an input terminal connected to an output terminal of said second inverting gate (3) and an output terminal connected to an input terminal thereof, said input terminal of said second inverting gate and said output terminal of said second feedback gate being connected to an output terminal of said second input gate (50) ; characterized in that, said second feedback gate (60) includes a fifth transistor row having a parallel circuit having parallel-connected first conductivity type MOS transistors (161, 162) for receiving one of said plurality of clock signals (CLK1, CLK2) respectively as gate inputs, and a first conductivity type MOS transistor (163) for receiving said output of said second inverting gate (3) as a gate input, said parallel circuit of first conductivity type MOS transistors (161, 162) being connected in series to said latter first conductivity type MOS transistor (163), and a sixth transistor row having a parallel circuit having parallel connected second conductivity type MOS transistors (164, 165) for receiving one of said inverted signals (CLK1B, CLK2B) of said plurality of clock signals respectively as gate inputs, and a second conductivity type MOS transistor (166) for receiving said output of said second inverting gate (3) as a gate input, said parallel circuit of second conductivity type MOS transistors (164, 165) being connected in series to said latter second conductivity type MOS transistor (166), a drain electrode of a first end of said fifth transistor row and a drain electrode of a first end of said sixth transistor row being connected together to be said output terminal of said second feedback gate (60), a source electrode of a second end of said fifth transistor row being fixed to said potential of said high-potential power source, and a source electrode of a second end of said sixth transistor row being fixed to said ground potential. The multi-input memory circuit according to claim 1 or 3 characterized in that said second input gate (50) includes a third transistor row having a series circuit having series-connected first conductivity type MOS transistors (141, 143) for receiving one of said plurality of inverted clock signals (CLK1B, CLK2B) respectively as gate inputs, and a first conductivity type MOS transistor (142) for receiving said output of said first input gate (20) as a gate input, said series circuit of first conductivity type MOS transistors (141, 143) being connected in series to said latter first conductivity type MOS transistor (142), and a fourth transistor row having a series circuit having series-connected second conductivity type MOS transistors (144, 146) for receiving one of said signals of said plurality of clock signals respectively as gate inputs, and a second conductivity type MOS transitor (145) for receiving said output of said first input gate (20) or said first feedback loop as a gate input, said series circuit of second conductivity type MOS transistors (144, 146) being connected in series to said latter second conductivity type MOS transistor (145), a drain electrode of a first end of said third transistor row and a drain electrode of a first end of said fourth transistor row being connected together to be said output terminal of said second input gate (50), a source electrode of a second end of said third transistor row being fixed to said potential of said high-potential power source, and a source electrode of a second end of said fourth transistor row being fixed to said ground potential. The multi-input memory circuit according to claims 1, 2 or 4, characterized in that said second feedback gate (60) includes a fifth transistor row having a parallel circuit having parallel-connected first conductivity type MOS transistors (161, 162) for receiving one of said plurality of clock signals (CLK1, CLK2) respectively as gate inputs, and a first conductivity type MOS transistor (163) for receiving said output of said second inverting gate (3) as a gate input, said parallel circuit of first conductivity type MOS transistors (161, 162) being connected in series to said latter first conductivity type MOS transistor (163), and a sixth transistor row having a parallel circuit having parallel-connected second conductivity type MOS transistors (164, 165) for receiving one of inverted signals (CLK1B, CLK2B) of said plurality of clock signals respectively as gate inputs, and an second conductivity type MOS transistor (166) for receiving said output of said second inverting gate (3) as a gate input, said parallel circuit of second conductivity type MOS transistors (164, 165) being connected in series to said latter second conductivity type MOS transistor (166), a drain electrode of a first end of said fifth transistor row and a drain electrode of a first end of said sixth transistor row being connected together to be said output terminal of said second feedback gate (60), a source electrode of a second end of said fifth transistor row being fixed to said potential of said high potential power source, and a source electrode of a second end of said sixth transistor row being fixed to said ground potential. The multi-input memory circuit according to one of claims 1 to 5, characterized in that, said first input gate (20) has a first clocked inverter (111), which receives a first data signal (IN1) and is controlled by an inverted signal (CLK1B) of a first clock signal, and a second clocked inverter (112), which receives a second data signal (IN2) and is controlled by an inverted signal (CLK2B) of a second clock signal, output ends of said first and second clocked inverters being connected together. The multi-input memory circuit according to one of claims 1 to 6, characterized in that, said first inverting gate is an inverter (2). The multi-input memory circuit according to one of claims 1 to 6, characterized in that, said first inverting gate is a logic circuit (6) for receiving the output of said first input gate (20) as an input signal as one input and a reset signal (RSTB) as another input and outputting said input signal after inversion when said reset signal has a logic value 1 and outputting a logic value 0 when said reset signal has a logic value 0. The multi-input memory circuit according to claim 1, characterized in that, said first conductivity type is p channel and said second conductivity type is n channel.

Inventors: NISHIZAWA TAKAHIKO, NISHIZAWA, TAKAHIKO, NISHIZAWA, TAKAHIKO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: G11C7
IPC codes: G11C7, H03K3, H03K17, G01R31