Programmable logic array

Abstract: A programmable logic array comprises a PLA area (20, 21, 22, 23) having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit (24, 25, 26, 271 to 274, 281 to 284, 291 to 294) for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.

Description: The present invention relates to a programmable logic array (PLA) for decoding a micro code in a one-chip microcomputer, a microprocessor (MPU), and a microcontroller (MCU) according to the preamble of claim 1. Such a programmable logic array is, e.g., described in EP-A-0 428 300. In general, a PLA for micro code has an AND array section for an input of the micro code and an OR array section for an output of decode. The AND array section is formed to be an AND typed or an OR typed. The AND typed AND array section is characterized in that the area of the section is small and the section is formed on a semiconductor chip. The OR typed AND array section is characterized in that the speed of an operation of the section is high. FIG. 1 shows one example of a conventional PLA for micro-code. In the PLA, the AND array section is formed to be AND typed. Reference numeral 51 is an AND typed AND array section, 52: an OR array section, 53: an address input buffer circuit provided on an input side of the AND array section 51, 54: a clock input buffer circuit provided on an input side of the AND array section 51, and 55: an output latch circuit provided on an output side of the OR array section. The buffer circuit 53 increases a PLA input signal IR〈m〉, and supplies the signal to the AND array section 51 as a command code. The buffer circuit 54 increases a precharge-discharge signal (Pre/Dis signal)and supplies the signal to the AND array section 51 and the OR array section 52. The AND array section 51 comprises a plurality of NAND circuits arranged in a column direction X, and a plurality of inverter circuits 511, which inverts each of outputs of the plurality of the NAND circuits, and inputs these outputs to the OR array section 52. Each NAND circuit comprises one P channel MOS transistor 512 for precharge wherein a source is connected to a power supply voltage (Vcc) node, one N channel MOS transistor 514 for discharge wherein a source is connected to a ground voltage (Vss) node, and a plurality of N channel MOS transistors 513 connected in series between a drain of the P channel MOS transistor 512 and a drain of the N channel MOS transistor 514. The OR array section 52 comprises a plurality of NOR circuits arranged in a row direction Y, a word line extending in a row direction Y, and a decode output wire (bit line) extending in a column direction X. Each NOR circuit comprises one P channel MOS transistor 521 for precharge wherein a source is connected to a power supply (Vcc) node and a plurality of N channel MOS transistors 522 wherein a drain is connected to a drain of the P channel MOS transistor 521 and a source is connected to a ground voltage (Vss) node. FIG. 2 is a timing chart showing an operation of the micro-code PLA of FIG. 1. First of all, when the Pre/Dis charge signal is set to a precharge mode ("0" level), the AND array section 51 and the OR array section 52 are precharge, respectively. If the PLA input signal IR〈m〉 is inputted during the precharge mode, all inputs of one NAND circuit are set to "1" level in the AND array section 51. Next, when the Pre/Dis charge signal is set to a discharge mode ("1" level), the N channel MOS transistor 514 of each NAND circuit is turned on. Therefore, an output signal of one NAND circuit in which all inputs are set to "1" level is set to "0" level, and the outputs of the other NAND circuits are set to "1" level. The output signal of each NAND circuit is reversed by the inverter circuit 511, and inputted to the OR array section 52. In the OR array section 52, the NOR circuit to which the voltage of "1" level is inputted outputs an output signal of "0" level. For example, in a case that a word line DECO is set to "0" level, a bit line Bit0 is set to "0" level. The output latch circuit 55 latches the output of the OR array section 52 by complementary clock signals PH, /PH, and outputs the signal as an output signal out of PLA. FIG. 3 shows an example of a conventional micro-code PLA. In the PLA, the AND array section is formed to be OR typed. Reference numeral 71 is an OR typed AND array section, 72: an OR array section, 53: an address input buffer circuit, 54: a clock input buffer circuit, and 55: an output latch circuit. The AND array section 71 comprises a plurality of NOR circuits arranged in a column direction X, and a plurality of inverter circuits 711 for inputting an output signal of each of the NOR circuits to the OR array section 72. Each NOR circuit comprises one P channel MOS transistor 712 for precharge wherein a source is connected to a power supply voltage (Vcc) node, one N channel MOS transistor 714 for discharge wherein a source is connected to a ground voltage (Vss) node, and one or more N channel MOS transistors 713 connected in parallel between a drain of the P channel MOS transistor 712 and a drain of the N channel MOS transistor 714. In this case, one specific NOR circuit of the NOR circuits has two N channel MOS transistors 714 for discharge. The OR array section 72 comprises a plurality of NOR circuits arranged in a row direction Y, a word line extending in a row direction Y, and a decode output wire (bit line) extending in a column direction X. For example, each NOR circuit comprises one P channel MOS transistor 721 for precharge wherein a source is connected to a power supply voltage (Vcc) node, one N channel MOS transistor 723 for discharge wherein a source is connected to a ground voltage (Vss) node, and one or more N channel MOS transistors 722 connected in parallel between a drain of the P channel MOS transistor 721 and a drain of the N channel MOS transistor 723. Moreover, in the OR array section 72, a delay circuit 73 is provided. The delay circuit 73 delays the discharge operation of the N channel MOS transistor 723 for discharge of each NOR circuit by a predetermined time as compared with the discharge operation of the N channel MOS transistor 714 for discharge of the AND array section 71. The delay circuit 73 comprises an inverter circuit 731 for inverting the output signal of one NOR circuit of the AND array section 71, an NAND circuit 732 to which the output signal of the inverter circuit 731 and the Pre/Dis signal are inputted, and an inverter circuit 733, which inverts the output signal of the NAND circuit 732, and inputs the signal to a gate of the N channel MOS transistor 723 for discharge of each NOR circuit. FIG. 4 shows one example of an operation timing of the micro-code of FIG. 3. First of all, when the Pre/Dis signal is set to a precharge mode ("0" level), precharging is performed in each of the AND array section 71 an the OR array section 72. An input IR(m) is inputted from the outer section of PLA during the precharge. In the AND array section 71, all inputs of one NOR circuit are set to "0" level. However, the output signals of all NOR circuits of the AND array section 71 are set to "1" level, and each of these output signals is inputted to the OR array section 72 through each inverter circuit 711. The input signals of all NOR circuits of the OR array section 72 are set to "1" level. The inverter circuit 731 outputs an output signal of "0" level. The NAND circuit 732 receives the Pre/Dis signal of "0" level and the output of the inverter circuit 731 of "0" level, and outputs an output signal of "1" level. The inverter circuit 733 supplies a Dis-OR signal of "0" level to a gate of the N channel MOS transistor 723 for discharge of each NOR circuit. Therefore, the N channel MOS transistor 723 is turned off, and the output signal of each NOR circuit of the OR array section is set to "1" level (precharge level). Next, if the Pre/Dis signal is set to a discharge mode ("1" level"), and the N channel MOS transistor 714 for discharge of each NOR circuit of the AND array section 71 is turned on, one NOR circuit in which all input signals are in "0" level outputs an output signal of "1" level, and supplies the outputs signal of "1" level (for example, DECO) to one word line of the OR array section. Since at least one input signal of the other NOR circuits of the AND array section 71 is set to "1" level, at least one N channel MOS transistor 712 is turned on. Therefore, the outputs of these residual NOR circuits are set to "0" level, and the outputs of "0" level are supplied to the word line of the OR array section 72. Moreover, the output signal of the NOR circuit having two N channel MOS transistors 714 for discharge is set to "0" level, and the output of "0" level is supplied to the OR array section 72. In the OR array section 72, the NOR circuit in which at least one input signal is set to "1" level outputs the output signal of "0" level (for example, Bit0). The discharge is not performed until the level of the word line is determined by the delay circuit 73, and the N channel MOS transistor 723 for discharge of each NOR circuit is maintained to be off state. Therefore, since the output signal of the NOR circuit in which all input signals are set to "1" level is maintained to be in "1" level (precharge level), the output signal (for example, Bit1, ...) of the bit signal of the NOR circuit is set to "1" level. The output latch circuit 55 latches the output signal of the OR array section 72 by complementary clock signals PH, /PH, and outputs the signal as an output signal OUt of PLA. As mentioned above, in the AND array section of the conventional PLA, the number of the NAND circuit in which all input signals are set to "1" level or the number of the NOR circuit in which all input signals are set to "0" is only one. However, the input signal IR(m) is inputted to all NAND circuits of the AND array section or all OR circuits thereof. Therefore, all NAND circuits of the AND array section or the MOS transistor of the NOR circuits are driven. Moreover, since the entire PLA is set to be an active state, the entire array section and the entire OR circuit are precharged/discharged. Particularly, in the PLA having the OR typed AND array section 71, all output signals of the AND array section 71 are set to "1" level (precharge level) at the time of precharging, and the output signals of the residual NOR circuits in which all input signals are set to "0" level, excepting one NOR circuit, are discharged to "0" level. Therefore, there is a disadvantage in that consumption of electric power of PlA is increased. This disadvantage becomes outstanding as the degree of integration of PLA increases and the capacity per unit area becomes large. In consideration of the above-mentioned disadvantage, the present invention has been made, and an object of the present invention is to provide a programmable logic array in which consumption of electric power of PLA can be reduced. In order to attain the above object, according to the present invention as claimed in claim 1, there is provided a programmable logic array comprising a PLA area having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle; and a control circuit for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks. Moreover, each of the banks comprises a latch control section for inputting a command code thereto; an AND array section for receiving an input signal from the latch control section; an OR array section having a plurality of decode output OR circuits to which an output signal of the AND array section is inputted; and an OR array section having at least one bank selection signal output NOR circuit; and the control circuit comprises an output selector for selecting a decode output from each bank every bank to be fetched; an output register for latching an output signal of the output selector based on a synch clock signal; a bank selection signal latch circuit for latching a bank selection signal outputted from the output register based on the synch clock signal to be supplied to the output selector as a selector control signal; a precharge signal line for supplying the synch clock signal to each of the bank as a precharge signal; a latch signal supply circuit, provided to each corresponding bank, for decoding the bank selection signal of the output register to be outputted as a latch signal of the latch control section; and a discharge control signal supply circuit, provided to each corresponding bank, for ORing the latch signal and the precharge signal to be supplied to each bank as a discharge signal. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram showing one example of a conventional PLA for a micro-code; FIG. 2 is a timing chart showing an operation of the PLA of FIG. 1; FIG. 3 is a circuit diagram showing the other examples of the conventional PLA for a micro-code; FIG. 4 is a timing chart showing an operation of the PLA of FIG. 3; FIG. 5 is a block diagram showing a PLA for a micro-code of the present invention; and FIG. 6 is a circuit diagram showing a specific example of the PLA of FIG. 5. A PLA of the present invention will be explained with reference to the drawings. FIG. 5 shows a PLA for micro-code of the present invention. FIG. 6 shows a PLA having an AND typed AND array section as a specific example of FIG. 5. Reference numerals 11 to 14 denote first to four banks, respectively. A PLA area comprises the first to fourth banks 14. Each bank comprises a latch control section 20 to which an address input signal IR〈m〉 is inputted, an AND array section 21 for receiving the address input signal IR〈m〉 from the latch control section 20, an OR array section 22 to which an output signal of the AND array section 21 is inputted, and an OR array section 23 for a band selection control. Moreover, the OR array section 23 for a bank selection control comprises a NOR circuit for a bank selection control, and a bit line for a bank selection for outputting the output signal of the NOR circuit. The number of the bit lines is one when the number of the banks is two, the number of the bit lines is two when the number of the banks is four, and the number of the bit lines is three when the number of the banks is eight. In other words, the number of the bit lines depends on the number of banks. The NOR circuit of the OR array section 23 outputs a bank selection signal for designating by which bank a command of a cycle executing a next command is decoded. Reference numeral 24 is an output selector (multiplexer) for selecting an output signal from each bank to be fetched. Reference numeral 25 is an output register (latch circuit), which is provided at the output side of the output selector 24, and inputs a synch clock signal  to a latch signal input terminal LE. Reference numeral 26 is a bank selection signal latching circuit for latching two bank selection signals, which outputted from the output register 25, by the synch clock signal . The bank selection signal latching circuit 26 supplies a latch output signal to the output selector 24 as selector control signals BS1A, BS0A. Reference numerals 271 to 274 are precharge signals lines for inputting the synch clock , which is supplied from a clock input buffer circuit (not shown), to each bank as a precharge signal Pre. Reference numerals 281 to 284 are latch signal buffers, which are provided to correspond to the banks 11 to 14, respectively, for decoding bank selection signals BS1 and BS0 outputted from the output register 25, and supplying the decoded signals to the latch signal LE input terminal of the latch control section 20 of each corresponding band. Reference numerals 291 to 294 are discharge control signal buffers, which are provided to correspond to the banks 11 to 14, respectively, for Oring the latch signal LE and the precharge signal Pre, and supplying the discharge signal Dis to each of the banks 11 to 14. In each bank, the precharge signal Pre is supplied to the AND array section 21, the OR array section 22, and the OR array section 23 for the bank selection control. The discharge signal Dis is supplied to only the AND array section 21. The AND array section 21 comprises a plurality of NAND circuits arranged in a column direction X, and a plurality of inverter circuits 511, which inverts each of outputs of the plurality of the NAND circuits, and inputs these outputs to the OR array section 22. Each NAND circuit comprises one P channel MOS transistor 512 for precharge wherein a source is connected to a power supply voltage (Vcc) node, one N channel MOS transistor 514 for discharge wherein a source is connected to a ground voltage (Vss) node, and a plurality of N channel MOS transistors 513 connected in series between a drain of the P channel MOS transistor 512 and a drain of the N channel MOS transistor 514. The OR array section 22 comprises a plurality of NOR circuits arranged in a row direction Y, a word line extending in a row direction Y, and a decode output wire (bit line) extending in a column direction X. Each NOR circuit comprises one P channel MOS transistor 521 for precharge wherein a source is connected to a power supply (Vcc) node) and a plurality of N channel MOS transistors 522 wherein a drain is connected to a drain of the P channel MOS transistor 521 and a source is connected to a ground voltage (Vss) node. The OR array section 23 comprises two NOR circuits for bank selection. Each NOR circuit comprises one P channel MOS transistor 231 for precharge wherein a source is connected to a power supply (Vcc) node and one or more N channel MOS transistors 232 wherein a drain is connected to a drain of the P channel MOS transistor 231 and a source is connected to a ground voltage (Vss) node. Table 1 shows the relationship between the state of two bank selection signals BS1 and BS0 outputted from the output register circuit 25 of the PLA for micro-code and the selected bank. BS0 BS1 Bank 0 0 0 0 1 1 1 0 2 1 1 3 An operation of the PLA for micro-code of the present invention will be explained with reference to FIG. 5. If the synch clock signal  is set to "0" level, the PLA is set to the precharge mode, and if the synch clock signal  is set to "1" level, the PLA is set to the discharge mode. If the PLA is set to the precharge mode, all banks 11 to 14 are precharged, respectively. Then, a command code of the outer section of the PLA is latched by the latch circuit of one bank, which is selected by two bank selection signals BS1 and BS0 determined by the previous cycle. For example, if two bank selection signals are set to "0", the output signal of the buffer 281 is activated, so that the command code of the outer section of the PLA is latched by the latch circuit 20 of the first bank 11. Then, in the other banks 12 to 14, the latch circuit 20 maintains the command of the previous cycle. In the selected first bank 11, all input signals of one NAND circuit of the AND array section 21 are set to "1" level by the command code of the cycle this time. Next, if the PLA is set to the discharge mode, the output signal (discharge control signal) of the discharge control signal buffer 291 is activated. Therefore, in the first bank 11, the output signal of one NAND circuit in which all input signals are set to "1" level becomes "0" level since all N channel MOS transistors are turned on. The output signal of "1" level (for example, DECO) to the word lines of the OR array sections 22 and 23 by the inverter circuit. At this time, in the residual NAND circuits of the AND array section 21 of the first bank 11, at least one input signal is in "0" level. Due to this, the output signals of these NAND circuits are maintained to be "1" level (precharge level). Therefore, the output signal of "0" level is supplied to the word lines of the OR array sections 22 and 23 by the inverter circuit. On the other hand, in the OR array section 22 of the first bank 11, the output signal of the NOR circuit wherein at least one input signal is in "0" level is set to "0" level. For example, the bit line Bit0 of one NOR circuit is set to "0" level. Moreover, the word line to which the output signal of "1" level is supplied is also supplied to two NOR circuits for bank selection of the OR array section 23. Two bank selection signals BS1 an BS0 are outputted from two bit lines for bank selection signal output, which are connected to the two NOR circuits for bank selection. In the OR array section 22 of the first bank 11, in order that the output signal of the NOR circuit to which the input signal of "0" level is inputted is maintained to be "1" level (precharge level), the bit line of the NOR circuit (for example, Bit1, ...) is maintained to be "1" level. Then, two bank selection signals, which are determined by the previous cycle, are latched by the bank selection signal latch circuit 26 when the synch clock signal  is set to "0" level. The output selector 24 selects the decode output of the first bank 11 by the output signal of the bank selection signal latch circuit 26 (signal wherein two bank selection signals BS1A and BS0A, which are determined by the previous cycle, are shifted by a half clock of the synch clock signal ). Next, when the synch clock signal  is set to "0" level, the output of the output selector 24 is latched by the output register 25, and outputted as a PLA output OUT. In the second to fourth banks 12 to 14 other than the first bank 11, the output signals of all AND array section are set to "0" level, and all bit lines are maintained to be "1" level. According to the above-structured PLA, the PLA area is formed of a plurality of banks. Then, in each bank, there is provided bank selection data for determining by which bank the command code of the next cycle is decoded. Then, bank selection data is outputted every cycle, and a bank for decoding the command of the next cycle is selected. Also, in the next cycle, the fetching of the input signal and the discharging are performed in only the selected bank, and the operations of the other banks is stopped. Therefore, in the bank, which is not used in the next cycle, the input signal is unchanged, and no discharge is performed. Due to this, the consumption electrical power of the non-used bank is controlled to be substantially zero. Whereby, if the number of the bank divisions is n, the consumption electrical power is controlled to be 1/n as compared with the case that no bank division is performed. In the above embodiment, the AND typed AND array section was used, but the OR typed AND array section may be used. In this case, in the selected bank, the NOR circuit in which all inputs signal are set to "0" maintains "1" level (precharge level), and the other NOR circuits perform the discharge, and outputs "0" level. Moreover, the AND array section of each bank and the OR array section, no precharge is performed if it is needed. Also, the output selector may be provided on the bank so as to make the chip size of the integrated circuit smaller.

Claims: A programmable logic array characterized by comprising: a) a PLA area (20, 21, 22, 23) having a plurality of banks wherein each of said bank has an array of logic circuits being operated in either a precharge mode or discharge mode for decoding a micro-code, b) a control circuit (24, 25, 26, 271 to 274, 281 to 284, 291 to 294) for selecting one bank, characterized in that c) the PLA (20, 21, 22, 23) is adapted to receive a sync clock signal () defining operating cycles and further to input a command code to each bank every cycle for executing a predetermined command, d) each bank is adapted to output bank selection data to determine by which bank a command of a next operating cycle will be decoded at a previous operating cycle; e) the control circuit (24, 25, 26, 271 to 274, 281 to 284, 291 to 294) is adapted to decode the command code of the next operating cycle from said plurality of banks based on said bank selection data of each bank in the previous operating cycle and is further adapted to send a command code to only the selected one bank to perform discharge of related logic circuit in the discharge mode, thereby stopping operations of other banks. The programmable logic array according to claim 1, characterized in that each of said banks comprises: a latch control section (20) for inputting a command code thereto; an AND array section (21) for receiving an input signal from said latch control section; an OR array section (22) having a plurality of decode output OR circuits to which an output signal of said AND array section is input; and an OR array section (23) having at least one bank selection signal output NOR circuit; and said control circuit comprises an output selector (24) for selecting a decode output from each bank every bank to be fetched; an output register (25) for latching an output signal of said output selector based on a sync clock signal; a bank selection signal latch circuit (26) for latching a bank selection signal output from said output register based on the sync clock signal to be supplied to said output selector as a selector control signal; a precharge signal line (271 to 274) for supplying said sync clock signal to each of said bank as a precharge signal; a latch signal supply circuit (281 to 284), provided to each corresponding bank, for decoding the bank selection signal of said output register to be output as a latch signal of said latch control section; and a discharge control signal supply circuit (291 to 294), provided to each corresponding bank, for ORing said latch signal and said precharge signal to be supplied to each bank as a discharge signal.

Inventors: ANDO KAZUMASA, HORIE SYOJI, ANDO, KAZUMASA, HORIE, SYOJI, ANDO, KAZUMASA, C/O INTELLECTUAL PROPERTY DIVISION, HORIE, SYOJI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1994
Main classification: G06F9
IPC codes: H03K19, H01L21, G06F9