Circuit for preventing turn-on of parasitic components in integrated circuits including a power stage and low-voltage control circuitry

Abstract: The integrated circuit (1) includes at least a power stage (2); a low-voltage component separated from the power stage by an isolating region (7); and a reference potential region (S) at a reference potential (ground). The power stage includes an N-type substrate region (D) which may be biased to a terminal voltage (V D ) with respect to the reference voltage; the isolating region (7) presents P-type conductivity; and the low-voltage component comprises an N-type input region (6) connected electrically to an input voltage (V IN ). The input voltage (V IN ) and the terminal voltage (V D ) may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors (8-10). To prevent turning on of the parasitic transistors, switchable conductive paths (L₁-L₃) are interposed between the isolating region (7) on the one hand, and the substrate region (D), the input region (6) and the reference potential region (S) on the other, for electrically connecting the isolating region to the one of the substrate, input and reference potential regions which presents instant by instant the lowest potential.

Description: The present invention relates to a circuit for preventing turn-on of parasitic components in integrated circuits including a power stage and low-voltage control circuitry. As is known, present demand is for integrated devices incorporating in the same chip both a power stage (e.g. MOSFET power transistor, VDMOS) and the relative low-voltage drive circuits (e.g. comprising NMOS and PMOS transistors). In some applications, the drive voltage of such devices may oscillate between two fairly high values (a few tens of volts) symmetrical with respect to the reference voltage (ground), in which case the problem arises of maintaining the drive circuit components and the power stage isolated. For a clearer understanding of the problem, refer to Figure 1 showing an integrated device 1 comprising a power transistor (VDMOS) 2 and relative control circuitry (drive stage) 3. The drain terminal D of VDMOS 2 presents voltage V D , its source terminal S is grounded, its gate terminal G is driven by drive stage 3, and 4 indicates the relative parasitic diode. In the case in question, power transistor 2 presents N + -type source and drain regions. Of the drive stage are shown only an input terminal 5 supplied with input voltage V IN (oscillating drive voltage); an N + -type region 6 connected to input terminal 5 (and forming part of any component, e.g. constituting the collector region of an NPN transistor); and a P + -type isolating region 7 surrounding and isolating region 6 from the substrate connected to or constituting the drain region of VDMOS 2. Figure 1 also shows two parasitic NPN transistors 8, 9 and a parasitic PNP transistor 10, which are associated with the Figure 1 structure as shown more clearly in the example implementation in Figure 2. Figure 2 shows a cross section of a silicon wafer including an N + -type substrate 11, and an N - -type epitaxial layer 12 forming with substrate 11 the drain region of VDMOS 2. To the left is shown VDMOS 2 including N + -type source regions 15, polysilicon gate regions 16 embedded in insulating layer 17, and metal source line 18. To the right is shown a CMOS component (including in known manner an N-channel and a P-channel MOS transistor) formed in a well comprising a P-type buried layer 20. P + -type regions 22, 23 provide for isolating the various components. More specifically, region 22 encloses and isolates the low-voltage components, corresponds to region 7 in Figure 1, and separates an N-well layer 24 and a P-well layer 25 over buried layer 20. N-well layer 24 presents an N + -type region 29; and P + -type regions 26 constituting the drain and source of the PMOS transistor and located beneath gate region 27 embedded in dielectric layer 28. P-well layer 25 presents N + -type regions 30 constituting the drain and source of the NMOS transistor and located beneath gate region 31 embedded in dielectric layer 32. Metal lines 33 contact the NMOS and PMOS transistor regions in the usual way. In the Figure 2 implementation, the N + -type regions (e.g. regions 29, 30) form parasitic diodes together with isolating region 22, and, together also with epitaxial layer 12 and substrate 11, form parasitic NPN transistors like 8 and 9 in Figure 1. In fact transistors 8, 9 present the base connected to isolating region 7, the emitter, respectively the collector connected to N + -type region 6, and the collector, respectively the emitter connected to the drain region of VDMOS 2. Moreover, region 23 (connected electrically to source region 15 by metal line 18) and regions 12 and 22 form a parasitic transistor like 10 in Figure 1. In fact such a parasitic transistor presents the collector connected to isolating region 7, the base connected to drain terminal D, and the emitter connected to source terminal S of VDMOS 2. With such a structure, isolating region 7 (22) cannot be grounded when drive voltage V IN is negative; in that case, in fact, if one of regions 29 or 30 is connected to voltage V IN , the aforementioned diode (formed by said region 29 or 30 and isolating region 22) would be biased directly, and the transistor (8 in Figure 1) formed by said regions and epitaxial layer 12 would be turned on. Similarly, isolating region 22 cannot be connected directly to input voltage V IN in that, when voltage V IN is positive, the parasitic diode formed by isolating region 22 and epitaxial layer 12 would be biased directly, and the parasitic transistor (9 in Figure 1) formed by the parasitic diode and the N + region connected to voltage V IN would be turned on, thanks also to the current injected by transistor 10 which is turned on when voltage V D is negative. If isolating region 22 were to be grounded, parasitic transistor 9 would also be turned on with a negative voltage V D . A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action is disclosed in US-A-5,051,612. It is an object of the present invention to provide a circuit for appropriately biasing the isolating region and so preventing the parasitic components of the integrated circuit from being turned on. According to the present invention, there is provided a circuit for preventing turn-on of parasitic components in integrated circuits including a power stage and low-voltage control circuitry, as claimed in Claim 1. In practice, according to the invention, the isolating region is connected instant by instant to the lowest-potential point via switches driven by the integrated circuit voltages. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a diagram of an integrated device to which the present invention applies; Figure 2 shows a cross section of a wafer of semiconductor material in which some of the components of the Figure 1 integrated device are implemented in known manner; Figure 3 shows an operating diagram of the circuit according to the present invention; Figures 4 and 5 show more detailed diagrams of the circuit according to the invention in two different operating conditions; Figure 6 shows a possible implementation of some of the Figure 3 circuit components; Figure 7 shows an alternative implementation of some of the Figure 6 components. Number 40 in Figure 3 indicates a circuit for preventing turn-on of parasitic components; circuit 40 is housed in the same integrated device 1 including power VDMOS 2 and relative drive circuit 3. Of drive circuit 3 are shown the N + -type region 6 connected to input terminal 5 and biased to voltage V IN , and isolating region 7. Circuit 40 comprises three switches S 1 , S 3 , S 2 located along respective connecting lines L 1 , L 2 , L 3 interposed between isolating region 7 and, respectively, the drain terminal of VDMOS 2, the source terminal of VDMOS 2, and region 6 (i.e. input terminal 5). Switches S 1 -S 3 are so driven as to connect isolating region 7 instant by instant to the lowest-potential point as shown in the Table below. V IN V D S 1 S 2 S 3 + - CLOSED OPEN OPEN - + OPEN CLOSED OPEN + + OPEN OPEN CLOSED 0 + OPEN OPEN CLOSED 0 - CLOSED OPEN OPEN Consequently, when the drain terminal of VDMOS 2 presents a negative potential (with a positive or zero input voltage V IN ), switch S 1 (the only one closed) connects isolating region 7 to the drain terminal; when input voltage V IN is negative (and drain voltage V D is positive), switch S 2 connects isolating region 7 to input terminal 5; and when drain voltage V D is positive and input voltage V IN is positive or zero, switch S 3 grounds isolating region 7; so that parasitic transistors 8 and 9 can never be turned on. One circuit embodiment of switches S 1 -S 3 including bipolar transistors and Schottky diodes is shown in Figures 4 and 5 wherein the components are turned around to show more clearly the behaviour of the circuit in two different operating conditions. In both Figures 4 and 5, switch S 1 may be represented by transistor T1, switch S 2 by Schottky diode D2, and switch S 3 by Schottky diode D3; and to ensure correct operation of the circuit, this also presents a further two Schottky diodes D4, D5, and a resistor R. More specifically, NPN transistor T1 is shown turned upside down in Figures 4 and 5 to take into account the different voltage conditions involved. In Figure 4, transistor T1 presents the collector terminal connected to isolating region 7 (shown as a line), the emitter terminal connected to drain terminal D of VDMOS 2, and the base terminal connected to node 45; Schottky diode D2 presents the anode connected to isolating region 7, and the cathode connected to input terminal 5; and Schottky diode D3 presents the anode connected to isolating region 7, and the cathode grounded. Node 45 is grounded via Schottky diode D4 (with its anode connected to node 45), and is connected to input terminal 5 via a resistor R and Schottky diode D5. Resistor R and diode D5 are connected parallel to each other, with the anode of D5 connected to node 45. Figures 4 and 5 also show two parasitic transistors 47 and 48 associated with the Schottky diodes. For a clearer understanding, refer to Figure 6 showing a possible implementation of part of circuit 40. More specifically Figure 6 shows a cross section of a wafer of semiconductor material in which the components are implemented using the same technology as in Figure 2, and wherein any parts common to both Figures 6 and 2 are shown using the same numbering system. Figure 6 shows the implementation of transistor T1 and one of the Schottky diodes. More specifically, transistor T1 is implemented by a vertical transistor including a P-type buried region 50 (forming the base region) separated from buried region 20 in which the CMOS components are formed and in which the Schottky diodes may be formed. Over buried region 50, there is provided an N-well 51 isolated by an isolating region 52 to be connected electrically to node 45 by base contacts 53 and metal lines (not shown). N-well 51 houses an N + -type region 55 connected to isolating region 22 by contact 56 and a metal line (not shown). The Schottky diode implemented over buried region 20 comprises an N-well 60 isolated from the other well regions 24, 25 by a portion of isolating region 22, and housing an N + -type region 61. Region 61 is connected to a contact 62 for connection (for example) to input terminal 5 (diodes D2, D5) or ground (diodes D3, D4); while N-well 60 is connected to a contact 63 (with which it forms a Schottky barrier) connected, for example, to isolating region 22 (diodes D3, D5) or to node 45 (diodes D4, D5). Regions 51 and 55 constituting the collector of transistor T1 are formed simultaneously with N-well regions 24, 25, 60 and N + -type regions 29, 30, 61. As can be seen, the Schottky diode is associated to a parasitic transistor formed by regions 61, 60 (emitter or collector), 22, 20 (base) and 12, 11 (collector or emitter). Consequently, Figure 4 diodes D3 and D4 are associated to transistors 47, 48 having the emitter formed by regions 11, 12 in Figure 6, the base formed by isolating region 22, and the collector formed by region 61. Similarly, diodes D2 and D5 are associated to respective parasitic transistors similar to parasitic transistor T1 and therefore not shown. In Figure 4, circuit 40 is shown with a positive input voltage V IN and a negative drain voltage V D . In this condition transistor T1 is turned on (saturated) and, like switch S 1 in Figure 3, maintains isolating region 7 at a potential close to drain voltage V D . As such, parasitic transistor 9 "sees" a very low base-emitter voltage drop which is insufficient to turn it on despite the charges injected by parasitic transistor 10. In the above operating condition, diodes D3, D2 and D5 are reverse biased; diode D4 is turned on and biases the base of T1; and, being insufficiently biased like parasitic transistor 9, parasitic transistors 47 and 48 are also turned off. Diode D4 and resistor R ensure that, during the falling half wave of voltage V D , transistor T1 is turned on before parasitic transistors 9, 10, thus preventing parasitic transistors 9, 10 from being turned on. In fact, T1 "sees" a slightly higher base-emitter voltage drop - equal to V D + V F (where V F is the voltage drop over diode D4) - than transistor 10 which sees a base-emitter voltage drop equal to V D . Consequently, as V D falls, and thanks also to resistor R supplying the base of transistor T1, T1 is turned on in advance of transistor 10, thus preventing any problems arising as V D falls. Figure 5 shows the Figure 4 circuit modified to illustrate the behaviour of the circuit with a negative input voltage V IN and a positive drain voltage V D . In Figure 5, parasitic transistor 8, which is the one likely to be turned on in the above bias condition, is shown in place of parasitic transistor 9; and transistors T1 and 47 are turned upside down (exchanging the collector for the emitter) to show the possible turn-on condition. In Figure 5, T1 also represents the parasitic transistor associated with diodes D2 and D5 (as in Figure 4) and the parasitic transistor associated with D3 (as in Figure 4) and D4 (the parasitic transistor of D4 in fact presents a grounded emitter, a base formed by isolating region 7, and a collector formed by layers 11, 12, in exactly the same way as transistor 47). In the Figure 5 operating condition, parasitic transistor 8 is prevented from being turned on by Schottky diode D2 maintaining isolating region 7 at a voltage close to input voltage V IN (roughly 0.2 V higher) and so producing an insufficient voltage drop at the base-emitter junction of transistor 8 (which requires 0.6-0.7 V for it to be turned on). Moreover, in the Figure 5 operating condition, D3, D5 and the relative parasitic transistors are turned off. D3 in fact is reverse biased, as is the base-emitter junction of the associated parasitic transistor 47. The same also applies to diode D4, whereas D5 is turned on and maintains the base of T1 at the same potential as the emitter, so that T1 remains off (as required, particularly in the case of a high drain voltage V D , for preventing failure of transistor T1). Finally, parasitic transistor 10 is also turned off, by virtue of its base presenting a higher potential as compared with the emitter and collector. In the Figure 4 and 5 circuits, diode D3 provides for grounding isolating region 7 when input voltage V IN and drain voltage V D are both positive, or when one is zero and the other is positive. In all these cases, diode D3 is turned on and maintains isolating region 7 at the minimum potential present in the circuit; and transistors 8, 9 and T1 are maintained off. Circuit 40 is easily implementable, for example, using the solutions shown in Figure 6. In particular, the resistor may be integrated using the polysilicon layer forming the gates of the MOSFET transistors (27 and 15 in Figure 6), or exploiting the diffused drain/source regions of the same MOSFET transistors, or by defining a higher-resistivity P-type diffused layer in a region isolated from the power stage. Figure 7 shows a possible implementation of diodes D2, D3 and transistor T1 using the same technique as in Figure 6. Any elements common to both are therefore indicated using the same numbering system with no further description. Number 70 in Figure 7 indicates the P-type buried layer over which the diodes are formed, and over which are provided two N-well regions 71, 72 separated by isolating regions 73 similar to regions 22, 23, 52. N-well regions 71, 72 house N + -type regions 74, 75 for connection to contacts 76, 77, and are directly contacted by aluminium contacts 78, 79 for forming the Schottky diodes of which regions 71, 72 form the cathodes. Contacts 78, 79 (diode anodes) are connected by a metal line 80 for electrically contacting the anodes of Schottky diodes D2 and D3. The Figure 7 implementation is characterized by a P + -type ring 81 in N-well region 71, surrounding contact 78 and which provides for increasing the breakdown voltage of diode D2. In fact, if the breakdown voltage of the Schottky diodes is below the maximum input voltage V IN value, the potential of isolating region 7 (anode of diode D2) is unable to follow V IN , thus impairing operation of the device as a whole. The above breakdown voltage, as is known, is limited by the rapid increase in the electric field along the periphery of the metal-semiconductor interface; which problem, however, can be solved by forming a guard ring, such as ring 81, connected to the anode of the diode and located along the edge of the Schottky junction. The advantages of the circuit described are as follows. Firstly, tying the isolating regions instant by instant to the lowest potential prevents the junction between the drain region of the power VDMOS and the isolating regions from being turned on and so impairing operation of the integrated device. Secondly, the circuit is easily integrated, and presents a high degree of reliability. Clearly, changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention as defined by the appended claims. In particular, the switches may be formed using other components, the implementation shown being provided purely by way of example.

Claims: A circuit (40) for preventing turn-on of parasitic components (8, 9, 10) in an integrated circuit (1) including at least a power stage (2), a low-voltage component separated from said power stage by an isolating region (7, 22), and a reference potential region (S, 15) which may be biased at a reference potential (ground); said power stage comprising an N-type substrate region (D, 11, 12) which may be biased to a terminal voltage (V D ) with respect to said reference potential; said isolating region (7, 22) presenting P-type conductivity; and said low-voltage component comprising an N-type input region (6) which may be biased at an input voltage (V IN ) ; characterized in that it comprises switchable conductive paths (L 1 -L 3 ) electrically connected between said isolating region (7) on the one hand, and said substrate region (D, 11, 12), said input region (6) and said reference potential region (S, 15) on the other, for electrically connecting at every moment said isolating region to the region among said substrate, input and reference potential regions, which presents the lowest potential. A circuit as claimed in Claim 1, characterized in that said switchable conductive paths (L 1 -L 3 ) each comprise a controlled switch (S 1 -S 3 ). A circuit as claimed in Claim 2, characterized in that said controlled switches (S 1 -S 3 ) are voltage controlled. A circuit as claimed in Claim 3, characterized in that it comprises a first switch (S 1 ) having a first terminal connected to said isolating region (7) and a second terminal connected to said substrate region (D), for electrically connecting said isolating region to said substrate region when said input voltage (V IN ) is greater than or equal to said reference potential and said terminal voltage (V D ) is less than said reference potential. A circuit as claimed in Claim 4, characterized in that said first switch (S 1 ) is a transistor (T1) having a control terminal connected to said reference potential region (S). A circuit as claimed in Claim 5, characterized in that said transistor (T1) is a bipolar transistor. A circuit as claimed in Claim 6, characterized in that said transistor is a vertical transistor having said second terminal formed by said substrate region (11, 12). A circuit as claimed in one of the foregoing Claims from 5 to 7, characterized in that it comprises a low-voltage-drop diode (D4) electrically connected between said control terminal of said transistor (T1) and said reference potential region (S). A circuit as claimed in Claim 8, characterized in that it comprises a bias resistor (R) electrically connected between said input region (6) and said control terminal of said transistor (T1). A circuit as claimed in any one of claims 5 to 9, characterized in that it comprises a low-voltage-drop diode (D5) electrically connected between said control terminal of said transistor (T1) and said input region (6), for maintaining said transistor off when said input voltage (V IN ) is less than, and said terminal voltage is greater than, said reference potential. A circuit as claimed in any one of claims 3 to 10, characterized in that it comprises a second switch (S 2 ) electrically connected between said isolating region (7) and said input region (6), for electrically connecting said isolating region to said input region when said input voltage (V IN ) is less than, and said terminal voltage (V D ) is greater than, said reference potential. A circuit as claimed in Claim 11, characterized in that said second switch (S 2 ) is a low-voltage-drop diode (D2). A circuit as claimed in any one of claims 3 to 12, characterized in that it comprises a third switch (S 3 ) electrically connected between said isolating region (7) and said reference potential region (S), for electrically connecting said isolating region to said reference potential region when said input voltage (V IN ) is greater than or equal to, and said terminal voltage (V D ) is greater than, said reference potential. A circuit as claimed in Claim 13, characterized in that said third switch (S 3 ) is a low-voltage-drop diode (D3). A circuit as claimed in any one of claims 8 to 14, characterized in that said low-voltage-drop diodes (D2-D5) are Schottky diodes. A circuit as claimed in Claim 15, wherein each of said Schottky diodes (D2-D5) is formed by a Schottky junction between a semiconductor region (71) and a metal electrode (78), which respectively form an anode and a cathode region; wherein each said Schottky diode has a P-type guard ring (81) connected electrically to its anode region and surrounding its semiconductor region (71) along the edge of the Schottky junction. A circuit as claimed in any one of the foregoing claims, wherein said power stage comprises a MOSFET power transistor (2) having a drain (D) and a source (5) region, said substrate region (11, 12) forming the drain region (D) of said MOSFET power transistor; and said reference potential region being connected to the source region (S) of said MOSFET power transistor.

Inventors: PALARA SERGIO, ZAMBRANO RAFFAELE, PALARA, SERGIO, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CONSORZIO PER LA RICERCA SULLA, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H01L27
IPC codes: H03K17, H01L27, H01L29