ANTIFUSE STRUCTURE WITH INCREASED BREAKDOWN AT EDGES

Abstract: An antifuse is provided which includes a first conductive layer (101), an antifuse layer (106, 107, 108) formed on the first conductive layer, and a second conductive layer (109) formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Description: ANTIFUSE STRUCTURE WITH INCREASED BREAKDOWN AT EDGES CROSS REFERENCE TO RELATED APPLICATION This application is a continuation-in-part of U.S. Patent Application Serial No. 07/933,428, entitled "Antifuse Structure and Method for Forming", filed August 21, 1992 (Atty.Doc.No. M-2164) . BACKGROUND OF THE INVENTION Field of the Invention This invention relates to antifuses, and in particular to an antifuse structure with an increased breakdown at the edges of an antifuse layer. Description of the Related Art Antifuses are well known in the art. An antifuse is a structure which is non-conductive when manufactured, but becomes permanently conductive by applying a predetermined voltage across its terminals. Antifuses are typically used in programmable logic devices to programmably interconnect conductive lines. Figures 1A-1D illustrate a conventional method of forming an antifuse. Referring to Figure 1A, a polycrystalline silicon layer 11 is formed on substrate 10 to provide a lower conductive terminal for the antifuse. An insulation layer 13 is then deposited and patterned to partially expose polycrystalline silicon layer 11 as shown in Figure IB. Referring to Figure 1C, an amorphous silicon layer 14 is then deposited and patterned to cover the exposed portion of polycrystalline silicon layer 11 and portions of insulation layer 13 adjacent to polycrystalline silicon layer 11. Referring to Figure ID, conductive layers 18, including titanium layer 15, titanium nitride layer 16, and aluminum-silicon layer 17, are formed over amorphous silicon layer 14, and then patterned (not shown) to form an upper conductive terminal. However, antifuse 20 requires a relatively high voltage, typically 12-14 volts, to program. Standard transistors used in 5-volt integrated circuit systems typically break down between 12-14 volts. Thus, special processing is needed to enhance the breakdown characteristic of the transistors for programming the antifuse. Moreover, to ensure proper operation of the integrated circuit system, other structures in the system must be isolated from the antifuse programming voltages. Furthermore, antifuse 20 is undesirably affected by internal temperatures generated during programming. Specifically, during programming of antifuse 20, the leakage current of this device increases with the increase in applied voltage. Eventually, the leakage current focuses on a localized weak spot in amorphous silicon layer 14. A thermal runaway condition then develops which results in localized heating and, eventually, filament formation between the upper conductive terminal and the lower conductive terminal. The different thermal expansion coefficients of the materials in different layers of the antifuse structure in turn cause stresses to develop in the material as it cools after programming. Over time, these stresses will relax, producing movement between layers of the antifuse material. Figure 2A shows a partial top view of antifuse 20 after programming in which filament 19 joins titanium layer 15 (Figure ID) and polysilicon layer 11. Note that Figure 2A illustrates an edge 21 of amorphous silicon layer 14 that contacts polycrystalline silicon layer 11. As described above, stress relaxation occurs within amorphous silicon layer 14, not at its boundaries. Therefore, referring to Figure 2B, if shearing occurs in prior art antifuse 20 due to stress relaxation, the sheared portion 19' of filament 19 significantly reduces the surface area 19A for conducting current, thereby resulting in instability of the resistance provided by antifuse 20. Therefore, a need arises for an antifuse which programs at a relatively low programming voltage and ensures a stable resistance irrespective of shearing conditions . SUMMARY OF THE INVENTION In accordance with the present invention, an antifuse comprises a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and again with the second conductive layer. This "double corner" formation of the antifuse layer enhances the electric field during programming. Thus, the resulting filament, i.e. the conductive path between the first and second conductive layers formed during programming, consistently forms along this corner. The present invention provides advantages under shearing conditions due to stress relaxation that typically occur within the programmed antifuse structure. Specifically, because a filament in accordance with the present invention is formed at one of the boundaries of the antifuse, not within the antifuse structure, the filament is substantially unaffected by shearing conditions caused by stress relaxation. Therefore, an antifuse in accordance with the present invention provides a stable resistance even under stress relaxation conditions. Furthermore, in contrast to the prior art antifuses which have a programming voltage of 12-14 volts, an antifuse in accordance with the present invention has a programming voltage of 8-9 volts. Thus, ordinary transistors which break down at 12-14 volts can be used both for programming antifuses and for logic functions. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A-1D illustrate one method of forming a conventional antifuse. Figure 2A shows a partial view of the conventional antifuse illustrated in Figure ID after programming. Figure 2B shows a partial view of the conventional antifuse illustrated in Figure ID after shearing occurs. Figures 3A-3J illustrate one method of forming an antifuse in accordance with the present invention. Figure 4 shows a partial view of the antifuse illustrated in Figure 3J after programming. DETAILED DESCRIPTION OF THE DRAWINGS Figures 3A-3J illustrate the steps to provide one embodiment of an antifuse in accordance with the present invention. Referring to Figure 3A, a conductive layer 101, approximately 4500A to 7000A thick, is formed on substrate 100. In this embodiment of the present invention, conductive layer 101 includes two layers, bottom layer 101A and top layer 101B. The bottom layer 101A is aluminum (Al) having a thickness of approximately 3500A to 6500A. The top layer 101B is titanium-tungsten (TiW) having a thickness of approximately lOOOA to 3000A. Layer 10IB is formed on top of layer 101A to prevent the diffusion of aluminum into a to-be-formed amorphous silicon layer (shown in Figure 3H) . In other embodiments, bottom layer 101A is aluminum-silicon (AISi) or aluminum-silicon-copper (AlSiCu) and top layer 101B is titanium-nitride (TiN) . In yet other embodiments of the present invention, conductive layer 101 is formed solely from titanium-tungsten (TiW) . Conductive layer 101 forms the lower conductive terminal (hereinafter lower conductive terminal 101) of the to-be-formed antifuse. After formation of this lower conductive terminal, a layer of undoped oxide, for example silicon dioxide, is deposited at a temperature of about 400°C to a thickness of approximately 15,000A. This oxide serves as a sacrificial oxide during the subsequent planarization process. Specifically, as shown in Figure 3A, a photoresist layer 102A is deposited on layer 102. Then, an etch removes photoresist layer 102A and approximately 9,000A to 11,000A of oxide layer 102. As is well known in the art, photoresist layer 102A forms a planar surface on the somewhat irregular surface of oxide layer 102. Etching of thinner portions of photoresist occurs more rapidly than thicker portions of photoresist. Thus, after removal of photoresist layer 102A and a portion of oxide layer 102, a substantially planar surface is provided on oxide layer 102 as shown in Figure 3B. Referring to Figure 3C, after the oxide etch, another oxide layer 103, approximately 8000A thick, is deposited at a temperature of about 400°C to a thickness between 9,000A and 10,000A on oxide layer 102 to ensure adequate isolation between lower conductive terminal 101 and the to-be-formed upper conductive terminal . Then, a photoresist layer 104 is deposited and patterned as shown in Figure 3D. A subsequent isotropic etch forms the opening 105A which is shown in Figure 3E. Typically, this isotropic etch uses a conventional, diluted HF solution which etches down approximately 5500A to 7500A. In one embodiment of the present invention, the HF solution etches down 6500A. In other embodiments, other etching processes, such as a plasma etch, are used to provide the angle 140, typically 40 degrees, which is measured from the beginning of the slope (point 140A) to the end of the slope (point 140B) . This angle ensures good step coverage of the to-be-formed antifuse layer and the upper conductive layer in opening 105A. Referring to Figure 3F, an anisotropic etch removes a portion of oxide layer 103 and oxide layer 102, thereby exposing lower conductive terminal 101. In this embodiment, the anisotropic etch is a plasma etch including a mixture of Freon-23 (CHF 3 ) and oxygen (0 2 ) at approximately 25°C. This anisotropic etch provides the via 105B. Subsequent to via definition, an oxygen plasma treatment is performed. During this oxygen plasma treatment, the temperature of the antifuse structure rises from approximately 25°C to approximately 125°C. The combination of elevated temperature and reactive oxygen plasma produces an oxide layer 106 on lower conductive terminal 101 in via 105B as shown in Figure 3G. Oxide layer 106 is typically an oxide of the material of lower conductive terminal 101. Thus, oxide layer 106 is either titanium oxide, tungsten oxide, or a mixture of titanium oxide and tungsten oxide. In this embodiment, oxide layer 106 is between 35A and 7θA thick. Then, referring to Figure 3H, an amorphous silicon layer 107 is deposited in via 105B as well as areas adjacent to via 105B. Amorphous silicon layer 107 is typically deposited to a thickness of between 350A and 550A to ensure that this deposition follows the contour of via 105B. In one embodiment of the present invention, amorphous silicon layer 107 is 450A thick and is formed by using pure silane gas (SiH 4 ) at a temperature of 300°C and a pressure of 250 mTorr. In another embodiment, a mixture of silane gas and nitrogen (N 2 ) at a temperature of 300 "C is used to produce amorphous silicon layer 107. In that embodiment, amorphous silicon layer 107 has a typical nitrogen content (measured by number of atoms) of between 10% to 20%. To improve the amorphous nature of amorphous silicon layer 107, i.e. break up any small crystals and reduce leakage, an argon implant, not shown, is performed at a dosage of lxlO 16 atoms/cc and an energy of 30 keV. Other implant dopants such as silicon, oxygen, or arsenic are alternatively used in other embodiments. Then, a photoresist layer (not shown) is deposited and patterned to define the edge 107A of the antifuse. An anisotropic etch etches the exposed portions of amorphous silicon layer 107, thereby providing the edges 107A shown in Figure 3H. Subsequent to this anisotropic etch, another oxygen plasma treatment is performed, thereby forming a silicon dioxide layer 108 approximately 10-30A thick which covers amorphous silicon layer 107 as shown in Figure 31. Finally, an upper conductive terminal 131 is formed using conventional methods In one embodiment shown in Figure 3J, upper conductive terminal 131 includes a titanium layer 109, a titanium- tungsten layer 110, and an aluminum-silicon-copper alloy layer 111. In other embodiments, upper conductive terminal 131 is formed from consecutive layers of titanium, titanium- nitride, titanium-tungsten, or consecutive layers of aluminum (formed on amorphous silicon layer 107) , aluminum- silicon, and aluminum-silicon-copper. In the embodiment of the present invention shown in Figure 3H, antifuse 130 typically needs a programming voltage between 7.5 and 10 volts to form a conductive filament 132 which connects upper conductive terminal 131 and lower conductive terminal 101. Because standard transistors can withstand this low antifuse programming voltage, transistors in the antifuse structure can be small, density is high, and no special transistor processing steps are needed. Moreover, a prior art antifuse having a typical length of 1500A provides an undesirably high resistance value on the order of 150Ω. In contrast, the short length, i.e. approximately 350A to 550A, of conductive filament 132 provides a significantly lower resistance value of approximately 50Ω. Furthermore, a prior art antifuses exhibits an unstable resistance value at stress current close to the programming current. A more detailed explanation of this phenomena is described in an article entited, "Antifuse Structure Comparison for Field Programmable Gate Arrays" by S. Chiang et al., IEEE IDEM, pages 611-614, 1992, which is herein incorporated by reference in its entirety. In contrast, an antifuse in accordance with the present invention provides a stable resistance value both under low current stress and under DC current stress close to the programming current over a time period of more than 1,000 hours. As described above, the present invention provides that a portion of the composite antifuse layer, i.e. oxide layer 106, amorphous silicon layer 107 and oxide layer 108, forms a substantially orthogonal angle with the lower conductive terminal 101 and the upper conductive terminal 131. This "double corner" formation of the composite antifuse layer enhances the electric field at this location during programming, thereby ensuring a predictable location, and therefore resistance, of filament 132. Furthermore, the present invention provides advantages under shearing conditions due to stress relaxation in the programmed antifuse. Specifically, stress relaxation typically occurs within a structure, not at its boundaries. Therefore, referring back to Figure 2B, if shearing occurs in prior art antifuse 20, the sheared portion 19' of filament 19 significantly reduces the surface area 19A for conducting current, thereby resulting in instability of the resistance provided by antifuse 20. In contrast, filament 132 of the present invention which is formed at one of the boundaries of antifuse 130 is substantially unaffected by shearing conditions caused by stress relaxation. Therefore, an antifuse in accordance with the present invention provides a low, stable resistance even under the above- described adverse conditions. Therefore, the antifuse of the present invention provides the following advantages: a predictable location of the antifuse filament, minimal shearing effects on the filament, a relatively low programming voltage, and a low, stable resistance value. The above description of the present invention is meant to be illustrative only and not limiting. Other embodiments will be apparent to those skilled in the art in light of the detailed description. The present invention is set forth in the appended claims .

Claims: CLAIMS We claim: 1. An antifuse comprising: a first conductive layer; an antifuse layer formed on said first conductive layer; and a second conductive layer formed on said antifuse layer, wherein a portion of said antifuse layer forms a substantially orthogonal angle with said first conductive layer and said second conductive layer. 2. The antifuse of Claim 1 wherein said antifuse layer includes an amorphous silicon layer. 3. The antifuse of Claim 2 wherein said amorphous silicon layer has a thickness between 350A and 550A. 4. The antifuse of Claim 3 wherein said amorphous silicon layer has a thickness of approximately 450A. k 5. The antifuse of Claim 2 wherein said antifuse layer further includes a first oxide layer formed between said first conductive layer and said amorphous silicon layer. 6. The antifuse of Claim 5 wherein said first oxide layer is formed from said first conductive layer. 7. The antifuse of Claim 5 wherein said first oxide layer has a thickness between 35A and 70A. 8. The antifuse of Claim 5 wherein said first oxide layer is titanium oxide. 9. The antifuse of Claim 5 wherein said first oxide layer is tungsten oxide. 10. The antifuse of Claim 5 wherein said first oxide layer is a combination of titanium oxide and tungsten oxide. 11. The antifuse of Claim 5 wherein said antifuse layer further includes a second oxide layer formed between said amorphous silicon layer and said second conductive layer. 12. The antifuse of Claim 11 wherein said second oxide layer is a silicon dioxide layer. 13. The antifuse of Claim 11 wherein said second oxide layer has a thickness between lOA and 30A. 14. The antifuse of Claim 11 wherein said second oxide layer completely insulates said amorphous silicon layer from said second conductive layer. 15. The antifuse of Claim 1 wherein said first conductive layer forms a lower conductive terminal of said antifuse. 16. The antifuse of Claim 15 wherein said first conductive layer includes a conductive metal. 17. The antifuse of Claim 16 wherein said conductive metal includes aluminum. 18. The antifuse of Claim 16 wherein said conductive metal includes an aluminum-silicon alloy. 19. The antifuse of Claim 16 wherein said conductive metal includes an aluminum-silicon-copper alloy. 20. The antifuse of Claim 16 wherein said conductive metal includes titanium. 21. The antifuse of Claim 16 wherein said conductive metal includes titanium nitride. 22. The antifuse of Claim 16 wherein said conductive metal includes titanium tungsten. 23. The antifuse of Claim 1 wherein said second conductive layer forms an upper conductive terminal of said antifuse. 24. A method of forming an antifuse comprising the steps of: forming a first conductive layer on a substrate; forming an antifuse layer on said first conductive layer; and forming a second conductive layer on said antifuse layer, wherein said antifuse layer forms a substantially orthogonal angle with each of said first conductive layer and said second conductive layer.

Inventors: LOOK KEVIN T, WOLSHEIMER EVERT A, LOOK, KEVIN, T., WOLSHEIMER, EVERT, A.
Applicants: XILINX INC, XILINX, INC.
Application year: 1994
Main classification: H01L23
IPC codes: H01L21, H01L23