Method of forming isolation trenches in integrated circuits

Abstract: The invention concerns the fabrication of oxide-filled isolation trenches in integrated circuits. A network of trenches is etched in the surface of a uniformly doped wafer which has experienced no substantial processing steps. Such a wafer will have little, if any, surface damage. Such a wafer will etch to the same depth everywhere, because two major factors which affect etching rate are (a) surface damage and (b) doping non-uniformity, and these factors are absent. The trenches are then filled with oxide. They define islands upon which devices (such as transistors) may now be fabricated.

Description: This invention relates to a method of forming isolation trenches in a semiconductor substrate. Figure 1 is highly simplified, and illustrates nine CELLs contained in an integrated circuit (IC). (Interconnections between the CELLs are not shown.) Each CELL contains a completed device, such as a transistor (not shpwn), which must be electrically insulated from neighbouring CELLS. The insulation is indicated by the empty SPACES, positioned between the devices, and which make up the gridwork 3, indicated in phantom. Points A, B, C, and D indicate corresponding locations. Gridwork 3 indicates that empty spaces, located in the substrate, are used as insulation. However, in fact, the spaces are not actually empty, but contain structures which facilitate insulation. (One reason for using these structures, rather than merely the silicon which forms the substrate, is that, for a given consumption of area, higher insulation values can be obtained from the structures than from silicon itself.) Several different types of structure are used. One approach is the use of junction isolation, as shown in Figure 2. A PN junction, formed between a P+ and N region, is held in a reverse-biased condition, and acts as an extremely high resistance, or insulator. Another approach, shown in Figure 3, is to use TRENCHes filled with specific dielectrics, which act as insulators. The TRENCHes can be configured into the pattern of the gridwork 3 in Figure 1. The structure labeled 6 in Figure 3 undergoes further processing, as indicated, in order to form a completed device. Yet another approach is shown in Figure 4, wherein V-GROOVEs are used. A specific type of V-groove approach is shown in the sequence of Figure 5. In Figure 5A, deep V-GROOVEs are etched into the surface of <100> silicon. An N+ diffusion is undertaken, followed by growth of a silicon dioxide layer on the surface, producing the N+ region and the silicon dioxide layer shown in Figure 5B. In Figure 5B, a thick layer of polysilicon is deposited upon the silicon dioxide. Then, the back (ie, the bottom part of the wafer shown in Figure 5B) is abraded away in a lapping process. The wafer is then flipped over, and transistors are fabricated on the new surface S which was created by the lappping operation, resulting in the structure shown in Figure 5C. The prior art approaches of Figures 3, 4, and 5, produce deep trenches (ie, deeper than 1.0 µm). In some fabrication processes, very shallow isolation trenches are required (eg, in the range of 0.1 - 0.3 µm in depth). Further, these shallow trenches must have uniform depths, because they are later filled with oxide, and the finished oxide must be level with the surface of the wafer. For example, as a rough approximation, assume that, during a given oxidation step, all shallow trenches in a given wafer become filled with the same depth of oxide, namely, a depth of 0.1 µm. If a TRENCH is too deep, as Figure 6 illustrates, the oxide will not reach the SURFACE of the wafer. On the other hand, if a TRENCH is too shallow, the oxide will form a mound above the SURFACE, as Figure 6 indicates. Both cases fail to meet the requirements: in neither case is the oxide level with the SURFACE. Thus, variations in trench depth cause the oxide to be non-level with the SURFACE, and cause problems in yield and reliability. Depth variations are caused by numerous factors, which affect the chemical etching process by which the trenches are formed. One factor is surface damage in the etched region. Particle implantation causes surface damage. Thus, the etching rate will probably be different in a region where implantation has occurred, as compared with a non-implanted region. Consequently, the same etching step will produce trenches of different depths in the two regions. Other factors include the following three: (1) conductivity of the material to be etched, (2) the dopant type of the material to be etched, and (3) the dopant concentration of the material to be etched. If one or more of these factors differ in two different regions of the wafer, the regions will probably experience different etch rates. Again, the same etching step will produce trenches of different depths in the two regions. Therefore, as a specific example, if a trench is etched into a wafer containing both an N-type region and a P-type region, as shown in Fig. 7, the trench will probably have different depths in the two regions, as indicated. This depth variation is unacceptable for the use of shallow trench isolation. The document S.C. Arney et al "Formation of submicron silicon-on-insulator structures by lateral oxidation of substrate-silicon islands", 31st International Symposium on Electron, Ion, and Photon Beams, Woodland Hills, Ca, US, 26-29 May 1987, ISSN 0734-211X, Journal of Vacuum Science & Technology B (Microelectronics Processing and Phenomena), vol,6, No. 1 (Jan.-Feb. 1988), US, pages 341 - 345, XP002027995 relates to the formation of relatively deep trenches in a silicon substrate and which deep trenches are arranged to serve as isolation features. Also, the document A.J. Jimenez: "Recessed oxide isolation having a planar surface", IBM Technical Disclosure Bulletin, US, vol.26, No. 9 (Feb. 1984), pages 4787 - 4788, ISSN 0018-8689, XP002027996 likewise discloses the provision of a recessed isolation pattern in a silicon substrate but when the recess formed are relatively deep. Neither of the aforementioned prior art documents address or identify problems that can become prevalent when forming relatively shallow isolation trenches. An object of the invention is to provide a trench formation process in integrated circuits capable of creating shallow trenches of uniform depth. Therefore, according to the present invention, there is provided a method of fabricating an integrated circuit, comprising forming isolation trenches in a uniformly doped substrate prior to any device formation steps that would result in the said substrate having differently doped regions, wherein the trenches have a uniform shallow depth in the range of 0.05 to 0.3 µm, the shallow depth being uniform within the range ± 10%. One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:- Figure 1 illustrates isolation between CELLS in an integrated circuit. Figure 2 illustrates junction isolation. Figure 3 illustrates trench isolation. Figure 4 illustrates V-groove isolation. The sequence of Figures 5A - 5C illustrate a specific type of V-groove isolation. Figure 6 illustrates how trenches of different depths produce different oxide configurations. Figure 7 illustrates how an N- type region can etch differently than does a P-type region. Figure 8 illustrates a sequence of processing steps used by the invention. Figure 9 illustrates a system of shallow trenches which the invention produces. The trenches are contained in a wafer in which no other structures have been fabricated. Referring now to Figure 8, a layer of silicon dioxide, and a layer of silicon nitride are applied to a wafer, using known process steps. A pattern of PHOTORESIST is applied. The PHOTORESIST defines the areas which are to be protected from etching. That is, each photoresist island PR covers a cell which will eventually contain a device. Such CELLs are shown in Figure 1. The structure 9 of Figure 8 is subjected to an etch, which produces the structure 10 having the TRENCHes indicated. Suitable etchants are known in the art. Field oxide is grown in the TRENCHes of structure 10, producing structure 11. Growth of field oxide is known in the art. The photoresist islands PR, the silicon nitride layers, and the silicon dioxide layers are removed, as indicated by the phantom lines in structure 11. The phantom lines show the relative locations of oxide growth. The resulting structure 11 is shown at the lower right part of Figure 8, without the phantom islands and layers. In one embodiment, the CELLS are laid out on a cartesian grid, uniformly spaced, thereby locating the shallow trenches between the CELLS. In other embodiments, the layout of the CELLs will depend on the specific integrated circuit to be ultimately fabricated, and the layout of the shallow trenches will not be on a cartesian grid, but will accommodate the layout of the CELLS. It will be appreciated that a trench system, shown in Figure 9, is produced, which is uniform in depth, because the substrate which was subjected to the etching process is uniform in characteristics: no fabrication steps (apart from possible cleaning) have been taken. There is no implantation damage, nor differential in doping or in conductivity across the substrate. Typically, a manufacturer of ICs purchases wafers from a supplier; the manufacturer, in general, does not produce its own wafers. Figure 9 shows a wafer on which a shallow trench system has been fabricated. The shallow trench system is the first structure fabricated on the wafer received from the supplier, prior to any other structures. These wafers arrive from the supplier in a nearly defect-free condition. The surfaces are highly polished, and almost flawless. The IC manufacturer uses such wafers directly for IC fabrication without further preparation (apart from possible cleaning). The quality of such wafers is called "incoming wafer quality." The invention applies the shallow-trench-fabrication steps outlined above to such wafers, before implantation and before other changes in doping are undertaken. Forming the trenches prior to implantation avoids the problems of etching implant-damaged surfaces. Also, forming the trenches prior to other doping changes avoids the problems of etching a surface containing regions which differ in (a) conductivity, (b) dopant type, or (c) dopant concentration. It is not necessary that no processing steps whatsoever be undertaken prior to fabrication of the trenches. For example, processing steps such as nitridation and oxidation can be tolerated. However, prior to applying the inventive steps to the wafer, the wafer is preferably subjected to no temperatures higher than 950°C. Further, if the wafer is subjected to temperatures in excess of 900°C, then for no longer than one hour. The trenches are fabricated upon a substrate having uniform conductivity and uniform doping. The doping was achieved by a diffusion process, so that implantation damage is not present. This doping is generally undertaken by the wafer supplier, although diffusion by the IC manufacturer is not precluded. The phrase "incoming wafer quality" was used above, to described the surface of the wafer being processed. Some parameters for defining the quality of this surface are the following: A. Incoming wafers, or a sample of an incoming batch, are commonly etched, in a test procedure, or as part of an initial cleaning procedure. If a defect is present, such as a stacking fault, the etching will decorate the defect, causing it to stand out. A maximum of one defect per square centimeter is allowed. Later processing will probably induce defects which exceed this limit. B. Another parameter is based on the fact that implantation causes the objectionable damage. The shallow trenches shown in Figure 9 are formed in a wafer which has experienced substantially no implantation. Implantation damage can be annealed out, but not completely. Thus, it is preferred that the SHALLOW TRENCHes in Figure 9 be fabricated in surfaces which have experienced no implantation damage, or, at least, in surfaces in which no substantial implantation damage remains. C. Another parameter is the requirement that no processing has been undertaken which would cause surface defects, in excess of the number identified in (A), above, nor scratches. D. The incoming wafers can contain a layer of epitaxial silicon. In this case, the UNIFORMLY DOPED SILICON in Figure 8 represents an epitaxial layer. The trenches of the invention can be fabricated in this layer. The epitaxial layer must meet the defect limit stated in (A), above. It is noted that epitaxial deposition can be a high temperature process, exceeding the time-temperature limits stated in (1), above. Epitaxial deposition is an exception to these limits. Also, epitaxial deposition is a fabrication step. Thus, when an epitaxial layer is used, the shallow trenches are not the first structures fabricated on the wafer. As stated above, shallow trenches are formed, which typically lie in the range of 0.05 to 0.3 µm deep, and are, certainly, no deeper than 0.5 µm. In contrast, deep trenches are defined in the art as exceeding 1.0 µm. One form of the invention produces the precursor structure shown in Figure 9. The precursor contains ISLANDS, which correspond to the CELLs of Figure 1. Each ISLAND-CELL of Figure 9 will later contain one or more devices (such as transistors) of which the overall integrated circuit will be comprised. The ISLANDS are isolated from each other by the SHALLOW TRENCHes, which are filled with oxide (or other dielectric) in a later processing step. The concept of uniform depth in trenches was discussed above. A variation in depth of ten percent, or less, qualifies a depth as "uniform." For example, a trench which is nominally 0.1 µm deep must be no deeper than 0.11µm, and no shallower than 0.09µm. It should be understood that the term "filling" in relation to "filling" trenches with oxide is used in a non-technical sense, and does not specify a particular method of oxide formation. The fabrication steps for the devices to be located in the ISLANDS shown in Figure 9 will certainly require masking. The term "masking" is known in the art, and includes the selective hardening of a material, or resist, by selective exposure to light, to electrons, or to some other energy source. The hardened parts are resistant to etching, and protect the underlying material. The shallow trench system is fabricated prior to this masking. Even though the shallow trench system itself involves a masking step, this masking step is prior to any others.

Claims: A method of fabricating an integrated circuit, comprising forming isolation trenches in a uniformly doped substrate prior to any device formation steps that would result in the said substrate having differently doped regions, wherein the trenches have a uniform shallow depth in the range of 0.05 to 0.3 µm, the shallow depth being uniform within the range ± 10%. A method according to Claim 1, characterized by the steps of filling said isolation trenches with an insulator material. A method according to Claim 2, characterized in that said step of forming isolation trenches includes the steps of forming, on said substrate, an insulator layer, forming, on said insulator layer, a masking layer, pattering said masking layer, and etching the regions exposed by said patterning step through said insulator layer and into said substrate. A method according to Claim 3, characterized in that said step of forming an insulator layer includes the steps of forming on said substrate, a first layer of silicon dioxide, and forming on said first layer, a second layer of silicon nitride. A method according to Claim 3 or Claim 4, characterized by the step of removing the patterned masking layer and underlying insulator layer material. A method according to any one of the preceding claims, wherein said substrate includes an epitaxial layer. A method according to any one of the preceding claims, characterized by the step of forming devices in substrate regions isolated by said trenches.

Inventors: CHIACCHIA CHRISTINE H, KELLEHER PATRICK J, MCCORMACK STEPHEN R, CHIACCHIA, CHRISTINE H., KELLEHER, PATRICK J., MCCORMACK, STEPHEN R.
Applicants: HYUNDAI ELECTRONICS AMERICA, NCR INT INC, SYMBIOS INC, NCR INTERNATIONAL, INC., SYMBIOS, INC.
Application year: 1994
Main classification: H01L21
IPC codes: H01L21