MOS transistor switch without body effect

Abstract: MOS-transistor switch without body effect comprising a pair of p-channel transistors (M1, M2) inserted in series between two connection terminals (A, B) and a third transistor (M3) with n-channel which is inserted between a connection node of the pair and a minimum potential reference (VSS) and a fourth transistor (M4) with n-channel in parallel with the pair of transistors (M1, M2). The substrates of the transistors of the pair are connected to the connection terminals (A, B). The substrate both of the third transistor (M3) and the fourth transistor (M4) is connected to the potential reference (VSS).

Description: The present invention relates to the switching circuitry means for integrated circuits and specifically to an electronic switch for low-voltage supply circuits integrated with CMOS technology. The switching circuitry means are indispensable in various integrated circuit applications such as, for example, switched capacitor circuits for filters with reduced harmonic distortion in which the electronic switches realized with MOS transistors are driven by distinct timing signals without superimposed phases. A rather simple type of electronic switch commonly used by those skilled in the art is the so-called 'pass-transistor' consisting of two complementary CMOS transistors connected in mutual parallel with their respective source and drain terminals and driven by signals in phase opposition upon switching. Said switch does not exhibit shortcomings in integrated circuits with sufficiently high power supply voltage on the order of at least 5V. But when the supply voltage is lower, typically around 3V, as is the present trend for many integrated circuits, it is necessary to take in consideration what in the technical literature is known as 'body' effect where the term 'body' indicates the actual substrate of a transistor. Indeed, in any CMOS process one of the two complementary transistors is provided in its own substrate called well or tub. For example, in a N-well CMOS process it is the p-channel transistor which is provided of an independent substrate defined N-well and vice versa for the P-well CMOS process. As known to those skilled in the art, the actual threshold voltage upon conduction of the transistors of an integrated circuit of the CMOS type depends on the 'body' effect in accordance with which the actual threshold voltage VTH of a transistor increases in absolute value when the voltage VSB between source and body of the transistor is other than zero, i.e. if the transistor substrate is not short-circuited with the source region and is the highest when the source region is insulated from the substrate. For the best operation of a pass-transistor the n-channel transistor substrate is kept at the lowest potential existing in the integrated circuit while the substrate of the p-channel transistor is kept at the highest potential. If the supply voltage is too low, for certain voltages values, at the two ends of the switch it may be impossible, due to the body effect, to switch to conduction at least one of the two transistors which constitute the pass-transistor and thus permit correct operation of the switch. As explained in the article 'Higher Sampling Rates in SC Circuits by On-Chip Clock-Voltage Multiplication' by F. Krummenacher, H. Pinier and A. Guillaume - Laboratoire d'électronique général, EPFL, Lausanne, Switzerland - the solution used by those skilled in the art is that of driving the switch transistors with signals in 'voltage-boosted' phase opposition, i.e. having amplitude almast doubled with respect to the value of the power supply voltage. Correct operation of the switch is thus assured even with low supply voltages, but this solution involves the shortcoming of requiring a complicated circuit for generation of the voltage-boosted driving signals. The technical problem underlying the present invention is thus that of providing an electronic switch with MOS transistors which permits avoiding the shortcomings due to body effect while keeping circuitry simplicity. The technical problem is solved by an electronic switch of the type set forth above and defined in the characterising part of the claims which follow this description. The characteristics and advantages of the electronic switch in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings. In the drawings: FIGS. 1, 2, 3 and 4 show possible circuit diagrams for an electronic switch in accordance with the present invention for integrated circuits with CMOS processes of the classical type, and FIGS. 5 and 6 shows circuitry diagrams for an electronic switch in accordance with the present invention for integrated circuits with CMOS processes of the 'twin-tub' type. An electronic switch in accordance with the present invention is provided by making use of the fact that in any CMOS process one of the two transistors is achieved in its own substrate with conductivity opposite that of the actual substrate in which is provided the other transistor. By utilising the circuitry diagrams displayed in the figures and appropriately connecting the substrates of the complementary transistors contained in said diagrams to maximum potential and minimum potential references of the integrated circuit there are obtained in accordance with the same inventive concept electronic switches free of 'body' effect. In the diagram of FIG. 1 are included a first and second p-channel transistors M1 and M2 inserted in mutual series by means of the source and drain terminals between two connection terminals A and B. A third transistor, M3, with n channel, is inserted between a connection node of the transistors M1 and M2 and a minimum potential reference VSS of the integrated circuit comprising the electronic switch in accordance with the present invention. A fourth transistor, M4, also with n channel, is inserted between the connection terminals A and B in parallel with the transistors M1 and M2 by means of the source and drain terminals. The substrate of the transistor M1 and the substrate of the transistor M2 are connected to the switch connection terminals A and B respectively. The substrate of the transistors M3, M4 are connected to the potential reference VSS. The transistor M4 through the gate terminal is driven with a ø signal in phase opposition both with the transistors M1 and M2 driven with a ø signal applied to their gate terminals and to the transistor M3 driven by the same ø signal but through an inverter. FIG. 2 shows a dual case with opposite polarities in which the reference VDD is a maximum potential reference in the integrated circuit. In the diagram shown in FIG. 3 the transistor M3 is with p channel instead of n channel and therefore its substrate, differently from the diagram shown in FIG. 1, is connected to a maximum potential reference VDD in the integrated circuit and not to the minimum potential reference VSS. The transistor M3 must also be driven in phase opposition in relation to the transistors M1 and M2. The substrates of the transistors M1 and M2 are connected to the connection node between said transistors and the transistor M3. FIG. 4 shows a dual case with polarities opposite those of FIG. 3. The circuitry diagrams shown in FIGS. 1, 2, 3 and 4 comprise a single transistor M4 in parallel with the other two M1 and M2 This is the simplest solution with the normal CMOS integration processes. However, with the 'twin tub' CMOS integration processes, such as for example generally those of the Bi-CMOS type, the single transistor M4 can be replaced with another pair of transistors in series mutually and with a connection node coupled to a potential reference through a transistor as for the first pair. FIGS. 5 and 6 show the possible circuits. The principal characteristics of the present invention are that the substrates of the transistors connected in series are each connected to a terminal of their own transistor in every operating condition thus avoiding the so-called 'body' effect and that the transistor inserted between the transistor pair and the potential reference prevent inappropriate charge injections when the switch is open. Although not indispensable, the use of an inverter to pilot the latter transistor (M3) with the signal ø and not the signal ø ensures its starting only after turning off of the transistor pair in series. Of course modifications and variations can be made to the device described above by way of nonlimiting example within the scope of the following claims.

Claims: Electronic switch for a low-voltage supply circuit integrated on a semiconductor substrate with CMOS technology and having at least a first (A) and a second (B) connection terminal and comprising a first transistor (M4) having a first and a second terminal and a control terminal and being inserted with said first and second terminals between said first and second connection terminals and characterised in that it comprises a second transistor (M1), a third transistor (M2) and a fourth transistor (M3) each having a first and a second terminal and a control terminal and the second transistor (M1) and the third transistor (M2), of a type complementary to that of the first transistor, being inserted between said first and second connection terminals in mutual series each by means of its own first and second terminal, and the fourth transistor (M3) being inserted by means of its own first and second terminals between a connection circuitry node between the second and third transistors and a first potential reference (VSS) and in that the fourth transistor (M3) has a substrate connected to said first potential reference (VSS) and each of said second transistor (M1) and third transistor (M2) has a substrate connected to the first terminal of the same transistor. Electronic switch in accordance with claim 1 characterised in that the fourth transistor (M3) is the same type as the first transistor (M4) and the second transistor (M1) and third transistor (M2) are connected together each by means of its own second terminal. Electronic switch in accordance with claim 2 characterised in that the first and fourth transistors are n-channel, the second and third transistors are p-channel and the potential of the first reference is equal to the lowest potential in the integrated circuit. Electronic switch in accordance with claim 2 characterised in that the first and fourth transistors are p-channel, the second and third transistors are n-channel, and the potential of the first reference is equal to the highest potential in the integrated circuit. Electronic switch in accordance with claim 1 characterised in that the fourth transistor (M3) is the type complementary to that of the first transistor (M4) and the second transistor (M1) and the third transistor (M2) are connected together each by means of its own first terminal. Electronic switch in accordance with claim 5 characterised in that the first transistor is n-channel, the second, third and fourth transistors are p-channel and the potential of the first reference is equal to the highest potential in the integrated circuit. Electronic switch in accordance with claim 5 characterised in that the first transistor is p-channel, the second, third and fourth transistors are n-channel and the potential of the first reference is equal to the lowest potential in the integrated circuit. Electronic switch in accordance with any one of claims 2, 3 and 4 and characterised in that the first transistor is driven by signals in phase opposition in relation to those which drive the second, third and fourth transistors. Electronic switch in accordance with claim 8 characterised in that it comprises an inverter circuit whose output is coupled to the control terminal of the fourth transistor and to whose input are applied the same signals which drive the first transistor. Electronic switch in accordance with any one of claims 5, 6 and 7 and characterised in that the first and the fourth transistors are driven by signals in phase opposition in relation to those which drive the second and third transistors. Electronic switch in accordance with claim 10 characterised in that it comprises an inverter circuit whose output is coupled to the control terminal of the fourth transistor and to whose input are applied the same signals by which are driven the second and third transistors. Electronic switch for a low-voltage supply circuit integrated on a semiconductor substrate with CMOS technology and having at least a first and a second connection terminals (A, B) characterised in that it comprises a first and a second transistor each of which has a first and a second terminal and a control terminal and which are inserted in mutual series each with its own first and second terminals between said first and second connection terminals and a third and a fourth transistor each of which has a first and a second terminal and a control terminal and are the type complementary to that of the first and second transistors and are inserted in mutual series each with its own first and second terminals between said first and second connection terminals and in that it comprises a fifth and a sixth transistor of the same type as the third and first transistors respectively and each having a first and a second terminal and a control terminal and the fifth transistor being inserted by means of the first and second terminals between a first potential reference (VDD) and a first circuitry node for connection between the first and second transistors and the sixth transistor being inserted by means of the first and second terminals between a second circuitry node for connection between the third and fourth transistors and a second potential reference (VSS) and in that the first and third transistors have substrates connected to the first connection terminal and the second and fourth transistors have substrates connected to the second connection terminal and the fifth and sixth transistors have substrates connected to the first and second potential references respectively. Electronic switch for a low-voltage supply circuit integrated on a semiconductor substrate with CMOS technology and having at least a first and a second connection terminals (A, B) and characterised in that it comprises a first and a second transistor each of which has a first and a second terminal and a control terminal and which are inserted in mutual series each with its own first and second terminals between said first and second connection terminals and a third and a fourth transistor each of which has a first and a second terminal and a control terminal and are the type complementary to that of the first and second transistors and are inserted in mutual series each with its own first and second terminals between said first and second connection terminals and in that it comprises a fifth and a sixth transistor of the same type as the third and first transistors respectively and each having a first and a second terminal and a control terminal and the fifth transistor being inserted by means of the first and second terminals between a first potential reference (VSS) and a first circuitry node for connection between the first and second transistors and the sixth transistor being inserted by means of the first and second terminals between a second circuitry node for connection between the third and fourth transistors and a second potential reference (VDD) and in that the first and second transistors have substrates connected to the first connection circuitry node and the third and fourth transistors have substrates connected to the second connection circuitry node and the fifth and sixth transistors have substrates connected to the first and second potential references respectively. Electronic switch in accordance with claim 12 characterised in that the first, second and fifth transistors are driven by signals in phase opposition in relation to those by which are driven the third, fourth and sixth transistors. Electronic switch in accordance with claim 13 characterised in that the first, second and sixth transistors are driven by signals in phase opposition in relation to those by which are driven the third, fourth and fifth transistors.

Inventors: CONFALONIERI PIERANGELO, NICOLLINI GERMANO, CONFALONIERI, PIERANGELO, NICOLLINI, GERMANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H03K17
IPC codes: H03K17, H01L27, H01L21