Semiconductor device having capacitor and manufacturing method thereof

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer, which covers the capacitor, and has a passivation layer which covers the interconnections of the capacitor. The passivation layer is composed of a phospho-silicate layer and a non-doped silicate layer formed sequentially from the interconnections side. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor device having ferroelectric layer or high dielectric layer as capacitor dielectric layer and a manufacturing method thereof. BACKGROUND OF THE INVENTION Recently, along with the trend of higher speed and lower power consumption of semiconductor device such as microcomputer and digital signal processor, electronic appliances for consumer use are more and more advanced in performance, while an electromagnetic interference which is an electromagnetic noise generated from these electronic appliances is posing a serious problem. Accordingly, not only in electronic appliances, but also in semiconductor devices used in them, measures against electromagnetic interference are demanded. The most effective measure against electromagnetic interference in the semiconductor device is to install a capacitor of a large capacitance between the bias line and ground line inside the semiconductor device, hitherto the capacitor was placed outside the semiconductor device. In addition, lately, nonvolatile random access memories in a simple construction having a capacitor, using a ferroelectric layer as capacitor dielectric layer, and dynamic random access memories having a capacitor using dielectric layer of high dielectric constant as storage capacitor have been developed. A conventional semiconductor device having capacitor is specifically described below. Fig. 1 is a partially sectional view of a representative semiconductor device. In Fig. 1, on a silicon substrate 1, an integrated circuit 6 represented by source/drain active areas 3, a gate oxide 4, and a gate electrode 5 is formed in a region enclosed by a field oxide area 2. Further on the silicon substrate 1, an insulating layer 7 is formed, and in a specific region on the insulating layer 7, a capacitor 11 consisting of a bottom electrode 8, a capacitor dielectric layer 9, and a top electrode 10 is formed. At least covering the capacitor 11, moreover, an interlayer insulating layer 12 is formed. There are also formed interconnections 14a connected to the source/drain active areas 3 through a first contact hole 13a, interconnection 14b connected to the bottom electrode 8 of the capacitor 11 through a second contact hole 13b, and interconnection 14c connected to the top electrode 10 of the capacitor 11 through a third contact hole 13c. Furthermore, a passivation layer 15 is formed in order to protect the interconnections 14a, 14b, 14c. A manufacturing method of the conventional semiconductor device having capacitor shown in Fig. 1 is explained below while referring to the flow chart of manufacturing process shown in Fig. 2, together with Fig. 1. First, at step (1), the integrated circuit 6 is formed on the silicon substrate 1. At step (2), an insulating layer 7 is formed on a silicon substrate 1. At step (3), a capacitor 11 is formed on the insulating layer 7. This capacitor 11 is formed by sequentially laminating a first conductive layer as bottom electrode 8, capacitor dielectric layer 9, and a second conductive layer as top electrode 10, and patterning respectively by etching. As the capacitor dielectric layer 9, a ferroelectric layer or high dielectric layer is used, and as bottom electrode 8 and top electrode 10, a two-layer composition consisting of platinum layer and titanium layer sequentially from the side contacting with the capacitor dielectric layer 9 is used. At step (4), an interlayer insulating layer 12 composed of PSG (phospho-silicate glass) is formed by CVD so that at least the capacitor 11 is covered. At step (5), a first contact hole 13a reaching the source/drain active areas 3 of the integrated circuit 6, a second contact hole 13b reaching the bottom electrode 8 of the capacitor 11, and a third contact hole 13c reaching the top electrode 10 of the capacitor 11 are formed. After forming interconnections 14a, 14b, 14c at step (6), a passivation layer 15 composed of silicon nitride layer or silicon oxynitride layer of high humidity resistance is formed by plasma CVD at step (7). However, in such conventional semiconductor device having capacitor, a PSG layer is used as interlayer insulating layer 12, and although the purpose of alleviating the stress to the capacitor 11 is achieved, the moisture generated when forming the PSG layer by CVD is absorbed by the PSG layer, and this moisture diffuses into the ferroelectric layer composing the capacitor dielectric layer, thereby lowering the electric resistance. This phenomenon gives rise to increase of leakage current of the capacitor 11 or decline of dielectric strength, which may induce dielectric breakdown of the capacitor dielectric layer 9. Yet, in such conventional semiconductor device having capacitor, as a passivation layer 15, silicon nitride layer or silicon oxynitride layer formed by plasma CVD is used, and although invasion of moisture from outside into the capacitor 11 may be prevented, activated hydrogen is generated in the layer forming process by plasma CVD, and this activated hydrogen may diffuse in the ferroelectric layer or high dielectric layer for composing the capacitor dielectric layer 9, which may induce increase of leakage current of the capacitor 11 or deterioration of electrical characteristic. Generally, the hydrogen atom content in the nitride layer formed by plasma CVD is as high as 10 22 atoms/cm 3 , and by heat treatment after layer forming, diffusion of hydrogen into the capacitor dielectric layer 9 is accelerated, and the characteristic of the capacitor 11 is further degenerated. EP-A-514 547 discloses a capacitor with a passivation layer according to the preamble of claim 1. SUMMARY OF THE INVENTION It is hence a primary object of the invention to present a semiconductor device according to claim 1 having capacitor with high reliability. It is other object thereof to present a manufacturing method according to claim 3 of such semiconductor device without deteriorating the integrated circuit formed on a semiconductor substrate. In the semiconductor device of the invention, as the passivation layer which covers the interconnections, a PSG layer (phospho-silicate glass layer) and NSG layer (non-doped silicate glass layer) are laminated sequentially from the interconnection side. According to the constitution, different from the silicon nitride layer or silicon oxynitride layer formed by the conventional plasma CVD, since hydrogen is not contained in the passivation layer, the capacitor dielectric layer will not deteriorate. Besides, the stress relaxation on the capacitor can be prevented by the PSG layer, and the moisture absorption which is a demerit of the PSG layer can be prevented by the NSG layer formed thereon, so that stress may not be applied on the capacitor, thereby realizing a high reliability. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partially sectional view showing the structure of principal parts of a conventional semiconductor device having capacitor. Fig. 2 is a flow chart for explaining a conventional manufacturing method of semiconductor device having capacitor. Fig. 3 is a partially sectional view showing the structure of principal parts of a semiconductor device having capacitor in Example 1. Fig. 4 is a flow chart for explaining a manufacturing method of a semiconductor device having capacitor in Example 1 of the invention. Fig. 5 is a diagram showing the temperature dependence of moisture release amount from PSG layer. Fig. 6 is a diagram showing the electrical reliability of the semiconductor device having capacitor in Example 1. Fig. 7 is a partially sectional view showing the structure of principal parts in a semiconductor device having capacitor in Embodiment 1 of the invention. Fig. 8, Fig. 9, and Fig. 10 are partially sectional views showing a manufacturing method of semiconductor device having capacitor in Embodiment 1 of the invention, in which Fig. 8 is a diagram showing the state of forming a capacitor on an insulating layer of a semiconductor substrate in which an integrated circuit is formed, forming an interlayer insulating layer on the capacitor, and forming contact holes, Fig. 9 is a diagram showing the state of forming the interconnections, and Fig. 10 is a diagram showing the state of forming two passivation layers to protect the interconnections. Fig. 11 is a partially sectional view showing the structure of principal parts of a semiconductor device in Embodiment 2 of the invention. Fig. 12 and Fig. 13 are partially sectional views showing a manufacturing method in Embodiment 2, in which Fig. 12 is a diagram showing the state of forming a second passivation layer possessing an opening corresponding to capacitor after forming interconnections, and Fig. 13 is a diagram showing the state of forming two passivation layers for protecting the interconnections. DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention shown in Fig. 7 is a modified example of Example 1 shown in Fig. 3. Before to describe the semiconductor device the invention, we will describe the semiconductor of Example 1. Example 1 In the semiconductor device shown in Fig. 3, an isolation oxide layer 32 is formed on a silicon substrate 31, and an integrated circuit 36 represented by a transistor composed of a diffusion region 33, a gate insulating layer 34, and a gate electrode 35 is formed in a region enclosed by the isolation oxide layer 32. On the silicon substrate 31, an insulating layer 37 composed of silicon oxide layer is formed, and a capacitor 41 comprising a bottom electrode 38 of platinum layer and titanium layer, a capacitor dielectric layer 39 composed of ferroelectric layer or high dielectric layer, and a top electrode 40 composed of platinum layer and titanium layer is formed on the insulating layer 37. Covering this capacitor 41, an interlayer insulating layer 42 composed of a PSG layer having the moisture content of 0.5g or less per 1 cm 3 is formed. In the conventional semiconductor device having capacitor, the moisture content of the interlayer insulating layer was 0.9g or more per 1 cm 3 . Above the integrated circuit 36, a first contact hole 43a reaching a diffusion region 33 is formed in the insulating layer 37 and interlayer insulating layer 42, and above the capacitor 41, a contact hole 43b reaching the bottom electrode 38 and a third contact hole 43c reaching the top electrode 40 are formed in the interlayer insulating layer 42. Through the first contact hole 43a, an interconnection 44a composed of aluminum layer or aluminum alloy layer connected to the diffusion region 33 is formed, and through the second and third contact holes 43b, 43c, interconnections 44b, 44c composed of aluminum layer or aluminum alloy layer connected to the bottom electrode 38 and top electrode 40 are formed. To protect these interconnections 44a, 44b, 44c, a passivation layer 45 composed of silicon nitride layer or silicon oxynitride layer is formed. According to such constitution of Example 1, in the interlayer insulating layer 42, the moisture content is controlled under 0.5g per 1 cm 3 , and if heated in the subsequent steps, diffusion of moisture into the capacitor dielectric layer 39 can be prevented, thereby preventing increase of leakage current and a drop in dielectric strength of the capacitor 41, so that a semiconductor device having the capacitor 41 hardly inducing trouble due to dielectric breakdown as compared with the prior art may be realized. A manufacturing method of such semiconductor device is explained below while referring to the flow chart of manufacturing method shown in Fig. 4, together with Fig. 3. First, at step (1), an integrated circuit 36 and others are formed on a silicon substrate 31. At step (2), an insulating layer 37 is formed on the silicon substrate 31. At step (3), a capacitor 41 is formed on the insulating layer 37. This capacitor 41 is formed by sequentially laminating a first conductive layer as bottom electrode 38, a capacitor dielectric layer 39, and a second conductive layer as top electrode 40, and patterning respectively by etching. As the capacitor dielectric layer 39, a ferroelectric layer or high dielectric layer is used, and as the bottom electrode 38 and top electrode 40, a two-layer composition consisting of a platinum layer and a titanium layer sequentially from the side contacting with the capacitor dielectric layer 39 is used. At step (4), the capacitor 41 is heated to enhance and stabilize the characteristic of the capacitor dielectric layer 39. At step (5), at least covering the capacitor 41 by CVD or the like, an interlayer insulating layer 42 composed of PSG layer (photo-silicate glass layer) is formed, and at step (6), the interlayer insulating layer 42 is heated in a nitrogen atmosphere, and the moisture contained in the interlayer insulating layer 42 is removed to not more than 0.5g per 1 cm 3 of the interlayer insulating layer 42. At step (7), a first contact hole 43a reaching the diffusion region 33 of the integrated circuit 36, and second and third contact holes 43b and 43c reaching the bottom electrode 38 and top electrode 40 of the capacitor 41 are formed. At step (8), interconnections 44a, 44b, 44c are formed, and at step (9), a passivation layer 45 composed of silicon nitride layer or silicon oxynitride layer high in humidity resistance is formed by plasma CVD. In the foregoing constitution and manufacturing method, the PSG layer is formed as interlayer insulating layer 42 by CVD, and the moisture is removed from the PSG layer in a subsequent heat treatment process, but it is not limited to this, and for example, a silicon oxide layer may be formed in a condition of high temperature and reduced pressure, and heat treatment may be omitted. In the manufacturing method described above, heat treatment of the interlayer insulating layer 42 at step (6) in Fig. 4 is conducted in nitrogen gas, but it may be also done in inert gas such as helium and argon, or in vacuum. Results of measurement of moisture adsorption of PSG layer formed by CVD are explained below by reference to Fig. 5. The abscissa in Fig. 5 denotes the temperature, and the ordinate represents the amount of moisture released at the corresponding temperature, and their relation corresponds to the intensity of moisture adsorption. As shown in Fig. 5, the peak temperature of the adsorbed moisture releasing from the PSG layer is 300 to 350°C in a first peak, and 450 to 530°C in a second peak. The moisture corresponding to the second peak is adsorbed to the PSG layer with a sufficiently strong adsorption, and it seems to hardly affect the reliability in normal use. By contrast, the first peak drags its foot down to the low temperature side, and water is released in a condition relatively close to operating temperature, and it seems to induce deterioration of the capacitor dielectric layer 39. It is preferable to heat at 350°C or higher in order to release the adsorbed water corresponding to the first peak in Fig. 4 right after forming the layer by CVD. Furthermore, as the interlayer insulating layer 42, heat treatment of silicon oxide layer containing phosphorus by 6 wt.% or less is found to be preferred also for lessening the stress applied to the capacitor 41. Besides, the above heat treatment is performed at a not higher temperature than temperature giving rise to deterioration of a characteristic of the integrated circuit. The deterioration generally occurs at about 900 °C. It is preferable to heat at about 850°C or lower. The result of evaluation of reliability of the capacitor 41 manufactured as above is shown in Fig. 6. As the capacitor dielectric layer 39, barium strontium titanate was used. The abscissa denotes the inverse number of electric field applied to the capacitor 41, and the ordinate represents the time until the leakage current reaches a specific value. Line (a) shows the leakage current while applying a voltage to the capacitor 41 manufactured by a conventional method, and the moisture content of the PSG layer used as interlayer insulating layer 42 was 0.93 g/cm 3 . Line (b) relates to the result of the capacitor 41 manufactured as above, and the moisture content of the PSG layer as interlayer insulating layer 42 was 0.45 g/cm 3 . By comparing these lines, it has been proved that this capacitor 41 lower in the moisture content of the interlayer insulating layer 42 is superior by far as compared with the conventional example. Incidentally, the moisture content in the PSG layer may be 0.5 g/cm 3 or less. After forming and heating the interlayer insulating layer 42, the contact holes 43a, 43b, 43c are formed, but the sequence of heat treatment may be changed in the order of formation of interlayer insulating layer 42, formation of contact holes 43a, 43b, 43c, and heat treatment. In such a case, the contact holes 43a, 43b, 43c serve as vent holes, and moisture adsorbed on the capacitor 41 is released easily. The interlayer insulating layer 42 is heated once, but the heat treatment may be divided in plural steps. For example, a first heat treatment may be given after forming the interlayer insulating layer 42, and a second heat treatment after forming the contact holes 43a, 43b, 43c. In this case, the heat treatment condition may be varied between the first and second heat treatment processes. Embodiment 1 of the invention What differs between this Embodiment 1 of the invention shown in Fig. 7 and Example 1 is that a multilayer passivation layer consisting of a first passivation layer 49 of PSG layer and a second passivation layer 50 of NSG layer (non-doped silicate glass layer) is formed in order to protect the interconnections 44a, 44b, 44c. The first passivation layer 49 and second passivation layer 50 are formed by other method than plasma CVD in which active hydrogen is produced in layer forming process, for example, low-pressure CVD or atmospheric-pressure CVD. In such constitution of Embodiment 1, unlike the silicon nitride layer or silicon oxynitride layer formed by the conventional plasma CVD, hydrogen is not contained in the passivation layer, so that the capacitor dielectric layer will not deteriorate. Furthermore, stress relaxation to the capacitor is realized by the PSG layer, and the moisture absorption which is a demerit of PSG layer can be prevented by the NSG layer formed thereon, so that a high reliability is realized without stress applied on the capacitor. A manufacturing method of this semiconductor device is described below with reference to Fig. 8, Fig. 9, and Fig. 10. In Fig. 8, an integrated circuit 36 and others are formed on a silicon substrate 31, an insulating layer 37 is formed thereon, a capacitor 41 is formed on the insulating layer 37, an interlayer insulating layer 46 is formed to cover the capacitor 41, a first contact hole 43a, and second and third contact holes 43b and 43c are formed, which may be the same as in a conventional manufacturing method. Then, as shown in Fig. 9, interconnections 44a, 44b, 44c are formed. Next, as shown in Fig. 10, covering the interconnections 44a, 44b, 44c, a first passivation layer 49 made of PSG layer and a second passivation layer 50 made of NSG layer are sequentially formed by low-pressure CVD. Or the first passivation layer 49 and second passivation layer 50 may be also formed by atmospheric-pressure CVD. Embodiment 2 of the invention Fig. 11 shows a modified example of Embodiment 1 shown in Fig. 7. What differs between this embodiment and Embodiment 1 is that a second interlayer insulating layer 51 composed of silicon nitride layer or silicon oxynitride layer possessing an opening 52 corresponding to the capacitor 41 is formed beneath the first passivation layer 49. In such constitution, deterioration of the integrated circuit 36 can be prevented by the second interlayer insulating layer 51 composed of silicon nitride layer, which is favorable to the integrated circuit. On the capacitor 41, the first passivation layer 49 composed of PSG layer and second passivation layer 50 composed of NSG layer are formed, and therefore the stress applied on the capacitor 41 is alleviated and the invasion of ionic impurities from outside is prevented by the first passivation layer 49, while the moisture resistance and water resistance which the PSG layer is not so good with are assured by the second passivation layer 50. A manufacturing method of the semiconductor device shown in Fig. 11 is explained below while referring to Fig. 12 and Fig. 13. After forming the interconnections 44a, 44b, 44c shown in Fig. 9, a second interlayer insulating layer 51 composed of silicon nitride layer or silicon oxynitride layer is formed so as to cover the interconnections 44a, 44b, 44c. Consequently, as shown in Fig. 12, an opening 52 corresponding to the capacitor 41 is formed by conventional etching method. Then, as shown in Fig. 13, on the entire surface, a first passivation layer 49 composed of PSG layer and a second passivation layer 50 composed of NSG layer are sequentially formed by low-pressure CVD or atmospheric-pressure CVD. As the second interlayer insulating layer 51, a dense silicon nitride layer is formed by plasma CVD at low temperature, and an opening 52 corresponding to the capacitor 41 is formed in the second interlayer insulating layer 51, and the capacitor 41 is heated, so that the hydrogen taken in the layer in the process of forming the silicon nitride layer can be released. A greater effect may be obtained by heating the capacitor 41 in two steps, that is, first heat treatment process of heating in inert gas or vacuum, and second heat treatment process of heating in gas containing oxygen. That is, the hydrogen in the capacitor dielectric layer 39 is released in the first heat treatment process, and oxygen is introduced in the second heat treatment process, thereby recovering the characteristic of the capacitor dielectric layer 39. In this embodiment, the opening 52 corresponding to the capacitor 41 is formed in the second interlayer insulating layer 51, but the opening 52 may be also provided in correspondence to the top electrode 40, instead of the entire capacitor 41, and the hydrogen in the capacitor dielectric layer 39 can be similarly released in the heat treatment process.

Claims: A semiconductor device comprising an integrated circuit (36) and a capacitor (41) formed on the integrated circuit, wherein the capacitor comprises a bottom electrode (38) composed of a conductive layer formed on an insulating layer (37) of the integrated circuit, a capacitor dielectric layer (39) composed of one of a ferroelectric layer and a high permittivity dielectric layer formed on the bottom electrode, and a top electrode (40) composed of a conductive layer formed on the capacitor dielectric layer, the top electrode and bottom electrode of the capacitor are connected with interconnections (44b, 44c) of the integrated circuit through contact holes (43b, 43c) provided in an interlayer insulating layer (46) formed so as to cover the capacitor, and a passivation layer is formed to cover the interconnections, characterized in that the passivation layer is composed of a phospho-silicate layer (49) and a non-doped silicate layer (50) formed on said phospho-silicate layer (49). A semiconductor device of claim 1, wherein a second interlayer insulating layer (51) possessing an opening at least in the part corresponding to the top electrode of the capacitor is provided beneath the passivation layer. A manufacturing method of semiconductor device comprising: a step of forming a capacitor (41) comprising a bottom electrode (38) composed of a conductive layer, a capacitor dielectric layer (39) composed of one of a ferroelectric layer and a high permittivity dielectric layer formed on the bottom electrode, and a top electrode (40) composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer (37) of a semiconductor substrate (31) in which an integrated circuit (36) is fabricated, a step of forming an interlayer insulating layer (46) by covering the capacitor, a step of forming contact holes (43a, 43b, 43c) reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections (44a, 44b, 44c) to be electrically connected with the integrated circuit and capacitor through the contact holes, and a step of forming a passivation layer covering the interconnections, characterized in that the passivation layer is composed of a phospho-silicate layer (49) and a non-doped silicate layer (50) formed on said phospho-silicate layer (49). A manufacturing method of semiconductor device of claim 3, wherein the step of forming the passivation layer is preceded by a step of forming a second interlayer insulating layer (51), and a step of removing the second interlayer insulating layer in the upper part of the top electrode of the capacitor. A manufacturing method of semiconductor device of claim 4, wherein the step of forming the second interlayer insulating layer is for forming a silicon nitride layer by plasma CVD, and a step of heating the capacitor is added after the step of removing the second interlayer insulating layer. A manufacturing method of semiconductor device of claim 5, wherein the heat treatment step of the capacitor consists of a first step of heating in inert gas or in vacuum, and a second step of heating in gas containing oxygen.

Inventors: ARITA KOJI, FUJII EIJI, INOUE ATSUO, MATSUDA AKIHIRO, MATSUURA TAKETOSHI, NAGANO YOSHIHISA, NASU TORU, OTSUKI TATSUO, SHIMADA YASUHIRO, UEMOTO YASUHIRO, ARITA, KOJI, FUJII, EIJI, INOUE, ATSUO, MATSUDA, AKIHIRO, MATSUURA, TAKETOSHI, NAGANO, YOSHIHISA, NASU, TORU, OTSUKI, TATSUO, SHIMADA, YASUHIRO, UEMOTO, YASUHIRO
Applicants: MATSUSHITA ELECTRONICS CORP, MATSUSHITA ELECTRONICS CORPORATION
Application year: 1994
Main classification: H01L27
IPC codes: H01L21, H01L27