A serial access memory

Abstract: A serial access memory comprises a data transfer unit including a memory cell array (101) having a plurality of memory cells arranged therein for storing data, a first transfer register (117) electrically connected to the memory cell array through a first switching circuit (115) and a second transfer register (127) electrically connected to the first transfer register through a second switching circuit (125). When each of the first and second switching circuits (115, 125) is in an ON state, data passes through the first transfer register (117) so as to be transferred from the memory cell array (101) to the second transfer register (127), and when the first switching circuit is in an ON state and the second switching circuit is in an OFF state, data is transferred from the memory cell array to the first transfer register.

Description: The invention relates to a serial access memory. EP-A-0 182 719 discloses a semiconductor memory device with shift registers which includes a parallel data transfer circuit between the shift registers to enable high speed reading and writing of data for a CRT display. EP-A-0 487 819 discloses a video RAM which includes a serial access memory connected to bi-directional random and serial ports, which permits parallel transfer of data between two serial access memories. Serial access memories for use in filtering interlaced TV signals have also been described in Japanese laid-open publication no. 64-59694, 7 March 1989 and Japanese laid-open publication no. 2-187989, 24 July 1990. According to the present invention, there is provided a serial access memory comprising a memory cell array, a first switching circuit, a first register connected to said memory cell array through the first switching circuit, a second switching circuit, and a second register connected to said first register through the second switching circuit, characterised by means arranged to control the first and second switching circuits such that data from the memory cell array passes through said first register so as to be transferred from said memory cell array to said second register when said first switching circuit and said second switching circuit are in a switched on state, and then data is transferred from said memory cell array to said first register when said first switching circuit is in a switched on state and said second switching circuit is in a switched off state. According to the present invention, there is also provided a method of transferring data from a serial access memory, the serial access memory comprising a memory cell array, a first register connected to the memory cell array through a first switching circuit, and a second register connected to the first register through a second switching circuit, characterised by switching the first and second switching circuits on so that data from the memory cell array passes through the first register to the second register, and then switching the first switching circuit on and switching the second switching circuit off so that data is transferred from said memory cell array to the first register. Examples of the invention can provide a low-cost serial access memory which occupies a reduced area on a silicon chip. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit block diagram showing the structure of a principal part of a serial access memory according to a first embodiment of the present invention; Figure 2 is a view illustrating characteristic portions of the serial access memory shown in Figure 1; Figure 3 is a partial timing chart for describing a data write operation of the serial access memory shown in Figure 1; Figure 4 is a partial timing chart for describing a data read operation of the serial access memory shown in Figure 1; Figure 5 is a circuit block diagram showing the structure of a clock signal generating circuit employed in the serial access memory shown in Figure 1 and is a partial timing chart for describing the operation of the clock signal generating circuit; Figure 6 is a circuit block diagram showing the structure of a principal part of a serial access memory according to a second embodiment of the present invention; Figure 7 is a partial timing chart for describing a data read operation of the serial access memory shown in Figure 6; Figure 8 is a circuit block diagram illustrating the structure of a principal part of a serial access memory according to a third embodiment of the present invention; Figure 9 is a circuit block diagram depicting the structure of a delay circuit employed in the serial access memory shown in Figure 8; Figure 10 is a partial timing chart for describing a data read operation of the serial access memory shown in Figure 8; Figure 11 is a circuit block diagram showing the structure of a principal pan of a serial access memory according to a fourth embodiment of the present invention; Figure 12 is a circuit block diagram illustrating the structure of a delay bypass circuit employed in the serial access memory shown in Figure 11; Figure 13 is a circuit block diagram showing the structure of a principal part of a serial access memory according to a fifth embodiment of the present invention; Figure 14 is a circuit block diagram depicting the structure of a principal part of a serial access memory according to a sixth embodiment of the present invention; Figure 15 is a circuit block diagram showing the structure of a delay selection circuit employed in the serial access memory shown in Figure 14; Figure 16 is a circuit block diagram showing the structure of a principal part of a serial access memory according to a seventh embodiment of the present invention; Figure 17 is a circuit block diagram illustrating the structure of a principal part of a serial access memory according to an eighth embodiment of the present invention; Figure 18 is a circuit block diagram showing the structure of a principal part of a serial access memory according to a ninth embodiment of the present invention; Figure 19 is a circuit block diagram showing the structure of a principal pan of a serial access memory according to an eleventh embodiment of the present invention; Figure 20 is a circuit block diagram illustrating the structure of another principal pan of the serial access memory shown in Figure 19; Figure 21 is a circuit block diagram depicting the structure of a further principal pan of the serial access memory shown in Figure 19; Figure 22 is a circuit block diagram showing the structure of a principal pan of a read register employed in a serial access memory according to a twelfth embodiment of the present invention; and Figure 23 is a circuit block diagram showing one example in which a serial access memory according to the present invention is applied to a display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings. Common elements employed in the respective embodiments are identified by like reference numerals. In the respective embodiments, memory control signal generating circuits and the like, which are not directly concerned with basic operations of the present invention, are omitted to provide an easy understanding of illustration. A first embodiment of the present invention will first be described with reference to Fig. 1. Fig. 1 is a schematic block diagram showing the structure of a serial access memory according to the first embodiment of the present invention. The serial access memory according to the present embodiment has a memory cell array 101. The memory cell array 101 has a plurality of word lines WL i (i = 1 ∼ n) and a plurality of complementary bit line pairs BL k and BL k (k = 1 ∼ m) which intersect the plurality of word lines WL i respectively. Memory cells Q ki (k = 1 ∼ m, i = 1 ∼ n) each comprised of a transistor and a capacitor are electrically connected to their corresponding points where the plurality of word lines WL i and the plurality of complementary bit line pairs BL k and BL k intersect respectively. Further, the memory cells Q ki are arranged in row and column directions. The bit line pairs BL k and BL k are respectively electrically connected to sense amplifiers SA k (k = 1 ∼ m). An X address decoder 103 is electrically connected to the memory cell array 101. The X address decoder 103 is electrically connected to the plurality of word lines WL i and has a function of selecting a desired column from the memory cell array 101 in response to one of X addresses supplied from the outside. An input circuit 105 serves as a circuit for inputting write data input from an input terminal D in to the memory cell array 101 through a pair of write data buses WDB and WDB . A Y address decoder (for writing) 107 has a function for decoding one of Y addresses supplied from the outside and selecting a desired row from the memory cell array 101 based on an address signal YW i . Data on the write data bus pair WDB and WDB are input to a desired memory cell arranged in the selected row. A transfer circuit 109 is comprised of a plurality of transistor pairs 109 k and 109 k . These transistors are of N channel MOS transistors (NMOSs). The transistor pairs 109k and 109k are respectively electrically connected between the write data bus pair WDB and WDB and flip-flops WF k of a write register 111. A desired transistor pair 109 k and 109 k is selected based on an output YW k produced from the Y address decoder 107. The transfer circuit 109 has a function for transferring the write data on the write data bus pair WDB and WDB to the write register 111. The write register 111 is comprised of the flip-flops WF k (k = 1 ∼ m) respectively electrically connected to the transistor pairs 109 k and 109 k of the transfer circuit 109. Each flip-flop WF k is comprised of two inverters WI nk and WI nk reversely parallel-connected to each other. The write register 111 has a function for storing write data therein. A transfer circuit 113 is electrically connected between the memory cell array 101 and the write register 111 and is comprised of a plurality of transistor pairs 113 k and 113 k . These transistors are of N channel MOS transistors (NMOSs). The transistor pairs 113 k and 113 k are respectively electrically connected between the flip-flops WF k and the bit line pairs BL k and BL k . The transfer circuit 113 has a function for writing the write data stored in the write register 111 therein and transferring the write data to the memory cell array 101 in response to a control signal PWT. Further, a transfer circuit 115 for transferring read data to a first read register 117 is electrically connected to the memory cell array 101. The transfer circuit 115 is made up of a plurality of transistor pairs 115 k and 115 k . These transistors correspond to N channel MOS transistors (NMOSs). The transistor pairs 115 k and 115 k are respectively electrically connected between the bit line pairs BL k and BL k and flip-flops RF k of the first read register 117. Further, the transistor pairs 115 k and 115 k transfer data read from the memory cell array 101 to their corresponding flip-flops RF k in response to a control signal PRT1. The first read register 117 is comprised of the flip-flops RF k (k = 1 ∼ m) respectively electrically connected to the transistor pairs 115 k and 115 k of the transfer circuit 115. Each of the flip-flops RF k is comprised of two inverters RI nk and RI nk electrically reversely parallel-connected to one another. The first read register 117 has a function for storing therein read data corresponding to each column, which have been transferred from the transfer circuit 115. A transfer circuit 119 is electrically connected between a pair of first read data buses RD1 and RD1 and the first read register 117 and comprises a plurality of transistor pairs 119 k and 119 k . These transistors are of N channel MOS transistors (NMOSs). The transistor pairs 119 k and 119 k are respectively electrically connected between the flip-flops RF k and the first read data bus pair RD1 and RD1 . The transfer circuit 119 transfers each read data stored in the first read register 117 to the first read data bus pair RD1 and RD1 in response to an address signal YR 1k supplied from a first Y address decoder (Read) 121. A first output circuit 123 is electrically connected to the first read data bus pair RD1 and RD1 . The first output circuit 123 outputs each read data transferred from the first read register 117 to a first output terminal DOUT1. In the serial access memory according to the present invention, a transfer circuit 125 is further electrically connected to the first read register 117. The transfer circuit 125 has a function for transferring the data read from the memory cell array 101 to a second read register 127 through the first read register 117 in response to a second read control signal PRT2. The transfer circuit 125 is comprised of a plurality of transistor pairs 125 k and 125 k . These transistors are of N channel MOS transistors (NMOSs). The transistor pairs 125 k and 125 k are respectively electrically connected between the flip-flops RF k of the first read register 117 and flip-flops RF' k of the second read register 127. Further, the transistors pairs 125 k and 125 k transfer data read from the memory cells Q ki of the memory cell array 101 to their corresponding flip-flops RF' k in response to the second read control signal PRT2. The second read register 127 is comprised of the flip-flops RF' k (k = 1 ∼ m) respectively electrically connected to the transistor pairs 125 k and 125 k of the transfer circuit 125. Each flip-flop RF' k is made up of two inverters RI n'k and RI n'k electrically reversely parallel-connected to one another. The second read register 127 has a function for storing therein read data corresponding to each column, which have been transferred from the transfer circuit 125. A transfer circuit 129 is electrically connected between a pair of second read data buses RD2 and RD2 and the second read register 127 and comprises a plurality of transistors pairs 129 k and 129 k . These transistors are of N channel MOS transistors (NMOSs). The transistor pairs 129 k and 129 k are respectively electrically connected between the flip-flops RF' k and the second read data bus pair RD2 and RD2 . The transfer circuit 129 transfers each read data stored in the second read register 127 to the second read data bus pair RD2 and RD2 in response to an address signal YR 2k supplied from a second Y address decoder (Read) 131. A second output circuit 133 is electrically connected to the second read data bus pair RD2 and RD2 . The second output circuit 133 outputs each read data transferred from the second read register 127 to a second output terminal DOUT2. The present invention will now be described with reference to Fig. 2 typically showing characteristic portions of the present invention to provide an easier understanding of the present invention. In this case, the same elements of structure as those employed in the serial access memory shown in Fig. 1 are identified by like reference numerals. In the serial access memory according to the present invention, the first read register 117 is electrically series-connected to the second read register 127 as shown in Fig. 2. When data are input to the second read register 127 in the present serial access memory, the transfer circuit 115 is first turned ON in response to the first read control signal PRT1 and the transfer circuit 127 is then turned ON in response to the second read control signal PRT2 as shown in Fig. 2(A). As a result, data read from the memory cell array 101 are transferred to the second read register 127 through the first read register 117. On the other hand, when data are input to the first read register 115, the transfer circuit 115 is first turned ON in response to the first read control signal PRT1 and the transfer circuit 127 is then turned OFF in response to the second read control signal PRT2 as shown in Fig. 2(B). As a result, data read from the memory cell array 101 are transferred to the first read register 117. The operation of the serial access memory according to the present embodiment will now be described in detail with reference to timing charts shown in Figs. 3 and 4. In this case, a write operation and a read operation will be described individually to provide an easy understanding of illustration. The write operation and the read operation will be described with reference to the timing charts shown in Figs. 3 and 4 respectively. The write and read operations of the serial access memory can be performed simultaneously by carrying out the write and read operations separately from each other. Such operations can be easily understood by reference to the following description. This description will be made for each period to provide an easy understanding. The serial access memory is activated in response to a clock signal CLK. The clock signal CLK is generated from a clock signal generating circuit 500 shown in Fig. 5(A). The clock signal generating circuit 500 comprises an inverter unit 501 comprised of a plurality of odd-stage inverters 501 l through 501 j (j : j ≥ odd number of three) electrically series-connected to each other, an inverter 503 and a gate circuit 505. An output of the inverter 501 j is electrically connected to an input of the inverter 501 l and an input of the inverter 503. An output P o of the inverter 503 is electrically connected to one of inputs of the gate circuit 505. A clock control signal CLE is supplied to the other input of the gate circuit 505. A simplified operation of the clock signal generating circuit 500 is represented by a timing chart shown in Fig. 5(B). During a period (corresponding to a time interval between t A and t B ) in which a logic level of the clock control signal CLE is of a HIGH LEVEL (hereinafter called "H"), a clock signal CLK is output from the clock signal generating circuit 500. The operation of the serial access memory at the time that data is input from the outside will first be described with reference to Fig. 3. 〈Period t 1 〉 Write data d 1 is input to the input circuit 105 from an input terminal DIN. The write data d 1 is supplied from the input circuit 105 to the write data bus pair WDB and WDB . Since an address signal YW 1 supplied from the Y address decoder (Write) 107 is of the "H" at this time, a pair of transistors 109 1 and 109 1 of the transfer circuit 109 is turned ON so that the write data d 1 is input to a flip-flop WF 1 of the write register 111. 〈Period t 2 〉 Similarly, write data d 2 is supplied to the write data bus pair WDB and WDB form the input circuit 105. Since an address signal YW 2 is of the "H" at this time, a transistor pair 109 2 and 109 2 of the transfer circuit 109 is turned ON so that the write data d 2 is input to a flip-flop WF 2 of the write register 111. 〈Period t 3 〉 Write data d 3 is supplied to the write data bus pair WDB sand WDB from the input circuit 105 in the same manner as described above. Since an address signal YW 3 is of the "H" at this time, a transistor pair 109 3 and 109 3 of the transfer circuit 109 is turned ON so that the write data d 3 is input to a flip-flop WF 3 of the write register 111. 〈Period t 4 〉 Write data d m is hereafter supplied to the write data bus pair WDB and WDB from the input circuit 105 in the same manner as described above. Since an address signal YW m is of the "H" at this time, a transistor pair 109 m and 109 m of the transfer circuit 109 is turned ON so that the write data dm is input to a flip-flop WF m of the write register 111. 〈Period t 5 〉 A desired word line WL a (1 ≤ a ≤ n) is selected by the X address decoder 103. In this case, a potential level of the selected word line WL a is brought to the "H". Simultaneously, a logic level of the write control signal PWT is rendered "H" in level so that transistor pairs 113 1 and 113 1 through 113 m and 113 m of the transfer circuit 113 are turned ON. Thus, the write data d1 through d m stored in the write register 111 are written into their corresponding memory cells Q 1, a through Q m,a electrically connected to the word line WL a . The write data are written into their corresponding memory cells of the memory cell array 101 in the above-described manner. The read operation of the serial access memory according to the present embodiment will now be described with reference to Fig. 4. In this case, the operations for outputting read data from the first and second output terminals DOUT1 and DOUT2 respectively will be described below. 〈Period t 1 〉 A desired word line WL a (1 ≤ a ≤ n) is selected by the X address decoder 103. In this case, the potential of the selected word line WL a is brought to the "H". The word line WL a is electrically connected to a memory cell group having data stored therein to be read from the second output terminal DOUT2. At this time, the data stored in the memory cells Q 1, a through Q m,a respectively connected to the word line WL a are read into the bit line pairs BL 1 and BL 1 through BL m and BL m to which their corresponding memory cells are electrically connected. Thereafter, the data read into the bit line pairs are amplified by sense amplifiers SA 1 through SA m respectively. 〈Period t 2 〉 Next, each of logic levels of the first and second read control signals PRT1 and PRT2 is brought to the "H". Accordingly, transistor pairs 115 1 and 115 1 through 115 m and 115 m of the transfer circuit 115 are turned ON and transistor pairs 125 1 and 125 1 through 125 m and 125 m of the transfer circuit 125 are turned ON. Thus, the data on the bit line pairs BL 1 and BL 1 through BL m and BL m , which have been amplified by the sense amplifiers SA 1 through SA m during the period t 1 , are transferred to the first read register 117 at a time. Further, the data are input to the second read register 127 through the first read register 117. 〈Period t 3 〉 Next, a desired word line WL b (1 ≤ b ≤ n) is selected by the X address decoder 103. In this case, the potential of the selected word line WL b is brought to the "H". The word line WL b is electrically connected to a memory cell group having data stored therein to be read from the first output terminal DOUT1. At this time, the data stored in the memory cells Q 1, b through Q m, b respectively connected to the word line WL b are read into the bit line pairs BL 1 and BL 1 through BL m and BL m to which their corresponding memory cells are electrically connected. Thereafter, the data read into the bit line pairs are amplified by the sense amplifiers SA 1 through SA m respectively. 〈Period t4〉 Next, the logic level of the first read control signal PRT1 is next brought to the "H" and the logic level of the second read control signal PRT2 is rendered "L" in level. Thus, the transistor pairs 115 1 and 115 1 through 115 m and 115 m of the transfer circuit 115 are turned ON and the transistor pairs 125 1 and 125 1 through 125 m and 125 m of the transfer circuit 125 are turned OFF. As a result, the data on the bit line pairs BL 1 and BL 1 through BL m and BL m , which have been amplified by the sense amplifiers SA 1 through SA m during the period t 1 , are input to the first read register 117 at a time. 〈Period t 5 〉 Next, an address signal YR 11 supplied from the first Y address decoder (Read) 121 is brought to the "H" so that a transistor pair 119 1 and 119 1 of the transfer circuit 119 is turned ON. Accordingly, the read data stored in the flip-flop RF 1 of the first read register 117 is transferred to the output circuit 123 through the first read data bus pair RD1 and RD1 . Thereafter, data D1 is output to the first output terminal DOUT1 from the output circuit 123. Similarly, an address signal YR 21 supplied from the second Y address decoder (Read) 131 is brought to the "H" so that a transistor pair 129 1 and 129 1 of the transfer circuit 129 is turned ON. Thus, the read data stored in the flip-flop RF' 1 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D1' is output to the second output terminal DOUT2 from the output circuit 133. 〈Period t 6 〉 An address YR 12 supplied from the first Y address decoder (Read) 121 is then brought to the "H" so that a transistor pair 119 2 and 119 2 of the transfer circuit 119 is turned ON. Thus, the read data stored in the flip-flop RF 2 of the first read register 117 is transferred to the output circuit 123 through the first read data bus pair RD1 and RD1 . Thereafter, data D2 is output to the first output terminal DOUT1 from the output circuit 123. Similarly, an address signal YR 22 supplied from the second Y address decoder (Read) 131 is brought to the "H" so that a transistor pair 129 2 and 129 2 of the transfer circuit 129 is turned ON. Thus, the read data stored in the flip-flop RF' 2 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D2' is output to the second output terminal DOUT2 from the output circuit 133. Similarly to the above operations as indicated by periods t 7 and t 8 , data D3, D4, ... Dm are subsequently successively output from the first output terminal DOUT1. Further, data D3', D4', ... Dm' are successively output from the second output terminal DOUT2. Thus, the data read from the memory cell array are successively output from the two output terminals. The following serial access memories are normally considered as the serial access memory (called "two port memory") of such a type that the data read from the memory cell array are read from the two output terminals. There is known a first serial access memory of a type wherein a memory cell at an address common to the same two serial access memories provided adjacent to each other and electrically connected to an input circuit in which a write data bus common to the serial access memories is used, is selected and the same write data is written into the memory cell and data stored in memory cells at different addresses are respectively read from separately-provided output circuits in accordance with separate read operations. There is known a second access memory cell of a type wherein two read registers are electrically parallel-connected to a bit line pair of a memory cell array through a transfer circuit and alternately-read data are output therefrom. Let's now perform a comparison between the serial access memory according to the first embodiment of the present invention and the aforementioned first serial access memory. In the first serial access memory, a two port memory is realized using the two serial access memories. In the serial access memory according to the first embodiment of the present invention in contrast with this, a two port memory can be materialized using a single serial access memory. Therefore, the serial access memory according to the first embodiment of the present invention permits a great reduction in its occupied area as compared with the first serial access memory. Since the occupied area can be reduced, wiring lengths of respective signal lines or conductors can also be shortened so that a high-speed operation can be expected. Since the two port memory is realized using the single serial access memory in the case of the serial access memory according to the first embodiment of the present invention, power consumption can be greatly reduced. Further, wires and transfer circuits are provided around a peripheral portion of a read register in close order. Therefore, the more the integration of memory cells is made forward, the more the degree of freedom of design at its peripheral portion is reduced. Since, however, the length of a wire for connecting the read registers to each other is made longer because the read registers are parallel-connected to each other in the second serial access memory, an improvement in integration makes it difficult to design the wires at the peripheral portion. Otherwise, an increase in pitch between memory cells in a column direction (i.e., in a direction parallel to the Y address decoder) is inevitable to ensure the degree of freedom of design at the peripheral portion. This interferes with the integration of a semiconductor memory device. On the other hand, since the serial access memory according to the first embodiment of the present invention is constructed such that the two read registers are electrically connected in series with each other, the wires electrically connected to the two read registers can be greatly reduced in length as compared with the second serial access memory. Therefore, the degree of freedom of design at the peripheral portion of each read register can be ensured and the integration of the peripheral portion can also be achieved according to the integration of each memory cell. According to the serial access memory showing the first embodiment of the present invention, as has been described above, a function identical to that which has been achieved by a plurality of serial access memories, can be realized by a single serial access memory. It is also possible to provide a serial access memory whose degree of integration can be rendered high and which enables a reduction in cost. A second embodiment of the present invention will now be described below with reference to Fig. 6. Fig. 6 is a circuit block diagram showing the structure of a serial access memory according to the second embodiment of the present invention. In this case, the same elements of structure as those shown in the serial access memory according to the first embodiment are identified by like reference numerals and their description will therefore be omitted. The serial access memory according to the second embodiment is basically substantially identical in structure to the serial access memory according to the first embodiment. The serial access memory according to the second embodiment is different from the serial access memory according to the first embodiment in that the first and second read Y address decoders 121 and 131 employed in the first embodiment are replaced by a common Y address decoder (Read) 601. The Y address decoder (Read) 601 is identical in structure and function to each of the first and second Y address decoders 121 and 131. Namely, an address signal YR k (1 ≤ k ≤ m) output from the Y address decoder (Read) 601 is supplied to a gate electrode of each of a plurality of transistor pairs 119 k and 119 k of a transfer circuit 119 and a gate electrode of each of a plurality of transistor pairs 129 k and 129 k of a transfer circuit 129. A read operation of the serial access memory according to the present embodiment will next be described with reference to a timing chart shown in Fig. 7. In this case, the operation of the serial access memory, for outputting read data from first and second output terminals DOUT1 and DOUT2 is shown in Fig. 7. The operation of the serial access memory according to the present embodiment can be easily understood by reference to the description of the operation of the serial access memory according to the first embodiment, which is shown by the timing chart of Fig. 4. Accordingly, the description of operations executed during periods t 1 through t 4 will be omitted by reference to the description of Fig. 4 and operations subsequent to a period t 5 will be described in the present embodiment. 〈Period t 5 〉 An address signal YR 1 supplied from the Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 1 and 119 1 of the transfer circuit 119 and a transistor pair 129 1 and 129 1 of the transfer circuit 129 are turned ON. Thus, read data stored in a flip-flop RF 1 of a first read register 117 is transferred to an output circuit 123 through a first read data bus pair RD1 and RD1 . Further, read data stored in a flip-flop RF' 1 of a second read register 127 is transferred to an output circuit 133 through a second read data bus pair RD2 and RD2 . Thereafter, data D1 is output to the first output terminal DOUT1 from the output circuit 123 and data D1' is output to the second output terminal DOUT2 from the output circuit 133. 〈Period t 6 〉 Next, an address signal YR 2 supplied from the Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 2 and 119 2 of the transfer circuit 119 is turned ON and a transistor pair 129 2 and 129 2 of the transfer circuit 129 is turned ON. Thus, read data stored in a flip-flop RF 2 of the first read register 117 is transferred to the output circuit 123 through first read data bus pair RD1 and RD1 . Further, read data stored in a flip-flop RF' 2 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D2 is output to the first output terminal DOUT1 from the output circuit 123 and data D2' is output to the second output terminal DOUT2 from the output circuit 133. Similarly to the above operations as indicated by periods t 7 and t 8 , data D3, D4, ... Dm are subsequently successively output from the first output terminal DOUT1. Further, data D3', D4', ... Dm' are successively output from the second output terminal DOUT2. Thus, the data read from the memory cell array are successively output from the two output terminals. The serial access memory according to the second embodiment brings about the advantageous effect obtained by the serial access memory according to the first embodiment and shares the use of the read Y address decoder. It is therefore possible to realize a serial access memory which is reduced in its occupied area. As fields to which the serial access memory according to the second embodiment is applied, there are considered those such as low-grade TV and VTR, etc. which do not necessarily require the correction of a time base and are accessible under the same Y address. A third embodiment of the present invention will now be described below with reference to Fig. 8. Fig. 8 is a block diagram showing the structure of a serial access memory according to the third embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. The serial access memory according to the third embodiment is basically substantially identical in structure to the serial access memory according to the second embodiment. The serial access memory according to the third embodiment is different from the serial access memory according to the second embodiment in that a first delay circuit 800 is electrically connected between a first read data bus pair RD1 and RD1 and a first output circuit 123. The first delay circuit 800 has a function for delaying the transfer of data read on the read data bus pair by a predetermined period or time upon transfer of the data. The first delay circuit 800 may be provided between a second read data bus pair RD2 and RD2 and a second output circuit 133 as an alternative to the provision of the first delay circuit 800 between the first read data bus pair RD1 and RD1 and the first output circuit 123. Namely, the delay circuit may be connected between either one of the read data bus pairs and either one of the output circuits. As shown in Fig. 9, the first delay circuit 800 comprises a plurality of flip-flops FF 1 through FF x electrically series-connected to one another so that read data can be delayed by a predetermined bit. If X = 2, then a delay corresponding to 2 bits is developed. If X = 3, then a delay corresponding to 3 bits is developed. The first delay circuit 800 is activated in synchronism with a clock signal CLK. A read operation of the serial access memory according to the present embodiment will now be described with reference to a timing chart shown in Fig. 10. In this case, the operation of the serial access memory, for outputting read data from first and second output terminals DOUT1 and DOUT2 when the delay corresponding to the three bits is developed (X = 3), is shown in Fig. 10. The operation of the serial access memory according to the present embodiment can be easily understood by reference to the description of the operations of the serial access memories according to the first and second embodiments, which are shown by the timing charts of Figs. 4 and 7. Thus, the description of operations executed during periods t 1 through t 4 will be omitted by reference to the description of Figs. 4 and 7 and operations subsequent to a period t 5 will be described in the present embodiment. 〈Period t 5 〉 An address signal YR 1 supplied from a Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 1 and 119 1 of a transfer circuit 119 and a transistor pair 129 1 and 129 1 of a transfer circuit 129 are turned ON. Thus, read data stored in a flip-flop RF 1 of a first read register 117 is transferred to the first delay circuit 800 through a first read data bus pair RD1 and RD1 . Thereafter, the read data is stored in a flip-flop FF 1 . Simultaneously, read data stored in a flip-flop RF' 1 of a second read register 127 is transferred to an output circuit 133 through a second read data bus pair RD2 and RD2 . Thereafter, data D1' is output to the second output terminal DOUT2 from the output circuit 133. 〈Period t 6 〉 Next, an address signal YR 2 supplied from the Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 2 and 119 2 of the transfer circuit 119 is turned ON and a transistor pair 129 2 and 129 2 of the transfer circuit 129 is turned ON. Thus, read data stored in a flip-flop RF 2 of the first read register 117 is transferred to the first delay circuit 800 through the first read data bus pair RD1 and RD1 . At this time, data stored in a flip-flop FF 1 is input to a flip-flop FF 2 in synchronism with the clock signal CLK and the data read from the flip-flop RF 2 is input to the flip-flop FF 1 . Further, read data stored in a flip-flop RF' 2 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D2' is output to the second output terminal DOUT2 from the output circuit 133. 〈Period t 7 〉 Next, an address signal YR 3 supplied from the Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 3 and 119 3 of the transfer circuit 119 is turned ON and a transistor pair 129 3 and 129 3 of the transfer circuit 129 is turned ON. Thus, read data stored in a flip-flop RF 3 of the first read register 117 is transferred to the first delay circuit 800 through the first read data bus pair RD1 and RD1 . At this time, the data stored in the flip-flop FF 1 is input to the flip-flop FF 2 in synchronism with the clock signal CLK and the data stored in the flip-flop FF 2 is input to a flip-flop FF 3 in synchronism with the clock signal CLK. Simultaneously, the data read from the flip-flop FF 3 is input to the flip-flop FF 1 . Further, read data stored in a flip-flop RF' 3 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D3' is output to the second output terminal DOUT2 from the output circuit 133. 〈Period t 8 〉 Next, an address signal YR 4 supplied from the Y address decoder (Read) 601 is brought to an "H" so that a transistor pair 119 4 and 119 4 of the transfer circuit 119 is turned ON and a transistor pair 129 4 and 129 4 of the transfer circuit 129 is turned ON. Thus, read data stored in a flip-flop RF 4 of the first read register 117 is transferred to the first delay circuit 800 through the first read data bus pair RD1 and RD1 . At this time, the data stored in the flip-flop FF 1 is input to the flip-flop FF 2 in synchronism with the clock signal CLK and the data stored in the flip-flop FF 2 is input to the flip-flop FF 3 in synchronism with the clock signal CLK. Further, the data stored in the flip-flop FF 3 is transferred to the output circuit 123. Simultaneously, data read from a flip-flop FF 4 is input to the flip-flop FF 1 . Further, read data stored in a flip-flop RF' 4 of the second read register 127 is transferred to the output circuit 133 through the second read data bus pair RD2 and RD2 . Thereafter, data D1 is output to the first output terminal DOUT1 from the output circuit 123 and data D4' is output to the second output terminal DOUT2 from the output circuit 133. Similarly to the above operations as indicated by periods t 9 , t 10 , ..., data D2, D3, ... Dm-3 are subsequently successively output from the first output terminal DOUT1. Further, data D5', D6', ... Dm' are successively output from the second output terminal DOUT2. Thus, the data delayed by the three bits as compared with the data output from the second output terminal DOUT2 is output from the first output terminal DOUT1. Thus, the data read from the memory cell array are successively output from the two output terminals. In addition to the advantageous effects obtained by the first and second embodiments, the present embodiment can bring about an advantageous effect capable of delaying data output from one of the output terminals. It is therefore possible to increase variations in data output and make a wide range of user's choice. A fourth embodiment of the present invention will now be described below with reference to Fig. 11. Fig. 11 is a block diagram showing the structure of a serial access memory according to the fourth embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. The serial access memory according to the fourth embodiment has a delay bypass circuit 1100 electrically connected to the first delay circuit 800 employed in the serial access memory according to the third embodiment. As shown in Fig. 12, the delay bypass circuit 1100 comprises transistors 1101, 1102 and 1103 and an inverter 1104. These transistors are of N-type MOS transistors. The transistor 1101 is electrically connected between a first read data bus pair RD1 and RD1 and a first output circuit 123 so as to be arranged in shunt with a delay circuit 800. Further, the transistor 1102 is electrically connected between a flip-flop FF 1 and the first read data bus pair RD1 and RD1 . Furthermore, the transistor 1103 is electrically connected between a flip-flop FFx and the first output circuit 123. A control electrode of the transistor 1101 is supplied with a delay bypass signal PBP. Further, both control electrodes of the transistors 1102 and 1103 are supplied with the delay bypass signal PBP through the inverter 1104. The delay bypass circuit 1100 has a function for controlling a delay in data transfer in response to the delay bypass signal PBP. When the delay bypass signal PBP is brought to an "H" in the serial access memory according to the fourth embodiment, the transistor 1101 is turned ON and the transistors 1102 and 1103 are turned OFF. In this case, data on the read bus pair bypasses the delay circuit 800 so as to be transferred to the first output circuit 123. Namely, a delay effect is not brought about due to this bypass process. On the other hand, when the delay bypass signal PBP is of a LOW LEVEL (hereinafter simply called "L"), the transistor 1101 is turned OFF and the transistors 1102 and 1103 are turned ON. Thus, since read data is transferred through the delay circuit 800, the output at the first output terminal DOUT1 is delayed by n bits as compared with the output at the second output terminal DOUT2 as in the description of the third embodiment. According to the serial access memory showing the present embodiment, the function of the serial access memory according to the second or third embodiment can be selected based on the delay bypass signal PBP supplied from the outside in addition to the achievement of the advantageous effects of the aforementioned embodiments. A fifth embodiment of the present invention will now be described below with reference to Fig. 13. Fig. 13 is a block diagram showing the structure of a serial access memory according to the fifth embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. The serial access memory according to the fifth embodiment is constructed such that a delay circuit 800' and a delay bypass circuit 1100' similar to those described in the third and fourth embodiments are added to the second read data bus pair RD2 and RD2 of the serial access memory according to the fourth embodiment. The delay circuit 800' and the delay bypass circuit 1100' are identical in structure to the delay circuit 800 and the delay bypass circuit 1100 respectively. These circuits are controlled based on a delay bypass signal PBP'. The operation of the serial access memory according to the present embodiment can be easily understood by reference to the third and fourth embodiments. The serial access memory according to the present embodiment can arbitrarily delay read data output from first and second output terminals based on a signal supplied from the outside as well as bring about the advantageous effects obtained by the aforementioned embodiments. A sixth embodiment of the present invention will now be described below with reference to Fig. 14. Fig. 14 is a block diagram showing the structure of a serial access memory according to the sixth embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. In the present embodiment, a delay selection circuit 1400 is electrically connected between a first read data bus pair RD1 and RD1 and a first output circuit 123. The delay selection circuit 1400 comprises a plurality of transistors as shown in Fig. 15. These transistors are respectively provided between the first read data bus pair RD1 and RD1 and the first output circuit 123 and between flip-flops FF 1 through FF x and the first output circuit 123. Further, these transistors are respectively supplied with delay select signals PBP1 through PBPx. Each of the transistors is ON- or OFF-controlled according to a logic level of each delay select signal. These transistors are of N channel MOS transistors. The serial access memory according to the present embodiment can select a desired delay bit based on each of the delay select signals PBP1 through PBPx as well as bring about the advantageous effects obtained by the aforementioned embodiments. Therefore, a delay in data output from a first output terminal can be suitably set. A seventh embodiment of the present invention will now be described below with reference to Fig. 16. Fig. 16 is a block diagram showing the structure of a serial access memory according to the seventh embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. The present embodiment has the structure of the sixth embodiment and is constructed such that a delay selection circuit 1400' identical in structure to the delay selection circuit 1400 employed in the sixth embodiment is electrically connected between a second read data bus pair RD2 and RD2 and a second output circuit 133. A detailed configuration of the delay selection circuit 1400' can be easily understood by reference to Fig. 15. These transistors are respectively provided between the second read data bus pair RD2 and RD2 and the second output circuit 133 and between flip-flops FF 1 ' through FF x ' and the second output circuit 133. Further, these transistors are respectively supplied with delay select signals PBP1' through PBPx'. Each of the transistors is ON- or OFF-controlled according to a logic level of each delay select signal. These transistors are of N channel MOS transistors. The serial access memory according to the present embodiment can select desired delay bits based on each of the delay select signals PBP1 through PBPx and each of the delay select signals PBP1' through PBPx' as well as bring about the advantageous effects obtained by the aforementioned embodiments. Therefore, a delay in data output from each of first and second output terminals can be suitably set. An eighth embodiment of the present invention will now be described below with reference to Fig. 17. Fig. 17 is a block diagram showing the structure of a serial access memory according to the eighth embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. In the present embodiment, a delay control address decoder 1700 for outputting delay select signals PBP1 through PBPx therefrom is electrically connected to the delay selection circuit 1400 employed in the serial access memory according to the sixth embodiment. The delay control address decoder 1700 has a function for decoding addresses AA1 through AAx supplied from the outside to control delay bits and outputting the delay select signals PBP1 through PBPx based on the result of decoding. According to the present embodiment, since the delay select signals are produced based on the external addresses in addition to the advantageous effects obtained by the aforementioned embodiments, the number of delay bits can be suitably set based on the reduced number of external signals. A ninth embodiment of the present invention will now be described below with reference to Fig. 18. Fig. 18 is a block diagram showing the structure of a serial access memory according to the ninth embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. In the present embodiment, a delay control address decoder 1700 for outputting the delay select signals PBP1 through PBPx described in the eighth embodiment and a delay control address decoder 1700' having a function equivalent to that of the delay control address decoder 1700 are respectively electrically connected to the delay selection circuit 1400 and 1400' of the serial access memory according to the seventh embodiment. The delay control address decoder 1700' has a function for decoding addresses AA1' through AAx' supplied from the outside to control delay bits and outputting delay select signals PBP1' through PBPx' based on the result of decoding. According to the present embodiment, since the delay select signals are produced based on the external addresses in addition to the advantageous effects obtained by the aforementioned embodiments, the number of delay bits can be suitabiy set based on the reduced number of external signals. A tenth embodiment of the present invention will now be described below. A serial access memory according to the present embodiment is basically identical in structure to the serial access memory according to the first embodiment. In the present embodiment, the inverters RI nk and RI nk of each of the flip-flops RF k and RF k of the first read register 117 employed in the serial access memory according to the first embodiment differ in dimension from the inverters RI n'k and RI n'k of each of the flip-flops RF k and RF k of the second read register 127. Namely, the dimensions of a P channel MOS transistor (hereinafter called "PMOS") and an N channel MOS transistor (hereinafter called "NMOS") which respectively form the inverters RI nk and RI nk , are smaller than those of a PMOS and an NMOS which respectively form the inverters RI n'k and RI n'k . According to the present embodiment, the serial access memory can be realised which is capable of improving the efficiency of data transfer and providing a satisfactory margin of operation. An eleventh embodiment of the present invention will now be described with reference to Figures 19, 20 and 21. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. In the present embodiment, resistors R1 and R2 are respectively provided between a second read register 127 and a power source line V DD for supplying a potential to the second read register 127 and between the second read register 127 and the power source line V DD as shown in Figure 20. Further, resistors R3 and R4 are respectively provided between a first read register 117 and power source lines V DD as shown in Figure 21. Furthermore, resistors R1 and R2, and R3 and R4 are respectively provided between a second read register 127 and power source lines V DD and between a first read register 117 and the power source lines V DD . According to the present embodiment, the serial access memory can be realised which is capable of improving the efficiency of data transfer and providing a satisfactory margin of operation. A twelfth embodiment of the present invention will now be described with reference to Figure 22. Figure 22 is a block diagram showing the structure of a principal pan of a serial access memory according to this embodiment of the present invention. In this case, the aforementioned elements are suitably blocked and typically shown to provide an easy understanding of illustration of the present embodiment. The same elements of structure as those described above are identified by like reference numerals and their description will therefore be omitted. In the present embodiment, flip-flops RF k and RF k of a first read register 117 or flip-flops RF' k and RF' k of a second read register 127 are respectively comprised of clocked inverters CRI nk and CRI nk or CRI n'k and CRI n'k . These clocked inverters are respectively controlled based on control signals 1 and 2. According to the present embodiment, the serial access memory can be materialised which is capable of improving the efficiency of data transfer and providing a satisfactory margin of operation. Thus, the various embodiments in which the two port memories have been realised by connecting the read registers in series with one another, have been described above. According to each of the serial access memories of the present invention as have been described above using the various embodiments, a function equivalent to the function which has been achieved by a plurality of serial access memories, can be realised by electrically series-connecting first and second transfer registers to one another. Each of the serial access memories of the present invention can be applied to a display unit or device 6000 as shown in Figure 23. The display device 6000 comprises a serial access memory 6001 according to the present invention, a D/A convener 6002 for receiving and digital-to-analog convening an output produced from the serial access memory 6001 and outputting the convened data therefrom, a controller 6003 for controlling the serial access memory 6001 and the D/A convener 6002, and a display panel 6004 for displaying the data from the D/A convener 6002 as display data. The serial access memories of the present invention can be applied to various fields in addition to the above application. While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention will be apparent to those skilled in the an with reference to this description.

Claims: A serial access memory comprising a memory cell array (101); a first switching circuit (115); a first register (117) connected to said memory cell array through the first switching circuit (115); a second switching circuit (125); and a second register (127) connected to said first register through the second switching circuit (125); characterised by means arranged to control the first and second switching circuits such that data from the memory cell array (101) passes through said first register (117) so as to be transferred from said memory cell array (101) to said second register (127) when said first switching circuit (115) and said second switching circuit (125) are in a switched on state, and then data is transferred from said memory cell array (101) to said first register (117) when said first switching circuit (115) is in a switched on state and said second switching circuit (125) is in a switched off state. A serial access memory according to claim 1, wherein the dimensions of individual transistors forming said first register (117) are smaller than those of individual transistors forming said second register (127). A serial access memory according to claim 1, wherein said first and second registers (117, 127) are respectively comprised of first and second inverters, said first inverter having an output connected to an input of said second inverter and said second inverter having an output connected to an input of said first inverter. A serial access memory according to claim 3, wherein a first resistor is connected between said first and second inverters and a drive power source. A serial access memory according to claim 3 or 4, wherein the dimensions of individual transistors forming the inverters of said first register (117) are smaller than those of individual transistors forming the inverters of said second register (127). A serial access memory according to any one of the preceding claims, wherein said control means includes a first control signal supply line (PRT1) for controlling said first switching circuit and a second control signal supply line (PRT2) for controlling said second switching circuit. A serial access memory according to any one of the preceding claims, comprising first and second transfer circuits (119,129) respectively connected between said first and second registers (117,127) and first and second read data bus pairs (RD1, RD1 , RD2, RD2 ). A serial access memory according to claim 7, comprising a Y address decoder (601) for supplying address signals to said first and second transfer circuits. A serial access memory according to claim 7, comprising first and second Y address decoders (121,131) for supplying address signals to said first and second transfer circuits. A serial address memory according to claim 8 or 9, further comprising a delay circuit (800) connected between a read data bus pair (RD1, RD1 , RD2, RD2 ) and a corresponding output circuit (123,133). A serial access memory according to claim 10, further comprising a delay bypass circuit (1100) connected to the delay circuit for controlling the data transfer delay in response to a delay bypass signal (PBP). A serial access memory according to claim 8 or 9, further comprising a first delay circuit (800) connected between a first read data bus pair (RD1, RD1 ) and a first output circuit (123) and a second delay circuit (800') connected between a second read data bus pair (RD2, RD2 ) and a second output circuit (133), further comprising first and second delay bypass circuits (1100,1100') connected to the respective delay circuits (800,800') for controlling the data transfer delay in response to respective delay bypass signals (PBP, PBP'). A serial access memory according to claim 8 or 9, further comprising a delay selection circuit (1400) connected between a first read data bus pair (RD1, RD1 ) and a first output circuit (123) for selecting between a plurality of predetermined delay periods. A serial access memory according to claim 13, comprising a further delay selection circuit (1400') connected between a second read data bus pair (RD2, RD2 ) and a second output circuit (133). A serial access memory according to claim 13 or 14, further comprising a delay control address decoder (1700,1700') connected to the delay selection circuit to produce delay select signals (PBP1-PBPx) for use by the delay selection circuit in selecting between a plurality of predetermined delay periods. A serial access memory according to claim 1, wherein said first and second registers (117,127) are respectively comprised of clocked inverters (CRI nk , CRI nk , CRI n'k , CRI n'k ). A method of transferring data from a serial access memory, the serial access memory comprising a memory cell array (101), a first register (117) connected to the memory cell array (101) through a first switching circuit (115), and a second register (127) connected to the first register through a second switching circuit (125); characterised by switching the first (115) and second (125) switching circuits on so that data from the memory cell array (101) passes through the first register (117) to the second register (127), and then switching the first switching circuit on and switching the second switching circuit off so that data is transferred from said memory cell array (101) to the first register (117).

Inventors: HIRAOKA TERUMI, TAKASUGI ATSUSHI, YOSHIOKA SHIGEMI, HIRAOKA, TERUMI, TAKASUGI, ATSUSHI, YOSHIOKA, SHIGEMI
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1994
Main classification: G11C7
IPC codes: G11C7