FREQUENCY DOUBLER

Abstract: A frequency doubler is described which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.

Description: Title of the Invention FREQUENCY DOUBLER Field of the Invention The present invention relates to a frequency doubler which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency. Summary of the Invention According to the present invention there is provided a frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising: a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom; and a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals. In the described embodiment the first set of logic gates comprises a first logic gate connected to receive the first and second input signals, a second logic gate connected to receive the second and third input signals, a third logic gate connected to receive the third and fourth input signals and a fourth logic gate connected to receive the first and fourth input signals, the signals supplied to each logic gate being 90 apart in phase and having a duty cycle close to 50%. The second set of logic gates comprises a fifth logic gate connected to receive the outputs of the first and third logic gates and a sixth logic gate connected to receive the outputs of the second and fourth logic gate. The logic gates are preferably NAND gates, but it is also possible to use NOR gates. However, the switching frequency of the logic gate will limit the maximum operating frequency of the circuit. NAND gates are preferred because they have a faster switching speed than NOR gates. The frequency doubler confers a particular advantage when used to double the frequency of quadrature outputs of a quadrature oscillator, which outputs are subject to buffering and conversion. It is usually difficult to make the oscillator, buffer and convertor operate fast enough but with the present frequency doubler they need operate only at a relatively low frequency. The frequency doubler is then the only circuit which is required to run at a high frequency. This is easier to achieve because it can be designed in high speed CMOS logic and could probably have the facility, to be powered by a full supply voltage, whereas the oscillator may be restricted to operate at low supply voltages (of less than 3V) . An oscillator with which the present invention has particular advantage is described in our copending Application No. (Page White & Farrer Ref. ), the contents of which are herein incorporated by reference. For a better understanding of the present invention, and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings. Brief description of the drawings Figure 1 is a circuit diagram of a frequency doubler; and Figure 2 shows the waveforms of signals in the frequency doubler. Description of the preferred embodiment Figure 1 shows a frequency doubler connected to receive 4-phase quadrature signals ø± ,βr2 ,p2 ,øA. The input signals p± to 04 can come for example from CMOS-level convertors which are connected to the outputs of a quadrature oscillator. The input signals zrl to jύ4 are fed to a first layer of NAND gates 2,4,6,8. The first NAND gate 2 receives as its inputs f4_. , 2 which are 90° apart. The second NAND gate 4 receives as its inputs the input signals 2,03 which are 90° apart. The third NAND gate 6 receives the input signals 01 , 4 which are 90° apart. The fourth NAND gate 8 receives input signals pi , ^4 which are 90° apart. The timing of the input signals is shown in the top two diagrams of Figure 2 labelled pi to respectively. A second layer of NAND gates comprises fifth and sixth NAND gates 10,12. The fifth NAND gate 10 has as its inputs outputs from the first and third NAND gates 2,6. The sixth NAND gate 12 has as its inputs outputs from the second and fourth NAND gates 4,8. The first layer of NAND gates 2 to 8 combine the inputs to 04 to produce four new signals SI to S4 which go low in turn for 25% of the period. This is shown in the next two diagrams in Figure 2. The waveforms for SI and S3 are shown in Figure 2 but it will be appreciated that S2 and S4 have equivalent waveforms at different parts of the cycle. The second layer of NAND gates 10, 12 combine the signals SI to S4 to produce a pair of output signals Outl,Out2 which alternate high and low twice in every period of the input signals. Thus,, the output is toggling at twice the frequency of the input. This is shown in the last diagram of Figure 2. For minimum distortion of mark/space ratio, the NAND gates 10,12 of the second layer are best implemented as symmetrical designs, that is the delay from input to output is identical for each input. A feature of this circuit is that no feedback is required between the layers of NAND gates. Thus, the second layer has as its inputs only inputs from the first layer and the first layer has as its inputs only the 4-phase input signals. There is no feedback from the first layer to the input or from the second layer to the first layer.

Claims: CLAIMS : 1. A frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising: a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom; and a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals. 2. A frequency doubler according to claim 1 wherein the first set of logic gates comprises a first logic gate connected to receive the first and second input signals, a second logic gate connected to receive the second and third input signals, a third logic gate connected to receive the third and fourth input signals and a fourth logic gate connected to receive the first and fourth input signals the signals supplied to each logic gate being 90° apart in phase and having a duty cycle close to 50%. 3. A frequency doubler according to claim 2 wherein the signals supplied to each logic gate being 90° apart in phase. The second set of logic gates comprises a fifth logic gate connected to receive the outputs of the first and third logic gates and a sixth logic gate connected to receive the outputs of the second and fourth logic gate. 4. A frequency doubler according to claim 1, 2 or 3 wherein the logic gates are NAND gates. 5. A frequency doubler according to claim 1 wherein the logic gates are NOR gates. 6. A frequency doubler according to claim 4 or 5 wherein the second set of logic gates is symmetric in design.

Inventors: HALL ANDREW MENDLICOTT, MONK TREVOR KENNETH, HALL, ANDREW, MENDLICOTT, MONK, TREVOR, KENNETH
Applicants: HALL ANDREW MENDLICOTT, INMOS LTD, MONK TREVOR KENNETH, HALL, ANDREW, MENDLICOTT, INMOS LIMITED, MONK, TREVOR, KENNETH
Application year: 1994
Main classification: H03K5
IPC codes: H03K3, H03K5