Wiring layer for semi conductor device and method for manufacturing the same

Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film (12) is deposited on a silicon substrate (11), and a concave groove (13) is formed in the insulating film (12) in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film (12) to form a titanium film (14) and a palladium film (15), respectively. A silver film (16) is formed on the palladium film (15) by electroplating, and a groove-shaped silver wiring layer (17) is formed by polishing. The resultant structure is annealed at a temperature of about 700°C, and an intermetallic compound (18) is formed by alloying the titanium film (14) and palladium film (15) with each other. Consequently, a burying type wiring layer (19) whose resistance is lower than that of aluminum, is constituted by the silver wiring layer (17) and intermetallic compound (18).

Description: The present invention relates to a semiconductor device and a method for manufacturing the same. FIGS. 1A to 1D show an example of a conventional process of manufacturing a wiring structure of a semiconductor device. First an insulating film 2 is thermally oxidized and formed on a semiconductor substrate 1, and then an aluminum (Al) or an alloy 3 containing aluminum (Al) as the principal ingredient is formed on the insulating film 2 by sputtering (FIG. 1A). The alloy 3 thus formed is patterned to have a predetermined shape through a well-known lithography process, thereby forming a first wiring layer 4 (FIG. 1B). An interlayer insulating film 5 is deposited on the resultant structure, and then a via hole 6 is formed in the film 5 (FIG. 1C). After that, a second wiring layer 7 formed of aluminum or an alloy containing aluminum as the principal ingredient, is formed on the interlayer insulating film 5, and connected to the first wiring layer 4 through the via hole 6 (FIG. 1D). Thus, a multilayer wiring layer of the first wiring layer 4 and second wiring layer 7 is formed. However, the width of a wiring layer has recently become narrower in accordance with the progress of high degree of integration of semiconductor devices. For this reason, a conventional wiring layer containing aluminum nearly reaches its limitation in reliability of EM (electromigration) or the like. Since high-speed operations of semiconductor devices cause a noticeable delay in signal transmission due to wiring resistance, it is desirable to decrease the wiring resistance further. According to the conventional technique of assembling an LSI (Large Scale Integrated Circuit), a layer of Ag (silver) or Cu (copper) whose resistance is lower than that of aluminum can be formed. However, neither silver nor copper has been used for forming a wiring layer since they are difficult for etching. It is accordingly an object of the present invention to provide a semiconductor device having a highly reliable wiring structure and a method for manufacturing the same. Accordingly, the present invention provides a semiconductor device according to claim 1. The present invention also provides a method for manufacturing a semiconductor device according to claim 3. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIGS. 1A to 1D are cross-sectional views showing a conventional process of forming a wiring layer; FIGS. 2A to 2D are cross-sectional views schematically showing a process of forming a wiring layer of a semiconductor device according to one embodiment of the present invention; FIG. 3 is a view showing the dependence of the resistivity of a silver film on the annealing temperature; FIGS. 4A to 4D are views for explaining the results of measurement of X-ray diffraction for a thin film; FIGS. 5A to 5C are views for explaining the results of analysis of the composition of the silver film in its depth direction using the Auger electron spectroscopy; and FIG. 6 is a view showing the dependence of the resistivity of the silver film on the annealing temperature, with respect to titanium and palladium films each having different thicknesses. An embodiment of the present invention will now be described, with reference to the accompanying drawings. FIGS. 2A to 2D schematically show a process of forming a wiring structure of a semiconductor device. Primarily an insulating film (SiO 2 ) 12 is deposited on a silicon (Si) substrate 11 such as a semiconductor substrate and a circuit board. Concave grooves 13 are formed in the insulating film 12 by predetermined wiring patterning (FIG. 2A). For example, titanium (Ti) and palladium (Pd) of noble metal are then deposited in sequence on the insulating film 12 by sputtering or CVD (chemical vapor deposition) to form a titanium film 14 of the first metal layer and a palladium film 15 of the second metal layer (FIG. 2B). In this case, the thickness of the titanium layer 14 is about 100 nm, and that of the palladium film 15 is about 50 nm. Thereafter, for example, the palladium film 15 serves as a cathode and is electroplated to form a silver (Ag) film 16 of the third metal layer thereon (FIG. 2C). The silver film 16 other than those portions of the silver film which are formed in the grooves 13, is removed by polishing to form groove-shaped wiring layers 17. After that, the resultant structure is annealed at a temperature of about 700°C in an atmosphere of inactive gas such as argon (Ar) and nitrogen (N 2 ), and the titanium film 14 and palladium film 15 are alloyed with each other, thus forming intermetallic compounds 18 (FIG. 2D). For example, the alloy of the films 14 and 15 can be attained by vacuum annealing as well as the annealing in the atmosphere of inactive gas. Consequently, wiring layers 19 each having the alloy of titanium and palladium (intermetallic compound 18) and the groove-shaped wiring layer 17 of silver whose resistivity is lower than that of aluminum, are obtained. The above-described multilayer wiring layer of the present invention is similar to the conventional one in that an interlayer insulating film is deposited, a via hole is formed, and a second (upper) wiring layer is formed. Since, in the foregoing annealing treatment, palladium is diffused from the palladium film 15 into the silver film 16 to form a solid solution, the resistivity of the silver is likely to increase. The increased resistivity is however lowered by the intermetallic compound 18 formed by the titanium film 14 and palladium film 15 in accordance with the rise of the annealing temperature. FIG. 3 shows the dependence of the resistivity of the silver on the annealing temperature. In this figure, the insulating film 12 of 100 nm, titanium film 14 of 100 nm, palladium film 15 of 50 nm, and silver film 16 of 600 nm, all of which are formed on the silicon substrate 11, are taken as samples, and the relationship between the annealing temperature (abscissa) and the ratio (ordinate) of the resistivity of each sample after the annealing treatment to that of each sample immediately after the films are formed, is shown. As is seen from FIG. 3, the resistivity of the silver increases and then decreases gradually in accordance with the rise of the annealing temperature. After the annealing temperature reaches 800°C, it is maintained at the same value as set before the annealing treatment (as indicated by round black spots). As is also seen from FIG. 3, the resistivity does not change so widely when the samples annealed at a temperature of 700°C are annealed again at a temperature of 500°C (indicated by a square black spot). Variations in structure and composition of the foregoing wiring layer of titanium, and palladium and silver with the rise of the annealing temperature, will now be described, with reference to FIGS. 4A to 4D and FIGS. 5A to 5C. FIGS. 4A to 4D show the results obtained from the measurement of X-ray diffraction for a thin film. In these figures, the insulating film 12 of 100 nm, titanium film 14 of 100 nm, palladium film 15 of 50 nm, and silver film 16 of 500 nm, all of which are formed on the silicon substrate 11, are taken as samples and, under the measurement conditions that the wavelength (CuKa)λ of an X ray is 0.15405 nm and its incident angle  is 5°, the abscissa indicates the angle and the ordinate does the reflection intensity of the X ray. FIGS. 4A to 4D show the measurement results obtained directly after the above films have been formed and when the annealing temperatures are 400°C, 600°C, and 800°C, respectively. FIGS. 5A to 5C show the results obtained from the analysis of composition of the silver film 16 in the depth direction using the Auger electron spectroscopy. In these figures, the same samples as shown in FIGS. 4A to 4D are used, and the abscissa indicates the sputtering time (min) and the ordinate does the relative concentration (%). FIGS. 5A to 5C show the analysis results obtained directly after the above films have been formed and when the annealing temperatures are 400°C and 600°C, respectively. It has been turned out from FIGS. 4A to 4D and 5A to 5C that the intermetallic compound 18 of titanium and palladium is formed and the palladium dissolved in the silver is decreased when the annealing temperature exceeds 600°C. In other words, the increased resistivity of the silver is decreased by removing the palladium from the silver film 16 when the intermetallic compound 18 is formed. According to the present invention, as described above, the wiring structure can be obtained in a simple fashion. More specifically, the wiring layer of silver can be formed by electroplating which is one of simple wiring-layer forming methods. This method allows the use of silver whose resistivity is lower than that of aluminum, though the silver has not been used because it is difficult to etch. Therefore, the resistance of the wiring layer can be lowered, and the wiring layer can easily be applied to high-speed semiconductor devices and is able to improve in reliability in high degree of integration. In the conventional method for manufacturing a semiconductor device, a high-temperature treatment could not be employed, in view of the melting point of aluminum. If, however, the silver of the present invention is used, the restriction on the temperature can be removed; accordingly, the freedom to select various treatments can be increased. Furthermore, since the surface of the multilayer wiring structure of the present invention is flattened by polishing and a burying type wiring layer is formed thereon, the step d of the conventional structure, shown in FIG. 1C, will not occur. Inevitably, there occurs no defects such as disconnection of wiring due to the step d . In the above embodiment, the thickness of the titanium film is about 100 nm and that of the palladium film is about 50 nm. However, the former can be set to 40 nm and the latter can be set to 20 nm. FIG. 6 shows the dependence of the resistivity of silver upon the treating temperature with respect to the titanium and palladium films having different thicknesses. For example, a layer having titanium film 14 of 100 nm and palladium film 15 of 50 nm is used as a first sample, a layer having titanium film 14 of 40 nm and palladium film 15 of 20 nm is used as a second sample, and a layer having titanium film 14 of 20 nm and palladium film 15 of 50 nm is used as a third sample. In each of these samples, the thickness of the insulating film 12 formed on the silicon substrate 11 is 100 nm and that of the silver film 16 is 500 nm. In FIG. 6, the abscissa represents the annealing temperature, and the ordinate does the ratio of the resistivity after the annealing treatment to the resistivity immediately after the formation of the films. It is understood from FIG. 6 that the resistivity of the silver is minimized at every annealing temperature when the second sample is used. Consequently, it is desirable that the titanium film should be thicker than the palladium film. Even though the thicknesses of the titanium and palladium films are the same, some advantages can be anticipated. In any case, it is desirable that the thickness of the palladium film should be 100 nm or less (≠ 0) and therefore the palladium film has only to be considerably thinner than the titanium film or the silver film. In the above embodiment, the annealing temperature is set to 700°C (when the thickness of the titanium film is about 100 nm and that of the palladium film is about 50 nm). However, the temperature the most suitable for alloying can be set in accordance with each individual thickness. Furthermore, the silver film is formed by plating as the third metal layer. However, the silver film can be formed by the sputtering. Gold (Au) or (copper (Cu) can be substituted for the silver. Each of the first, second and third metal layers can be formed of an alloy as well as a single metal. In order to lower the resistance of the wiring layer further and improve the reliability thereof further, another layer can be formed in addition to the first, second, and third metal layers.

Claims: A semiconductor device including an insulating film (12) formed on a substrate (11) and a wiring layer (19) formed on said insulating film (12), wherein said wiring layer (19) comprises a layer (18) containing titanium palladium intermetallic compound and formed from a first metal, comprising essentially titanium or an alloy containing titanium as principal constituent, and a second metal, comprising essentially palladium or an alloy containing palladium as principal constituent, and further comprises a metal layer (17) formed from a third metal, comprising essentially silver, copper or gold, or an alloy containing silver, copper or gold as principal constituents, provided on the intermetallic compound layer (18), said insulating film (12) having a groove (13) in its surface in which said wiring layer (19) is embedded so as to be flush with the surface of said insulating film (12). A semiconductor device according to Claim 1, wherein said third metal includes one of a plating film of silver and a plating film of an alloy containing silver as a principal ingredient. A method for manufacturing a semiconductor device comprising the steps of: providing an insulating film (12) on a substrate (11); providing a wiring groove portion (13) in a surface of said insulating film (12); providing a first metal layer (14) comprising essentially titanium or an alloy containing titanium as principal constituent, on said insulating film (12) in which said wiring groove portion (13) is formed; providing a second metal layer (15) comprising essentially palladium, or an alloy containing palladium as principal constituent, on said first metal layer (14); providing a third metal layer (16) comprising essentially silver, copper or gold, or an alloy containing silver, copper or gold as principal constituent, on said second metal layer (15); removing said first metal layer (14), said second metal layer (15), and said third metal layer (16) formed on said insulating film (12), except in said wiring groove portion (13), such that the remaining portion of the layers is embedded in groove portion (13) and flush with the surface of said insulating film (12); and forming a layer (18) comprising an intermetallic compound of palladium and titanium from the remaining portion of said first metal layer (14) and said second metal layer (15) by annealing at a temperature capable of forming the intermetallic compound layer. A method according to Claim 3 wherein the third metal layer (16) comprises one of a plating film of silver and a plating film of an alloy containing silver as a principal ingredient. A method according to Claim 3 or 4, wherein said second metal layer (15) has a thickness which is equal to or smaller than the thickness of said first metal layer (14). A method according to Claim 5, wherein the thickness of said second metal layer (15) is less than 100 nm.

Inventors: EZAWA HIROKAZU, IKEDA YUKIO, INOUE HIROAKI, MIYATA MASAHIRO, OGURE NAOAKI, OHDAIRA TAKEYUKI, TSUJIMURA MANABU, EZAWA, HIROKAZU, IKEDA, YUKIO, INOUE, HIROAKI, MIYATA, MASAHIRO, OGURE, NAOAKI, OHDAIRA, TAKEYUKI, TSUJIMURA, MANABU, EZAWA, HIROKAZU, C/O INTELLECTUAL PROPERTY DIV., MIYATA, MASAHIRO, C/O INTELLECTUAL PROPERTY DIV., OGURE, NAOAKI, C/O INTELLECTUAL PROPERTY DIV., TSUJIMURA, MANABU, C/O INTELLECTUAL PROPERTY DIV.
Applicants: EBARA CORP, TOSHIBA KK, EBARA CORPORATION, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L23
IPC codes: H01L23, H01L21