NUMERICALLY CONTROLLED OSCILLATOR AND DIGITAL PHASE LOCKED LOOP

Abstract: The invention relates to a numerically controlled oscillator comprising a first oscillator section (41) having a counter (22) acting as a frequency divider, and an external oscillator (21) supplying a clock signal (fext) connected to the counter (22) for generating an output signal (fNCO) with a divided frequency from said clock signal, the counter (22) comprising at least one phase control input (A, B) for connecting phase correction requests to the counter (22) for adjusting the phase of said output signal (fNCO) in a desired direction. In order that the gain factor of the oscillator could be diminished and the oscillator could be connected to a digital filter, a second accumulator-type oscillator section (42) known per se is connected to control the first oscillator section (41), the second oscillator section comprising an adder (31) and a register (32), to which the output of the adder is connected, the adder (31) having a first input for connecting a binary digit (x) to control said second oscillator section (42), and a second input for feeding the output signal of the register back to the adder (31). The invention also relates to a phase-locked loop utilizing a numerically controlled oscillator.

Description: Numerically controlled oscillator and digital phase locked loop The invention relates to a numerically con- trolled oscillator according to the preamble of the attached claim 1, and to a digital phase-locked loop according to the preamble of the attached claim 4, comprising a numerically controlled oscillator. Figure 1 shows a digital phase-locked loop (DPLL) 10 known per se in its general form, in which it comprises a phase comparator 13, a lowpass-type loop filter 14 having an input to which the output signal of the phase comparator is connected, and a numerically controlled oscillator 15 arranged to be controlled by the loop filter. A signal is applied to each one of inputs II and 12 of the phase comparator through a frequency divider 11 and 12, respectively. A reference signal f ref is applied to the frequency divider 11, which divides the frequency of the refer- ence signal by an integer p, whereby a signal having a frequency f ref /p (in this text the reference f refers both to the signal and to its frequency) is applied to the first input II in the phase comparator 13. The function of the numerically controlled oscillator 15 is to generate a wide range of frequencies from an external clock signal f ext having a frequency higher than that of the output signal f NC0 of the oscillator. The output signal of the oscillator is applied through the frequency divider 12 back to the second input 12 of the phase comparator 13. The phase comparator thus compares the phase of a signal having the frequency f ref /p with the phase of a signal having the frequency f NCO /q. The result of this comparison is lowpass- filtered in the loop filter 14, and the filtered signal is applied to the oscillator 15 to control it. When the loop is locked , Formula ( 1 ) is valid for the output signal of the loop : ( 1 ) f _ 3 ^ I ■ ' • NCO p ■L ref i.e. the frequency of the output signal is the fre¬ quency of the reference signal multiplied by the number q/p. In prior art solutions, the numerically con- trolled oscillator 15 of the digital phase-locked loop is typically implemented in two different ways: either based on a counter or based on an accumulator. Figure 2 illustrates an implementation of the numerically controlled oscillator 15 based on a counter. In this case, the implementation is based on a counter 22 which divides with a divisor N and the change of state of which is controlled by an accurate clock signal f ext fed from an external oscillator 21 and by a "lead" signal E and a "lag" signal J received as control data from the loop filter and connected to a counter input A and B, respectively, according to the concerned signal. The counter 22 is implemented by an N-state state machine having the above-mentioned signals E and J as its control signals. When the "lead" signal E is true, the state machine steps in place during one clock period, whereby the phase of the output signal f NC0 is delayed by one clock period of the clock signal f ext of the external oscillator. When the "lag" signal J is true, the state machine skips one state, whereby the phase of the output signal f NC0 is advanced by one clock period of the clock signal f ejtt of the external oscillator. Accord¬ ingly, the length of the phase correction step is always the period length of the output signal f NC0 divided with the divisor N. A drawback of the solution based on the N- counter is that the counter cannot be connected e.g. to a digital filter but it requires a filter of a certain type, such as a so-called lead-lag filter. The digital filter, however, would be a better alternat¬ ive, as it provides a filter with a narrower bandwidth and, more generally, better properties than the simpler lead-lag filter, for instance. Figure 3 illustrates an implementation of an accumulator-type numerically controlled oscillator. In this case the oscillator comprises an adder 31 and a register 32, to which the output of the adder is connected. The input signal of the accumulator-type oscillator is a binary (N-bit) digit x applied to a first input in the adder and indicating the magnitude and direction of the required phase correction. The binary digit is obtained from a digital loop filter, and it varies as a function of time in accordance with the filtering result. An output signal f NC0 is gener- ated by continuously adding binary digits x to the previous value of the register at the frequency of the external clock signal f ext , which clock signal is connected to a clock input C in the register. At the rising edge of the external clock signal the N-bit value of the output signal y of the adder is stored in the register 32, the value of which indicates the current phase of the output signal. The output signal f NC0 of the oscillator is formed by the most signi¬ ficant bit of the register. The N-bit accumulator-type numerically con¬ trolled oscillator generates a frequency obtained from the frequency of the external oscillator in accordance with Formula (2) ( • • ? Δ ) l f J- NCO = -. N ■ f x ext The word width N of the register of the accu¬ mulator-type numerically controlled oscillator affects both the gain factor of the oscillator and the highest frequency that can be generated. In order that a relatively low gain factor could be achieved, the word width has to be great; on the other hand, a great word width also increases the length of the adder and thus also the propagation delay of the adder. The accumul¬ ator-type numerically controlled oscillator can operate only if the length of the period of the external clock signal (l/f ext ) exceeds the delay of the adder. For this reason, it is impossible in many applications to achieve a gain factor low enough. The achievement of a low gain factor, however, is important in order that the phase-locked loop could have a narrow bandwidth. According to a definition known per se, the gain factor K 0 of the accumulator-type numerically con¬ trolled oscillator is the ratio of a change in an angular frequency applied to the phase comparator to a change Δx in a binary digit x controlling the oscil¬ lator: Δx χ 2πf ext 2 N 2πf, ext ( 3 ) K Q = Δx 2 N q In the above Formula (3) a constant q is the divisor of the frequency divider (possibly) provided between the output of the oscillator and the second input of the phase comparator (cf. Figure 1). Another drawback of the accumulator-type oscil¬ lator is that the gain factor cannot be set with any particularly high accuracy (it can be set by varying the word width N) . The digital phase-locked loop and the accumu¬ lator-type numerically controlled oscillator are described e.g. in Digital Phase-Locked Loop with Jitter Bounded . Walters, S. M., Troudet T., IEEE Transactions on Circuits and Systems, Vol. 36, No. 7, July 1989, which is referred to for a more detailed discussion. The object of the present invention is to avoid the above-described drawbacks and to provide a numerically controlled oscillator which has a gain factor which both can be made low and can be set more accurately than previously and which can also be con¬ nected to a digital filter. These objects are achieved by an oscillator according to the invention, which is characterized by what is disclosed in the character- izing portion of the attached claim 1. The phase- locked loop according to the invention, in turn, is characterized by what is disclosed in the charac¬ terizing portion of the attached claim 4. The idea of the invention is to combine the previously known implementations of the numerically controlled oscillator in such a way that the frequency of the phase correction requests of an oscillator section based on a counter is controlled by an accumu¬ lator-type oscillator section. In the following the invention and its preferred embodiments will be described more fully with refer¬ ence to Figure 4 in the examples shown in the attached drawings, where Figure 1 is a block diagram illustrating a digital phase-locked loop known per se; Figure 2 shows one previously known implemen¬ tation of the numerically controlled oscillator of the digital phase-locked loop; Figure 3 shows another previously known imple- mentation of the numerically controlled oscillator of the digital phase-locked loop; and Figure 4 shows an implementation according to the invention of the numerically controlled oscillator of the digital phase-locked loop. Figure 4 is a block diagram illustrating a numerically controlled oscillator implemented accord¬ ing to the invention. The oscillator comprises a first numerically controlled oscillator section 41, which corresponds to the above-described counter-based oscillator implementation shown in Figure 2, where the change of state of a counter 22 is controlled by an accurate clock signal f ext from an external oscillator 21 and by a "lead" signal E and a "lag" signal J, respectively, received as control data. A second numerically controlled oscillator section 42 is con¬ nected to control the first oscillator section. The second oscillator section is based on the accumulator- type oscillator shown in Figure 3, comprising an adder 31 and a register 32, to which the output of the adder is connected and the output of which is fed back to one input in the adder. As the first oscillator section 41 corresponds to the counter-based oscil¬ lator, and the second oscillator section 42 corre¬ sponds substantially to the accumulator-type oscil- lator, the same reference numerals as in Figures 2 and 3 have been used in Figure 4 for corresponding parts. The idea of the invention is to adjust the frequency of the phase correction requests (signals E and J) of the counter-based oscillator section 41 by the accumulator-type oscillator section 42, that is, in fact, by a binary digit x, as the accumulator-type oscillator is controlled by a binary digit, and addi¬ tionally by a signal S indicating the direction of the phase correction. To effect the control, phase control inputs A and B in the first oscillator section are connected to respective outputs in a selector 43, and a selector input is connected to an output in the second oscillator section. The selector is controlled by the direction signal S, which is connected to a control input CTR in the selector. The direction signal S determines whether the output of the second oscillator section 42 is connected to the input A in the first oscillator section, corresponding to the "lead" signal, or to the input B in the first oscil- lator section, corresponding to the "lag" signal. The second oscillator section 42 corresponds otherwise to the accumulator-type oscillator shown in Figure 3 except that the output signal of the register 32, now indicated with the reference f k , is connected to an edge detector circuit 44, the output of which forms an output in the second oscillator section 42, which output is connected to an input in the selector 43. The edge detector circuit detects the rising edges of the output signal f k and shapes the signal such that its pulse width corresponds to the pulse width of the external clock signal f ext (which controls the N counter 22). A signal obtained from the register 32 of the second oscillator section thus has a frequency which can be obtained as follows: ^ f * - ~M f * This frequency is also the frequency of pulses from the output of the edge detector circuit, that is, a signal having this frequency either advances or delays the phase of the counter 22 of the first oscillator section. The frequency of the numerically controlled Oscillator according to the invention can now be calculated from Formula (5) : ( c \ f _ • f* • ext _, ■ "" • f ■* - x In Formula (5), the sign of the ± operation depends on the sign of the phase correction signal S. On the basis of Formula (5), it is possible to cal¬ culate the gain factor of the numerically controlled oscillator shown in Figure 4, which factor, according to a definition known per se, is the ratio of a change in an angular frequency applied to the phase com¬ parator of the phase-locked loop to a change in the controlling binary digit x. The gain factor will thus be: 2πΔf WC0 2π Δxf x 2 M N 2πf K = = - X. (6) ° Δx Δx g 2 M N g where a constant q is the divisor of a frequency divider (possibly) provided between the output of the oscillator and the input of the phase comparator in the feedback loop of the phase-locked signal. It appears from Formula (6) that a low gain factor is easy to achieve in the oscillator according to the invention by setting the frequency of the signal f x to a low value, whereby the value of the gain factor also diminishes. The signal f x controlling storing into the register 32 is, in fact, advanta¬ geously obtained by dividing the frequency of the signal f ext from the external oscillator 21 of the first oscillator section 41 by a divisor m in a fre¬ quency divider 45. The frequency of the signal f x is thus considerably lower than that of the signal f eχt . The numerically controlled oscillator shown in Figure 4 can be connected to a digital loop filter, as the desired control signals x and S are obtained directly from the digital filter, or the output signal of the digital filter is at least easy to shape so that the desired control signals are obtained. The direction signal S, for instance, may be contained in a binary word x obtained from the loop filter, and it can be extracted from the binary word into a separate control signal, which is connected, as described above, to control the selector 43. (In Figure 4, this alternative is shown by an arrow H drawn by a broken line). Even though the invention has been described above with reference to the examples of the attached drawings, it is self-evident that the invention is not limited to the examples, but it may be modified within the inventive idea disclosed above and in the attached claims. For instance, the more detailed switching arrangements of the oscillator and the phase-locked loop may vary, even though the accumulator-type oscil¬ lator section is connected to control the counter-type oscillator section in accordance with the idea of the invention. Essential is that the accumulator-type oscillator section controls the counter-type oscil¬ lator section, whereas it is not essential in which way it is connected to control the counter-type oscil- lator section, i.e. whether it is connected to the counter-type oscillator section directly or through various intermediate circuits irrelevant to the idea of the invention. The solution according to the inven¬ tion is not only applicable in all digital phase locks where the oscillator is controlled by a binary word but, in principle, it is also possible to use the invention in other applications where a similar control is available.

Claims: Claims : 1. Numerically controlled oscillator comprising a first oscillator section (41) having a counter (22) acting as a frequency divider and an external oscil¬ lator (21) supplying a clock signal (f ext ) connected to the counter (22) for generating an output signal (f NC0 ) with a divided frequency from said clock signal, the counter (22) comprising at least one phase control input (A, B) for connecting phase correction requests to the counter (22) for adjusting the phase of said output signal (f NC0 ) in a desired direction, c h a r¬ a c t e r i z e d in that a second accumulator-type oscillator section (42) known per se is connected to control the phase of the output signal (f NC0 ) of the first oscillator section (41), the second oscillator section comprising an adder (31) and a register (32), to which the output of the adder is connected, the adder (31) having a first input for connecting a binary digit (x) to control said second oscillator section (42), and a second input for feeding the output signal of the register back to the adder (31). 2. Oscillator according to claim 1, comprising two phase control inputs (A, B), c h a r a c t e r- i z e d in that said accumulator-type oscillator section (42) is operationally connected to one of the phase control inputs through a selector (43), which comprises means for connecting a signal present at its input to a desired output. 3. Oscillator according to claim 1, c h a r a c¬ t e r i z e d in that a clock input (C) in said register (32), to which a clock signal (f x ) is con- nectable to control storing into the register, is connected to said external oscillator (21) through a frequency divider (45) for dividing the frequency of the signal (f ext ) from the external oscillator (21) before connecting it to the clock input (C) in the register. 4. Phase-locked loop comprising - a phase comparator (13) having at least two comparator inputs for comparing the phases of signals connected to the inputs; - a lowpass-type loop filter (14) having an input to which the output of the phase comparator is connected; and a numerically controlled oscillator (15) arranged to be controlled by the loop filter (14) and comprising a first oscillator section (41) having a counter (22) acting as a frequency divider and an external oscillator (21) supplying a clock signal (f ext ) connected to the counter (22) for generating an output signal (f NC0 ) with a divided frequency from said clock signal, the counter (22) comprising at least one phase control input (A, B) for connecting phase cor- rection requests to the counter (22) for adjusting the phase of said output signal (f NC0 ) i- n a desired direction, c h a r a c t e r i z e d in that a second accumulator-type oscillator section (42) known per se is connected to control the phase of the output signal (f N∞ ) of "the first oscillator section (41), the second oscillator section comprising an adder (31) and a register (32), to which the output of the adder is connected, the adder (31) having a first input con¬ nected operationally to the loop filter (14) for con- necting the loop filter to control said second oscil¬ lator section (42), and a second input for feeding the output signal of the register back to the adder (31). 5. Phase-locked loop according to claim 4, comprising two phase control inputs (A, B), c h a r - a c t e r i z e d in that said - accumulator-type oscillator section (42) is operationally connected to one of the phase control inputs through a selector (43), which comprises a control input (CTR) operat¬ ionally connected to the loop filter (14) for con- necting the loop filter to control the switching of a signal present at the selector input to a desired selector output. 6. Phase-locked loop according to claim 4, c h a r a c t e r i z e d in that a clock input (C) in said register (32), to which a clock signal (f x ) is connectable to control storing into the register, is connected to said external oscillator (21) through a frequency divider (45) for dividing the frequency of the signal (f βxt ) from the external oscillator (21) before connecting it to the clock input (C) in the register.

Inventors: PELTOLA SEPPO, PELTOLA, SEPPO
Applicants: NOKIA TELECOMMUNICATIONS OY, PELTOLA SEPPO, PELTOLA, SEPPO
Application year: 1994
Main classification: H03L7
IPC codes: H03B28, H03L7