Amplifier

Abstract: This invention has as its object to prevent the lower limit value of the linear input range of an amplifier from being changed even when the threshold voltage of a transistor varies. In order to achieve this object, a power supply voltage to be applied to the source electrode of a field effect transistor 17 which receives an input of the amplifier is supplied by an output from a source follower 21, 22 constituted by a field effect transistor. A power supply voltage to be applied to the emitter electrode of a bipolar transistor which receives an input of the amplifier is supplied by an output from an emitter follower constituted by a bipolar transistor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an amplifier and, more particularly, to an amplifier constituted by transistors. The present invention is suitably used as a pre-amplifier for amplifying, e.g., a sensor signal and the like. Related Background Art Fig. 3 shows an equivalent circuit diagram of a two-dimensional sensor using a conventional pre-amplifier. Referring to Fig. 3, the sensor comprises photoelectric conversion cells each constituted by a bipolar transistor 1 constituting a sensor for accumulating carriers generated upon incidence of light energy at its base, a capacitor 2 for controlling the base potential of the bipolar transistor 1, and a p-MOS transistor 3 for resetting the base potential of the bipolar transistor 1. The sensor further comprises drive lines 4 for driving each cell, vertical output lines 5 connected to the emitters of the bipolar transistors 1, buffer MOS transistors 6 each of which is selected by a vertical shift register and supplies pulses to the drive line 4 to be driven, a pulse input terminal 7 for applying drive pulses, capacitors 8 for accumulating output signal voltages from the cells, MOS transistors 9 each for switching between the vertical output line 5 and the capacitor 8, a horizontal output line 10, MOS transistors 11 each of which is selected by an output from a horizontal shift register, and transfers a signal voltage from the corresponding capacitor 8 onto the horizontal output line 10, a MOS transistor 12 for resetting the horizontal output line 10, MOS transistors 13 for resetting the sensor cells, the vertical output lines 5, and the capacitors 8, a power supply terminal 14 for applying a reset voltage as a reference voltage of this sensor system, a terminal 15 for applying pulses to the gates of the MOS transistors 9, a terminal 16 for applying pulses to the gates of the MOS transistors 13, an amplifier MOS transistor 17 whose gate is connected to the horizontal output line 10, a load MOS transistor 18 whose well and source are connected to the drain of the amplifier MOS transistor 17, and whose gate and drain are connected to the power supply voltage, a terminal 19 for applying pulses to the gate of the MOS transistor 12, and an output terminal 20 of a pre-amplifier defined by the amplifier MOS transistor 17 and the load MOS transistor 18. Fig. 3 exemplifies the sensor having 2 × 2 cells for the sake of simplicity. The operation of this conventional two-dimensional sensor is described in Japanese Patent Application Laid-Open No. 63-186466. The characteristics of the pre-amplifier defined by the MOS transistors 17 and 18 will be described below with reference to Fig. 4. If the transconductances of the MOS transistors 17 and 18 are respectively represented by g m1 and g m2 , the ratio ΔV OUT /ΔV in of a change ΔV OUT in output voltage to a change ΔV in in input voltage, i.e., the gain, is given by: - g m1 / g m2 Both the MOS transistors 17 and 18 have constant transconductances g m1 and g m2 in a saturation region, and the amplifier output becomes linear with respect to the input. If the linear input range is assumed to be a range between V 1 and V 2 , these voltages V 1 and V 2 are respectively theoretically given by V 1 = v th and V 2 = V DD /(1 + g) + g/(1 + g)·V th (where V th is the threshold value of the MOS transistors 17 and 18, V DD is the power supply voltage, and -g is the gain of the amplifier). The input voltage to this amplifier ranges from V VC to (V VC + V SAT ) (where V VC is the reference reset potential of the sensor and V SAT is the saturation voltage of the sensor). When the amplifier is set to satisfy V 1 < V VC and (V VC + V SAT ) < V 2 , as shown in Fig. 4, the sensor output can be amplified with high linearity. However, in the above-mentioned prior art, since the threshold voltage V th of the MOS transistor for defining the linear input range of the pre-amplifier varies due to a variation in an element formation process or a change in operation temperature, the linear input range (V 1 to V 2 ) of the amplifier may deviate from the amplifier input range (V VC to V VC + V SAT ). When V VC is set to be relatively high to satisfy V th (= V 1 ) < V VC even if the threshold voltage V th varies, and the linear input range is widened to satisfy (V VC + V SAT ) < V 2 , the gain g of the amplifier must be decreased. Document GB-A-2,184,623 also discloses an amplifier circuit which compensates for the threshold voltage, V th of a MOS transistor. However, this prior art uses more transistors and a different approach to the present invention. SUMMARY OF THE INVENTION The invention is defined by the appended claims. According to the present invention, since the power supply voltage to be applied to the source electrode of a field effect transistor for receiving an input to an amplifier is supplied by the output from a source follower constituted by a field effect transistor, the lower or upper limit of a linear input range of the amplifier has a value lower than or higher than the lower or upper limit of an input voltage range regardless of a variation in threshold voltage of the field effect transistor, and the like. According to the present invention, since the power supply voltage to be applied to the emitter electrode of a bipolar transistor for receiving an input to an amplifier is supplied by the output from an emitter follower constituted by a bipolar transistor, the lower or upper limit of a linear input range of the amplifier has a value lower than or higher than the lower or upper limit of an input voltage range regardless of a variation in threshold voltage of the bipolar transistor, and the like. For example, when an input signal is assumed to be a sensor signal output from an optical sensor in a photoelectric conversion device, a voltage lower than the reset potential of the sensor by the threshold voltage value of the field effect transistor is formed using the source follower, and this voltage is supplied to the source electrode of the transistor which receives the input to the amplifier. Therefore, even when the threshold voltage of the field effect transistor varies, the lower limit value of the linear input range of the amplifier can be controlled to be unchanged, and input/output characteristics of the amplifier with a high gain and a small V th variation dependence can be realized. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing the first embodiment of an amplifier according to the present invention; Fig. 2 is a circuit diagram showing the second embodiment of an amplifier according to the present invention; Fig. 3 is a circuit diagram showing a sensor using a conventional amplifier; and Fig. 4 is a graph showing the input/output characteristics of the amplifier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The embodiments to be described below will exemplify a case wherein the present invention is applied to a pre-amplifier used in a two-dimensional sensor. However, the present invention is not limited to such an application. FIRST EMBODIMENT Fig. 1 is a circuit diagram showing the first embodiment of an amplifier according to the present invention. Note that the same reference numerals in Fig. 1 denote the same parts as in Fig. 3, and a detailed description thereof will be omitted. Referring to Fig. 1, a MOS transistor 21 is connected to a resistor 22. A voltage (V VC ) of a reset power supply level of an amplifier input is applied from a terminal 14 to the gate and drain of the MOS transistor 21. The MOS transistor 21 and the resistor 22 constitute a source follower, and the output of the source follower, i.e., the source of the MOS transistor 21 serves as a low-voltage power supply of the amplifier. If the threshold value level of the MOS transistor 21 is represented by V th , the source follower output level is given by ( V VC - V th - Δ) (where Δ is a small voltage determined by the design value of the source follower). When the low potential of the amplifier is determined in this manner, the lower limit of the linear input range of the amplifier is defined by (V VC - Δ), and always has a margin Δ from the minimum value V VC of the amplifier input. When a MOS transistor 17 and the MOS transistor 21 are formed at positions close each other on a single chip, the threshold values of these transistors have substantially the same variation amounts which are caused by a variation in the manufacture and a change in temperature. For this reason, large margins need not be provided to the lower limit value of the linear input range and the voltage V VC in consideration of a variation in threshold voltage value unlike in the prior art, and an amplifier with a large gain and a wide input range can be designed. SECOND EMBODIMENT Fig. 2 shows the second embodiment of an amplifier according to the present invention. Referring to Fig. 2, the substrate-side electrode and the source electrode of the MOS transistor 17 are connected to each other, and the substrate-side electrode and the source electrode of the MOS transistor 21 are connected to each other. In the first embodiment, the source electrode and the substrate-side electrode of a transistor 18 are connected to each other, while the MOS transistor 17 has different source and substrate potentials and is back-gate-biased. For this reason, due to different channel mobilities of the MOS transistors 17 and 18, the gain of the amplifier may be lowered. However, with the arrangement shown in Fig. 2, since the MOS transistors 17 and 18 always have the same channel mobility, the amplifier gain can be accurately designed. The input range of the amplifier becomes constant with respect to a variation in threshold voltage of the MOS transistor in the same manner as in the first embodiment. In each of the above embodiments, the lower limit of an input voltage is set based on a predetermined reset potential. Of course, the present invention can be applied to a case wherein the upper limit of the input voltage is set based on the predetermined reset potential. For example, when n-MOS transistors as constituting elements in Fig. 1 are replaced by p-MOS transistors, a high potential V DD replaces GND and GND replaces the drain power supply for the transistor 18. At this time, the upper limit of an input voltage to an amplifier constituted by p-MOS transistors is set based on the reset potential. The present invention is not limited to an amplifier constituted by field effect transistors, but may be applied to an amplifier constituted by bipolar transistors. In this case, the power supply voltage to be applied to the emitter electrode of a bipolar transistor for receiving an input can be supplied by an output from an emitter follower constituted by a bipolar transistor. As described above, according to the present invention, since the power supply voltage to be applied to the source electrode of a field effect transistor for receiving an input to an amplifier is supplied by the output from a source follower constituted by a field effect transistor, or since the power supply voltage to be applied to the emitter electrode of a bipolar transistor for receiving an input to an amplifier is supplied by the output from an emitter follower constituted by a bipolar transistor, even when the threshold value voltages of transistors constituting the amplifier deviate from a design value due to a manufacturing condition or a change in temperature, the linear input range of the amplifier can be controlled to be unchanged. For this reason, an amplifier with a high gain and a wide input range can be provided. This invention has as its object to prevent the lower limit value of the linear input range of an amplifier from being changed even when the threshold voltage of a transistor varies. In order to achieve this object, a power supply voltage to be applied to the source electrode of a field effect transistor 17 which receives an input of the amplifier is supplied by an output from a source follower 21, 22 constituted by a field effect transistor. A power supply voltage to be applied to the emitter electrode of a bipolar transistor which receives an input of the amplifier is supplied by an output from an emitter follower constituted by a bipolar transistor.

Claims: An amplifier comprising: a first field effect transistor (17) connected to an input terminal receiving an input; a second field effect transistor (12) for resetting the input terminal at a reference voltage (Vvc); and a third field effect transistor (21) having drain and gate connected to the reference voltage (Vvc), and a source connected to said first field effect transistor (17); wherein an output from said third field effect transistor (21) is supplied to a source of said first transistor (17). An amplifier according to claim 1, wherein said first and third transistors (17, 21) have respectively substrate side electrodes and source electrodes connected in a short circuiting manner. An amplifier according to claim 1, wherein said first and third transistors (17, 21) are formed close to each other on the same chip. An amplifier comprising: a first bipolar transistor (17) connected to an input terminal receiving an input; a second bipolar transistor (12) for resetting the input terminal at a reference voltage (Vvc); and a third transistor (21) having collector and base connected to the reference voltage (Vvc), and an emitter connected to said first bipolar transistor (17); wherein an output from said third transistor (21) is supplied to an emitter of said first bipolar transistor (17).

Inventors: SHINOHARA MAHITO, SHINOHARA, MAHITO, SHINOHARA, MAHITO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: H03F3
IPC codes: H03F3