Device for converting the frame rate of an image

Abstract: This invention relates to a device for converting image signal frame format including a motion compensation means for restoring image signals by carrying out motion compensations employing motion information, variable length decoded and inverse multiplex converted, and displaced frame difference, variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted, and a first frame ratio conversion means for classifying areas by pixels employing the motion information, variable length decoded and inverse multiplex converted, macroblock type information and the displaced frame difference, variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted, and for converting frame ratios of image signals received from the motion compensation means according to the classified areas. Accordingly, this invention provides users with advantages of watching natural display picture having good picture quality by carrying out classification of the corresponding pixel areas and subsequent interpolation easily utilizing various informations applied from an image signal decoder.

Description: FIELD OF THE INVENTION This invention relates to a device for converting the frame rate of an image signal, more particularly to a device for converting image signal frame format which can convert frame rate through frame interpolation. BACKGROUND OF THE INVENTION In general, digital transmission of image signal requires high compression. For example, in transmission methods of image signals, there are H.261 for teleconferencing, MPEG I for multimedia, MPEG II for multipurpose use such as for a digital TV etc., and, besides, a compression method for HDTV, all of which employ, for a high compression, a method for compressing through compensation of motion so as to eliminate duplication existing on time base. Especially, in order to raise compression ratio of H.261 and MPEG I, a dessimination is carried out lowering frame rate for a coding, other than the method for compression through compensation of motion explained above. That is, the compression is carried out with a lowered frame rate to 25Hz or 30Hz. However, even though a transmission has been carried out compressed with a lowered frame rate to 25Hz ot 30Hz, signals transmitted compressed with a lowered frame rate to 25Hz or 30Hz should be converted into signals with a frame rate of 50Hz or 60Hz for displaying on a monitor at the stage of final display. And to accommodate film modes with a frame rate of 24Hz or 30Hz, film mode signals transmitted compressed to a frame rate 24Hz or 30Hz should be converted into signals with a frame rate of 60Hz to facilitate displaying on a monitor at the final display stage. SUMMARY OF THE INVENTION The object of this invention for the foregoing can be achieved by providing a device for converting the frame rate of an image signal which can convert frame rates through classification of areas by pixels, and carrying out compensation of motion and averaging interpolation according to the classified areas. These and other objects and features of this invention can be achieved by providing a device having the features of appended claim 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram of a device for converting image signal frame rates in accordance with this invention. FIG.2 shows area markings of pixels classified in accordance with this invention. FIG.3 shows a basic unit for coding. FIG.4 shows details of the frame rate converter of FIG.1. FIG.5 shows signal wave patterns for each part of FIG.4. FIG.6 shows details of the pixel area classification part of FIG.4. FIG.7 shows details of another embodiment of the frame rate conversion part of FIG.1. FIG.8 shows details of a 60Hz/59.94Hz frame rate conversion part. FIG.9 shows details of the control part of FIG.8. FIG.10 shows details of a 59.94Hz/60Hz frame rate conversion part. FIG.11 shows details of the control part of FIG.10. DETAILED DESCRIPTION OF THE INVENTION. Details of this invention is to be explained hereinafter, referring to attached drawings. As shown in FIG.1, a device for converting frame rate in accordance with this invention includes a variable length decoding and inverse multiplex conversion part 100, an inverse quantization conversion part 200, a inverse discrete cosine conversion part 300, a motion compensation part 500, and a frame rate conversion part 400, for converting frame rates of image signals. The variable length decoding and inverse multiplex conversion part 100 restores the incoming compressed bit stream to meaningful signals by carrying out variable length decoding, and classifies into motion information, macroblock type information, quantum conversion coefficient and control parameters by carrying out inverse multiplex conversion. The inverse quantization conversion part 200 carries out an inverse quantization conversion according to the quantum conversion coefficient received from the variable length decoding and inverse multiplex conversion part 100, and the inverse cosine conversion part 300 generates displaced frame difference(DFD) based on motion ratio estimation by carrying out a inverse cosine conversion of the inverse quantization converted signals at the inverse quantization conversion part 200. The motion compensation part 500 restores image signals by carrying out motion compensation using the motion information, variable length decoded and inverse quantization converted, and received from the variable length decoding and inverse quantization conversion part 100, and the DFD received from, and variable length decoded and, inverse multiplex, inverse quantization, and inverse discrete cosine converted at the variable length decoding and inverse multiplex conversion part 100, the inverse quantization conversion part 200 and the inverse cosine conversion part 300, respectively. The frame rate conversion part 400 classifies the image signal areas into still areas, motion compensation areas, covered areas and uncovered areas classified by pixels using the motion information, variable length decoded and inverse multiplex, macrobolck type information, and the DFD received from, and variable length decoded and inverse multiplex, inverse quantization, and inverse discrete cosine converted at the variable length decoding and inverse multiplex conversion part 100, inverse quantization conversion part 200, and inverse cosine conversion part 300, respectively, and converts the frame ratios of the image signals received from the motion compensation part 500 according to the classified areas. One frame 9 to be subjected to an interpolation is classified into still areas, motion compensation areas, covered areas and uncovered areas by pixels, which classified areas have, as shown in FIG.2, still areas 4 areas having no changes between front and rear frames (n)th and (n+1)th ie., between adjoining two frames 8 and 9, motion compensation areas 5 motion compensation have to be carried out due to existence of motion, covered areas 7 appearing from behind a coverage as the motion part moves and uncovered areas 6 being covered as the motion part moves. Herein, details of the motion compensation part 500 and the frame rate conversion part 400 are to be explained. The motion compensation part 500 includes a motion compensator 501 for compensating motion using the motion information, variable length decoded and inverse multiplex converted at the variable length decoding and inverse multiplex conversion part 100, an adder 502 for adding the DFD received from, and variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted at the variable length decoding and inverse multiplex conversion part 100, inverse quantization conversion part 200 and inverse discrete cosine conversion part 300, respectively, and signals received from and motion compensated at the motion compensator 501, and for transmitting the image signals to the frame conversion part 400, and a frame memory 503 for storing image signals received from the adder 502 for the motion compensation of the next frame and for transmitting the stored image signals to the motion compensator 501. One embodiment of the frame rate conversion part 400 includes a summer 401 for summing up the DFD in macroblock units received from, and variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted at the variable length decoding and inverse multiplex conversion part 100, the inverse quantization conversion part 200 and the inverse discrete cosine conversion part 300, respectively, a latch 402 for temporary storing of the DFD received from the summer 401 in macroblock units, a latch 403 for temporary storing of the motion information received from, and variable length decoded and inverse multiplex converted at the variable length decoding and inverse multiplex conversion part 100 in order to compensate delay at the summer 401, a latch 404 for temporary storing of the macroblock type information received from, and variable length decoded and inverse multiplex converted at the variable length decoding and inverse multiplex converoion part 100 in order to compensate for the delay at the summer 401, and a frame rate converter 405 for converting frame rates by forming one frame through classifying areas by pixels utilizing the image signals received from the motion compensation part 500 and signals received from the latches 402,403 and 404, and carrying out corresponding interpolations according to the result of the classification. The compressed bit stream applied to the variable length decoding and inverse multiplex conversion part 100 is restored to meaningful signals by undergoing a variable length decoding, and classified into motion information, macroblock type information, quantum conversion coefficient and control parameters by undergoing a inverse multiplex conversion, at the variable length decoding and inverse multiplex conversion part 100, the control parameters transmitted from the variable length decoding and inverse multiplex conversion part 100 to the inverse quantization conversion part 200 is converted into inverse quantization at the inverse quantization conversion part 200 according to the quantum conversion coefficient received from the variable length decoding and inverse multiplex conversion part 100, and the signals converted into inverse quantization is undergone a inverse discrete cosine conversion at the inverse discrete cosine conversion part 300 restoring the DFD based on estimated motion path of image. Image signals of front one frame stored in the frame memory 503 is undergone a motion compensation at the motion compensator 501 according to the motion information received from the variable length decoding and inverse multiplex conversion part 100, which is, combined with the DFD received from the inverse discrete cosine conversion part 100 at the adder 502, producing image signals which is transmitted to the frame rate converter 405 and stored into the frame memory 503. The image signals transmitted from the adder 502, being mostly image signals having a frame rate of 25Hz or 30Hz, should be converted into image signals with two times of frame ratio of 50Hz or 60Hz in order to display on a monitor. To do this,the DFD transmitted from, and undergone a variable length decoding and inverse multiplex, inverse quantization and inverse discrete cosine conversion through the variable length decoding and inverse multiplex conversion part 100, the inverse quantization conversion part 200 and the inverse discrete cosine conversion part 300, respectively, is summed up into macroblock units, and stored in the latch 402, temporarily. And the motion information transmitted from, and undergone a variable length decoding and inverse multiplex conversion at the variable length decoding and inverse multiplex conversion part 100 is stored in the latch 403, temporarily in order to compensate delay at the summer 401, and the macroblock type information transmitted from, and undergone a variable length decoding and inverse multiplex conversion in the variable length decoding and inverse multiplex conversion part 100 is stored in the latch 404 temporarily in order to compensate delay at the summer 401. As shown in FIG.3, basic unit for coding is a macroblock 1 which has m ≠ n pixels. And M/m macroblocks makes one slice 2, and one slice has n x M pixels. N/n slice 2 makes one frame 3. Since one frame has M x N pixels, one frame comes to have (N/n) x(M/m) blocks. Therefore, to know the rate of change between frames, signals coded and transmitted in macroblock units should be waited until they are piled up to make one frame. This is the reason why the DFD received from the inverse discrete cosine conversion part 300 should be gathered in macroblock units in the summer 401, and to compensate for the delay of time for the gathering, the latches 403 and 404 are required. The signals transmitted from the latches 402, 403 and 404 to the frame rate converter 405 is used for classifying into still areas, motion compensation areas, covered areas and uncovered areas at the frame rate converter 405, based on which required interpolation can be carried out at the frame rate conversion part 405 using the image signals received from the motion compensation part 500. Details of the frame rate converter 405 is to be explained hereinafter, referring to the FIG.4. As shown in FIG.3, the frame rate converter 405 includes a frame memory 410 for storing image signals received from the motion compensation part 500, a divider 420 for dividing the motion information received from the latch 403 by 2, a interpolation control part 440 for classifying into still areas, motion compensation areas, covered areas and uncovered areas classified by pixels using signals received from the latches 402 and 404 and the divider 420, an interpolation part 430 for carrying out interpolation to complete one frame using image signals received from the frame memory 410 and signals received from the divider 420 under the control of the compensation control part 440, a frame memory 450 for temporary storing of the image signals received from the frame memory 410 to match the synchronization, a frame memory 460 for temporary storing of the image signals received from the interpolation part 430 to match the synchronization, and a multiplexer 470 for selecting and transmitting one of the image signals received from the frame memories 450 and 460 under the control of the compensation control part 440. Herein, the frame memory 450 and 460 may be removed making the multiplexer 470 to select and transmit one of the signals received from the frame memory 410 and the compensation part 430,directly. The interpolation control part 440 includes a comparator 441 for comparing the DFD received from the latch 402 to a preset critical value, a pixel area classification part 442 for controlling the interpolation part 430 classifying into still areas, motion compensation areas, covered areas and uncovered areas by pixels using signals received from the divider 420, the latch 404 and the comparator 441, and a scene change detection part 443 for controlling output of the multiplexer 470 detecting changes of scenes using signals received from the comparator 441. The scene change detection part 443 includes a summer 444 for summing signals received from the comparator 441 in frame units, a comparator 445 for comparing the signals received from the summer 444 to a critical value, and a delay compensator 446 for compensating delays by storing signals received from the comparator 445 temporarily, and for controlling the output of the multiplexer 470. The interpolation part 430 includes a frame memory 431 for storing the image signals received from the frame memory 410, an averaging interpolation part 432 for carrying out interpolation with the average of two frames using the image signals received from the frame memories 410 and 431, a motion compensation region interpolation part 434 for carrying out motion compansation using signals received from the frame memory 431 and the divider 420 under the control of the pixel area classification part 442, a frame memory 435 for storing signals received from the motion compensation region interpolation part 434, and a multiplexer 433 for selecting and transmitting signals received from the frame memories 410, 431 and 435 and the averaging interpolation part 432 under the control of the pixel area classification part 442. The averaging interpolation part 432 includes an adder 436 for adding the image signals received from the frame memories 410 and 431, and a divider 437 for dividing signals received from the adder 436 by 2. Operation of the frame rate converter 405 having the foregoing is to be explained hereinafter, referring to FIG.5. The image signals B transmitted from the adder 502 of the motion compensation part 500 is stored into the frame memory 410 in frame units according to the input frame clock A, and the image signals C stored in the frame memory 410 in frame units is stored into the frame memory 431, again. Herein, the image signals stored in the frame memories 410 and 431 in frame units are for adjoining two frames ie., for frames front and rear (n+1)th and (n)th. The image signals stored in the frame memories 410 and 431 are, added in the adder 436 and divided by 2 in the divider 437, become average values between two frames. The motion information received from the latch 403 of the frame conversion part 400 is,divided by 2 at the divider 420, become an average value between two frames, and transmitted to the motion compensation region interpolation part 434 and the pixel area classification part 442. The average motion information received from the divider 420 is used for carrying out motion compensation of the image signals received from the frame memory 431 at the motion compensation region interpolation part 434 under the control of the pixel area classification part 442. The image signals D motion compensated at the motion compensation region interpolation part 434 are, after stored in the frame memory 435 temporarily, transmitted to the multiplexer 433.E. The image signals transmitted from the frame memories 410, 431 and 435 and the divider 437 of the averaging interpolation part 432 to the multiplexer 433 is selected and transmitted under the control of the pixel area classification part 442. The process for contolling the multiplexer 433 to select and transmit one of the applied image signals is to be explained hereinafter. The DFD summed up in macroblock units transmitted from the latch 402 of the frame rate conversion part 400 to the comparator is compared with a critical value preset to determine the areas as motion compensation areas. And the motion information received from the latch 403 of the frame rate conversion part 400 is divided by 2 at the divider 420 in order to compute the average motion information between two frames. The macroblock type information transmitted from the latch 404 of the frame rate conversion part 400 together with the signals transmitted from the comparator 441 and the divider 420 to the pixel area classification part 442 are used for interpolation after classified into still areas, motion compensation areas, covered areas and uncovered areas by pixels at the pixel area classification 442. That is, if the DFD in macroblock units transmitted from the latch 402 is greater than the critical value, determining that it is an uncovered area unconditionally at the pixel area classification part 442 irrespective of the macroblock type information, the multiplexer 433 is controlled to transmit a corresponding image signals after selecting the corresponding image signals from the front frame (n)th received from the frame memory 431. And if the DFD in macroblock units transmitted from the latch 402 is smaller than or same with the critical value and the macroblock type information is appeared to have been coded in intraframe coding, determining that it is an uncovered area at the pixel area classification part 442, the multiplexer 443 is controlled to transmit a corresponding signal after selecting the corresponding image signal from the front frame (n)th received from the frame memory 431. And if the DFD in macroblock units transmitted from the latch 402 is smaller than or the same with the critical value and the macroblock type information is appeared to have been coded in motion compensated coding, determining that it is covered area or motion compensation area at the pixel area classification part 442, the multiplexer 433 is controlled to transmit a corresponding image signal after selecting the corresponding image signal either from the next frame (n+1)th received from the frame memory 410 or from the motion compensation frame received from the frame memory 435. And if the DFD in macroblock units transmitted from the latch 402 is smaller than or the same with the critical value and the macroblock type information is appeared to have been coded in non motion compensated intraframe coding, determining that it is a still area, the multiplexer 433 is controlled to transmit an image signal after selecting the image signal from the average value of corresponding pixel from the front and rear frame (n)th and (n+1)th received from the averaging interpolation part 432. In this instant, if corresponding pixel is determined to be a still area at the pixel area classification part 442, the multiplexer 433 is controlled to transmit after selecting from either the front frame (n)th or the rear frame (n+1)th. The image signals transmitted from the frame memory 410 and the multiplexer 433 are, stored temporarily in the frame memories 450 and 460 respectively to match synchronization, and selected and transmitted from the multiplexer 470 under the control of the scene change detection part 443.G. The signals transmitted from the comparator 441, summed up at the summer 444 in frame units, compared with a critical value preset to determine the signal to be a scene change at the comparator 445, and delay compensated matching synchronization at the delay compensator 446, controls the multiplexer 470 to select an output. That is, if the signal received from summer 444 is found to be greater than the critical value as the result of comparison at the comparator 445, determining that the scene has been changed, the multiplexer 470 is controlled to select and transmit an image signal of the next frame (n+1)th received from the frame memory 450. And if the signal received from summer 444 is found to be smaller than or the same with the critical value as the result of comparison at the comparator 445, determining that the scene has not been changed, the multiplexer 470 is controlled to select and transmit the image signals received from the frame memories 450 and 460,alternatively.G. Then, the multiplexer 470 finally transmits an image signal corresponding to two times of the frame rate of the received image signals to facilitate a display on a monitor. Details of the pixel area classification part 442 of the interpolation control part 440 is to be explained hereinafter, referring to FIG.6. As shown in FIG.6, the pixel area classification part 442 of the interpolation control part 440 includes a macroblock type classifier 481 for classifying the macroblock type information received from the latch 404 of the frame rate conversion part 400 into intraframe information and motion compensation information, an inverter 485 for inverting signals received from the comparator 441 of the interpolation control part 440, an AND gate 486 for determining a motion compensation area by logic multiplying of the signals received from the inverter 485 and the motion compensation information received from the macroblock type classifier 481, and for transmitting the motion compensation area to the motion compensation region interpolation part 434, a memory 487 for storing the position of the corresponding pixel using signals received from the divider 420 in response to the signal received from the AND gate 486, a delay compensator 482 for compensating delays by storing signals received from the macroblock type classifier 481, an interpolation selection controller 483 for controlling the multiplexer 433 in response to the signals stored in the memory 487 and received from the delay compensator 482, and a delay compensator 484 for compensating delays by storing the signals received from the interpolation selection controller 484 and transmitting the delay compensated signals to the multiplexer 433. The macroblock type information received from the latch 404 is, after classified into intraframe information and motion compensation information at the macroblock type classifier 481, temporarily stored into the delay compensator 484. In this instant, since the intraframe information and the motion interpolation information classified at and received from the macroblock type classifier 481 show that whether the corresponding pixel has been coded in intraframe coding, motion compensated coding, or non motion compensated intraframe coding, if it is found that the corresponding pixel has been coded in intraframe coding, the pixel is determined to be an uncovered area, if it is found that the corresponding pixel has been coded in motion compensated coding, the pixel is determined to be either covered area or motion compensated area, and if it is found that the corresponding pixel has been coded in non motion compensated intraframe coding, the pixel is determined to be a still area. In this instant, if the corresponding pixel has been coded in motion compensated coding, in order to classify the corresponding pixel into covered area and motion compensated area, the output of the comparator 485 is utilized, which process is to be explained hereinafter. The signals received from the comparator 441 is transmitted after inverted at the inverter 485, logic multiplied at the AND gate 486 together with motion compensated information received from the macroblock type classifier 481. The signals received from the AND gate 486, signals showing that the corresponding pixel has been interpolated through a motion compensation, does not actuate the motion compensation region interpolation part 434 in case the signal shows that the corresponding pixel has not been motion compensated, but actuate the motion compensation region interpolation part 434 only in case the signal shows that the corresponding pixel has been motion compensated for the motion compensation of the corresponding. Data indicating motion compensated position within a frame received from the diveder 420 in response to the signal received from the AND gate 486 is stored in the memory 487. That is, in case the signal received from the AND gate 486 indicates that the corresponding pixel has been motion compensated, the motion compensated position within a frame is stored into the memory 487 using the motion information divided by 2 received from the divider 420, and in case the signal received from the AND gate 486 indicates that the corresponding pixel has not been motion compensated, the memory 487 is not actuated. The interpolation selection controller 483 classifies the corresponding pixels into covered areas and motion compensated areas in case the delay compensated signal at the delay compensator 482 shows that the corresponding pixel has been written in motion compensated coding. That is, in case the corresponding pixel corresponds the motion compensated position stored in the memory 487, determining that the corresponding pixel is a motion compensated area, the interpolation selection controller 483 controls the multiplexer 433 to select and transmit the image signals stored in the frame memory 435 in order to generatio a motion compensated image signals, and in case the corresponding pixel does not corresponds the motion compensated position stored in the memory 487, determining that the corresponding pixel is a covered area, the interpolation selection controller 483 controls the multiplexer 433 to select and transmit the image signals stored in the frame memory 410 in order to select a corresponding image signals from the rear frame (n+1)th. In another words, the interpolation selection controller 483 transmits signals for controlling the multiplexer 433 based on the determination through classifying into uncovered area, still area, and covered area or motion compensated area based on signals received from the delay compensator 482, and further based on determination through classifying into covered area and motion compensated area based on signals stored in the memory 487, . That is, the interpolation selection controller 483 controls the multiplexer 433 to select the output of, the divider 437 in order to interpolate with the average of both frames in case the signals received from the delay compensator 482 shows that the corresponding pixel is a still area, the frame memory 435 in order to interpolate through motion compensation in case the signals received from the delay compensator 482 and the memory 487 show that the corresponding pixel is a motion compensated area, the frame memory 410 in order to interpolate using the image signals of rear frame (n+1)th in case the signals received from the delay compensator 482 and the memory 487 show that the corresponding pixel is a covered area, and the frame memory 431 in order to interpolate using the image signals of the front frame (n)th in case the signals received from the delay compensator 482 shows that the corresponding pixel is an uncovered area. Further, the interpolation selection controller 483 may control the multiplexer 433 either to select the output of the frame memory 431 in order to interpolate using the image signals of the front frame (n)th ,or the output of the frame memory 410 in order to interpolate using the image signals of rear frame (n+1)th in case the signals received from the delay compensator 482 shows that the corresponding pixel is a still area. The signals received from the interpolation selection controller 483 is, delay compensated stored in the delay compensator 484, and applied to the multiplexer 433 in order to control the multiplexer 433. Another embodiment of the frame rate conversion part 400 is to be explained hereinafter, referring to FIG.7. As shown in FIG.7, another embodiment of the frame rate conversion part 400 includes frame memories 620 and 620 connected in series for storing the image signals in frame units received from the motion compensator 500, a motion estimation part 600 for estimating motion information and DFD using image signals of two adjoining frames received from the frame memories 610 and 620, a divider 680 for dividing the motion information received from the motion estimation part 600 by 2, a interpolation control part 670 for classifying areas by pixels using the motion information received from the motion estimation part 600 and the signals received from the divider 680, a interpolation part 630 for completing one frame by carrying out interpolation using the image signals received from the frame memories 610 and 620 and the signals received from the divider 680 under the control of the interpolation control part 670, a frame memory 640 for storing the image signals received from the frame memory 610 temporarily to match the synchronization, a frame memory 650 for storing the image signals received from the interpolation part 630 temporarily to match the synchronization, and a multiplexer 660 for selecting and transmitting one of the image signals received from the frame memories 640 and 650 under the control of the interpolation control part 670, thereby the frame rates of the image signals received from the motion compensation part 500 can be converted based on areas classified into still areas, motion compensated areas, covered areas, and uncovered areas, classified by pixels through estimation of the motion information and the DFD using the image signals of two adjoining frames received from the motion compensation part 500. Herein, the frame memory 640 and 650 can be removed permitting the multiplexer 660 to select and transmit one of the signals received from the frame memory 610 and the interpolation part 630, directly. The interpolation control part 670 includes a comparator 671 for comparing the DFD received from the motion estimation part 600 to a preset critical value, a pixel area classification part 672 for controlling the interpolation part 630 through classifying into still areas, motion compensated areas, covered areas and uncovered areas, classified by pixels using signals received from the divider 680 and the comparator 671, and a scene change detection part 676 for detecting changes of scenes using signals received from the comparator 671 for controlling output of the multiplexer 660. The scene change detection part 676 includes a summer 673 for summing signals received from the comparator 671 in frame units, a comparator 674 for comparing the signals received from the summer 673, and a delay compensator 675 for compensating delays by storing signals received from the comparator 674 temporarily, and for controlling the output of the multiplexer 660. The interpolation part 630 includes an averaging interpolation part 631 for carrying out interpolation with the average of both frames using the image signals received from the frame memories 610 and 620, a motion compensation region interpolation part 633 for carrying out motion compansations using signals received from the frame memory 620 and the divider 680 according to the control of the pixel area classification part 672, a frame memory 634 for storing signals received from the motion compensation region interpolation part 633, and a multiplexer 632 for selection of the signals received from the frame memories 610, 620 and 634, and the averaging interpolation part 631 and for transmitting the selected signals according to the control of the pixel area classification part 633. Operation of another embodiment of the frame rate conversion part having the foregoing is to be explained hereinafter. The image signals received from the adder 502 of the motion compensation part 500 is stored into the frame memory 610 in frame units, and the image signals stored in the frame memory 610 in frame units is stored into the frame memory 620, again. Herein, the image signals stored in the frame memories 610 and 620 in frame units are for two adjoining frames ie., for frames front and rear (n+1)th and (n)th. The image signals in frame units transmitted from the frame memories 610 and 620 to the motion estimation part 600 are estimated and detected on motion information and DFD in macroblock units. The motion information transmitted from the motion estimation part 600 is,divided by 2 in the divider 680 into an average motion value between two frames, and transmitted to the motion compensation region interpolation part 634 and the pixel area classification part 672. The average motion information received from the divider 680 is used for carrying out motion compensation of the image signals received from the frame memory 620 at the motion compensation region interpolation part 633 according to the control of the pixel area classification part 672. The image signals motion compensated at the motion compensation region interpolation part 633 is, after stored in the frame memory 634,temporarily, transmitted to the multiplexer 632. The image signals stored in the frame mamories 610 and 620 are, added up at the adder 635, and divided by 2 at the divider into an average between frames. The image signals transmitted from the frame memories 610, 620 and 634 and the divider 636 of the averaging interpolation part 631 to the multiplexer 433 are selected and transmitted under the control of the pixel area classification part 672. The process for contolling the multiplexer 632 to select and transmit one of the applied image signals is to be explained hereinafter. The DFD in macroblock units received from the motion estimation part 600 is compared with a critical value preset to determine the areas as motion compensation areas at the comparator 671. And the motion information received from the motion estimation part 600 is divided by 2 at the divider 680 in order to compute the average motion information between two frames. The signals transmitted from the comparator 671 and the divider 680 to the pixel area classification part 672 are used therein for interpolation through classifying into still areas, motion compensated areas, covered areas and uncovered areas classified by pixels. That is, if the DFD in macroblock units received from the motion estimation part 600 is greater than the critical value, determining that it is an uncovered area at the pixel area classification part 672, the multiplexer 632 is controlled to select a corresponding image signal from the front frame (n)th received from the frame memory 620 and to transmit the selected corresponding image signal. And if the DFD in macroblock units transmitted from the motion estimation part 600 is smaller than or the same with the critical value, determining that it is an uncovered area, a motion compensated area, a covered area or a still area at the pixel area classification part 672 depending on the average motion information, the multiplexer 632 is controlled to select a corresponding image signal from the front frame (n)th received from the frame memory 620, a corresponding signal from the motion compensated frame received from the frame memory 633, a corresponding image signal from the rear frame (n+1)th received from the frame memory 610, and the image signals by the average value of the corresponding pixels of the front and rear frames (n)th and (n+1)th, and to transmit the selected image signals. In another words, the pixel area classification part 672 controls the the multiplexer 632 to interpolate, with the average between two frames when the corresponding pixel is determined to be a still area, through motion compensation when the corresponding pixel is determined to be a motion compensated area, using an image signal of the rear frame (n+1)th when the corresponding pixel is determined to be a covered area, and using image signal of the front frame (n)th when the corresponding pixel is determined to be an uncovered area. In this instant, if corresponding pixel is determined to be a still area at the pixel area classification part 672, the multiplexer 632 is controlled to transmit a corresponding image signal after selecting the corresponding image signal from either the front frame (n)th or the rear frame (n+1)th. The image signals received from the frame memory 610 and the multiplexer 632 are, stored temporarily in the frame memories 640 and 650 respectively to match synchronization, and selected at and transmitted from the multiplexer 660 under the control of the scene change detection part 676. The signals received from the comparator 671, summed up at the summer 673 in frame units, compared with a critical value preset to determine to be a scene change at the comparator 674, delay compensated matching synchronization at the delay compensator 675, controls the multiplexer 660 to select an output. That is, if the signal received from the summer 673 is found to be greater than the critical value as the result of comparison at the comparator 674, determining that the scene has been changed, the multiplexer 660 is controlled to select and transmit an image signal of the rear frame (n+1)th received from the frame memory 640. And if the signal received from the summer 673 is found to be smaller than or the same with the critical value as the result of comparison at the comparator 674, determining that the scene has not been changed, the multiplexer 660 is controlled to select and transmit the image signals received from the frame memories 640 and 650,alternatively. Then, the multiplexer 660 finally transmits an image signal corresponding to two times of the frame rate of the applied image signals to facilitate a display on a monitor. At present, since the frame rates or field rates of an HDTV existing worldwide are 50Hz, 60Hz and 59.94Hz, cases in which image signals with 60Hz frame rate should be converted into image signals with 59.94Hz frame rate can happen. To do this, a frame rate conversion device can be provided which further includes a frame rate conversion part 700 that can convert image signals with 60Hz frame rate received from the frame rate conversion part 400 into image signals with 59.94Hz frame rate. As shown in FIG.8, the frame rate conversion part 700 includes a FIFO memory 710 for storing and transmitting one frame of image signals of the image signals with 60Hz frame rate received from the frame rate conversion part 400, a control part 720 for controlling the FIFO memory 710 using frame synchronization signal at 60 Hz, and a 59.94Hz frame synchronization signal generation part 730 for generating frame synchronization signals at 59.94Hz using 60Hz frame synchronization signals and 59.94Hz clock. To convert image signals with 60Hz frame rate into image signals with 59.94Hz frame rate, every 1000 frames should be converted into 999 frames, of which the simplest method is to remove every 1000th incoming frame. That is, of the incoming 1000 frames, only 999 frames should be read in abandoning remained one frame. In another words, if, while 1000 frames of image signals with 60 Hz frame rate are coming in, 999 frames are read in leaving the remaining 1000th frame in the FIFO memory 710 when the FIFO memory 710 is reset again, and continues reading and writing, since only 999 frames of the incoming 1000 frames can be resulted to be read and transmitted, making the frame rate 59.94 Hz. Details of the foregoing process is to be explained hereinafter. Image signals with 60 Hz frame rate applied to the FIFO memory 710 are stored therein frame by frame, and transmitted therefrom as image signals with 59.94 Hz under the control of the control part 720. The 60Hz frame synchronization signals, applied to the control part 720, are used to control the FIFO memory 710 to transmit image signals with 59.94Hz frame ratio. That is, the control part 720, receiving 60Hz frame synchronization signals, controls the FIFO memory 710 not to transmit only the image signals corresponding to the 1000th frame of the image signals applied therein by resetting the FIFO memory 710 at 1000th frame synchronization. In another words, the incoming image signals with 60Hz frame rate is, stored in the FIFO memory 710 sucessively, and transmitted until the image signals corresponding to 999th frame is transmitted under the control of the control part 720, and when the 1000th frame synchronization signal is received, the control part 720 controls the FIFO memory 710 to reset preventing transmission of the image signals corresponding to the last 1000th frame stored in the FIFO memory 710. The FIFO memory 710 with the image signals corresponding to the 1000th frame stored therein, after reset, transmits again starting from the image signals corresponding to the first frame only to the image signals corresponding to the 999th frame. And, to match the synchronization, the 60Hz frame synchronization signal together with 59.94 Hz clock are applied to the 59.94Hz frame synchronization signal generation part 730, generating 59.94Hz frame synchronization signals. Details of the control part 720 is to be explained hereinafter, referring to FIG.9. As shown in FIG.9, the control part 720 includes a counter 721 for counting 60Hz frame synchronization signals applied thereto, and a comparator 722 for comparing the counted value received from the counter 721 to 1000 for controlling the FIFO memory 710. Herein, the counter 721 is provided with a 10 bit counter capable of counting up to 1000. The 60Hz frame synchronization signal is reset everytime the 1000th frame synchronization signal counted at the counter 721 is applied thereto. The signals transmitted from the counter 721 is compared with 1000, and the result of the comparison is transmitted as the control signals for the FIFO memory 710. That is, if the output of the counter 721 is not 1000, the comparator 722 is controlled to transmit a low level signal to the FIFO memory 710 to carry out writing and reading, and if the output of the counter 721 is 1000, the comparator 722 is controlled to transmit a high level signal to the FIFO memory 710 to reset preventing the FIFO memory 710 from carrying out reading the image signal corresponding to the 1000th frame. Thus, image signals with 60Hz frame rate can be converted into image signals with 59.94Hz frame rate. At present, since the frame rates or field rates of an HDTV existing worldwide are 50Hz, 60Hz and 59.94Hz, cases in which image signals with 59.94Hz frame ratio should be converted into image signals with 60Hz frame rate can happen. To do this, a frame rate conversion device can be provided which further includes a frame rate conversion part 800 that can convert image signals with 59.94Hz frame rate transmitted from the frame ratio conversion part 400 into image signals with 60Hz frame rate. As shown in FIG.10, the frame rate conversion part 800 includes a FIFO memory 810 for storing temporarily and transmitting one frame of image signals of the image signals with 59.94Hz frame rate received from the frame rate conversion part 400, a frame memory 820 for storing one frame of image signals received from the FIFO memory 810 and for transmitting image signals with 60Hz frame rate, a 60Hz frame synchronization signal generation part 840 for generating frame synchronization signals at 60Hz using 59.94Hz frame synchronization signals and 60Hz clock, and a control part 830 for controlling the FIFO memory 810 and the frame memory 820 using frame synchronization signals at 60Hz received from the 60Hz frame synchronization signal generation part 840. Herein, the FIFO memory 810 should be capable of storing image signals corresponding to one frame. To convert image signals with 59.94Hz frame rate into image signals with 60Hz frame rate, every 999 frames should be converted into 1000 frames, of which the simplest method is to repeat transmitting every 999th incoming frame once more. That is, after completion of reading in the incoming 999 frames, only the 999th frame should be read in once more. Details of the foregoing process is to be explained hereinafter. The image signals with 59.94Hz frame rate read and stored in the FIFO memory 810 frame by frame under the control of the control part 830, are written on the frame memory 820 again, and transmitted therefrom as image signals with 60Hz frame rate under the control of the control part 830. To match synchronization, the 59.94Hz frame synchronization signals and 60Hz clocks applied to the 60Hz frame synchronization signal generation part 840, are transmitted as 60Hz frame synchronization signals therefrom. The 60Hz frame synchronization signals transmitted from the 60Hz frame synchronization signal generation part 840 to the control part 830, are used to control the FIFO memory 810 and the frame memory 820 to transmit image signals with 60Hz frame rate. That is, the control part 830, receiving 60Hz frame synchronization signals, controls the FIFO memory 810 to read in the image signals corresponding to each frame from each synchronization and,to transmit the read in image signals. And the control part 830, after reading in the image signals corresponding to each of the 999th frame from each of the 999th frame synchronization stored in the FIFO memory 810, controls, for 1/60 second, to hold the FIFO memory 810 reading and the frame memory 820 writing, and to continue the FIFO memory 810 writing and the frame memory 820 reading. Through this operation, it is made possible to prevent the FIFO memory 810 from underflowing ane to permit the frame memory 820 to repeat reading in each of the 999th frame once more after every 999 frames. Details of the control part 830 is to be explained hereinafter, referring to FIG.11. As shown in FIG.11, the control part 830 includes a counter 831 for receiving and counting the 60Hz frame synchronization signals transmitted from the 60Hz frame synchronization signal generation part 840, and a comparator 832 for comparing the counted value received from the counter 831 to 999 for controlling the FIFO memory 810 and frame memory 820. Herein, the counter 831 is provided with a 10 bit counter capable of counting up to 1000. The 60Hz frame synchronization signal received from the 60Hz frame synchronization signal generation part 840 is reset everytime 999th frame synchronization signal counted at the counter 831 is applied thereto. The signals received from the counter 831 is compared with 999 at the comparator 832, and the result of the comparison is applied as control signals to the FIFO memory 810 and the frame memory 820. That is, if the output of the counter 831 is not 999, the signals applied from the comparator 832 controls the FIFO memory 810 and the frame memory 820 to carry out reading and writing according to the frame synchronization signals, and if the output of the counter 831 is 999, the signals applied from the comparator 832, for 1/60 second after the FIFO memory 810 is read in the 999th frame, controls to hold the FIFO memory 810 reading and the frame memory 820 writing, and to continue the FIFO memory 810 writing and the frame memory 820 reading, permitting the frame memory 820 to repeat reading the image signals corresponding to every 999th frame once more. Thus, image signals with 59.94Hz frame rate can be converted into image signals with 60Hz frame rate. As has been explained, this invention provides users with advantages of watching natural display picture having good picture quality by carrying out classification of the corresponding pixel areas and subsequent interpolation easily utilizing various informations applied from an image signal decoder.

Claims: A device for converting the frame rate of an image signal comprising: decoding means (100) for decoding an incoming compressed bit stream, and for performing a classification into motion information, macroblock type (1) information, a quantum coefficient, and control parameters, which classification is performed by carrying out an inverse multiplex operation; quantization means (200) for inverse quantizing signals outputted from the decoding means (100) according to the quantum coefficient; conversion means (300) for carrying out an inverse discrete cosine conversion of the inverse quantized signal supplied by the quantization means (200), and thereby generating a displaced frame difference (DFD) based on motion rate estimation; motion compensation means (500) for decoding image signals using the motion information supplied from the decoding means (100) and the displaced frame difference (DFD) supplied from the conversion means (300); and first frame rate conversion means (400) for classifying areas (4, 5, 6, 7) by pixels using the motion information, the macroblock type information, and the displaced frame difference (DFD), and for converting the frame rate of the decoded image signals from the motion compensation means (500), which frame rate is converted based on the classified areas (4, 5, 6, 7) by carrying out corresponding interpolations according to the result of the classification. A device as claimed in claim 1, wherein the areas classified by pixels are still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6). A device as claimed in claim 1, wherein the motion compensation means (500) includes, a motion compensator (501) for compensating motion using the motion information, variable length decoded and inverse multiplex converted, an adder (502) for adding the displaced frame difference (DFD), variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted, and signals received from and motion compensated at the motion compensator (501), and for transmitting the image signals to the frame conversion means, and a frame memory (503) for storing image signals received from the adder (502), and for transmitting the stored image signals to the motion compensator (501). A device as claimed in claim 1, wherein the frame rate conversion means (400) includes, a summer (401) for summing up the displaced frame difference (DFD), variable length decoded and inverse multiplex, inverse quantization and inverse discrete cosine converted, in macroblock units (1), a first latch (402) for temporary storing the displaced frame difference (DFD) received from the summer (401) in macroblock units (1), a second latch (403) for temporary storing the motion information, variable length decoded and inverse multiplex converted, in order to compensate for a delay at the summer (401), a third latch (404) for temporary storing the macroblock type information, and variable length decoded and inverse multiplex converted, in order to compensate for the delay at the summer (401), and a frame rate converter (405) for receiving the output signals transmitted from the first, second and third latches (402, 403, and 404) and classifying into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) by pixels, and converting the frame rate using the signals received from the motion compensation means (500). A device as claimed in claim 4, wherein the frame rate converter (405) includes, a first frame memory (410) for storing image signals received from the motion compensation means (500), a first divider (420) for dividing the motion information received from the second latch (403) by 2, an interpolation control means (440) for classifying areas into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) by pixels using signals received from the first and the third latches (402, 404) and the first divider (420), an interpolation means (430) for carrying out interpolation to complete one frame using image signals received from the first frame memory (410) and signals received from the first divider (420) under the control of the interpolation control means (440), and a first multiplexer (470) for selecting and transmitting one of the image signals received from the first frame memory (410) and the interpolation means (430) under the control of the interpolation control means (440). A device as claimed in claim 5, further including a second frame memory (450) for temporary storing the image signals received from the first frame memory (410) to match the synchronization, and a third frame memory (460) for temporary storing the image signals received from the interpolation means (430) to match the synchronization. A device as claimed in claim 5, wherein the interpolation control means (440) includes, a first comparator (441) for comparing the displaced frame difference (DFD) received from the first latch (402) to a first preset critical value, a pixel area classification means (442) for controlling the interpolation means (430) by classifying an area into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) by pixels using signals received from the first divider (420), the third latch (404) and the first comparator (441), and a scene change detection means (443) for controlling the output of the first multiplexer (470) through detecting changes of scenes using signals received from the first comparator (441). A device as claimed in claim 7, wherein the scene change detection means (443) includes, a summer (444) for summing signals received from the first comparator (441) in frame units, a second comparator (445) for comparing the signals received from the summer (444) to a second preset critical value, and a first delay compensator (446) for compensating delays by temporarily storing signals received from the second comparator (445), and for controlling the output of the first multiplexer (470). A device as claimed in claim 7, wherein the interpolation means (430) includes, a second frame memory (431) for storing the image signals received from the first frame memory (410), an averaging interpolation means (432) for carrying out an interpolation with the average of two frames using the image signals received from the first and second frame memories (410, 431), a motion compensation region interpolation means (434) for carrying out motion compensation using signals received from the first divider (420) under the control of the pixel area classification means (442), a third frame memory (435) for storing signals received from the motion compensation region interpolation means (434), and a second multiplexer (433) for selecting and transmitting signals received from the first, second and third frame memories (410, 431, 435) and the averaging interpolation means (432) under the control of the pixel area classification means (442). A device as claimed in claim 9, wherein the pixels area classification means (442) classifies the area into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) classified by pixels. A device as claimed in claim 9, wherein the averaging interpolation means (432) includes an adder (436) for adding the image signals received from the first and second frame memories (410, 431) and a second divider (437) for dividing signals received from the adder (436) by 2. A device as claimed in claim 10, wherein the pixel area classification means (442) includes, a macroblock type classifier (481) for classifying the macroblock type information received from the third latch (404) into intraframe information and motion compensation information, an inverter (485) for inverting signals received from the first comparator (441), an AND gate (486) for determining a motion compensation area by logic multiplying of the signals received from the inverter (485) and the motion compensation information received from the macroblock type classifier (481), and for transmitting the motion compensation area to the motion compensation region interpolation means (434), a memory (487) for storing the position of the corresponding pixel using signals received from the first divider (420) in response to the signal received from the AND gate (486), a second delay compensator (482) for compensating delays by storing signals received from the macroblock type classifier (481), an interpolation selection controller (483) for controlling the second multiplexer (433) in response to the signals stored in the memory (487) and the signals received from the second delay compensator (482), and a third delay compensator (484) for compensating delays by storing the signals received from the interpolation selection controller (483) and transmitting the delay compensated signals to the second multiplexer (433). A device as claimed in claim 12, wherein the interpolation selection controller (483) controls the second multiplexer (433) to interpolate with the average of both frames in case the signals received from the second delay compensator (482) shows that the corresponding pixel is a still area (4), to interpolate through motion compensation in case the signals received from the second delay compensator (482) and the memory (487) show that the corresponding pixel is a motion compensation area (5), to interpolate using the image signals of a rear frame or (n+1)th frame in case the signals received from the second delay compensator (482) and the memory (487) show that the corresponding pixel is a covered area (7), and to interpolate using the image signals of the front frame or (n)th frame in case the signals received from the second delay compensator (482) show that the corresponding pixel is an uncovered area (6). A device as claimed in claim 13, wherein the interpolation selection controller (483) controls the second multiplexer (433) to interpolate using the image signals of the front frame in case the signals received from the second delay compensator (482) show that the corresponding pixel is a still area (4). A device as claimed in claim 13, wherein the interpolation selection controller (483) controls the second multiplexer (433) to interpolate using the image signals of the rear frame in case the signals received from the second delay compensator (482) show that the corresponding pixel is a still area (4). A device as claimed in claim 1, wherein the first frame rate conversion means (400) classifies the area into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) by pixels by estimating the motion information and the displaced frame difference (DFD) using image signals of two adjoining frames received from the motion compensation means (500), and converts the frame rate of image signals received from the motion compensation means (500) according to the classified areas. A device as claimed in claim 16, wherein the areas classified by pixels are still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6). A device as claimed in claim 17, wherein the frame rate conversion means (400) includes, a first and a second frame memories (610, 620) connected in series for storing the image signals in frame units received from the motion compensator (500), a motion estimation means (600) for estimating motion information and displaced frame difference (DFD) using image signals of two adjoining frames received from the first and the second frame memories (610, 620), a first divider (680) for dividing the motion information received from the motion estimation means (600) by 2, an interpolation control means (670) for classifying areas by pixels using the motion information received from the motion estimation means (600) and the signals received from the first divider (680), an interpolation means (630) for completing one frame by carrying out interpolation using the image signals received from the first and the second frame memories (610, 620) and the signals received from the first divider (680) under the control of the interpolation control means (670), and a first multiplexer (660) for selecting and transmitting one of the image signals received from the first frame memory (610) and the interpolation means (630) under the control of the interpolation control means (670). A device as claimed in claim 18, further including a third frame memory (640) for temporary storing of the image signals received from the first frame memory (610) to match the synchronization, and a fourth frame memory (650) for temporary storing of the image signals received from the interpolation means (630) to match the synchronization. A device as claimed in claim 18, wherein the interpolation control means (670) includes, a first comparator (671) for comparing the displaced frame difference (DFD) received from the motion estimation means to a first critical value, a pixel area classification means (672) for controlling the interpolation means (630) through classifying the areas into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6), by pixels using signals received from the first divider (680) and the comparator (671), and a scene change detection means (676) for detecting changes of scenes using signals received from the first comparator (671) for controlling output of the first multiplexer. A device as claimed in claim 20, wherein the scene change detection means (676) includes, a summer (673) for summing signals received from the first comparator (671) in frame units, a second comparator (674) for comparing the signals received from the summer (673) to a second preset critical value, and a first delay compensator (675) for compensating delays by temporarily storing signals received from the second comparator (674), and for controlling the output of the first multiplexer (660). A device as claimed in claim 20, wherein the interpolation means (630) includes, an averaging interpolation means (631) for carrying out an interpolation with the average of two frames using the image signals received from the first and second frame memories (610, 620), a motion compensation region interpolation means (633) for carrying out motion compensation using signals received from the second frame memory (620) and the second divider (680) under the control of the pixel area classification means (672), a fourth frame memory (634) for storing signals received from the motion compensation region interpolation means (633), and a second multiplexer (632) for selecting and transmitting signals, received from the first, second and third frame memories (610, 620, 634) and the averaging interpolation means (631) under the control of the pixel area classification means (672). A device as claimed in claim 22, wherein the pixel area classification means (672) classifies the areas into still areas (4), motion compensation areas (5), covered areas (7) and uncovered areas (6) classified by pixels. A device as claimed in claim 22, wherein the averaging interpolation means (631) includes an adder (635) for adding the image signals received from the first and second frame memories (610, 620) and a second divider (636) for dividing signals received from the adder (635) by 2. A device as claimed in claim 23, wherein the pixel area classification means (672) controls the second multiplexer (632) to interpolate with the average of both frames in case the corresponding pixel is determined to be a still area (4), to interpolate through motion compensation in case the corresponding pixel is determined to be a motion compensation area (5), to interpolate using the image signals of a rear frame in case the corresponding pixel is determined to be a covered area (7), and to interpolate using the image signals of a front frame in case the corresponding pixel is determined to be an uncovered area (6). A device as claimed in claim 25, wherein the pixel area classification means (672) controls the second multiplexer (632) to interpolate using the image signals of the front frame in case the corresponding pixel is determined to be a still area (4) . A device as claimed in claim 25, wherein the pixel area classification means (672) controls the second multiplexer (632) to interpolate using the image signals of the rear frame in case the corresponding pixel is determined to be a still area (4). A device as claimed in claim 1, further including a second frame rate conversion means (700) for converting image signals with a 60 Hz frame rate received from the first frame rate conversion means (400) into image signals with a 59.94 Hz frame rate. A device as claimed in claim 28, wherein the second frame rate conversion means (700) includes, a FIFO memory (710) for storing and transmitting one frame of image signals of the image signals with the 60 Hz frame rate received from the first frame rate conversion means, a control means (720) for controlling the FIFO memory (710) using a frame synchronization signal at 60 Hz, and a 59.94 Hz frame synchronization signal generation means (730) for generating frame synchronization signals at 59.94 Hz using a 60 Hz frame synchronization signal and a 59.94 Hz clock. A device as claimed in claim 29, wherein the control means (720) includes, a counter (721) for counting the 60 Hz frame synchronization signals applied thereto, and a comparator (722) for comparing the counted value received from the counter (721) to 1000 for controlling the FIFO memory (710). A device as claimed in claim 30, wherein the counter (721) is a 10 bit counter. A device as claimed in claim 1, further including a second frame rate conversion means (800) for converting image signals with a 59.94 Hz frame rate received from the first frame rate conversion means (400) into image signals with a 60 Hz frame rate. A device as claimed in claim 32, wherein the second frame rate conversion means (800) includes, a FIFO memory (810) for storing temporarily and transmitting one frame of image signals of the image signals with the 59.94 Hz frame rate received from the first frame rate conversion means (400), a frame memory (820) for storing one frame of image signals received from the FIFO memory (810) and for transmitting image signals at the 60 Hz frame rate, a 60 Hz frame synchronization signal generation means (840) for generating frame synchronization signals at 60 Hz using a 59.94 Hz frame synchronization signal and a 60 Hz clock, and a control means (830) for controlling the FIFO memory (810) and the frame memory (820) using frame synchronization signals at 60 Hz received from the 60 Hz frame synchronization signal generation means (840). A device as claimed in claim 33, wherein the control means (830) includes a counter (831) for receiving and counting the 60 Hz frame synchronization signals transmitted from the 60 Hz frame synchronization signal generation means (840), and a comparator (832) for comparing the counted value received from the counter (831) to 999 for controlling the FIFO memory (810) and the frame memory (820). A device as claimed in claim 34, wherein the counter (831) is a 10 bit counter.

Inventors: LEE DONG HO, LEE, DONG HO
Applicants: LG ELECTRONICS INC, LG ELECTRONICS INC.
Application year: 1994
Main classification: H04N7
IPC codes: H04N7