Plasma display panel with reduced power consumption

Abstract: A flat display comprises an address current detecting means (3) for detecting a value of address current consumed for each frame to be displayed on the flat display, a comparator (4) for comparing the address current value detected by the address current detecting means (3) with a given reference value, and an address frequency control means (5) for controlling address frequencies related to a display frame in response to the output of the comparator (4) so as to restrict the power used for addressing purposes.

Description: The present invention relates to flat displays, for example plasma displays or electroluminescent (EL) displays. Flat displays including plasma displays and electroluminescent (EL) displays have small depths. Moreover, flat displays permit the construction of large display screens. The application range and production scale of flat displays are therefore rapidly expanding and an address current suppressing means may be desirable for use in a brightness drive utilized in such a display. In general, a flat display utilizes a change accumulated between electrodes and causes a discharge to emit light for display. For better understanding of the general principle of display, the structure and operation of, for example, a plasma display will be described briefly. A previously-considered plasma display (AC type PDP) can be a dual-electrode type that uses two electrodes for selective discharge (addressing discharge) and sustaining discharge or a triple-electrode type that uses three electrodes for addressing discharge. In a plasma display (PDP) for a color display, infrared rays resulting from discharge are used to excite phosphors formed in discharge cells. The phosphors are susceptible to the impact of ions or positive charge induced by the discharge. The above dual-electrode type has a structure that the phosphors directly hit ions. This structure may reduce the service lives of phosphors. To avoid the deterioration, the color plasma display usually employs the triple-electrode structure based on surface discharge. The triple-electrode type falls into an arrangement in which the third electrode is formed on the substrate on which first and second electrodes thereof for sustaining discharge are arranged and an arrangement in which a third electrode is formed on another substrate opposed to the one on which first and second electrodes are arranged. In the arrangement in which three electrodes are formed on the same substrate, the third electrode may be placed on or under the two electrodes for sustaining discharge. Furthermore, visible light emitted from phosphors may be transmitted or reflected by the phosphors for observation. The foregoing plasma displays of different types have the same principle. Mention will therefore be made of a flat display in which first and second electrodes for sustaining discharge are formed on a first substrate and a third electrode is formed on a second substrate opposed to the first substrate. Fig. 6 is a schematic plan view showing a configuration of a triple-electrode type plasma display (PDP). Fig. 7 is a schematic sectional view of one of discharge cells 10 formed in the plasma display shown in Fig. 6. As apparent from Figs. 6 and 7, the plasma display comprises two glass substrates 12 and 13. The first substrate 13 has first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15. The first electrodes 14 and second electrodes 15 serve as sustaining electrodes, lie in parallel with one another, and are shielded with a dielectric layer 18. A coat 21 made of magnesium oxide (MgO) is formed as a protective coat over the discharge surface that is the dielectric layer 18. On the surface of the second substrate 12 opposed to the first glass substrate 13, electrodes 16 acting as third electrodes or address electrodes are formed to intersect the sustaining electrodes 14 and 15. On the address electrodes 16, phosphors 19 each having one of red, green, and blue light-emitting characteristics are placed in discharge spaces 20 each defined by walls 17 formed on the surface of the second substrate 12 on which the address electrodes are arranged. Discharge cells 10 in the plasma display are separated from one another by partitions. In a plasma display 1 of the aforesaid example, the first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15 are lying in parallel with one another and paired. The second electrodes (Y electrodes) 15 are driven independently, while the first electrodes (X electrodes) 14 act as a common electrode and are driven by a single driver. Fig. 8 is a schematic block diagram showing peripheral circuits for driving the plasma display shown in Figs. 6 and 7. The address electrodes 16 are connected one by one to an address driver 31. During addressing discharge, the address driver 31 applies an address pulse to each address electrode. The Y electrodes 15 are connected one by one to a Y-electrode scan driver 34. The scan driver 34 is connected to a Y-electrode common driver 33. For addressing discharge, pulses are generated by the scan driver 34. For sustaining discharge, pulses are generated by the Y-electrode common driver 33, and then applied to the Y electrodes 15 via the Y-electrode scan driver 34. The X electrodes 14 are connected in common with respect to all display lines on a panel of the flat display. An X-electrode common driver 32 generates a write pulse and a sustaining pulse, and applies these pulses to the Y electrodes 15 concurrently. These drivers are controlled by a control circuit. The control circuit is controlled with a synchronizing signal and a display data signal which are fed by an external unit. As apparent from Fig. 8, the address driver 31 is connected to a display data control unit 36 incorporated in the control circuit 35. The display data control unit 36 inputs a dot clock signal CLOCK and a display data signal DATA, which are display data and fed from an external unit, and outputs data via, for example, a frame memory 37 incorporated in the display data control unit 36 according to the timing of addressing address electrodes which are to be selected for one frame. The Y-electrode scan driver 34 is connected to a scan driver control unit 39 in a panel drive control unit 38 incorporated in the control circuit 35. In response to a vertical synchronizing signal V SYNC that is a signal instructing the start of scanning one frame (or field) and fed by an external unit, and a horizontal signal H SYNC that is a signal instructing the start of one horizontal scanning period, the Y-electrode scan driver 34 is driven to select a plurality of Y electrodes 15 in the flat display 1 one by one. Thus, an image of one frame is displayed. In Fig. 8, Y-DATA denotes scan data that is supplied by the scan driver control unit 39 and used to turn on the Y-electrode scan driver bit by bit. Y-CLOCK denotes a transfer clock pulse for use in turning on the Y-electrode scan driver bit by bit. Y-STB1 denotes a timing signal for use in turning on the Y-electrode scan driver. Y-STB2 denotes a timing signal for use in turning off the Y-electrode scan driver. The X-electrode common driver 32 and Y-electrode common driver 33 in this example are connected to a common driver control unit 40 incorporated in the control circuit 35. The X electrodes 14 and Y electrodes 15 are driven all together by reversing polarities of applied voltages alternately. Thus, the aforesaid sustaining discharge is executed. In Fig. 8, an X-UD signal is supplied by the common driver control unit 40, is used to control the on and off states of the X common driver, and the X-UD signal includes voltage signals Vs and Vw. An X-DD signal supplied by the common driver control unit 40 is used to control the on and off states of the X-electrode common driver and the X-DD signal includes a GND level signal. Likewise, a Y-UD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver, and the Y-UD signal includes voltage signals Vs and Vw. A Y-DD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver and the Y-DD signal includes a GND level signal. Fig. 9 shows waveforms in a first example of a previously-considered method of driving the plasma display PDP shown in Figs. 6 and 7. Fig. 9 shows one drive cycle in a line-sequential drive and self-erasure addressing mode. In this example, at a time instant (1) during one drive cycle, the voltages of the X electrodes are held at 0V, and a voltage -Vs is applied simultaneously to the Y electrodes associated with all sub-frames constituting one frame. Thus, the waves of all the display lines corresponding to the sub-frames are reshaped in terms of phase. Since it is unknown which phase was set last for display lines corresponding to sub-frames in a previous frame, the phase of each display lines should preferably be synchronized to each other to form a new frame. That is why the operation at the time instant (1) is necessary. Next, at a time instant (2) in Fig. 9, voltage -Vs is applied to the Y electrodes associated with a display line (C) which is selected by the Y-electrode scan driver and common driver to write display data, while 0V is applied to the Y electrodes associated with the other display lines (D) except the selected display line. (A voltage Vs is a sustaining voltage.) In this example, a write voltage Vw is applied as a write pulse to the X electrodes at the same time. At this instant, a voltage exceeding a discharge start voltage Vf is applied to the discharge spaces 19. This causes a discharge to start. The selected display line has a voltage Vs + Vw, while the unselected display lines have the voltage Vw. When Vs + Vw > Vf (discharge start voltage) > Vw is established, a selected display line alone can be discharged. At the time instant (2), all the cells 10 associated with the selected line are written. A positive surface charge accumulated between the walls (referred to as "wall charge") is therefore accumulated in the protective coat (MgO coat) over the X electrodes 14 associated with the selected line (C), while a negative wall charge is accumulated in the protective coat (MgO coat) over the Y electrodes associated with the selected line. As discharge progresses, the wall charges have a polarity causing the electric fields in the discharge spaces 19 to shrink. The discharge therefore dies down and lasts only for one to several microseconds. Next, at a time instant (4) in Fig. 9, the sustaining pulse of the voltage -Vs is applied alternately to the X electrodes 14 and the Y electrodes 15 associated with the selected display line. The wall charge accumulated is added to the applied voltages. Thus, sustaining discharge is repeated in all the cells except those not to be lit (illuminated). In this example, at a time instant (3) in Fig. 9, a sustaining pulse is applied to the X electrodes in the cells 10 not to be lit. After a negative wall charge is accumulated in the MgO coat over the Y electrodes associated with the selected line, synchronously with the sustaining pulse applied first to the Y electrodes associated with the selected line, an address pulse ADP of a positive voltage Va is applied selectively to the address electrodes in the cells 10 not to be lit. Sustaining discharge occurs in all the cells associated with the selected display line. In the cells whose address electrodes are applied the address pulse ADP, especially, the sustaining discharge triggers discharge between the address electrodes and Y electrodes. Consequently, positive wall charge is accumulated excessively in the MgO coat over the Y electrodes. When the voltage Va is set to such a value that allows the produced wall charge itself to exceed the discharge start voltage, after an external voltage is removed; that is, after the X and Y electrodes are set to 0V and the address electrodes are set to ground, the voltage of the wall charge itself starts discharging. As for this discharge, since the potential difference between the X and Y electrodes is 0V, the space charge or wall charge resulting from the discharge will not accumulate in the MgO coat over the X and Y electrodes. The space charge is recombined and neutralized in the discharge spaces. This action is referred to as self-erasure discharge. Thereafter, even if the sustaining pulse -Vs is applied alternately to the X and Y electrodes, sustaining discharge will not occur but erasure is effected. As for the cells to be lit, the address pulse ADP is not applied to the address electrodes of the cells. Sustaining discharge alone occurs but self-erasure discharge does not. With a sustaining pulse applied thereafter, sustaining discharge is repeated. As mentioned above, display data is written for a selected display lien during one drive cycle. In this example, the writing is executed for each display line. Fig. 10 is a timing chart for the writing. In Fig. 10, W denotes a drive cycle for writing. S denotes a drive cycle for sustaining discharge alone and s denotes a drive cycle for sustaining discharge for a previous frame (or field). Fig. 11 shows waveforms in the second example of a previously-considered method of driving the plasma display PDP shown in Figs. 6 and 7. Fig. 11 shows one sub-frame (or sub-field) period SF in a write addressing mode of an addressing/sustaining discharge separated style. In this example, one sub-frame period SF consists of at least a reset period 61, an addressing period 62, and a sustaining discharge period 63. The reset period 61 is provided to erase data concerning the sub-frames of a previous frame immediately before displaying a new image of one frame. During the reset period 61, all the Y electrodes are de-energized to be 0V, and a write pulse of a voltage Vw is applied to the X electrodes at the same time. Thereafter, the Y electrodes are applied a voltage Vs and the X electrodes are de-energized to be 0V. Sustaining discharge then occurs in all the cells. This leads to execution of whole-screen write, whereby an erasure pulse EP is applied to the X electrodes 14 so that information recorded in all the cells 10 are erased temporarily. This is the reset period 60. In this example, during the reset period 60, first, all the Y electrodes are de-energized to 0V. At the same time, all the cells associated with all display lines are discharged; that is, the write pulse of the voltage Vw is applied to the X electrodes. The Y electrodes are then applied the voltage Vs, and the X electrodes are de-energized to have 0V at the same time. Thus, sustaining discharge is effected in all the cells. Erasure discharge occurs between the X electrodes and Y electrodes, whereby wall charge disappears (part of the wall charge is neutralized). The reset period 61 is useful in placing all the cells in the same state irrelevant of whether or not they are lit for a previous sub-frame, and is intended to hold the wall charge, which triggers address discharge, at a voltage that does not start discharge with the sustaining pulse. In this example, the reset period 61 is succeeded by the addressing period 62. During the addressing period 62, addressing discharge is effected line-sequentially so that the cells are turned on or off depending on the display data to be placed in the cells. First, a scan pulse SCP of 0V is applied to the Y electrodes. The address pulse ADP of the voltage Va is applied to the address electrodes in the cells to be subjected to sustaining discharge or to be lit. Thus, the cells to be lit are discharged for writing. This brings about minor discharge, which will not be discerned directly, between the address electrodes and selected Y electrodes. A given amount of charge is then accumulated in the cells 10. Thus, (address) writing for one display line terminates. The foregoing operation is performed for the other display lines sequentially. New display data are thus written for all the display lines. Thereafter, during the sustaining discharge period 63, the sustaining pulse of the voltage Vs is applied alternately to the Y electrodes and X electrodes. Thus, sustaining discharge is effected. An image is displayed in units of one sub-frame. In the aforesaid write addressing mode of an addressing/sustaining discharge separated style, a brightness level of a display screen is determined depending on the length of the sustaining discharge period or the number of sustaining pulses. A brightness level of a pixel in the display screen depends on the number of sustaining discharge cycles performed during the sustaining discharge period 63 for each sub-frame under the setting conditions for each sub-frame. In short, a brightness level is dependent on the length of the sustaining discharge period. In principle, the greater the number of sustaining discharge cycles performed during the sustaining discharge period 63 is, the higher the brightness becomes. Otherwise, the brightness becomes lower. For determining a brightness level, an optimal one of multiple predetermined sub-frame patterns, of which numbers of sustaining discharge cycles are different from one another due to different given weights, is selected for each sub-frame, and then sustaining discharge is executed for the sub-frame. After this operation is executed for all sub-frames of one frame, a brightness level for the frame is determined. In this example, as shown in Fig. 12, one frame is divided into eight sub-frames SF1 to SF8. The length of the sustaining discharge period 63 is different from sub-frame to sub-frame. The reset period 61 and addressing period 62 are the same in length among the sub-frames SF1 to SF8. However, the length of the sustaining discharge period 63 differs from sub-frame to sub-frame. For example, the numbers of sustaining discharge cycles for the sub-frames SF1 to SF8 are set to have a relationship of 1:2:4:8:16:32:64:128. By selecting any one or ones of the patterns shown as the sub-frames SF1 to SF8 in Fig. 12 using addresses, the numbers of sustaining discharge cycles for sub-frames in one frame can be changed appropriately. In this example, brightness can be set to any one of 256 levels. This example based on the addressing mode of an addressing/sustaining discharge separated style is utilized for the display with a large number of scanning lines (corresponding to display lines) or the full-color display with multiple brightness levels. The configuration and operation for this addressing mode are disclosed in, for example, Japanese Unexamined Patent Publication No. 4-195188 corresponding to EP-A-0 488 891. An example of actual time allocation in the aforesaid example will be described below. Assuming that screen rewriting is performed with 60 Hz, it takes 16.6 ms (1/60 Hz) to rewrite one frame. Assuming that the number of sustaining discharge cycles for one frame is 510, the number of sustaining discharge cycles for the sub-frame SF1 is 2, that for the sub-frame SF2 is 4, that for the sub-frame SF3 is 8, that for the sub-frame SF4 is 16, that for the sub-frame SF5 is 32, that for the sub-frame SF6 is 64, that for the sub-frame SF7 is 128, and that for the sub-frame SF8 is 256. Assuming that it takes 8 microseconds to complete a sustaining discharge cycle, 4.08 ms is required to complete all the sustaining discharge cycles for one frame. The remaining 12 milliseconds or so is allocated to eight addressing periods. It takes about 1.5 milliseconds to complete the addressing period for each sub-frame. Assuming that about 50 microseconds is required for the reset period preceding each addressing period, it takes 3 microseconds to complete each addressing cycle for driving a panel having 500 scanning lines. The addressing mode of an addressing/sustaining discharge separated style is currently the most effective mode for displaying images at different brightness levels, wherein a memory in an AC plasma display PDP or an electroluminescent (EL) display is utilized for effective use of time. Address current flowing through an AC plasma display PDP or electroluminescent (EL) display having the aforesaid configuration is broadly divided into address electrode-to-address electrode capacitance discharge current (hereinafter, A-A current), address write current, and address driver loss current. It is the A-A current that is most dominant in a maximum address current. The A-A current is used to charge or discharge a space having a floating capacitance between address electrodes in a panel. Referring to Fig. 6, two address electrodes A1 and A2 are adjacent to each other and can therefore be modeled as a capacitance. A square wave having a voltage expressed below is regarded as a signal to be fed to the address electrode A1: V(t) = VmF (wt) where, F(wt) denotes a frequency factor of 0 or 1. Assume that the address electrode A2 has a voltage 0 and the capacitance between the address electrodes A1 and A2 is C12, the equation below is established. I(t) = C12Vm F'(wt) The A-A current is therefore determined by the A-A capacitance, A-A potential difference, and address frequency. The C12 and Vm values are usually unchanged. The peak address current therefore depends directly on the address frequency. When cells are arranged in a zigzag pattern, the A-A current becomes maximum. To ensure this A-A current, a large power supply is required. The is disadvantageous in terms of cost and installation. However, since the zigzag pattern is seldom used, a large power supply is not always required. In a previously-considered plasma display PDP which cannot control address current actively, a large power circuit is a must. It is desirable to provide a flat display in which address current is controlled automatically to reduce a power consumption, and a power circuit is small-sized to improve efficiency and economy. This objective is achieved by the flat display of the invention as defined in claim 1. At least two substrates having electrodes on the surfaces thereof are arranged closely so that the electrodes intersect and face mutually. A plurality of intersections formed between the electrodes construct cells associated with pixels. Each cell has a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell. A flat display having the above structure comprises an address current detecting means for detecting a value of address current consumed for each frame to be displayed on the flat display, a comparator for comparing the address current value detected by the address current detecting means with a given reference value, and an address frequency control circuit for controlling an address frequency or a frequency of a pulse generated by each of address electrodes associated with a display frame. In an embodiment of the present invention, one frame displayed on the flat display is temporally segmented into a plurality of sub-frames corresponding to scanning lines. Each of the sub-frames is composed of an addressing period during which at least a plurality of cells are selected and written display data and a sustaining discharge period during which the cells that are written the display data are discharged so as to emit light for a given period of time. The length of the sustaining discharge period in each sub-frame is varied depending on a sub-frame address signal that is a weighting signal, whereby a brightness level of one frame to be displayed on the flat display is changed. A flat display embodying the present invention adopts the aforesaid technological configuration. Even when a previously-considered flat display such as a plasma display PDP or an electroluminescent (EL) display is employed, address current flowing through a plurality of address electrodes may be controlled actively by controlling the frequencies of data pulses applied to the address electrodes. Even a small-sized power circuit can drive the flat display successfully. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram showing an example of a configuration of a flat display embodying the present invention. Fig. 2 is a block diagram showing a configuration of an example of an address frequency control means employed for a flat display embodying the present invention. Fig. 3 is a truth table of control data handled by the address frequency control means shown in Fig. 2. Figs. 4A and 4B are flowcharts showing a procedure of address frequency control employed in an embodiment of the present invention. Fig. 5 is a truth table of control data handled by another address frequency control means in an embodiment of the present invention. Fig. 6 is a block diagram showing an example of a previously-considered flat display. Fig. 7 is a block diagram showing an example of a structure of a cell in the flat display shown in Fig.6. Fig. 8 is a block diagram showing a circuitry for driving the flat display shown in Fig. 6. Fig. 9 shows waveforms to explain a drive cycle in the flat display of Fig. 6. Fig. 10 is a timing chart for writing and sustaining discharge in the flat display of Fig. 6. Fig. 11 shows waveforms to explain another drive cycle in the flat display of Fig. 6. Fig. 12 shows an example of sub-frame patterns employed in the flat display of Fig. 6. Fig. 1 is an explanatory diagram showing the principle of a flat display embodying the present invention. In Fig. 1, at least two substrates 12 and 13 having electrodes on the surfaces thereof are arranged closely so that the electrodes intersect and face mutually. Phosphors 19 are interposed between the substrates 12 and 13. A plurality of intersections formed between the electrodes construct cells 10. Each of the cells 10 has a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell and also has an ability of discharge and light emission. In a flat display having this structure, one frame to be displayed on the flat display is segmented temporally into a plurality of sub-frames SF corresponding to scanning lines. Each of the sub-frames SF is composed of an addressing period 62 during which at least a plurality of cells 10 are selected and written with display data, and a sustaining discharge period 63 during which the cells 10 that are written with display data are discharged so as to emit light for a given period of time. A brightness level of one frame to be displayed on the flat display is changed by appropriately weighting the length of the sustaining discharge period 63 of each sub-frame SF. The flat display comprises an address current detecting means 3 for detecting a value of address current consumed for each frame to be displayed on the flat display, a comparator 4 for comparing the address current value detected by the address current detecting means 3 with a given reference value, and an address frequency control means 5 for controlling the address frequencies related to a display frame in response to the output of the comparator 4. The flat display 1 embodying the present invention may be a plasma display or an electroluminescent display. Embodiments of the present invention can be applied to any flat displays that hold charge to exert a capability of a memory. In the flat display 1 embodying the present invention, as shown in Fig. 1, the address current detecting means 3 for detecting an address current Ia is interposed between a power circuit 2 and an address driver 31. The address current detecting means 3 is not limited to any specific circuitry but may be a known current detecting means having a capacity for current detection. Fig. 2 shows an example of a configuration of an example of the address current detecting means 3 usable in an embodiment of the present invention. According to this example, the address current detecting means 3 is connected to a line linking the power supply 2 and address driver 31. A resistor R4 is connected in the line. The emitters of bipolar transistors TR1 and TR2 are connected across the resistor 4. The bases of the transistors TR1 and TR2 are connected in common. The collector of the transistor TR2 is grounded via a resistor R3 and is connected to the base of transistor TR2. The collector of the transistor TR1 is grounded via a resistor R1 and is connected to one end of a capacitor C1 via a resistor R2. The junction between the transistor TR1 and capacitor C1 is connected to the comparator R4 to be described later. An address current value to be detected by the address current detecting means 3 in an embodiment of the present invention is a value of address current consumed for each frame, or more preferably, an average of address current values detected relative to a plurality of consecutive frames. Unfortunately, in this technology, when a higher brightness level is set for display of images, the images become brighter and the screens become easy-to-see but the number of data pulses to be applied to each address electrode increases. In other words, the address current flowing through each address electrode increases as the frequency of a data pulse becomes higher. In an embodiment of the present invention, which attempts to solve the aforesaid problems, a flat display is such that when a given image is to be displayed and address current flows through address electrodes is detected, and any value of the address current exceeds a predetermined given value, the frequency of display data to be applied to the address electrode is lowered, and that thus the address current is held at a certain value or less. In an embodiment of the present invention, when a detected address current exceeds a certain value, any of sustaining discharge cycles within a sustaining discharge period of each sub-frame is not executed. In other words, sustaining discharge is not performed at a predetermined time instant at which sustaining discharge is supposed to be done. Alternatively, even if sustaining discharge is performed, information is output so that the period of an on/off pulse for pixel display data generated by a given address electrode is seemingly shortened. The address frequency to be controlled in the present invention is a frequency of a pulse generated at each of the plurality of address electrodes. In an embodiment of the present invention, address current flowing through the address electrodes may be detected and controlled individually. In practice, the sum of the address current flowing through the whole of the panel 30 of the flat display 1 is detected for more efficient control. It is therefore preferred that address current values be detected in units of one frame to be displayed on the flat display or in units of a plurality of frames, and then averaged for use in the aforesaid control. Details of a brightness-level control method, for a display screen in a flat display embodying the present invention, that have been disclosed previously will be omitted from the following description. In the brightness-level control, the lengths of sustaining discharge periods in display lines or a plurality of sub-frame which constitute one frame and are associated with Y electrodes 15; that is, the numbers of sustaining discharge cycles in the sustaining discharge periods are set by selecting one pattern or a plurality of patterns from the eight-stepped patterns shown as sub-frames SF1 to SF8 in Fig. 12. The addresses of the sub-frames for which the sustaining discharge frequencies are set, for example, RDI0 to RDI7, are appended to the display data (DATA) of the frame. As previously described, one of the eight-stepped sub-frame patterns SF1 to SF8 or a combination thereof is used to enable the display of brightness varying in 256 levels. In an embodiment of the present invention, the address frequency control means 5 preferably comprises a plurality of gate means 42, which are connected in parallel with one another, each having an input port 40 for inputting a sub-frame address signal or any of RDI0 to RDI7 that determines which cells in a sub-frame be selected, and an input port 41 for inputting a control signal or any of R0 to R7 provided in response to the output signal of the comparator 4. By controlling the plurality of gate means 42, the output of a given sub-frame address signal is controlled so as to reduce the relevant address frequencies. The comparator 4 in an embodiment of the present invention is, for example, as shown in Fig. 2, composed of an A/D converter 43 to which the output of the address current detecting means 3 is fed, and a reference data output means 45 that stores a reference current value used relative to an address current value and that is an appropriate storage means. The comparator 4 further comprises a comparing circuit 46 that compares the data provided by the A/D converter 43 with the data provided by the reference data output means 45, and that when the data sent from the A/D converter 43 represents a higher value than the reference data, outputs a given control signal, and an arithmetic logic unit (CPU) 44 for controlling the actions of these means. The comparator 4 embodying the present invention outputs, as shown in Fig. 2, three independent control signals SFEN0, SFEN1, and SFEN2 to the address frequency control means 5 which will be described later. The control signals SFEN0, SFEN1, and SFEN2 have their logical states varied depending on a detected address current value. Fig. 3 shows an example of logical states of output signals SFEN0, SFEN1, and SFEN2 of the comparator. The address frequency control means 5 according to the present invention comprises, as shown in Fig. 2, the plurality of gate means 42, which are connected in parallel with one another, each having the input port 40 for inputting a sub-frame address signal or any of RDI0 to RDI7 that determines which cells in a sub-frame be selected, and the input port 41 for inputting a control signal or any of R0 to R7 that are output signals of a control signal generating means 50 which is incorporated in the address frequency control means 5 and outputs given control signals. By controlling the plurality of gate means 42, the output of a given sub-frame address signal is generated so as to change the relevant address frequencies. The control signal generating means 50 in an embodiment of the present invention may have any logical circuitry as long as it can output signals having the voltage levels shown in Fig. 3 through output terminals R0 to R7 in response to the output signals SFEN0, SFEN1, and SFEN2 of the comparator 4. Truth values listed in Fig. 3 determine the logical states of signals provided by the control signal generating means 50. That is to say, the logical states of the output signals SFEN0, SFEN1, and SFEN2 of the comparator 4 are varied depending on the detected value of address current. The logical states of the output signals sent from the output terminals of the control signal generating means 50 are determined according to a combination of the logical states of the output signals SFEN0, SFEN1, and SFEN2. In this example, it is assumed that the address frequency control means 5 comprises AND gate circuits 42, that the sub-frame address signal RDI7 represents an address indicating a sub-frame for which a large brightness level or a high sustaining discharge frequency is specified, and that the sub-frame address signal RDI0 represents an address indicating a sub-frame for which a small brightness level or a low sustaining discharge frequency is specified. In this case, when a detected address current value is small, the output signals SFEN0, SFEN1, and SFEN2 of the comparator 4 are low. The output signals sent from the output terminals of the control signal generating means 50 are therefore driven high. When a detected address current value is small as mentioned above, since all the AND gate circuits 42 are open, any of the sub-frame address signals RDI0 to RDI7 is input. The address signal is then output by the control means 5 via a gate circuit 47, and fed to the common driver control unit in the panel drive control unit 38. Sustaining discharge is then executed. When a detected address current value is slightly larger, the output signal SFEN0 of the comparator 4 is driven high, while the output signals SFEN1 and SFEN2 are held low. In the foregoing state, as apparent from the truth table of Fig. 3, the output signal sent from the output terminal R0 of the control signal generating means 50 goes low. The other output signals provided via the output terminals R1 to R7 stay high. Even when the sub-frame address signal RDI0 is input, the sub-frame address signal RDI0 is not output by the control means 5 but masked. This results in an address frequency reduced by the masked signal portion. In other words, since the detected address current value is slightly larger, any of the sub-frame address signals RDI7 to RDI0 is masked to compensate for the increase in current. This results in lower address frequencies. In an embodiment of the present invention, an output signal sent from the output terminal R0 of the control signal generating means 50 is masked, because the output signal is a sub-frame address signal indicating a sub-frame for which a small brightness level is specified. That is to say, erasing such a sub-frame address signal hardly affects the change in brightness of a whole frame. Likewise, when a detected address current has a large value, if the output signals SFEN0 and SFEN1 of the comparator 4 go high but the other output signal SFEN2 stays low, as apparent from the truth table of Fig. 3, the output signals sent from the output terminals R0 to R2 of the control signal generating means 50 are driven low but the other output signals sent from the output terminals R3 to R7 thereof are held high. In the foregoing state, even when the sub-frame address signals RDI0 to RDI2 are input as data, the sub-frame address signals RDI0 to RDI2 are not output by the control means 5 but masked. This results in address frequencies reduced by those of the masked signals. An example of a procedure for executing brightness-level control embodying the present invention will be described in conjunction with the flowcharts of Figs. 4(A) and 4(B). In a flat display embodying the present invention, image displaying starts at a step (1). At a step (2), initialization is executed to set initial data that are given conditions. The image displaying then actually starts. Control is then passed to a step (3). When an image of one frame is displayed, an interrupt enable signal for enabling execution of a subroutine of address current detection is output in synchronization with a V SYNC signal. Control is then passed to a step (4). The subroutine then starts. At a step (5), a detected address current value Ia is compared with a reference current value Ia REF . If the Ia value is larger than the Ia REF value, control is passed to a step (6). The aforesaid control is then executed. Control is then passed to a step (7), and returned to the step (4). If it is found at the step (5) that the Ia value is not larger than the Ia REF value, control is passed directly to the step (7) and then returned to the step (4). In this example, when a color display is to be implemented, the aforesaid control means 5 is provided for each of three colors; red, blue, and green. The aforesaid operations are then executed for each color. In another example of the address frequency control means 5, the AND gate circuits 42 shown in Fig. 3 may be replaced with, for example, OR gate circuits. In this case, a truth table shown in Fig. 5 is adopted to control signals sent from the output terminals of the control signal generating means 50. In this example, unlike the aforesaid example, even when any of the sub-frame address signals RDI0 to RDI7 is not input, required ones of the sub-frame address signals RDI0 to RDI7 are output according to the detected address current value Ia. Thus, the address frequencies are controlled. In this case, a truth table shown in Fig. 12 is adopted. All the sub-frame address signals indicating selected sub-frames go high. As described so far, in a embodiment of the present invention, address frequencies are automatically controlled to cope with an increase in address current. Thus, address power can be limited to a reference value or less. This permits a small-sized power supply. The aforesaid control method adopted for the flat display of an embodiment of the present invention is applicable to an addressing mode of either a conventional line-sequential self-erasure type or a conventional batch write/erase type.

Claims: A flat display, in which at least two substrates each having electrodes on the surface thereof are arranged closely so that said electrodes intersect and face mutually, a plurality of intersections formed between said electrodes construct cells, each serving as a pixel, and each of said cells has a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell, said flat display comprising: an address current detecting means for detecting a value of an address current consumed for each frame to be displayed on said flat display; a comparator for comparing the address current value detected by said address current detecting means with a given reference value; and an address frequency control means for controlling an address frequency or a frequency of a pulse generated by each of address electrodes, which are associated with a display frame, in response to the output of said comparator. A flat display according to claim 1, wherein said flat display is a plasma display. A flat display according to claim 1, wherein said flat display is an electroluminescent display. A flat display according to claim 1, wherein said address current value detected by said address current detecting means is an average of values of address current consumed for each frame. A flat display according to claim 1, wherein said address frequency control means includes a plurality of gate means, which are connected in parallel with one another, each having an input port for inputting a sub-frame address signal that determines which cells in an associated sub-frame should be selected, and an input port for inputting a control signal provided in response to the output of said comparator, and wherein by controlling said plurality of gate means, the output of a given sub-frame address signal is controlled so as to reduce said address frequencies. A flat display according to claim 1, wherein said address frequency control means includes a plurality of gate means, which are connected in parallel with one another, each having an input port for inputting a sub-frame address signal that determines which cells in an associated sub-frame should be selected, and an input port for inputting a control signal provided in response to the output of said comparator, and wherein by controlling said plurality of gate means, the output of a given sub-frame address signal is generated so as to change said address frequencies. A flat display according to any of claims 1 to 6, wherein a single frame to be displayed on said flat display is segmented temporally into a plurality of sub-frames corresponding to scanning lines, wherein each said sub-frame is composed of an addressing period during which at least a plurality of cells are selected and written with display data, and a sustaining discharge period during which said cells that are written with said display data are discharged so as to emit light for a given period of time, and wherein the lengths of the sustaining periods in the sub-frames of a frame are weighted appropriately so as to change brightness levels of the frame to be displayed on said flat display. A flat display according to claim 1, wherein said address frequency control means controls the address frequency by masking at least one of sub-frame address signals selected by a sub-frame address signal masking means in response to a variation of said address current detected by said address current detecting means. A flat display according to claim 7, wherein the generation of said sub-frame address signal, in an optional sub-frame among a plurality of sub-frames, is stopped in an addressing period, in response to the variation of said address current. A flat display according to claim 9, wherein the stop of the generation of the sub-frame address signal is predominantly effected from a sub-frame having sustaining discharge period the duration of which being relatively short.

Inventors: FUJISAKI TAKASHI, OTSUKA AKIRA, TAJIMA MASAYA, TOMIO SIGETOSHI, UEDA TOSHIO, FUJISAKI, TAKASHI, OTSUKA, AKIRA, TAJIMA, MASAYA, TOMIO, SIGETOSHI, UEDA, TOSHIO, FUJISAKI, TAKASHI, C/O FUJITSU LIMITED, OTSUKA, AKIRA, C/O FUJITSU LIMITED, TAJIMA, MASAYA, C/O FUJITSU LIMITED, TOMIO, SIGETOSHI, C/O FUJITSU LIMITED, UEDA, TOSHIO, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1994
Main classification: G09G3
IPC codes: H04N5, G09G3