Space diversity receiver for a digital communications system

Abstract: A diversity receiver system includes reception circuits (11,21) connected to antennas (10,20) and for converting frequency of received signal to a base band signal; a diversity branch comparison circuit (30) for directing a base band signal to be used by comparing an intermediate frequency supplied through the reception circuit; a base band delay detection circuit (40) for outputting a detection signal which is generated by a delay detection of the base band signal directed by the diversity branch comparison circuit; and a DPLL circuit (46) for generating an internal clock by using the detection signal supplied from the base band delay detection circuit, thereby securing a stable reception and providing a diversity receiver system having a small circuit scale.

Description: BACKGROUND OF THE INVENTION The present invention relates to a diversity receiver system used in a digital communication, and more particularly, to a diversity receiver system capable of having a stable reception performance in spite of a condition of receiving a signal and capable of suppressing a power consumption. There are conventionally well known diversity receiver systems each having a plurality of reception antennas and which are used in a land mobile radiotelephone system, a mobile communication system, a portable telephone set system and a satellite communication system or the like. In such a receiver system, each of reception antennas receives a signal relative to the same data so as to output only demodulation data selected from a plurality of the same data which are received by respective antennas. There will be described later a conventional diversity receiver system, for example, a diversity receiver for a portable telephone set system having two reception antennas. Document JP-A-05 030084 discloses a prior art diversity receiver. FIG. 1 schematically shows a constitution of such a conventional diversity reception system. In FIG. 1, reception antennas 10 and 20 respectively receive a radio signal transmitted from a base station. The signal received by the reception antenna 10 is supplied to a reception circuit 11 in which a frequency of the signal is converted into a base band signal, thereby outputting an in-phase component I 1 and an quadrature (orthogonal) component Q 1 to a delayed detection circuit 12, respectively. The delayed detection circuit 12 performs a delayed detection with respect to the in-phase component I 1 and the quadrature component Q 1 both supplied, respectively, so as to output reception clock component extraction signals Id 1 and Qd 1 which are generated by the wave detection. A digital phase-locked loop (hereafter abbreviated to a DPPL) circuit 13 receives the reception clock component extraction signals Id 1 and Qd 1 to generate an internal clock. The internal clock is delivered to be used for judging a positive and negative of the reception clock component extraction signals Id 1 and Qd 1 . In the same manner of this, a signal which is received by the reception antenna 20 is also converted in its frequency into a base band signal in a reception circuit 21, and a delayed detection circuit 22 performs a delayed detection with respect to an in-phase component I 2 and an quadrature component Q 2 included in the base band signal to generate reception clock component extraction signal Id 2 and Qd 2 which are used for generating an internal clock in a DPLL circuit 23. The internal clock is delivered to judging circuits 24 and 25 to be used for judging a positive and negative of the reception clock component extraction signals Id 2 and Qd 2 . A diversity branch comparison circuit 30 compares an electric field strength of the reception signals which are respectively taken in the reception circuits 11 and 21 through the reception antennas 10 and 20 to determine the reception signal which is used as demodulation data so as to output a signal (a selective signal) representing a determined result. A selector 31 selects any pair of signals Id 1 , Qd 1 and Id 2 , Qd 2 which are respectively outputted from the judging circuits 14, 15 and 24, 25 in correspondence with the selective signal supplied from the diversity branch comparison circuit 30. A parallel/serial conversion circuit 32 converts the signals Id* and Qd* (namely, Id 1 * and Qd 1 * or Id 2 * and Qd 2 *) supplied from the selector 31 into a serial signal to output demodulation data. In this manner, the conventional diversity receiver has a plurality of demodulation systems comprising delayed detection circuits and the like corresponding to each of the reception antennas, for respectively demodulating the reception signal received by each reception antenna. According to this, a generation of the internal clock used in each demodulation system is respectively performed in any of the DPLL circuits 13 and 23 which are different from each other. In the DPLL circuit of the diversity receiver, since the electric field strength of the reception signal of the reception antenna is very weak, it happens that the internal clock is not generated. In this case, if the electric field of the reception signal of the other reception antenna is strong, the diversity branch comparison circuit 30 selects the stronger reception signal. In such a case, when the field strength of the reception signal of the demodulation system in which th internal clock has not been generated yet sharply increases more than the field strength of the reception signal of the demodulation system in which the internal clock has already been generated, the diversity branch comparison circuit 30 changes the selection of the reception signal at once. However, even though it is possible to generate the internal clock by increasing the electric field strength of the reception signal, it is necessary to take a predetermined time period until a phase synchronous of the internal clock generated by the DPLL circuit is concentrated. Accordingly, before the phase synchronous by the DPLL circuit is concentrated, it is happened that the reception signal of the demodulation system according to the DPLL circuit is issued as the demodulation data. According to such a reason, in the conventional diversity receiver system shown in FIG. 1, it is impossible to secure a stable reception in the case where the electric field strength of the reception signal by the reception antenna sharply changes. Furthermore, since it is necessary to provide the respective delayed detection circuit and DPLL circuit for each reception antenna, the circuit scale becomes large not only to obstruct a miniaturization and a low price of the portable telephone set but also to become a cause of the increase of consumed power. SUMMARY OF THE INVENTION In view of the above-mentioned faults of the prior art, an object of the present invention is to provide a diversity receiver system capable of securing the stable reception and miniaturizing a circuit scale even though a receiving condition of the reception antenna sharply changes. According to the present invention there is provided a diversity receiver system for digital communication according to claim 1. A diversity receiver system according to the present invention only employs the one of the modulation signals, as directed by the comparison circuit, for generating the internal clock output from the selector. The digital phase-locked loop circuit generates the internal clock from the thus selected modulation signal. Therefore, immediately after the selection in the comparison circuit is changed, it is possible to use the internal clock corresponding to the modulation signal which is selected before the change. Accordingly, since the present invention does not use the internal clock before the phase synchronous is concentrated, it is possible to secure the stable reception even though the electric field strength of the signal received by the reception antenna sharply changes. Furthermore, since it is possible to miniaturize the digital phase-locked loop circuit and the like, the circuit scale can be reduced. As described above, since the diversity receiver system according to the present invention uses the internal clock before the change-over of the reception signal immediately after the reception signal to be used changes over, even when the receiving condition sharply changes, it is possible to secure the stable reception. Furthermore, since the digital phase-locked loop circuit and the like are commonly used one another, it is possible to miniaturize the circuit scale. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a block diagram schematically showing a constitution of the conventional diversity receiver system; FIG. 2 is a block diagram schematically showing a constitution of a diversity receiver system according to a first embodiment of the present invention; FIG. 3 is a block diagram schematically showing an internal constitution of a base band delayed detection circuit shown in FIG. 2; and FIG. 4 is a block diagram schematically showing a constitution of a diversity receiver system according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS There will be described in detail a diversity receiver system according to preferred embodiments of the present invention by way of an example of a portable telephone set in reference with the attached drawings. FIG. 2 is the block diagram schematically showing the constitution of a diversity receiver system according to a first embodiment. Furthermore, FIG. 3 is the block diagram schematically showing the internal constitution of a base band delayed detection circuit 40 shown in FIG. 2. In FIG. 2, reception antennas 10 and 20 respectively receive a radio signal transmitted form a base station in the same manner of the conventional reception antennas (refer to FIG. 1). Reception circuits 11 and 21 change frequencies of the reception signals which are received by the reception antennas 10 and 20, respectively, into base band signals. The reception circuit 11 outputs an in-phase component I 1 and a quadrature component Q 1 of a base band signal, while the reception circuit 21 outputs an in-phase component I 2 and a quadrature component Q 2 of the base band signal. In the first embodiment, it is supposed that each of the component signals I 1 , Q 1 , I 2 and Q 2 is an 8-bit signal. Furthermore, these reception circuits 11 and 21 respectively output an intermediate frequency (IF) signal to a diversity branch comparison circuit 30. The diversity branch comparison circuit 30 (corresponding to a "comparison circuit" of the present invention) compares the electric field strength of both reception signals by using the intermediate frequency signals which are supplied from the reception circuits 11 and 21, respectively, to determine the base band signal which will be converted into the demodulation data, thereby outputting a selective signal as a signal showing the determined result. The comparison may be performed by using the base band signal in the place of the intermediate frequency signal. A base band delayed detection circuit 40 (corresponding to a "detection circuit" of the present invention) receives all of the components I 1 , Q 1 and I 2 , Q 2 of each of the above base band signals and the selective signal SEL, The detection circuit 40 only performs the delayed detection of the base band signal component selected by the selective signal SEL, but does not perform the delayed detection of the base band signal component which is not selected by the selective signal SEL. In the base band delayed detection circuit 40, delay circuits 41, 42, 43 and 44 (corresponding to "delay means" of the present invention) inputs each of the base band signal components I 1 , Q 1 , I 2 and Q 2 according to a timing of a sample clock signal S CK so as to generate delay signals DI 1 , DQ 1 , DI 2 and DQ 2 which are delayed from each of signals with one symbol time. A selector 45 (corresponding to "selection means" of the present invention) inputs all of the base band signal components I 1 , Q 1 , I 2 and Q 2 , the delay signals DI 1 , DQ 1 , DI 2 and DQ 2 of respective components and the selective signal SEL, respectively. The selector 45 selects and outputs the base band signal components and respective delay signals which are selected by the selective signal SEL. For example, when the selective signal of the comparison circuit 30 directs the base band signal outputted from the reception circuit 11, the selector 45 selects the component I 1 from the base band signal in-phase components I 1 and I 2 , and outputs the component I 1 as the in-phase component signal I, and selects the component Q 1 from the base band signal quadrature components Q 1 and Q 2 , and outputs the component Q 1 as the quadrature component signal Q. Furthermore, the selector 45 selects the delay signal DI 1 from the delay signals DI 1 and DI 2 , and outputs the signal DI as the delay signal DI, and selects the delay signal DQ 1 from the delay signals DQ 1 and DQ 2 , and outputs the signal DQ 1 as the delay signal DQ. A complex multiplier circuit 50 (corresponding to "calculation means" of the present invention) receives the output signals I, Q, DI and DQ from the selector 45 to perform the delayed detecting calculation. In the complex multiplier circuit 50, a multiplier 51 multiplies the signal I by the signal DI, a multiplier 52 multiplies the signal Q by the signal DQ, a multiplier 53 multiplies the signal DI by the signal Q, and the multiplier 54 multiplies the signal I by the signal DQ, so as to output calculated results of 16-bit signals, respectively. An adder 55 adds the output values of the multipliers 51 and 52 so as to output a detection signal Id of the in-phase component. Furthermore, a subtracter 56 subtracts the output values of the multipliers 53 and 54 with each other so as to output a detection signal Qd of the quadrature component. A digital phase-locked loop (DPLL) circuit 46 inputs the output signals Id and Qd of the base band delayed detection circuit 40 to generate an internal clock. the internal clock is delivered to judging circuits 47 and 48 and used for judging the positive and negative of the signals Id and Qd. The parallel/serial conversion circuit 32 converts parallel signals Id* and Qd* of the 16-bit signals as the judged result into serial signals to output the demodulation data. In such a manner, the first embodiment has only one of the DPLL circuit which only generates the internal clock by using the signal selectively detected by the base band delayed detection circuit 40. Namely, the selection of the reception signals is performed before the internal clock is generated without the selection of the demodulation data which are outputted after each of the reception signals is demodulated in the manner of the conventional diversity receiver system shown in FIG. 1. Accordingly, in the diversity receiver system with reference to the first embodiment of the present invention, immediately after the selection is switched over by the change of the electric field strength of the reception signal, the system uses the internal clock itself which is based on the reception signal before switching over. Therefore, since there is not a possibility that the internal clock before the concentration of the phase synchronous is used, it is possible to secure the stable reception even in the case where there is a sharp change of the electric field strength of the reception signal through the reception antenna. Furthermore, since all of the antennas can be commonly used for the same DPLL circuit 46 and complex multiplier circuit 50, it is possible to miniaturize the circuit scale. When the positive and negative are judged by the internal clock generated by using an output of the delayed detection performed after the diversity selection, if the delaying difference at the reception time between the reception signals of one reception antenna and the other reception antenna is sharply large, there is a general possibility that jitters of the clock become large at switching over the diversity branch. Therefore, when the delaying difference is large as above, it is necessary to provide a waveform equalizing circuit for compensating a multipath, which is a circuit for decreasing the jitters. However, a delayed detection method used in the first embodiment is a method that is used when it is no problem that there is a delaying difference between the reception signals from respective reception antenna. Accordingly, since this method has a premise that such the problem does not occur, it is unnecessary to use the waveform equalizing circuit for compensating the multipath. Even though the first embodiment of the present invention is described above, the present invention is not limited in the first embodiment. For example, even though the selector 45 is provided before the complex multiplier circuit 50 for selecting the base band signal, the selection of the base band signal may be performed after a calculation of the delayed detection by the complex multiplier circuit 50. Namely, since a commonness of the DPLL circuit can achieve an effect of the present invention for stabilizing the reception signal, the selection of the reception signal may be performed at least before the DPLL circuit. However, since the common (or shared) circuits are desired to be more in order to miniaturize the circuit scale, it is suitable that the selector 45 is provided before the complex multiplier circuit 50 for commonly using the complex multiplier circuit. Furthermore, even though the first embodiment as an example is applied to the portable telephone set having two reception antennas, the present invention may be applied to the telephone system having a plurality of reception antennas more than three, and to other apparatus and devices, thereby naturally obtaining the same effect. FIG. 4 shows a diversity reception system according to a second embodiment of the present invention for describing in more detail. In FIG. 4, a plurality of antennas 10A, 10B, ..., 10M and 10N are connected to a plurality of reception circuits 11A, 11B, ..., 11M and 11N, respectively. The plurality of the reception circuits 11A, 11B, ..., 11M and 11N respectively output intermediate frequency signals to a diversity branch comparison circuit 300 which compares an electric field strength of a plurality of the intermediate frequency signals inputted thereto so as to determine a base band signal which will be converted into demodulated data, thereby outputting a selecting signal SEL showing a determined result to a selector 450. On the other hand, the reception circuits 11A, 11B, ..., 11M and 11N respectively output in-phase components I 1 , I 2 , ..., I M and I N and quadrature components Q 1 , Q 2 , ..., Q M and Q N to the selector 450, and respectively supply.the in-phase components I 1 , I 2 , ..., I M and I N to delay circuits 4A1, 4B1, ..., 4M1 and 4N1, so as to obtain delayed signal DI 1 , DI 2 , ..., DI M , DI N and supply the quadrature components Q 1 , Q 2 , ..., Q M and Q N to delay circuits 4A2, 4B2, ..., 4M2 and 4N2 so as to obtain delayed signal DQ 1 , DQ 2 , ..., DQ M and DQ N . The selector 450 outputs each of the signal components I, DI, Q and DQ of anyone selected from the reception circuits 11A, 11B, ..., 11M and 11N which determined by the selecting signal SEL to a complex multiplier 500 as calculation means, respectively. The complex multiplier 500 has a configuration as the same as the complex multiplier 50 of the first embodiment shown in FIG. 3, which outputs the detection signal Id of the in-phase component and the detection signal Qd of the quadrature component by the calculation in a plurality of stages. The detection signals Id and Qd of the respective components outputted from the complex multiplier 500, are supplied to a digital phase-locked loop circuit 46 and judging circuits 47 and 48, respectively, thereby outputting parallel signals Id* and Qd* of 16 bits to the parallel/serial conversion circuit 32 which supplies a demodulation data to the output terminal 33 of the diversity receiver system. As described above, in the diversity receiver system according to the second embodiment having a large number of antennas more than three, it is possible to provide one DPLL circuit 46 and a pair of the judging circuit 47 and 48 for the in-phase and quadrature components, respectively, in the manner of the diversity receiver system according to the first embodiment having two antennas. Analogizing from the system of the first embodiment corresponding to the conventional system in the case of two antennas, as clearly understood by the system of the second embodiment having a large number of the antennas as shown in FIG. 4, the conventional system having a large number of antennas needs a large number of DPLL corresponding to the number of the antennas. Accordingly, by the system of the second embodiment, the specific effect is expected in that a common utilization of the DPLL circuit and the like causes the circuit scale to be miniaturized less than the system according to the first embodiment.

Claims: A diversity receiver system for digital communication, having a plurality of antennas (10, 20; 10A, 10B, 10M, 10N), for outputting demodulation data of a received signal selected from reception signals of the plurality of antennas, the diversity receiver system comprising: a plurality of reception circuits (11, 21; 11A, 11B, 11M, 11N) each of which is connected to corresponding one of said plurality of antennas and is for outputting a modulation signal which is generated from the received signal supplied through said antenna; comparison means (30; 300) for determining which one of said modulation signals, which are each outputted from a respective one of said plurality of reception circuits, is to be used as a selected modulation signal; a selector (45; 450) receiving the plurality of the modulation signals output from the reception circuits, the selector outputting one of the modulation signals as said selected modulation signal in accordance with the directions of said comparison means; and a digital phase locked loop (46) coupled to the selector (45; 450), the digital phase locked loop using said signal output from said selector to generate an internal clock, and wherein the internal clock generated by the phase locked loop (46) is used in demodulating the signal output from the selector, and a demodulation of the signal output from the selector is performed by demodulating only the reception signal of the respective one of the plurality of reception circuits outputting the selected modulation signal. The diversity receiver system according to Claim 1, wherein said selector comprises part of a base band delayed detection circuit (40; 400) including, delay means (41-44; 4A1, 4A2, 4B1, 4B2, 4M1, 4M2, 4N1, 4N2) for delaying said modulation signals respectively supplied from each of said plurality of the reception circuits to generate and output a delayed modulation signal; the selector (45; 450) receiving said modulation signals and said delayed modulation signals and outputting said modulation signals and said delayed modulation signals in accordance with the directions of said comparison means; and including calculation means (50; 500) for performing a delayed detection calculation by using said one modulation signal and said one delayed modulation signal which are supplied from said selector. The diversity receiver system according to claim 2, wherein said calculation means comoprises a complex multiplier including a first multiplier (51) for multiplying an in-phase component (I) with a delayed in-phase component (DI) of said selected modulation signal a second multiplier (52) for multiplying a quadrature component (Q) with a delayed quadrature component (DQ) of said selected modulation signal; a third multiplier (53) for multiplying said quadrature component (Q) with said delayed in-phase component (DI) a fourth multiplier (54) for multiplying said in-phase component (I) with said delayed quadrature component (DQ); an adder (55) for adding an output of said first multiplier (51) with an output of said second multiplier (52) to output an in-phase component detection signal (Id); and a subtracter (56) for performing a subtraction between an output of said third multiplier (53) and an output of said fourth multiplier (54) to output a quadrature component detection signal (Qd). The diversity receiver system according to claim 1, wherein said plurality of antennas and said plurality of said reception circuits for supplying said reception signals to said comparison means (30) and said selector (45), are comprised of a first antenna (10) and a first reception circuit (11), and a second antenna (20) and a second reception circuit (21). The diversity receiver system according to claim 1, wherein said plurality of antennas and said plurality of said reception circuits for supplying said reception signals to said comparison means and said selector, are comprised of first through N-th antenna or antennas (10A, 10B, 10M, 10N) and first through N-th reception circuit or circuits (11A, 11B, 11M, 11N) corresponding to said first through N-th antenna or antennas, and wherein N is more than three.

Inventors: OGURA KOJI, SEKI KEIKO, OGURA, KOJI, SEKI, KEIKO, OGURA, KOJI, 302, KUREARE MOTOSUMIYOSHI, 1931
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1994
Main classification: H04B7
IPC codes: H04B7