High-to-low-voltage signal level shift circuit

Abstract: A level shift circuit (1) for a voltage input signal (S,SN) presenting at least first and a second high-voltage levels, the circuit comprising two parallel branches (2,3) each formed by a current modulator (6,7,9; 14,15,17) and signal converters (8,16). The current modulators are supplied with two signals (S,SN) in phase opposition to each other, and generate current signals (I7,I15) whose value depend on the level of the respective input signal (S,SN); the signal converters (8,16) convert the current signals (I7,I15) into ground-related voltage signals (V1,V2). The signal converters (8,16) together form a single-ended differential circuit (20), the output (21) of which therefore presents a low-voltage digital signal which can be processed by normal digital circuits and is unaffected by noise or variations in supply voltage.

Description: The present invention relates to a high-to-low-voltage signal level shift circuit, in particular a circuit for low voltage shifting a digital signal which may assume two different values close to a high supply voltage, as defined in the preamble of claim 1. Modern electronic circuits sometimes require that a high-voltage-related signal (even as high as 500 V) be converted to a low voltage compatible with normal digital circuits (typically operating between 0 and 5 V). Such is the case, for example, with low-side or high-side power MOS transistor drivers which supply digital diagnostic signals (e.g. relative to short-circuiting, correct open/close operation of the power MOS transistor, etc.) which may selectively assume two different high-voltage-related levels (e.g. 500 and 495 V), and the level of which must therefore be shifted and related to ground for the signals to be processed by normal digital circuits, e.g. microprocessor systems. In some cases, the need arises of a shift circuit including active, low breakdown voltage components, as, for example, when the fabrication technology available does not permit the use or formation of bipolar P-channel PNP or MOS transistors capable of withstanding the high input voltage. A level shift circuit of the considered type is disclosed in EP-A-0 485 291, wherein the shift circuit includes an ECL logic circuit including a current switch circuit having a pair of input emitter-coupled transistors (differential pair stage) receiving complementary input signals of ECL logic level, respectively, and a pair of output transistors having the base connected to a corresponding collector of the input transistors; a current control circuit including a current mirror circuit having a pair of transistors coupled to a corresponding output end of the output transistors of the ECL logic circuit; and a switch circuit operatively coupled between the output transistors of the ECL logic circuit and the two transistors of the current control circuit and responding to a control signal for supplying a current or breaking thereof from the output transistors of the ECL logic circuit to the two transistors of the current control circuit. JP-A-60 004331 discloses another level shift circuit substantially corresponding to the one disclosed in EP-A-0 485 291. EP-A-0 096 349 discloses a further level shift circuit including a first and a second input emitter-coupled transistors (differential pair stage) of one conductivity type receiving an input reference voltage and a input voltage respectively, the second transistor collector being connected to a first DC power source terminal; a first constant current source connected between the emitters of the two input transistors and a second DC power source terminal; a third and a fourth base-coupled transistors (current mirror circuit) of another conductivity type having their emitters connected to the first DC power source terminal, the third transistor collector and base being connected to the first transistor collector and the fourth transistor collector being connected to a second constant current source connected to the first DC power source terminal. JP-A-3 135 220 discloses a level shift circuit comprising a voltage modulating means formed by a first and a second resistors connected to each other in series and by a signal controlled switch element having a control terminal supplied with the input signal and arranged in parallel to the first resistor; the switch element is controlled by the input signal so as to connect the first resistor in series with the second resistor or to bypass it. The voltage modulating means is supplied by a constant current source arranged in series therewith so as to generate two different voltage drops according to the value of the input signal. The output of the voltage modulating means is connected to a differential circuit for generating the output voltage. It is an object of the present invention to provide a voltage shift circuit capable of operating even at the aforementioned high voltages, and supplying at the output a ground-related signal coding the same information as the high-voltage-related signal at the input. According to the present invention, there is provided a high-to-low-voltage signal level shift circuit, as claimed in Claim 1. A number of preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a first embodiment of the circuit according to the present invention; Figure 2 shows a second embodiment of the circuit according to the present invention; Figure 3 shows a circuit that lacks the current mirror of the present invention; Figure 4 shows a third embodiment applied to a half-bridge power MOS transistor driver. Number 1 in Figure 1 indicates a shift circuit comprising a first and second branch 2, 3 parallel connected between a supply line 4 at a high voltage V H (e.g. 500 V) and ground. Branch 2 comprises a first and second resistor 6, 7, and a first transistor 8, here an N-channel MOS type, connected to one another in series. A first controlled switch 9 is provided parallel to first resistor 6 (connected to supply line 4), and receives a supply-related digital signal S supplied to a terminal 10. Similarly, branch 3 comprises a third and fourth resistor 14, 15, and a second transistor 16, again an NMOS type, also connected to one another in series. A second controlled switch 17 is provided parallel to third resistor 14 (connected to supply line 4), and is supplied with a digital signal SN in phase opposition to signal S and supplied to a terminal 18. Signal SN is also supply-related. For example, when S assumes a value of 500 V, SN assumes a maximum value of 495 V, and vice versa. Transistor 8 is diode connected, i.e. presents the drain terminal (connected to resistor 7) connected to the gate terminal. The source terminals of transistors 8 and 16 are grounded, and the gate terminals are connected to each other to form a current mirror circuit 20. The drain terminal of transistor 16 is connected to fourth resistor 15, and forms an output node 21 of circuit 1. Switches 9, 17 are formed in this case by PMOS transistors 23, 24, with the source terminals connected to supply line 4, the drain terminals connected to the intermediate nodes between resistors 6, 7 and 14, 15 respectively, and the gate terminals connected respectively to terminals 10 and 18. In circuit 1, S and SN are the high-voltage digital signals to be shifted to low voltage, while at the same time maintaining the digital information coded by them. If I7 is the current through resistor 7; I15 the current through resistor 15; I8 the current through transistor 8; and I16 the current through transistor 16: I7 = I8 = (µCox)/2 (W/L) (V GS - V T ) 2 where µ is the permeability coefficient; Cox the capacitance of the oxide layer; (W/L) the width/length ratio; V GS the gate-source voltage and V T the threshold voltage of transistor 8. If transistor 16 is the same as transistor 8 (same technology and W/L ratio): I8 = I16 Resistors 6, 7, 14, 15 are so sized that their resistances R6, R7, R14, R15 conform with the following equation: R6 + R7 = R14 + R15 In this case, in the balanced condition with switches 9 and 17 open, if V1 and V2 are the voltages with respect to ground of the drain terminals of transistors 8 and 16, respectively, it results V1 = V2 , and I7 = I15 . If voltage V H is much higher than the source-gate voltage drop V GS of transistor 8, current I8 may also be given by the following equation: I8 = I7 = V H /(R6 + R7) Controlling switches 9, 17 by means of phase-opposed signals S and SN, in a first operating mode (S high, SN low), switch 9 is open and switch 17 closed; and in a second operating mode (S low, SN high), switch 9 is closed and switch 17 open. More specifically, when switch 9 is open and switch 17 closed, resistor 14 is bypassed, so that: V2 = V H - R15 * I15 In this case, current I7 is given by equation (1). By appropriately sizing resistors 6, 7, 14, 15 (e.g. so that ratio R6/R7 = R14/R15 = 1/100 ), in the first operating mode, current I15 presents a value close to but higher than the balanced value given by (1); and, since I8 = I16, the output current I O of circuit 1, given by: I O = I15 - I16 = I15 - I7 is therefore positive. Conversely, in the second operating mode with switch 9 closed and switch 17 open, resistor 6 is bypassed, so that: V2 = V H - (R14 + R15) * I15 and: I7 = I8 = V H /R7 Consequently, in the second operating mode, and by virtue of the sizing of resistors 6, 7, 14, 15, current I15 is slightly less than the balanced current, so that I O is negative. By means of appropriate sizing, it is also possible, in the second operating mode wherein (4) applies, to obtain: V2 < (V GS - V T ) so that transistor 16 operates in the linear region. In which case: V2 = Ron * I16 = Ron * I8 where Ron is the equivalent resistance of transistor 16 in the linear region. The circuit may therefore be operated so that voltage V2 assumes two widely differing values, i.e. two ground-related digital values, in the first and second operating modes, thus permitting signal V2 to be used directly by normal digital circuits. In other words, the shift circuit according to the present invention provides for shifting the high-voltage signal S or SN by means of an element (controlled switch 9 or 17 and resistors 6, 7 or 14, 15) which modulates a current so that it presents two different values, depending on the digital value of the high-voltage signal, and may thus be converted to a voltage compatible with normal digital circuits. The Figure 1 circuit also presents a differential circuit (current mirror 20) for obtaining a differential current value (equal to the difference between the modulated value and a reference value generated by branch 2) so that the circuit is unaffected by variations or noise in the signal, e.g. for obtaining comparable output voltages even in the event of variations in supply voltage V H . PMOS transistors 23, 24 may be low-voltage types. In fact, by appropriately sizing resistors 6, 7, 14, 15, the drain-source voltage drop of transistors 23, 24 may be made less than the breakdown voltage (BVdss); and, similarly, the drain-source voltage drop of transistors 8, 16 may be such as not to exceed the breakdown voltage; thus enabling circuit 1 to be formed using only low-voltage components, which, in addition to enabling implementation of the shift circuit even when high-voltage elements cannot be employed, also provides for considerable space saving. Circuit 30 in Figure 2 is the same as the Figure 1 circuit, with the exception of current mirror circuit 20 which, in this case, comprises two bipolar NPN transistors 31, 32. More specifically, transistor 31 forms part of branch 2, and presents the collector terminal connected to second resistor 7, to its own base terminal, and to the base terminal of transistor 32 which in turn presents the collector terminal connected to output node 21 and to fourth resistor 15. The emitter terminals of both transistors are grounded. The rest of circuit 30 is exactly the same as circuit 1 and therefore requires no further description. In circuit 30, the ratio between reference current I31 (in branch 2) and current I32 in transistor 32 is determined by the emitter area ratio of transistors 31, 32. Also, current I31 is given by the equation: I31 = (V H - V BE )/(R6 + R7) where V BE is the base-emitter voltage drop of transistor 31; and R6, R7 have the same significance as indicated above. More specifically, if V BE << V H , it may be disregarded, and current I31 is given by the equation: I31 = V H /(R6 + R7). For the rest, equations (2) and (4) indicated above apply. Circuit 35 in Figure 3 is similar to circuits 1 and 30, with the exception of the differential element. In this case, mirror 20 is replaced by a comparator 36, the inputs of which are connected to a fifth and sixth resistor 37, 38 in place of transistors 8, 16 and 31, 32. More specifically, in Figure 3, fifth resistor 37 is located in series with resistors 6, 7; and the terminal of resistor 37 connected to resistor 7, and defining node 39, is connected to the noninverting input of comparator 36. Sixth resistor 38 is located in series with resistors 14, 15; and the terminal of resistor 38 connected to resistor 15, and defining node 40, is connected to the inverting input of comparator 36, the output 41 of which defines the output of circuit 35. In circuit 35, current I15 in branch 3 depends solely on the value of resistors 14, 15 and 38, and obviously differs according to whether switch 17 is open or closed (high or low signal SN). Current I15 is compared with the current I7 (reference current) in branch 2 by comparator 36, the output 41 of which therefore presents a ground-related digital signal, the value of which depends on the digital value of (supply-related) signal SN. The Figure 4 embodiment is similar to that of Figure 1, but more complete and applied to a half-bridge power MOS driver. More specifically, in circuit 1' in Figure 4, a first high-voltage DMOS transistor 45 is interposed between resistor 7 and the drain terminal of transistor 8; a second high-voltage DMOS transistor 46 is interposed between the drain terminal of transistor 16 and resistor 15; and DMOS transistors 45, 46 present the gate terminals connected to each other and to an input terminal 47 supplied with a digital signal EN for turning the DMOS transistors on or off and so enabling or disabling circuit 1'. DMOS transistors 45, 46 therefore provide for limiting consumption of circuit 1' when the shifted digital information at output 21 is not required; and must be in the form of high-voltage components in that, when the circuit is turned off, the terminals connected respectively to resistors 7 and 15 present a high impedance and may assume values equal to the supply voltage (V S in the Figure 4 example). In the Figure 4 embodiment, the gate terminals of transistors 23, 24 forming switches 9, 17 (terminals 10, 18) are connected to two outputs of a drive and diagnostic stage 50 controlling the upper transistor 51 of a half-bridge stage 52 also including a lower transistor 53 which, alternatively, may be replaced by a load. More specifically, transistor 51 is an N-channel power transistor with the drain terminal connected to supply line 54 at voltage V HV , the gate terminal connected to the control output 55 of stage 50, and the source terminal connected to a source line 56 to which are connected both stage 50 and the drain terminal of lower transistor 53. Lower transistor 53 is also an N-channel power transistor, and presents a grounded source terminal, and a gate terminal 57 supplied with a drive signal S1 generated by a drive stage (not shown) separate from stage 50. Drive and diagnostic stage 50 also presents an input connected to a terminal 60 supplied with a clock signal CK for driving MOS transistor 51, and is connected to a high-voltage supply line 61 to which shift circuit 1' is also connected. A bootstrap capacitor 62 is located between the source terminal of upper transistor 51 and supply line 61; and a diode 63, with its cathode connected to line 61, is interposed between line 61 and a terminal 64 supplied with supply voltage V S . In known manner, drive stage 50 in the Figure 4 circuit generates at terminal 55 a drive signal oscillating between V S and V S + V HV , depending on the level of clock signal CK; and, again in known manner, diagnostic tests half-bridge stage 52 to determine correct operation of upper transistor 51, any short-circuiting to ground of line 56 (source terminal of transistor 51), etc., and generates at the output a high-voltage-related digital signal. More specifically, in the example shown, stage 50 generates the two phase-opposed signals S and SN supplied to terminals 10 and 18, the level of which therefore codes correct operation or a defect of half-bridge stage 52. Circuit 1' thus provides for shifting signals S and SN, as described in detail above, for obtaining information usable, for example, by a microprocessor system. The advantages of the circuit according to the present invention will be clear from the foregoing description. Clearly, changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention as defined in the Claims.

Claims: A level shift circuit (1; 1'; 30) for a voltage input signal (S, SN) presenting at least a first and a second level for coding information, said first and second levels being comprised in a region close to a first reference value (V H ), the difference between said first and second levels being much lower than said first reference value; said circuit comprising a first and a second branch (2, 3) parallel to each other; said first branch forming a reference branch (2) including current source means (6, 7, 9) and reference converting means (8; 31); said current source means comprising reference curent modulating means (6, 7, 9); said second branch (3) comprising signal modulating means (14, 15, 17) and signal converting means (16; 32) arranged in series to each other and connected to each other at a circuit output node (21); said reference and signal convening means (8, 16; 31, 32) forming a current mirror circuit (20); said reference current and signal modulating means (6, 7, 9, 14, 15, 17) being supplied with said input signal (S) and an inverted input signal (SN) in phase opposition to said input signal (S) and generating current signals (I7, I15) having non-zero first and second values related to said first and second levels of said input signal; said current mirror circuit (16; 32) being supplied with said current signals and generating at said output node a voltage output signal (V2) presenting at least a third and a fourth level; said third and fourth levels being arranged in a region close to a second reference value much lower than said first reference value. A circuit as claimed in Claim 1, characterized in that said signal modulating means (14, 15, 17) comprise a signal voltage divider (14, 15) connected between a first reference potential line (4) at said first reference value, and said circuit output node (21); said signal voltage divider comprising at least a first and a second electric component (14, 15) connected to each other in series and connected respectively to said first potential line and said circuit output node (21); said signal modulating means also comprising a signal controlled switch element (17) having a control terminal (18) supplied with said inverted input signal (SN) and being arranged in parallel to said first electric component (14). A circuit as claimed in Claim 2, characterized in that said current mirror circuit (20) performs as a single-ended differential circuit. A circuit as claimed in Claim 3, characterized in that said reference current modulating means includes a reference voltage divider (6, 7) and a reference controlled switch element (9); said reference switch element presenting a control terminal (10) supplied with said input signal (S). A circuit as claimed in Claim 4, characterized in that said switch elements (9, 17) each comprise a MOS transistor (23, 24). A circuit as claimed in Claim 5, characterized in that said MOS transistor (23, 24) is a P-channel type, and presents the source terminal connected to said first reference potential line (4). A circuit as claimed in one of the foregoing Claims from 4 to 6, characterized in that said signal and reference voltage dividers comprise resistive elements (6, 7, 14, 15). A circuit as claimed in any one of the foregoing Claims, characterized in that said current mirror circuit (20) comprises NMOS transistors (8, 16). A circuit as claimed in any one of the foregoing Claims, characterized in that said current mirror circuit (20) comprises bipolar transistors (31, 32). A circuit as claimed in any one of the foregoing Claims, characterized in that said input signal (S, SN) is a digital signal generated by a drive and diagnostic circuit (50) for a power transistor (51).

Inventors: MENNITI PIETRO, NOVELLI ALDO, MENNITI, PIETRO, NOVELLI, ALDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H03K19
IPC codes: H03K19