Three-terminal insulated-gate power electronic device with a variable-slope saturated output characteristic depending in a discontinuous way on the output current

Abstract: A three-terminal insulated-gate power electronic device comprises a first, bipolar power transistor (T2) and a second, insulated-gate transistor (T1) forming a darlington pair, the bipolar power transistor (T2) having a first electrode (C2), a second electrode (E2) and a control electrode (B2) respectively connected to a first electrode (D1) of the insulated-gate transistor (T1) and to a first external terminal (C) of the three-terminal device, to a second external terminal (E) of the three-terminal device, and to one second electrode (S11) of the insulated-gate transistor (T1); the three-terminal device comprises switching means (T3) connected between the control electrode (B2) and the second electrode (E2) of the bipolar power transistor (T2), and control circuit means (H;T4) connected to another second electrode (S12) of the insulated-gate transistor (T1) and controlling the swicthing means (T3) to switch them from a highly-conducting condition for low values of a current (I) flowing through the first (C) and second (E) external terminals, to a non-conducting condition for high values of the current (I) flowing through the first (C) and second (E) external terminals.

Description: The present invention relates to a three-terminal insulated-gate power electronic device with a variable-slope saturated output characteristic depending in a discontinuous way on the output current. Modern lamp ballast circuits make use of Power MOS transistors, which combine fast switching performances to driving easiness. In such circuits, the required value for the Power MOS transistor "on" resistance (Ron) in saturation condition is about 1.2 ohm. Since in steady-state operating conditions the current flowing through the Power MOS transistor is in the range of 200-400 mA, the power dissipated on the Power MOS transistor is not of concern; the problem arises during the circuit start-up, when currents of the order of 5 A are necessary: in this phase the power dissipation becomes significant, as well as the voltage drop across the power MOS transistor, which can reach 6 V. This problem is related to the linearity of the output current-voltage characteristic of the Power MOS transistor, thereby the output resistance is substantially costant and indipendent from the output current. A power electronic device is also well-known comprising a MOSFET designed for high voltages (e.g. 650 V) and a bipolar power transistor, connected in darlington configuration, with the MOSFET source and drain electrodes connected respectively to the bipolar transistor collector and base electrodes; such a device, called "Insulated Gate Darlington" (IGD), exhibits a saturation output resistance which, for high collector currents, is much lower than that of a MOS field effect transistor, so that even when currents of some Amperes flow, the power dissipation and the voltage drop across the power device are kept low; for low collector currents however the IGD output resistance is higher than that of a MOS field effect transistor, thus leading to excessive power dissipation during the steady state operation. A possible solution, described for example in FR-A-2 471 702, provides for the connection of a low value resistor (e.g. 1 ohm) in parallel to the base-emitter junction of the power bipolar transistor of the IGD: in this way, the saturated output characteristic of the overall device is MOSFET-type for low output currents, and bipolar-type for high output currents. The output resistance in the MOSFET-type region of the output characteristic is given by the sum of the MOSFET on resistance plus 1 ohm; if the ballast circuit is designed for working with a resistance value of 1.2 ohm, the MOSFET on resistance must be 0.2 ohm: such a low value is not common, and not practical to achieve, in high-voltage MOSFETs. On the other hand, the resistance value of the base-emitter resistor cannot be significantly reduced, since this would result in a too high current flowing through the MOSFET when the power bipolar transistor is on (such current is in fact given by V BE /R, where V BE is the voltage across the base-emitter junction of the power bipolar transistor in saturation, typically 650 mV, and R is the resistance value of the base-emitter resistor); a too high current flowing through the MOSFET is again responsible for a too high voltage drop across it, and therefore for an excessive power dissipation. In view of the state of the prior art described, the object of the present invention is to provide a three-terminal power electronic device which does not causes excessive power dissipation neither for low output currents nor for high output currents; particularly, the three-terminal device shall be suitable to be used in ballast circuits, without being affected by the abovementioned drawbacks. According to the present invention, such object is attained by means of a three-terminal insulated-gate power electronic device as defined in Claim 1. Thanks to the present invention, it is possible to realize a three-terminal power electronic device with an output resistance which for low currents is dominated by the on resistance of the insulated-gate transistor, while for high currents is dominated by the output resistance of the bipolar power device. These and other features of the present invention will be made more evident by the following detailed description of two embodiments, illustrated as non-limiting examples in the annexed drawings, wherein: Figure 1 is a schematic circuit diagram of a lamp ballast circuit making use of two three-terminal devices according to the present invention; Figure 2 is a circuit diagram of a first embodiment of a three-terminal device according to the present invention; Figure 3 shows an output curren-voltage characteristic curve for the device of Figure 2; Figure 4 is a circuit diagram of a second, practical embodiment of the three-terminal device according to the present invention. As shown in Figure 1, and as known to anyone skilled in the art, a ballast circuit for driving a lamp L comprises two three-terminal power electronic devices 1 having each two power terminals C and E and a driving terminal G; a first one of the two three-terminal devices 1 has one power terminal C connected to a power supply line V+ and the other power terminal E connected to one end 3 of a primary winding 2 of a transformer, in series with the lamp L; the second three-terminal device 1 has one power terminal C also connected to the end 3 of the primary winding 2, and the other power terminal E connected to a ground line GND. The first three-terminal device 1 has the driving terminal G connected, through a first secondary winding 2' of the transformer, to the end 3 of the primary winding 2, while the second three-terminal device 1 has the driving terminal G connected, through a second secondary winding 2'', to the ground line GND. The ballast circuit is also provided with a starter circuit (not shown). The circuit thus obtained is self-oscillating, i.e. once the power supply line V+ has been powered, a sinusoidal current starts flowing through the lamp L, and the three-terminal devices 1 alternatively connect the end 3 of the primary winding 2 of the transformer to the power supply line V+ and to the ground line GND. As shown in Figure 2, a three-terminal electronic device 1 according to the present invention comprises a high-voltage MOS field effect transistor T1, a low-voltage MOS field effect transistor T3, and a bipolar power transistor T2; the high-voltage MOS transistor T1 is composed, in a per-se known way, by a plurality of identical elementary source cells, and has a drain electrode D1 connected to a collector electrode C2 of the bipolar power transistor T2 and to an external collector terminal C; the high-voltage MOS transistor T1 has a first source electrode S11, to which a first subset of said plurality of elementary source cells is connected, which is connected to a base electrode B2 of the bipolar power transistor T2 and to a drain electrode D3 of the low-voltage MOS transistor T3. A source electrode S3 of the low-voltage MOS transistor T3 and an emitter electrode E2 of the bipolar power transistor T2 are commonly connected to an external emitter terminal E. The high-voltage MOS transistor T1 has a second source electrode S12, to which a second subset of the plurality of elementary source cells is connected, which is connected to a first, inverting input of a comparator H whose second, non-inverting input is connected to a reference voltage supply VREF; the output of the comparator H is connected to a gate electrode G3 of the low-voltage MOS transistor T3. A gate electrode of the high-voltage MOS transistor T1 is connected to an external gate terminal G. A diode D is back-connected between the external gate terminal G and the base electrode E2 of the bipolar power transistor T2. Supposing that the three-terminal device 1 just described is used in the ballast circuit of Figure 1, when the voltage applied to the external gate terminal G is positive and sufficient to drive T1 into saturation (let's assume such voltage to be 10 V), T1 and T3 are on, and they drain a current I from the external collector terminal C; since T3 is a low-voltage MOS transistor, its on resistance is negligible with respect to that of T1, which is instead a high-voltage MOS transistor: for this reason, the voltage drop across T3 is negligibile, and the voltage drop across T1, i.e. the voltage between its drain electrode D1 and its first source electrode S11, is almost equal to the voltage V CE applied across the external collector and emitter terminals C and E; since no significant current is drained by the comparator H inputs, the voltage on the second source electrode S12 of T1 is almost equal to the voltage on the drain electrode D1: that is, the voltage on the second source electrode S12 of T1 substantially follow the voltage on the external collector terminal C. The current I starts flowing in a sinusoidal way. In this phase the output resistance of the three-terminal device 1 is dominated by the on resistance of the MOS transistor T1. When the voltage drop across T1 and T3, i.e. V CE , exceeds the value V of the reference voltage generated by VREF, the comparator H switches and turns T3 off, so that the voltage on the first source electrode S11 of T1 is pulled toward the voltage on the collector terminal C. If the reference voltage supply VREF is designed to generate a reference voltage V equal or greater to the turn-on base-emitter voltage V BEON of T2 (typically 650 mV), T1 can drive the base electrode B2 of T2 to turn it on. From now on, the three-terminal device works as an IGD, and its working point trips into a low-resistance region, dominated by the output resistance of T2. When the current I flowing into the collector terminal C of the three-terminal device starts decreasing, so does the voltage V CE . When V CE falls below the voltage value V, the comparator H switches and turns T3 on which, in turn, having as already told a much lower on resistance than T1, pulls the base voltage of T2 toward the voltage on the emitter terminal E, and thus turns T2 off. The output characteristic of the three-terminal device is again dominated by the on resistance of T1. The presence of the diode D increases the switching speed of the three-terminal device, since it helps to turn T2 off when the voltage applied to the gate terminal G with respect to the emitter terminal E goes negative. The output current-voltage characteristic of the three-terminal device of Figure 2 is shown in Figure 3: it is possible to see that for V CE values below the reference voltage V, i.e. for low currents, the three-terminal device shows an output resistance higher than that shown for V CE values above V, i.e. for high currents; such resistance is however lower than that shown by a common IGD (shown in dash-and-dot line in figure 3). With respect to the IGD with base-emitter resistor device according to the prior art, the three-terminal device according to the present invention exhibits a much lower voltage drop across it for low currents; furthermore, the bipolar power transistor T2 is better driven, since after T3 has been turned off, the whole drain current of T1 flows into the base of T2, instead being partitioned between the base of the bipolar power transistor and the base-emitter resistor. Figure 4 shows another, practical embodiment of the three-terminal device according to the invention; the comparator H and the voltage reference VREF have been replaced by an NPN bipolar transistor T4 having a base-electrode B4 connected to the second source electrode S12 of T1, and an emitter electrode E4 connected to the external emitter electrode E. A collector electrode C4 of T4 is connected to the gate electrode G3 of T3 and, through a bias resistor R1, to the external gate terminal G. In this embodiment, when a positive voltage is applied to the external gate terminal G of the device, and when the voltage applied to the external collector terminal C exceeds the base-emitter turn-on voltage V BEON of the transistor B4 (approximatively 650 mV), T4 turns on and turns T3 off. In fact, as long as the voltage V CE is lower than V BEON , no current is supplied by the second source electrode S12 of T1, and the voltage on S12 is equal to the voltage on C. When the voltage V CE equals V BEON , T4 is turned on. As in the previous embodiment, T1 can now drive the base electrode B2 of T2 to turn it on, and the working point trips into the bipolar-type, low-resistance region of Figure 3. The three-terminal device according to both the embodiments of the present invention can be realized both with discrete components, and preferably as a monolithic device integrated on a single silicon chip, utilizing any known manifacturing process adopted for the fabrication of the IGD device.

Claims: A three-terminal insulated-gate power electronic device comprising a first, bipolar power transistor (T2) and a second, high-voltage MOS transistor (T1) forming a darlington pair, the bipolar power transistor (T2) having a first electrode (C2), a second electrode (E2) and a control electrode (82) respectively connected to a first electrode (D1) of the high-voltage MOS transistor (T1) and to a first external terminal (C) of the three-terminal device, to a second external terminal (E) of the three-terminal device, and to one second electrode (S11) of the high-voltage MOS transistor (T1), characterized in that it comprises switching means (T3) connected between the control electrode (B2) and the second electrode (E2) of the bipolar power transistor (T2), said switching means having negligible resistance with respect to the high-voltage MOS transistor, and control circuit means (H;T4) connected to another second electrode (S12) of the high-voltage MOS transistor (T1) and controlling said switching means (T3) to switch them from a highly-conducting condition for low values of a current (I) flowing through the first (C) and second (E) external terminals, to a non-conducting condition for high values of the current (I) flowing through the first (C) and second (E) external terminals, so that the bipolar power transistor is turned off for low values of said current. The three terminal device according to claim 1, characterized in that said control circuit means (H;T4) causes said switching means (T3) to switch from the highly-conducting to the non-conducting conditions when a voltage applied between the first (C) and the second (E) external terminals equals a prescribed value (V;V BEON ). The three-terminal device according to claim 2, characterized in that said prescribed value (V;V BEON ) is at least equal to the base-emitter turn-on voltage (V BEON ) of a bipolar transistor. The three-terminal device according to claim 1, characterized in that said control circuit means (H;T4) comprise a comparator (H) with a first input connected to said another second electrode (S12) of the hight voltage MOS transistor (T1), a second input supplied with a reference threshold voltage (V), and an output controlling said switching means (T3). The three-terminal device according to claim 4, characterized in that said reference threshold voltage (V) is equal to the base-emitter turn-on voltage (V BEON ) of a bipolar transistor. The three-terminal device according to claim 1, characterized in that said control circuit means (H;T4) comprise a third transistor (T4) having a first electrode (C4) controlling said switching means (T3), a second electrode connected to the second external terminal (E), and a control electrode connected to said another second electrode (S12) of the hight-voltage MOS transistor (T1). The three-terminal device according to claim 4, characterised in that said switching means comprise a fourth transistor (T3) having a control electrode (G3) connected to the output of said comparator (H). The three-terminal device according to claim 6, characterized in that said switching means comprise a fourth transistor (T3) having a control electrode (G3) connected to the first electrode (C4) of the third transistor (T4). The three-terminal device according to anyone of the preceding claim, characterized in that the bipolar power transistor (T2) is of the NPN type. The three-terminal device according to anyone of the preceding claims, characterized in that the high-voltage MOS transistor (T1) is a high-voltage N-channel MOSFET. The three-terminal device according to claim 10, characterized in that the high-voltage MOS transistor (T1) comprises a plurality of elementary transistor cells, a first subset of said plurality of cells being connected to said one second electrode (S11) and a second subset of said plurality of cells being connected to said another second electrode (S12) of the high-voltage MOS transistor. The three-terminal device according to claim 7, characterized in that said fourth transistor (T3) is a low-voltage N-channel MOSFET. The three-terminal device according to claim 6, characterized in that said third transistor (T4) is an NPN bipolar transistor. The three-terminal device according to anyone of the preceding claims, characterized in that it is integrated on a single silicon chip.

Inventors: PALARA SERGIO, PALARA, SERGIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H03K17
IPC codes: H02M1, H05B41, H03K17, H02M7