Amplifier

Abstract: An amplifier having an automatic threshold control circuit (ATC, 10) and a limiting amplifier (40). The ATC (10) detects and holds a top value (peak value) and bottom value of an input signal, and outputs the middle value between the top and bottom values as a reference voltage. The limiting amplifier (40) amplifies the input signal in a linear operating region whose center is set at the reference voltage, thereby maintaining the output amplitude at a constant value. Even if the amplitude and the level of the input signals instantaneously changes by a large amount, the ATC can follow the change, so that the offset compensation and gain compensation of the amplifier can be achieved instantaneously. This makes it possible to continue producing the output of a constant amplitude with little phase deviations.

Description: The present invention relates to an amplifier for an optical receiver circuit, and particularly to an amplifier which can stably maintain a constant output amplitude by automatically and instantaneously controlling offset voltage and gain in response to wide range changes in an input signal. Amplifiers are essential in an optical digital communications system for amplifying an attenuated signal in an optical receiver circuit, or for generating a stable clock signal by extracting a timing signal from input data by using a timing signal recovery circuit. These amplifiers are required to have a large gain, a wide dynamic range for an input signal, and a constant output amplitude. In an optical receiver circuit for an optical digital communications system as shown in Fig. 1, an optical signal is first converted into a current signal by a photodiode. Subsequently, the current signal is converted into a voltage signal, and then, amplified by an amplifier to a voltage amplitude, at which the logic levels can be identified. In addition, the voltage amplitude of the output signal must be maintained constant by automatically controlling the offset voltage and gain of the amplifier even if the input signal changes its level. A conventional amplifier implements these functions by combining a variable gain amplifier and a DC feedback circuit. Recently, introduction of an optical communications system that handles a burst mode data signals of various signal levels has been studied. The optical receiver circuit of such a system strongly requires an amplifier that can maintain a constant output amplitude by instantaneously controlling the offset voltage and gain. The conventional amplifier, however, has a problem in that it is slow in response because of a feedback loop, and cannot follow changes in the input signal. This problem will be explained in detail referring to Fig. 2 showing a conventional optical receiver circuit. In this figure, the intensity of an optical signal is converted into a current by a photodiode 1, and the current signal produced from the photodiode 1 is amplified and converted into a voltage signal by a preamplifier 2. The voltage output from the preamplifier 2 is further amplified and converted into an output voltage of a fixed amplitude by a voltage amplifier 3 which automatically performs the offset compensation and the gain control. The output voltage of a fixed amplitude is produced from the output terminal To. The offset compensation refers to a function which is achieved by providing the DC bias of the amplifier with an offset so that the reference voltage of the voltage amplifier 3 (that is, the voltage at point d of Fig. 2) is always set at the midpoint of the input signal waveform WF, which is shown by a dashed-and-dotted line in Fig. 2. Thus, the voltage amplifier 3 operates in the linear operating region whose center is the reference voltage. For example, if the peak value (referred to as a top value below) of the output waveform WF from the preamplifier 2 varies as shown in Fig. 2 in response to changes in the optical digital signal inputted to the photodiode 1, and is amplified by a common amplifier, only half of the linear operating region of the amplifier (one direction with regard to the bottom value of the waveform) becomes available. Thus, a wide dynamic range cannot be efficiently achieved, and distortions of the output waveform and deviations of the duty thereof are liable to occur. In view of this, the reference voltage applied to the voltage amplifier 3 is continually controlled to always take the middle value of the waveform WF by providing the DC bias of the amplifier with an offset. Thus, the voltage amplifier 3 operates in the linear operating region whose center is determined at the renewed reference voltage. More specifically, the offset control is carried out by an automatic offset compensation control circuit 5 including a top-holding capacitor 5A and a voltage amplifier 5B. The automatic offset compensation control circuit 5 detects the top value (peak value) of the output voltage of a variable gain amplifier 4, and feeds the detected component back to the offset control terminal d of the variable gain amplifier 4. Thus, the output waveform of the variable gain amplifier 4 is controlled to take a constant top level. On the other hand, the gain control refers to a function that controls the gain of the voltage amplifier 3 in order to maintain its output amplitude even if the input signal changes its amplitude or level. More specifically, the gain control is achieved by a gain control circuit 6 including a top-holding capacitor 6A and a voltage amplifier 6B. The gain control circuit 6 detects the top value of the output voltage of the variable gain amplifier 4, and feeds the detected component back to the gain control terminal c of the variable gain amplifier 4. Thus, the output amplitude of the voltage amplifier 3 is controlled to take a constant value. Combining these two feedback circuits can implement the offset compensation and the gain compensation at the same time. Thus, the automatic offset compensation control circuit 5 and the gain control circuit 6 have a top-detecting circuit composed of an amplifier and a capacitor. The top-detecting circuit charges the capacitor when the input is high, and blocks the discharge path by establishing a high output impedance of the amplifier when the input is low, thereby holding the detected top level of the waveform. Fig. 3A schematically illustrates an input waveform to the conventional voltage amplifier, and Fig. 3B illustrates the output waveform of the voltage amplifier produced in response to the input waveform. When the input waveform to the amplifier 4 changes instantaneously from a small to a large amplitude as illustrated in Fig. 3A, the output waveform begins to be generated under the condition that the small amplitude operation has established with regard to the gain and offset voltage, because the offset compensation and the gain compensation cannot be carried out instantaneously. As a result, the output waveform as illustrated in Fig. 3B is produced. In this case, a desired output amplitude cannot be obtained until the feedback fully achieves its function. The response delay is determined by the time constants associated with the capacitors 5A and 6A of the top-detecting circuits (that is, the automatic offset compensation control circuit 5 and the gain control circuit 6), and the delay times of the negative feedback circuits and the amplifier. The time constants associated with the capacitors 5A and 6A of the top-detecting circuit must be reduced as small as possible, in order to implement a circuit which provides a desired output amplitude as quick as possible. Even this, however, cannot give a response characteristics quicker than the delay time of the amplifier. Furthermore, although the time constant of the automatic gain control circuit 6 and that of the automatic offset compensation control circuit 5 are set different from each other to achieve a stable operation, the difference between the two must be reduced to implement the instantaneous response. This would make the system unstable because of the interference between the two feedback loops. This instability of the system occurs because the offset and the gain of the voltage amplifier are not independent. As described above, the output waveform of the voltage amplifier employed by the conventional optical receiver circuit largely changes in response to an instantaneous, large change in the input signal amplitude, and it takes rather a long time for the output waveform to take a constant amplitude. Thus, the conventional voltage amplifier is unsuitable to a receiver circuit that must achieve an instantaneous response to amplitude or level changes in a received optical signal. In other words, the conventional voltage amplifier has a problem in that the amplitude and duty of the output waveform are unstable because of the delay of the feedback circuits, when the amplitude or level of the input signal changes instantaneously. Document DE-A-2 905 904 discloses the features recited in the preamble of claim 1. In detail, this prior art document describes an amplifier comprising a limiting amplifier and an automatic threshold circuit. The limiting amplifier produces a limited output signal in the case where the amplitude of an input signal is greater than a predetermined value and the level of the input signal is within a predetermined range with regard to a reference voltage. The automatic threshold control circuit supplies the reference voltage to the limiting amplifier and comprises a top-hold circuit and a bottom-hold circuit. It is an object of the present invention to further develop this prior art amplifier such that it can output a signal of a constant amplitude and small phase deviations by performing the offset compensation and the gain compensation instantaneously, following large, instantaneous changes in the amplitude or level of the input signal. This object is achieved by an amplifier as set out in claim 1. Further aspects of the invention are set out in the dependent claims. The present invention combines the automatic threshold control circuit and the limiting amplifier. The automatic threshold control circuit detects the top value and bottom value of the input signal waveform, and outputs the midpoint between the two values as the reference voltage. The limiting amplifier maintains its output amplitude at a fixed value by operating on the basis of the reference voltage. This makes it possible to carry out instantaneous offset compensation and gain compensation for the amplitude or level change in the input signal, and to maintain the constant amplitude output with little waveform distortion and duty fluctuations. Moreover, a multi-staged configuration of the basic circuit makes it possible to implement a wide dynamic range, and to reduce offset variations involved in fabrication processes of integrated circuits. Furthermore, the reset function added to the basic circuit immediately returns the top value and the bottom value of the input signal waveform to their initial values. This makes it possible for the voltage amplifier to respond to instantaneous changes in the input signal from a large to a small amplitude. In addition, since the delay circuits are added between the reset signal terminals of the basic circuits connected in cascade, and the reset signal terminal of the first stage basic circuit is used as the reset signal terminal of the whole circuit, the reset operation is sequentially carried out from the first stage to the last stage, thereby carrying out correct initialization of each stage. Since the limited output amplitude of the amplifier is determined by the transistor characteristics such as transistor sizes by using the limiting amplifier in accordance with the present invention, the amplitude fluctuations of the limited output can be reduced in comparison with the conventional amplifier. Thus, the amplifier in accordance with the present invention is preferably applied to equalizing amplifiers of various communications systems, and serves to implement a high accuracy timing signal recovery circuit. Finally, the present invention can provide an amplifier which can prevent bit errors during a signaless period from the reset signal generation to the reception of the input signal, and which serves to implement high accuracy receiver circuits of the communications systems. The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings. Fig. 1 is a schematic block diagram showing an optical digital communications system; Fig. 2 is a circuit diagram showing a conventional optical receiver circuit; Figs. 3A and 3B are diagrams schematically illustrating input and output waveforms of the voltage amplifier of the conventional optical receiver circuit; Fig. 4 is a circuit diagram showing a basic circuit BC1 of a first embodiment in accordance with the present invention; Figs. 5A and 5B are waveform diagrams illustrating simulation results of the input and output waveforms in the first embodiment; Fig. 6 is a circuit diagram showing a second embodiment in accordance with the present invention, in which n basic circuits BC1 as shown in Fig. 4 are connected in cascade; Fig. 7 is a level diagram showing output levels of respective stages of the second embodiment as shown in Fig. 6; Fig. 8 is a diagram illustrating offset compensation operations at respective stages in the multi-staged configuration as shown in Fig. 6; Fig. 9 is a graph illustrating the relationships between the number of stages and allowable offset voltages due to variations of devices caused by fabrication processes, when the minimum amplitude of the input signal is assumed to be 10 mV in the multi-staged configuration as shown in Fig. 6; Figs. 10A - 10D are diagrams illustrating simulation results of waveforms when the number of stages is three in the multi-staged configuration as shown in Fig. 6; Fig. 11 is a circuit diagram showing a third embodiment in accordance with the present invention, which includes a reset function added to the basic circuit as shown in Fig. 4; Figs. 12A - 12C are diagrams illustrating simulation results of the reset operation in the third embodiment as shown in Fig. 11; Fig. 13 is a circuit diagram showing a fourth embodiment in accordance with the present invention, in which basic circuits BCa1 as shown in Fig. 11 are multi-staged; Figs. 14A - 14E are diagrams illustrating simulation results in the fourth embodiment as shown in Fig. 13, when the number of stages is three; Fig. 15 is a circuit diagram showing a conventional limiting amplifier; Figs. 16A and 16B are graphs illustrating the input-output characteristics of the conventional limiting amplifier; Figs. 17A - 17C are circuit diagrams showing a limiting amplifier of an example not forming part of the present invention; Figs. 18A - 18E are diagrams illustrating the limiting operation of the first stage amplifier 112 of the example shown in Figs. 17A-17C ; Figs. 19A and 19B are diagrams illustrating the limiting operation of the second stage amplifier 113 of the example shown in Figs. 17A-17C ; Figs. 20A - 20C are circuit diagrams showing a limiting amplifier of a further example not forming part of the present invention; Figs. 21A - 21C are graphs illustrating the limiting operation of the limiting amplifier of the the example shown in Figs. 21A-21C ; Figs. 22A and 22B are graphs illustrating gain sharing between the two amplifiers of the limiting amplifier of the example shown in Figs. 21A-21C; Figs. 23A - 23C are circuit diagrams showing a limiting amplifier of another example not forming part of the present invention; Figs. 24A - 24D are graphs illustrating input-output characteristics of the limiting amplifier of the example shown in Figs. 23A-23C ; Figs. 25A and 25B are a circuit diagram and an equivalent circuit diagram of its part, showing a top-hold circuit of a fifth embodiment in accordance with the present invention; Figs. 25C and 25D are a circuit diagram and an equivalent circuit diagram of its part, showing a bottom-hold circuit of the fifth embodiment in accordance with the present invention; Figs. 26A and 26B are waveform diagrams illustrating noise generating mechanism in the third embodiment as shown in Fig. 11; Figs. 27A and 27B are a waveform diagram and a graph illustrating noise and its voltage in the fourth embodiment as shown in Fig. 13; Fig. 28A is a circuit diagram showing an amplifier of a further example not forming part of the present invention; Figs. 28B and 28C are diagrams illustrating main waveforms of the example shown in Fig. 28A ; Fig. 29A is a circuit diagram showing an amplifier of another example not forming part of the present invention; Fig. 29B is a diagram illustrating main waveforms of the example shown in Fig. 29A ; Fig. 30A is a circuit diagram showing an amplifier of a sixth embodiment in accordance with the present invention; Figs. 30B and 30C are diagrams illustrating main waveforms of the sixth embodiment; Fig. 31A is a circuit diagram showing an amplifier of a seventh embodiment in accordance with the present invention; Fig. 31B is a diagram illustrating main waveforms of the seventh embodiment; Fig. 32A is a circuit diagram showing an amplifier of an eighth embodiment in accordance with the present invention; Fig. 32B is a diagram illustrating main waveforms of the eighth embodiment; and Fig. 33 is a circuit diagram showing an amplifier of a nineth embodiment in accordance with the present invention. The invention will now be described with reference to the accompanying drawings. EMBODIMENT 1 Fig. 4 is a circuit diagram showing a basic circuit BC1 of a first embodiment in accordance with the present invention. The basic circuit BC1 includes an ATC (Automatic Threshold Control circuit) 10, and a limiting amplifier 40, in addition to an input terminal Ti and an output terminal To. The ATC 10 is an example that detects and holds the top value and the bottom value of the input waveform, and outputs an approximately middle value between the top value and the bottom value, as a reference voltage. The ATC 10 comprises a top value detect and hold circuit (referred to as a top-hold circuit below for the purpose of simplicity) 20, a bottom value detect and hold circuit 30 (referred to as a bottom-hold circuit below for the purpose of simplicity) 30, and resistors R1 and R2 connected in series between the output terminals of the two circuits 20 and 30. The top-hold circuit 20 has a holding capacitor 21 and an amplifier 22, and detects and holds the top value of the input signal waveform applied to the input terminal Ti. The bottom-hold circuit 30 has a holding capacitor 31 and an amplifier 32, and detects and holds the bottom value of the input signal waveform applied to the input terminal Ti. The top-hold circuit 20 charges the holding capacitor 21 while the input signal is high, and blocks the discharge path by making the output impedance of the amplifier 22 high while the input signal is low, thereby detecting and holding the top value of the waveform. Conversely, the bottom-hold circuit 30 charges the holding capacitor 31 while the input signal is low, and blocks the discharge path by making the output impedance of the amplifier 32 high while the input signal is high, thereby detecting and holding the bottom value of the waveform. The limiting amplifier 40 receives the input signal which is supplied from the input terminal Ti, and the reference voltage which makes the input signal operate in the linear operating region, and produces the output signal of a constant amplitude when the amplitude of the input signal exceeds a particular level. The limiting amplifier 40 has an input terminal a, an output terminal b, and a reference voltage (offset voltage) control terminal d. The input terminal a of the limiting amplifier 40 and the input terminal of the ATC 10 are connected in common to the input terminal Ti of the basic circuit BC1. The output terminal of the ATC 10 is connected to the reference voltage input terminal d of the limiting amplifier 40, and the output terminal b of the limiting amplifier 40 is connected to the output terminal To of the basic circuit BC1. Next, the operation of this embodiment will be described. First, the top-hold circuit 20 and the bottom-hold circuit 30 generate the top value and the bottom value of the input signal waveform, respectively. Then, the middle voltage between the top value and the bottom value is generated from the voltage divider consisting of the resistors R1 and R2. The middle voltage is applied to the limiting amplifier 40 as its reference voltage (offset voltage) so that the offset compensating operation is carried out. The limiting amplifier 40 also implements the gain compensating operation by limiting the output amplitude associated with an input signal whose amplitude is above a certain level. According to this embodiment, the delay of response involved in the offset compensation and gain compensation, which mainly occurs owing to the negative feedback loop in the conventional circuit as shown in Fig. 2, can be greatly reduced, because the response time of this embodiment is determined by the time constant of the top-hold circuit 20 and that of the bottom-hold circuit 30. Reduction of these time constants to a certain level will prevent the entire circuit from becoming unstable, which is different from the conventional circuit as shown in Fig. 2. Thus, this embodiment can achieve the offset compensation and the gain compensation at the same time during a single bit of the signal. Figs. 5A and 5B show simulation results of the input and output waveforms in the present embodiment. The simulation was carried out under the assumptions that the amplifiers were differential amplifiers fabricated using 0.8 micrometer MOS integrated circuit technique, and that the code rate of the input signal was 30 Mb/s. Fig. 5A shows the input signal waveform 51 at the input terminal Ti, the output signal waveform 52 of the top-hold circuit 20, the output signal waveform 53 of the bottom-hold circuit 30, and the output signal waveform 54 of the ATC 10. Fig. 5B shows the output signal waveform 55 of the limiting amplifier 40. The output signal waveform 54 of the ATC 10 is the signal waveform applied to the reference voltage input terminal d of the limiting amplifier 40, and the output signal waveform 55 of the limiting amplifier 40 is the output signal waveform of the basic circuit BC1. As will be seen from this figures, the output signal waveform 52 of the top-hold circuit 20 and the output signal waveform 53 of the bottom-hold circuit 30 instantaneously follow the transition from a small to a large amplitude of the input signal. Thus, the reference voltage, that is, the output signal waveform 54 of the ATC 10, is instantaneously set within a single bit duration of the data. The limiting amplifier 40, receiving the input signal and the reference voltage, performs a limiting amplification that limits the output amplitude. Since the reference voltage is set at the midpoint of the input signal waveform 41, the output signal waveform 55 of the limiting amplifier 40 (that is, the output of the basic circuit BC1) includes little waveform distortions or duty fluctuations, and continues to output a signal of a fixed amplitude. Thus, this embodiment carries out instantaneous offset and gain compensations against changes in the input signal, and continues the output signal of a fixed amplitude including little waveform distortions and duty fluctuations. Effects of the present embodiment were confirmed by a prototype integrated circuit corresponding to an optical receiver of a PDS (Passive Double Star) subscriber system. An amplifier IC (integrated circuit) of this embodiment was combined with a photodiode and a low-noise CMOS preamplifier to constitute a receiver module. The receiver module achieved a minimum receiving sensitivity of -42 dBm, and a dynamic range of 25 dB in a burst transmission of 29 Mb/s, which were not achieved in the conventional circuit. In addition, the instantaneous response of the amplifier IC during a single bit was confirmed in the transmission test. Table 1 shows measured results of the characteristics of the amplifier IC and the receiver module. PROTOTYPE IC PERFORMANCE AMP IC DYNAMIC RANGE > 65 dB (IN VOLTAGE POWER) GAIN > 60 dB (IN VOLTAGE POWER) BANDWIDTH > 60 MHz RECEIVER MINIMUM RECEIVING SENSITIVITY -42 dBm MODULE (IN OPTICAL POWER: η = 0.85 A/W) DYNAMIC RANGE 25 dB (IN OPTICAL POWER) SUPPLY VOLTAGE +5v SINGLE This embodiment is suitable for the low-cost CMOS process because it can allow considerable offset variations. This embodiment is also suitable for integrated circuits because it operates without adjustment and requires no external components such as level holding capacitors. Thus, this embodiment is very advantageous to reduce the cost of the receiver. In addition, the amplifier of this embodiment is expected to serve as a high gain, wide dynamic range, low jitter limiting amplifier, which is needed in wireless communications systems or in measurement systems. EMBODIMENT 2 Fig. 6 is a circuit diagram showing a second embodiment in accordance with the present invention, in which n basic circuits BC1, BC2, ..., and BCn, which are identical to the basic circuit BC1 shown in Fig. 4, are connected in cascade. This n-stage cascade connection of the basic circuit BC1, BC2, ..., and BCn makes possible the wide dynamic range amplification of the input signal. In addition, it can tolerate the variations in the amplifiers 22, 32 and 40, resistors R1 and R2, and the holding capacitors 21 and 31 due to variations in the components caused during fabrication of the integrated circuit. This will be explained in more detail below. Fig. 7 schematically illustrates the level diagram of this embodiment as shown in Fig. 6. Fig. 7 shows that if the input signal level to the basic circuit BC1 is x, the second basic circuit BC2 limits the amplitude of the output signal associated with the input signal. If the input signal level to the basic circuit BC1 is y, the third basic circuit BC3 limits the amplitude of the output signal associated with the input signal, and if the input signal level to the basic circuit BC1 is z, which is still smaller, the n-th basic circuit BCn limits the amplitude of the output signal associated with the input signal. Thus, the received minimum level of the input signal to the first stage basic circuit BC1 can be further improved as the number of stages of the basic circuits is increased, thereby increasing the dynamic range. Fig. 8 illustrates the offset compensation operations at individual stages in the multi-staged configuration as shown in Fig. 6. Fig. 8 illustrates the way how the multi-stages reduce the amount of deviation of the output of the ATC 10 in the first basic circuit BC1 from the middle value of the input signal, considering variations in the components (variations in the transistor performances, resistances, and capacitances) involved in the fabrication processes of the integrated circuit. In this figure, the bold arrows 51a, 51b and 51c represent the amplitudes of the input signals to the respective stages, P1, P2 and P3 designate the output levels of the top-hold circuits 20 of the respective stages, B1, B2 and B3 designates the output levels of the bottom-hold circuits 30 of the respective stages, and Vt1, Vt2 and Vt3 denote the output levels of the ATCs 10 of the respective stages. In the circuit operation, it is assumed that although the top-hold circuits 20 follow and hold the changes from a low level to a high level, it does not follow the inverse changes from a high level to a low level. At the same time, it is assumed that although the bottom-hold circuits 30 follow and hold the changes from a high level to a low level, it does not follow the inverse changes from a low level to a high level. This is because the detection and holding of the top value and the bottom value are generally carried out by charging a capacitor, which can follow in one direction only. As will be seen from Fig. 8, although the reference voltage Vt1 of the first stage is not set at the center of the amplitude of the input signal, the reference voltage Vt3 of the limiting amplifier 40 of the third stage is set at the center of the signal amplitude, after repeating the amplification (inverting amplification) together with the detection and holding of the top and bottom values. Thus, the multi-stages can tolerate more component variations (variations in transistor performances, resistances and capacitances) involved during the fabrication of the integrated circuit. This is because the reference voltages are generated through the voltage dividers consisting of the resistors R1 and R2, and hence, the gain for the reference voltage is less than the gain for the signal by an amount of 6 dB at each stage when R1 = R2. Thus, the gain difference, together with the multi-stages, allows the variations generated during the fabrication. The relationships between the number of stages and the allowable offset voltage Voff are obtained analytically. Assuming that the voltage gain of the limiting amplifier 40 is Av, and the minimum amplitude of the input signal is Vs, the condition for setting an optimum reference voltage is given by the following expression, because the optimum reference voltage is obtained when the amplified signal output amplitude exceeds the amplified voltage of the offset voltage Voff applied to the first limiter amplifier. Voff·Av·(Av/2) n-1 < Vs·(Av) n Reducing this expression gives Voff < Vs·2 n-1 It should be notices here that the allowable offset voltage Voff at the input terminal of the limiting amplifier in the first stage is determined by the number of the stages, independent of the gain of the amplifiers. Fig. 9 shows the relationships between the number of stages in the multi-staged configuration as shown in Fig. 6 and the allowable offset voltages caused by the variations in the components involved in the fabrication processes. The relationships were calculated using expression (2), assuming that the minimum amplitude Vs is 10 mV. As will be seen from Fig. 9, the allowable offset voltage increases consistently with the number of stages of the basic circuits. Figs. 10A - 10D illustrate simulation results of the operational waveforms when the number of stages of the multi-staged configuration as shown in Fig. 3 was three. It was assumed in the simulation that the code rate of the input signal was 30 Mb/s, and that the amplifiers were a differential amplifier. Figs. 10A - 10D illustrate the input signal waveforms 51-1, 51-2 and 51-3 at the input terminals of the limiting amplifiers 40 of the respective stages, the output signal waveforms 52-1, 52-2 and 52-3 of the top-hold circuits 20 of the respective stages, the output signal waveforms 53-1, 53-2 and 53-3 of the bottom-hold circuits 30 of the respective stages, the output signal waveforms 54-1, 54-2 and 54-3 of ATCs 10 of the respective stages, and the output signal waveform 55 of the final stage. The numerals attached via a hyphen to the numerals denoting the signal waveforms designate the stage numbers. For example, the input signal waveform 51-1 designates the input signal waveform to the first basic circuit BC1, and the output signal waveform 52-3 designates the output signal waveform from the third basic circuit BC3. The amplitude of the input signal waveform 51-1 to the first stage was set at 0.0065 V from the beginning to 400 ns, at 0.065 V from 400 ns to 700 ns, and at 0.65 V thereafter. The output amplitude of the final stage was set at 3.2 V. The input signal of the minimum amplitude of 0.0065 V was limited at the third stage, the input signal of 0.065 V was limited at the second stage, and the input signal of 0.65 V was limited at the first stage. The optimum setting of the reference voltage makes it possible to produce the output signal waveform of a fixed amplitude and of little duty fluctuations for a dynamic range of 40 dB of 0.0065 V - 0.65 V. EMBODIMENT 3 Fig. 11 shows a third embodiment, in which a reset function is added to the first embodiment as shown in Fig. 4. Although the basic circuit BCa1 as shown in Fig. 11 is fundamentally similar to the basic circuit BC1 as shown in Fig. 4, the basic circuit BCa1 differs from the basic circuit 10 in that it has an ATC 10a instead of the ATC 10, and that a reset signal terminal 71t is connected to the basic circuit BCa1 via a buffer amplifier 71 for the reset signal. Specifically, the ATC 10a of the basic circuit BCa1 is connected to the reset signal terminal 71t via the external buffer amplifier 71, so that the input signal and output signal of the ATC 10a, that is, the voltages at points a and d of Fig. 11, are made equipotential by a signal applied to the reset signal terminal 71t. The ATC 10a differs from the ATC 10 in that it has a top-hold circuit 20a instead of the top-hold circuit 20, and a bottom-hold circuit 30a instead of the bottom-hold circuit 30. The top-hold circuit 20a differs from the top-hold circuit 20 in that it includes an amplifier 22a having a reset signal terminal r instead of the amplifier 22. Likewise, the bottom-hold circuit 30a differs from the bottom-hold circuit 30 in that it includes an amplifier 32a having a reset signal terminal r instead of the amplifier 32. The top-hold circuit 20 and the bottom-hold circuit 30 of the first embodiment as shown in Fig. 4 can only follow the level changes in one direction as described above. As a results, although they can instantaneously follow when the input signal changes from a small amplitude to a large amplitude as shown in Figs. 10A - 10D, they cannot follow the inverse changes from a large amplitude to a small amplitude. The present embodiment as shown in Fig. 11, however, can follow when the amplitude of the input signal reduces. More specifically, the electric charges in the holding capacitors 21 and 31 of the top-hold circuit 20a and the bottom-hold circuit 30a are instantaneously discharged by the reset signal, and the circuits 20a and 30a are returned to the initial state in this embodiment. Hence, if these circuits 20a and 30a are returned to the initial states immediately before the input signal changes from a small amplitude to a large amplitude, the ATC 10a can instantaneously respond to this change. Thus, the reset function of the top-hold circuit 20a and the bottom-hold circuit 30a refers to the function that instantaneously discharges the electric charges stored in the holding capacitors 21 and 31, thereby returning the circuits 20a and 30a to the initial state. Fig. 12A - 12C illustrate simulation results of the reset operation in the third embodiment as shown in Fig. 11. It was assumed in the simulation that the code rate of the input signal was 30 Mb/s, and that the amplifiers were a differential amplifier. In addition, the reset signal was assumed to have a pulse width of 60 ns. Figs. 12A - 12C illustrate the input signal waveform 51 at the input terminal Ti, the output signal waveform 52 of the top-hold circuit 20a, the output signal waveform 53 of the bottom-hold circuit 30a, the output signal waveform (reference voltage) 54 of the ATC 10a, the output signal waveform 55 of the limiting amplifier 40, and the reset signal waveform 56 at the reset signal terminal 71t. The output signal waveform 54 of the ATC 10a is the signal waveform applied to the reference voltage input terminal d of the limiting amplifier 40, and the output signal waveform 55 of the limiting amplifier 40 is the output signal waveform of the basic circuit BC1. Fig. 12A - 12C show a case, in which after the input signal waveform 51 had terminated its large amplitude state, the reset signal 56 was applied, followed by the input signal waveform 51 of a small amplitude. The output signal 52 of the top-hold circuit 20a, the output signal 53 of the bottom-hold circuit 30a, and the output signal 54 of the ATC 10a had been once returned to the initial state, in which they had been set at substantially equipotential, and subsequently, followed the input signal of a small amplitude. The reset signal was supplied from the outside to the reset signal terminal 71t. EMBODIMENT 4 Fig. 13 is a circuit diagram showing a fourth embodiment in accordance with the present invention, in which a plurality of basic circuits BCa1 as shown in Fig. 11 are connected in cascade. More specifically, the basic circuits BCa1, BCa2, ... , and BCan, which are identical to the basic circuit BCa1, are connected in cascade, and the individual ATCs 10a in the basic circuits BCa1, BCa2, ... , and BCan can be reset sequentially by an external reset signal so that the input signal and output signal of each ATC 10a are made equipotential by the reset signal. For this purpose, delay circuits 81, 82, ... are provided between the buffer amplifiers 71, 72, ... and 7n connected to the basic circuits BCa1, BCa2, ..., and BCan, respectively, and the reset signal terminal 71t of the first basic circuit BCa1 is made the reset signal terminal of the entire circuit. The delay circuits 81, 82, ... provide the reset signals for the respective stages with a delay, and this will stabilize the reset operation. If all the stages are reset simultaneously, the outputs of all the stages will change at the same time. Thus, the second and the following stages will be influenced by the response characteristics of the output of the preceding stages, which may cause reset errors. To prevent this, the delay circuits 81, 82, ... are interposed between the buffer amplifiers 71, 72, ... , and 7n so that the respective stages are correctly reset to the initial state. Figs. 14A - 14D illustrate results of a simulation carried out in the fourth embodiment as shown in Fig. 13, in which the number of stages was three. It was assumed in the simulation that the code rate of the input signal was 30 Mb/s, and that the amplifiers were a differential amplifier. In addition, the reset signal was assumed to have a pulse width of 60 ns. Figs. 14A - 14E illustrate the input signal waveforms 51-1, 51-2 and 51-3 at the input terminals of the limiting amplifiers 40 of the respective stages, the output signal waveforms 52-1, 52-2 and 52-3 of the top-hold circuits 20a of the respective stages, the output signal waveforms 53-1, 53-2 and 53-3 of the bottom-hold circuits 30a of the respective stages, the output signal waveforms 54-1, 54-2 and 54-3 of the ATCs 10a of the respective stages, and the output signal waveform 55 of the final stage. The simulation results were obtained when the input signal waveform 51-1 of a large amplitude of 0.65 V had been applied to the first stage, and subsequently, the input signal was made zero, followed by the application of the reset signal, and then, the input signal of a small amplitude of 0.0065 V was applied to the first stage. It will be seen from these figures that the circuits of the respective stages were sequentially reset to the initial state by the delayed reset signal, so that the outputs of the top-hold circuit 20a, bottom-hold circuit 30a, and ATC 10a were made substantially equipotential, and that instantaneous responses were obtained when the small amplitude signal was inputted thereafter. Since this embodiment can tolerate the offset variations, it is very suitable for an integrated circuit. Although the ATCs 10 and 10a of the above embodiments output the middle value between the top value and the bottom value, as the reference voltage, the reference voltage is not restricted to the middle value. A value about the middle value between the top value and the bottom value may be outputted as the reference voltage. The above described embodiments 1 - 4 can be applied not only to the optical receiver circuit, but also to wireless communications systems or measurement systems, which require a high gain, wide dynamic range, low jitter limiting amplifier. In the above described embodiments 1 - 4, the limiting amplifier 40 plays an important role. A conventional limiting amplifier as shown in Fig. 15 has been used as such a type of amplifier. This amplifier 101 includes a differential amplifier 101A and an output stage 101B. In addition, the amplifier 101 includes an output limiting resistor 102, an input terminal 103, an output terminal 104, a drain supply voltage terminal 105, and a source supply voltage terminal 106. Figs. 16A and 16B show typical relationships between the input signal voltage and output signal voltage of the limiting amplifier. In these figures, the reference numeral 107 designates the input-output characteristics of the conventional limiting amplifier 101, 108 designates the input signal, 109 designates the lower limit value Vl of the limited output of the limiting amplifier, 110 designates the upper limit value Vh of the limited output, and 111 designates the central value of the input signal. The output amplitude of the conventional limiting amplifier 101 is limited as follows: First, the upper limit of the output is determined by Vh which is determined by a constant gate-source voltage VGS of a transistor mn4 when Ir = 0, as will be described later. On the other hand, the lower limit of the output is given by Vl = VDD - R1 × Ir, , which is determined by a saturation current Ir. The saturation current Ir in turn is determined by the resistor 102 (whose value is R1) and the DC characteristics of the transistors mn4 and mn5. Thus, the limiting amplifier 101 limits the output amplitude between Vl - Vh as shown in Fig. 16A. The values R1 and Ir, however, will be influenced by a fabrication process of the IC. The value R1 of the resistor 102 will be changed owing to deviations of sheet resistances and contact resistances from the design values, and the current Ir will be influenced by the variations in the threshold voltage of a current source transistor mn5 in the output stage 101B of the limiting amplifier 101, because Ir is determined by the DC characteristics of the transistor mn5. The differential amplifier 101A itself will operate as a limiting amplifier because its load current is limited by a constant current source. Using FETs (Field Effect Transistors) in the constant current source of the differential amplifier employing FETs, however, presents a problem in that the lower limit of the output will fluctuate in response to the input signal level as shown in Fig. 16B. This is because the FET used in the constant current source has a large drain conductance, and this will cause the reduction of the drain-source voltage of the FET, which will hinder the FET from carrying out a constant current source function, and will cause fluctuations of the constant current. Thus, the conventional limiting amplifier has a problem in that the limiting characteristics of the output will fluctuate owing to the characteristics (current-voltage characteristics) of the transistors, or the variations in the resistor. In addition, it is difficult to stably maintain the limiting level of the output against the changes in the input signal level. This arises a problem in that it is difficult to make a matching between the output of a limiting amplifier and the input range of the next stage, when the limiting amplifier is used in a multi-staged configuration or the output of the limiting amplifier undergoes a signal processing of the next stage. The following examples not forming part of the invention can implement a limiting amplifier meeting the following requirements. (1) The upper and lower limits of the limited output can be correctly set by only utilizing the current-voltage characteristics of the transistors of the output source-follower stage without using a resistor. (2) The upper and lower limits of the limited output can be stably set at a desired value. (3) The output should have a good waveform. This will be achieved by utilizing a complementary effect of a cascade connection of amplifiers composed of different conductivity type transistors. One example includes cascaded two amplifiers of different conductivity types, and limits the upper and lower limits of the output by the source-gate voltages of the FETs of the output stages of the respective amplifiers. The second stage amplifier must be a non-inverted amplifier in this example. Figs. 17A - 17C show the limiting amplifier of this example. Fig. 17A show the entire configuration of the limiting amplifier, Fig. 17B shows a circuit configuration of an n-channel drive CMOS amplifier 112, and Fig. 17C shows a circuit configuration of a p-channel drive CMOS amplifier 113. In these figures, the reference numeral 114 designates an input terminal, and 115 designates an output terminal. This example differs from the conventional limiting amplifier in that it implements the limiting characteristics of the CMOS limiting amplifier by using the transistor characteristics without using a resistor. In other words, both the upper and lower limits of the output are determined by the transistor characteristics. More specifically, the cascade connection of the n-channel drive CMOS amplifier 112 and the p-channel drive CMOS amplifier 113 makes it possible to determine the upper and lower limits of the output of the limiting amplifier by the gate-source voltage Vgs of the transistors. The operation of setting the upper and lower limits of the output of the limiting amplifier will be described below. Figs. 18A - 18E illustrate the operation of setting the upper and lower limits of the n-channel amplifier 112. As shown in Fig. 18A, the upper limit voltage Vnh of the n-channel amplifier 112 will be determined by the following equation. Vnh = VDD - VGSn where VDD is the drain supply voltage, and VGSn is the gate-source voltage of the transistor mn4 of the output stage. This relationship will be described. First, relationships between the gate-source voltage Vgs and the drain current Id of a transistor are generally as shown in Fig. 18B. The drain current Id is proportional to the square of the difference between the gate-source voltage Vgs and the threshold voltage Vth, and its constant of proportionality is determined by the ratio W/L (referred to as a transistor size below), where W and L are the channel width and the channel length of the transistor, respectively. Accordingly, maintaining the gate-source voltage Vgs at a constant value VGS will make the drain current ID constant. Conversely, maintaining the drain current ID at a constant value will make Vgs a constant value VGS. The gate voltage of the transistor mn5 of the n-channel amplifier 112 is kept constant, and hence, it functions as a constant current source that supplies the transistor mn4 of the output stage with a constant current In. Accordingly, the gate-source voltage Vgs of the transistor mn4 of the output stage is maintained at a constant value VGS which is determined by the Id-Vgs characteristics of the transistor and the constant current In. Since the output voltage of the n-channel amplifier 112 equals the gate voltage of the transistor mn4 minus VGS, it takes a maximum value when the gate voltage is maximum. Since the gate voltage becomes maximum when it is equal to the drain voltage as shown in Fig. 18C, the upper limit voltage of the n-channel amplifier 112 is determined by the above-mentioned equation. Thus, the upper limit of the output voltage of the n-channel amplifier 112 is determined by VDD and VGS. The value VGS can be controlled by changing the transistor size of the transistor mn4, or by changing the constant current In by varying the transistor size of the transistor mn5. On the other hand, the lower limit voltage Vnl of the n-channel amplifier 112 will be changed in response to the input signal level as shown in Fig. 16B. This will be explained in more detail. As shown in Fig. 18D, if the input voltage to the n-channel amplifier 112 drops, the drain voltage of the transistor mn2 will also drop. Thus, if the gate-source voltage Vgs of the source follower transistor mn4 of the output stage approaches the threshold value Vth, the drain current of the transistor mn4 approaches zero. In this case, the operation of the transistor mn5 of the output stage, which has been functioning as a constant current source, moves into the linear ohmic region as shown in Fig. 18E, so that the drain-source voltage Vds of the transistor mn5 changes in response to the input signal level. As a result, the lower level voltage of the n-channel amplifier 112 will change in response to the input signal level. Next, the operation for setting the upper and lower limit values of the p-channel amplifier 113 will be explained with reference to Figs. 19A and 19B. First, the lower limit value Vpl is given by the following equation as shown in Fig. 19A. Vpl = VSS + VGSp where VGSp is the gate-source voltage of the source follower transistor mp4 of the output stage, as shown in Fig. 19B. This relationship will be described referring to Fig. 19B. As in the n-channel amplifier 112, the transistor mp5 functions as a constant current source generating a constant current Ip. Therefore, the gate-source voltage Vgs of the transistor mp4 of the output stage is maintained at a constant value VGSp. Thus, the output of the p-channel amplifier 113 takes a lower limit value when the gate voltage equals VSS, and that lower limit value is given the above-mentioned equation. The value VGSp can be controlled by changing the transistor size of the transistor mp4, or by changing the constant current Ip by varying the transistor size of the transistor mp5. Thus, the lower limit value of the p-channel amplifier 113 is determined by the transistor characteristics and VSS. On the other hand, the upper limit value Vph of the p-channel amplifier 113 will fluctuate in response to the input signal level as the low limit value of the n-channel amplifier 112. The upper limit of the input signal to the p-channel amplifier 113, however, has been limited at Vnh. Therefore, the upper limit of the output of the p-channel amplifier 113 is limited to Vph that corresponds to Vnh. As a result, the output of the p-channel amplifier 113 takes the lower limit VPl and the upper limit Vph as shown in Fig. 19A. Thus, the upper and lower limits of the limited output can be determined by the gate-source voltages VGS of the source follower transistors of the n-channel and p-channel amplifiers 112 and 113 in this embodiment. Since this example does not use a resistor, it is not influenced by variations in the resistor, thereby stably maintaining the upper and lower limits of the limited output. In addition, combining the two amplifiers of the different conductivity types makes it possible to obtain a high-quality output waveform of good symmetry due to the complementary effect. Furthermore, the amplitude and the upper and lower limit values of the limited output can be determined at a desired value as a design parameter. The conductivity type of the amplifier 112 and that of the amplifier 113 can be exchanged without losing the effects describe above. In addition, the gain of each amplifier can be set at a desired value without any adverse effect on the limiting operation. Moreover, it is not required that the first amplifier 112 be a non-inverting amplifier. In other words, the differential amplifier of the n-channel amplifier 112 can be used by exchanging the signal input terminal and the reference voltage terminal. EMBODIMENT 6 Figs. 20A - 20C show a further example not forming part of the present invention, which differs from the above example in the following points: (1) An inverting amplifier is employed as a second stage p-channel amplifier 113A. More specifically, the signal input terminal and the reference voltage terminal of Fig. 20C are exchanged for those of Fig. 17C. (2) The gain of the differential amplifier of the first stage n-channel amplifier 112 is increased, and the gate-source voltage Vgs of the source follower transistor mn4 is increased in comparison with those of the n-channel amplifier 112 of Fig. 17B. This will make the source supply voltage VSS the lower limit value of the n-channel amplifier 112 as shown in Fig. 21A. More specifically, the gate voltage of the source follower transistor mn4 will drop below the threshold voltage Vth when the input signal level drops below a certain level, and this will make the drain current zero. As a result, the drain current of the constant current source transistor mn5 becomes zero, and its drain-source voltage also falls to zero. Thus, the output of the n-channel amplifier 112 is limited to the source supply voltage VSS. (3) The gain of the second stage p-channel amplifier 113A is decreased in comparison with that of the p-channel amplifier 113 in Fig. 17C. In addition, the reference voltage Vrefp of the p-channel amplifier 113A is biased from the center of the input range toward the source supply voltage VSS. Thus, the input-output characteristics of the p-channel amplifier 113A is as shown in Fig. 21B, in which the upper limit voltage Vph of the p-channel amplifier 113A, which corresponds to the lower limit input VSS from the first stage n-channel amplifier 112, is set such that it does not reach the drain voltage VDD. The lower limit of the limited output of the p-channel amplifier 113A is determined either by the gate-source voltage VGSp of the source follower transistor mp4, or by the upper limit voltage Vnh' of the output of the first stage n-channel amplifier 112 as shown in Fig. 21C. In the latter case, the lower limit can be determined by the gate-source voltage VGSn of the source follower transistor mn4. Thus, the limiting operation can be achieved without using a resistor, even if the second stage p-channel amplifier is an inverting amplifier. Therefore, the upper and lower limits of the limited output can be stabilized independently of variations in resistors. A rather arbitrary gain sharing can be implemented between the n-channel amplifier 112 and the p-channel amplifier 113A. Figs. 22A and 22B illustrate the states when the gain of the n-channel amplifier 112 and that of the p-channel amplifier 113A are changed. Since the upper and lower limits of respective amplifiers are determined independently of the gains, a desired gain sharing can be determined in a certain range. Figs. 23A - 23C show another example not forming part of the present invention. The limiting amplifier of this example also includes an n-channel amplifier 123 and a p-channel amplifier 124 as its basic part as in the above described example. The p-channel amplifier 124 is an inverting amplifier, which constitutes a voltage follower circuit together with resistors R2 and R3. The reference voltage of the p-channel amplifier 124 is generated by an internal voltage source including three transistors mn5, mn6 and mp7. Fig. 24A - 24D are graphs for explaining the upper and lower limits of the limiting amplifier. Figs. 24A and 24B illustrate the upper and lower limits of the n-channel amplifier 123 and the p-channel amplifier 124, respectively, as Figs. 21A and 21B. The lower limit voltage of the limited output is determined either by the upper limit voltage Vnh of the n-channel amplifier 123 as shown in Fig. 24C, or by the lower limit voltage Vpl of the p-channel amplifier 124 as shown in Fig. 24D. In other words, the lower limit of the limited output is determined either by the gate-source voltage VGSn of the source follower transistor mn4 of the n-channel amplifier 123, or by the gate-source voltage VGSp of the source follower transistor mp4 of the p-channel amplifier 124. On the other hand, the upper limit of the limited output is determined in the same way as in the above example. Since the present example employs a voltage follower consisting of the p-channel amplifier 124 and the resistors R2 and R3, as the second stage amplifier, the following advantages can be gained. (1) This makes possible a wide frequency range operation, and a large capacitive load drive. (2) A desired gain can be achieved by selecting the resistance ratio of the resistors R2 and R3. Since a high accuracy resistance ratio can be established between resistors in a monolithic circuit, a stable gain can be obtained. EMBODIMENT 5 Figs. 25A and 25C show an example of the top-hold circuit 20 and an example of the bottom-hold circuit 30 used in the embodiments 1 - 4. Fig. 25B shows a major part of the top-hold circuit 20. The top value of a differential amplifier 140 is held by a capacitor 142 through a diode 141. The electric charge in the capacitor 142 is discharged by turning on a reset switch 143. Fig. 25D shows a major part of the bottom-hold circuit 30. The bottom value of a differential amplifier 145 is held by a capacitor 147 through a diode 146. The electric charge in the capacitor 147 is discharged by turning on a reset switch 148. In the above described embodiments 1 - 4, the middle value between the output of the top-hold circuit 20 (or 20a) that holds a maximum value of the input burst signal, and the output value of the bottom-hold circuit 30 (or 30a) that holds a minimum value thereof, is set as the reference voltage of the amplifier 40. Thus, the offset compensation is carried out so that burst signals of different levels are received instantaneously and amplified stably. Fig. 26A illustrates received data inputted to the amplifier BCa1 of the third embodiment as shown in Fig. 11, amplitude noise superimposed on the received data, the output signal from the top-hold circuit 20a, the output signal from the bottom-hold circuit 30a, and the output signal from the ATC 10a. The ordinate of this figure represents voltage, and the abscissa represents time. Fig. 26B illustrates the output data of the final stage amplifier BCan, and amplified noise in a multi-staged configuration of the amplifiers BCa1 - BCan. The ordinate of this figure represents voltage, and the abscissa represents time. The third embodiment as shown in Fig. 11 has a reset function which makes the input and output voltages of the top-hold circuit 20a equal, and those of the bottom-hold circuit 30a equal, by a reset signal inputted to the ATC 10a. Thus, applying the reset signal to the ATC 10a makes the input signal and the output signal of the ATC 10a equipotential. As a result, even if the input data changes from a large amplitude to a small amplitude, the offset compensation is carried out instantaneously. In this case, noise V noise occurs about the output signal of the ATC 10a, and the noise is also superimposed on a burst signal as shown in Fig. 26B. This is because when the circuits are reset, the reference voltage of the limiting amplifier 40 is set approximately at the center of the linear operating region, and this increases the gain of the limiting amplifier 40 for the noise. In Fig. 26B, V out represents the voltage amplitude of the output signal. Fig. 27A illustrates, in the case where the amplifiers BCa1 are multi-staged, the output data from the final stage amplifier, and the output signal of the ATC 10a of the final stage amplifier, in addition to the output signals from the top-hold circuit 20a and the bottom-hold circuit 30a of the final stage amplifier. In this figure, the ordinate represents voltage and abscissa represents time. When the multi-staged circuit of the amplifiers BCa1 receives a burst signal, the noise superimposed on the burst signal will be limited by the limiting amplifier 40. This situation, however, will be changed by the reset signal. More specifically, the reset signal will set the reference voltage of each amplifier at an optimum value that makes its gain maximum. In other words, the reset signal sets the reference voltage at the center of the linear operating region of the limiting amplifier 40, thereby establishing the maximum gain. This presents a problem in that the adverse effect of the noise will be increased during a signaless period from the occurrence of the reset signal to the input of a burst signal. Fig. 27B illustrates the relationships between the equivalent noise current density referred to input, and the output noise voltage, under the conditions that the output of the preamplifier (see, Fig. 2) is inputted to the amplifier BCa1 of the third embodiment as shown in Fig. 11, and that the dominant factor of the noise superimposed is white noise of the preamplifier. The output noise voltage V noise of the preamplifier is given by the following equation. V noise = A v × {F w × (Z in × I noise ) 2 } 1/2 where Av is the voltage gain of the preamplifier, Fw is a noise bandwidth, Zin is the input impedance of the preamplifier, I noise is the equivalent noise current density of the preamplifier referred to its input. The output noise voltage V noise takes a rather large value of 1.8 V when I noise = 1.5 pA/ Hz . In particular, since the amplifier BCa1 has a limiting function, the output voltage is saturated. This will further increase the ratio of the noise voltage V noise to the output voltage V out , thereby increasing the effect of the noise. Thus, the amplifier presents a problem in that the noise, which occurs during the signaless period from the reset signal occurrence to the burst signal input, is liable to be recognized as the start of the burst signal of the input data, and this may lead to bit errors. The following examples and embodiments are proposed to provide an amplifier that can prevent the bit errors during the signaless period from the reset signal occurrence to the burst signal input while receiving the input data including burst signals. This can be achieved by deviating the reference voltage of the amplifier from the linear operating region during the signaless period from the reset signal occurrence to the burst signal input. According to this, the output of the amplifier is maintained at a low level between consecutive burst signals, thereby preventing bit errors during the signaless period. Fig. 28A is a circuit diagram showing an amplifier 150 of an example not forming part of the present invention, and Figs. 28B and 28C are diagrams illustrating the operation of the amplifier 150. The amplifier 150, which includes an amplifier 151 and an ATC 170, receives the input data including a burst signal at the input terminal I1, and produces the output data from the output terminal O1. The amplifier 151 comprises an input terminal 161, to which the received data is applied, and a reference voltage input terminal 162, to which the reference voltage is applied. The amplifier 151 is a limiting amplifier which inversely amplifies the received data. The ATC 170 generates the reference voltage applied to the reference voltage input terminal of the amplifier 151. The ATC 170 includes a top-hold circuit T holding a maximum value of the received data, and generates the middle voltage between the fixed voltage of a fixed voltage source 180 and the maximum value held by the top-hold circuit T. The middle voltage is supplied to the reference voltage input terminal 162 of the amplifier 151 as the reference voltage. More specifically, a serial circuit of resistors R11 and R12 is connected between the output terminal of the top-hold circuit T and the fixed voltage source 180, and the connecting point of the resistors R11 and R12 is led out as an output terminal 173 of the ATC 170. Then, the output terminal 173 is connected to the reference voltage input terminal 162 of the amplifier 151. The input terminal 171 of the ATC 170 is connected to the input terminal I1 of the amplifier 150. One end of the serial circuit of the resistors R11 and R12 is led out as an output terminal 172 of the ATC 170, which is connected to the fixed voltage source 180. The top-hold circuit T of the ATC 170 has a reset terminal r, and the input and output signals of the top-hold circuit T are made equipotential when a reset signal is applied to the reset terminal r from the outside. Next, the operation of this example will be described. Fig. 28B illustrates waveforms of this example. As is shown in Fig. 28B, the output signal of the ATC 170, that is, the reference voltage of the amplifier 151 is set at a value lower than the signaless level (which is set at the center of the received data) during the signaless period from the occurrence of the reset signal to the input of the burst signal. Thus, the output data from the amplifier 150 is set at a low value during the signaless period because the amplifier 151 is an inverting limiting amplifier. The low value of the output data from the amplifier 150 during the signaless period can prevent bit errors between consecutive burst signals. As described above, the middle voltage between the output of the top-hold circuit T and the fixed voltage of the fixed voltage source 180 is generated from the voltage divider consisting of the resistors R11 and R12, and is supplied to the reference voltage input terminal 162 of the amplifier 151. In addition, since the top-hold circuit T follows maximum values of burst signals after it has been reset, the reference voltage applied to the reference voltage input terminal 162 of the amplifier 151 approaches an optimum value. Fig. 28C illustrates the output data from the amplifier 150 from the occurrence of the reset signal to the input of the burst signal. The fixed voltage of the fixed voltage source 180 is set at a value which is lower than the voltage at the input terminal I1 (signaless level) during the signaless period from the occurrence of the reset signal to the input of the burst signal, and which causes the output data from the amplifier 151 to take the low value as shown in Fig. 28C. Thus, the fixed voltage is determined considering the amplification factor of the amplifier 151, the resistances of the resistors R11 and R12, and the like. The resistances of the resistors R11 and R12 need not be the same: They can be selected at desired values as long as they suffice the condition that the output data from the amplifier 151 is set at the low value during the signaless period. Fig. 29A is a circuit diagram showing an amplifier 200 of another example not forming part of the present invention, and Fig. 29B is a diagram illustrating the operation of the amplifier 200. The amplifier 200, which includes an amplifier 210 and an ATC 220, receives the input data including a burst signal at the input terminal I2, and produces the output data from the output terminal 02. The amplifier 210 comprises an input terminal 211, to which the received data is applied, and a reference voltage input terminal 212, to which the reference voltage is applied. The amplifier 210 is a limiting amplifier which carries out a non-inverting amplification of the received data on the basis of the reference voltage. The ATC 220 generates the reference voltage applied to the reference voltage input terminal of the amplifier 210. The ATC 220 includes a bottom-hold circuit B holding a minimum value of the received data, and generates the middle voltage between the fixed voltage of a fixed voltage source 230 and the minimum value held by the bottom-hold circuit B. The middle voltage is supplied to the reference voltage input terminal 212 of the amplifier 210 as the reference voltage. More specifically, a serial circuit of resistors R21 and R22 is connected between the output terminal of the bottom-hold circuit B and the fixed voltage source 230, and the connecting point of the resistors R21 and R22 is led out as an output terminal 223 of the ATC 220. Then, the output terminal 223 is connected to the reference voltage input terminal 212 of the amplifier 210. The input terminal 221 of the ATC 220 is connected to the input terminal I2 of the amplifier 200. One end of the serial circuit of the resistors R21 and R22 is led out as an output terminal 222 of the ATC 220, which is connected to the fixed voltage source 230. The bottom-hold circuit B of the ATC 220 has a reset terminal r, and the input and output signals of the bottom-hold circuit B are made equipotential when a reset signal is applied to the reset terminal r from the outside. Next, the operation of this example will be described. Fig. 29B illustrates waveforms of this example. As shown in this figure, the output signal of the ATC 220, that is, the reference voltage of the amplifier 210 is set at a value higher than the signaless level of the received data (which is set at the center of the received data) during the signaless period from the occurrence of the reset signal to the input of the burst signal. Thus, the output data from the amplifier 200 is set at a low value during the signaless period. The low value of the output data from the amplifier 200 during the signaless period can prevent bit errors between consecutive burst signals. As described above, the middle voltage between the output voltage of the bottom-hold circuit B and the fixed voltage of the fixed voltage source 230 is generated from the voltage divider consisting of the resistors R21 and R22, and is supplied to the reference voltage input terminal 212 of the amplifier 210. In addition, since the bottom-hold circuit B follows minimum values of burst signals after it has been reset, the reference voltage applied to the reference voltage input terminal 212 of the amplifier 210 approaches an optimum value. The output data from the amplifier 200 from the occurrence of the reset signal to the input of the burst signal take the same waveform as shown in Fig. 28C. The fixed voltage of the fixed voltage source 230 is set at a value which is higher than the voltage at the input terminal I2 (signaless level) during the signaless period from the occurrence of the reset signal to the input of the burst signal, and which causes the output data from the amplifier 210 to take the low value as shown in Fig. 28C. Thus, the fixed voltage is determined depending on the amplification factor of the amplifier 210, the resistances of the resistors R21 and R22, and the like. The resistances of the resistors R21 and R22 need not be the same: They can be selected at desired values as long as they suffice the condition that the output data from the amplifier 210 is set at the low value. EMBODIMENT 6 Fig. 30A is a circuit diagram showing an amplifier 300 of an sixth embodiment in accordance with the present invention, and Figs. 30B and 30C are diagrams illustrating the operation of the amplifier 300. The amplifier 300, which includes an amplifier 310 and an ATC 320, receives the input data including a burst signal at the input terminal I3, and produces the output data from the output terminal O3. The amplifier 310 comprises an input terminal 311, to which the received data is applied, and a reference voltage input terminal 312, to which the reference voltage is applied. The amplifier 310 is a limiting amplifier which carries out an inverting amplification of the received data on the basis of the reference voltage. The ATC 320 generates the reference voltage applied to the reference voltage input terminal 312 of the amplifier 310. The ATC 320 includes the top-hold circuit T holding a maximum value of the received data, the bottom-hold circuit B holding a minimum value of the received data, and a clamping diode 340 whose anode is connected to the output of the bottom-hold circuit B, and whose cathode is connected to a fixed voltage source 330. The ATC 320 generates the middle voltage between the output voltage of the top-hold circuit T and the output voltage of the bottom-hold circuit B, and supplies it to the reference voltage input terminal 312 of the amplifier 310 as the reference voltage. More specifically, a serial circuit of resistors R31 and R32 is connected between the output terminal of the top-hold circuit T and the output terminal of the bottom-hold circuit B, and the connecting point of the resistors R31 and R32 is led out as an output terminal 323 of the ATC 320. Then, the output terminal 323 is connected to the reference voltage input terminal 312 of the amplifier 310. The input terminal 321 of the ATC 320 is connected to the input terminal I3 of the amplifier 300. One end of the serial circuit of the resistors R31 and R32 is led out as an output terminal 322 of the ATC 320, which is connected to the fixed voltage source 330. The top-hold circuit T and the bottom-hold circuit B of the ATC 320 have a reset terminal r, and the input and output signals of the top-hold circuit T and those of the bottom-hold circuit B are made equipotential when a reset signal is applied to the reset terminals r through a buffer amplifier. Next, the operation of this embodiment will be described. Fig. 30B illustrates waveforms of this embodiment. As shown in this figure, the output signal of the ATC 320, that is, the reference voltage of the amplifier 310 is set at a value lower than the signaless level of the received data (which is set at the center of the received data) during the signaless period from the occurrence of the reset signal to the input of the burst signal. This is carried out because the output of the bottom-hold circuit B is clamped by the clamping diode 340. Thus, the output data from the amplifier 300 is set at a low value during the signaless period because the amplifier 310 is an inverting limiting amplifier. The low value of the output data from the amplifier 300 during the signaless period can prevent bit errors between consecutive burst signals. In addition, since the top-hold circuit T follows maximum values of burst signals, and the bottom-hold circuit B follows minimum values of burst signals after they have been reset, the reference voltage applied to the reference voltage input terminal 312 of the amplifier 310 approaches an optimum value. Fig. 30C illustrates the output data from the amplifier 300 from the occurrence of the reset signal to the input of the burst signal in this embodiment. The fixed voltage of the fixed voltage source 330 is set at a value which is lower than the voltage at the input terminal I3 (signaless level) during the signaless period from the occurrence of the reset signal to the input of the burst signal, and which causes the output data from the amplifier 310 to take the low value as shown in Fig. 30C. Thus, the fixed voltage is determined depending on the amplification factor of the amplifier 310, the resistances of the resistors R31 and R32, and the like. The resistances of the resistors R31 and R32 need not be the same: They can be selected at desired values as long as they suffice the condition that the output data from the amplifier 310 is set at the low value. EMBODIMENT 7 Fig. 31A is a circuit diagram showing an amplifier 400 of a seventh embodiment in accordance with the present invention, and Fig. 31B is a diagram illustrating the operation of the amplifier 400. The amplifier 400, which includes an amplifier 410 and an ATC 420, receives the input data including a burst signal at the input terminal I4, and produces the output data from the output terminal O4. The amplifier 410 comprises an input terminal 411, to which the received data is applied, and a reference voltage input terminal 412, to which the reference voltage is applied. The amplifier 410 is a limiting amplifier which carries out a non-inverting amplification of the received data on the basis of the reference voltage. The ATC 420 generates the reference voltage applied to the reference voltage input terminal 412 of the amplifier 410. The ATC 420 includes the top-hold circuit T holding a maximum value of the received data, the bottom-hold circuit B holding a minimum value of the received data, and a clamping diode 440 whose cathode is connected to the output of the top-hold circuit T, and whose anode is connected to a fixed voltage source 430. The ATC 420 generates the middle voltage between the output voltage of the top-hold circuit T and the output voltage of the bottom-hold circuit B, and supplies it to the reference voltage input terminal 412 of the amplifier 410 as the reference voltage. More specifically, a serial circuit of resistors R41 and R42 is connected between the output terminal of the top-hold circuit T and the output terminal of the bottom-hold circuit B, and the connecting point of the resistors R41 and R42 is led out as an output terminal 423 of the ATC 420. Then, the output terminal 423 is connected to the reference voltage input terminal 412 of the amplifier 410. The input terminal 421 of the ATC 420 is connected to the input terminal I4 of the amplifier 400. One end of the serial circuit of the resistors R41 and R42 is led out as an output terminal 422 of the ATC 420, which is connected to the fixed voltage source 430. The top-hold circuit T and the bottom-hold circuit B of the ATC 420 have a reset terminal r, and the input and output signals of the top-hold circuit T and those of the bottom-hold circuit B are made equipotential when a reset signal is applied to the reset terminals r through the buffer amplifier. Next, the operation of this embodiment will be described. Fig. 31B illustrates waveforms of this embodiment. As shown in this figure, the output signal of the ATC 420, that is, the reference voltage of the amplifier 410 is set at a value higher than the signaless level of the received data (which is set at the center of the received data) during the signaless period from the occurrence of the reset signal to the input of the burst signal. This is because the output of the top-hold circuit T is clamped to the fixed voltage by the clamping diode 440. Thus, the output data from the amplifier 400 is set at a low value during the signaless period because the amplifier 410 is a non-inverting limiting amplifier. The low value of the output data from the amplifier 400 during the signaless period can prevent bit errors between consecutive burst signals. In addition, since the top-hold circuit T follows maximum values of burst signals, and the bottom-hold circuit B follows minimum values of burst signals after they have been reset, the reference voltage applied to the reference voltage input terminal 412 of the amplifier 410 approaches an optimum value. The waveform of the output data from the amplifier 400 from the occurrence of the reset signal to the input of the burst signal in this embodiment is the same as that shown in Fig. 30C. The fixed voltage of the fixed voltage source 430 is set at a value which is higher than the voltage at the input terminal I4 (signaless level) during the signaless period from the occurrence of the reset signal to the input of the burst signal, and which causes the output data from the amplifier 410 to take the low value as shown in Fig. 30C. Thus, the fixed voltage is determined depending on the amplification factor of the amplifier 410, the resistances of the resistors R41 and R42, and the like. The resistances of the resistors R41 and R42 need not be the same: They can be selected at desired values as long as they suffice the condition that the output data from the amplifier 410 is set at the low value. EMBODIMENT 8 Fig. 32A is a circuit diagram showing an amplifier 500 of a eighth embodiment in accordance with the present invention, and Fig. 32B is a diagram illustrating the operation of the amplifier 500. The amplifier 500, which includes an amplifier 510, an ATC 520, a transistor 530, and a buffer amplifier 540, receives the input data including a burst signal at the input terminal I5, and produces the output data from the output terminal O5. The amplifier 510 comprises an input terminal 511, to which the received data is applied, and a reference voltage input terminal 512, to which the reference voltage is applied. The amplifier 510 is a limiting amplifier which carries out a non-inverting amplification of the received data on the basis of the reference voltage. The ATC 520 generates the reference voltage applied to the reference voltage input terminal 512 of the amplifier 510. The ATC 520 includes the top-hold circuit T holding a maximum value of the received data, and the bottom-hold circuit B holding a minimum value of the received data. The ATC 520 generates the middle voltage between the output voltage of the top-hold circuit T and the output voltage of the bottom-hold circuit B, and supplies it to the reference voltage input terminal 512 of the amplifier 510 as the reference voltage. More specifically, a serial circuit of resistors R51 and R52 is connected between the output terminal of the top-hold circuit T and the output terminal of the bottom-hold circuit B, and the connecting point of the resistors R51 and R52 is led out as an output terminal 523 of the ATC 520. Then, the output terminal 523 is connected to the reference voltage input terminal 512 of the amplifier 510. The input terminal 521 of the ATC 520 is connected to the input terminal I5 of the amplifier 500. The top-hold circuit T and the bottom-hold circuit B of the ATC 520 have a reset terminal r, and the input and output signals of the top-hold circuit T and bottom-hold circuit B are made equipotential when a reset signal is applied to the reset terminals r through the buffer amplifier. The transistor 530 is an n-channel MOSFET, and the drain is connected to the output terminal of the non-inverting amplifier 510, the source is grounded, and the gate is connected to a reset terminal 53r, to which the reset signal is applied. Next, the operation of this embodiment will be described. Fig. 32B illustrates waveforms of this embodiment. An unstable operation of the ATC 520 at a reset will cause noise while a reset signal is applied to the reset terminal 53r, as shown at the top of Fig. 32B. The reset signal, however, turns on the transistor 530, thereby grounding the output terminal of the amplifier 510. Thus, the output data is forced to take the low value during the reset signal. This will eliminate the noise during the reset signal period as shown at the bottom of Fig. 32B. Although the waveform at the top of Fig. 32B is depicted as if the reset signal ended before starting to receive the burst signal, the end timing of the reset signal is set in such a manner that it approximately agrees with the start timing of receiving the burst signal, which is known beforehand. In other words, the reset signal is generated before starting to receive the burst signal by a predetermined number of bits, and is continued for the predetermined number of bits from the generation. This makes it possible to eliminate the amplitude noise during the signaless period from the occurrence of the reset signal to the start of receiving the burst signal. To accomplish this function, the reset signal, which is applied to the top-hold circuit T and the bottom-hold circuit B, may be applied to the gate of the transistor 530 after it is delayed by a certain amount of time. This will ensure that the noise, which is due to unstable operation of the ATC 520 after the reset, and may remain after the completion of the reset operation, is completely eliminated. The ATC 520 in Fig. 32A is the same as that of the third embodiment as shown in Fig. 11. The ATC 520 can be replaced with the combination of the ATC 170 and the fixed voltage source 180 as shown in Fig. 28A, with the combination of the ATC 220 and the fixed voltage source 230 as shown in Fig. 29A, with the combination of the ATC 320, the fixed voltage source 330 and the diode 340 as shown in Fig. 30A, or with the combination of the ATC 420, the fixed voltage source and the diode 440 as shown in Fig. 31A. In these cases, the end timing of the reset signal need not be set such that it agrees with the start timing of receiving the burst signal. That is, the reset signal may be ended before starting to receive the burst signal, because the noise due to the unstable operation of the ATC immediately after the reset is eliminated by the transistor 530, and the amplitude noise during the remainder of the signaless duration is eliminated by the operation described in the ninth to twelfth embodiments. EMBODIMENT 9 Fig. 33 shows the circuit of an amplifier 600 of a nineth embodiment in accordance with the present invention. The amplifier 600, which includes an amplifier 610, an ATC 620, a transistor 630, inverters 640 and 650, and a buffer amplifier 660, receives the input data including a burst signal at the input terminal I6, and produces the output data from the output terminal O6. The amplifier 610 is the same as the amplifier 510, and comprises an input terminal 611, to which the received data is applied, and a reference voltage input terminal 612, to which the reference voltage is applied. The amplifier 610 is a limiting amplifier which carries out a non-inverting amplification of the received data on the basis of the reference voltage. The ATC 620 is the same as the ATC 520, and generates the reference voltage applied to the reference voltage input terminal 612 of the amplifier 610. The ATC 620 includes the top-hold circuit T holding a maximum value of the received data, and the bottom-hold circuit B holding a minimum value of the received data. The ATC 620 generates the middle voltage between the output voltage of the top-hold circuit T and the output voltage of the bottom-hold circuit B, and supplies it to the reference voltage input terminal 612 of the amplifier 610 as the reference voltage. More specifically, a serial circuit of resistors R61 and R62 is connected between the output terminal of the top-hold circuit T and the output terminal of the bottom-hold circuit B, and the connecting point of the resistors R61 and R62 is led out as an output terminal 623 of the ATC 620. Then, the output terminal 623 is connected to the reference voltage input terminal 612 of the amplifier 610. The input terminal 621 of the ATC 620 is connected to the input terminal I6 of the amplifier 600. The top-hold circuit T and the bottom-hold circuit B of the ATC 620 have a reset terminal r, and the input and output signals of the top-hold circuit T and bottom-hold circuit B are made equipotential when a reset signal is applied to the reset terminals r through the buffer amplifier. The transistor 630 is a p-channel MOSFET, and the drain is connected to the output terminal of the non-inverting amplifier 610, the source is connected to the power supply VDD, and the gate is connected through an inverter 640 to a reset terminal 64r, to which the reset signal is applied. Next, the operation of this embodiment will be described. Major waveforms of this embodiment are the same as those of Fig. 32B. An unstable operation of the ATC 620 at a reset will cause noise while a reset signal is applied to the reset terminal 64r, as shown at the top of Fig. 32B. The reset signal, however, turns on the transistor 630, thereby clamping the output terminal of the amplifier 610 to VDD. Thus, the output data is forced to take the high value during the reset signal. This will eliminate the noise during the reset signal period as shown at the bottom of Fig. 32B. The end timing of the reset signal is set in such a manner that it approximately agrees with the start timing of receiving the burst signal, which is known beforehand. In other words, the reset signal is generated before starting to receive the burst signal by a predetermined number of bits, and is ended after that predetermined number of bits from the generation. This makes it possible to eliminate the amplitude noise during the signaless period from the occurrence of the reset signal to the start of receiving the burst signal. To accomplish this function, the reset signal, which is applied to the top-hold circuit T and the bottom-hold circuit B, may be applied to the gate of the transistor 630 after it is delayed by a certain amount of time. This will ensure that the noise, which is due to unstable operation of the ATC 620 after the reset, and may remain after the completion of the reset operation, is completely eliminated. The ATC 620 in Fig. 33 is the same as that of the third embodiment as shown in Fig. 11. The ATC 620 can be replaced with the combination of the ATC 170 and the fixed voltage source 180 as shown in Fig. 28A, with the combination of the ATC 220 and the fixed voltage source 230 as shown in Fig. 29A, with the combination of the ATC 320, the fixed voltage source 330 and the diode 340 as shown in Fig. 30A, or with the combination of the ATC 420, the fixed voltage source and the diode 440 as shown in Fig. 31A. In these cases, the end timing of the reset signal need not be set such that it agrees with the start timing of receiving the burst signal. That is, the reset signal may be ended before starting to receive the burst signal, because the noise due to the unstable operation of the ATC immediately after the reset is eliminated by the transistor 630, and the amplitude noise during the remainder of the signaless duration is eliminated by the operation described in the ninth to twelfth embodiments. When a plurality of amplifiers are connected in cascade as the amplifiers 610, 650 and 660 in Fig. 33, the transistor 630 or 530 may be connected to the input terminal of any one of the post stage amplifiers. In this case, the transistor 630 should be connected to the input terminal if the post stage amplifier is a non-inverting amplifier, and the transistor 530 should be connected to the input terminal if the post stage amplifier is an inverting amplifier. Furthermore, the above-described embodiments 6-9 and the examples not forming part of this invention shown in Figs. 28A - 29B are applicable to the final stage of the multi-staged configurations of Figs. 6 and 13. An amplifier having an automatic threshold control circuit (ATC, 10) and a limiting amplifier (40). The ATC (10) detects and holds a top value (peak value) and bottom value of an input signal, and outputs the middle value between the top and bottom values as a reference voltage. The limiting amplifier (40) amplifies the input signal in a linear operating region whose center is set at the reference voltage, thereby maintaining the output amplitude at a constant value. Even if the amplitude and the level of the input signals instantaneously changes by a large amount, the ATC can follow the change, so that the offset compensation and gain compensation of the amplifier can be achieved instantaneously. This makes it possible to continue producing the output of a constant amplitude with little phase deviations.

Claims: An amplifier comprising: a limiting amplifier (40) including a signal input terminal (a) and a reference voltage input terminal (d), amplifying an input signal applied to said signal input terminal (a), and producing a limited output signal in the case where the amplitude of the input signal is greater than a predetermined value, and the level of the input signal is within a predetermined range with regard to a reference voltage applied to the reference voltage input terminal (d); and an automatic threshold control circuit (10; 10a) supplying a reference voltage to a reference voltage input terminal (d) of said limiting amplifier (40) and comprising a top-hold circuit (20; 20a) for detecting and holding a top value of the input signal and a bottom-hold circuit (30; 30a) for detecting and holding a bottom value of the input signal; characterized in that said automatic threshold control circuit (10; 10a) further comprises a voltage divider (R1, R2) that produces a substantially middle value between the top value and the bottom value of the input signal as the reference voltage. An amplifier according to claim 1, characterized in that each of said top-hold circuit (20; 20a) and said bottom-hold circuit (30; 30a) comprises a reset signal terminal (r), and produces an output signal of substantially the same predetermined level when the top-hold circuit (20; 20a) and the bottom-hold circuit (30; 30a) are reset by a reset signal externally supplied to the reset signal terminals (r). An amplifier according to claim 2, characterized by further comprising a transistor, the drain of said transistor being connected to the signal input terminal or the output terminal of said limiting amplifier (40), the source of said transistor being connected to a common terminal, and the gate of the transistor being provided with the reset signal. An amplifier according to claim 3, characterized in that the reset signal is ended in accordance with a start timing of receiving the input signal. An amplifier according to any of the preceding claims, characterized in that said voltage divider (R1, R2) produces, as the reference voltage, a divided voltage between the output of said top-hold circuit (20; 20a) and a fixed voltage which is supplied from the outside, wherein voltages of the input terminal and output terminal of said top-hold circuit (20; 20a) are made substantially equal when said top-hold circuit (20; 20a) is reset by an external reset signal. An amplifier according to any of the claims 1 to 4, characterized in that said voltage divider (R1, R2) produces, as the reference voltage, a divided voltage between the output of said bottom-hold circuit (30; 30a) and a fixed voltage which is supplied from the outside, wherein voltages of the input terminal and output terminal of said bottom-hold circuit (30; 30a) are made substantially equal when said bottom-hold circuit (30; 30a) is reset by an external reset signal. An amplifying means comprising a plurality of amplifiers according to any of the preceding claims, characterized in that said plurality of amplifiers is connected in cascade. An amplifying means according to claim 7, characterized by further comprising a final stage amplifier according to any of claims 1 to 6, said final stage amplifier being connected to the output of the plurality of amplifiers connected in cascade. An amplifying means according to claim 7, characterized by comprising a delay circuit (81, 82) interposed between each consecutive two amplifiers of said plurality of amplifiers connected in cascade, so that said top-hold circuit (20; 20a) and said bottom-hold circuit (30; 30a) of each of said plurality of amplifiers are reset sequentially.

Inventors: AKAZAWA YUKIO, ISHIHARA NOBORU, ISHIKAWA MASAYUKI, NAKAMURA MAKOTO, AKAZAWA, YUKIO, ISHIHARA, NOBORU, ISHIKAWA, MASAYUKI, NAKAMURA, MAKOTO
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1994
Main classification: H03G7
IPC codes: H03G11, H03G1, H03G3