Memory array cell reading circuit

Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

Description: The present invention relates to a memory array cell reading circuit. As is known, in currently marketed nonvolatile memories, the array cells are read by comparing the content of the cells with the known content of a selected reference cell. More specifically, the cell to be read (together with other cells in the same column of the array) is connected to an array bit line, while the reference cell (normally a virgin or erased cell) is connected (possibly with other reference cells in the same column) to a reference line. Via a respective decoding circuit, the bit lines are connected to a current/voltage converter (hereinafter also referred to as an array converter) in turn connected to the supply. The decoding circuit (controlled by a decoding signal) provides for read-enabling, or not, a specific bit line by connecting or disconnecting it to/from the respective converter. The converter comprises a precharge circuit and a load connected in series, the node between which constitutes the output of the converter and is connected to one input of a sense amplifier, another input of which is connected to the output of a reference current/voltage converter located between the reference line and supply and presenting the same structure as the array converters. According to one known solution, the reference converter is the same as that of the array, except for the load which is doubled, and the reference and array converter loads are current mirror connected so that the current supplied to the cell to be read is half that of the reference cell. Reading therefore consists in a first precharging and equalizing step wherein the selected bit line (connected to the cell to be read) and the reference line are biased to a predetermined voltage, and the cell to be read and the reference cell are appropriately biased at the control terminal; and in a detecting step wherein the output of the comparator is read. At the equalizing step, the output voltage of the reference converter initially falls from the supply value to an intermediate reference value; whereas the output voltage of the array converters initially falls from the supply value to a low value. If the cell to be read is erased, the output voltage subsequently settles at a low value, below the reference value, due to the cell receiving less than the required current (as already stated, the current supplied to the cell to be read is half that of the reference cell). Conversely, if the cell to be read is written, it absorbs almost no current, and the output node switches to a high voltage approximating the supply voltage. The output voltage is therefore higher than the reference voltage in the case of a written cell, and is lower than the reference voltage in the case of an erased cell, thus permitting the comparator to distinguish between a written and erased cell once the output voltage of the current/voltage converters settles. In the above circuit, though essential for distinguishing between written and erased cells, the relationship between the reference and array currents is a disadvantage as regards reading speed. In the case of a written cell in fact, the increase, following the initial decrease, in the voltage at the output node of the array converter depends on the amount of current supplied. This being equal to half the reference current, the above known circuit is therefore slow and involves a certain time lapse for the output voltage of the converter to reach the correct value permitting reading of the cell. What is more, due to the slowness of the circuit, the speed with which the output voltage increases may be so slow as to prevent the reading of partially programmed (written) cells within the allotted time, with the result that the cell, though not actually defective and otherwise usable under enhanced speed conditions, must be rejected or redounded. It is an object of the present invention to provide a high-speed reading circuit designed to overcome the aforementioned drawback. According to the present invention, there is provided a memory array cell reading circuit as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a reading circuit in accordance with the present invention; Figures 2 and 3 show diagrams of the voltages at various points of the Figure 1 circuit in the case of a written and erased cell respectively. Number 1 in Figure 1 indicates a reading circuit comprising, in known manner, a number of array reading branches 2 (only one shown), and a reference branch 3. Array reading branch 2 comprises a precharge circuit 4 connected (via a decoding circuit not shown) to a number of bit lines 5 (only one shown); and bit line 5 is connected to a number of cells of which only cell 6 to be read at a given time is shown. Precharge circuit 4 is connected to a supply line 7 at voltage V DD via a load composed of a P-channel MOS transistor 8; and precharge circuit 4 and transistor 8 form a current/voltage converter, the output of which consists of the drain terminal of transistor 8 (node 9). Similarly, reference branch 3 presents a precharge circuit 10 connected to a reference line 11 in turn connected to a reference cell 12 or, like bit lines 5, to a number of reference cells in one column. The load is located between precharge circuit 10 and supply line 7, and in this case is composed of two P-channel MOS transistors 13, 15 of the same size and fabrication specifications as transistor 8, but diode-connected. In this case also, precharge circuit 10 and loads 13, 15 form a current/voltage converter, the output of which is formed by an intermediate node 16 between transistors 13, 15 and precharge circuit 10. More specifically, transistors 13, 15 present the gate terminals connected to each other, to the respective drain terminals, to the gate terminal of load transistor 8 of array branch 2, and to node 16. Node 16 of reference branch 3 and node 9 of array branch 2 are connected to respective inputs of a sense amplifier 17, the output 18 of which defines the output of circuit 1. The example described above presents one reference branch 3, and transistors 13, 15 provide for multimirror controlling the gate terminals of transistors 8 of each array reading branch 2 (one for each sense amplifier 17) by means of a simple solution with very little dissipation. Alternatively, a reference branch 3 may be provided for each sense amplifier 17, i.e. for each array reading branch 2. Array precharge circuit 4 comprises a cascode stage 20 interposed between node 9 and bit line 5; a pair of stabilizing transistors 21, 22 for preventing voltage overshooting on the bit line; and a fast precharge transistor 28. More specifically cascode stage 20 comprises a first native, i.e. low-threshold, N-channel transistor 25 connected at the drain terminal to node 9 and at the source terminal (node 23) to bit line 5; and a NOR gate 26 with a first input connected to bit line 5, a second input connected to a node 26a supplied with a logic signal ENM, and the output (node 27) connected to the gate terminal of transistor 25. A first stabilizing transistor 21 is a P type with the source terminal connected to node 9, the drain terminal connected to the output of NOR gate 26, and the gate terminal connected to a node 29 supplied with a logic signal BLDN. The second stabilizing transistor 22 is an N type with a grounded source terminal, the drain terminal connected to bit line 5, and the gate terminal connected to a node 30 supplied with a logic signal BLD opposite to BLDN. Fast precharge transistor 28, which is a native N-channel type, is connected at the drain terminal to V DD supply line 7, at the source terminal to node 9, and at the gate terminal to the output of NOR gate 26. Reference precharge circuit 10 presents the same structure as array precharge circuit 4, except for an extra-current branch 31. Reference precharge circuit 10 therefore presents a cascode stage 32; a first and second stabilizing transistor 33, 34; and a fast precharge transistor 39. Cascode stage 32 in turn comprises a native N-channel transistor 35 connected at the drain terminal to node 16, and at the source terminal (node 41) to reference line 11; and a NOR gate 36 with a first input connected to reference line 11, a second input connected to a node 37 supplied with a logic signal ENR, and the output (node 38) connected to the gate terminal of transistor 35. Transistor 33 is a P type with the source terminal connected to node 16, the drain terminal connected to node 38, and the gate terminal connected to a node 40 in turn connected to node 29 and therefore supplied with signal BLDN. Transistor 34 is an N type with a grounded source terminal, the drain terminal connected to reference line 11, and the gate terminal connected to node 30. Fast precharge transistor 39, which a native N-channel type, is connected at the drain terminal to V DD supply line 7, at the source terminal to node 16, and at the gate terminal to node 38. Extra-current branch 31 comprises an N type extra-current transistor 43 with the source terminal connected to reference line 11, the gate terminal connected to node 38, and the drain terminal grounded via a switch 44. The extra-current transistor is so sized that, upon biasing of reference line 11 by cascode stage 32, it absorbs a current approximating that of reference cell 12. More specifically, switch 44 is formed by an N-channel transistor with the source terminal connected to the drain terminal of extra-current transistor 43, a grounded drain terminal, and the gate terminal connected to node 30. The Figure 1 circuit operates as follows. Upon enabling of the equalizing step by signals ENM and ENR switching to low, signal BLD is high, so that, disregarding for the time being transistors 21, 22, 28, 33, 34, 39 and 43, cascode stages 20, 32 are enabled to bring bit line 5 and reference line 11 to a predetermined voltage, e.g. 1 V. More specifically, the formerly low outputs of gates 26 and 36 switch to high (lines 5 and 11 are discharged and grounded) thus turning on transistors 25 and 35 which connect load transistor 8 to line 5 and transistors 13, 15 to line 11; lines 5, 11 (which are capacitive) begin charging, and so raise the voltage at nodes 23, 41 and lower the voltage at nodes 9, 16. The increase in voltage at nodes 23, 41, and hence in the voltage supplied to gates 26, 36, is accompanied by a fall in voltage at the outputs of gates 26, 36, and hence in the voltage at the control terminals of transistors 25, 35, which therefore conduct less and tend to decouple nodes 9, 16 from nodes 23, 41 which therefore fall in voltage. In other words, at this step, as the voltage of lines 5, 11 increases, it is reduced by gates 26, 36 at least partly turning off transistors 25, 35; and, as the voltage of lines 5, 11 falls, it is increased by gates 26, 36 turning on transistors 25, 35 to a greater extent; this opposed combined action provides for achieving a balanced condition (bias) wherein transistors 25, 35 are turned on by no more than the amount required for ensuring a predetermined voltage of lines 5, 11. Fast precharge transistors 28, 39 provide for accelerating the above step, on account of load transistors 8, 13, 15 being fairly resistive and so having a current limiting effect preventing rapid charging of the bit line (and rapid attainment of the desired bias condition). To speed up charging of lines 5, 11 (which, as stated, are capacitive), low-resistance transistors 28, 39 are turned on initially to supply a high current, and, as the voltage at nodes 23, 41 increases, i.e. on nearing the desired bias condition, are turned off automatically by the output voltage of gates 26, 36 also increasing and so reducing the gate-source voltage drop of transistors 28, 39 until they are eventually turned off. Transistors 28, 39 are therefore only turned on at the very start of the equalizing phase for accelerating it. To ensure the desired bias condition is achieved, transistors 21 and 39 also provide for an auxiliary function, that of ensuring respective transistors 25, 35 are never turned off completely. In fact, in the absence of transistors 21 and 39, node 23 or 41 could possibly overshoot the predetermined level (e.g. on account of the intrinsic delay of cascode 20 or in the presence of undesired connections with other lines in the array) to the extent that the output of gate 26 (or 36) falls so low as to turn off transistor 25 (35) and bring node 9 (16) back to the voltage of supply line 7; in that case, sensing amplifier 17 could mistake an erased cell for a written one. This, however, is prevented by transistors 21, 39, which connect the output of gate 26 (36) to node 9 (16), to prevent the node from falling below a given level at which transistor 25 (35) is guaranteed to remain on. Transistors 22 and 34 also provide for preventing line 5 (11), should it be charged to too high a level, from turning off transistor 25 (35). For which purpose, any tendency of line 5 (11) to rise excessively, due to excess current from load 8 (13, 15), is counteracted by transistor 22 (34) (which is of small size) absorbing part of the surplus current. Transistors 22, 34 also provide for grounding bit line 5 and reference line 11 respectively when these are floating (when circuit 1 is not in read mode). Extra-current transistor 43 provides for rapidly bringing back up the voltage at output node 9 of the array branch in the event the cell to be read is written. As already stated, once the precharge (bias) condition of lines 5, 11 is achieved, a written cell 6 is nonconductive and therefore does not absorb the current supplied by load 8, so that the voltage at node 9 (output of array branch 2) increases once more to the supply voltage. Since the current supplied by array load 8 to bit line 5 is less than (half of) that supplied by reference loads 13, 15 to the bit line or at any rate requested by cell 6, the increase in the voltage at node 9, in the absence of transistor 43, would be slow by virtue of depending on the current supplied by load 8, so that a far from negligible time lapse would exist between the start of precharging and the output voltage reaching the steady-state value, thus slowing down reading as a whole. With the Figure 1 circuit, on the other hand, the increase in the output voltage at node 9 in the presence of a written cell is accelerated by transistor 43 which is kept on by switch 44 during initial precharging of lines 5, 11 and for a brief period as the voltage at node 9 settles, and which absorbs a current added to that absorbed by reference cell 12 and supplied by loads 13, 15. The total current supplied by loads 13, 15 is therefore greater than that required by reference cell 12, and more specifically each load 13, 15 supplies approximatively the current required by cell 12. Since the current supplied by each load 13, 15 is mirrored in array load transistor 8, the current supplied to bit line 5 approximates that of reference cell 12, so that, if cell 6 is written and nonconductive, the voltage at output 9, after falling to the predetermined voltage, is restored rapidly to a value approximating the supply voltage. The extra-current is only maintained for part of the settling phase of the voltage at output node 9. In fact, in the case of an erased, intead of a written, cell 6, the increase in the current supplied by load 8 produces an increase in the output voltage at node 9, which increase must be limited as far as possible to ensure a sufficient difference between the output voltage of the array and the reference voltage for safely discriminating between an erased and written cell. As such, transistor 43 is only kept on long enough to rapidly increase the output voltage at node 9 in the case of a written cell, and is turned off as soon as possible, by switching signal BLD to low. In the case of an erased cell 6, therefore, the output voltage at node 9 is maintained at all times below the reference voltage (voltage at node 16), and is then restored to its normal low level to permit correct comparison with the reference voltage. In other words, extra-current transistor 43 ensures that the ratio R 1 between the current I M supplied by load transistor 8 and the current I R requested by reference cell 12 during equalization is greater than the ratio R 2 between the same currents during evaluation. An example of the voltages obtainable in the Figure 1 circuit in the case of a written or erased cell 6 is shown in Figures 2 and 3 respectively, wherein the voltages at nodes 9, 16, 18, 23, 27, 38, 41 are respectively indicated V9, V16, V18, V23, V27, V38, V41. As shown in Figure 2 (relative to a written cell 6), following its initial fall, the voltage at output node 9 rises rapidly so that output voltage V18 reaches the steady-state value in advance as compared with known circuits. Conversely, in the case of an erased cell 6 (Figure 3), after falling and oscillating about a predetermined value, the voltage at output node 9 increases to an intermediate value higher than that of standard circuits (yet still lower than that of reference voltage V16); and, following switching of signal BLD (with a delay due to the intrinsic turn-off time of transistor 43), switches to its natural lower level. The delay with which the output voltage reaches its natural value in the case of an erased cell is in any case less than the advance provided for by the extra-current; and, bearing in mind that voltage V9 never exceeds reference voltage V16, the present circuit clearly provides for reading the output voltage V18 of sensing amplifier 17 in advance with respect to known circuits. The circuit described also provides for reading partially programmed cells which are slower than those programmed correctly, so that array output node 9 fails to reach the steady-stage value within the normally allotted read time, and which, with known circuits, were therefore rejected or redounded during evaluation. With the circuit described, on the other hand, by accelerating the voltage increase, the output voltage of such cells manages to reach the steady-state value within the allotted read time, thus permitting otherwise unusable cells to be salvaged. The circuit described therefore provides for a high degree of reliability by permitting reading of the cells even under less than optimum conditions involving atypically erased or written cells. Transistors 21, 22, 28 and 33, 34 in fact provide for precharging the bit and reference lines to the correct value even under such difficult conditions. In the case, for example, of an overerased, i.e. highly conductive, cell 6 resulting in an excessive fall in the voltage of bit line 5 and an increase in voltage at output 27 of gate 26, transistor 28 may be turned on again (due to the gate-source voltage drop being restored to a value greater than the threshold value) and so contribute towards the current supplied to cell 6, for arresting the fall in voltage on the bit line and achieving more stable voltage levels. Moreover, transistor 43 provides for a high degree of working stability, even at different supply voltages, by virtue of its control terminal being connected to node 38, the voltage of which (though subject to oscillation at the start of precharging) is fairly stable alongside variations in supply voltage. Clearly, changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention. In particular, other solutions may be provided for supplying the selected bit line with a higher current during precharging, and subsequently reducing the current to permit correct comparison of the output voltage of the selected cell with the reference voltage.

Claims: A memory array cell reading circuit (1) comprising at least one array branch (2) connected to at least one bit line (5); and a reference branch (3) connected to a reference line (11); said array branch comprising an array precharge circuit (4) and array loading means (8) each interposed between a first reference potential line (7) and said bit line (5), said reference branch comprising a reference precharge circuit (10) and reference loading means (13, 15) each interposed between said first reference potential line (7) and said reference line (11); said reference line (11) conducting a reference current (I R ), and said array loading means (8) generating an array current (I M ) lower than said reference current, at least during evaluation of said memory array; characterized in that it comprises current control means (43, 44) for so controlling said array loading means (8) as to generate a first value of said array current at the equalizing step, and a second value of said array current at said evaluation step; the ratio (R 1 ) between said first array current value and said reference current being greater than the ratio (R 2 ) between said second array current value and said reference current. A circuit as claimed in Claim 1, characterized in that said control means comprise a switchable current source (43). A circuit as claimed in Claim 2, characterized in that said switchable current source (43) is located in parallel to a reference cell (12) of known content, connected to said reference line (11). A circuit as claimed in Claim 3, characterized in that said switchable current source comprises an extra-current transistor (43) having a first and second terminal and a control terminal; said first terminal of said extra-current transistor being connected to said reference line (11); said second terminal being connected to a second reference potential line (ground); and said control terminal being connected to said reference precharge circuit (10). A circuit as claimed in Claim 4, wherein said reference precharge circuit (10) comprises a cascode stage (32) including a precharge transistor (35) interposed between said reference loading means (13, 15) and said reference line (11), and an inverting element (36) connected between a first terminal and the control terminal of said precharge transistor (35); characterized in that said control terminal of said extra-current transistor (43) is connected to said control terminal of said precharge transistor (35). A circuit as claimed in Claim 4 or 5, characterized in that it comprises controlled switch means (44) interposed between said second terminal of said extra-current transistor (43) and said second reference potential line (ground); said controlled switch means having a control terminal supplied with a logic open/close signal (BLD). A circuit as claimed in one of the foregoing Claims from 1 to 4, characterized in that said array precharge circuit (4) and said reference precharge circuit (10) each comprise a cascode stage (20, 32) including a precharge transistor (25, 35) and an inverting element (26, 36); said precharge transistor being interposed between said loading means (8, 13, 15) and said bit line (5) and said reference line (11) respectively; and said inverting element being connected between a first terminal and the control terminal of said precharge transistor. A circuit as claimed in Claim 7, characterized in that it comprises first array and reference stabilizing means (22, 34); said first array stabilizing means (22) being connected between said bit line (5) and said second reference potential line (ground); and said first reference stabilizing means (34) being connected between said reference line (11) and said second reference potential line. A circuit as claimed in Claim 8, characterized in that said first array and reference stabilizing means (22, 34) comprise a respective switchable transistor. A circuit as claimed in one of the foregoing Claims from 7 to 9, characterized in that it comprises second array and reference stabilizing means (21, 33); said second stabilizing means being connected between said respective loading means (8, 13, 15) and said control terminal of said respective precharge transistor (25, 35). A circuit as claimed in one of the foregoing Claims from 7 to 10, characterized in that said array and reference precharge circuits (4, 10) comprise a respective fast precharge transistor (28, 39) interposed between said reference potential line and an intermediate node (9, 16) between said loading means (8, 13, 15) and said precharge circuit (4, 10). A circuit as claimed in Claim 11, characterized in that said fast precharge transistor (28, 39) presents a control terminal connected to said control terminal of said precharge transistor (25, 35) of said precharge circuit (4, 10).

Inventors: GOLLA CARLA MARIA, MACCARRONE MARCO, PASCUCCI LUIGI, GOLLA, CARLA MARIA, MACCARRONE, MARCO, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G11C16
IPC codes: G11C16, G11C17