Gain-controlled solid-state image pickup device

Abstract: Photo-electric Conversion Apparatus A photo-electric conversion apparatus having a plurality of photo-electric conversion elements is provided with an amplifier which can externally control a gain thereof, at an output terminal of each of the photo-electric conversion elements.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photo-electric conversion apparatus e.g. used in an AE (Auto-Exposure) sensor or AF (Auto-Focus) sensor of a copying machine, a facsimile machine, a video camera recorder and a camera. Related Background Art As electronics technology has developed recently, high image resolution and high image quality have rapidly been realised in the field of a solid state image pick-up device used as a photo-electric conversion apparatus. An output of the solid state image pick-up device is rarely used as it is but it is processed in several stages before it is formed into a TV signal. Accordingly, when the number of pixels is increased to attain high resolution, a huge volume of operation and processing are required in the signal processing and the high image quality may be restricted by the signal processing. GB-A-2185654 discloses an array of photosensors for detecting a scanned laser beam reflected from an original. Because of the scanning action, the amount of light integrated by the photosensors for a uniform original varies according to the position of each sensor along the array. Several arrangements are proposed for compensating the output signals from the photosensors for this effect. In one case the array is divided into sets of consecutive sensor elements, each set having a respective signal amplifier, or alternatively a separate signal amplifier is provided for each photosensor. The gains of the different amplifiers are set at different levels, so as to provide the necessary compensation. WO-A-91/04633 discloses an array image sensor having an array of pixels laid out in rows and columns, and each vertical column of pixels is connected to a common bit line conductor which is connected to a respective analog switch sense amplifier. In one illustrated circuit for the sense amplifier, its gain is controlled by the value of a feedback capacitor. It is proposed that within the column sense amplifier automatic gain control may be used to improve black image quality. SUMMARY OF THE INVENTION According to the present invention there is provided photoelectric conversion apparatus as set out in claim 1. Optional features are set out in the remaining claims. A solid state image pick-up device embodying the invention produces signals multiplied by coefficients in order to build a signal processing function into the solid state image pick-up device. An embodiment of the present invention provides a photo-electric conversion apparatus comprising a plurality of photo-electric conversion elements and an externally gain controllable amplifier at an output terminal of each photo-electric conversion element, so that signal processing is provided by multiplying each signal by a desired coefficient. Other aspects and advantages of the present invention will be apparent from the claims, and from the following description of non-limiting embodiments and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a circuit configuration of a photo-electric conversion apparatus in accordance with an embodiment 1 of the present invention, Fig. 2 shows a timing chart for illustrating an operation of the embodiment 1 of the photo-electric conversion apparatus, Fig. 3 shows a circuit diagram of an amplifier used in the present invention, Fig. 4 shows a graph of a characteristic of the amplifier, Fig. 5 shows a circuit configuration of a photo-electric conversion apparatus in accordance with an embodiment 2 of the present invention, Fig. 6 shows a circuit configuration of a photo-electric conversion apparatus in accordance with an embodiment 3 of the present invention, Fig. 7 shows a circuit configuration of a photo-electric conversion apparatus in accordance with an embodiment 4 of the present invention, and Fig. 8 shows a circuit configuration of a photo-electric conversion apparatus in accordance with an embodiment 5 of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows a first embodiment of the present invention. In the present embodiment, bipolar photo-electric conversion elements are one-dimensionally arranged as photo-electric conversion elements, and base regions thereof are interconnected through PMOS transistors M 11 - M 14 . Amplifiers A1 - A4 are independently connected to respective emitter output lines of the photo-electric elements. An operation of the present embodiment is explained by referring to a timing chart of Fig. 2. At a time t 1 , a pulse of a low level is applied to  R so that the PMOS transistors M 11 - M 14 are turned on and the bases of the bipolar transistors B 1 - B 4 are connected in common and reset to V BR . Thereafter,  R rises to a middle level so that the PMOS transistors M 11 - M14 are turned off and the reset operation is terminated. At a time t 2 , a pulse  VC1 rises and the NMOS transistors M 21 - M 24 are turned on so that emitter terminals of all bipolar transistors B 1 - B 4 are reset to a voltage V VC1 and at a time t 3 , a pulse  R rises to a high level so that the base potentials of the bipolar transistors B 1 - B 4 are brought up through capacitors C 1 - C 4 and the base-emitter junctions is forwardly biased. Thus, the bipolar transistors simultaneously operate in an emitter follower mode and holes in the bases are recombined and the base potentials are settled around V VC1 + V BE (Transient reset operation). When the transient reset operation is terminated, at a time t 4 , the pulse  R falls to the middle level so that the base potentials of the respective bipolar transistors fall through the capacitors C 1 - C 4 and the base-emitter junction is reversely biased. From this state, an accumulation operation of the photo-carriers starts. After a predetermined accumulation time has elapsed, at the time t 5 , the pulses  T and  R rise to the high level so that the NMOS transistors M 31 - M 34 are turned on and the base potentials of the bipolar transistors B 1 - B 4 are brought up to forwardly bias the base-emitter junction. Thus, the photo-carriers accumulated on the bases are outputted from the emitter terminals. By applying predetermined voltages from a signal supply 2 to the control terminals of the amplifiers A 1 - A 4 , the respective amplifiers may have desired gains. The outputs of the amplifiers A 1 - A 4 are read to capacitors G 1 - G 4 , respectively, and at a time t 6 , the pulse  T falls to the low level so that the NMOS transistors M 31 - M 34 are turned off and the voltages on the respective capacitors G 1 - G 4 are maintained. At the time t 5 , the pulses  T and  R rise to the high level simultaneously. However, it is preferable that the pulse  T raises to the high level earlier than the pulse  R . Thereafter, at a time t 7 , a high level pulse is applied to  RES so that the NMOS transistor M RS is turned on, and after the output line 4 is reset, the scan circuit 1 is operated from time t 8 onwards to transfer the signals to the output terminal V OUT through the output buffer 3 starting from the signal on G 1 . A preferred embodiment of the amplifiers A1 - A4 and a DC characteristic thereof are shown in Figs. 3 and 4. Fig. 3 shows an inverting amplifier using an NPN transistor and a gain thereof is controlled by a gate voltage of an NMOS transistor connected to an emitter terminal. Calculation of a DC characteristic of the inverting amplifier is shown in Fig. 4. In Fig. 4, an abscissa represents an input voltage V IN and an ordinate represents an output voltage V OUT , and a graph is shown with the gain control voltage V C being used as a parameter. As seen from Fig. 4, the larger the V C is, the larger is the gain. Thus, it is suitable for the present invention because of its smaller circuit scale. Needless to say, other types of amplifier may be used. Fig. 5 shows a second embodiment of the present invention. The present embodiment is an improvement over the first embodiment in that the signal supply 2 is omitted and the gain control voltages of the amplifiers A1 - A4 are serially applied from a terminal V-GAIN. In operation, the scan circuit 1 is operated during the accumulation period and the pulse  WR rises to the high level, the NMOS transistor M51 is turned on so that the gain control voltage of the amplifier A1 is written from the terminal V-GAIN. Thereafter, the pulse L1 is set to the low level and M51 is turned off to hold the written voltage. This operation is sequentially carried out for the amplifiers A1 - A4, and thereafter the pulse  R is set to the high level so that the respective photo-electric conversion elements carry out the read operation and the voltages multiplied by the factors of the respective gains are stored in capacitors G 1 - G 4 . Other operations may be carried out in the same manner as those of Fig. 1. Accordingly, the space is significantly saved compared to case where the signal supply 2 is provided for each amplifier. In the above explanation of the operation, the control voltages of the amplifiers A1 - A4 are written during the accumulation period although they may be written in some other period, for example during the sequential transfer of the charges from capacitors G 1 - G 4 . In this case, the gain control voltages written in the amplifiers A1 - A4 are used in the next photo-electric conversion operation. Fig. 6 shows a third embodiment of the present invention. In the present embodiment, the second embodiment is developed to a two-dimensional photo-electric conversion apparatus. A vertical scan circuit 5 is provided to conduct serial resetting and signal reading of the photo-electric conversion elements row by row. The basic operation is identical to that of the second embodiment. Fig. 7 shows a fourth embodiment of the present invention. In the first to third embodiments, the photo-electric conversion apparatus the photo-electric conversion elements are bipolar transistors having the base-collector junctions used as the photo-diodes. In the present embodiment, MOS's are used. The like elements to those of the previous embodiments are designated by the like numerals and the explanation thereof is omitted. In a sensing unit 11, a photo-diode is connected to a gate of an MOS, and in a variable gain unit 10, a resistor of an MOS amplifier is a variable resistor which comprises a double structure MOS gate switch. A lower gate 12 of the MOS gate switch is floating, a first upper gate 13 is connected to a power supply, and a voltage pulse is applied to the second upper gate 14. The potential of the floating gate changes with the amplitude of the voltage pulse applied to the second upper gate 14 so that the MOS's of the amplifier 10 function as variable resistors. In the present embodiment, the photo signal generated by the photo-diode is amplified by the gain of the amplifier as determined by the variable resistor, and the modulated signal is sequentially read by a shift register via a read capacitor. While Fig. 7 shows the one-dimensional sensor, it should be understood that the present invention is not limited to the one-dimensional sensor but it may be applied to a two-dimensional sensor. A fifth embodiment of the present invention is shown in Fig. 8. S ij (ij = 1-2) comprises a base isolation PMOS 12, a base potential control capacitor 13 and a bipolar transistor 15. Cells S 11 and S 21 output to a vertical line 16, and cells S 12 and S 22 output to a vertical line 17. Line selection is conducted by pulses  PR1 and  PR2 . First, a high pulse is applied to  PR1 so that the cells S 11 and S 12 are selected, and the respective outputs are simultaneously read to the gates of the amplifiers a ij (i,j = 1,2). The gains of the amplifiers are adjusted by the vertically arranged signal supplies through wires 18, 19, 20 and 21, and the pulse  PT1 is set to the high level to read the photo output of the S 11 multiplied by the gain of the amplifier a 11 to the capacitor 22, the photo output of the S 12 multiplied by the gain of the amplifier a 12 to the capacitor 23, the photo output of the S 11 multiplied by the gain of the amplifier a 21 to the capacitor 24, and the photo output of the S 12 multiplied by the gain of the amplifier a 22 to the capacitor 25. The pulse  PR1 is then set to the low level and the pulse  PR2 is rendered to the high level so that the cells S 21 and S 22 are selected and they are read to the gates of the amplifiers a ij (ij = 1 - 2). The pulse  PT2 is set to the high level to read the photo output of the cell S 21 multiplied by the gain of the amplifier a 11 to the capacitor 26, the photo output of the cell S 22 multiplied by the gain of the amplifier a 12 to the capacitor 27, the photo output of the cell S 21 multiplied by the gain of the amplifier a 21 to the capacitor 28, and the photo output of the cell S 22 multiplied by the gain of the amplifier a 22 to the capacitor 29. The signals read to the capacitors 22, 23, 26 and 27 are summed through the capacitors 30, 31, 32 and 33 and outputted from the amplifier 38, and the signals read to the capacitors 24, 25, 28 and 29 are summed through the capacitors 34, 35, 36 and 37 and outputted from the amplifier 39. The outputs of the amplifiers 38 and 39 are substracted by a differential amplifier 40. Accordingly, the gains may include positive gains and negative gains so that Fourier transform output of the image can be read at a high speed. Using the above, and other analogous embodiments, the following technological advantages (1)-(4) can be attained since the sensor can output therefrom a signal on which various image processings, for example, convolution, edge output, Laplace transform, Fourier transform and wavelet transform, have been performed. (1) A photo-electric conversion apparatus can be formed on one chip, so that the cost of production can be reduced. (2) High-speed processing can be attained since processing can be done in a parallel operation on image data itself rather than on the serial output of the sensor. (3) A plurality of processings can be attained by one chip. (4) Image recognition and image discrimination can be attained functionally. Other types of photosensor element may be used, such as non-bipolar phototransistors, and the bipolar type phototransistor may be used without the base control capacitors C1, C2, C3, C4 (in which case accumulation and read-out from the phototransistor may be simultaneous).

Claims: Photo-electric conversion apparatus comprising: a) a plurality of photo-electric conversion elements (B, 11, S); b) a plurality of separate output lines each connected to receive an output signal from one or a plurality of said photo-electric conversion elements; c) a plurality of gain controllable amplifiers (A, 10), each said output line being connected to at least one said amplifier for amplifying the said output signals received by the output line, characterised in that each said amplifier has a terminal for receiving a respective gain control signal so that it amplifies the said output signals received by its respective output line by a gain controlled by the gain control signal, and in that the apparatus further comprises d) control means (2) common to the said plurality of amplifiers (A, 10) for supplying the respective gain control signals and thereby controlling the gains of said amplifiers, to perform a function other than AGC, where AGC is automatic gain control in response to the amplitudes of the output signals. Photo-electric conversion apparatus according to claim 1 further comprising storage means (G, 22-29) for storing said output signals after amplification by the amplifiers. Photo-electric conversion apparatus according to claim 2 wherein said storage means includes capacitors. Photo-electric conversion apparatus according to claim 2 further comprising read means (M41 - M44) for serially reading the signals of said storage means. Photo-electric conversion apparatus according to claim 4 wherein said read means is controlled by said control means. Photo-electric conversion apparatus according to claim 1, wherein each of said gain controllable amplifiers includes a transistor having a plurality of gate electrodes (12, 13, 14), including a floating gate electrode (12). Photo-electric conversion apparatus according to claim 1, further comprising processing means (38, 39, 40) for processing a plurality of output signals amplified by said gain controllable amplifier. Photo-electric conversion apparatus according to claim 7, wherein the control means controls the gains of the amplifiers in accordance with a processing operation of the processing means which processing operation is Fourier transform. Photo-electric conversion apparatus according to claim 7, wherein the control means controls the gains of the amplifiers in accordance with a processing operation of the processing means which processing operation is convolution, edge output, Laplace transform, or wavelet transform. Photo-electric conversion apparatus according to claim 1, wherein the possible gains of the said amplifiers, controlled by the gain control signals, include positive and negative gains. Photo-electric conversion apparatus according to claim 1 wherein said control means comprises means for supplying the respective gain control signals (V-GAIN) serially to the amplifiers. Photo-electric conversion apparatus according to claim 1 wherein said control means comprises means for supplying the respective gain control signals in parallel to the amplifiers. Photo-electric conversion apparatus according to claim 1 wherein the same said amplifier receives output signals from a plurality but not all of the said photo-electric conversion elements. Photo-electric conversion apparatus according to claim 1 wherein the same photo-electric conversion element provides output signals to a plurality of said amplifiers. Photoelectric conversion apparatus according to any one of the preceding claims, wherein the control means supplies the gain control signals during operation of the photoelectric conversion apparatus.

Inventors: MIYAWAKI MAMORU, UENO ISAMU, MIYAWAKI, MAMORU, UENO, ISAMU, MIYAWAKI, MAMORU, C/O CANON KABUSHIKI KAISHA, UENO, ISAMU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: H04N3
IPC codes: H04N3, H04N5, H04N1