Roll call circuit for semi-conductor memory

Abstract: A roll call circuit for a semiconductor memory having a plurality of redundant memory cells, comprises a circuit for cutting off a path for transferring a memory cell information to an output pad at the time of a roll call test, and another circuit for transferring the result of the roll call test to the path so that the result of the roll call test is outputted from the output pad at the time of the roll call test.

Description: Background of the Invention Field of the invention The present invention relates to a roll call circuit, and more specifically to a roll call reading circuit for a semiconductor memory having a plurality of redundant word lines or a plurality of redundant column lines. Description of related art Recent semiconductor memories are inclined to have a large storage capacity, and therefore, have an increased number of word lines and column lines. With this inclination, the recent semiconductor memories have redundant word lines and redundant column lines for lowering a fraction defective. Therefore, most of the semiconductor memories are provided with a roll call circuit for discriminating use or non-use of each redundant memory line (such as redundant word lines and redundant column lines) at the time of evaluating a product and of analyzing a defective product. Referring to Figure 1, there is shown a circuit diagram of one example of the conventional roll call circuit. The shown conventional roll call circuit includes a data-out buffer 12 for outputting data on an input/output pad I/O, a data amplifier 17 for amplifying data on a pair of complementary lines RWBST and RWBSN of an internal read/write bus so as to supply the amplified data to the data-out buffer 12, a sense amplifier data reading circuit 16 receiving a memory cell data from a sense amplifier (not shown in Figure 1) to supply the received memory cell data to the pair of complementary lines RWBST and RWBSN, and a roll call result reading circuit 15 for supplying a roll call discrimination result to the pair of complementary lines RWBST and RWBSN. Furthermore, the shown conventional roll call circuit includes a redundancy decoder 1 receiving internal address signals XADD 1 to XADD 9 which correspond to an X address supplied to external address input pins A 1 to A 9 (not shown), respectively. For example, if the X address supplied to the address input pin A 1 is "1", the signal XADD 1 is brought to a logical high level, or the X address supplied to the address input pin A 1 is "0" (zero), the signal XADD 1 is brought to a logical low level. Similarly, the signals XADD 2 to XADD 9 are brought to the logical high level or the logical low level in accordance with the value of the X address supplied to the address input pins A 2 to A 9 , respectively. This redundancy decoder 1 determines whether or not a redundancy word line should be selected. The shown conventional roll call circuit also includes an X decoder 6 receiving the signals XADD 1 to XADD 9 , an internal address signal XADD 0 brought to the logical high level or the logical low level in accordance with the value of the X address supplied to an external address input pins A 0 (not shown), and an output XRDS of the redundancy decoder 1. This X decoder 6 determines on the basis of its inputs XADD 0 , XADD 1 to XADD 9 , which of words lines should be selected. The shown conventional roll call circuit furthermore includes a roll call decoder 14 receiving the output XRDS of the redundancy decoder 1, a one-shot precharge signal YRD generated by an ATD generation circuit 9, and a signal RCLB. The one-shot precharge signal YRD generated by the ATD generation circuit 9 is used for precharging a dynamic circuit (not shown in Figure 1) incorporated in the roll call decoder 14. At the time of a roll call testing, the roll call decoder 14 generates an output RCSB on the basis of the result of the roll call testing The sense amplifier data reading circuit 16 includes a pair of transfer gates composed of N-channel transistors Tr 45 and Tr 46 , respectively, which are respectively connected between the pair of complementary lines RWBST and RWBSN and a pair of complementary data lines READT and READN from the sense amplifier, and a NOR gate NOR 3 for outputting a control signal to a gate of each of the transfer gate transistors Tr 45 and Tr 46 . The NOR gate NOR 3 has one input connected to receive an input signal BSLB and the other input connected to receive an output RCE of the roll call result reading circuit 15. The roll call result reading circuit 15 includes a NOR gate NOR 2 having one input connected to an output RCSB of the roll call decoder 14 and the other input connected to receive the signal RCLB, a transfer gate N-channel transistor Tr 43 connected between the line RWBSN and ground and having a gate connected to an output of the NOR gate NOR 2 , and another transfer gate N-channel transistor Tr 44 connected between a voltage supply line and the line RWBST and having a gate connected to the output of the NOR gate NOR 2 . The pair of complementary lines RWBST and RWBSN are clamped to a voltage supply voltage by means of a clamp circuit 13 formed of a pair of a gate-grounded P-channel transistors Tr 9 and Tr 10 connected between the voltage supply line and the pair of complementary lines RWBST and RWBSN, respectively. Now, operation will be described. First, an operation for reading a memory cell data is as follows: The signal RCLB is a test mode activation signal which is brought to the logical low level only when the roll call test is carries out. Therefore, at the time of reading the memory cell data, since signal RCLB is at the logical high level, the signal RCE is at the logical low level. Accordingly, during a low period of the input signal BSLB, the N-channel transistors Tr 45 and Tr 46 are ON, so that the sense amplifier data READT and READN are transferred to the lines RWBST and RWBSN, respectively, and therefore, amplified by the data amplifier 17 so as to outputted through the data-out buffer 12 to the input/output pad I/O. In this condition, since the signal RCE is at the logical low level, the N-channel transistors Tr 43 and Tr 44 are OFF, and therefore, no data is sent from the roll call result reading circuit 15 to the lines RWBST and RWBSN. The following is the operation of the roll call testing. At the time of the roll call testing, the signal RCLB is brought to the logical low level. Therefore, the data on the lines RWBST and RWBSN is determined by the level of the output signal RCSB of the roll call result reading circuit 14. If the output signal RCSB is at the logical low level, the signal RCE is brought to the logical high level, so that the N-channel transistors Tr 43 and Tr 44 are ON and the N-channel transistors Tr 45 and Tr 46 are OFF. Accordingly, the line RWBST is brought to the logical high level, and the line RWBSN is brought to the logical low level. This data is amplified by the data amplifier 17 and outputted through the data-out buffer 12 to the input/output pad I/O. If the output signal RCSB is at the logical high level, the N-channel transistors Tr 43 and Tr 44 are OFF and the N-channel transistors Tr 45 and Tr 46 are rendered ON during the logical low level period of the input signal BSLB. Accordingly, the sense amplifier data is transferred to the lines RWBST and RWBSN, and amplified by the data amplifier 17 so as to be outputted through the data-out buffer 12 to the input/output pad I/O. As mentioned above, at the time of a roll call testing, the roll call decoder 14 generates an output RCSB on the basis of the result of the roll call testing. Therefore, if the memory cell is previously written to the effect that the sense amplifier data READT is at the logical high level and the sense amplifier data READN is at the logical low level, the data outputted on the input/output pad I/O changes dependently upon whether the signal RSSB is at the logical high level or at the logical low level. Thus, if the roll call testing is carried out while changing the combination of the high level and the low level in the signals XADD 1 to XADD 9 , it is possible to discriminate, from the signal appearing on the input/output terminal I/O, use or non-use of the redundancy word line in accordance with the condition of XADD 1 to XADD 9 . Referring to Figure 2, there is shown a circuit of the roll call decoder 14 included in the conventional roll call circuit shown in Figure 1. The shown roll call decoder 14 includes an inverter INV 14 receiving the one-shot precharge signal YRD, a P-channel transistor Tr 48 having a gate connected to an output of the inverter INV 14 , and another P-channel transistor Tr 47 having a gate connected to receive the input signal RCLB. These transistors Tr 47 and Tr 48 are connected in series between the voltage supply line and a precharge node "N". The input signal RCLB is also applied to a gate of an N-channel transistor Tr 49 , which is connected between the precharge node "N" and ground. Another N-channel transistor Tr 50 , which has a gate connected to receive the output signal XRDS, is also connected between the precharge node "N" and ground. The precharge node "N" is connected to a cascaded inverters INV 15 and INV 16 , which operate to buffer a level on the precharge node "N" so as to generate the output RCSB. Now, operation of the roll call decoder 14 will be described. At the time of the roll call testing, since the input RCLB is the logical low level, the precharge node "N" is precharged to the voltage supply voltage level during the logical high level period of the one-shot precharge signal YRD. If the input signal XRDS is at the high level, a level on the precharge node "N" is determined by a resistance division ratio of the transistors Tr 47 , Tr 48 and Tr 50 . The inverter INV 15 is set or configured to have such a threshold that the inverter INV 16 outputs a logical high level as the output RSCB at this time. At a time other than the roll call testing, the input RCLB is at the logical high level, and therefore, the transistor Tr 49 is ON so that the precharge node "N" is fixed to a ground level. Here, if the redundancy word line is used, the XRDS is at the logical high level, and if the redundancy word line is not used, the XRDS is at the logical low level. Therefore, the roll call can be realized. In the above mentioned roll call circuit, since the sense amplifier data is read out when the roll call decoder output RCSB is at the logical high level, if there is a failure in the sense amplifier, in the memory cell and in a write circuit, there is possibility that the data outputted onto the input/output pad is inverted. Furthermore, since one roll call decoder and one roll call result reading circuit are required for each one redundancy word line, in the case that a plurality of redundancy word lines are provided, a required circuit area and the required number of signal lines are increased. To an extreme, there is possibility that the output line pairs RWBST and RWBSN, the data amplifiers, the data-out buffers and the input/output buffers become shortage. From EP-A-0 241 203 a memory device having redundant rows is known, where said device is provided with a repair detection circuit. It is further taught to include an AND gate for blocking the data during repair detection so as to output a test result to the output pad. Summary of the Invention Accordingly, it is an object of the present invention to provide a roll call circuit for a semiconductor memory, which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a roll call circuit for a semiconductor memory having a plurality of redundant word or column lines, which roll call circuit can perform the roll call test even if the semiconductor memory is a defective product having a defect in a memory cell. Still another object of the present invention is to provide a roll call circuit for a semiconductor memory having a plurality of redundant word or column lines, which roll call circuit can test use or non-use of the plurality of redundant word or column lines by use of one roll call decoder. The above and other objects of the present invention, as defined in detail in appended claim 1, are achieved in accordance with the present invention by a roll call circuit for a semiconductor memory having a plurality of redundant memory cells, the roll call circuit comprising a circuit for cutting off a path for transferring a memory cell information to an output pad at the time of a roll call test, and another circuit for transferring the result of the roll call test to the path so that the result of the roll call test is outputted from the output pad at the time of the roll call test. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of one example of the conventional roll call circuit; Figure 2 is a circuit diagram of the roll call decoder included in the conventional roll call circuit shown in Figure 1; Figure 3 is a circuit diagram of one embodiment of the roll call circuit in accordance with the present invention; Figure 4 is a circuit diagram of one example of the roll call decoder included in the roll call circuit shown in Figure 3; and Figure 5 is a circuit diagram of another example of the roll call decoder included in the roll call circuit shown in Figure 3. Description of the Preferred embodiments Referring to Figure 3, there is shown a circuit diagram of one embodiment of the roll call circuit in accordance with the present invention. In Figure 3, elements similar or corresponding to those shown in Figure 1 are given the same Reference Numerals or Signs. The shown embodiment includes a data-out buffer 12 for outputting data onto an input/output pad I/O, a data amplifier 11 for amplifying data on a pair of complementary lines RWBST and RWBSN of an internal read/write bus so as to supply the amplified data to the data-out buffer 12, a sense amplifier data reading circuit 8 receiving a memory cell data from a sense amplifier 20 to supply the received memory cell data to the pair of complementary lines RWBST and RWBSN, and a roll call result reading circuit 7 for supplying a roll call discrimination result to the pair of complementary lines RWBST and RWBSN. The sense amplifier 20 is coupled to a memory cell matrix including a number of memory cells 22 and a plurality of redundant memory cells 24, which are arranged in the form of a matrix having a plurality of rows and a plurality of columns. Furthermore, the shown embodiment includes four redundancy decoders 1, 2, 3 and 4 each receiving internal address signals XADD 1 to XADD 9 for determining whether or not a redundancy word line should be selected, an X decoder 6 receiving the signals XADD 1 to XADD 9 , another internal address signal XADD 0 and redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 outputted from the redundancy decoders 1, 2, 3 and 4, for the purpose of determining which of words lines should be selected. The shown embodiment also includes a roll call decoder 5 receiving the redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 of the redundancy decoders 1, 2, 3 and 4, the signal XADD 0 , an internal address signal YADD 0 , a one-shot precharge signal YRD generated by an ATD generation circuit 9, and a signal RCLB. The internal address signal YADD 0 is brought to the logical high level when "I" is given as a Y address or the logical low level when "0" is given as a Y address. The one-shot precharge signal YRD generated by the ATD generation circuit 9 is used for precharging a dynamic circuit (not shown in Figure 3) 'incorporated in the roll call decoder 5. At the time of a roll call testing, the roll call decoder 5 generates an output RCSB on the basis of the result of the roll call testing. The sense amplifier data reading circuit 8 includes a data amplifier 10 having a pair of complementary inputs connected to a pair of complementary data output lines READT and READN of the sense amplifier 20, respectively. A pair of complementary data outputs of the data. amplifier 10 are connected to a gate of two source-grounded N-channel transistors Tr 6 and Tr 8 , respectively. A transfer gate N-channel transistor Tr 5 is connected between the line RWBSN and a drain of the transistor Tr 6 , and an another transfer gate N-channel transistor Tr 7 is connected between the line RWBST and a drain of the transistor Tr 8 . The sense amplifier data reading circuit 8 also includes an NAND gate NAND 2 receiving the signal YRD and the signal RCLB, and a NOR gate NOR 1 receiving an output DEDB of the NAND gate NAND 2 and a signal BSLB and having an output connected to a gate of each of the transfer gate transistors Tr 5 and Tr 7 . The roll call result reading circuit 7 includes an N-channel transistor Tr4 having a drain connected to a high voltage supply voltage and a gate connected to an output RCSB of the roll call decoder 5, an inverter INV 3 receiving the output RCSB of the roll call decoder 5, a source-grounded N-channel transistor Tr 2 having a gate connected to an output of the inverter INV 3 , a transfer gate N-channel transistor Tr 1 connected between the line RWBSN and a drain of the transistor Tr 2 , and an another transfer gate N-channel transistor Tr 3 connected between the line RWBST and a source of the transistor Tr 4 . The roll call result reading circuit 7 further includes an inverter INV 1 receiving the signal RCLB, a NAND gate NAND 1 receiving an output of the inverter INV 1 and the signal YRD, and another inverter INV 2 having an input connected to an output of the NAND gate NAND 1 and also having an output DEDR connected to a gate of each of the transfer gate N-channel transistor Tr 1 and Tr 3 . The pair of complementary lines RWBST and RWBSN are clamped to the high voltage supply voltage by means of a clamp circuit 13 formed of a pair of a gate-grounded P-channel transistors Tr 9 and Tr 10 connected between the high voltage supply voltage and the pair of complementary lines RWBST and RWBSN, respectively. Now, operation will be described. First, the following is an operation for reading the memory cell data. Since the input signal RCLB is at the logical high level, the signal DEDB is brought to the logical low level during a high level period of the one-shot precharge signal YRD. Accordingly, when the input signal BSLB is at the logical low level, the transfer gate N-channel transistors Tr 5 and Tr 7 are turned ON, so that a voltage difference is created between the lines RWBST and RWBSN, as the result of an amplification function of the data amplifier 10 which amplifies the memory cell data from the sense amplifier 20. At this time, since the signal DEDR is at the logical low level, the transfer gate N-channel transistors Tr 1 and Tr 3 are OFF, and therefore, no data is transferred from the roll call result reading circuit 7 to the lines RWBST and RWBSN. The following is an operation in the roll call testing. Since the input signal RCLB is at the logical high level at the time of the roll call testing, the signal DEDR is brought to the logical high level during a period in which the one-shot precharge signal YRD is at a logical high level, so that the transfer gate N-channel transistors Tr 1 and Tr 3 are turned ON. Accordingly, a voltage difference is created between the lines RWBST and RWBSN in accordance with the condition of the output RCSB of the roll call decoder 5. On the other hand, since the transfer gate N-channel transistors Tr 5 and Tr 7 are OFF, the lines RWBST and RWBSN are isolated from the data amplifier 10. Therefore, even if the semiconductor memory is a defective product having a defect in the memory cell or the sense amplifier, it is possible to carry out the roll call testing. Referring to Figure 4, there is shown a circuit diagram of one example of the roll call decoder 5 included in the roll call circuit shown in Figure 3. The roll call decoder 5 includes an inverter INV4 receiving the one-shot precharge signal YRD, a P-channel transistor Tr 24 having a gate connected to an output of the inverter INV 4 , and another P-channel transistor Tr 23 having a gate connected to receive the input signal RCLB. These transistors Tr 23 and Tr 24 are connected in series between the high voltage supply voltage and a precharge node "N". The input signal RCLB is also applied to a gate of an N-channel transistor Tr 25 , which is connected between the precharge node "N" and ground. Furthermore, between the precharge node "N" and ground, there are connected four series circuits, each of which is composed of three series-connected N-channel transistors Tr 11 , Tr 12 and Tr 13 , Tr 14 , Tr 15 and Tr 16 , Tr 17 , Tr 18 and Tr 19 , or Tr 20 , Tr 21 and Tr 22 . A gate of the transistors Tr 11 , Tr 14 , Tr 17 and Tr 20 are connected to receive the signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 , respectively. A gate of the transistors Tr 12 and Tr 18 are connected to receive the signal XADD 0 , and a gate of the transistors Tr 15 and Tr 21 are connected to an output of an inverter INV 5 having an input receiving the signal XADD 0 . A gate of the transistors Tr 13 and Tr 16 are connected to receive the signal YADD 0 , and a gate of the transistors Tr 19 and Tr 22 are connected to an output of an inverter INV 6 having an input receiving the signal YADD 0 . The precharge node "N" is connected to an input of an inverter INV 7 , which has an output connected to an input of an inverter INV 8 , which generates the signal RCSB at its output. Now, operation of the roll call decoder 5 will be described. At the time of the roll call testing, since the input RCLB is the logical low level, the precharge node "N" is precharged to the high voltage supply voltage level during the logical high level period of the one-shot precharge signal YRD. At this time, if all of the three transistors (Tr 11 , Tr 12 and Tr 13 , Tr 14 , Tr 15 and Tr 16 , Tr 17 , Tr 18 and Tr 19 , or Tr 20 , Tr 21 and Tr 22 ) of one of the four series circuits are turned on, a level on the precharge node "N" is determined by a resistance division ratio of the transistors Tr 23 , Tr 24 and the three series-connected transistors all of which are in an ON condition. Therefore, the inverter INV 7 is set or configured to have such a threshold that the inverter INV 8 outputs a logical high level as the output RSCB at this time. In this embodiment, the four redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 are supplied to the roll call decoder 5. Each of these redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 selects a redundant word line independent of each other. If the redundant word line is used, a corresponding redundancy selection signal XRDS 1 , XRDS 2 , XRDS 3 or XRDS 4 is at the logical high level. Otherwise, the redundancy selection signal XRDS 1 , XRDS 2 , XRDS 3 or XRDS 4 is at the logical low level. For example, in order to know whether the redundancy selection signal XRDS 1 is at the logical high level or at the logical low level, it is sufficient if it is set to XADD 0 ="1" and YADD 0 ="1". Similarly, the level of the redundancy selection signals XRDS 2 , XRDS 3 and XRDS 4 can be known by controlling XADD 0 and YADD 0 . Here, whether the redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 are at the logical high level or at the logical low level, is determined by a combination of XADD 1 to XADD 9 . In other words, the use or non-use of the redundant word lines is determined independently of XADD 0 and the Y address. Accordingly, in order to know which of XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 is at the logical high level and which of XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 is at the logical low level, it is sufficient if the level of XADD 0 and YADD 0 are changed, with no necessity of dividing the input/output pad I/O. At a time other than the roll call testing, the input RCLB is at the logical high level, and therefore, the transistor Tr 25 is ON so that the precharge node "N" is fixed to a ground level. Referring to Figure 5, there is shown a circuit diagram of another example of the roll call decoder 5 included in the roll call circuit shown in Figure 3. The second embodiment of the roll call decoder 5 includes an inverter INV 9 receiving the one-shot precharge signal YRD, a P-channel transistor Tr 36 having a gate connected to an output of the inverter INV 9 , and another P-channel transistor Tr 35 having a gate connected to receive the input signal RCLB. These transistors Tr 35 and Tr 36 are connected in series between the high voltage supply voltage and a first precharge node "N 1 ". The input signal RCLB is also applied to a gate of an N-channel transistor Tr 37 , which is connected between the first precharge node "N 1 " and ground. The second embodiment of the roll call decoder 5 also includes a P-channel transistor Tr 39 having a gate connected to an output of the inverter INV 9 , and another P-channel transistor Tr 38 having a gate connected to receive the input signal RCLB. These transistors Tr 38 and Tr 39 are connected in series between the high voltage supply voltage and a second precharge node "N 2 ". The input signal RCLB is also applied to a gate of an N-channel transistor Tr 40 , which is connected between the second precharge node "N 2 " and ground. Furthermore, between the first precharge node "N 1 " and ground, there are connected two series circuits, each of which is composed of two series-connected N-channel transistors Tr 27 and Tr 28 or Tr 29 and Tr 30 . In addition, between the second precharge node "N 2 " and ground, there are connected two series circuits, each of which is composed of two series-connected N-channel transistors Tr 31 and Tr 32 or Tr 33 and Tr 34 . A gate of the transistors Tr 27 , Tr 31 , Tr 29 and Tr 33 are connected to receive the signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 , respectively. A gate of the transistors Tr 28 and Tr 32 are connected to receive the signal XADD 0 , and a gate of the transistors Tr 30 and Tr 34 are connected to an output of an inverter INV 10 having an input receiving the signal XADD 0 . In addition, the first precharge node "N 1 " is connected through a transfer gate N-channel transistor Tr 41 to an input of an inverter INV 12 , and the second precharge node "N 2 " is connected through a transfer gate N-channel transistor Tr 42 to the input of the inverter INV 12 . An output of the inverter INV 12 is connected to an input of another inverter INV 13 , which outputs the signal RCSB. A gate of the transistor Tr 41 is connected to receive the signal YADD 0 , and a gate of the transistor Tr 42 is connected to an output of an inverter INV 11 having an input receiving the signal YADD 0 . In this second embodiment, after the first and second precharge nodes "N 1 " and "N 2 " are simultaneously precharged, the level of the first and second precharge nodes "N 1 " and "N 2 " are determined in accordance with the redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 and XADD 0 , and one of the first and'second precharge nodes "N 1 " and "N 2 " is supplied to the inverter INV 12 through the transfer gates controlled by YADD 0 . In this embodiment, therefore, the level of the first and second precharge nodes "N 1 " and "N 2 " is determined by the resistance division ratio of the four transistors. Namely, since the number of the series-connected transistors is reduced, the ON resistance, of the transistors becomes small. In the above mentioned embodiments, XADD 0 and YADD 0 are used for selecting the redundancy selection signals XRDS 1 , XRDS 2 , XRDS 3 and XRDS 4 . However, it would be apparent to persons in the art to possible to use any address bits which are not supplied to the redundancy decoders. The above mentioned embodiments are applied to the roll call for the redundant word lines, but it would be apparent that the present invention can be applied to a roll call for redundancy column lines. As will be apparent from the above, since the roll call circuit in accordance with the present invention is constructed to output the roll call result without reading out the memory cell information, it is possible to carry out the roll call testing even if the semiconductor memory is a defective product having a defect in a memory cell. Furthermore, since the roll call circuit in accordance with the present invention is so constructed that a plurality of redundancy selection signals are supplied to one roll call decoder and decoded or selected by utilizing address bits which are influenced by the selection and non-selection of the redundant word or column lines, it is possible test use or non-use of the plurality of redundant word or column lines by use of the one roll call decoder. Therefore, it is possible to reduce the required circuit area and the required number of external pads. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A roll call circuit for a semiconductor memory having a plurality of memory cells including a plurality of redundant memory lines, the roll call circuit comprising: a first circuit (8) coupled to an output pad (I/O) during a condition other than a roll call test, for transferring a memory cell information (READT, READN) to said output pad, said first circuit (8) being separated from said output pad (I/O) at the time of the roll call test so that said memory cell information is not transferred to said output pad (I/O), and a second circuit (7) coupled to said output pad (I/O) at the time of the roll call test, for transferring a result of the roll call test to said output pad (I/O), characterized in that said second circuit (7) is controlled by a roll call decoder (5), which includes a precharge node (N) precharged to a first potential at the time of the roll call test, a first group of transistors (Tr 11 , Tr 12 ; Tr 27 , Tr 28 ) connected in series between said precharge node (N) and a second potential, one transistor (Tr 11 ; Tr 27 ) of said first group of transistors having a gate connected to a first redundancy selection signal (XRDS 1 ) activated when a corresponding first redundant memory line is used, another transistor (Tr 12 ; Tr 28 ) of said first group of transistors having a gate connected to a first internal address signal (XADD 0 ) selectively activated and deactivated in accordance with a first external address signal, and a second group of transistors (Tr 14 , Tr 15 ; Tr 31 , Tr 32 ) connected in series between said precharge node (N) and said second potential, one transistor (Tr 14 ; Tr 31 ) of said second group of transistors having a gate connected to a second redundancy selection signal (XRDS 2 ) activated when a corresponding second redundant memory line is used, another transistor (Tr 15 ; Tr 32 ) of said second group of transistors having a gate connected to a second internal address signal (YADD 0 ) selectively activated and deactivated in accordance with a second external address signal, said precharge node (N) being connected through a buffer circuit (INV 7 , INV 8 ; INV 12 , INV 13 ) as an output to said second circuit (7). A roll call circuit as claimed in claim 1 wherein said first and second internal address signals (XADD 0 ; YADD 0 ) are selectively activated and deactivated by address signals other than address signals that change when any one of said plurality of redundant memory lines is selected.

Inventors: KOSHIKAWA YASUJI, KOSHIKAWA, YASUJI
Applicants: NEC ELECTRONICS CORP, NIPPON ELECTRIC CO, NEC CORPORATION, NEC ELECTRONICS CORPORATION
Application year: 1994
Main classification: G06F11
IPC codes: G11C17, G11C11, G11C29