Nonlinear operation unit and data processing apparatus using the nonlinear operation unit

Abstract: A nonlinear operation unit includes nonlinear function operation means for receiving at least one input signal and performing the computing operation of the input signal by using a nonlinear function, multiplying means for multiplying the function value as the results of the computing operation by the nonlinear function operation means by a weight value, and adder means for adding together the results of the multiplying operations by the multiplying means and adding a threshold value to the sum.

Description: BACKGROUND OF THE INVENTION (Field of the Invention) The present invention relates to an apparatus for performing computing operations according to the neural network theory. More particularly, the invention relates to a nonlinear operation unit of simple circuit constructions and improved accuracy, and a data processing apparatus using the nonlinear operation units. (Discussion of the Prior Art) A neural-network basis apparatus having the functions of computing operations, storage, learning and the like has been realized by circuits and operation means, which are modeled on each neuron. The fact that most of the outputs of nerves become the inputs of other nerves has been well known. Also in the neural-network basis apparatus, the output signal of the circuit and the operation means, which are modeled on a neuron, frequently become the input signal of the circuit and operation means, which are modeled on another neuron. By convention, a neural network is constructed by combining those neuron circuits and operation means. Accordingly, the neural network includes the neuron circuits and operation means, which are necessary for forming each neuron but are omissible in light of constructing the overall network. In other words, the conventional neural network must include unnecessary circuits and operation means. The neuron linearly multiplies the signals from other neurons in accordance with a strength of bonding of synapses for transferring the signals, adds the results of multiplying operations from the synapses of the neuron to the threshold value of the neuron, and transfers the output signals, which are equivalent to the results of the process carried out by the nonlinear function, to other neurons, through the synapses. The conventional art constructs the neuron circuits and operation means in a similar order. An example of this is described in "High-Speed Analog Neural Network LSI for Neuro Processing Type Light Demultiplexes", Electric/Electronics/Information/Communication Academy NC90-53 (Article 1). The synapses of each neuron are constructed by a circuit corresponding to a linear multiplier circuit, invented by Gilbert and disclosed in Japanese Patent Laid-Open Publication No. Sho. 48-20932 (Article 2). The output currents of the synapses are added together. Then, a nonlinear characteristic is gained by a differential amplifier. The current is converted into a corresponding voltage, which is then used as an output signal of the neuron. A neural circuitry based on the neural circuitry theory is constructed by connecting the circuits modeled on the neurons. When carefully studying the Gilbert multiplier circuit, it is seen that the multiplier circuit is made up of a multiplier core circuit and a circuit for correcting the nonlinearity of the multiplier core circuit. These circuits each include a circuit for converting a voltage difference into a current difference. Generally, this voltage-to-current converting circuit suffers from an appreciable error. The circuit including diode-connected transistors also suffers from an appreciable error arising from a variation of the characteristics of the elements, which is caused during the manufacturing process. Therefore, it is impossible to perfectly correct the nonlinearity of the multiplier core circuit. The Gilbert multiplier circuit is attendant with an error, although appreciable. For this reason, an error owing to the nonlinearity is observed in the multiplier characteristic, as described on page 87, Fig. 5 in the article 2. The nonlinear function circuit using the differential amplifier, which is connected to the output of the multiplier circuit, also causes an error. The nonlinear function circuit is influenced by temperature of the elements. The input sensitivity of the circuit is proportional to absolute temperature. Consequently, the characteristic of the overall neural network also varies. When a signal passes through multiple stages of circuits, the error is accumulated to increase. In an extreme case, it is almost impossible to realize desired functions. The computing operation of a nonlinear function is performed at the output of another neuron. If this computing operation is performed in the synapses, it little affects the operation of an overall neural network, when taking account of the fact that most of the output signal of a neuron become the input signal to another neuron. A non-linear operation unit as specified in the pre-characterising part of claim 1 is known from document Regelungstechnik und Prozeß-Datenverarbeitung, vol. 18, no. 11, November 1970, pages 500 to 503. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and has as object to simplify the units corresponding to nerves and to obtain a high speed computing operation, while keeping the operation of an overall neural network unchanged. Another object of the present invention is to provide a simple analog circuit of the unit corresponding to each nerve, and to reduce errors arising from temperature variation and the circuits per se, and computing time. These objects are achieved by the subject-matter of claim 1. Preferred embodiments are defined in dependent claims 2 to 9. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description, serve to explain the objects, advantages and principles of the invention. In the drawings, Fig. 1 is a block diagram showing a nonlinear operation unit according to an embodiment of the present invention; Fig. 2 is a block diagram showing an arrangement with the function of an exclusive OR, which is the combination of two nonlinear operation units shown in Fig. 1; Fig. 3 is a block diagram showing a nonlinear operation unit according to another embodiment of the present invention. Fig. 4 is a block diagram showing a circuit, constructed with one nonlinear operation unit of Fig. 3, for obtaining the derivative of a hyperbolic tangent function; Fig. 5 is a block diagram showing a nonlinear operation unit for performing the operation of an equation (6); Fig. 6 is a block diagram showing a circuit, constructed with two nonlinear operation units of Fig. 5, for performing an exclusive OR operation; Fig. 7 is a block diagram showing another nonlinear operation unit for performing the equation (4); Fig. 8 is a block diagram showing a circuit, constructed with one nonlinear operation unit of Fig. 7, for obtaining the derivative of a hyperbolic tangent function; Fig. 9 is a block diagram showing an exclusive OR circuit using two nonlinear operation units shown in Fig. 5, in which all the values during the computing process are real numbers and the nonlinear function includes a monotonous function of bounded type; Fig. 10 is a block diagram showing an exclusive OR circuit using two nonlinear operation units shown in Fig. 7, in which all the values during the computing process are real numbers and the nonlinear function includes a logistic function as a monotonous function of bounded type; Fig. 11 is a block diagram showing a general binary function operation unit using two nonlinear operation units shown in Fig. 7, in which the weights and threshold values may be properly set; Fig. 12 is a circuit diagram of the nonlinear operation unit shown in Fig. 7 constructed using three terminal amplifier elements, such as electron tubes, junction type field effect transistors, and bipolar transistors; Fig. 13(a) is a circuit diagram showing a nonlinear function operation circuit realized by a differential amplifier constructed using bipolar transistors; Fig. 13(b) is a graph showing the characteristic of the differential amplifier of Fig. 13(a); Fig. 14 is a circuit diagram of the nonlinear operation unit shown in Fig. 7 constructed using three terminal amplifier elements, such as electron tubes, junction type field effect transistors, and bipolar transistors; Fig. 15(a) is a circuit diagram showing a nonlinear function operation circuit realized by combining two differential amplifiers constructed using bipolar transistors; Fig. 15(b) is a graph showing the characteristic of the differential amplifier of Fig. 15(a); Fig. 16 is a circuit diagram showing a nonlinear operation unit constructed using three nonlinear function operation circuits of Fig. 15(a); Fig. 17 is a graph showing the temperature characteristic of a sigmoid synapsis circuit; Fig. 18(a) is a circuit diagram showing a temperature compensating circuit constructed with the preamplifier; Fig. 18(b) is a graph showing the input-to-output voltage characteristic of the circuit shown in Fig. 18(a) with a parameter of the temperature; Fig. 18(c) is a circuit diagram showing the nonlinear operation unit of Fig. 16 including temperature compensating means; Fig. 19(a) is a circuit diagram showing a constituent element of the embodiment of the present invention, which additionally includes a circuit for modulating the weight in accordance with the absolute temperature of differential amplifier circuits; Fig. 19(b) is a circuit diagram showing an amplifier circuit of which the amplification factor is proportional to absolute temperature; Fig. 19(c) is a circuit diagram showing an amplifier circuit of which the amplification factor is inversely proportional to absolute temperature; Fig. 20 is a block diagram showing a network containing temperature compensating circuits; Fig. 21(a) functionally illustrates the nonlinear function operation circuit of Fig. 19; Fig. 21(b) is a graph showing the temperature characteristic of the weight multiplying section; and Fig. 22 is a block diagram for explaining the neutralizing operation of the temperature characteristics in the network structure circuit of Fig. 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before preceding with the detailed description of the invention, major technical ideas of the present invention to achieve the above objects and the operations of the invention will briefly be described. A nonlinear operation apparatus of the invention comprises: nonlinear function operation means (11a to 11n in Fig. 1 and 31a to 31n in Fig. 3) for receiving at least one input signal and performing the computing operation of the input signal by using a nonlinear function (g(uj)); multiplying means (2a to 2n in Fig. 1 and 32a to 32n in Fig. 3) for multiplying the function value as the results of the computing operation by said nonlinear function operation means by a weight value (wji); and adder means (13 in Fig. 1 and 33 in Fig. 3) for adding together the results of the multiplying operations by said multiplying means and adding a threshold value to the sum. If required, the threshold value (i) is set at 0 and a means for adding the threshold value may be omitted. In this specification, the term "weight" represents a value, optionally set, to be multiplied by the result of the nonlinear computing operation. The weight corresponds to "weight" or "strength of bonding" in the neural network. The term "threshold value" indicates a value, optionally set, to be added to the sum of the results of the multiplying operation, and corresponds to "threshold value" in the neural network. In the neural network theory, the output xi of a neuron i is given by xi = g(ui) ui = Σj {wji•xj} + i where ui : inner potential of a nerve neuron i wji : strength of bonding of a nerve neuron j to another nerve neuron i i : threshold value of the nerve neuron i g : logistic function of real number - real number xj : output potential of the neuron j The conventional circuit modeled on the neuron in the neural network, which computes the equations (1) and (2), is made up of a multiplier section for multiplying an input signal xj and a weight value wji, an adder section for adding together the results of multiplications by the multiplying section, and a section for computing the output signal of the adder section by a nonlinear function g(ui). The present invention provides such a circuit for computing an equation (4) to be given later. The operation of a network constructed with the circuits of the invention as unit cells is equivalent to the operation of an overall neural network. The output signal of a neuron j is given by xj = g(uj) where uj : internal potential of the nerve neuron j. Therefore, the internal potential of the neurons j is expressed as uj = Σi {wji•g(ui)} + j In the present invention, as seen from the equation (4), each input uj is computed by using a nonlinear function g. The result of each computation is multiplied by a weight wji, which corresponds to the strength of bonding. The results of the multiplying operations are summed. A threshold value j of the neuron is added to the sum. The result is the internal potential. Also in another neuron, there is no need of computing a value corresponding to the output potential since the computing operation is based on the inner potential of another neuron. In the equation (4), the threshold value j may be set at 0, as described above. A nonlinear operation apparatus according to another embodiment of the present invention comprises nonlinear function operation means (71a to 71n in Fig. 7) for performing the computing operation of a function (f(wji, uj)), which produces the results of operations equivalent to the results of the process carried out by computing at least one input signal (uj) by using a nonlinear function, and multiplying the results of the computing operations by weight values (wji), and adder means (72 in Fig. 7) for adding together the results of the computing operations by the nonlinear function operation means and adding a threshold value to the sum of these results. If required, the threshold value (i) is set at 0 and a means for adding the threshold value may be omitted (Fig. 5). In the specification, the terms "nonlinear function operation means" or "nonlinear function operation section" means a means for performing a nonlinear operation alone, and also a means for performing a function, which produces the results equivalent to the results of the nonlinear operation and the multiplying operation. A function f of real number * real number → real number is defined as follows: f(w, u) = w•g(u) The internal potential of each neuron can be written using the function f ui = Σj {f(wji, uj)} + i When using the function f as defined above, the internal potentials of all the neurons in a neural network can be obtained not computing the output potentials of the neurons. In a normal apparatus based on the neural network theory, the input signal to a neuron and the output signal to another neuron are expressed in terms of the output potential of the neuron. In the invention, the internal potential of the neuron is used for the input signal from exterior and the output signal to exterior. As in the embodiment to be given later, a desired input/output relation can be obtained without converting it into the output potential of the neuron. In the present invention, a function value is obtained using a function (wji, uj), which produces the results of operations equivalent to the results of the process carried out by computing each input signal uj by using a nonlinear function, and multiplying the result of the computation by the weight wji corresponding to the strength of bonding. The results of the computing operations are summed and added to the threshold value i. In this way, the internal potential of the neuron is obtained. The function can be obtained by a digital computer apparatus, but it can easily be realized by a apparatus including an analog circuitry. When it is realized using the digital computing apparatus, complexes can be handled in the computing process. Where the real numbers are used for all the values during the computing process, design of an actual apparatus is easy. In the digital computer, general methods to represent the real numbers are floating-point representation and the fixed-point representation, both being of the fixed accuracy type. The values represented by the methods are contained in the finite subset of real numbers. In embodying the invention, if the real numbers are used for the inputs, computing process, and outputs, and the finite subset of real numbers that can be handled by a digital computing apparatus is used for at least a part of the computing process, the results of computation are within a tolerable difference. Thus, if the accuracy is limited, and a part or the whole of the computing process is carried out by the digital computing apparatus, the results of computing operations can be obtained as desired. In another approach, a part of the computing process is carried out by a digital computing apparatus, using the finite subset, the remaining computing process is carried out by an analog computing apparatus. In this case, the quantities of the type in which the real numbers cannot be expressed by the digital computing apparatus may be expressed by continuous quantities, such as time and volume. In an additional approach, the real numbers of the inputs, computing process, outputs are expressed in terms of current or voltage proportional to the real numbers. The current or voltage is processed by analog electronic circuit means. In one preferred mode of the present invention, the nonlinear function operation means is expressed by an analog electronic circuit. The analog electronic circuit includes differential amplifier circuits. Each differential amplifier circuit consists of a pair of amplifier elements each having at least three terminals (for example, 3-terminal amplifier elements such as bipolar transistors, field effect transistors, and pentode electrode tubes, and amplifier elements of four or more terminals, such as multi-gate transistors and multielectrode tubes). The paired amplifier elements are coupled with each other at the first terminals (for example, the emitters of the bipolar transistors, the sources of the field effect transistors, and the cathodes of the electron tubes). A voltage difference proportional to the input signal is applied to between the second terminals (bases of the bipolar transistors, the gates of the field effect transistors, and the grids of the electron tubes) of the paired amplifier elements each having at least three terminals and constituting the differential amplifier circuits. A current proportional to the weight, which is used for obtaining the product, is fed to the first terminals (emitters, sources, and the cathodes). As a result, an output signal is produced as a current difference at the third terminals (collectors of the bipolar transistors, the drains of the field effect transistors, and the plates of the electron tubes) of the differential circuit. In a specific example of the differential amplifier using the bipolar transistors (Fig. 13), the difference I C1 - I C2 between the collector currents I C1 and I C2 of each transistor is expressed I C1 - I C2 = I E •tanh((V B1 - V B2 )/2V T ) This circuit can produce a current difference proportional to the product of multiplying a function value that is obtained by applying a hyperbolic tangent function as a logistic function to the input voltage difference by the emitter total current I E . This characteristic may be functioned as means for producing the operation results equivalent to the products of multiplying the function values, which are obtained by computing the input signals by using the nonlinear function, by weight values. If I E is set at a fixed value, it may be operated as means for obtaining the function values of a nonlinear function of each input signal. To change the sign of weight, the nonlinear function operation means comprises: (1) a first differential amplifier circuit (151 in Fig. 15) including first and second amplifier elements of at least three terminals being connected to each other at the first terminals (emitters, sources or cathodes); (2) a second differential amplifier circuit (152 in Fig. 15) including third and fourth amplifier elements of at least three terminals being connected to each other at the first terminals (emitters, sources or cathodes); wherein the second terminals (bases, gates, or grids) of the first and fourth amplifier elements of at least three terminals are connected to form a first input terminal (Vin1), the second terminals of the second and third amplifier elements of at least three terminals are connected to form a second input terminal (Vin2), a voltage proportional to the input signal is applied to between the first and second input terminals, the third terminals (collectors, drains, and plates) of the first and third amplifier elements of at least three terminals are connected to form a first output terminal (Ioutl), the third terminals of the second and fourth amplifier elements of at least three terminals are connected to form a second output terminal (Iout2), a current difference (I E1 - I E2 ) proportional to the weight value is supplied to the first terminals of the first second differential amplifier circuits, whereby a current difference (Iout1 - Iout2) proportional to the product of multiplying a positive or negative value and the result of processing the input signal by a bounded, monotonous function is produced at the first and second output terminals. A specific example of the differential amplifier circuit of at least three terminals, constructed using bipolar transistors, is as shown in Fig. 15. As shown, the collectors of the transistors Q3 and Q5 are connected to each other, and the total collector current is Ioutl. The collectors of the transistors Q4 and Q6 are connected to each other, and the total collector current is Iout2. The difference of the total currents is expressed by Iout1 - Iout2 = (I E1 - I E2 )•tanh((Vin1 - Vin2)/2V T ) The circuit described above is the circuit constructed using the bipolar transistors. The circuit having the characteristics of the bounded, monotonous function and the multiplication, can be achieved by another 3-terminal amplifying elements of nonlinear characteristics, such as field effect transistors generally operating as balanced modulators, electron tubes having the remote cut-off characteristic, electron tubes having variable µ characteristics. In the case where continuous values during the computing process are handled in the form of current or voltage, as described above, an error is generally caused. Some type of the error is influenced by disturbance. When real numbers are expressed in terms of voltage using a semiconductor electric circuit, the voltage is often varied by ambient temperature. A measure can be taken for such a disturbance by using means for measuring the quantity of disturbance. If a correcting means to reduce the influence by the disturbance, which is used depending on the quantity of disturbance, is known, the influence of the disturbance can be reduced by using that means. This can be applied to a circuit where the learning is performed and another circuit where the learning is not performed (to be described later). The nonlinear operation unit of the invention comprises: first means (182, 185, 188 in Fig. 18) for detecting an intensity of disturbance; second means (183, 186, 189 in Fig. 18(c)), located at the inputs, for changing the weight values and threshold values so as to reduce the influence by the disturbance, in accordance with the disturbance intensity obtained by the first means. Particularly when the disturbance is due to temperature, the quantity of the disturbance, i.e., temperature, is easy. And the influence by temperature can be predicted, and also be corrected. The influence by temperature comes in two cases. In the first case, the influence by the disturbance is proportional to the absolute temperature. In the second case, it is inversely proportional to the absolute temperature. Let us consider a case where the nonlinear function f is inversely proportional to the absolute temperature, and it varies according to the following equation ft. ft = f((t0/t)•x) where ft(x) : actual function value of the function f(x) at absolute temperature t t0 : reference temperature at which ft(x) = f(x) holds. The ft may be corrected by using a function "at" defining a variation of the amplification, which depends on temperature. at(x) = (t/t0)•x Applying this function before the ft is applied, we have ft(at(x)) = ft((t/t0)•x) = f((t0/t)•(t/t0)•x) = f(x) In the construction using an electric circuit, the nonlinear circuit using bipolar transistors as shown in Fig. 18 sometimes has a temperature characteristic as defined by the ft. This can be corrected by an electric circuit, which operates according to the function at. In the nonlinear operation unit of the invention, the first means may be detecting means (182, 185, 188 in Fig. 18(c)) for detecting absolute temperature. The second means may be multiplying means (183, 186, 189 in Fig. 18(c)) for multiplying the values proportional to the absolute temperature derived from the detecting means and the input values of the nonlinear function. A nonlinear unit for temperature compensation may comprise: detecting means (199 in Fig. 19(b)) for detecting absolute temperature; first multiplying means (1910 in Fig. 19(b), 191 and 192 in Fig. 19) for multiplying a value proportional to the absolute temperature obtained by the detecting means and an input signal externally applied; second multiplying means (197, 198 in Fig. 19(a)) for multiplying a value proportional to absolute temperature derived from the first multiplying means and each weight: value, which is to be multiplied by the result of the operation by the nonlinear function operation means; and third multiplying means (Fig. 19(c), 194 in Fig. 19) for multiplying a value inversely proportional to the absolute value gained by the detecting means and an output signal applied to exterior. In the data processing apparatus of the invention, as described above, a plural number of nonlinear operation units are connected (Figs. 2, 6, 9, 10, and 11), and a desired function is achieved by properly setting the weight value and the threshold value. In the data processing apparatus of the invention, each of the plural number of nonlinear operation units interconnected comprises: first and second differential amplifier circuits (195 and 196 in Fig. 19(a)); and weight multiplying circuits (197 and 198 in Fig. 19(a)) for supplying current signals each of a current difference proportional to a weight value to the first terminals of the first and second differential amplifier circuits, and for modulating the weight value by absolute temperature. Characteristic variations of the first and second differential amplifier circuits of the nonlinear function operation means in a first stage (206 in Fig. 22), cancel out as the result of a characteristic variation of the modulating circuit of the nonlinear function operation means located in a second stage preceding to the first stage. Such a data processing apparatus may be constructed using means for detecting a difference between a desired output and an actual output, and means for automatically altering the weight value and the threshold value on the basis of the detected difference, by a back-propagation method. When the weight value and the threshold value are determined through the learning by the back-propagation process, in the neural network where the computing operation by the nonlinear function follows the normal product sum operation, differences each between each output and a teacher signal representative of a desired output are obtained, and the squares of the differences are added together. The resultant sum is used as energy. The energy is smaller as the difference between the output and the teacher signal is smaller. The energy is zero when all the outputs are equal to the teacher signals. The process in which the energy function is used and each weight value and each threshold value are altered so as to decrease the energy function, is known as the back-propagation. Also in the network where the computing operation by the nonlinear function follows the normal product sum operation, the energy may be defined in a manner that the differences each between the internal potential of each neuron, which becomes the output signal, and a teacher signal are squared, and the squares of the differences are added together for all the outputs. The energy is the function of the weight and threshold values. The means during the computing process include the continuous function, multiplication, and addition. Therefore, the energy function can be differentiated, with variables of the weight and threshold values. The energy function can be decreased by altering the weight and threshold values so as to decrease the energy function, using the differentiated function. Fig. 1 showing an arrangement of a nonlinear operation unit according to an embodiment of the present invention. The nonlinear operation unit, which performs the computing operation of the equation (4), nonlinear function operation sections 11a to 11n for computing the input signals by using the nonlinear function g(uj), multiplier sections 12a to 12n for multiplying the function values produced by the nonlinear function operation sections lla to lln by a weight value wji, and an adder section 13 for adding together the results of the multiplying operations by the multiplier sections 12a to 12n. The threshold value (i) is set at 0 and a means for adding the threshold value is omitted. ui = Σj {wji•g(uj)} + i The nonlinear function of the nonlinear function operation sections lla to lln may be a monotonous function of bounded type, such as a hyperbolic tangent function as a logistic function. The nonlinear operation unit may be realized by an analog electronic circuit, a digital electronic circuit, or the combination of a digital computer and a program. A desired data processor may be constructed by combining a plural number of nonlinear operation units, and by properly selecting a nonlinear function and properly setting a weight value. An example of this is shown in Fig. 2. In the example, the two nonlinear operation units shown in Fig. 1 are combined to perform an exclusive OR operation shown in Table 1 using two input signals. INPUT 1 INPUT 2 OUTPUT 0 0 0 0 1 1 1 0 1 1 1 0 Two nonlinear operation units are combined into a circuit as shown in Fig. 2. The circuit has two inputs. The nonlinear functions are each cos(πx/2). The weight value used for each multiplication is 1. The output signal of the circuit is the result of exclusively ORing the input signals. In this instance, these two units have the same constructions. Because of this, the combination of the units is easy. It is evident that in combining the nonlinear operation units, there is no need of using the same functions, the equal weight values, and the same units. Fig. 3 is a block diagram showing an arrangement of a nonlinear operation unit according to another embodiment of the present invention. The nonlinear operation unit of this embodiment performs the operation of the equation (4). The construction of this embodiment is they same as that of the nonlinear operation unit of Fig. 1 except that an adder section 33 additionally includes a means for adding the threshold value i to the sum of the multiplication results. In the nonlinear operation unit of this embodiment, the input signals are computed by using the nonlinear functions in the multiplier sections 32a to 32n. The results are multiplied by the weight values in the multiplier sections 32a to 32n. The products from the multiplier sections and the threshold value are added together in the adder section 33. In this way, the input signals are converted into an output signal. Fig. 4 is a block diagram showing a circuit, constructed with one nonlinear operation unit of Fig. 3, for obtaining the derivative of a hyperbolic tangent function. The hyperbolic tangent function tanh'(x) is given by tanh'(x) = 1 - (tanh(x)) 2 In this circuit, the nonlinear function is (tanh(x)) 2 . The output signal from the (tanh(x)) 2 operation unit 41 is multiplied by a weight value of -1 in the multiplier 42. A threshold value of 1 is added to the product from the multiplier 42. The output signal of the circuit is the derivative of the hyperbolic tangent function. Fig. 5 is a block diagram showing a nonlinear operation unit for performing the operation of the equation (6) already referred to. This nonlinear operation unit includes function operation sections 51a to 51n each for performing the computing operation of a function f(w, u), which produces the operation results equivalent to the products of multiplying the function values, which are obtained by computing the input signals u by using the nonlinear function g(uj), by weight values wji, and an adder section 52 for summing the results of the operations by the function operation sections 51a to 51n. In the nonlinear operation unit, i is 0, and a means for adding it is omitted. ui = Σj {f (wji, uj)} + i The input signals u are computed by using the function f(w, u), which produces the operation results equivalent to the product of multiplying the results of computing the input signals u by using the nonlinear function, by the weight values, so that input signals are converted into an output signal. Fig. 6 is a block diagram showing a circuit, constructed with two nonlinear operation units of Fig. 5, for performing an exclusive OR operation. As shown, the circuit has two inputs. The function f for each input is defined as follows: f(w, u) = wcos(πu/2) In this embodiment, nonlinear operation units receiving the two input signals of the same nonlinear function and a nonlinear operation unit receiving one input signal are arranged as shown. The output signal produced from the circuit is the result of exclusively ORing the input signals. The embodiment shown in Fig. 7 is an nonlinear operation unit, which performs the operation of the equation (4), and is different from the nonlinear operation unit shown in Fig. 5 in that a means for adding the threshold i is additionally provided in an adder section 72. The input signals are computed by using nonlinear functions, and the results of the computation are multiplied by a weight of a proper value. The products of the multiplication are added to the threshold value. In this way, the input signals are converted into an output signal. Fig. 8 is a block diagram showing a circuit, constructed with one nonlinear operation unit of Fig. 7, for obtaining the derivative of a hyperbolic tangent function. In this embodiment, the function f is defined as follows: f(w, u) = w•{tanh(u)} 2 By setting the threshold value to "1", the derivative of the hyperbolic function of the input is produced. Fig. 9 is a block diagram showing an exclusive OR circuit using two nonlinear operation units shown in Fig. 5, in which all the values during the computing process are real numbers and the nonlinear function includes a monotonous function of bounded type. The monotonous function g of bounded type is given g(x) = 0 (x < 0) g(x) = x (0 ≤ x ≤ 1) g(x) = 1 (1 < x) Using the function, f1, f2, f3, f4, and f5 are defined as follows: f1 (w, u) = w•g(u) f2 = f3 = f4 = f5 = f1 The weights are set as shown. With this construction, inputs a and b are exclusively ORed as shown in Table 1. Fig. 10 is a block diagram showing an exclusive OR circuit using two nonlinear operation units shown in Fig. 7, in which all the values during the computing process are real numbers and the nonlinear function includes a logistic function as a monotonous function of bounded type. The logistic function is g1(x) = 1/(1 + 2 -x ) Using the function, the functions f6, f7, f8, f9, and f10 are defined as follows: f6(w, u) = w•g1(u) f6 = f8 = f9 = f10 = f7 The weights and threshold values are set as shown. With this construction, inputs a and b are exclusively ORed as shown Table 1. Fig. 11 is a block diagram showing a general binary function operation unit using two nonlinear operation units shown in Fig. 7, in which the weights and threshold values may be properly set. The nonlinear function is the monotonous function of bounded type of the equation (12). The functions f1, f2, f3, f4, and f5 are defined as in the equation (13). Using those functions, the circuit is arranged as shown in Fig. 11. By altering the weights and the threshold values, a binary function with two-input/one output shown in Table 2 is realized. A desired input/output relation can be obtained by the weight and threshold value according to the table. FUNCT ION OUTPUTS FOR INPUTS WEIGHT & THRESHOLD a=0 b=0 a=0 b=1 a=1 b=0 a=1 b=1 W 13 W 14 W 23 W 24 W 34 δ 3 δ 4 (0) 0 0 0 0 0 0 0 0 0 0 0 Λ 0 0 0 1 1 1 1 1 -1 0 0 0 0 1 0 1 1 -1 -1 -1 1 1 (x) 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 -1 -1 1 1 -1 1 1 (y) 0 1 0 1 0 0 0 1 0 0 0 xor 0 1 1 0 1 -1 1 -1 2 0 0 Y 0 1 1 1 1 0 1 0 1 0 0 ¬V 1 0 0 0 1 0 1 0 -1 0 1 ¬xor 1 0 0 1 1 1 1 1 -2 0 1 (¬y) 1 0 1 0 0 0 0 -1 0 0 1 1 0 1 1 -1 1 1 -1 1 1. 0 (¬x) 1 1 0 0 0 -1 0 0 0 0 1 1 1 0 1 1 -1 -1 1 1 1 0 ¬Λ 1 1 1 0 1 -1 1 -1 1 0 1 (1) 1 1 1 1 0 0 0 0 0 0 1 Fig. 12 is a circuit diagram of the nonlinear operation unit of Fig. 7 constructed using 3-terminal amplifier elements, such as electron tubes, junction type field effect transistors, and bipolar transistors. As shown, the circuit with both the bounded, monotonous function and the multiplying function is realized by using differential amplifier circuits using the electron tubes, junction type field effect transistors, and bipolar transistors. As shown, this circuit includes three differential amplifier circuits 121, 122 and 123 each consisting of a pair of three-terminal amplifier elements being connected such that the first terminals (emitter, source or cathode) are interconnected. Differential potentials proportional to the input signal are input to between the second terminals (base, gate and grid). Currents, proportional to the weights, are input to the first terminals (emitter, source and cathode) of the amplifying element. The third terminals (collector, drain and plate) of the 3-terminal amplifier elements respectively constituting the differential amplifier circuits 121, 122 and 123 provide the output signals of nonlinear functions, respectively. The output signals of the differential amplifier circuits 121, 122 and 123 are added together by a current adder circuit 124, and output as the output signal of this nonlinear operation unit. In the illustration of the embodiment, the electron tube is a triode, but may be a pentode in lieu of the triode. The weights 1 and 3 are positive value and the weight 2 is a positive value. A nonlinear function operation section using bipolar transistors will be described. In the bipolar transistor, the collector current I c flowing into the collector is mathematically expressed by the following equation I C = Is•exp(V BE /V T ) where V T = k•T/q k : Boltzmann constant T : absolute temperature q : electron charge Is : reverse saturation current The reverse saturation current is a value proper to each transistor. Within the same integrated circuit, it is proportional to the emitter area. Therefore, it can be controlled by controlling the emitter area. The absolute temperature is the temperature of the junction pat of the element. The adjacent transistors within the same integrated circuit have approximately equal absolute temperature. In the circuit to follow, it is assumed that the transistors are equal in the reverse saturation current and the absolute temperature, and those current and temperature are represented by Is and T, respectively. The current amplification factor (I C /I B ) is generally large, and then it is assumed that I B is 0 unless otherwise referred to, and that the collector current I C and the emitter current I E are equal. When bipolar transistors Q1 and Q2 are connected as shown in Fig. 13(a), the collector current I C1 and I C2 , as well known, are given by the following equation I C1 = Is•exp((V B1 -V E )/V T ) I C2 = Is•exp((V B2 -V E )/V T ) where V B1 : base potential of the transistor Q1 V B2 : base potential of the transistor Q1 V E : emitter potential of the transistors Q1 and Q2 Assuming that the total emitter current of both transistors is I E , and arranging the above equations for the current difference, then we have I C1 - I C2 = I E •(exp((V B1 - V B2 )/2V T ) - 1)/ (exp((V B1 - V B2 )/2V T ) + 1) The hyperbolic tangent function is defined by the following equation: tanh(x) = (exp(x/2) - 1)/(exp(x/2) + 1) Rearranging the equation (21) using the above hyperbolic tangent function, we have I C1 - I C2 = I E •tanh((V B1 - V B2 )/2V T ) This circuit can produce a current difference proportional to the product of multiplying a function value that is obtained by applying a hyperbolic tangent function as a logistic function to the input voltage difference by the emitter total current I E . As seen from the equation (23), when the reverse saturation currents of the two transistors are equal to each other, the circuit is not influenced by the reverse saturation currents. In the analog integrated circuit, it is difficult to set the reverse saturation currents of the transistors to preset values, but it is relatively easy to set the characteristics of the two transistors to the same ones. It is for this reason that this circuit (differential amplifier) is used. The results of the circuit by using an analog circuit simulation circuit are shown in Fig. 13(b). Fig. 13(b) illustrates the input/output relation of the circuit under the condition that the current i is varied from 0.0 mA to 2.0 mA in the step of 0.2 mA at 300°K (27°C). At this time, the thermal voltage is approximately 26 mV. In this circuit, i ≥ 0. Fig. 14 is a circuit diagram of the nonlinear operation unit shown in Fig. 7 constructed using three terminal amplifier elements, such as electron tubes, junction type field effect transistors, and bipolar transistors. As shown, a bounded, monotonous function and a multiplier are constructed using electron tubes, junction type field effect transistors, and bipolar transistors. This unit includes three nonlinear function operation circuits, and the output signals of those circuits are added together by a current adder circuit. In each nonlinear function operation circuit, first and second 3-terminal amplifier elements 141 and 142 are interconnected at the first terminals (emitter, source, and cathode), thereby forming a first differential amplifier circuit 145. Third and fourth 3-terminal amplifier elements 143 and 144 are interconnected at the first terminals (emitter, source and cathode), thereby forming a second differential amplifier circuit 146. The first and fourth 3-terminal amplifier elements 141 and 144 are interconnected at the second terminals (base, gate, and grid), thereby forming a first input terminal. The second and third 3-terminal amplifier elements 142 and 143 are interconnected at the second terminals (base, gate, and grid), thereby forming a second input terminal. A voltage proportional to the input signal is supplied to the first and second input terminals. The first and third 3-terminal amplifier elements 141 and 143 are connected at the third terminal (collector, drain, and plate), thereby forming a first output terminal. The second and fourth 3-terminal amplifier elements are connected at the third terminal (collector, drain, and plate), thereby forming a second output terminal. Currents of a current difference proportional to a weight value are fed to the first terminals (emitter, source, and cathode) of the first and second differential amplifier circuits, thereby applying the bounded, monotonous function to the input signals. As a result, the current differences proportional to the products of them by a negative or positive value appear at the first and second output terminals. The nonlinear function operation section constructed with bipolar transistors as 3-terminal amplifier elements will be described. The circuit of this section is arranged as shown in Fig. 15. Use of two differential amplifier circuits 151 and 152 shown, a nonlinear function circuit of four quadrants which may take a positive or negative value can be realized. This circuit is constructed with four bipolar transistors Q3, Q4, Q5 and Q6 of which the reverse saturation currents are equal. The collector currents I C3 , I C4 , I C5 , and I C6 of the transistors are given by the following equations I C3 = I S • exp((Vin1 - V E1 )/V T ) I C4 = I S • exp((Vin2 - V E1 )/V T ) I C5 = I S • exp((Vin2 - V E2 )/V T ) I C6 = I S • exp((Vin1 - V E2 )/V T ) where Vin1, Vin2 : potential at the input terminal V E1 : potential at the emitters of the transistors Q3 and Q4 V E2 : potential at the emitters of the transistors Q5 and Q6 Assuming that the total emitter current of the transistors Q3 and Q4 is I E1 and the total emitter current of the transistors Q5 and Q6 is I E2 , and arranging the above equations for the current difference, then we have I C3 - I C4 = I E1 •tanh((Vin1 - Vin2)/2V T ) I C5 - I C6 = I E2 •tanh((Vin2 - Vin1)/2V T ) As shown in Fig. 15(a), the collectors of the transistors Q3 and Q5 are connected to each other, and the total collector current is Iout1. The collectors of the transistors Q4 and Q6 are connected to each other, and the total collector current is Iout2. The difference of the total currents is expressed by Iout1 - Iout2 = (I E1 - I E2 )•tanh((Vin1 - Vin2)/2V T ) Also in this circuit, the signs of the total emitter currents I E1 and I E2 cannot be changed, but the sign of the difference of the total emitter currents can be changed. This circuit, generally called a multiplier core, is widely used for the analog circuit, such as VTR, and some of logic circuits. The results of simulating this circuit by an analog simulation circuit are shown in Fig. 15(b). The figure illustrates the input/output relation of the circuit under the condition that the current I E1 - I E2 is varied from -1. 0 mA to + 1.0 mA in the step of 0.2 mA at 300°K (27°C). The instance described above is the circuit constructed using the bipolar transistors. The circuit having the characteristics of the bounded, monotonous function and the multiplication, can be achieved by another 3-terminal amplifying elements of nonlinear characteristics, such as field effect transistors generally operating as balanced modulators, electron tubes having the remote cut-off characteristic, electron tubes having variable µ characteristics. Fig. 16 is a circuit diagram showing a nonlinear operation unit constructed using three nonlinear function operation circuits of Fig. 15(a). Each nonlinear function operation circuit is a nonlinear operation unit for performing the operation of the hyperbolic tangent function and the multiplication, viz., a sigmoid synapsis circuit. The nonlinear operation unit includes three nonlinear function operation circuits and a current adder circuit 167 for adding together the output signals of those nonlinear function operation circuits. Each nonlinear function operation circuit includes a first differential amplifier circuit 165 in which first and second bipolar transistors 161 and 162 are connected at the emitters, and a second differential amplifier circuit 166 in which third and fourth bipolar transistors 163 and 164 are connected at the emitters. In the nonlinear function operation circuit, the bases of the first and fourth bipolar transistors 161 and 164 are connected to form a first input terminal. The bases of the second and third bipolar transistors 162 and 163 are connected to form a second input terminal. A voltage proportional to the input signal is applied to between the first and second input terminals. The collectors of the first and third bipolar transistors 161 and 163 are connected to form a first output terminal. The collectors of the second and fourth bipolar transistors 162 and 164 are connected to form a second output terminal. Current of a current difference proportional to a weight value is supplied to the emitter of the second differential amplifier circuit. With such an arrangement, the input signals are processed by the hyperbolic tangent functions as the bounded, monotonous functions. The results of the processing are multiplied by positive or negative values. A current difference proportional to each product appears at the first and second output terminals. The output signals and a threshold value are added together by the current adder circuit 167. The result of the addition is output as an output signal of the nonlinear operation unit. As described above, when the bipolar transistors are used, the characteristics of the hyperbolic tangent function and the multiplication are obtained. In this circuit, the amplification factor varies depending on temperature since the mathematical expression of the characteristics of the circuit contains a term describing absolute temperature. Rearranging the equation describing the characteristic of the balanced modulator, for absolute temperature T, then we have Iout1 - Iout2 = (I E1 - I E2 )•tanh((1/2)•q• (Vin1 - Vin2)/kT) As seen from the above equation, a sensitivity to the input voltage difference is inversely proportional to the absolute temperature. As seen from Fig. 17, a temperature characteristic curve of this circuit is gentle at high temperature and steep at low temperature. The inclination of the characteristic curve, when the input voltage difference is 0, is inversely proportional to absolute temperature. Even if the circuit has such a characteristic, the characteristic, in most cases, can be automatically corrected through the back-propagation basis learning. Where no learning is carried out or when temperature varies after the back-propagation basis learning is completed, some temperature compensating measure must be taken. In one of possible ways for compensating for the temperature characteristic, circuits which detects an absolute temperature of the circuit of the nonlinear operation unit and vary their amplification factors in accordance with the absolute temperature, are located in the prestages of the respective inputs. The amplification factor A(T) of each preamplifier circuit is expressed by A(T) = Ao/T where T : absolute temperature Ao : constant The characteristic of a circuit resulting from the combination of the prestage amplifiers, which the characteristic is equivalent to that of the balanced modulator, is expressed by Iout1 - Iout2 = (I E1 - I E2 )•tanh((1/2)•q•A(T)• (Vin1 - Vin2)/kT) = (I E1 - I E2 )•tanh((1/2)•q•(Ao/T)• (Vin1 - Vin2)/kT) = (I E1 - I E2 )•tanh((1/2)•q•Ao• (Vin1 - Vin2)/k) The term concerning temperature is not contained in the above equation. A multi-layered neural network using the above circuits has a less temperature-dependency. Fig. 18(a) shows a temperature compensating circuit using the preamplifier as mentioned above. In the circuit, a thermo sensitive resistor is used as a feedback resistor of an operational amplifier. The circuit has such a characteristic that the amplification factor varies depending on temperature as shown in Fig. 18(c). Fig. 18(c) is a circuit diagram showing the nonlinear operation unit of Fig. 16 including temperature compensating means. As shown, the circuit operable for the computing operation of the hyperbolic tangent function and the multiplication is constructed using bipolar transistors. Amplifiers 181, 184, and 187 having such sensitivity as to neutralize the temperature variation of the sensitivity of the bipolar transistor are located in the inputs of the nonlinear operation unit, viz., in the prestages of the nonlinear function operation circuits of the unit. With provision of those amplifiers having the temperature compensating function, the characteristics of the nonlinear operation unit is insensitive to temperature. Operational amplifier circuits 183, 186, and 189 are combined with feed back resistors of thermo sensitive resistors 182, 185 and 188, to form inverting amplifiers. The thermo sensitive resistor has such a temperature characteristic that its resistance is 0.33 %/°K at 300 °K in absolute temperature. In the inverting amplifiers, the amplification factor varies at 0.33 %/°K. The temperature characteristic of the bipolar transistor is inversely proportional to absolute temperature. Accordingly, at 300 °K in absolute temperature its sensitivity reduces at approximately - 0.33 %/°K. With use of the preamplifiers, the temperature characteristic is neutralized. The temperature compensating method using the preamplifiers can reduce the influence by the temperature variation but the circuitry to execute the compensating method sometimes is complicated. In a multi-layered neural network, no problem arises when the overall network is not influenced by temperature even if the individual layers of the network are influenced by temperature. The interlayer correction in the multilayered neural network may be made by modulating an intensity corresponding to the weight, viz., (I E1 - I E2 ) in the case of the balanced modulator, so as to be proportional to the absolute temperature. As described above, using the function f as the combination of the hyperbolic tangent function and the multiplication, the internal potential in each neuron is expressed by ui = Σj{f(wji, uj)} + i If a balanced modulator is used in lieu of the function f, the neuron internal potential can be expressed by the following equation depending on temperature ui = Σ{f(wji, uj)} + βi Ui = Σj(Ijiout1 - Ijiout2) + i = ∑j[(IjiE1 - IjiE2)•tanh{(1/2)•q•R•Uj/(k•T)}] + i where Ui : current corresponding to the internal potential ui of a neuron i βi : current corresponding to a threshold value i of the neuron i Ijiout1, Ijiout2 : first and second output currents of the balanced modulator connecting from the neuron j to the neuron i IjiE1, IjiE2 : first and second emitter currents of the balanced modulator connecting from the neuron j to the neuron i R : resistance of a resistor for converting the output current difference to voltage. Let us consider a temperature compensating amplifier circuit with an amplification factor proportional to an absolute temperature. When the absolute temperature is T, an amplitude factor B(T) of the circuit is expressed by B(T) = T•Bo where Bo : constant. In the circuit, the emitter current and the threshold current of each balanced modulator are modulated by the amplification factor or temperature, and then U'i and U'j are U'i = ∑j(B((I 1jE1 -I 1jE2 ),T)•tanh((1/2)•q•R•U'j/(k•T))) + B(i, T) = ∑1(T•B 0 •(I 1JE1 - I 1jE2 )•tanh((1/2)•q•R•U' 1 /(k•T))) + T•B 0 •i = T•B0•(∑1((I 1jE1 -I 1jE2 )•tanh((1/2)•q•R•U' 1 /(k•T))) + j) U'j = ∑i(B((I jiE1 - I jiE2 ), T)•tanh((1/2)•q•R•U'j/(k•T))) + B(i,T) = T•B0•(Σi((I jiE1 - I jiE2 )•tanh((1/2)•q•R•U'j/(k•T))) + i) = T•B 0 •(Σi((I 1jE1 - I jiE2 )•tanh((1/2)•q•R•[ T •B0•(Σ1((I 1jE1 - I 1jE2 )•tanh((1/2)•q•R•U'1/(k•T))) + j)]/(k• T ))) + i) = T•B0•(Σi((I jiE1 - I jiE2 )•tanh((1/2)•q•R•[B0•(Σj((Iij E1 - Iij E2 )•tanh((1/2)•q•R•U'j/(k•T))) +i)]/k)) + j) where U'i : current corresponding to the internal potential ui of a neuron i after temperature compensation U'j : current corresponding to the internal potential uj of the neuron j after temperature compensation As seen from the above equations, where two nerve neurons are connected, if the temperature compensation is carried out using the amplification factor B, the temperature characteristics of them cancel out, and consequently the terms of temperature marked with the underline in the equation are eliminated. The method for the temperature compensation between two neurons thus far described is applicable for the interneuron temperature compensation in any type of network. As described above, the accumulation of a characteristic variation caused by temperature may be avoided by increasing the number of layers of the network. Additionally, all the terms of temperature can be eliminated in a manner that the amplification factor A is applied to the input coming from exterior, and the amplification factor B is applied to the output to exterior. While description about the temperature compensation has been made using the layered network, the same thing is correspondingly applicable for a recurrent network in which a variation of the output of a neuron becomes a variation of the input of the neuron per se. Fig. 19(a) is a circuit diagram showing a constituent element of the embodiment of the present invention, which additionally includes a circuit for modulating the weight in accordance with the absolute temperature of differential amplifier circuits 195 and 196. As shown in Fig. 19(a), the computing function of the hyperbolic tangent function and the multiplication is realized by using bipolar transistors 191 to 194. With regard to the current corresponding to the weight, current mirror circuits 197 and 198 in which the output emitters are connected to fixed resistors feed a current difference proportional to the absolute temperature and input current difference to the differential amplifier circuits 195 and 196. The current mirror circuit in which the output emitter is connected to the fixed resistor is widely used as a circuit which receives a constant current as an input current and outputs a current proportional to an absolute temperature. A current proportional to temperature is obtained by the current mirror circuits and is supplied to the differential amplifier circuits 195 and 196. As a result, the temperature characteristic of the output current difference is equal to the temperature characteristic of a sensitivity of the input voltage. The characteristic of this circuit is expressed by f t (w, u). The characteristics of an amplifier circuit, shown in Fig. 19(b), of which the amplification factor is proportional to an absolute temperature, and another amplifier circuit, shown in Fig. 19(c), of which the amplification factor is inversely proportional to an absolute temperature, are expressed by a t (x) and b t (x), respectively. In a network constructed using these circuits as shown in Fig. 20, the temperature characteristics in the network cancel out. In the network of Fig. 20, the compensation is made for the portions indicated by double lines. The temperature compensation in the Fig. 20 circuitry of the network structure will be described in more detail. The nonlinear function operation circuit of Fig. 19(a), illustrated in block form in Fig. 21(a), is made up of a sigmoid synapsis section (hyperbolic tangent function circuit) 211 and a weight multiplying circuit 212. The sigmoid synapsis section 211 is mathematically described by the equation (27), as already described. The output signal of the sigmoid synapsis section is inversely proportional to an absolute temperature, as shown in Fig. 17. The weight multiplying circuit 212 characteristically operates to modulate the weight in proportion with an absolute temperature, as shown in Fig. 21(b). Fig. 22 is a block diagram for explaining the neutralizing operation of the temperature characteristics in the network structure circuit of Fig. 20. The temperature characteristic of the sigmoid synapsis part in a f t (w, u) operation section 206 is neutralized by the temperature characteristics of the multiplying parts in f t (w, u) operation circuits 202 and 203. The temperature characteristic of the sigmoid synapsis part in a f t (w, u) operation section 202 is neutralized by the temperature characteristics of an a t (u) operation section 200 of which the amplification factor is proportional to absolute temperature. The temperature characteristic of the sigmoid synapsis part in a f t (w, u) operation section 203 is neutralized by the temperature characteristics of an a t (u) operation section 201. The temperature characteristic of the multiplying parts in the f t (w, u) operation section 205 to 207 is neutralized by the temperature characteristics of an b t (u) operation section 209 of which the amplification factor is inversely proportional to absolute temperature. In the conventional neural network, a processing unit is constructed with a circuit modeled on a neuron, and a plural number of the circuits are networked in a multiple of layers. The processing unit, which performs the computing operation of the equations (1) and (2), includes a multiplying section for multiplying an input xj and a weight wj, an adder section for adding together the results of the multiplying operations by the multiplying section, and a section for processing the output signal of the adder section by a nonlinear operation g(ui). The present invention employs the construction of the processing unit different from that of the conventional one. Means for computing the equation (4) is used as an operation unit (unit cell). A network is constructed using the operation units. The operation of the network is equivalent to the operation of an overall neural network. In the present invention, as described by the equation (4), the inputs uj are processed by a nonlinear function q , the results of the processing by the nonlinear function are multiplied by a weight corresponding to a strength of bonding of synapses, the products of the multiplying operations are added together, and a threshold value i is added to the sum of the products. In this way, the internal potential of the neuron is obtained. Thus, the computing operation of an operation unit is performed on the basis of a value corresponding to the internal potential of a neuron, which is the output signal from another neuron. Therefore, there is no need of computing a value corresponding to the output potential of the neuron. This simplifies the construction of the operation unit and increases the computing speed. In the present invention, as described above, the input signals u are processed by the nonlinear function g(uj), and the function values resulting from the processing are multiplied by the weight value wji. Alternatively, a function (f(wji, uj)), which produces the results of operations equivalent to the results of the computing process of the nonlinear function g(uj) and the multiplying process of the weight wji, may be used. In this case, the circuit construction is considerably simplified. The technical idea of the present invention simplifies the circuit construction when the nonlinear operation unit is realized by an analog circuit, and reduces an error arising from temperature variation and the circuit per se and computing time. The foregoing description of preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims: A non-linear operation unit, comprising: non-linear function operation means (11a to 12n, 31a to 32n, 71a to 71n) for performing computing operations, which produce results by processing at least one input signal by using a non-linear function, and multiplying the results of the computing operations by weight values; and adder means (13, 33, 72) for adding together the results multiplied by the weight values and adding a threshold value to the sum of these results; characterised in that said non-linear function operation means includes differential amplifier circuits (121-123; 145, 146; 165, 166), each said differential amplifier circuit consisting of a pair of amplifier elements each having at least three terminals, said paired amplifier elements being coupled with each other at the first terminals, a voltage difference proportional to the input signal is applied to between the second terminals of said paired amplifier elements, a current proportional to the weight is fed to the first terminals, whereby the output signal is produced as a current difference at the third terminals of said paired amplifier elements constituting a said differential amplifier circuit. A non-linear operation unit according to claim 1, wherein said non-linear function operation means comprises: a first differential amplifier circuit (145; 151; 165) including first and second amplifier elements of at least three terminals being connected to each other at the first terminals; a second differential amplifier circuit (146; 152; 166) including third and fourth amplifier elements of at least three terminals being connected to each other at the first terminals; and wherein the second terminals of the first and fourth amplifier elements are connected to form a first input terminal, the second terminals of the second and third amplifier elements are connected to form a second input terminal, a voltage proportional to the input signal is applied to between the first and second input terminals, the third terminals of the first and third amplifier elements are connected to form a first output terminal, the third terminals of the second and fourth amplifier elements are connected to form a second output terminal, a current difference proportional to the weight value is supplied to the first terminals of the first and second differential amplifier circuits, whereby a current difference proportional to the product of multiplying one of a positive value and a negative value and the result of processing the input signal by a bounded, monotonous function is produced at the first and second output terminals. The non-linear operation unit according to one of claims 1 to 2, in which the threshold value is zero. The non-linear operation unit according to any of claims 1 or 2, further comprising: first means (182, 185, 188) for detecting an intensity of disturbance; and means (183, 186, 189) for correcting the input signals so as to reduce an error, in accordance with the disturbance intensity obtained by the first means(182, 185, 188). The non-linear operation unit according to claim 4, in which said first means (182, 185, 188) is a detecting means (182, 185, 188) for detecting absolute temperature, and said second means is multiplying means (183, 186, 189) for multiplying the values proportional to the absolute temperature derived from the detecting means and the input values of the non-linear function. The non-linear operation unit according to any of claims 1 or 2, further comprising: first means (197, 1911) for detecting an intensity of disturbance; and second means (212) located at the inputs, for changing the weight values and threshold values so as to reduce the influence by the disturbance, in accordance with the disturbance intensity obtained by the first means. A data processing apparatus using a plurality of non-linear operation units according to one of the previous claims, wherein a desired function is set up by properly setting the weight and threshold values, and wherein the data processing apparatus further comprises: detecting means (199, 1911, 182, 185, 188) for detecting absolute temperature; first multiplying means (195, 196, 200, 201) for multiplying a value proportional to the absolute temperature detected by said detecting means by an input signal; second multiplying means (202, 203, 205-207) for multiplying a value proportional to absolute temperature derived from the first multiplying means and each weight value, which is to be multiplied by the result of the operation by the non-linear function operation means; and third multiplying means (209) for multiplying a value inversely proportional to the detected absolute temperature and an output signal. A data processing apparatus using a plurality of non-linear operation units according to one of the claims 2 and 3 to 6, as dependent on claim 2, further comprising: weight multiplying circuits (197, 198) for supplying current signals, each of a current difference proportional to a weight value, to the first terminals of the first and second differential amplifier circuits (195, 196) and for modulating the weight value by absolute temperature, whereby characteristic variations of the first and second differential amplifier circuits of the non linear function operation means in a first, stage (206) are cancelled out as a result of the weight multiplying circuits modulation of the non-linear function operation means located in a second, preceding stage (202, 203). The data processing apparatus according to claim 8, further comprising: detecting means (199, 1911, 182, 185, 188) for detecting absolute temperature; first multiplying means (200, 201) for multiplying a value proportional to the absolute temperature detected by said detecting means by an input signal; second multiplying means (197, 198, 202, 203, 205-207) for multiplying a value proportional to absolute temperature derived from the first multiplying means and each weight value, which is to be multiplied by the result of the operation by the non-linear function operation means; and third multiplying means (209) for multiplying a value inversely proportional to the detected absolute temperature and an output signal.

Inventors: MURAI KAZUMASA, MURAI, KAZUMASA, MURAI, KAZUMASA, C/O FUJI XEROX CO., LTD.
Applicants: FUJI XEROX CO LTD, FUJI XEROX CO., LTD.
Application year: 1994
Main classification: G06N3
IPC codes: G06F15, G06G7, G06N3, G06N99