Apparatus for smoothed scaling of facsimile images

Abstract: Facsimile image-scaling and -smoothing method and apparatus are described. They scale a received facsimile image along a given axis to increase the printed image resolution therealong, while smoothing the scaled image to reduce visually objectionable ticks. They do so by analyzing received image data with respect to adjacent received lines having disparate pixel counts and by filling in pixels therebetween in accordance with predefined fill rules that are designed also to smooth the output image to be printed. Various predefined rules are applied to produce intermediate results (LS, NS, LR, NR) some or all of which are comprehended by the scaling/smoothing algorithm to produce the final smoothed, scaled output pixel image. Preferably such analyzing and filling in accordance with such rules are performed by a hybrid hardware and firmware subsystem within a receiving facsimile machine or facsimile-receiving printer.

Description: Technical Field The present invention relates generally to the scaling of facsimile images. More particularly, it concerns the smoothed vertical-resolution multiplication of received facsimile images to reduce the objectional visibility of transmitted image artifacts and to achieve higher print quality. Background Art Facsimile images typically are of one of two vertical resolution standards, e.g. 98 lines per inch or 196 lines per inch. In facsimile reception-capable printers and certain more recent facsimile equipment, 300 dots per inch (DPI) vertical resolution is more common. Thus, there is a need to have higher resolution facsimile imaging equipment vertically expand, or scale, the received facsimile image as by filling in between vertically adjacent received dots with print dots to render the printed facsimile image vertically full scale and contiguous, i.e. spatially continuous. When facsimile images are produced, there frequently is a potentially visible pixel or dot artifact called a 'tick', which will be understood to refer to an extraneous black dot in the transmitted image that is added by the imaging equipment above or below horizontal lines within the scanned image. There is a need to reduce the objectionable visibility of such ticks in printed facsimile output images. In US-A-4791491, there is described a method of generating supplemental lines for placement between adjacent lines of facsimile data. In this method, logical combinations of incoming pixel data are generated so as to generate supplemental data points which are determined by the intersecting boundary between inverse borders. In the preferred embodiment described, this results in the generation of intermediate on-pixel blocks which are longer than those of the adjacent lines of real data. In Patent Abstracts of Japan, Vol. 7 No. 272 (E-214) (JP-A-58153450), there is described a system for converting the resolution of received facsimile information using a simple algorithm. In accordance with the present invention, there is provided apparatus for processing a received facsimile image data structure as defined in Claim 1. The apparatus of the present invention is thus arranged so as to scale a received facsimile image along the given axis to increase the printed image resolution therealong, while smoothing the scaled image to reduce visually objectionable ticks. This is achieved by analyzing the received image data with respect to adjacent received lines having disparate pixel counts and by filling in pixels therebetween in accordance with predefined fill rules which are designed also to smooth the output image to be printed. Various predefined rules are applied to produce intermediate results which are comprehended by the scaling/smoothing algorithm to produce the final smoothed, scaled output pixel image. Preferably, such analyzing and filling in accordance with such rules are performed by a hybrid hardware and firmware subsystem within a receiving facsimile machine or facsimile receiving printer. The present invention will be more readily understood after a consideration of the drawings and the detailed description of the preferred embodiment. Brief Description of the Drawings Figs. 1A and 1B illustrate a first input facsimile image and a corresponding, smoothed, resolution-multiplied intermediate image produced in accordance with one aspect of the preferred method and apparatus. Figs. 2A and 2B illustrate a second input facsimile image and a corresponding intermediate image produced by another aspect of the preferred method and apparatus. Figs. 3A and 3B illustrate the first input facsimile image and a corresponding intermediate image produced by yet another aspect of the invention. Figs. 4A and 4B illustrate the second input facsimile image and a corresponding intermediate image produced by still another aspect of the invention. Fig. 5 illustrates the smoothed, resolution-multiplied output image that results from application of the invented process on the first input facsimile image. Fig. 6 illustrates the smoothed, resolution-multiplied output image that results from application of the invented process on the second input facsimile image. Figs. 7A through 7F are a functional block diagram illustrating the preferred hardware register layout and gating logic, in accordance with the preferred hardware-assisted implementation of the preferred method and apparatus. Figs. 8A through 8D illustrate typical input and smoothed, resolution-multiplied output pixel images processed in accordance with the invention. Detailed Description of the Preferred Embodiments and Best Mode of Carrying Out the Invention Referring first briefly to Figs. 1A and 1B, Fig. 1A represents a typical lower resolution received pixel image consisting of two vertically adjacent pixel rows having a disparate number of on pixels (represented by circles). Fig. 1B represents a corresponding higher resolution intermediate pixel image having two spacing pixel rows added between the two original pixel rows. In accordance with the invented method and apparatus, such resolution-multiplied output pixel images not only are of higher resolution, but also are smoothed by the choice of pixel images within the added spacing rows. Preferably, as may be seen from Fig. 1B, such added pixel images are of on-pixel lengths, or have on-pixel counts, that are intermediate, and preferably graduated, between the counts of the narrower upper pixel row and the wider lower pixel row of the received pixel image. It will be understood that Fig. 1B illustrates only an intermediate result of the invented method and apparatus, and not an end result. Considering next Figs. 2A and 2B, it may be seen that another typical input pixel image is shown in Fig. 2A, with a corresponding intermediate output pixel image shown in Fig. 2B that similarly is smoothed and resolution multiplied. Contrasting Figs. 1B and 2B reveals that the processing steps that produce them in accordance with the rules described herein are not exactly complementary, yet both yield intermediate results that are resolution multiplied and smoothed between adjacent pixel rows of the received pixel image that have disparate on-pixel counts, e.g. one in the upper or lower row and nine in the other row. Again, it will be understood that Fig. 2B represents an intermediate result, and not an end result of the invented resolution multiplying and smoothing method and apparatus. Referring briefly now to Figs. 3A and 3B, yet another intermediate result of received pixel image processing is illustrated whereby the identical received pixel image of Fig. 1A is processed differently, in accordance with the rules described herein, to produce a slightly differently smoothed, yet resolution-multiplied intermediate pixel image. As noted above, Fig. 3B represents only an intermediate and not an end result of the invented method and apparatus. Figs. 4A and 4B illustrate still another intermediate result of received pixel image processing similar to that shown in Figs. 2A and 2B, wherein the lower one of adjacent received pixel rows has a single on pixel and wherein the upper one thereof has nine on pixels. Once again, a slightly differently smoothed, resolution-multiplied intermediate pixel image is produced, as may be confirmed by comparing Figs. 2A and 2B with Figs. 4A and 4B. Turning now to Fig. 5, it will be appreciated that there is represented an output, to-be-printed pixel image having a desirably smoothed and resolution-multiplied correspondence with the input pixel images of Figs. 1A and 3A. It will be understood that the output pixel image of Fig. 5 represents a pixel row-by-pixel row logical combination of on pixels of the corresponding intermediate pixel images of Figs. 1B and 3B. Specifically, in accordance with the invented method and apparatus, the first and last rows of the output pixel images of Fig. 5 are merely a replication of the upper and lower input pixel image rows. In other words, in accordance with the invented method and apparatus, the resolution-multiplying and smoothing steps do not affect these output pixel rows. In accordance with the invented method and apparatus, the added spacing, or filler, lines (the number of which in this illustrated example is two) are formulated in accordance with predefined rules that ensure desirable smoothing of the resolution-multiplied pixel image between the adjacent rows of the received pixel image. Specifically, the first added spacing row (the upper one of the two spacing rows) is determined by operation 1 illustrated in Figs. 1A and 1B. In contrast, the second added spacing row (the lower one of the two spacing rows) is determined by combining operation 1 illustrated in Figs. 1A and 1B and operation 3 illustrated in Figs. 3A and 3B. In accordance with the invention, such combination is a bit-wise logical OR of the on pixels in Figs. 1B and 3B, as may be seen. Referring to Fig. 6, the result of applying the invented smoothing, resolution-multiplying method and apparatus to the received pixel image shown in Figs. 2A and 4A may be seen. Fig. 6 represents a combined application of operations 2, 3 and 4 corresponding, respectively, with Figs. 2A and 2B, 3A and 3B and 4A and 4B. It may be seen that, as before, the top and bottom received pixel rows simply are replicated in the output, while the upper spacing, or filler, row is same as the corresponding row of the intermediate pixel image in Fig. 2B and the lower spacing row is the same as the corresponding row of the intermediate pixel image in Fig. 4B. Those skilled in the art will appreciate that operations 1, 2, 3 and 4 illustrated in Figs. 1A, 1B, 2A, 2B, 3A, 3B, 4A and 4B may be thought of as smoothing primitives that usefully are combined, in accordance with invention, to produce smoothed, resolution-multiplied, printable output pixel images. For purposes of the equations listed below and the boolean calculations or combinations involved in their solution, it will be appreciated that LS and NS values represent "smeared" values, and LR and NR values represent "rounded" values. It also will be appreciated that the logical AND operator is designated by ∩ and that the logical OR operator is designated by ∪ in the boolean combinations. The equations implemented by the preferred method and apparatus are as follows: LS: For i = 0 to 7, LS[i] = (L[i+7] ∪ L[i+8] ∪ L[i+9]) ∩ N[i+8] NS: For i = 0 to 7, NS[i] = (N[i+7] ∪ N[i+8] ∪ N[i+9]) ∩ L[i+8] LR: For i = 0 to 7, LR[i] = L[i+7] ∩ L[i+8] ∩ L[i+9] NR: For i = 0 to 7, NR[i] = N[i+7] ∩ N[i+8] ∩ N[i+9] LSorNS = LS ∪ NS LSorLR = LS ∪ LR LSorNR = LS ∪ NR NSorLR = NS ∪ LR NSorNR = NS ∪ NR LRorNR = LR ∪ NR LSorNSorLR = LS ∪ NS ∪ LR LSorNSorNR = LS ∪ NS ∪ NR LSorLRorNR = LS ∪ LR ∪ NR NSorLRorNR = NS ∪ LR ∪ NR and LSorNSorLRorNR = LS ∪ NS ∪ LR ∪ NR Those skilled in the art will appreciate that, while all of the above equations are implemented in accordance with the preferred embodiment of the invention, only equations (6) and (12) are used by the invented solution to produce the desired facsimile image fill and smooth attributes. Specifically, LSorNSorNR defines the last fill row and LSorLR defines all but the last fill row, as will be better illustrated by example. All equations are implemented in hardware for the sake of firmware flexibility in devising alternative invented solutions for various applications or image resolution-multiplying and -smoothing criteria. In accordance with the preferred embodiment of the invention, equations (1) through (15) are implemented in hardware illustrated in Figs. 7A through 7D. Those skilled in the art will appreciate that the illustrated hardware registers and gating logic readily may be incorporated into existing facsimile receiving or printer equipment, as by sharing an input/output (I/O) bus with read-and-write memory (RAM), read-only memory (ROM), central processing unit (CPU) and print control logic that form part of a graphics processor module (GPM). Such conventional GPM typically communicates with host processor logic including, for example, COmpress/DECompress (CODEC) logic, RAM, ROM, CPU and a modem-connected line control unit (LCU). It will be appreciated that compressed image data received over a telephone line and stored in RAM within the host processor may be decompressed by the CODEC and sent to the GPM, where it is stored uncompressed in RAM for processing by the invented apparatus prior to printing of smoothed, high-resolution facsimile images. The hardware of the invented apparatus preferably includes two 17-bit shift registers L (last) and N (next), only the eight LSBs of which may be written under firmware control and combinational logic circuits shown schematically in Figs. 7A through 7F. Such combinational logic preferably includes an array of AND and OR gates defining what may be thought of logically as four 8-bit "registers" or bytes, LS, NS, LR, NR (which it will be appreciated need not be implemented as physical registers); and an array of two-, three- and four-input OR gates, the outputs of which may be read under firmware control. While the illustrated LS, NS, LR, NR bytes, or bit-wise organizations of the logic combinations of selected bits of the L and N hardware registers, within the spirit of the invention, may be implemented as hardware registers, or storage elements, those skilled in the art will appreciate that the outputs of the AND and OR gates shown in Figs. 7A through 7D more simply may be input directly to the OR gates shown in Figs. 7E and 7F, without buffering or drive circuitry therebetween. The least-significant byte of the L register successively is written under control of the firmware with the most recently input (e.g. received) or processed (whether passed unchanged or added) pixel row, and the least-significant byte of the N register successively is written under control of the firmware with the next input (e.g. received) and to-be-processed pixel row. Stated another way, the L register always contains either a received byte of last input pixel row data or the last-created byte of added pixel row data, whereas the N register always contains a next received byte of adjacent input pixel row data. In effect, the combinational logic rounds and smears the output pixel image, not as between adjacent input pixel rows, but instead as between adjacent output pixel rows. Combinational logic connected with bits 7 through 16 of the L and N registers produces last and next rounded and smeared outputs represented as four eight-bit "registers" LS, NS, LR, NR that correspond with equations (1) through (4) above (and also with operations 1 through 4, described above), as illustrated in Figs. 7A through 7D. Those of skill will appreciate that, although they are illustrated in quadruplicate in Figs. 7A through 7D, registers L, N are actually singular, i.e. each merely represents a singular, seventeen-bit register, the selected output bits of which are combined as shown in four different ways to produce the desired LS, NS, LR, NR logic combinations, or bytes. Not shown in Figs. 7A through 7D are the array of OR gates that generate LSorNS, LSorLR, LSorNR, NSorLR, NSorNR, LRorNR, LSorNSorLR, LSorNSorNR, LSorLRorNR, NSorLRorNR, LSorSNorLRorNR, the inputs of which are corresponding bits of the outputs of ones of the LS, NS, LR, NR logic combinations that implement equations (5) through (15). The outputs of these OR gates will be understood by skilled persons to define the bit-wise logical OR combinations of two or more of the LS, NS, LR, NR bytes shown in Figs. 7A through 7D. As is pointed out above, by the invented method, only the LSorLR and LSorNSorNR OR gate outputs are actually read by the firmware and written to an array of output, or fill pattern, pixel rows. These two bit-wise logic combinations are shown in Figs. 7E and 7F, where it will be understood that LS, NS, LR and NR are the same bytes shown in Figs. 7A through 7D and that there actually are eight OR gates (only two of which are shown) that produce the eight-bit output LSorLR (designated "LS OR LR" in Fig. 7E) and that there are actually eight OR gates (only two of which are shown) that produce the eight-bit output LSorNSorNR (designated "LS OR NS OR NR" in Fig. 7F). In alternative hardware and firmware implementations, within the spirit of the invention, these and/or other logic combinations of LS, NS, LR and NR also may be implemented, as all are available for ORing by hardware and for reading by firmware. Thus, more or fewer logic combinations may be provided, with an attendant increase or decrease in the flexibility with which the firmware may be implemented to perform a desired facsimile image-smoothing function in accordance with the invention. It also will be appreciated that the invention alternatively may be implemented in software or firmware executing within the CPU or a dedicated microprocessor. Briefly summarizing the scaling method used in conjunction with the invented method and apparatus, reference is made to Figs. 8A, 8B, 8C and 8D. Figs. 8A and 8B illustrate (at grossly exaggerated scale), respectively, the vertical scaling or resolution multiplying of a 196 line per inch input pixel image of the letter "E" into a 300 DPI output pixel image, with smoothing in accordance with the invented method and apparatus. Figs. 8C and 8D illustrate, respectively, the vertical scaling or resolution multiplying of a 98 lines per inch input pixel image of the letter "E" into a 300 DPI output pixel image, also with smoothing in accordance with the invented method and apparatus. Those who are skilled will appreciate that, at the typically small scale and high resolution at which a facsimile image such as the illustratively represented (and grossly enlarged) letter "E" would be printed--e.g. in ten or twelve point type and at 300 DPI--the invented scaling and smoothing substantially enhances the visual appearance of the output facsimile image, regardless of the resolution and accuracy of the received facsimile image. While only textual facsimile images are illustrated herein as being subject to the invented scaling and smoothing, those of skill will appreciate that the resolution-multiplying and smoothing method and apparatus described and illustrated herein lends itself as well to enhanced graphic facsimile image processing, as the invention simply processes adjacent rows of received pixel data in accordance with predefined smearing and rounding rules without regard for the larger picture, i.e. without concern with overall facsimile image content. Figs. 8A and 8C illustrate lower resolution received pixel images received, for example, by a facsimile machine, wherein extraneous pixels, or ticks, visibly and objectionably appear at the top, bottom and left side of the letter "E." Figs. 8B and 8D illustrate higher resolution printable output pixel images corresponding, respectively, to Figs. 8A and 8C that are produced by the invented method and apparatus. Figs. 8B and 8D may be seen to replicate pixel rows of their corresponding received pixel images with higher resolution pixel rows of identical length, and in addition vertically to expand the number of higher resolution pixel rows by vertically spacing such replicate rows and adding therebetween one or more so-called "spacing" rows of pixels in accordance with the rules described above. The result, as may be seen is that there is beneficial rounding of corners that otherwise would be apparent in the output pixel image. Unless the resolution of the to-be-printed image is an integral multiple of that of the received image, it is not possible to place spacing pixel rows in the output image at exactly corresponding vertical locations. For example, the fifth row of pixels (shaded) from the top of the "E" in Fig. 8D should have placed one and one-half lines down from the fourth row of pixels (black) to center it between the fourth and seventh rows (black) that correspond to the upper leg of the "E" of the original pixel image in Fig. 8C. The limits of the high-resolution grid on which output pixels may be placed require that the spacing line be placed one or two lines below the fourth row. Thus, scaling in accordance with the invented method and apparatus is achieved by varying the number of spacing lines that are added between original pixel rows, in accordance with the ratio between the low-resolution received pixel image and the high-resolution printed output pixel image. Those of skill in the art will appreciate that it is preferred to select a nominal number of lines that would create an output pixel image line spacing that is as close as possible to, but never more than, the original spacing. Then extra spacing lines are added occasionally to correct for accumulated placement errors over a page of facsimile image printed output. At typically high print resolutions such as 300 DPI, such controlledly limited placement errors are imperceptible. Preferably, received pixel images are processed from top to bottom. Each received, or original, pixel row is replicated in the output pixel image in a location that is spaced from the previous original pixel row in the output by at least the nominal number of spacing lines. As each such spacing line is placed, any line placement error is added to a variable cumulative placement error maintained in memory. If the cumulative error is greater than the line placement resolution, an extra line of spacing is added between the current and previous line. Then the amount of the line placement resolution is subtracted from the cumulative error prior to proceeding to the next original pixel row. Nominal line spacing may be calculated by dividing the higher resolution by the lower resolution using integer division, with any remainder being the line placement error. Such ratiometric output pixel image line spacing is readily accomplished by those skilled in the art. It may be seen by contrasting Figs. 8A and 8B that there also is some rounding of corners of the original received pixel image that are not artifacts but that instead represent defined features of the original pixel image. For example, the upper left and right corners of the upper horizontal leg of the E and the upper right corner of the center horizontal leg thereof are rounded by the invented method and apparatus. Similar rounding occurs by the smoothed scaling or resolution-multiplying process that produces the output pixel image illustrated in Fig. 8D from that illustrated in Fig. 8C. These are an effect of the invented method and apparatus that represents a desirable compromise in producing smoothed, high resolution facsimile image printed output. The invented facsimile image-processing apparatus now may be understood to include 1) input facsimile image data structure having a defined resolution along a given axis (e.g. the vertical axis as shown in Figs. 8A and 8C), with the structure including a first and a second row each having plural pixels each having a defined on/off state, the first and second rows being adjacent (also as shown in Figs. 8A and 8C); and 2) a processor for processing the input data structure (e.g. the processor described herein as including the hardware registers and combinational logic shown in Figs. 7A through 7F and a microprocessor executing the described firmware operations). Preferably, the processor includes a first plural-pixel storage element (e.g. the L register) storing a defined number of plural pixels of said first pixel row and a second plural-pixel storage element (e.g. the N register) storing a defined number of plural pixels of the second pixel row. In accordance with the preferred embodiment of the invention, the processor also includes combinational logic (e.g. the OR and AND gates illustrated in Figs. 7A through 7D) producing plural predefined first logic combinations of selected ones of the stored pixels from the first and second storage elements, with the first logic combinations defining plural-pixel intermediate data structures (e.g. LR, LS, NR, NS) representing a predefined number of plural pixels corresponding to the outputs of the first logic combinations (e.g. those shown in Figs. 7A through 7D). Also in keeping with the preferred embodiment, the invented processor defines a plural-pixel output data structure (e.g. LSorLR and LSorNSorNR illustrated in Figs. 7E and 7F) based upon predefined second logic combinations (e.g. the OR gates also illustrated in Figs. 7E and 7F) of selected ones of such intermediate data structures. As may be seen from Figs. 8A and 8B, the processor effectively performs input pixel image rounding and smearing as between selected pixels of the first and second pixel rows (e.g. the darkly shaded pixel rows of Figs. 8A and 8C). Further, it may be seen from Figs. 7C and 7D that the first logic combinations preferably include one or more bit-wise AND functions to perform such image rounding (as represented by bytes LR, NR) and it may be seen from Figs. 7A and 7B that the second logic combinations preferably include one or more bit-wise OR functions to perform such image smearing (as represented by bytes LS, NS). As described and illustrated herein, the first and second logic combinations preferably are performed in hardware, due to pixel processing rate requirements, although of course one or both, within the spirit of the invention, may be performed instead in firmware. Preferably, the processor includes firmware for reading the plural-pixel output data structure (e.g. LSorLR and LSorNSorNR of Figs. 7E and 7F), as described above. As illustrated in Figs. 8B and 8D, the processor may be seen to produce a third row of plural pixels (the lightly shaded pixels of Figs. 8B and 8D) each having a determined on/off state, with the determined on/off state of at least one of the plural pixels in the third row being based upon such processing of the input data structure, with the third row of plural pixels being output, e.g. for printing by a facsimile printer, by the processor spatially between and along with (i.e. in addition to) the first and second rows of plural pixels of the input facsimile image data structure. In this way, the resolution of such facsimile image along the given axis, e.g. a vertical axis, effectively is increased by a desired ratio, as described above and as illustrated in Figs. 8A through 8D. An invented method of scaling lower resolution received image data for printing on a higher resolution output device also now may be understood, based upon an understanding of the invented apparatus described above. The preferred method may be characterized as including the following steps: 1) identifying received image data containing, along a given print axis (such as the vertical axis represented in Figs. 8A and 8C), disparate pixel counts of adjacent received pixel rows (e.g. the first row of each of the letters "E" containing a singular on pixel representing a tick and the second row thereof containing one or more horizontal rows of on pixels representing the top leg of the letter "E"), and in connection with such identified data; 2) selectively turning on off pixels in one or more added output pixel rows located between received pixel rows of the received image data (e.g. those pixel rows of Figs. 8B and 8D that are lightly shaded) to produce modified output image data for printing, wherein the average number of on pixels in the added output pixel rows is intermediate the number of pixels in such received pixel rows and is graduated in a predetermined manner between such disparate pixel counts (e.g. the thirteen-pixel second row of Fig. 8B being intermediate in count between the single-pixel top row and the fifteen-pixel second row of Fig. 8A; the three-pixel second row of Fig. 8D being intermediate in count between the single-pixel top row and the fifteen-pixel second row of Fig. 8C; the thirteen-pixel third row of Fig. 8D also being intermediate in count between the single-pixel top row and the fifteen-pixel second row of Fig. 8C; the count of on pixels in the added row(s) graduating predeterminedly from one to thirteen to fifteen in Fig. 8B and from one to three to thirteen to fifteen in Fig. 8D). The invention alternatively may be understood to be a facsimile image resolution-multiplying method that includes the following steps: 1) receiving a facsimile image of a first pixel resolution along a given axis (e.g. the vertical axis shown in Figs. 8A and 8C); 2) expanding such received image along such given axis to multiply the first pixel resolution, with the expanding being performed by spacing apart selected ones of adjacent rows of such received image a predefined amount (e.g. by spacing apart each pair of input pixel rows, as illustrated in Figs. 8C and 8D); and 3) filling such expanded image between said spaced-apart adjacent rows by selectively adding rows of on pixels based upon predetermined fill criteria (e.g. by adding the lightly shaded pixel rows of Fig. 8D). Preferably, the filling step includes smoothing in accordance with predetermined smooth criteria that produce a smooth filled pixel region between spaced-apart adjacent rows represented by on pixel row counts within the filled pixel region that are graduated between the counts of the spaced-apart adjacent rows (e.g. the three- and thirteen-pixel counts of second and third rows of Fig. 8D effectively smoothing the single-pixel tick in the top row of Fig. 8C into the fifteen-pixel second row thereof, as illustrated). Industrial Applicability It may be seen then that the method and apparatus of the invention are compatible with higher resolution receiving facsimile or related printer equipment, and produce output or printed images that are of increased resolution along a given axis but without objectionable ticks and sharp corners and other features that would be apparent if no smoothing were had. The resolution-multiplying, or image-scaling, rules straightforwardly and inexpensively may be implemented in software, firmware, hardware or a combination thereof within a receiving facsimile machine or dot printer. The result is significant, but relatively inexpensive, on-the-fly improvement in printed facsimile images.

Claims: Apparatus for processing a received facsimile image data structure having a defined resolution along a given axis, said structure including first and second adjacent rows, each row having plural pixels, each of which is in either an on or an off state, said apparatus comprising: a processor for processing said image data structure, said processor comprising: a first storage element (L) for storing a predetermined number of pixels of said first row; a second storage element (N) for storing a predetermined number of pixels of said second row; and means (AND, OR) for producing first predefined logical combinations of pixels stored in said first and said second storage elements (L,N), said first logical combinations defining plural-pixel intermediate data structures (LR, LS, NR, NS) representing the on/off state of a predetermined number of pixels, said processor being arranged to produce a plural-pixel output data structure (LS OR LR; LS OR NS OR NR) representing the on/off state of a number of pixels based upon second predefined logical combinations (OR) of two or more of said intermediate data structures (LR, LS, NR, NS), said plural-pixel output data structure (LS OR LR; LS OR NS OR NR) representing the on/off states of respective pixels to be inserted between said first and second rows and defining a smooth filled on-pixel region which is graduated between said first and said second rows, irrespective of the received image data structure. Apparatus as claimed in Claim 1, wherein said processor is arranged to perform image rounding and smearing between pixels of said first and said second pixel rows. Apparatus as claimed in Claim 2, wherein said first logical combinations comprise one or more bit-wise AND functions (AND) for performing said image rounding and one or more bit-wise OR functions (OR) for performing said image smearing. Apparatus as claimed in Claim 3, wherein said first logical combinations are performed in hardware. Apparatus as claimed in Claim 3, wherein said second logical combinations comprise one or more bit-wise OR functions (OR) performed in hardware. Apparatus as claimed in Claim 3, wherein said first and said second logical combinations are performed in hardware. Apparatus as claimed in Claim 6, wherein said processor further comprises firmware for reading said plural-pixel output data structure (LS OR LR; LS OR NS OR NR). Apparatus as claimed in any preceding claim, wherein said smooth filled on-pixel region comprises a third row of plural pixels, the processor being arranged to output said third row.

Inventors: BENJAMIN TRUDY L, EATON WILLIAM S, LOWE DAVID J, BENJAMIN, TRUDY L., EATON, WILLIAM S., LOWE, DAVID J.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1994
Main classification: H04N1
IPC codes: H04N1, G06T3