Method of forming contacts in the memory region and the peripheral region of an IC

Abstract: A first contact hole (39a) for a bit line is formed in an interlayer insulating film (39), and a polysilicon film (40) is formed on the inner surface of the contact hole (39a) and on the interlayer insulating film (39). Subsequently, the polysilicon film (40) is subjected to isotropic dry etching using a resist (43) as a mask, and the interlayer insulating film (39) is subjected to RIE etching, thereby forming a second contact hole (39b) in the interlayer insulating film (39) in a peripheral circuit region (31b). Then, a laminated film (44) containing a metal is formed on the inner surface of the second contact hole (39b) and on the polysilicon film (40), and the second contact hole (39b) is filled with a filling member (45). The laminated film (44) and the polysilicon film (40) are patterned, thereby forming a bit line (46) in a memory cell region (31a). The laminated film (44) contacts the silicon substrate directly in the second contact hole (39b), thereby forming a silicide and resulting in a contact of very low resistance. In the first contact hole (39a) the firstly deposited polysilicon film (40) prevents a silicidation of the substrate and therefore a P n failure in a memory cell region, where dimensions of transistors are smaller than in a peripheral region.

Description: This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with wiring which has contacts of low resistance. The following documents are mentioned in relation to the present invention. EP-A-0 018 175 relates to a method for producing a semiconductor device, in particular a MIS structure semiconductor device, and forming ohmic contact with the semiconductor substrate of the semiconductor device. EP-0 349 107 describes a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body. An insulator layer region is formed between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body JP-A-2 249 264 describes a semiconductor de-Jice which is stable for thermal treatment and which has less variability of element characteristics by laminating an amorphous silicon film and a heat-resistant and conductive nitriding metal film or metal film silicide at the take-out port of one electrode of lower-part electrodes. Furthermore, EP-A-0 315 422 discloses a semiconductor memory device having an ohmic contact between an aluminum-silicon alloy metallization film and a silicon substrate. FIGS. 1 - 3 are cross sectional views, illustrating a method for manufacturing a first conventional semiconductor device, i.e. a DRAM (Dynamic Random Access Read Write Memory). First, an element-separating oxide film 2 is formed on a P-type silicon substrate 1, thereby separating the surface thereof into a memory cell region la and a peripheral circuit region 1b. Then, a gate insulating film 3 is formed on the P-type silicon substrate 1. Gate electrodes 4 each of which is incorporated in a transistor 6 for data transmission are provided on the gate insulating film 3 in the memory cell region la. A gate electrode for a driving transistor (not shown) is formed on the gate insulating film 3 in the peripheral circuit region 1b. Subsequently, ions of an impurity are injected into the P-type silicon substrate 1, using as masks the gate electrodes of the transistors 6 for data transmission and the gate electrode of the driving transistor. As a result, diffusion layers 15 and 5 for forming the source and drain regions of the driving transistor and the data-transmitting transistors 6 are formed in the P-type silicon substrate 1. In other words, the data-transmitting transistors 6 each consisting of the gate insulating film 3, the gate electrode 4 and the diffusion layer 5 serving as the source/drain region are formed in the memory cell region 1a. The driving transistor is formed in the peripheral circuit region 1b. The memory cell region has a capacity for data accumulation. These transistors 6 and the data accumulation capacity form one memory cell. Thereafter, an insulating film 7 is formed on the side surfaces and the upper surfaces of the gate electrodes 4. An interlayer insulating film 8 is formed on the insulating film 7, the P-type silicon substrate 1, and the element-separating oxide film 2. Then, a first contact hole 8a for a bit line is formed in the interlayer insulating film 8 such that the hole 8a is aligned with the gate electrodes 4, by the use of FOBIC (Fully Overlapping Bitline Contact) described in 1987 Symposium on VLSI Technology, Digest of Technical Papers, p. 93. Subsequently, a second contact hole 8b is formed in the interlayer insulating film 8 in the peripheral circuit region 1b. As is shown in FIG. 2, a polysilicon film 9 having a thickness of about 1000 Å is deposited on the interlayer insulating film 8 and on the inner surfaces of the first and second contact holes 8a and 8b by means of the CVD (Chemical Vapor Deposition). Thereafter, about 5 × 10 15 cm -2 of ions of an N-type impurity 10 such as phosphorus or arsenic are injected into the P-type silicon substrate 1, using the interlayer insulating film 8 as a mask. As a result, N-type diffusion layers 11 and 12 of high density are formed in the surface portions of the substrate 1 which are located under the first and second holes 8a and 8b. Thereafter, as is shown in FIG. 3, a WSi 2 film 13 having a thickness of about 2000 Å is deposited on the polysilicon film 9 by sputtering. Then, the WSi 2 film 13 and the polysilicon film 9 are patterned by the lithography and the RIE (Reactive Ion Etching), thereby forming a bit line 14 as a polycide wire which has a laminated structure of the WSi 2 film 13 and the polysilicon film 9. The WSi 2 film 13 is annealed at a relatively high temperature, e.g. 800 - 950°C, so as to activate the diffusion layer and stabilize the film 13. Since in the above-described first conventional semiconductor device, the P-type silicon substrate 1 and the polysilicon film 9 contact each other in the first and second contact holes 8a and 8b, the contact resistance in each of the holes cannot be reduced, although the rate of PN-junction failure can be reduced. As regards the contact resistance of the bit line contact in the memory cell region 1a, it suffices if the contact resistance is lower than the channel resistance of the data-transmitting transistor 6. This means that the contact resistance of the bit line is not necessarily set to a very low value, and may be set, for example, to about 1 kΩ. On the other hand, the contact resistance in the second contact hole 8b in the peripheral circuit region 1b must be set to a low value with respect to the channel resistance of the driving transistor, i.e., to a value of as low as several tens Ω. The above-described manufacturing method cannot satisfy the requirement that the contact resistance in the peripheral circuit region 1b be kept to a very low value, as the degree of integration increases. FIGS. 4 and 5 are cross sectional views, illustrating a method for manufacturing a second conventional semiconductor device. In these figures, elements similar to those employed in the first conventional semiconductor device are denoted by corresponding reference numerals, and an explanation will be given of only different elements. As is shown in FIG. 4, a laminated film 21 consisting of a TiN upper layer and a Ti lower layer is formed, by sputtering, on the interlayer insulating film 8 and on the inner surface of each of the first and second contact holes 8a and 8b. Then, the resultant structure is annealed at a relatively low temperature, for example, of about 600°C, thereby forming a TiSi 2 film on the bottom of each of the first and second contact holes 8a and 8b. Thereafter, as is shown in FIG. 5, a metal film 22 of W or the like is deposited on the laminated film 21 by the CVD. Subsequently, the metal film 22 and the laminated film 21 are patterned by the lithography and the RIE, thereby forming in the memory cell region 1a a bit line 23 consisting of the laminated film 21 and the metal film 22. As described above, in the above-described second conventional semiconductor device, the P-type silicon substrate 1 contacts the Ti lower layer of the laminated film 21 in each of the first and second contact holes 8a and 8b. Therefore, the contact resistance is made low in the contact holes 8a and 8b, but the rate of pn-junction failure is high since a silicide is formed as a result of reaction of Ti and Si in the contact portion of the P-type silicon substrate 1 and the Ti layer. In other words, silicon contained in the N-type diffusion layers 11 and 12 becomes a silicide as a result of reaction of Ti and Si in the contact portion, so that pn-junction failure is liable to occur in the N-type diffusion layers 11 and 12. Forming deep N-type diffusion layers 11 and 12 is considered to prevent the failure. However, although deep diffusion layers can prevent the failure, they reduce the withstand voltage between adjacent elements. This is because the distance between the adjacent elements is shorten as their size is reduced. Therefore, the diffusion layers 11 and 12 cannot actually be made deep, and accordingly the pn-junction failure cannot be prevented. The occurrence of the pn-junction failure is especially disadvantage to the bit line contacts in the memory cell region la, since the number of the bit line contacts in the memory cell region 1a is much larger than that of the contacts in the peripheral circuit region 1b. Specifically, where the number of the contacts in the peripheral circuit region 1b is several tens thousands, the number of the bit line contacts in the memory cell region la is several millions. Thus, the method for manufacturing the second conventional semiconductor device cannot satisfy the requirement that the rate of pn-junction failure in the memory cell region 1a be kept low. FIG. 6 is a cross sectional view, showing an "in-house" development of a CMOS DRAM. In FIG. 5, elements similar to those employed in the first conventional semiconductor device are denoted by corresponding reference numerals, and an explanation will be given of only different elements. First, a P-type well region 28 and an N-type well region 29 are formed in a P-type silicon substrate 1. Then, first and second element-separating oxide films 2a and 2b are formed on the P-type silicon substrate 1. The first element-separating oxide film 2a divides the surface of the P-type silicon substrate 1 into a memory cell region la and a peripheral circuit region 1b. N-type diffusion layers 5 and 15 for forming the source and drain regions are formed in the P-type well region 28, and a P-type diffusion layer 17 is formed in the N-type well region 29. Then, a first interlayer insulating film 8 is formed on the P-type silicon substrate 1, and the element-separating oxide films 2a and 2b. A first contact hole 8a for a bit line is formed in the interlayer insulating film 8 in the memory cell region la such that the hole 8a is aligned with gate electrodes 4. Subsequently, a polysilicon film 9 having a thickness of about 1000 A is deposited on the interlayer insulating film 8 and on the inner surface of the first contact hole 8a by means of the CVD. Thereafter, N-type diffusion layer 11 of high density is formed in the surface portion of the P-type silicon substrate 1 which is located under the first hole 8a. Thereafter, a WSi 2 film 13 is deposited on the polysilicon film 9. Then, the WSi 2 film 13 and the polysilicon film 9 are patterned by the lithography and the RIE, thereby forming, in the memory cell region 1a, a bit line 14 as a polycide wire which has a laminated structure of the WSi 2 film 13 and the polysilicon film 9, and a polycide wire 16 in the peripheral circuit region 1b. The WSi 2 film 13 is then annealed. Subsequently, a second interlayer insulating film 18 is deposited on the first interlayer insulating film 8, the bit line 14, and the polycide wire 16. Third and fourth contact holes 18a and 18b and a fifth contact hole (not shown) are formed in the first and second interlayer insulating films 8 and 18. Further, a sixth contact hole 18d is formed in the second interlayer insulating film 18. The third contact hole 18a extends to the N-type diffusion layer 15, while the fourth contact hole 18b extends to the P-type diffusion layer 17. The fifth contact hole extends to a gate electrode (not shown), while the sixth contact hole 18d extends to the polycide wire 16 located at a level identical to that of the bit line. Then, a laminated film (not shown) consisting of a TiN upper layer and a Ti lower layer is deposited on the inner surfaces of the third through sixth contact holes 18a, 18b, 18d, and on the second interlayer insulating film 18. An Al alloy film is formed on the laminated film. Thereafter, the laminated film and the Al alloy film are patterned, therefore a first Al wire 19 is formed on the second interlayer insulating film 18. A third interlayer insulating film 20 is deposited on the first Al wire 19 and the second interlayer insulating film 18. A seventh contact hole 20a is formed in the interlayer insulating film 20 such that it extends to the first Al wire 19. A second Al wire 24 is formed on the inner surface of the seventh contact hole 20a and on the third interlayer insulating film 20. In the above-described method for manufacturing the "in-house" developed semiconductor device, the rate of PN-junction failure can be kept low since the P-type silicon substrate 1 contacts the polysilicon film 9 in the first contact hole 8a. The contact resistance can be reduced, since the diffusion layers 15 and 17 contact the first Al wire 19 in the third and fourth contact holes 18a and 18b. It is therefore an object of the present invention to further improve a semiconductor device such that a low rate of PN-junction failure in a memory cell region and a low contact resistance in a peripheral circuit region is provided, and also to provide a method for manufacturing the semiconductor device. The above object is achieved by providing a device according to independent apparatus claim 1, and a method according to independent method claim 13. Preferred embodiments of the present invention are described in appended dependent claims. Since in the invention, the semiconductor substrate is in contact with the semiconductor film in the first contact hole, the rate of PN-junction failure can be restrained. Further, since the semiconductor substrate is in contact with the film containing at least the metal, the contact resistance can be minimized in the second contact hole. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross sectional view, useful in explaining a method for manufacturing a first conventional semiconductor device; FIG. 2 is a cross sectional view, showing a process performed next to that shown in FIG. 1; FIG. 3 is a cross sectional view, showing a process performed next to that shown in FIG. 2; FIG. 4 is a cross sectional view, useful in explaining a method for manufacturing a second conventional semiconductor device; FIG. 5 is a cross sectional view, showing a process performed next to that shown in FIG. 4; FIG. 6 is a cross sectional view, showing an "in-house" development of a semiconductor device; FIG. 7 is a cross sectional view, useful in explaining a method for manufacturing a semiconductor device according to a first or fifth embodiment of the invention; FIG. 8 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the first or fifth embodiment, and showing a process performed next to that shown in FIG. 7; FIG. 9 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the first embodiment, and showing a process performed next to that shown in FIG. 8; FIG. 10 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the first embodiment, and showing a process performed next to that shown in FIG. 9; FIG. 11 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the first embodiment, and showing a process performed next to that shown in FIG. 10; FIG. 12 is a cross sectional view, showing a semiconductor device according to a second embodiment of the invention; FIG. 13 is a cross sectional view, showing a semiconductor device according to a third embodiment of the invention; FIG. 14 is a cross sectional view, showing a semiconductor device according to a fourth embodiment of the invention; FIG. 15 is a cross sectional view, useful in explaining a method for manufacturing a semiconductor device according to a fifth embodiment, and showing a process performed next to that shown in FIG. 8; FIG. 16 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the fifth embodiment, and showing a process performed next to that shown in FIG. 15; FIG. 17 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the fifth embodiment, and showing a process performed next to that shown in FIG. 16; FIG. 18 is a cross sectional view, useful in explaining the method for manufacturing the semiconductor device according to the fifth embodiment, and showing a process performed next to that shown in FIG. 17; FIG. 19 is a cross sectional view, showing a semiconductor device according to a sixth embodiment of the invention; and FIG. 20 is a circuit diagram, showing a CMOS sense amplifier in a memory cell region. The embodiments of the invention will be explained with reference to the accompanying drawings. FIGS. 7 - 11 are cross sectional views, illustrating a method for manufacturing a semiconductor device according to a first embodiment of the invention, i.e., a DRAM. First, an element-separating film 32 is formed on a P-type silicon substrate 31, thereby dividing the substrate 31 into a memory cell region 31a and a peripheral circuit region 31b. Then, a gate insulating film 33 is formed on the substrate 31. Gate electrodes 34 for data transmitting transistors 36 are provided on the gate insulating film 33 in the memory cell region 31a. A gate electrode for a driving transistor (not shown) is provided on the gate insulating film 33 in the peripheral circuit region 31b. Thereafter, ion injection is performed using as masks the gate electrodes of the driving transistor and the data-transmitting transistor 36, thereby forming in the P-type silicon substrate 1 diffusion layers 37 and 35 which serve as the source/drain regions of the driving transistor and the data-transmitting transistors 36. Thus, the data-transmitting transistors 36 each consisting of the gate insulating film 33, the gate electrode 34 and the diffusion layer 35 serving as a source/drain region is formed in the memory cell region 31a, while the driving transistor is formed in the peripheral circuit region 31b. The diffusion layer 37 in the peripheral circuit region 31b has a density higher than the diffusion layer 35 in the memory cell region 31a, so that the diffusion layer 35 can be brought into contact with a polysilicon film in the memory cell region 31a, while the diffusion layer 37 can be brought into contact with a metal in the peripheral circuit region 31b. In other words, in the case of bringing the diffusion layer 35 into contact with a polysilicon film, it is necessary to keep the density of the diffusion layer 35 low so as to minimize the growth of a natural oxide film on the layer 35. On the other hand, in the case of bringing the diffusion layer 37 into contact with a metal, it is necessary to keep the density of the diffusion layer 37 high so as to enable ohmic contact. The memory cell region 31a has a capacitor for accumulating data. An insulating film 38 is formed on the upper and side surfaces of each gate electrode 34. An interlayer insulating film 39 is formed on the insulating film 38, the P-type silicon substrate 31 and the element-separating oxide film 32. Then, a first contact hole 39a for a bit line is formed in the interlayer insulating film 39 such that the hole 39a is aligned with the gate electrodes 34, by the use of FOBIC. As is shown in FIG. 8, a semiconductor film, for example, a polysilicon film 40, having a thickness of about 1000 Å is deposited on the interlayer insulating film 39 and on the inner surface of the first contact hole 39a by means of the CVD. Thereafter, about 5 × 10 15 cm -2 of ions of an N-type impurity 41 such as phosphorus, arsenic or the like are injected into the P-type silicon substrate 31, using the interlayer insulating film 39 as a mask. The P-type silicon substrate 31 is annealed for activation at a relatively high temperature, for example, of about 800 - 950°C. As a result, a deep N-type diffusion layer 42 of high density is formed in the surface portion of the substrate 31 which is located under the first contact hole 39a for a bit line. Thereafter, as is shown in FIG. 9, a resist 43 is coated on the polysilicon film 40, and a mask pattern 43a is formed by patterning the resist 43 by lithography. Then, the polysilicon film 40 is subjected to isotropic dry etching, using the resist 43 as a mask. Subsequently, the interlayer insulating film 39 is etched by the RIE, using the resist 43 as a mask. As a result, a second contact hole 39b is formed in the portion of the interlayer insulating film 39 which is located in the peripheral circuit region 31b, such that it extends to the diffusion layer 37 as the source/drain region. The contact hole 39b has a diameter smaller than the hole formed in the polysilicon film 40 by dry etching. Thus, a step portion 40a is formed between the polysilicon film 40 and the interlayer insulating film 39 in the vicinity of the second contact hole 39b. The step portion 40a is provided for preventing an overhang from being formed at a peripheral portion of the second contact hole 39b. Thereafter, as is shown in FIG. 10, the resist 43 is removed, and a laminated film 44 consisting of a TiN upper layer and a Ti lower layer is formed, by sputtering, on the inner surface of the second contact hole 39b and on the polysilicon film 40, or at least on the portion of the polysilicon film 40 in the vicinity of the second contact hole 39b. Subsequently, resultant structure is annealed at a relatively low temperature of e.g. 600°C, thereby forming a TiSi 2 film (not shown) on the bottom of the second contact hole 39b. Then, as is shown in FIG. 11, in order to flatten the surface of the laminated film 44, a filling member 45 such as an amorphous silicon film doped with an impurity of high density or a W film is filled in the second contact hole 39b by the use of an etching-back method. Subsequently, the laminated film 44 and the polysilicon film 40 are simultaneously patterned by the lithography and the RIE, thereby forming in the memory cell region 31a a bit line 46 consisting of the laminated film 44 and the polysilicon film 40. In the above-described first embodiment, the P-type silicon substrate 31 is in contact with the polysilicon film 40 in the first contact hole 39a in the memory cell region 31a, while the P-type silicon substrate 31 is in contact with the Ti layer as the lower layer of the laminated film 44 in the second contact hole 39b in the peripheral circuit region 31b. Accordingly, a multiplicity of bit line contacts in the memory cell region 31a can be free from pn-junction failure. Further, the contact resistance in the contact hole 39b in the peripheral circuit region 31b can be kept at a sufficiently low value relative to the channel resistance of the driving transistor. As a result, contacts are formed, which can satisfy both the requirement that the rate of PN-junction failure be reduced in the memory cell region 31a and the requirement that the contact resistance in the peripheral circuit region 31b be reduced in accordance with high integration. Moreover, although in the first embodiment, the laminated film 44 consisting of the TiN upper layer and the Ti lower layer is formed on the inner surface of the second contact hole 39b and on the polysilicon film 40, a metal silicide can be formed thereon. In other words, a film which contains at least a metal can be formed on the inner surface of the second contact hole 39b and on the polysilicon film 40, in place of the laminated film 44. FIG. 12 is a cross sectional view, showing a semiconductor device according to a second embodiment of the invention. In FIG. 12, elements similar to those in FIG. 11 are denoted by corresponding reference numerals, and an explanation will be given only of different elements. A polysilicon film 40 which has a thickness greater than a half of the diameter of the bit line contact is deposited on the inner surface of the first contact hole 39a and on the interlayer insulating film 39, thereby filling the first contact hole 39a with the film 40. The second embodiment can provide the same advantage as the first embodiment. Further, in the second embodiment, at the time of forming a TiSi 2 film on the bottom of the second contact hole 39b by annealing, a silicide is created also at the boundary between the polysilicon film 40 and the laminated film 44. However, since the first contact hole 39a is filled with the polysilicon film 40, the silicide is created only on an upper portion of the first contact hole 39a. As a result, the influence of stress of creation of the silicide upon a pn-junction in a lower portion of the first contact hole 39a can be minimized. Accordingly, the rate of pn-junction failure can be further reduced. FIG. 13 is a cross sectional view, showing a semiconductor device according to a third embodiment of the invention. In FIG. 13, elements similar to those shown in FIG. 11 are denoted by corresponding reference numerals, and an explanation will be given only of different elements. After a TiSi 2 film is formed on the bottom of the second contact hole 39b, a metal (such as W) film 47 is formed on the laminated film 44, and the second contact hole 39b is not completely filled with the film 47. Thereafter, the metal film 47, the laminated film 44 and the polysilicon film 40 are simultaneously patterned by the lithography and the RIE, thereby forming, in the memory cell region 31a, a bit line 46 consisting of the metal film 47, the laminated film 44 and the polysilicon film 40. The third embodiment can provide the same advantage as the first embodiment. Moreover, since the metal (e.g. W) film 47 is formed by the CVD, the steps can be sufficiently covered. Thus, there is no possibility of breakage of a line in the contact hole, and hence it is not necessary to fill the contact hole. As a result, the filling process can be omitted, that is, the number of processes can be reduced, enhancing the yield of production. FIG. 14 is a cross sectional view, showing a CMOS DRAM according to a fourth embodiment of the invention. In FIG. 14, elements similar to those in FIG. 11 are denoted by corresponding reference numerals, and an explanation will be given only of different elements. A P-type well region 52 and an N-type well region 53 are formed in the surface of the P-type silicon substrate 31, and then first and second element separating films 54 and 55 are formed on the surface of the substrate 31 to divide the substrate 31 into a memory cell region 51a, an N-type channel peripheral circuit region 51b and a P-type channel peripheral circuit region 51c. Subsequently, gate electrodes for respective driving transistors (not shown) are provided on those portions of a gate insulating film 33 which are located in the N-type and P-type channel peripheral circuit regions 51b and 51c. Thereafter, an N - -type diffusion layer 56 which serves as a source/drain region of a data transmitting transistor 36 is formed in the substrate 31 in the memory cell region 51a. An N + -type diffusion layer 57 which serves as a source/drain region is formed in the P-type silicon substrate 31 in the N-type channel peripheral circuit region 51b. A P + -type diffusion layer 58 which serves as a source/drain region is formed in the P-type silicon substrate 31 in the P-type channel peripheral circuit region 51c. Then, the first contact hole 39a is formed, and the polysilicon film 40 and the interlayer insulating film 39 are etched, using a resist (not shown) as a mask, thereby forming second and third contact holes 39b and 39c in the interlayer insulating film 39 in the N-type channel peripheral circuit region 51b and the P-type channel peripheral circuit region 51c, respectively. The laminated film 44 consisting of the TiN upper layer and the Ti lower layer is formed on the inner surfaces of the second and third contact holes 39b and 39c and on the polysilicon film 40. TiSi 2 films (not shown) are formed on the bottom surfaces of the second and third contact holes 39b and 39c. The second and third contact holes 39b and 39c are filled with the filling member 45. The above-described fourth embodiment can provide the same advantage as the first embodiment. Further, since in the fourth embodiment, the N + -type diffusion layer 57 as the source/drain region is connected to the P + -type diffusion layer 58 as the source/drain region, via the laminated film 44. Accordingly, an N + -type impurity contained in the N + -type diffusion layer 57 and an P + -type impurity contained in the P + -type diffusion layer 58 are prevented from mixing with each other. Therefore, the above embodiment can avoid a problem which will occur if the aforementioned first conventional semiconductor device is applied to a CMOS DRAM, i.e., the problem that the N + -type impurity and the P + -type impurity are inevitably mixed with each other via a polycide wire (consisting of a polysilicon film and a WSi film) to thereby increase the contact resistance, where the N + -type diffusion layer 57 is connected to the P + -type diffusion layer 58 by means of the polycide wire. The mixing of the N + -type impurity and the P + -type impurity through the polycide wire is performed in the annealing process. It is effective means for fine elements that the N + -type diffusion layer 57 is connected to the P + -type diffusion layer 58, via the laminated film 44. This invention is every effectively applicable to a CMOS sense amplifier as shown in FIG. 20, which has a peripheral circuit region wherein fine elements are highly integrated. In FIG. 20, reference numeral 62 indicates a word line, reference numeral 63 and 64 bit lines, reference numeral 65 a memory cell, and reference numeral 66 and 67 I/O lines. As described above, in the fourth embodiment, the second and third contact holes 39b and 39c are formed in the polysilicon film 40 and the interlayer insulating film 39, the laminated film 44 is formed on the inner surfaces of the first and second contact holes 39b and 39c and on the polysilicon film 40, and thereafter the contact holes are filled with the filling member 45. However, this embodiment may be modified such that a WSi 2 film, for example, is formed on the polysilicon film 40, the second and third contact holes 39b and 39c are formed in the WSi 2 film, the polysilicon film 40 and the interlayer insulating film 39, the laminated film 44 is formed on the inner surfaces of the first and second contact holes 39b and 39c and on the WSi 2 film, the contact holes are filled with the filling member 45, and the exposed portions of the laminated film 44 are removed. FIGS. 7, 8 and 15 - 18 are cross sectional views, showing a method for manufacturing a semiconductor device according to a fifth embodiment of the invention. In these figures, elements similar to those in FIG. 11 are denoted by corresponding reference numerals, and an explanation will be given only of different elements. As is shown in FIG. 15, a WSi 2 film 61 having a thickness of about 2000 Å is formed on the polysilicon film 40 by sputtering. Then, the WSi 2 film 61 is annealed at a relatively high temperature of e.g. about 800 - 950°C, thereby stabilizing the film 61 and activating diffusion layers 35, 37 and 42. Referring then to FIG. 16, the film 61 is coated with a resist (not shown), and the resist is patterned by the lithography for forming a contact hole. Thereafter, the WSi 2 film 61, the polysilicon film 40 and the interlayer insulating film 39 are sequentially etched with the use of the resist as a mask, thereby forming the second contact hole 39b in the interlayer insulating film 39 in the peripheral circuit region 31b such that it extends to the diffusion layer 37 as a source/drain region. Thereafter, as is shown in FIG. 17, the resist is removed, and the laminated film 44 consisting of the TiN upper layer and the Ti lower layer is formed by sputtering on the inner surface of the second contact hole 39b and on the WSi 2 film 61. Then, the TiSi 2 film is formed on the bottom of the second contact hole 39b by annealing. The second contact hole 39b is then filled with the filling member 45 by the etching-back method. Subsequently, as is shown in FIG. 18, the exposed portions of the laminated film 44 are removed, and the WSi 2 film 61 and the polysilicon film 40 are simultaneously patterned by the lithography and the RIE, thereby forming a bit line 46 consisting of the WSi 2 film 61 and the polysilicon film 40. The fifth embodiment can provide the same advantage as the first embodiment. Although in the fifth embodiment, the WSi 2 film 61 and the polysilicon film 40 are patterned after removing the laminated film 44, the laminated film 44, the WSi 2 film 61 and the polysilicon film 40 may be simultaneously patterned without removing the laminated film 44. FIG. 19 is a cross sectional view, showing a semiconductor device according to a sixth embodiment of the invention. In FIG. 19, elements similar to those in FIG. 13 are denoted by corresponding reference numerals, and an explanation will be given only of different elements. A P-type well region 49 and an N-type well region 50 are formed in the surface of the P-type silicon substrate 31, and then first and second element separating films 32a and 32b are formed on the surface of the substrate 31 to divide the substrate 31 into a memory cell region 31a and a peripheral circuit region 31b. Subsequently, N-type diffusion layers 35 and 37 are formed in the P-type well region 49, while a P-type diffusion layer 58 is formed in the N-type well region 50. Then, a first interlayer insulating film 39 is formed on the insulating film 38, the P-type silicon substrate 31 and the element separating oxide films 32a and 32b, and a first contact hole 39a is formed in the interlayer insulating film 39. Thereafter, a polysilicon film 40 is deposited on the inner surface of the contact hole 39a and the first interlayer insulating film 39. A resist film (not shown) is formed on the polysilicon film 40, and used as a mask to etch the film 40. Then, the first interlayer insulating film 39 is etched by the RIE, using the resist film as a mask, thereby forming second and third contact holes 39b and 39c and a fourth contact hole (not shown) in the first interlayer insulating film 39 in the peripheral circuit region 31b. The second contact hole 39b extends to the N + -type diffusion layer 37, while the third contact hole 39c extends to the P + -type diffusion layer 58. The fourth contact hole extends to a gate electrode (not shown). Thereafter, the resist film is removed, and a laminated film 44 consisting of a TiN upper layer and a Ti lower layer is formed by sputtering on the inner surfaces of the second and third contact holes 39b and 39c and on the polysilicon film 40. TiSi 2 films are formed on the bottom surfaces of the second and third contact holes 39b and 39c and on the polysilicon film 40, and then a metal (e.g. W) film 47 is formed on the laminated film 44. The metal film 47, the laminated film 44 and the polysilicon film 40 are patterned. As a result, a bit line 46 consisting of the metal film 47, the laminated film 44 and the polysilicon film 40 is formed in the memory cell region 31a, and a wire layer 48 having the same level of the bit line and consisting of the metal film 47, the laminated film 44 and the polysilicon film 40 is formed in the peripheral circuit region 31b. Thereafter, a second interlayer insulating film 71 is deposited on the metal film 47 and the first interlayer insulating film 39, and is provided with fifth and sixth contact holes 71a and 71b formed therein and extending to the bit-line-level wire layer 48. A laminated film (not shown) consisting of a TiN upper layer and a Ti lower layer is formed on the inner surfaces of the contact holes 71a and 71b and on the second interlayer insulating film 71. An Al alloy film 72 is provided on this laminated film. Subsequently, the Al alloy film and the laminated film are patterned, therefore a first Al wire 72 is provided on the laminated film, and then a third interlayer insulating film 73 is deposited on the first Al wire 72 and the second interlayer insulating film 71. A seventh contact hole 73a is formed in the interlayer insulating film 73 such that it extends to the first Al wire 72. Thereafter, a second Al wire 74 is formed on the inner surface of the seventh contact hole 73a and on the third interlayer insulating film 73. The above-described sixth embodiment can provide the same advantage as the third embodiment. The first Al wire 72 can be directly connected to the N + -type diffusion layer 37 and the P + -type diffusion layer 58 through a contact hole formed in the first and second interlayer insulating films 39 and 71. In this (conventional) structure, the contact hole has a great depth, and hence the first Al wire 72 may be broken in the contact hole. In the sixth embodiment, however, the wire 72 is connected to the diffusion layers 37 and 58 through the wire layer 48 without such a deep contact hole. Therefore, the sixth embodiment is free from breakage of a wire in a deep contact hole as in the above conventional structure. More specifically, in the sixth embodiment, the wire layer 48 of a bit line level is connected to the N + -type diffusion layer 37 and the P + -type diffusion layer 58 through the second and third contact holes 39b and 39c formed in the first interlayer insulating film 39, and is led onto the first interlayer insulating film 39. The wire layer led on the film 39 is connected to the first Al alloy wire 72 through the sixth contact hole 71b formed in the second interlayer insulating film 71. Thus, the wire 72 can be connected to the diffusion layers 37 and 58 without a deep contact hole. As a result this structure is free from the conventional disadvantage that a wire may be broken in a deep contact hole. In addition, there is another method for preventing breakage of a wire in a deep contact hole. In this method, a conductive layer made, for example, of W is filled in the deep contact hole, and the first Al wire 72 is formed on the conductive layer. To fill the hole, a technique for selectively growing W, which contains a small number of processes, may be employed. This technique, however, cannot be used unless a plurality of contact holes, if formed, have the same depth. In other words, the selective growth technique cannot uniformly fill contact holes of different depths to provide a flat surface. The technique cannot be used in the conventional case where a deep contact hole is formed in the first and second interlayer insulating films 39 and 71, and a shallow contact hole 71a is formed in the second interlayer insulating film 71. Therefore, the etching-back method must be employed to fill contact holes of different depths. However, the number of processes employed in the etching-back method is larger than that of the selective-growth technique of W. In the etching-back method, a filling member is deposited in the contact holes and on the second interlayer insulating film 71, and is then etched back to provide a flat surface. In the sixth embodiment, however, it is not necessary to fill a deep contact hole by the etching-back method, and hence the wire is prevented from being broken in the contact holes. Moreover, the selective growth technique of W which includes a small number of processes can be used to fill the contact holes 71a and 71b, since the holes 71a and 71b have the same depth in the second interlayer insulating film 71.

Claims: A semiconductor device comprising: a semiconductor substrate (31) having a memory cell region (31a, 51a) and a peripheral circuit region (31b, 51b, 51c); a first source or drain region (42) having a first conductivity type of a first MOSFET formed in the surface of said semiconductor substrate (31) in said memory cell region (31a, 51a); at least one second source or drain region (37, 57, 58) of at least one further drive MOSFET formed in said surface of said semiconductor substrate (31) in said peripheral circuit region (31a, 51b, 51c); an insulating film (39) formed on said semiconductor substrate (31); a first contact hole (39a) formed in the insulating film (39) and extending to said first source or drain region (42) of said first MOSFET, forming a bit line contact hole in the memory cell region (31a); a semiconductor film (40) having said first conductivity type formed on the inner surface of said first contact hole (39a) and on said insulating film (39), such that said semiconductor film (40) directly contacts the first source or drain region (42) in said first contact hole (39a); at least one second contact hole (39b, 39c) formed in said semiconductor film (40) and in said insulating film (39) and extending to a respective one of said at least one second source or drain region (37, 57, 58); characterized by a metal layer (44) formed on the inner surface of said at least one second contact hole (39b, 39c) on said insulating film (39) and on the semiconductor film (40), such that a portion of said metal layer (44) is in direct contact with the respective one of said at least one second source or drain regions (37, 57, 58) in said at least one second contact hole (39b, 39c). A semiconductor device according to claim 1, characterized in that the impurity concentration of the at least one second source or drain region (37, 57, 58) is higher than the impurity concentration of the first source or drain region (42). A semiconductor device according to claim 1, characterized in that the first contact hole (39a) is filled with the semiconductor film (40). A semiconductor device according to claim 1, characterized in that the diameter of the at least one second contact hole is smaller in the insulating film (39) than in the semiconductor film (40), thereby forming a step (40a). A semiconductor device according to claim 1, characterized in that the at least one second contact hole (39b, 39c) is filled with a filling member (45). A semiconductor device according to claim 1, further comprising a metal film (47) formed on the metal layer (44). A semiconductor device according to claim 1, characterized in that the first source or drain region (42) is of a first-conductivity type. A semiconductor device according to claim 1, characterized in that said at least one second source or drain region (37, 57) is of a first-conductivity type. A semiconductor device according to claim 8, characterized in that a further second source or drain region (58) of a second-conductivity type is provided. A semiconductor device according to claim 9, characterized in that said second source or drain regions (57,58) are connected via the metal layer (44). A semiconductor device according to claim 9, characterized in that said second source or drain regions (57,58) are connected via said metal layer (44) and said semiconductor film (40). A semiconductor device according to claim 1, further comprising a metal film (47) formed on said metal layer (44); a second insulating film (71) formed on said metal film (47); a further contact hole (71b) formed in said second insulating film (71) and extending to said metal film (47); and an Al alloy wire (72) provided on the inner surface of said further contact hole (71b) and on said second insulating film (71). A method of manufacturing a semiconductor device, comprising the steps of: forming a first source or drain region (42) having a first conductivity type of a first MOSFET in the surface of a semiconductor substrate (31) in a memory cell region (31a, 51a); forming at least one second source or drain region (37, 57, 58) of at least one further drive MOSFET in the surface of said semiconductor substrate (31) in a peripheral circuit region (31a, 51b, 51c); forming an insulating film (39) on the surface of the semiconductor substrate (31); forming a first contact hole (39a) in the insulating film (39) such that the first contact hole (39a) extends to the first source or drain region (42) of said first MOSFET, to form a bitline contact hole in the memory cell region (31a, 51a); forming a semiconductor film (40) having said first conductivity type on the inner surface of said first contact hole (39a) and on the insulating film (39) such that the semiconductor film (40) is in direct contact with said first source or drain region (42) in said first contact hole (39a); forming at least one second contact hole (39b, 39c) in said semiconductor film (40) and said insulating film (39) such that said at least one second contact hole (39b, 39c) extends to a respective one of said at least one second source or drain region (37, 57, 58); characterized by forming a metal layer (44) on the inner surface of said at least one second contact hole (39b, 39c) on said insulsting film (39) and on said semiconductor film (40) such that said metal layer or metal compound layer (44) is in direct contact with the respective one of said at least one second source or drain region (37, 57, 58) of said at least one second contact hole (39b, 39c). A method according to claim 13, characterized in that the first contact hole (39a) is formed in a self aligned manner with respect to a gate electrode (34) of the first MOSFET. A method according to claim 13, characterized in that the step of forming said semiconductor film (40) on the inner surface of said first contact hole (39a) and on said insulating film (39) includes the step of performing heat treatment at a high temperature after forming said semiconductor film (40) in order to activate said dopant. A method according to claim 13, characterized in that the step of forming said metal layer (44) on the inner surface of said at least one second contact hole (39b, 39c) and on said semiconductor film (40) includes the step of performing a heat treatment at a low temperature after forming said metal layer (44). A method according to claim 13, characterized by further comprising the step of filling said at least one second contact hole (39b, 39c) with a filling member (45). A method according to claim 13, characterized by further comprising the step of forming a metal film (47) on said metal layer (44). A method according to claim 13, characterized by further comprising the steps of forming a metal film (47) on said metal layer (44); forming a second insulating film (71) on said metal film (47); forming a further contact hole (51b) in said second insulating film (71) such that it extends to said metal film (47); and forming an Al alloy wire (72) on the inner surface of said further contact hole (71b) and on said second insulating film (71).

Inventors: KOHYAMA YUSUKE, SUGIURA SOUICHI, KOHYAMA, YUSUKE, SUGIURA, SOUICHI, KOHYAMA, YUSUKE, C/O INTELLECTUAL PROP. DIV., SUGIURA, SOUICHI, C/O INTELLECTUAL PROP. DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L23
IPC codes: H01L27