Method and dielectric structure for facilitating overetching of metal without damage to inter-level dielectric

Abstract: Integrated circuit fabrication with a thin layer (230) of oxynitride atop the interlevel dielectric (220), to provide an etch stop to withstand the overetch of the metal layer (300).

Description: The present invention relates to methods of fabrication of, and interlevel dielectric structures in, integrated circuits and similar devices. EP-A-0,343,698 describes a method of forming a contact to an underlying semiconductor substrate through an isolation layer. A separation layer is placed between the isolation layer and an overlying metal layer. In a first embodiment the metal layer and separation layer are etched at the same rate. In a second embodiment an aluminum separation layer is used as a blocking layer at the end of the etch step in which the metal layer is etched. GB-A-2,104,285 describes the manufacture of an integrated circuit in which an oxynitride layer is used. The oxynitride layer is etched to a greater extent than an overlying glass layer. IBM Technical Disclosure Bulletin, vol. 36, No. 03, March 1993, New York US, pages 3 to 5 describes a method of forming metallic studs in a contact opening. Contact openings are formed by etching through a boron nitride layer and an underlying dielectric layer. An layer of metal is then deposited to fill the contact openings. An etched is performed to form metal studs within the contact openings. The boron nitride layer is removed, acting as a sacrificial layer which is used to eliminate excess metal stud recessing. IBM Technical Disclosure Bulletin, vol. 32, No. 10A, March 1990, New York US, pages 221 to 223, "self-aligned double-layer insulator process" describes the formation of a multilayer wiring structure using both organic and inorganic insulating layers. A layer of nitride is deposited over polyimide. An opening is made through both layers. A layer of metal is deposited patterned and etched. The nitride layer acts as a etch stop during the etching of the metal layer. With the increasing complexity of devices, as seen from the addition of more and denser layers of interconnection, the need for overetching becomes more prevalent. This overetch is required to remove "stringers" or filaments seen at the edge of the deepest underlying features when the metal has been etched away from most of the area. However, one of the by-products of the overetch step is an erosion of the contact oxide. This has the potential to cause device failure: if the oxide is very thin over a step, (which may be caused by reflow, for example), the overetching of the metal layer can poke through the insulating oxide and cause voids, which could later produce shorts. Current approaches increase the selectivity to oxide; however, this decreases the ability to remove the "stringers". According to one aspect of the present invention there is provided a method of fabricating an integrated circuit, comprising the steps of: a) providing a partially fabricated structure which includes a semiconductor substrate and transistors formed therein; b) depositing an interlevel dielectric layer comprising silicate glass over said transistors; c) depositing an insulating etch stop layer of silicon oxynitride over said interlevel dielectric layer; d) etching contact holes into said etch stop and interlevel dielectric layers to expose portions of said transistors for electrical connection; e) depositing a layer of metal over said etch stop layer and within said contact holes; f) etching said metal, with a plasma etch chemistry which etches the material of said etch stop layer more slowly than the material of said interlevel dielectric and more slowly than the material of said metal, and continuing said etching step beyond the time required to clear said metal from flat surfaces; whereby said etch stop layer protects said interlevel dielectric from erosion by said metal etching step. According to another aspect of the present invention there is provided an integrated circuit, comprising: a semiconductor substrate and transistors formed therein; an interlevel dielectric layer, predominantly comprising silicate glass, over said transistors; a layer of silicon oxynitride over said interlevel dielectric layer; contact holes extending through said silicon oxynitride and inter-level dielectric layers; a patterned thin-film layer of metal running over said silicon oxynitride layer and extending down into said contact holes, to connect said transistors in a desired electrical configuration. The disclosed inventions provide methods and structures which greatly reduce the danger of this. An etch stop layer is added to the top of the contact oxide, to provide an etch stop to withstand the overetch after the metal is cleared, and thereby prevent erosion of the oxide. In one class of embodiments, a disclosed innovative method adds a thin layer of oxynitride (e.g. 50-100 nm, i.e. 500-1000Å) to the top of a much thicker (e.g. 500-1000 nm, i.e. 5000-10,000Å) silicate glass film (e.g. BPSG or PSG). The presence of nitride in the top film will retard the metal etch from etching into the contact oxide. An advantage of the disclosed innovative method is its compatability with conventional process flows. The innovative method departs from conventional processes only after the deposition and reflow of the doped silicate glass (typically BPSG or PSG). After reflow (which causes significant planarization), the thin oxynitride film is deposited. The contact etch can then be performed with greater safety. Processing then continues conventionally, with metal deposition, metal etch, etc. etc. Thus, the disclosed innovations essentially eliminate oxide erosion during metal overetch step. As a result of this, the degree of overetching used with the metal etch can be increased if required. As a further result, since increased overetching can be tolerated, the requirements for planarization before deposition of the metal layer can be relaxed to some extent. For example, a normal degree of overetch for metal-1 etching would be 40 or 50% - but with the present invention much larger degrees of overetching are permissible. For example, the presently preferred embodiment uses 110% overetching ( i.e. etching for 2.1 times as long as would be required to remove the film from flat surfaces). The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein: Figure 1 shows a process according to a sample embodiment, wherein oxynitride has been deposited on BPSG after reflow. Figure 2 shows a later stage of processing of the embodiment of Figure 1, after contacts have been patterned and etched. Figure 3 shows a later stage of processing of the embodiment of Figure 2, after metal has been deposited, patterned and etched. The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. Figure 1 shows a partially fabricated structure according to a sample embodiment. In this embodiment a monocrystalline silicon substrate 100 has had field oxide regions 110 grown on it, to define active device regions 112 where the field oxide 110 is not present. A polycide layer 120 (silicide-clad polysilicon) has been patterned to form transistor gates and interconnects, and sidewall spacers 122 have been formed on the edges of the patterned layer. (Second, third, and fourth layers of polysilicon, with associated interlevel dielectrics, can be added to the process if desired.) Thereafter an interlevel dielectric is formed: an undoped layer 210 of low-temperature oxide is first deposited, e.g. 100 to 200 nm (1000 to 2000 Å) of TEOS or of plasma oxide. A layer 220 of BPSG (borophosphosilicate glass) is then deposited, to e.g. 300 to 600 nm (3000 to 6000 Å), and a reflow/densification step is performed ( e.g. 25 minutes at a temperature of 875°C, in the presently preferred embodiment). Alternatively, PSG (phosphosilicate glass) or other doped silicate glasses, or other interlevel dielectric materials (including composite multilayer structures) can be used instead. A layer 230 of oxynitride is now deposited by conventional CVD methods. In the presently preferred embodiment, this is deposited to have a refractive index of 1.75, but the O/N ratio can be varied to provide different optical densities (and different O/N ratios) if desired. In the presently preferred embodiment, this is deposited to have a thickness of 80 nm (800Å), but the thickness can be varied if desired (preferably within the range of 50-100 nm (500-1000Å) and less preferably within a wider range). A smaller thickness will provide less protection against erosion, but an excessive thickness will unnecessarily increase the aspect ratio of the contact holes. Figure 2 shows a later stage of processing of the embodiment of Figure 1, after contacts 250 have been patterned and etched. Two locations of contacts 250 are illustrated, one (on the left) exemplifying a contact to active and the other (on the right) exemplifying a contact to poly-1. In etching these contacts, conventional fluoro-etch oxide-etching chemistries can be used, since these will etch oxynitride too. Figure 3 shows a later stage of processing of the embodiment of Figure 2, after metal 300 has been deposited, patterned and etched. The metal 300 may be, for example, Al:1 %Cu over a Ti/TiN barrier layer, but of course other compositions may be used. The metal etch chemistry, in the presently preferred embodiment, is BCl 3 + Cl 2 + SiCl 4 + CHF 3 , but of course other chemistries can be used. This chemistry will etch the aluminum alloy at about 70 nm/min (700Å/min), and etches BPSG at about 12 nm/min (120Å/min), but etches oxynitride only at about 6 nm/min (60Å/min). For a total metal thickness of 750 nm (7500Å), over the moderate planarization provided by the reflowed BPSG layer, about 960 sec of overetching will typically be required from the time the metal first begins to clear. The oxynitride withstands this, which is particularly advantageous at locations where the interlevel dielectric is otherwise relatively thin, e.g. near corners of the poly-1 level over field oxide. Processing continues with conventional steps to complete fabrication, e.g. deposition and planarization of further interlevel dielectric, via patterning, second metal deposition and etch, protective overcoat deposition, etching contact pad apertures, etc. etc. See generally, e.g., VLSI TECHNOLOGY (2.ed. Sze 1988); G.Anner, PLANAR PROCESSING PRIMER (1990); R.Castellano, SEMICONDUCTOR DEVICE PROCESSING (1991); W.Runyan & K.Bean, SEMICONDUCTOR INTEGRATED CIRCUIT PROCESSING TECHNOLOGY (1990 ed.); and the annual proceedings of the IEDM conferences; all of which are hereby incorporated by reference. Advantages Thus, the disclosed innovations, in various embodiments provide some or all of at least the following advantages: 1. Eliminates oxide etching during metal overetch step. 2. Allows overetch step to be increased, if required, since oxide loss is eliminated. 3. Since increased overetching can be tolerated, the requirements for planarization before deposition of the metal layer can be relaxed. 4. High compatibility with conventional process flows. It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts. A variety of interlevel dielectrics can be substituted for the undoped oxide 210 and BPSG 220 of the preferred embodiment, including without limitation phosphosilicates, germanosilicates, arsenosilicates or other doped silicate glasses, other inorganic interlevel dielectric materials, and composite multilayer structures of many kinds. In some processes it may also be possible to use an oxynitride layer over a polyimide or other organic interlevel dielectric materials. In such cases it may be preferable to use plasma-assisted low-temperature deposition of the oxynitride atop the interlevel dielectric. While the disclosed process could be used for via formation, it is much less preferable in that context. The dielectric constant for nitride is about twice that for oxide, so that the parasitic capacitive loading on the metal lines would be increased. While the inventions have been described with primary reference to a single-poly process, it will be readily recognized that these inventions are equally applicable to double-, triple- or quadruple-poly structures and processes. Similarly, while the contact from first metal to first poly and active has been particularly described, it will be readily recognized that the disclosed inventions are equally applicable to processes with multiple layers of metal. The innovative process teachings may also be adapted for contact formation in bipolar or other device technologies. Similarly, it will be readily recognized that the described process steps can also be embedded into hybrid process flows, such as BiCMOS or smart-power processes. Of course a variety of structures can be used to implement the polysilicon or polycide gate. Similarly, while sidewall spacers are normally used, they are not strictly necessary to the practice of the invention. Similarly, a wide variety of materials, and of combinations of materials, can be used to implement the metal layer. Of course, the specific etch chemistries, layer compositions, and layer thicknesses given are merely illustrative, and do not by any means delimit the scope of the claimed inventions. As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.

Claims: A method of fabricating an integrated circuit, comprising the steps of: a) providing a partially fabricated structure which includes a semiconductor substrate and transistors formed therein; b) depositing an interlevel dielectric layer (210,220) comprising silicate glass over said transistors; c) depositing an insulating etch stop layer (230) of silicon oxynitride over said interlevel dielectric layer (210,220); d) etching contact holes (250) into said etch stop and interlevel dielectric layers (210,220,230) to expose portions of said transistors for electrical connection; e) depositing a layer of metal (300) over said etch stop layer (230) and within said contact holes (250); f) etching said metal, with a plasma etch chemistry which etches the material of said etch stop layer (230) more slowly than the material of said interlevel dielectric (210,220) and more slowly than the material of said metal, and continuing said etching step beyond the time required to clear said metal from flat surfaces; whereby said etch stop layer (230) protects said interlevel dielectric (210,220) from erosion by said metal etching step. The method of claim 1 wherein in step e) etching of said metal is continued for more than 175% of the time required to clear said metal from flat surfaces. The method of claim 1 or 2, wherein, in step f), said plasma etch chemistry includes chlorine. The method of any preceding claim wherein, in step f), said plasma etch chemistry is one which etches said dielectric layer more slowly than the material of said metal layer. The method of any preceding claim wherein said interlevel dielectric (210,220) is reflowed prior to deposition of said insulating etch stop layer. The method of any preceding claim wherein the ratio of the as-deposited thickness of said metal layer (300) to the as-deposited thickness of said insulating etch stop layer (230) is in the range between 5:1 to 10:1. The method of any preceding claim wherein said insulating etch stop layer (230) is deposited to an initial thickness in the range of 50-100nm (500-1000Å). The method of any preceding claim wherein said insulating etch stop layer (230) is deposited to an initial thickness f about 80nm (800Å). The method of any preceding claim wherein said interlevel dielectric comprises either a doped silicate glass over an undoped silicate glass, or borophosphosilicate glass. An integrated circuit, comprising: a semiconductor substrate (100), and transistors formed therein; an interlevel dielectric layer (210,220), predominantly comprising silicate glass, over said transistors; a layer of silicon oxynitride over said interlevel dielectric layer (210,220); contact holes (250) extending through said silicon oxynitride and inter-level dielectric layers (210,220, 230); a patterned thin-film layer of metal (300) running over said silicon oxynitride layer (230) and extending down into said contact holes (250), to connect said transistors in a desired electrical configuration. The integrated circuit of claim 10, wherein said interlevel dielectric comprises either a doped silicate glass over an undoped silicate glass, or borophosphosilicate glass. The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 or 11, wherein said interlevel dielectric comprises at least two layers (210,220). The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 12, wherein said silicon oxynitride layer (230) has a refractive index of 1.75. The integrated circuit of any one of claims 10 to 13, wherein said silicon oxynitride layer (230) has a thickness in the range, 50-100nm of (500-1000Å). The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 14, wherein said metal layer (300) has a thickness in the range between about 300nm (3000Å) and about 600nm (6000Å) inclusive. The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 15, wherein said metal layer (300) comprises an alloy of aluminum, preferably over a barrier layer comprising at least 40% of titanium. The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 16, wherein said metal comprises a multilayer structure. The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 17 wherein said interlevel dielectric (210,220) has a total thickness in the range of 0.3-1µm (3000-10,000Å) inclusive. The method of any one of claims 1 to 9 or the integrated circuit of any one of claims 10 to 18, wherein said metal layer and exposed oxynitride layer have an overlying layer of interlevel dielectric or protective overcoat.

Inventors: SARDELLA JOHN C, SARDELLA, JOHN C.
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L23