Semiconductor device with noise suppression

Abstract: A CMOS IC device operable at a frequency of 300 MHz or higher includes a power supply wiring (1) for inter-connecting circuit elements and a power supply pad, and a phase-shifting split wiring (2, 3a-3d) connected to the power supply wiring (1) and not directly connected to any circuit elements, which is provided for producing a noise phase difference between noise signals on the power supply wiring and on the phase-shifting split wiring. A noise signal entering from the phase-shifting split wiring has a phase different from the phase of a signal transmitted on the power supply wiring to thereby reduce spike noise. The split wiring can take the form of one or more loops (2) or one or more split wirings (3a-3d).

Description: The present invention relates to a CMOS IC device. In particular, the present invention concerns the suppression of noise in power supply wirings of a semiconductor device. CMOS circuits feature low power dissipation in which substantial current is dissipated only in a very short period while circuit elements are being switched. Low power dissipation has become desirable as the integration of semiconductor devices has increased, which makes CMOS IC devices more important. However, spike current flows in CMOS IC devices so that spike noise is likely to be generated on power supply wirings. To satisfy the requirements of high speed circuit operation, techniques of high speed and high frequency operations of CMOS circuits have advanced. A power supply voltage has been lowered. In CMOS circuits operating at a high frequency and at a low voltage, if spike noise or other noise generated by the switching of circuit elements changes a voltage on a power supply wiring, noise is generated in other circuit portions. Noise present on a power supply wiring greatly limits the circuit function. One approach for alleviating the influence of switching noise on other circuit elements is to widen a power supply wiring. If the potential of a power supply wiring is pinned to a power supply voltage, the influence of switching noise can be reduced. There is a limit, however, on widening a power supply wiring because of the requirements of high integration. Other conventional proposals for preventing noise from entering other circuit elements via a power supply wiring are to form a number of pads, to form slits in parallel with a power supply wiring, or to form a power supply wiring in a lattice shape. These countermeasures intend to reduce switching noise itself by increasing the effective current capacity of a power supply wiring, and/or to alleviate the influence of noise by increasing the resistance of a path from a noise source to a connection node of a power supply wiring. These conventional approaches of suppressing noise on power supply wirings narrow a usable range of a power supply potential (lowering a high level potential and raising a low level potential) so that an operating margin of a CMOS IC device is narrowed and its operating speed is lowered. Conventional approaches of suppressing noise on power supply wirings have taken into consideration wiring resistance (R) components and capacitance (C) components, or time constants. It has been found that the approaches relying upon this technique have various restrictions. Restrictions are severe particularly at an operating frequency of 250 MHz or higher, for example in a frequency range of 250-300 MHz. According to the present invention, there is provided a CMOS IC device comprising: a semiconductor substrate; a power supply pad formed on said semiconductor substrate; circuit elements including CMOS elements formed on said semiconductor substrate; and a power supply wiring for interconnecting one of said circuit elements and said power supply pad; characterised in that said device is additionally provided with a phase-shifting split wiring which is connected to said power supply wiring and not directly connected to any of said circuit elements, and which is adapted to suppress noise by producing a phase difference between a noise signal on said power supply wiring and a noise signal on said phase-shifting split wiring. An embodiment of the present invention can provide a CMOS IC device operable at a frequency of 300 MHz or higher and having the above feature for reducing noise on power supply wirings. The power supply wiring connects a power source to a circuit element and the additional phase-shifting split wiring (branch wiring) is connected only to the power supply wiring for producing a phase difference between noise on the power supply wiring and on the split wiring. Especially at an operating frequency of 250 MHz or higher, the inductance (L) components and capacitance (C) components of a circuit play an important role. The phase-shifting split wiring (by-pass wiring) for producing a phase difference, connected to a power supply wiring for interconnecting a circuit element and a power source, adds noise components having different phases to the noise components on the power supply wiring. Noise signals having different phases are thus cancelled so that noise can be reduced. Noise on power supply wirings of a device operating at a frequency of 250 MHz or higher can thus be reduced by connecting a phase-shifting by-pass or split wiring to the power supply wiring for changing noise signal phases. If a plurality of split wirings are formed to change the phases of a plurality of noise signal waveforms, noise on a power supply wiring can be efficiently reduced. Reference is made, by way of example, to the accompanying drawings in which: Figs.1A and 1B are schematic diagrams showing the fundamental structures of power supply wirings according to embodiments of the present invention. Figs.2A and 2B are plan views showing the structures of power supply wirings according to specific embodiments of the present invention. Figs.3A, 3B, and 3C are a circuit diagram of a CMOS inverter, a plan view of a wiring, and a cross sectional view of the CMOS Inverter. Figs.4A, 4B, and 4C are graphs showing the characteristics of power supply wirings according to the embodiments of the invention, and to a conventional power supply wiring. Figs.5A and 5B are plan views showing the structures of power supply wirings according to other embodiments of the invention. Figs.6A and 6B are plan views showing the structures of power supply wirings according to other embodiments of the invention. Figs.7A and 7B are plan views showing the structures of power supply wirings according to other embodiments of the invention. Figs.8A and 8B are plan views showing the structures of power supply wirings according to other embodiments of the invention. Fig.9 is a circuit diagram of a MOS inverter circuit. Figs. 10A and 10B are a plan view and a cross-section of a wiring structure in a MOS inverter. Figs. 11,12,13,14,15 and 16 are plan views of wiring structures in a MOS inverter. Fig.17 is a cross section of a wiring structure as shown in Fig.16. Prior to the description of embodiments of the present invention, a CMOS circuit will be briefly explained. Fig.3A is a circuit diagram of an inverter of a CMOS structure. A p-channel MOS transistor (p-MOST) and an n-channel MOS transistor (n-MOST) are serially connected between power supply wirings V DD and V SS , which are connected to power supply pads PS. The gate electrodes of two MOSTs are connected in common to an input terminal IN. The interconnection between two MOSTs is connected to an output terminal OUT. Fig.3B is a plan view of a power supply wiring V DD connecting p-MOST to a power supply pad or another power supply wiring V SS connecting n-MOST to another power source pad. This wiring 51 has a thickness of t and a width of W 1 . To increase the conductance of the wiring 51, the cross sectional area of the wiring represented by a product of the thickness t and width W1 is increased in a general case. Fig.3C is a cross sectional view of a CMOS circuit. An n-type well 61 is formed in a p-type silicon substrate 60. N-type source/drain regions 62S and 62D are formed in the p-type region of the substrate 60, and p-type source/drain regions 63S and 63D are formed in the n-type well 61. Polycrystalline silicon gate electrodes 65 and 66 are formed above the channels between the source and drain, with gate oxide films being interposed therebetween. The electrodes 51, 68 and 69 are connected to the source/drain regions via openings formed in an insulating film 67. Another insulating film 70 is formed on these electrodes. This CMOS circuit structure is well known. Other known structures may also be employed. Referring to Fig.3A, if the potential at the input terminal IN is high, n-MOST turns on and p-MOST turns off so that the potential at the output terminal OUT takes a low level. Conversely, if the potential at the input terminal IN is low, n-MOST turns off and p-MOST turns on so that the potential at the output terminal OUT takes a high level. Therefore, a serial connection of n-MOST and p-MOST constitute an inverter. In such a CMOS inverter, one of the MOSTs turns off in a steady state. As a result, current does not flow or flows minimally , consuming a very small power. Current flows in a CMOS inverter only when both MOSTs turn on transiently while an input signal potential changes. At the instant when both MOSTs turn on, a large current flows in the inverter so that current flows through the power supply wirings, generating spike noise because of a voltage drop by resistance components, or other factors. Fig.3B shows a conventional CMOS circuit wiring. V DD and V SS wirings are both formed by a conductive wiring layer 51 having a fixed width as shown in Fig.3B. In order to avoid a voltage drop by a transient current, the cross sectional area of the power supply wiring layer 51 is made sufficiently large to lower the resistance sufficiently. However, a large cross sectional area of the conductive wiring layer 51 increases greatly a ratio of the wiring area to the other area occupied by other elements of a semiconductor CMOS IC device. To suppress noise on a power supply wiring , such as in a CMOS IC device operating at a frequency of 300 MHz or higher, the present inventors propose to connect a wiring or wirings having different phase shift or phase change to the power supply wiring so as to add a potential waveform having a different phase to the noise on the power supply wiring. Noise is suppressed not only from the viewpoint of wiring capacitance and resistance but also from the viewpoint of wiring inductance discernible in a high speed operation. Noise on power supply ground wirings V SS and on high potential wirings V DD is generated by the current flowing in a noise source such as an inverter. Such noise is generated more as the clock frequency rises higher. A noise margin is reduced in a low voltage operation so that the influence of noise cannot be neglected. With a scale-down of an IC, although the size of a semiconductor element becomes small and integration is improved, noise sources are concentrated. Nearby wirings are coupled by a mutual inductance so that noise becomes a serious problem. If a circuit is designed without thickening a power supply wiring, inductance in addition to wiring capacitance and resistance becomes discernible, thereby increasing noise . A method of suppressing noise from the viewpoint of wiring capacitance (C), resistance (R), and inductance (L) without thickening a power supply wiring will be described below. A voltage at an optional point x on a single wiring having R, L, and C of an equivalent circuit is represented by the following equation: V(x) = K 1 exp [- αx ] * exp [- jβx] where α is an attenuation constant, β is a phase constant, and K 1 represents a voltage at x = 0. An instantaneous value at an optional point x is given by: V(x, t) = Im [(2) 1/2 K 1 exp [- αx] * sin ( ωt - βx)] = (2) 1/2 K 1 exp [- αx] * sin ( ωt - βx) where α and β are: α = [RG - ω 2 LC + {(R 2 + ω 2 L 2 ) * (G 2 + ω 2 C 2 )} 1/2 /2] 1/2 β = [- RG - ω 2 LC + {(R 2 + ω 2 L 2 ) * (G 2 + ω 2 C 2 )} 1/2 /2] 1/2 Figs.1A and 1B show the fundamental structures of power supply wirings according to embodiments of the present invention. Fig.1A shows an example of a loop-forming split wiring whose two ends are connected to a same power supply wiring, and Fig.1B shows an example of a phase-shifting lone split wiring whose one end is connected to a power supply wiring and the other end is made free. Referring to Fig.1A, a loop-forming split wiring 2 is connected to a main wiring 1. The loop-forming split wiring 2 is a single wiring connected to the main wiring 1 at different positions to form a loop circuit. In the loop circuit, the main wiring 1 has a phase shift  1 and the loop-forming split wiring 2 has a phase shift  2 different from  1 . As a result, a phase difference of Δ=  2 -  1 is generated between signals inputted to the loop circuit at one point, transmitted through different paths in the loop circuit, and outputted to the main wiring 1 jointly at the other point. The loop-forming split wiring may be formed of a same level wiring 2 as the main wiring 1 as shown by a solid line, or of a different level wiring 2α from the main wiring 1 as shown by a broken line. Referring to Fig.1B, one end of a single phase-shifting split wiring 3 is connected to a main wiring 1. The other end of the phase-shifting split wiring 3 is not connected to any point and is made isolated. The phase-shifting split wiring 3 does not function as a general wiring and no d.c. current will flow therein. The phase-shifting split wiring 3 has a phase split of  3 . A signal entering the phase-shifting split wiring 3 from the main wiring 1 receives a phase shift of Δ= 2 3 when it is reflected at the other end of the phase-shifting split wiring 3 and returned back to the main wiring 1. The phase-shifting split wiring may also be formed of a same level wiring 3 as the main wiring or of a different level wiring 3a from the main wiring 1. In the wiring shown in Fig.1A, consider the potential of signals entering from the left side of the main wiring 1, transmitting through the main wiring 1 and transmitting through the loop-forming split wiring 2 constituting the loop circuit, and being added together at the downstream junction point of the loop circuit. The signal potential at the downstream junction point is given by the following equation: V (junction) = V(a, t) + V(b, t) where a represents the length of the main wiring 1 constituting the loop circuit and b represents the length of the loop-forming split wiring 2. Assuming that this signal is noise, a noise potential V (junction) lowers if a phase difference between V(a, T) and V(b, t) is larger than 0 and smaller than 2π. The phase difference is preferably between π/2 and 3π/2, and more preferably is between 3π/4 and 5π/4. In other words, noise amplitudes are attenuated if ωt - β 1 a - ( ωt - β 2 b) = β 2 b - β 1 a = Δ is larger than 0 and smaller than 2π. Cancellation becomes maximum when the phase difference is π. The phase constants β 1 and β 2 can be set in the range of larger than 0 and smaller than 2π because Δ can be adjusted by changing the lengths a and/or b . The following approximation is possible at a high frequency, e.g.250 MHz or higher for a CMOS IC. The numerator of the equation (3) can be represented by: RG - ω 2 LC + {(R 2 + ω 2 L 2 ) * (G 2 + ω 2 C 2 )} 1/2 = RG + ω 2 LC [- 1 + {(R 2 + ω 2 L 2 ) * (G 2 + ω 2 C 2 )/ ω 4 L 2 C 2 } 1/2 ] = RG + ω 2 LC [- 1 + {(R 2 / ω 2 L 2 + 1) * (G 2 / ω 2 C 2 + 1)} 1/2 ] = RG + ω 2 LC [- 1 + { 1 + (R 2 /L 2 + G 2 /C 2 )/ ω 2 + R 2 G 2 / ω 4 L 2 C 2 } 1/2 ] = RG + ω 2 LC [ -1 + 1 + (1/2) * (1/ω 2 ) * (R 2 /L 2 + G 2 /C 2 + R 2 G 2 / ω 2 L 2 C 2 ) + (-1/4) * (1/2!) * (1/ω 2 ) 2 * (R 2 /L 2 ...) 2 + ... = RG + LC[(1/2) * (R 2 /L 2 + G 2 /C 2 + R 2 G 2 / ω 2 L 2 L 2 ) + ( -1/4) * (1/2!) * (1/ω 2 ) * (R 2 /L 2 + ...) 2 +...] ω → ∞ : RG + LC * (1/2) * (R 2 /L 2 + G 2 /C 2 ) = (1/2LC) * (2LCRG + C 2 R 2 + L 2 G 2 ) = (1/2LC) * (CR + LG) 2 It becomes therefore that: α = {(1/2LC) * (CR + LG) 2 (1/2)} 1/2 = (R/2) * (C/L) 1/2 + (G/2) * (L/C) 1/2 Similarly, it becomes that: β = [ - RG + ω 2 LC + {(R 2 + ω 2 L 2 ) * (G 2 + ω 2 C 2 )} 1/2 /2] 1/2 ω → ∞ : [{ ω 2 LC + ( ω 2 L 2 * ω 2 C 2 ) 1/2 }/2] 1/2 = ( ω 2 LC) 1/2 = ω(LC) 1/2 The phase constants α and β change their values with L and C. The phase constant β in particular changes its value with only L and C. By using the wiring structures shown in Figs.1A and 1B and designing the main wiring and split wiring, a desired phase difference can be obtained. Figs.2A and 2B show examples of wirings having the structures shown in Figs.1A and 1B, in more concrete forms. Fig.2A shows an example of the structure of a loop-forming split wiring, and Fig.2B shows an example of the structure of a lone phase-shifting split wiring with only one end thereof connected to the main wiring. Referring to Fig.2A, the main wiring 1 and loop-forming split wiring 2 are formed by the same wiring layer. The width of the loop-forming split wiring 2 is set narrower than the width of the main wiring 1. The length of the loop-forming split wiring 2 is set longer than the corresponding length of the main wiring 1. Referring to Fig.2B, a plurality of phase-shifting split wirings 3 are branched from the main wiring 1. Each phase-shifting wiring 3 is connected at its one end to the main wiring 1, and the other end is not connected to any point and is made isolated. No circuit element is connected to the phase-shifting split wiring itself. In Fig.2B, four phase-shifting split wirings 3a to 3d are shown. The number of these split wirings is optional. The characteristics of the wiring structures shown in Figs.2A and 2B and the conventional wiring structure shown in Fig.3B were simulated for the purpose of comparison. In the structure shown in Fig.2A, the width W 1 of the main wiring 1 was set to 10µm , the distance between the junction points d 1 was set to 200 µm, the length d 2 of the loop-forming split wiring 2 was set to 1 mm, and the width W 2 thereof was set to 1 µm. For the structure of the phase-shifting split wiring shown in Fig.2B, a single split wiring having a length d of 1 mm and a width W 2 of 1 µm was used. The main wiring 1 having the same dimension as Fig.2A was used. For the structure of the conventional wiring shown in Fig.3B, a wiring having a width W 1 of 15 µm was used. These wirings were designed to be formed on a substrate having a surface insulating film and a total thickness of H 1 . These wirings were designed to have a thickness of T. The thickness of the insulating film of the substrate was set to H 2 . L, R, and C of each wiring can be expressed by the following equations: L ≃ 2 ln {6H 1 /(0.8W + T)} [nH/cm] C ≃ {1.15(W/H 2 ) + 2.8 (T/H 2 ) 0.222 }ε ox [F/m] ε ox = 8.855 * 10 -12 * 3.9 [F/m] R = (d/W) * R[] [Ω/µm] where H 1 represents a thickness of the substrate(i.e. level of the wiring), W represents a width of a wiring, T represents a thickness of a wiring, H 2 represents a thickness of an insulating film, R[] represents a sheet resistance of a wiring, and d represents a length of a wiring. By using the equations (9), L, R, and C of each wiring shown in Figs.1A and 1B and Fig.3B were calculated. Figs.4A, 4B, and 4C show changes in the noise waveforms of the wirings having the structures shown in Figs.2A and 2B and Fig.3B. Fig.4A stands for the structure shown in Fig.2A, Fig.4B stands for the structure shown in Fig.2B, and Fig.4C stands for the structure shown in Fig.3B. It is apparent that noise waveforms of the structures shown in Figs.2A and 2B attenuate considerably fast as compared to the waveform of the conventional wiring structure shown in Fig.3B. As seen from the waveforms shown in Figs.4A, 4B, and 4C, the noise amplitudes of the structures shown in Figs.2A and 2B are suppressed in 3 nsec and the noise as a whole is more effectively suppressed as compared to the conventional wiring. The effects of noise amplitude attenuation of the wirings become thus effective in the above example especially at a frequency of 250 MHz or higher, more specifically between about 250 MHz and 300 MHz. The noise suppressing effect is remarkable also in the frequency range above 300 MHz. Let us assume that a noise signal is coming from the lefthand side of Fig 2A. The noise signal is divided at point A into two parts. The divided noise signals propagate through the main wiring 1 and the loop-forming split wiring 2 and then join at point B. At point B, the joined signal voltage can be expressed as V(t) = V o q exp(-2α 1 d 1 ) sin(ωt-β 1 d 1 ) +V o (1-q) exp(-2α 2 d 2 )sin(ωt-β 2 d 2 ). Simplifying the situation by assuming that the attenuation components related with α are the same and that α 1 ≃ α 2 ≃ α and q ≃ 1-q , we get V(t) = 2C{sin(ωt-β 1 d 1 ) + sin(ωt-β 2 d 2 )} = 2C sin{ωt-(β 1 d 1 -β 2 d 2 )/2}cos{(β 1 d 1 -β 2 d 2 )/2}. For assuring attenuation of the noise amplitude, the difference between phase shift β 1 d 1 and phase shift β 2 d 2 should not be 2nπ, where n is zero or an integer. For assuring amplitude reduction by 10% or more, we get -0.9 < cos{(β 1 d 1 -β 2 d 2 )/2} < 0.9 Namely, 52° ≤ β 1 d 1 -β 2 d 2 ≤ 308° The width w and the length d of the wiring may be determined to satisfy the above-mentioned conditions. If the attenuation effects of noise amplitude of the phase-shifting split wiring shown in Fig.2B are defined to be (amplitude of combined wave)/(amplitude of initial wave), the effects can be given approximately by: { 1 + exp [- 4dα] + 2 exp [- 2dα] * cos (2dβ)} 1/2 where d is the length, α the attenuation constant, and β the phase constant of the phase-shifting split wiring. In order to give such effects, the value of this equation is required to be smaller than 1. That is to say, the following inequality is to be satisfied to give the effects: cos (2dβ) < - (exp [- 2dα]/2) The wiring length d and width W are selected so as to satisfy the above condition. The condition for the loop-forming split wiring may also be derived by solving the equation of the combined wave in the manner similar to the phase-shifting split wiring. In Figs.2A and 2B, the split wiring is constituted by a straight wiring or a set of straight wirings. The shape of the split wiring is not limited to such wirings, but various other shapes of wiring may be used if only a signal transmitted to the split wiring can be superposed on a signal transmitted to the main wiring at a different phase. The split wiring is used for suppressing noise on the main wiring, and current consuming circuit elements are not connected to the split wiring. In a semiconductor integrated circuit device, power supply wirings are connected to power supply pads formed for example in a peripheral portion of a chip, and the power supply pads are connected to terminals such as leads of a lead frame by gold lead wires. These lead wires have inductance. If noise on the power supply wirings is transferred to lead wires, voltage waveforms may oscillate by the inductance of the lead wires and resistance of the pads and lead wires. Figs.5A and 5B show examples of the structures which allow noise on power supply wirings to be suppressed on the pad side. In Fig.5A, a power supply wiring 11 is disposed at the peripheral area of a chip generally parallel to bonding pads 15, and connected to power supply pads 15 via connection areas or neck portions 14 at a plurality of chip peripheral areas. Phase-shifting split wirings are connected to the connection areas 14 between the power supply wiring 11 and power supply pads 15. For example, in the case of the power supply pad 15b, two phase-shifting split wirings 12a and 12b are branched from the connection area 14b between the power supply wiring 11 and power supply pad 15b, on the both sides thereof. The widths and lengths of the phase-shifting split wirings 12a and 12b can be determined in accordance with the above-described analysis so as to reduce noise . The determined values may be modified after testing the noise on a power supply wiring having a sample split wiring. In Fig.5A, phase-shifting split wirings are formed on both the sides of the connection area connected to the power supply pad. Only one side of the connection area may be connected to a phase-shifting split wiring. Fig.5B shows phase-shifting wirings connected to only one side of connection areas connected to power supply pads. A phase-shifting split wiring 12 is connected to the left side of the connection area 14b between the power supply line 11 and power supply pad 15b. The cross sectional area and length of each phase-shifting split wiring can be determined in accordance with the above-described analysis and by checking the test result of a sample phase-shifting split wiring. Figs.5A and 5B show examples of the structures of phase-shifting split wirings whose one ends are connected to the connection area and the other ends are isolated. A loop-forming split wiring may be formed near the power supply pad. Figs.6A and 6B show examples of the structures of power supply wirings having loop-forming split wirings near power supply pads. In Fig.6A, loop-forming split wirings 12a and 12b are connected to both the sides of connection areas 14 at the chip peripheral areas between the power supply wiring 11 and power supply pads 15. The cross sectional area and length of each loop-forming split wiring 12a, 12b can be determined in accordance with the above-described analysis and by checking the test result of a sample phase-shifting split wiring. In Fig.6A, two loop-forming split wirings are formed on both the sides of the connection area. The number of loop-forming split wirings is not limited to two. In Fig.6B, a loop-forming split wiring 12 is connected to one side of a connection area 14 between the power supply wiring 11 and power supply pad 15. It is obvious to those skilled in the art that split wirings for suppressing noise on a power supply wiring shown in Figs.5A and 5B and Figs.6A and 6B can be selectively used by considering the pitch between power supply pads or the like. Presence of split wirings connected to a power supply wiring for suppressing noise on a power supply wiring increases a chip area necessary for patterning a power supply wiring. If split wirings connected to a plurality of power supply wirings are disposed by being juxtaposed with each other, the chip area necessary for forming split wirings can be effectively used. Figs.7A and 7B show examples of the structures of phase-shifting split wirings whose one ends are connected to power supply wirings and other ends are isolated, the phase-shifting wirings being disposed in an inter-digital form. In Fig.7A, two power supply wirings 11a and 11b are disposed in parallel. In the area where a pair of power supply wirings faces each other, a plurality of split wirings 13a are formed extending from one power supply wiring 11a, and another plurality of split wirings 13b are formed extending from the other power supply wiring 11b. The extending split wirings 13a and 13b are alternately disposed to constitute an inter-digital form. In the structure shown in Fig.7A, two power supply wirings face each other and split wirings extend from one wiring to the other wiring and from the other to the one. Three or more power supply wirings may be disposed in parallel, and the similar structure to the above may be used. In Fig.7B, power supply wirings 11a, 11b, 11c, and 11d are disposed in parallel. For example, the two power supply wirings 11b and 11c have split wirings 13b and 13c extending from both sides of the power supply wirings 11b and 11c. These split wirings are alternately disposed and meshed with one another extending from the power supply wirings 11b and 11c on opposite sides thereof to constitute an inter-digital form. Split wirings 13b extend from opposite sides of the power supply wiring 11b at right and left positions thereof displaced from one another. On the other hand, split wirings 13c extend from opposite sides of the power supply wiring 11c at the same right and left positions thereof. The connections of split wirings can be modified in various ways as described above. Use of a plurality of split wirings allows noise on power supply wirings to be suppressed more effectively. Figs.8A and 8B show examples of the structures of power supply wirings each having a plurality of loop-forming split wirings. In the structure shown in Fig.8A, loop-forming split wirings 12a and 12b having the same shape are symmetrically connected to both the sides of a power supply wiring 11. In Fig.8B, loop-forming split wirings 12a and 12b are connected to both the sides of a power supply wiring 11 in a staggered manner. The noise-reducing wiring structure as described above can be formed at such places where noise occurrence disturbs the circuit function, for example in a CMOS circuit. Fig.9 shows a circuit diagram of a CMOS circuit. In Fig.9, two inverters INVa and INVb are connected in parallel between the source voltage line V DD and the ground potential line GND. A first inverter INVa is formed of a pMOS transistor Q 1 and an nMOS transistor Q 2 connected in series between the source voltage line V DD and the ground line GND. The gates of the transistors Q 1 and Q 2 are commonly connected to an input terminal Vin1 and the output terminal Vout is connected to a load La. Another inverter INVb is similarly formed of a pMOS transistor Q 3 and an nMOS transistor Q 4 connected in series between the source voltage line V DD and the ground line GND. The gates of the transistors Q 3 and Q 4 are commonly connected to an input terminal Vin2, and the output terminal Vout is connected to a load Lb. When the input signal Vin1 is changed from the high "1" state to a low "0" state, the pMOS transistor Q 1 will be turned on, to allow a current to flow therethrough to the load La. At this point, the current begining to flow from V DD to the load La will cause noise in wiring. This noise will be transmitted and give influence to the neighboring inverter INVb. When the potential of the voltage source line is lowered by the current flowing into the load La, the source voltage for the inverter INVb is lowered. If the input signal Vin2 changes from a "1" state to "0" state at this moment, the lowering of the source voltage will reduce the effect of the input signal change. That is to say, the change in the input signal Vin2 will give only a reduced effect to the transistor Q 3 . Then, the action of the pMOS transistor Q 3 is slowed down. Therefore, the rising speed of the inverter INVb is lowered. A similar phenomenon will occur when the inverter INVb is first driven and then another inverter INVa is then driven. If the input signal changes from a low level ("0") to a high level ("1"), the nMOS transistor Q 2 or Q 4 is turned on to discharge the charge at the load La or Lb. Such a current may raise the potential of the ground line GND. If the potential of the ground line GND is raised, the action of the nMOS transistor Q 2 or Q 4 is slowed down. For preventing the reduction of the operation speed of the inverter, it is preferable to avoid the effect of the noise in such a CMOS circuit. Figs.10A and 10B show an example of a basic structure of a CMOS inverter. Fig.10A shows a plan view and Fig.10B shows a cross section. In Fig.10A, a pMOS transistor is formed in the upper part and an nMOS transistor is formed in the lower part. A p-type source region 31S and a p-type drain region 31D are formed in an n-type well 22. A gate electrode 25 is disposed between the source region 31S and the drain region 31D. An n-type source region 32S and an n-type drain region 32D are formed in a p-type substrate. The gate electrode 25 extends vertically between the source region 32S and 32D. A local interconnect 33 connects the p-type drain region 31D and the n-type drain region 32D. A source voltage (V DD ) line 28 extends horizontally in the upper part of the figure and a ground line 27 extends horizontally in a lower part of the figure. A contact CT1 connects the voltage source line 28 with the source region 31S of the pMOS transistor and a contact CT2 connects the ground line V SS with the source region 32S of the nMOS transistor. Contact CTw represents the connection between the source voltage line 28 and the n-type well 22, and a contact CTs represents the connection between the ground line 27 with the substrate. Fig.10B shows a cross section along line XB-XB in Fig 10A. In a p-type substrate 21, an n-type well 22 is formed. A field oxide film 23 and a gate oxide film 24 are formed in the surface of the substrate 21. A poly-crystalline silicon gate electrode 25 is formed on the gate oxide film 24. An inter-layer insulating layer 26 such as SiO 2 26 covers the gate electrode 25. On the inter-layer insulating film 26, a source voltage line 27 and a ground line 28 are formed. If a current suddenly begins to flow in the source voltage line 28 or a ground line 27, noise may be generated and give influence on the other circuit elements. Fig.11 shows a wiring structure capable of reducing the effect of noise. Compared to the basic structure shown in Fig.10, loop-forming split wirings 35A are connected to the ground wiring 27, and loop-forming split wirings 35B are connected to the voltage source wiring 28. These loop-forming wirings 35 are formed of a metal layer at the same level as the power supply wirings 27 and 28. Fig.12 shows another structure capable of reducing the effect of noise. Lone split wirings 36A1, 36A2, 36A3,... are connected to, or project from the ground wiring 27, and lone split wiring 36B1, 36B2, 36B3,... are connected to, or project from the voltage source wiring 28. The power supply wirings may be formed in multiple layers. Noise-reducing split wirings may be formed in every wiring layer in such a case. Fig.13 shows an example of multi-layer power supply wiring. In this figure, in addition to the wiring structure as shown in Fig.11, another power source wiring layer is formed thereabove. A ground wiring 41 extends vertically in the figure, and is connected to the lower level ground wiring 27 through contacts CT8 and CT9. A voltage source wiring 42 also extends vertically and is connected to the lower level voltage source wiring 28 through contacts CT6 and CT7. Loop-forming split wirings 37A and 37B are connected to the ground wiring 41 and voltage source wiring 42. In this way, phase-shifting loop-forming split wirings are formed in both the lower and the upper power supply wirings. Fig.14 shows another example of a multi-layer power supply wiring. In this figure, in addition to the power supply wiring as shown in Fig.12, an upper level power supply wirings are formed thereabove. An upper level ground wiring 41 extends vertically and is connected to the lower level ground wiring 27 through contacts CT13 and CT14. An upper level voltage supply wiring 42 extends vertically and is connected to the lower level voltage source wiring 28 through contacts CT11 and CT12. Lone split wirings 38A and 38B are connected to the upper level ground wiring 41 and the upper level voltage source wiring 42, respectively. In the above structures, the power supply wiring and the phase-shifting split wiring are formed in the same level. The phase-shifting split wiring can be formed in a different level from the power supply wiring. Fig.15 shows a structure of power supply wirings in which different level phase-shifting split wirings are connected thereto. In this figure, the power supply wirings 27 and 28 are covered by an inter-layer insulating film and another wiring layer including phase-shifting split wirings is formed thereon. Loop-forming split wirings 39A1 and 39A2 are connected to the lower level ground wiring 27 through contacts CT15-CT18. Further, the loop-forming split wiring 39A1 projects upward while the other loop-forming split wiring 39A2 projects downward. Also, loop-forming split wiring 39B1 and 39B2 are connected to the lower level voltage source wiring 28 through contacts CT21-CT24. Fig.16 shows another structure of phase-shifting split wiring in different layer. In this figure, lone split wirings 40A1, 40A2, 40A3,... are connected to the lower Level ground wiring 27 through contacts CT25, CT26, CT27,.... Lone split wirings 40B1, 40B2, 40B3,... are connected to the lower level voltage source wiring 28 through contacts CT28, CT29, CT30,.... In FIgs.15 and 16, phase-shifting split wirings project upward and downward from the contacts. Fig. 17 shows a cross section of the structure in Fig. 16. In this figure, a p-type well 35 is formed in a p-type substrate 21. An n-type source 31S and an n-type drain 31D are formed in the p-type well 35. A polycrystalline silicon gate electrode 25 is formed above the channel between the source region 31S and the drain region 31D through a gate oxide film 24. An inter-layer insulating oxide 26 covers the transistor structure. A lower level power supply wiring 27 (28) extends on the inter-layer insulating film 26. Another inter-layer insulating film 44 is formed to cover the lower level power supply wiring 27 (28). An upper level power supply wiring 40A is formed on the inter-layer insulating film 44 and is connected to the lower layer power supply wiring 27 (28) through contact holes in the inter-layer insulating film 44. Another insulating film 46 covers the upper level power supply wiring 40A. In such multi-layer noise-reducing structure as shown in Figs.15-17, the material of the power supply wiring and the phase-shifting split wiring may be differentiated. In such a case, the resistivity of the wiring material can be employed as a parameter for determining the phase constant. The power supply wirings can also be formed in three layers or more. Phase-shifting split wirings may be connected to the power supply wiring at any level at any place where there is a space for forming such phase-shifting split wiring. In the above-described embodiments, wirings such as power supply wirings are made of Al, Al alloy, refractory metal such as tungsten, cobalt, titanium, molybdenum, tantalum, or refractory metal silicide, and formed on an insulating film such as silicon oxide above the surface of a semiconductor substrate such as silicon. Patterning of wirings can be performed by using known photolithography. The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent to those skilled in the art that various modifications, substitutions, combinations and the like can be made without departing from the scope of the appended claims.

Claims: A CMOS IC device comprising: a semiconductor substrate; a power supply pad formed on said semiconductor substrate; circuit elements including CMOS elements formed on said semiconductor substrate; and a power supply wiring for interconnecting one of said circuit elements and said power supply pad; characterised in that said device is additionally provided with a phase-shifting split wiring which is connected to said power supply wiring and not directly connected to any of said circuit elements, and which is adapted to suppress noise by producing a phase difference between a noise signal on said power supply wiring and a noise signal on said phase-shifting split wiring. A CMOS IC device according to claim 1, wherein said phase-shifting split wiring and said power supply wiring form a loop, and the phase shift of the signal on that part of said power supply wiring which forms said loop is different from the phase shift of the signal on said phase-shifting split wiring, and the difference is not 2nπ where n is an integer. A CMOS IC device according to claim 1, wherein said phase-shifting split wiring has one end connected to said power supply wiring and the other end isolated, and the phase shift of the signal transmitted from said one end, reflected from said other end, and returned back to said one end takes a finite value except 2nπ, where n is zero or an integer. A CMOS IC device according to claim 1, wherein said phase-shifting split wiring has a plurality of split wirings branching from both sides of said power supply wiring, at least some of said split wirings and said power supply wiring form loops, and the phase shift of the signal on said power supply wiring at each of said loops is different from the phase shift of a signal on said split wiring at each of said loops. A CMOS IC device according to claim 1, wherein said phase-shifting split wiring has a plurality of split wirings branching from both sides of said power supply wiring, at least some of said split wirings have one ends connected to said power supply wiring and the other ends thereof being isolated, and the phase shift of a signal transmitted from said one end, reflected from said other end, and returned back to said one end of each of said split wirings takes a finite value except 2nπ, where n is zero or an integer. A CMOS IC device according to claim 1, wherein two of said power supply wirings are disposed facing each other, at least one phase-shifting split wiring is connected to each of said power supply wirings, and said phase-shifting split wirings each have a tooth shape meshing with one another to form an inter-digital configuration. A CMOS IC device according to any of claims 1 to 6, wherein said phase-shifting split wiring is made of a conductive member having a cross sectional area smaller than said power supply wiring. A CMOS IC device according to claim 2 or 4, wherein, in said loop, the power supply wiring has a length d 1 and a phase constant β 1 , the phase-shifting split wiring has a length d 2 and a phase constant β 2 , and the difference between phase shift β 1 d 1 and phase shift β 2 d 2 is not equal to 2nπ, where n is zero or an integer. A CMOS IC device according to claim 8, wherein the difference between the phase shifts is between 52 degrees and 308 degrees. A CMOS IC device according to claim 3 or 5, wherein said phase-shifting split wiring has an attenuation constant α, a phase constant β and a length d, which satisfy cos (2dβ) < -exp (-2dα)/2. A CMOS IC device according to any of claims 1 to 10, wherein said power supply pad is located at a peripheral region of said semiconductor substrate, and said phase-shifting split wiring is located adjacent to said bonding pad in said peripheral area. A CMOS IC device according to claim 11, wherein there are provided a plurality of said power supply pads, said power supply wiring includes a common potion running across neighborhoods of said power supply pads, and neck portions connecting said common portion and said power supply pads, and said phase-shifting split wiring is connected to each of said neck portion. A CMOS IC device according to claim 12, wherein said phase-shifting split wiring has an elongated shape parallel to said common portion. A CMOS IC device according to claim 12, wherein said of said phase-shifting split wirings has one end connected to the associated neck portion of the power supply wiring and the other end isolated. A CMOS IC device according to claim 12, wherein each of said phase-shifting wirings has both ends connected to different points of the associated neck portion of the power supply wiring. A CMOS IC device according to claim 12, wherein each of said phase-shifting split wirings has a plurality of split wirings branching from both sides of the associated neck portion of said power supply wiring. A CMOS IC device according to any preceding claim, wherein said phase-shifting split wiring has a different level from that of said power supply wiring. A method of making a CMOS IC device, the device comprising: a semiconductor substrate; a power supply pad formed on said semiconductor substrate; circuit elements including CMOS elements formed on said semiconductor substrate; and a power supply wiring for interconnecting one of said circuit elements and said power supply pad; the method characterised by comprising a step of: suppressing noise on said power supply wiring by forming a phase-shifting split wiring connected to said power supply wiring and not directly connected to said circuit elements, said phase-shifting split wiring being adapted to produce a phase difference between a noise signal on said power supply wiring and a noise signal on said phase-shifting split wiring. A method according to claim 18, wherein said phase-shifting split wiring and said power supply wiring form a loop, further comprising a step of: selecting length and width of the power supply wiring and the phase-shifting split wiring so that the phase shift of a signal on that part of said power supply wiring which forms said loop is different from the phase shift of a signal on said phase-shifting split wiring, and the difference is not 2nπ where n is an integer. A method according to claim 18, wherein said phase-shifting split wiring has one end connected to said power supply wiring and the other end being isolated, further comprising a step of: selecting length and width of said phase-shifting split wiring so that the phase shift of a signal transmitted from said one end, reflected from said other end, and returned back to said one end of said phase-shifting split wiring takes a finite value except 2nπ, where n is zero of an integer. A method according to claim 19, wherein said selecting step includes selecting the width and length of said power supply wiring and said phase-shifting split wiring in such a manner that, in said loop, the power supply wiring has a length d, and a phase constant β 1 , the phase-shifting split wiring has a length d 2 and a phase constant β 2 , and the difference between phase shift β 1 d 1 and phase shift β 2 d 2 is not equal to 2nπ, where n is zero or an integer. A method according to claim 21, wherein the difference between the phase shifts is between 52 degrees and 308 degrees. A method according to claim 22, wherein said selecting step includes selecting the width and length of said phase-shifting split wiring in such a manner that said phase-shifting split wiring has an attenuation constant α, a phase constant β and a length d, which satisfy cos (2dβ) < -exp(-2dα)/2.

Inventors: SATO TOMIO, TATSUOKA MASATO, SATO, TOMIO, TATSUOKA, MASATO, SATO, TOMIO, FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1994
Main classification: H01L23
IPC codes: H01L23