METHOD OF AC-DRIVING LIQUID CRYSTAL DISPLAY, AND THE SAME USING THE METHOD

Abstract: First and second source bias voltages (V S+ , V S- ) are generated alternately every frame period. The polarity of a gradation level signal (V a ) given to each picture element on a selected gate bus is inverted every frame period, the resultant signal is added to the source bias voltages. V S+ , and V S- , and the obtained source voltages (V S ) are outputted to the respective source buses. A gate voltage (V G ) given to each gate bus comprises a period of a high-level gate pulse which causes a thin film transistor to conduct during the time nearly equal to the horizontal scanning interval (H) in each frame period, a gate bias period which precedes continuously the rise of the high-level gate pulse and in which the gate voltage (V G ) takes first and second gate bias voltages (V x1 , V x2 ) alternately every frame period, and a low-level period other than the above two periods. The high-level gate pulses given to the respective gate buses are shifted in time by the horizontal scanning interval (H) from each other in succession. The gate bias period in the i-th row has the time width from the rise of the high-level gate pulse of the i-th row to a time point after the fall of the preceding high-level gate pulse in the (i-1)-th row. Thereby, the first and second gate bias voltage (V x1 , V x2 ), which are given in the i-th row, are applied alternately to the picture elements in the (i-1)-th row, correspondingly to each negative or positive write period in alternating current drive, and flickers generated in the liquid crystal display are reduced.

Description: TECHNICAL FIELD The present invention relates to an AC-drive method for an active matrix liquid crystal display and, more particularly, to an AC-drive method which is intended to lessen display flicker and reduce power consumption by combining a bias voltage with a display drive voltage. The display image quality by the active matrix liquid crystal display (hereinafter referred to as AMLCD) has been drastically improved in recent years. The prior art device has, however, a problem of flicker and a problem that a fixed image is printed immediately after being displayed; various solutions to these problems have been reported. In view of its use such as a liquid crystal TV or the like, it is desirable that the AMLCD be driven with as low power consumption as possible. Solutions to the flicker problem are disclosed in Japanese Pat. Laid-Open Gazette Nos. 29893/86 and 59493/86. The methods proposed therein, however, do not compensate for a DC voltage which is caused by the dielectric anisotropy of the liquid crystal material used and a parasitic capacitance in the AMLCD itself, and hence do not reduce the flicker for each display pixel but merely lessen apparent flicker all over the display screen. A method for reducing the power consumption of the source driver is proposed in Japanese Pat. Laid-Open Gazette No. 116923/87, for instance, but the proposed method does not compensate for the DC voltage by the dielectric anisotropy either. The drive method which compensates for the DC voltage attributable to the dielectric anisotropy is set forth in "Compensation of the Display Electrode Voltage Distortion" (Japan Display '86, p. 191-195; this will hereinafter be referred to as literature 1) and "COMPENSATIVE ADDRESSING FOR SWITCHING DISTORTION IN A-SI TFTLCD" (Euro Display '87, p. 107-110; this will hereinafter be referred to as literature 2). Literature 1 proposes a method which compensates for the DC voltage by changing the amplitude of an image signal voltage between positive and negative sides of its amplitude center. This method is defective in that the positive-negative amplitude ratio needs to be changed in accordance with the magnitude of the image signal. Literature 2 proposes a method which applies a correcting pulse via a capacitance provided in an adjacent gate line; the above-mentioned DC voltage is not generated in principle. The both methods compensate for the DC voltage but do not provide any improvements in the reduction of power dissipation of the source driver. A method which cuts the power consumption of the source driver as well as compensates for the DC voltage is proposed in Japanese Pat. Laid-Open Gazette No. 157815/90 and EP-A-O 373 565. This method has, however, such a defect as mentioned below. After writing into pixel capacitors image signals corresponding to the positions of the pixels, it is necessary to turn OFF TFTs (thin film transistors) to hold therein the written charges. To perform this, the voltage that is applied to the gate of each TFT to turn it OFF needs to have a potential which sufficiently reduces its source-drain current I DS . According to the disclosure of Pat. Laid-Open Gazette No. 157815/90, the write of the image signals into the pixel capacitors is followed by the application of a pulse V e(+) or V e(-) . This impairs the charge retaining characteristic of the pixels. The same technique is disclosed in US-A-5,151,805. Incidentally, the method of literature 2 uses, as a pulse -V E the pulse identified by V e(-) in Pat. Laid-Open Gazette No. 157815/90, and hence has the same defect as does the latter. A method according to the precharacterizing part of claim 1 and an active matrix liquid crystal display according to the precharacterizing part of claim 13 are disclosed in JP-A-4 367 821. A first object of the present invention is to provide a method for AC-driving liquid crystal display which provides improved charge retaining characteristic of the pixels and a liquid crystal display using the method. A second object of the present invention is to provide a method for AC-driving liquid crystal display which reduces the output power of the source driver and a liquid crystal display using the method. A third object of the present invention is to provide a method for AC-driving liquid crystal display which is capable of compensating for the DC voltage which is caused by the dielectric anisotropy of liquid crystal or the like and a liquid crystal display using the method. These objects are achieved with a method as claimed in claim 1 and an active matrix liquid crystal display as claimed in claim 13. Preferred embodiments of the invention are subject-matter of the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is an equivalent circuit diagram illustrating the electrical construction of a liquid crystal display to which the present invention is applied. Fig. 1B is an equivalent circuit diagram of one pixel and its vicinity in Fig. 1A. Fig. 2 is a waveform diagram for explaining the operation of the principal part of the display depicted in Fig. 1. Fig. 3A is an equivalent circuit diagram for explaining the migration of charges at the time when a TFT is in the ON state in Fig. 1B. Fig. 3B is an equivalent circuit diagram for explaining the migration of charges at the time when the TFT is in the OFF state in Fig. 1B. Fig. 4A is a waveform diagram for explaining one driving method in Fig. 1B. Fig. 4B is a diagram showing waveforms occurring in the principal parts when changing the drain voltage V Dpp while holding the source voltage V Spp unchanged in Fig. 4A. Fig. 5A is a waveform diagram for explaining another driving method in Fig. 1B. Fig. 5B is a diagram showing waveforms occurring in the principal parts when changing the source voltage V Spp while holding the drain voltage V Dpp unchanged in Fig. 5A. Fig. 6A is a diagram showing an approximately equivalent circuit for driving one source bus by the source driver in Fig. 1A. Fig. 6B is a graph showing an example of the applied voltage vs. transmittivity characteristic of liquid crystal. Fig. 6C is a diagram showing an approximately equivalent circuit for driving one gate bus by the gate driver in Fig. 1A. Fig. 7 is a diagram illustrating, by way of example, the gate driver and voltage source circuits for generating drive voltages to be applied to the gate driver in Fig. 1A. Fig. 8A is a waveform diagram showing the time relationship between the gate pulse P G of the gate voltage V G1 and the second bias voltage V x2 of the gate voltage V Gi+1 in Fig. 1A, with Δ 1 > 0 and Δ 2 > 0. Fig. 8B is a waveform diagram when Δ 1 = t 6 - t 5 < 0 . Fig. 8C is a waveform diagram when t 7 = t 8 (Δ 2 = 0) . Fig. 8D is a waveform diagram when Δ 1 extends over a plurality of rows. Fig. 9 is a waveform diagram when rise and fall times are present at leading and trailing edges of the gate pulse and the second bias voltage, respectively, in Fig. 8A. Fig. 10 is a waveform diagram for explaining the operation when the gate pulse P G is not added to the gate voltage V Gm+1 of the last gate bus alone in Fig. 1A. BEST MODE FOR CARRYING OUT THE INVENTION Fig. 1A is an equivalent circuit diagram showing the principal part of the AMLCD according to the present invention, Fig. 1B is an equivalent circuit diagram of one pixel on an i-th row of the display panel and Fig. 2 a waveform diagram showing drive signals for application to pixels in Fig. 1A according to the present invention. A source driver 2 has connected thereto n columns of source buses S 1 - S n and a gate driver 3 m+1 rows of gate buses G 1 - G m+1 . In a mesh or area defined by the gate buses G i , G i+1 (i = 1 to m) and the source buses S j (j = 1 to n), there is disposed a liquid crystal pixel L ij . In the vicinity of the intersection of the gate bus G i and the source bus S j , there is disposed a TFT Q ij which is electrically connected to the respective buses. One of electrodes which hold therebetween a liquid crystal cell 4 of each liquid crystal pixel L ij is used as a display electrode 4a, which is connected to the drain D of the TFT Q ij , and the other electrode is used as a common electrode 4b common to all cells. Each pixel L ij has a signal storage capacitor 5. The one electrode of the capacitor 5 is connected to the display electrode 4a and the other to the gate bus G i+1 . The source driver 2 provides to source buses S j at the same time, for application to the respective j columns of pixels L 1j , L 2j , ..., L mj , signal voltages (referred to also as source bus drive voltages or source voltages) V 1j , V 2j , ..., V mj (identified generically by V Sj or V S ) of a duration substantially equal to or shorter than one horizontal scanning time H. The gate driver 3 supplies the gate buses G 1 , G 2 , ..., G m+1 one after another with pulse-like scanning voltages (referred to also as gate bus drive voltages or simply as gate voltages) V G1 , V G2 , ..., V Gm+1 which remain low-level except for substantially one horizontal scanning period H and are sequentially displaced one horizontal scanning period apart in phase. By this, TFTs on each row are sequentially selected and turned ON. Fig. 1B is a diagram showing an equivalent circuit of the pixel in one mesh in Fig. 1A. In Fig. 1B, C gd denotes a parasitic capacitance between the gate and drain of the TFT, C LC the pixel capacitance of the liquid crystal cell 4 and C S the storage capacitance of the signal storage capacitor 5. Fig. 2 shows typical waveforms of the source voltage V Sj (identified by V S for brevity's sake), the gate voltage V Gi , V Gi+1 and a drain voltage V D at the time of driving the liquid crystal pixel L ij in the Fig. 1B embodiment. Incidentally, V C denotes a common voltage that is applied to the common electrode 4b. V S- and V S+ denote bias voltages (source voltages when a display gray-scale level signal V a is zero) that are used to effect a negative and a positive write for AC-wise driving of the liquid crystal pixel, respectively. The gray-scale level signal V a is indicated by the arrow, the length and direction of the arrow indicating the magnitude of the signal and the polarity in which the signal is written in the pixel. In this specification, charging of the pixel capacitor from the source bus through the TFT turned ON by a gate pulse P G of a select level is called a write. For AC-wise driving of the liquid crystal cell, the gray-scale level signal V a is written into the pixel with the polarity inverted every frame; the write of the positive gray-scale level signal V a is called a positive write and the write of the negative signal V a a negative write. Usually, a commercially available source driver for AMLCD can be used to implement a source driver circuit equivalent to the source driver which, for the above-mentioned AC-wise driving of the liquid crystal cell, applies first and second source bias voltages to the source bus alternately with each other and adds the gray-scale level signal V a to the bias voltages while inverting its polarity. The difference between a non-select level (a level at which to turn OFF the TFT) and a select level (a level at which to turn ON the TFT) of the gate voltage V G is represented by Vg and the two bias voltages that are provided following an AC-wise signal (not shown) are identified by V x1 and V x2 . The gate voltage V Gi (i = 1 to m+1) which is applied to each gate bus G i from the gate driver 3 has in every frame period a rectangular gate pulse P G of the high level (the select level) V GH with a fixed duration shorter than the horizontal scanning period H and the remaining portion of the low level V GL . In the first aspect of the present invention, it is the most outstanding feature that the gate voltage V Gi on each gate bus G i has a period of about 1H width (in the example of Fig. 2, for a period 1H + Δ 1 is longer than 1H but shorter than one frame period) immediately preceding the gate pulse P G in which the first and second bias voltages V x1 and V x2 alternate every frame. Hence, the periods of the first and second gate bias voltages on the gate bus G i each cover at least the fall time or entire duration of the gate pulse P on the immediately preceding gate bus G i-1 . Accordingly, the first and second gate bias period on an i-th row correspond to the negative and positive write periods in the AC-wise driving of pixels on an (i-1)th row, respectively. Similarly, the gate voltage V Gi+1 which is applied to the gate bus G i+1 contains the first and second bias voltages V x1 and V x2 which are added to the low level V GL during the negative write and positive write in the pixel L ij , respectively, as shown in Fig. 2. In the fourth aspect of the present invention described later, provision is made for preventing the gate voltage V Gm+1 to the last gate bus from having the gate pulse P G as depicted in Fig. 10. The reason for this is that neither pixels nor TFTs are provided on the row m+1 and that the exclusion of the gate pulse does not exert bad influence on the pixels and TFTs on the m-th row. Next, the present invention will be described in detail following the elapse of time from t 0 to t 3 shown in Fig. 2. In t ≦ t 0 the drain voltage V D of each TFT on the i-th row, written therein at the time of application of the gate select pulse (the gate pulse) P G in the preceding frame, is being held at a shifted potential. In the subsequent period t 0 < t < t 1 the TFT on the i-th row is turned ON by the select pulse P G and new data is written by the source voltage V S . In consequence, the capacitors C gd , C LC and C S are charged until the drain potential V D reaches the source potential V S = V S- - V a . At t = t 1 the gate potential V GH drops to the level V GL . Fig. 3A shows an equivalent circuit including the gate driver at t 0 < t < t 1 and Fig. 3B a similar equivalent circuit at t 1 < t < t 2 . In Fig. 3A, since the TFT is ON, the potential at a circuit point 11, that is, the drain voltage is equal to V S . Accordingly, the total amount of charges, q A , that are stored in the capacitors C gd , C LC and C S is as follows: q A = C LC (V S - V C ) + C S (V S - V x1 ) + C gd (V GH - V S ) Letting the drain potential at the circuit point 11 in Fig. 3B be represented by V D , the total amount of charges, q B , that are stored in the capacitors C gd , C LC and C S is as follows: q B = C LC (V D - V C ) + C S (V D - V x1 ) + C gd (V D - V GL ) Since Eqs. (1) and (2) are equal according to the principle of conservation of charge, the following equation (3) holds. C LC (V S - V C ) + C S (V S - V x1 ) + C gd (V S - V GH ) = C LC (V D - V C ) + C S (V D - V x1 ) + C gd (V D - V GL ) Rearranging Eq. (3), we have (C LC + C S + C gd )(V S - V D ) = C gd ·(V GH - V GL ) Hence, V S - V D = [C gd /(C LC + C S + C gd )](V GH - V GL ) Setting V S - V D = dV P Eq. (4) becomes as follows: dV P = [C gd /(C gd + C S + C LC )](V GH - V GL ) That is, the drain voltage V D shifts downward by dV P expressed by Eq. (6). Incidentally, it is known from the afore-mentioned literature 1, for instance, that the drain voltage V D shifts by the gate pulse as mentioned above. In the period t 1 < t < t 2 , since the TFT on the i-th row is OFF, the drain voltage V D remains unchanged and is held at V S - dV P . At t = t 2 , the select level V GH is provided to the gate of the TFT on the (i+1)th row. By this, the drain potential at the circuit point 11 on the i-th row shifts in proportion to the potential V GH applied from the C S side in Fig. 3B. The shift amount dV Q is calculated on the same principle as that for the shift of the drain voltage by Eq. (6), and the drain potential shifts upward by dV Q which is given by the following equation (7). dV Q = [C S /(C gd + C LC + C S )](V GH - V x1 ) In the period t 2 < t < t 3 , the drain potential V D of the TFT on the i-th row remains unchanged. At t = t 3 , the non-select level V GL is provided to the gate of the TFT on the (i+1)th row. By this, the drain potential V D on the i-th row shifts in proportion to the applied potential. The shift amount dV R is calculated on the same principle as that for the shift by Eq. (6), and the drain potential shifts downward by the amount that is given by the following equation (8). dV R = [C S /(C gd + C LC + C S )](V GH - V GL ) After all, the total shift amount ΔV C '' of the drain potential V D in the period from t = t 1 to t = t 3 is expressed by the following equation. ΔV C '' = dV P - dV Q + dV R Substitution of Eqs. (6), (7) and (8) into Eq. (9) gives ΔV C '' = [C gd /(C gd + C LC + C S )](V GH - V GL ) + [C S /(C gd + C LC + C S )](V x1 - V GL ) Letting V D- (the minus sign meaning the negative write) denote the drain voltage on the i-th row in the period t 3 ≦ t < t 4 from time t 3 the gate pulse P G applied to the gate of the TFT on the (i+1)th row falls to the time immediately preceding time t 4 the second bias voltage V x2 is applied to the gate of the TFT on the i-th row, it is expressed as follows: V D- = V S- - V a - ΔV C '' The potential difference between the drain voltage V D- and the common voltage V C is held as a display voltage for the liquid crystal cell 4 of the pixel L ij concerned in the frame FR_ in which the negative write was effected. In the period t 4 < t ≦ t 6 of the second bias voltage V x2 which is provided to the gate bus G i of the i-th row in the frame FR + period in which to effect the positive write -- in Fig. 2 the drain potential V D is shown to vary in accordance with gate waveforms on the gate buses G i and G i+1 on the assumption that the TFT is OFF -- even if the TFT is in the ON state and its drain potential undergoes whatever variations in this period, it does not exert any influence on the drain potential at t ≧ t 7 since in the period t 6 < t < t 7 following time instant t 6 new data is written into the TFT by the gate pulse P G which is applied to the gate bus G i . For this reason, no description will be made of the fluctuation of the drain potential in this period. During the period t 6 < t < t 7 for which the gate pulse P G is fed to the gate bus G i , the TFT of the i-th row is ON, and consequently, the capacitors C gd , C LC and C S are charged until the drain potential V D reaches the source potential V S = V S+ + V a . At t = t 7 the gate pulse P G falls as at t = t 1 , in consequence of which the TFT of the i-th row is turned OFF and the drain potential shifts downward by dV P which is given by Eq. (6). During t 7 < t < t 8 the TFT of the i-th row remains OFF, and hence the drain potential V D remains unchanged. At t = t 8 the gate pulse P G of the select level V GH is fed to the gate of the TFT of the (i+1)th row. At this time, the drain potential V D of the TFT on the i-th row shifts upward by the shift amount dV S given by the following equation as in the case of t = t 2 . dV S = [C S /(C gd + C LC + C S )](V GH - V x2 ) During t 8 < t < t 9 over which the gate pulse P G is applied to the (i+1)th gate bus, the drain potential of the TFT on the i-th row remains unchanged. At t = t 9 the non-select level V GL is provided to the gate of the TFT on the (i+1)th row. At this time, the drain potential V D of the TFT on the i-th row shifts downward by the amount which is given by the following equation as in the case of t = t 3 . dV R [C S /(C gd + C LC + C S )](V GH - V GL ) After all, the total shift amount ΔV C ' of the drain potential V D in the period from t = t 7 to t = t 9 is expressed by the following equation. ΔV C ' = -dV P + dV S - dV R Substitution of Eqs. (6), (12) and (13) into Eq. (14) gives ΔV C ' = -[C gd /(C gd + C LC + C S )](V GH - V GL ) + [C S /(C gd + C LC + C S )](V GL - V x2 ) Letting the drain potential at t > t 9 be represented by V D+ (the plus sign meaning the positive write), it is expressed as follows: V D+ = V S+ + V a + ΔV C ' The potential difference between the drain potential V D+ and the common voltage V C is held as a display voltage for the pixel L ij concerned at the time of positive write in the frame FR + . Next, the relationships among the source voltage V S , the drain potential V D , the common voltage V C and the two bias voltages V x1 and V x2 will be discussed on the basis of the description given above. To implement AC-wise driving of liquid crystal, the common voltage V C to be applied to the common electrode 4b needs to match an average value V do of the drain potential V D+ at the time of positive write and the drain potential V D- at the negative write so that they are symmetrical with each other. Hence, V C = V do ≡ (V D+ + v D- )/2 Substitution of Eqs. (11) and (16) into Eq. (17) gives V C = V do ≡ (V S- + V S+ )/2+(ΔV C ' - ΔV C ")/2 Substituting Eqs. (10) and (15) for ΔV C " and ΔV C ' and rearranging Eq. (18), we have V C = V do ≡ (V S- + V S+ )/2 -[C gd /(C gd + C LC + C S )](V GH - V GL ) -[C S /(C gd + C LC + C S )][(V x1 + V x2 )/2-V GL ] On the other hand, a peak-to-peak value, V Dpp = V D+ - V D- , of the drain potential is expressed by the following equation (20) from Eqs. (11) and (19). V Dpp ≡ V D+ - V D- = (V S+ + V a + ΔV C ') - (V S- - V a - ΔV C ") = (V S+ - V S- ) + 2V a + ΔV C '+ ΔV C " Substituting Eqs. (15) and (10) for V C ' and V C " in Eq. (20), respectively, we have V Dpp ≡ V D+ - V D- = V S+ - V S- + 2V a + [C S /(C gd + C LC + C S )](V x1 - V x2 ) = V Spp + [C S /(C gd + C LC + C S )](V x1 - V x2 ) Now, a description will be given of the points that must be noted in the analysis described above. A. Eq. (19) will be discussed first. The first term, ((V S- + V S+ )/2, on the right side of Eq. (19) represents an average value of the bias voltages V S- and V S+ of the source voltage V S during the negative and the positive write and the average value is the center value of a peak-to-peak value of the source voltage V Spp . It is the third term that must be noted. By adjusting the average value, (V x1 + V x2 )/2, of the first and second bias voltages, the average value V do of the drain potential can freely be set. To implement AC-wise driving of liquid crystal, the average value V do of the drain potential needs to be equal to V C (the common voltage). This requirement could be met by the two adjustment methods mentioned below. (a) Adjust the common voltage V C to make it equal to the average value V do of the drain potential that is given by Eq. (19). (b) Adjust the average value, (V x1 + V x2 )/2, of the first and second bias voltages so that the average value V do of the drain potential becomes equal to a given common voltage V C . The fifth aspect of the present invention features that either one of the common voltage V C and the average value (V x1 + V x2 )/2 is given arbitrarily and the other is set to satisfy V C = V do . B. Eqs. (21) and (21') will be discussed here. The last term should be noted. V x1 - V x2 represents the difference between the first and second bias voltages which are applied to the gate. By adjusting the difference, V x1 - V x2 , between the first and second bias voltages V x1 and V x2 , the drain voltage V Dpp can freely be set without changing the source voltage V Spp . Furthermore, Eqs. (21) and (21') can be made to hold regardless of the average value, (V x1 + V x2 )/2, of the bias voltages; according to the sixth aspect of the present invention, it is possible to freely set the drain voltage V Dpp while holding the source voltage V Spp constant by adjusting the difference (V x1 - V x2 ) while holding the above-mentioned average value constant. Figs. 4A and 4B show examples of drive voltage waveforms in the case of changing the drain voltage V Dpp while holding the source voltage V Spp constant. In Figs. 4A and 4B, the thick lines indicate the case where the gray-scale level signal V a is zero. In the case of a display in black, the level is shown as the drain voltage V D (B), which assumes levels shifted from the source bias voltages V S- and V S+ by ΔV C " and ΔV C ', respectively. For an arbitrary value of the gray-scale signal V a , the source voltage V S and the drain voltage V D are each shifted by the amount and in the direction indicated by the arrow V a . In Figs. 4A and 4B, the peak-to-peak value V Dpp of the drain voltage is set to a different value by setting the difference (V x1 - V x2 ) to a different value without changing the average value, (V x1 + V x2 )/2, of the first and second bias voltages. However, the source signals V S- - V a and V S+ + V a remain unchanged in Figs. 4A and 4B. Moreover, as shown in Fig. 5A and 5B, according to Eqs. (21) and (21'), the peak-to-peak value, (V S+ + V a ) - (V S- - V a ) ≡ V Spp , of the source voltage (and the peak-to-peak value, (V S- - V S+ ), of the source voltage for a display in black in which case V a = 0) can be changed by adjusting the difference (V x1 - V x2 ) while holding constant the peak-to-peak value, V Dpp = V D+ - V D- , of the drain potential. It is also evident that, in Fig. 5A, for instance, the peak-to-peak value V Dpp of the drain voltage can similarly be set to an arbitrary value through adjustment of the peak-to-peak value V Spp of the source voltage by Eqs. (21) and (21') (the seventh aspect of the present invention). Under special circumstances the peak-to-peak value V Spp of the source voltage V S may be made equal to the maximum amplitude V amx of the gray-scale level signal V a as shown in Figs. 2, 4A, 4B and 5B (the eighth aspect of the present invention). In this instance, since the following equation holds V Spp ≡ (V S+ + V a ) - (V S- - V a ) = V a the following equation holds from Eq. (22) V S- - V S+ = V a In the case of Fig. 5A, the peak-to-peak value V Spp is set as expressed by the following equation. V Spp ≡ (V S+ + V a ) - (V S- - V a ) = 2V a Hence, from Eq. (24) we obtain V S+ = V S- A decrease in the output V Spp from the source driver causes a decrease in its output power in proportion to the square of the output; therefore, the output power of the source driver can be minimized by setting the source driver output V Spp to a value equal to the maximum one V amx of the gray-scale level signal V a . While in the above the embodiments of the AC-wise driving methods according to the respective aspect of the invention have been described to invert the polarity of the gray-scale level signal by the source driver every frame, it is also possible to employ a well-known interlinear AC-wise driving method (which inverts the polarity every row); a discussion will be made of the output power of the source driver in this instance. The source buses, which are loads on the source driver, are capacitive loads. Letting the equivalent capacitance per bus be represented by C SB as shown in Fig. 6A, a charge of C SB ·V Spp [C] flows to the ground GND via a capacitor C SB from a battery V Spp in two horizontal scanning periods 2H. Hence, the output power P S of the source driver is as follows: P S = n·C SB ·(f H /2)·V Spp 2 [W] where f H is the frequency of a horizontal synchronizing signal and n is the total number of source buses. Fig. 6B is a graph showing the relationship between the voltage (on the abscissa) applied across the pixel electrode and the common electrode and the transmittivity of a normally white liquid crystal cell (on the ordinate) in the case of the conventional AC-wise driving method. With the conventional AC-wise driving scheme, the peak-to-peak value V Spp of the source voltage needs to be 11 V, at least twice higher than the maximum gray-scale level V amx , as shown in Fig. 6B. In contrast to this, in the AC-wise driving method according to the seventh aspect of the present invention (Figs. 2, 4A, 4B and 5B), the peak-to-peak value V Spp can be selected, and hence needs only to be equal to the gray-scale level signal V a of 3.5 V. Thus, assuming that n = 2000, C SB = 100 pF and f H = 30 kHz, the drive power that is needed in the conventional driving method is P S ≃ 363 mW, whereas in the AC-wise drive method according to the fifth aspect of the present invention P S ≃ 36.8 mW. As will be seen from the above, the problem in operating the AMLCD is the power for charging the buses, not the power for charging the pixel capacitances. On the other hand, in the drive method of the present invention the first and second bias voltages V x1 and V x2 alternately precede the rise of the conventional gate pulse; this causes an increase in the output power of the gate driver, which will hereinbelow be discussed in respect of the second aspect of the invention (that is, V x1 > V GL > V x2 ). The gate buses, which are loads on the gate driver, are also capacitive loads as is the case with the afore-mentioned source buses. Letting the equivalent capacitance of each gate bus be represented by C GB , and equivalent gate drive circuit for each gate bus is such as depicted in Fig. 6C. Voltages V GH , V GL , V x1 and V x2 from a first gate voltage source 12, a second gate voltage source 13, a first bias voltage source 14 and a second bias voltage source 15 are respectively provided to the gate driver, wherein they are selected by a switch SW i corresponding to the respective gate bus G i , in a predetermined sequential order and at predetermined timing for output to the corresponding gate bus G i . The output power of the gate driver 3 is to charge and discharge the equivalent capacitance C GB . With the drive method of the present invention, in the frame during which the first bias voltage V x1 is provided from the first bias voltage source 14, the equivalent capacitance C GB is charged first up to V x1 and then up to V GH . Then, the charges thus stored are discharged down to V GL -- this means the migration of charges of C GB (V GH - V GL ) ≐ C GB ·V g [C] . Also in the conventional drive method which does not utilize the first bias voltage V x1 , the equivalent capacitance C GB is charged up to V GH and the stored charges are discharged down to V GL ; hence, the amount of migration of charges is the same as in the present invention. The migration of charges takes place in the form of a current; the current does not change, whether the bias voltage is used or not. Accordingly, no increase in the output power is caused by newly providing the bias voltage V x1 . In the frame during which the second bias voltage V x2 is provided from the second bias voltage source 15, the equivalent capacitance is charged first up to V x2 and then up to V GH . Then, the charges thus stored are discharged down to V GL -- this means the migration of the following charges. C GB [V GH - V GL - (V x2 - V GL )] = C GB (V g + V GL - V x2 ) [C] In the above, the migration of the charge C GB ·V g occurs in the conventional drive method as well; accordingly, the increase in the output power solely by the second bias voltage V x2 needs to be taken into account. Thus, the increase in the output power of the gate driver is such as given by the following equation ΔP G ≃ m·C GB ·f v ·(V GL - V x2 ) 2 /2 [W] where f v is the frequency of a vertical synchronizing signal. In a typical example wherein C GB = 500 pF, f v = 60 Hz, m = 500 and V x2 = 10 V, the increase in the output power of the gate driver is 0.75 mW, very small as compared with the decrease in the supply power of the source driver, 363-37 = 326 mW. As will be understood from the above, when the bias voltages V x1 and V x2 are higher than the voltage V GL , the power of the gate driver does not increase. It is when the bias voltage V x1 or V x2 is lower than the voltage V GL that the power of the driver increases. In the case of the third aspect of the present invention, since V x1 ≦ V GL and V x2 ≦ V GL , the output power of the gate driver is increased not only by the bias voltage V x2 according to Eq. (27) but also by the bias voltage V x1 which is substituted for V x2 in Eq. (27). Even in a typical example wherein V x1 = -3 V and the other values are such as mentioned above, the increase in the output power by the first bias voltage is 0.07 mW and even if added with the increase by the second bias voltage V x2 , the total amount of power increased is only 0.82 mW. Thus, the seventh aspect of the present invention permits effective power savings throughout the display device. C. Next, a description will be given of a bias generator for supplying the first and second bias voltages V x1 and V x2 to the gate driver 3 which is used in the above-described embodiments. To make the drain center voltage V do equal to the common voltage V C as indicated by Eq. (19), it is necessary that a k 1 (an arbitrary constant) multiple of the sum of the first and second bias voltages, k 1 (V x1 + V x2 ), be variable. Furthermore, to set the drain voltage V Dpp of source bus drive voltage V Spp to a predetermined value in relation to Eq. (21'), it is necessary that a k 2 (an arbitrary constant) multiple of the difference between the first and second bias voltages, k 2 (V x1 - V x2 ), be variable. In addition, it is desirable that k 1 (V x1 + V x2 ) and k 2 (V x1 - V x2 ) be adjustable independently of each other. In Fig. 7 there is shown an example of the power supply circuit for the gate driver which satisfies these requirements. The output from a variable voltage source 6, which generates a voltage corresponding to a desired voltage value (V x1 + V x2 )/2, and the output from a variable voltage source, which generates a voltage corresponding to a desired voltage value (V x1 - V x2 )/2, are fed into an adder circuit 8 and a subtractor circuit 9, wherein they are added together and subtracted one from the other to obtain the first and second bias voltages V x1 and V x2 . The first and second variable voltage sources 6 and 7 and the adder circuit constitute a first bias voltage source 14 which outputs the first bias voltage V x1 , and the first and second variable voltage sources 6 and 7 and the subtractor circuit 9 constitute a second bias voltage source 15 which generates the second bias voltage V x2 . These bias voltages are applied to the gate driver 3 together with the gate select level V GH from the first gate voltage source 12 and the non-select level V GL from the second gate voltage source 13, and they are adequately selected by the switch SW i (i = 1 to m+1) corresponding to the respective gate bus G i to generate the gate bus drive voltage V Gi . In Fig. 7, it is also possible to generate voltages k 1 (V x1 + V x2 ) and k 2 (V x1 - V x2 ) from the first and second variable voltage sources 6 and 7 and properly add them together and subtract them one from the other in the adder circuit 8 and the subtractor circuit 9, respectively (the ninth aspect of the present invention). D. It must be noted that the bias voltages V x1 and V x2 are provided immediately prior to the application of the gate select level V GH . It has already been described with reference to the prior art in this specification that the application of the bias voltages V x1 and V x2 to the TFT causes an increase in the source-drain current I DS , incurring the possibility of partly rewriting the gray-scale level signal V a written in the pixel. With the scheme of the present invention, however, even if the gray-level signal written in the pixel is partly rewritten by the bias voltage V x1 or V x2 , it is immediately rewritten to the gray-scale level signal V a to be written into the pixel concerned next; thereafter, the non-select level V GL , which reduces the current I DS sufficiently small, is applied to the gate of the TFT until the instant preceding the application of the bias voltage V x1 or V x2 . This indicates that it is possible to prevent the degradation of the charge retaining characteristic of the pixel mentioned as a shortcoming of the method proposed in literature 2 or Japanese Pat. Laid-Open No. 157815/90 referred to as the prior art. E. When a voltage is applied across the capacitance C LC of the liquid crystal cell, the liquid crystal material assumes, for instance, a stand-up position with respect to the transparent base plate forming the liquid crystal panel. The liquid crystal material has dielectric anisotropy, and when the liquid crystal material stands up, its dielectric constant varies, causing a change in the value of the capacitance C LC accordingly. That is, the value of the capacitance C LC is expressed as a function of the voltage applied thereacross. As seen from Eq. (21'), a change in the source voltage V Spp causes a change in the drain voltage V Dpp as well and the voltage that is applied to the liquid crystal cell varies, causing a change in the value of the capacitance C LC . When the capacitance C LC thus changes, the center potential V do of the amplitude of the drain voltage changes as seen from Eq. (19), causing a change in the optimum common potential to be provided from the outside. This means that since the gray-scale level signal differs with pixels when a certain display is provided on the liquid crystal display panel, the optimum common voltage to be applied to each pixel differs. Since it is impossible to apply the optimum common voltage to every pixel, it is customary in the art to apply a certain optimum common voltage uniformly all over the display screen instead. With this method, however, every pixel "might be supplied with an optimum common voltage or not." Accordingly, there is a DC voltage difference between the optimum common voltage and the common voltage actually applied to each pixel, and this DC voltage difference needs to be compensated for. The simplest idea of compensating for this DC difference is "to shift the common voltage in a reverse direction by the same amount as that dV P by the voltage difference V g " as proposed in the afore-mentioned prior art literature 2. With this method, the drain voltage V D becomes equipotential with the source signal V S after time t 1 in Fig. 2, with the result that even if the source voltage V Spp varies, the center of the drain voltage V Dpp matches the center of the source signal V Spp and always remains constant. Hence, a constant common voltage V C is provided to match the center of the amplitude of the drain and source voltages V Dpp and V Spp which coincide with each other. In this case, even if the amplitude of the source voltage V Spp undergoes a change, application of an optimum common voltage can be attained. A further discussion will be made of Eq. (19). Eq. (19) indicates that the average value V do of the drain potential can be set to an arbitrary value by freely changing the third term on the right-hand side. To solve the problems of flicker and image printing in the AMLCD, it is preferable to compensate for the above-mentioned DC voltage difference which is caused by the dielectric anisotropy of the liquid crystal material (and a parasitic capacitance in the AMLCD). Referring to Eq. (19), by applying an appropriate voltage (V x1 + V x2 )/2 to adjust the center V do of the drain potential, it is possible to compensate for the DC voltage which is attributable to the dielectric anisotropy and the parasitic capacitance in the AMLCD. That is, by providing the common voltage V C equipotential with the center of the source signal V Spp and by adjusting the voltage (V x1 + V x2 )/2 so that the center of the drain voltage V Dpp (equal to the center V do of the drain potential), the common voltage that can be said to be optimum to any pixels can be set as mentioned above, while at the same time the compensation of the DC voltage can be achieved. For such a reason, substituting the following equation for V do in Eq. (19). V do = (V S+ + V S- )/2 we have -(C gd /C S )(V GH - V GL ) = V GL - (V x1 + V x2 )/2 In Eq. (29) there is not contained the capacitance C LC as a parameter. Hence, even if the capacitance C LC undergoes a change as the result of a change in the dielectric constant of the liquid crystal material which is caused by its dielectric anisotropy or a temperature change, as long as the voltage V GL - (V x1 + V x2 )/2 is set to be equal to (C gd /C S )(V GH - V GL ), the above-said equation V do = (V S+ + V S- )/2 holds and V do remains unchanged. The tenth aspect of the present invention features the setting of V do to the center of (V S+ + V S- )/2 ≡ V Spp . The relationship between the voltage V GL and the bias voltages V x1 and V x2 at this time will be discussed with reference to Fig. 6B. Fig. 6B is a graph showing the applied voltage vs. transmittivity characteristic of liquid crystal in the case where the potential of the opposed electrode (the common electrode), that is, the common voltage V C is zero volt. In the driving method according to the tenth aspect of the invention, since the center of the amplitude of the source voltage, the center of the amplitude of the drain voltage and the potential of the opposed electrodes are equal, the zero volt in Fig. 6B is the center of the amplitude of the source voltage. Since the gray-scale level signal is 3.5 V, V S+ is -1.75 V and V S- 1.75 V. Therefore, ΔV C '' = 3.75 V. In Eq. (10), V GH - V GL , C gd , C LC and C S take various values according to the liquid crystal display used. Hence, the first term on the right-hand side of Eq. (10) may sometimes become greater than 3.75 V. In this instance, the second term on the right-hand side becomes negative or minus (the third aspect). That is, in the case of [C gd /(C gd + C LC + C S )](V GH - V GL ) < 3.75, V x1 > V GL holds (the second aspect), and in the case of [C gd /(C gd + C LC + C S )](V GH - V GL ) ≧ 3.75, V x1 ≦ V GL holds (the third aspect). In either case, it is evident from Eq. (15) that V x2 < V GL . The above holds true in the case where the common potential is set to a value near the center of the amplitude of the source voltage as well as in the case where the center of the amplitude of the source voltage and the common potential have the same value. F. Next, a description will be given of the timing for supplying the bias voltages V x1 and V x2 . Fig. 8A is a waveform diagram showing only the gate signal waveforms V Gi and V Gi+1 in Fig. 2. In the period from time t 4 through t 9 , the period over which to apply the second bias voltage V x2 to the electrode opposite the signal storage capacitor C S provided in the pixel on the (i+1)th row is from time t 5 through t 8 , and the period over which to apply the select level to select the pixel of the i-th row is from time t 6 to t 7 . That is, in Fig. 8A, the second bias voltage V x2 is applied to the pixel of the (i+1)th row earlier by a time t 6 - t 5 = Δ 1 than the voltage V Gi reaches the select level, and the second bias voltage is still held for a time t 8 - t 7 = Δ 2 after the voltage V Gi went down to the non-select level. But Fig. 8A shows merely an example of the idea of the invention and the idea can be further expanded as described below. That is, even if it happens that the time t 5 at which the gate voltage V Gi+1 reaches the bias voltage V x2 satisfies Δ 1 = t 6 - t 5 < 0 as shown in Fig. 8B, it is evident that no problem would arise if the TFT in the ON state for the period from time t 5 through t 7 is sufficiently capable of charging the capacitors C gd , C LC and C S up to the source signal potential V S . Hence, the time Δ 1 = t 6 - t 5 is effective in the present invention through the vicinity of Δ 1 = t 6 - t 5 = 0 on the plus or minus side thereof. Fig. 8C is a waveform diagram on the assumption that t 7 = t 8 in Fig. 8A. In Fig. 8C, the time t 7 at which V Gi on the gate bus of the i-th row starts to change from the select level V GH to the non-select level V GL coincides with the time t 8 at which V Gi+1 on the gate bus of the (i+1)th row starts to change from the level of the bias voltage V x2 to the select level V GH . Furthermore, even if the time Δ 1 is so long that it extends over gate pulses P G of a plurality of preceding rows as depicted in Fig. 8D, no problem arises when it is sufficiently shorter than the time t 4 - t 3 (usually than the one-frame period). In the above, the period over which the bias voltage V x2 is provided; the same is true of the period over which the bias voltage V x1 is provided. On the other hand, as disclosed in "TFT-LCD Optical Characteristics Simulations," Transaction of the Institute of Electronics, Information and Communication Engineers of Japan, [Eletronic Display] EID91-45, pp. 41-45, it is known that image signals are distorted during the transition from the select level to the non-select level. This is because of a time difference t OFF between the start of transition from the select level to the non-select level and the time when the TFT actually exerts a sufficient OFF characteristic. In such a case, under the condition t 7 = t 8 according to the present invention, the gate pulse P G is applied to the (i+1)th row when the TFT of the i-th row is turned OFF; hence, there is a fear that the bias of the (i+1)th row differs from the bias to be applied thereto, resulting in an error being induced. However, such a bias error is mostly negligible in the case where (a) the output resistance of the gate driver and the time constant of the gate bus are relatively small and the afore-mentioned time difference t OFF is very small and (b) the on-state resistance of the TFT is relatively large and leakages from the capacitors C gd , C LC and C S during the period t OFF are negligible. Therefore, when these conditions (a) and (b) are satisfied, Δ 2 = 0, that is, t 7 = t 8 is not against the principles of the present invention. Usually, Δ 2 = t 8 - t 7 > 0 as shown in Fig. 8A but it may preferably be Δ 2 = t 8 - t 7 > t OFF . This is shown in Fig. 9. [With respect to the signal waveform of the gate bus of the last row] The gate pulse P G can be omitted from the gate voltage V Gm+1 of the gate bus of the last row; the gate voltages V Gm+1 and V Gm and the drain voltage V D and source voltage V S of the TFT of the m-th row at that time are shown in Fig. 10. The operation at time t < t 2 in Fig. 10 is exactly the same as described previously with respect to Fig. 2, and hence no description will be repeated. At t = t 2 , the gate voltage V Gm+1 drops to V x1 , and consequently, the drain potential of the TFT of the m-th row shifts downward in proportion to the potential applied from the C S side. The shift amount dV Q ' in this case is given by the following equation (30). dV Q ' = [C S /(C gd + C LC +C S )](V x1 - V GL ) As a result, the total shift amount ΔV C '' during the period from t = t 1 through t = t 2 is expressed by the following equation. ΔV C '' = dV P + dV Q ' = -[C gd /(C gd + C LC +C S )](V GH -V GL ) + [C S /(C gd + C LC +C S )](V x1 -V GL ) This is the same as Eq. (10). Similarly, the operation during the period t 4 < t < t 8 is also exactly the same as described previously in respect of Fig. 2, and hence no description will be repeated. At t = t 8 , since the gate voltage V Gm+1 rises by V x2 , the drain potential of the m-th row shifts upward in proportion to the potential applied from the C S side. The shift amount dV R ' is given by the following equation (32). dV R ' = [C S /(C gd + C LC + C S )](V GL - V x2 ) In consequence, the total shift amount ΔV C ' during the time interval from t = t 7 to t = t 8 is given as follows: ΔV C ' = -dV P + dV R ' = -[C gd /(C gd + C LC + C S )](V GH - V GL ) + [C S /(C gd + C LC +C S )](V GL - V x2 ) This is exactly the same as Eq. (15). Thus, the absence of the gate pulse P G in the gate voltage V Gm+1 does not ever lessen the effect of the present invention for the reasons given below (the fourth aspect of the present invention). (a) No TFT to be written is present. (b) The shift amounts V C " and V C ' of the drain potential on the m-th row are expressed by exactly the same equations as those of the shift amounts of the drain potential on the i-th row (1 ≦ i ≦ m-1). As described above, (1) according to the present invention, the bias voltage is added to the non-select level V GL of the gate voltage V G at a time instant earlier than the rise of the gate pulse P G . From time t 1 when the gate pulse P G dropped to the non-select level V GL to time t 4 when the bias voltage is provided in the next frame, the gate voltage is held at the non-select level which sufficiently reduces the source-drain current I DS . Thus, the present invention is free from the problem of the prior art that data once written in the TFT is partly rewritten by a leakage current flowing therein owing to the bias voltage which is applied after time t 1 when the write of the gray-scale level signal was completed; consequently, the charge retaining characteristic of the pixel can be improved. (2) According to the present invention, by setting the peak-to-peak value V Spp of the output voltage from the source driver to be equal to the maximum amplitude V amx of the gray-scale level signal V a contained in the source driver output voltage, it is possible to minimize the source driver output voltage and, at the same time, implement reduction of the entire power consumption of the device. (3) According to the present invention, by adjusting the average value, (V x1 + V x2 )/2, of the first and second bias voltages to make the center value V do of the drain voltage V Dpp (the common voltage V C being selected to be equal to the value V do ) equal to the center value of the source voltage V S , it is possible to compensate for the DC voltage which is caused by the dielectric anisotropy of liquid crystal and the parasitic capacitance in the AMLCD.

Claims: A method for driving an active matrix liquid crystal display wherein n x m pixels (L ij ) defined by liquid crystal cells each formed by a display electrode (4a) and a common electrode (4b) separated by liquid crystal held therebetween are arranged in a matrix form defined by n source buses (S j ) arranged in columns and m + 1 gate buses (G i ) arranged in rows; thin film transistors (Q ij ) are formed, each having a source (S) connected to one of said source buses near the intersection of said one source bus and one of said gate buses, a gate (G) connected to said one gate bus and a drain (D) connected to a corresponding one of said display electrodes (4a); a signal storage capacitor (Cs) is formed in each of said pixels (L ij ), said signal storage capacitor having its one electrode connected to said corresponding display electrode (4a) and having the other electrode connected to the gate bus (G i+1 ) in the succeeding row; a gray-scale level signal (V a ) is applied from a source driver (2) to all of said source buses every horizontal scanning period (H); and gate pulses (P G ) of a high level (V GH ) are each applied from a gate driver (3) to said gate buses one after another every horizontal scanning period (H); wherein: (a) said gray-scale level signal (V a ) which is applied to pixels on a selected one of said gate buses, is added, with its polarity inverted every predetermined alternating period, to first and second source bias voltages (V S+ and V S- ) which are generated alternately with said alternating period, whereby source voltages are obtained, said source voltages being outputted to said source buses; and (b) a gate voltage (V G ) includes a period of said high-level gate pulse for holding said thin film transistors in the ON state substantially during said horizontal scanning period (H) in each frame period, a gate bias period which immediately precedes the rise of each of said gate pulses and during which the gate voltage assumes either one of first and second gate bias voltages (V x1 ) and (V x2 ), and a period of a predetermined low-level voltage (V GL ) for holding said thin film transistors in the OFF state during said frame period except said gate pulse period and said gate bias period, said gate voltage (V G ) being applied to said gate buses so that said gate pulses are sequentially displaced said horizontal scanning period (H) apart, and said gate bias period of an i-th row has a wide span from a time prior to the fall of said gate pulse on the immediately preceding (i-1)th row to the time of rise of said gate pulse on said i-th row, whereby said first and second gate bias voltages (V x1 ) and (V x2 ), which are applied to said i-th row, are alternately added to said gate voltage (V G ) in positive and negative write periods in AC-wise driving of the pixels on the (i-1)th row, respectively, characterized in that no gate pulse period is included in the gate voltage (V G ) applied to the (m + 1)th gate bus this gate voltage assuming said first or second bias voltages (V x1 and V x2 ) during said gate bias period and said low level voltage (V GL ) during the remaining part of each frame period. The drive method of claim 1, wherein said first gate bias voltage (V x1 ) is set to be greater than said low level voltage (V GL ) and said second gate bias voltage (V x2 ) is set to be smaller than said low level voltage (V GL ). The drive method of claim 1, wherein said first gate bias voltage (V x1 ) is set to be equal to or smaller than said low level voltage (V GL ) and said second gate bias voltage (V x2 ) is set to be greater than said low level voltage (V GL ). The drive method of any one of claims 1 through 3, wherein either one of a common electrode voltage (V C ) to be applied to said common electrode (4b) or an average value ((V x1 +V x2 )/2) of said first and second gate bias voltage (V x1 and V x2 ) is set to an arbitrary value and the other is set such that said common electrode voltage (V C ) equals the center value (V do ) of the drain voltage (V D ). The drive method of any one of claims 1 through 4, wherein the difference (V x1 - V x2 ) between said first and second bias voltages (V x1 and V x2 ) is adjusted holding their average value ((V x1 + V x2 )/2) constant, and the peak-to-peak value (V Dpp ) of the drain voltage of said TFT is set to an arbitrary value, holding the peak-to-peak value (V Spp ) of the output voltage of said source driver (2) constant. The drive method of any one of claims 1 through 4, wherein the peak-to-peak value (V Spp ) of the output voltage of said source driver (2) is adjusted and the peak-to-peak value (V Dpp ) of the drain voltage of said TFT is set to an arbitrary value holding the difference (V x1 - V x2 ) between said first and second gate bias voltages (V x1 and V x2 ) constant. The drive method of claim 5, wherein said peak-to-peak value (V Spp ) of the output voltage of said source driver (2) is set to be equal to the maximum amplitude of said gray-scale level signal (V a ) contained in the output from said source driver. The drive method of any one of claims 1 through 4, wherein an output voltage k 1 (V x1 + V x2 ) of a first variable DC supply, where k 1 is an arbitrary constant, V x1 is said first gate bias voltage and V x2 is said second gate bias voltage, and an output voltage k 2 (V x1 -V x2 ) of a second variable DC supply, where k 2 is an arbitrary constant, are calculated to obtain said first and second gate bias voltages. The drive method of claim 4, wherein said average value ((V x1 + V x2 )/2) of said first and second gate bias voltages is adjusted to make the center value (V do ) of said drain voltage (V D ) equal to the center value of peak-to-peak value (V Spp ) of said source voltage. The drive method of claim 6, wherein said peak-to-peak value (V Spp ) of the output voltage of said source driver (2) is set to be equal to the maximum amplitude of said gray-scale level signal (V a ) contained in the output from said source driver. The drive method of any one of claims 1 through 4, wherein said alternating period has a cycle of one or more rows or said frame period. The drive method of any one of claims 1 through 4, wherein said gate bias period of said i-th row is set to a value such that it covers said gate pulse period of the immediately preceding (i-1)th row. An active matrix liquid crystal display comprising: a display panel wherein pixels (L ij ) defined by liquid crystal cells each formed by a display electrode (4a) and a common electrode (4b) separated by liquid crystal held therebetween are arranged in the form of a matrix defined by n source buses (S j ) arranged in columns and (m+1) gate buses (G i ) arranged in rows; thin film transistors (Q ij ) are formed, each having a source (S) connected to one of said source buses near the intersection of said one source bus and one of said gate buses, a gate (G) connected to said one gate bus and a drain (D) connected to a corresponding one of said display electrodes (4a); a signal storage capacitor (Cs) is formed in each of said pixels (L ij ), said signal storage capacitor having its one electrode connected to said corresponding display electrode and having the other electrode connected to the gate bus in the succeeding row; source driver means (2) whereby a gray-scale level signal (V a ) which is applied to pixels on a selected one of said gate buses, is added, with its polarity inverted every predetermined alternating period, to first and second source bias voltages (V S+ and V S- ) which are generated alternately with said alternating period to obtain source voltages (V S ) said source voltages being simultaneously supplied to said source buses during each horizontal scanning period; high-level voltage source means for outputting a high level voltage (V GH ) which turns ON said thin film transistors; gate bias voltage source means for outputting first and second gate bias voltages (V x1 and V x2 ); low-level voltage source means for outputting a predetermined low level voltage (V GL ) which holds said thin film transistors in the OFF state; and gate bus drive means (3) which selects said high-level voltage source means substantially during said horizontal scanning period (H) in each frame period and outputs said high level voltage as a gate pulse, selects either one of said first and second gate bias voltages (V x1 and V x2 ) immediately prior to the rise of said gate pulse in correspondence with a negative and a positive write period in AC-driving of pixels on an (i-1)th row and outputs said selected one of said first and second gate bias voltages, selects and outputs said low-level voltage (V GL ) in each frame period except the period of said gate pulse and said gate bias period, and applies said gate pulse to each of said gate buses so that said gate pulse is displaced said horizontal scanning period (H) apart from said gate pulse applied to adjacent ones of said gate buses, said gate bias period of an i-th row having a wide span from a time prior to the fall of said gate pulse on the immediately preceding (i-1)th row to the time of rise of said gate pulse on said i-th row, characterized in that said gate bias voltage source means comprises: a first variable voltage source (6) for outputting a first variable voltage as a voltage corresponding to the sum of said first and second gate bias voltages; a second variable voltage source means (7) for outputting a second variable voltage as a voltage corresponding to the difference between said first and second gate bias voltages; adding-amplifying means (OP, R) for outputting the sum of said first and second variable voltages as said first gate bias voltage; and subtracting-amplifying means (OP, R) for outputting the difference between said first and second variable voltages as said second gate bias voltage.

Inventors: HOSOMICHI MASANORI, KAMIYA TAKEO, YASUI MASARU, HOSOMICHI, MASANORI, KAMIYA, TAKEO, YASUI, MASARU
Applicants: HOSIDEN AND PHILIPS DISPLAY CO, HOSIDEN AND PHILIPS DISPLAY CORPORATION
Application year: 1994
Main classification: G02F1
IPC codes: G09G3, G02F1