Decoder circuit which resists a fluctuation of a power supply

Abstract: A decoder circuit includes p-channel MOS transistors (P₁, P₂), n-channel MOS transistors (N₁ to N₄) having gates to which data signals (D₁ to D₄) are inputted, respectively, a further n-channel MOS transistor (N s ) connected in series to the n-channel MOS transistors (N₁ to N₄) and having a gate to which a precharging signal (Φ) is inputted, and a further n-channel MOS transistor (N₅) connected between the transistors P₂ and N₁. In the decoder circuit, the gate of transistor N₅ is connected to the drain of transistor P₂, and a capacity C H is connected between the gate of transistor N₅ and a power potential. In a holding state, the power potential is held by the aid of the capacity C H connected to the gate of transistor N₅.

Description: BACKGROUND OF THE INVENTION (Field of the Invention) The present invention relates to a decoder circuit, and more particularly to a dynamic decoder which resists a noise from a power supply. (Description of the Related Art) A conventional dynamic decoder circuit, for example, having four input terminals is constituted as shown in Fig. 4. That is, the circuit includes a p-channel MOS transistor P 1 having a source connected to a power supply VDD and a gate to which a precharging signal Φ is supplied through a buffer 1, and an n-channel MOS transistor N s having a source which is grounded and a gate to which the precharging signal Φ is supplied through the buffer 1. In this circuit, a MOS transistor train consisting of n-channel MOS transistors N 1 to N 4 which are connected to each other in series are inserted between a drain of the p-channel MOS transistor P 1 and a drain of the n-channel MOS transistor Ns. Data signals D 1 to D 4 are supplied to gates G 1 to G 4 of the n-channel MOS transistors N 1 to N 4 through buffers 2 to 5, respectively. In such an arrangement, an output signal V out of the decoder circuit is obtained from the drain of the p-channel MOS transistor P 1 . Subsequently, an operation of the decoder circuit will be described. At first, the precharging signal Φ is set to a L level. At this time, the buffer 1 makes ground potential inputted to the gate of the p-channel MOS transistor P 1 as well as the gate of the n-channel MOS transistor N s . Therefore, the p-channel MOS transistor P 1 brings into an on-state whereas the n-channel MOS transistor N 2 brings into an off-state. As a result, the output signal V out becomes a potential of power supply regardless of the levels of the data signals D 1 to D 4 (hereinafter this state being referred to as "a precharging state"). Subsequently, the precharging signal Φ is changed into a H level. At this time, the buffer 1 makes power potential inputted to the gate of the p-channel MOS transistor P 1 as well as the gate of the n-channel MOS transistor N s . As a result, the p-channel MOS transistor P 1 is changed into the off-state whereas the n-channel MOS transistor N s is changed into the on-state. Therefore, the output signal V out depends on the levels of the data signals D 1 to D 4 . That is, in the case where all of the data signals D 1 to D 4 are at the H level, since the buffers 2 to 5 output power potential, respectively, all of the n-channel MOS transistors N 1 to N 4 bring into the on-state, whereby the output signal V out outputs ground potential (hereinafter this state being referred to as "a sampling state"). On the other hand, if the levels of the data signals D 1 to D 4 are set in such a manner that D 1 , D 2 and D 3 are at the H level and D 4 is at the L level, since the buffers 2 to 4 output power potential, the n-channel MOS transistors N 1 to N 3 bring into the on-state. However, the n-channel MOS transistor N 4 brings into the off-state because the buffer 4 outputs ground potential. Hence, the output signal V out holds power potential, which is the output level in the precharging state, as it is (hereinafter this state being referred to as "a holding state"). By the way, in the above-mentioned conventional decoder circuit, there exist floating capacities C 1 to C 3 and C L irrelevant to the nodes of the n-channel MOS transistors N 1 to N 4 and output signal V out . An influence of those floating capacities C 1 to C 3 and C L on a signal outputted from the decoder when power potential fluctuates will be described below. It is assumed that the data signals D 1 to D 4 are set such that D 1 to D 3 are at the H level but D 4 is at the L level. In this case, the decoder circuit is changed from the precharging state to the holding state, and its timing chart is shown in Fig. 5. In the precharging state, when power potential VDD is V 1 , the respective gate potentials G 1 to G 4 for the n-channel MOS transistors N 1 to N 4 are so that G 1 to G 3 are V 1 and G 4 is 0. Since the p-channel MOS transistors N 1 to N 4 have a threshold value V TN , the respective nodes A to C have a level V 1 - V TN . Thereafter, the precharging signal is changed into the H level so that the decoder circuit comes to the holding state. At this time, because the p-channel MOS transistor P 1 is in the off-state, the output signal V out is held to V 1 by the floating capacity C L . At this time, a charge Q L of the floating capacity C L is equal to C L V 1 . On the other hand, the levels of the nodes A to C are held to V 1 - V TN because the n-channel MOS transistor N 4 is in the off-state. At this time, the charges Q 1 to Q 3 of the respective floating capacities C 1 to C 3 are represented as follows: Q 1 = C 1 (V 1 - V TN ) Q 2 = C 2 (V 1 - V TN ) Q 3 = C 3 (V 1 - V TN ) Here, it is assumed that the power potential VDD is changed from V 1 to V 2 where V2 - V1 ≥ V TN . Although the source of the p-channel MOS transistor P 1 is changed into V 2 in level with fluctuation of power supply, the gate thereof is also changed into V 2 in level by the aid of the buffer 1. The p-channel MOS transistor P 1 is held in the off-state against fluctuation of power supply. On the other hand, the gate potential G 1 to G 3 for the n-channel MOS transistors N 1 to N 3 are moved to V 2 in level by the aid of the buffers 2 and 3 likewise. At this time, because of G 1 = V 2 ≥ V out + V TN = V 1 + V TN , the node A rises up to the same level as the output signal V out . However, because the p-channel MOS transistor P 1 is in the off-state, electric charges which are charged in the floating capacity C L result in transfer. That is, the charges are shared between the floating capacity C L and the floating capacities C 1 , C 2 and C 3 , as a result of which the output signal V out is fluctuated as follows: V out = V 1 - {(C 1 + C 2 + C 3 )/(C 1 + C 2 + C 3 + C L )}·V TN Thereafter, even though power potential VDD is again returned to V 1 , the level of the output signal V out is held as it is. If C 1 + C 2 + C 3 = C L and V TN = V 1 /2, then the following condition is satisfied. V out ≈ V 1 - V TN = V 1 /2 This means that, if a logical threshold value for a post-stage to which the output signal V out of the decoder circuit is inputted is VDD/2, the level of the output signal V out is logically inverted intentionally. That is, when the fluctuation of power supply exceeds V TN , the decoder circuit malfunctions. As a first countermeasure against the above-described fluctuation of power supply, the floating capacity C L , which is set so as to satisfy the condition of C L ≥ C 1 + C 2 + C 3 , is inserted into the decoder circuit as shown in Fig. 4. A timing chart at this case is shown in Fig. 6. Likewise in the above-described case, the charge sharing occurs against the fluctuation of power supply in the holding state. However, if C L = C 1 + C 2 + C 3 and V TN = V 1 /2, then the output signal V out can be set as follows: V out = V 1 - V TN /2 = 3/4V 1 Likewise in the foregoing case, if a logical threshold value for a post-stage to which the output signal V out of the decoder circuit is inputted is VDD/2, this makes it unnecessary to logically invert the level of the output signal V out . Furthermore, as a second countermeasure against the fluctuation of power supply, there is a decoder circuit shown in Fig. 7. This decoder circuit includes a p-channel MOS transistor P 1 having a source which is connected to a power supply VDD and a gate which inputs a precharging signal Φ through a buffer 11, and an n-channel MOS transistor N s having a source which is connected to ground potential and a gate to which the precharging signal Φ is inputted through the buffer 11. In the decoder circuit, a MOS transistor train consisting of n-channel MOS transistors N 1 to N 4 which are connected in series is inserted between the drain of the p-channel MOS transistor P 1 and the drain of the n-channel MOS transistor N s . Data signals D 1 to D 4 are inputted to gates G 1 to G 4 of the n-channel MOS transistors N 1 to N 4 through 2-input type OR buffers 12 to 15, respectively. The precharging signal Φ is inversely inputted to one input terminal of each of the 2-input type OR buffers 12 to 15. Also, one terminals of capacities C H1 to C H4 are connected to the gates G 1 to G 4 , respectively, whereas the other terminals of the capacities C H1 to C H4 are commonly connected to each other, and input a step-up signal Φ' through a buffer 16. In this decoder circuit, an output signal V out is obtained from the drain of the p-channel MOS transistor P 1 . Now, an operation of the decoder circuit thus organized will be described with reference to a timing chart shown in Fig. 8. At first, when the precharging signal Φ is at the L level, the p-channel MOS transistor P 1 is in an on-state and the output signal V out comes to a V 1 level. Also, since the two-input type OR buffers 12 to 15 inversely input the precharging signal Φ, they output a signal of the V 1 level regardless of the levels of the data signals D 1 to D 4 , respectively. Nodes A to C between the respective n-channel MOS transistors N 1 to N 4 are precharged up to the levels of V 1 - V TN likewise in the decoder circuit shown in Fig. 4. Subsequently, when the step-up signal Φ' comes to the H level, the respective potentials of the gates G 1 to G 4 rises up to the level of 2V 1 due to C H1 to C H4 . Hence, because of G 1 = 2V 1 ≥ V out + V TN = 3/2V 1 , the potential of the node A rises up to the same level as the output signal V out . However, unlike the foregoing case, because the p-channel MOS transistor P 1 is in the on-state, the potential of the node A rises up to the level of V 1 . Likewise, the potentials of the nodes B and C rise up to the level of V 1 . When the step-up signal Φ' comes to the L level, the levels of the gates G 1 to G 4 are changed into V 1 again. However, the levels of the nodes A to C are not changed. Then, when the precharging signal Φ comes to the H level, the p-channel MOS transistor P 1 is changed into the off-state, and the gates G 1 to G 4 also come to the levels of the data signals D 1 to D 4 , respectively. In Fig. 8, the data signals D 1 to D 3 are set to the H level whereas the data signal D 4 is set to the L level, likewise in the foregoing case. Since the n-channel MOS transistor N 4 is in the off-state, the output signal V out is held to the V 1 level. At this time, it is assumed that the power potential VDD fluctuates from V 1 to V 2 (V 2 ≥ V 1 + V TN ). The gates G 1 to G 3 are changed from V 1 to V 2 with fluctuation of VDD. However, the electric charges in the floating capacities C 1 to C 3 and C L is not transferred anywhere. Hence, the condition of V out = V 1 is held with no change in level of the output signal V out . That is, the decoder circuit does not malfunction against the fluctuation of power supply. The conventional decoder circuit shown in Fig. 4 makes it necessary to increase the capacity C L . However, for that reason, it has a drawback that the reading speed is low in the sampling state. On the other hand, the conventional decoder circuit shown in Fig. 7 has no drawback that the reading speed is low. However, it has a drawback that a lot of additional circuits such as the 2-input OR buffers and the capacities C H1 to C H4 as well as the control operation using the step-up signal Φ' are required for making the potentials of the gates G 1 to G 4 rise. WO-A-82/00741 discloses clocked IGFET serial decoder circuit which has a precharge transistor with its conduction channel connected between a V DD supply and an output terminal, a string of transistors with their conduction channels connected in series between the output terminal and a switch ground node and a ground switch transistor with its conduction channel connected between the switch ground node and a Vss supply. The gates of the transistors of the string receive input signals from clocked input buffers which bias the gates at V DD during the precharge interval when the precharge transistor is ON and the ground switch transistor is OFF. This allows the parasitic capacitances at the junctures of the transistors in the string to become substantially charged during the precharge interval and thus prevent rapid charge sharing at the output terminal when the circuit is enabled. WO-85/04539 discloses a semiconductor logic circuit which adds data processing capability to a programmed logic array having an AND plane and an OR plane connected serially between an input register and an output register by inserting a multi-stage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multi-stage network. "International Journal of Electronics", Vol. 66, No. 5, pages 679 to 695 discloses a dynamic CMOS logic intended to be free from problems of charge sharing and clock skew. It discloses for example a logic comprising a logic tree composed of NMOS devices. A first precharging transistor is connected between a power supply line and an output node, a second transistor is connected between the output node and one end of the logic tree, and a discharging transistor is connected between the other end of the logic tree and a ground voltage. This prior art provides the basis for the preamble portion of Claim 1. SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks with the conventional decoder circuit, and an object of the invention is to provide a decoder circuit which prevents the reading speed in the sampling state from being low and does not require complicated timing control and a lot of additional circuits. The above object has been achieved by provision of a decoder circuit as defined in claim 1. Claim 2 defines a particular embodiment thereof. The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a general diagram showing a decoder circuit in accordance with one embodiment of the present invention; Fig. 2 is a diagram showing a dynamic circuit used in the decoder circuit according to the embodiment of the invention; Fig. 3 is a timing chart representing the operation of the decoder circuit shown in Fig. 2; Fig. 4 is a diagram showing one example of a conventional decoder circuit; Fig. 5 is a first timing chart representing the operation of the decoder circuit shown in Fig. 4; Fig. 6 is a second timing chart representing the decoder circuit shown in Fig. 4; Fig. 7 is a diagram showing another example of the conventional decoder circuit; and Fig. 8 is a timing chart representing the operation of the decoder circuit shown in Fig. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, description will be given of an embodiment in accordance with the present invention with reference to the accompanying drawings. Fig. 1 is a general diagram showing a decoder circuit in accordance with one embodiment of the present invention. In Fig. 1, the decoder circuit is arranged so as to decode input data signals D 1 to D 4 in the form of 4 bits to generate output signals V out 1 to V out 16. The respective data signals D 1 to D 4 are used to generate true and complementary signals which are inputted to dynamic circuits 20-1 to 20-16 having different combination of the signals inputted thereto, respectively, as shown in Fig. 1. Since all of the dynamic circuits 20-1 to 20-16 are formed by the same circuit arrangement, for simplification of the description, one dynamic circuit 20-1 among the circuits 20-1 to 20-16 is shown in Fig. 2 as one example in detail. The dynamic circuit 20-1 shown in Fig. 2 includes a p-channel MOS transistor P 1 having a source which is connected to a power supply VDD and a gate which inputs a precharging signal Φ through a buffer 1, and an n-channel MOS transistor N s having a source which is connected to the ground potential and a gate which inputs the precharging signal Φ through the buffer 1. In the dynamic circuit, a MOS transistor train consisting of n-channel MOS transistors N 1 to N 4 which are connected in series is inserted between the drain of the p-channel MOS transistor P 1 and the drain of the n-channel MOS transistor N s . Input data signals D 1 to D 4 are inputted to gates G 1 to G 4 of the n-channel MOS transistors N 1 to N 4 through buffers 2 to 5, respectively. Further, an n-channel MOS transistor N 5 is inserted between the drain of the n-channel MOS transistor N 1 and the p-channel MOS transistor P 1 . Moreover, the source of a p-channel MOS transistor P 2 is connected to the power supply VDD, and the gate of the p-channel MOS transistor P 2 receives the precharging signal Φ through the buffer 1. The drain of the p-channel MOS transistor P 2 is connected to the gate of the n-channel MOS transistor N 5 and also to the ground potential through a capacity C H . In the dynamic circuit, an output signal V out 1 is obtained from the drain of the p-channel MOS transistor P 1 . Now, an operation of the dynamic circuit 20-1 shown in Fig. 2 will be described. At first, when the precharging signal Φ is at the ground level indicative of L level, both of the p-channel MOS transistors P 1 and P 2 are in an on-state and an output signal V out 1 from the respective drains of those transistors P 1 and P 2 as well as an node D therebetween has a power potential VDD which is equal to V 1 . At this time, the capacity C H is charged with electric charges of Q H = C H V 1 . On the other hand, if the levels of the input data signals D 1 to D 4 are set such that D 1 , D 2 and D 3 are at the H level, but D 4 is at the L level, since the buffers 2 to 4 output power potential VDD = V 1 , respectively, the potentials of the gates G 1 to G 3 are equal to V 1 . If a threshold value of the n-channel MOS transistors is V TN (= 1/2V 1 ), then the potential at a node E between the n-channel MOS transistors N 5 and N 1 satisfies the condition of E = V 1 -V TN . Similarly, the nodes A to C between the n-channel MOS transistors N 1 to N 3 satisfy the condition of A = B = C = V 1 - V TN . At this time, the floating capacities C 0 to C 3 connected to the respective nodes are charged with the following electric charges. Q 0 = C 0 (V 1 - V TN ) Q 1 = C 1 (V 1 - V TN ) Q 2 = C 2 (V 1 - V TN ) Q 3 = C 3 (V 1 - V TN ) Subsequently, when the precharging signal Φ comes to the power voltage VDD indicative of level, then the p-channel MOS transistor P 1 and P 2 are changed into the off-state. At this time, the node D is held to V 1 by the capacity C H . On the other hand, the n-channel MOS transistor N s changes into the on-state, however, since the n-channel MOS transistor N 4 is in the off-state, the nodes E and A to C are held to the level of V 1 - V TN , respectively, but V out 1 is held to the level of V1. In this state, it is assumed that the power potential VDD is changed from V 1 to V 2 (V 2 ≥ V 1 + V TN ). At this time, because the output signal of the buffer 1 also fluctuates from V 1 to V 2 simultaneously, both of the p-channel MOS transistors P 1 and P 2 are held in the off-state. Hence, the level V 1 of the node D is held as it is. Accordingly, because of D = V 1 〈 V out + V TN = V 1 + V TN , the node E is also held to the level of V 1 - V TN . The node G 1 fluctuates to V 2 due to the buffer 2. However, since both of the nodes E and A have the level of V 1 - V TN , electric charges are not transferred anywhere so that the node A comes to V 1 - V TN . Therefore, because the output signal V out is held to the level of V 1 , the dynamic circuit does not malfunction against the fluctuation of power supply. As was described above, the present invention can realize a decoder circuit which does not require to add a capacity to an output terminal of the decoder circuit, does not share electric charges against the fluctuation of power supply only by adding two MOS transistors and one capacity, and does not malfunction. As a result, the reading speed in the sampling state is prevented from being low, and a complicated timing control and a lot of additional circuits are not required, thereby being capable of providing a decoder circuit with ease and high performance. The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. The embodiment was chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention as defined in the Claims.

Claims: A decoder circuit comprising an output node (V out ), first precharging means for precharging said output node to a first potential (V DD ) in response to a precharging signal (), a transistor circuit having first and second nodes and at least one first transistor (N 1 ,...,N 4 ) coupled between said first and second nodes and receiving at a gate thereof an input signal (D 1 ,...,D 4 ), a second transistor (N 5 ) inserted between said output node and said first node of said transistor circuit, discharging means (N s ) for discharging said second node of said transistor circuit to a second potential when said precharging signal disappears, said first precharging means including a third transistor (P 1 ) connected between a first power supply line supplying said first potential and said output node and having a gate supplied with said precharging signal, said discharging means (N s ) including a fourth transistor (N s ) connected between a second power supply line supplying said second potential and said second node and having a gate supplied with said precharging signal, said third (P 1 ) transistor being of a first channel type, and said fourth transistor (N s ) being of a second channel type, characterised by second precharging means (P 2 ) for precharging a gate of said second transistor (N 5 ) to said first potential in response to said precharging signal said second precharging means including a fifth transistor (P 2 ) connected between said first power supply line and said gate of said second transistor (N 5 ) and having a gate supplied with said precharging signal, said fifth transistor (P 2 ) being of the said first channel type. The decoder circuit as claimed in claim 1, further comprising a capacitor (C H ) connected between the gate of said second transistor (N 5 ) and said second power supply.

Inventors: KONDOH CHIAKI, KONDOH, CHIAKI, KONDOH, CHIAKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03K19
IPC codes: H03K19, G11C8, G11C7