Logic gate testing

Abstract: Apparatus for generating digital waveforms for use in the testing of logic gates comprises a calculator (1) operable to generate a sucession of output values which consist of solutions to a stored generator equation. The said output values are applied to the gate array (6) under test and may be altered according to the form of the generator equation.

Description: This invention relates to an apparatus for generating digital waveforms for use in the testing of logic gates. In order to test logic gates, there is a requirement for sending uniquely coded bit streams along a set of wires which are connected to the gates under test. A conventional approach for synchronous testing of an array of gates includes the following steps; (i) partition the requirement into clock periods, (ii) define the most significant bit (MSB) and the least significant bit (LSB) for the wires, (iii)tabulate logic states in columns for the required bit-streams and calculate a decimal word for each column, (iv) read out the decimal words one by one into the gate array. This invention performs the above functions and further provides a novel approach for generating and controlling the bit-streams. According to this invention as set forth in the claims, there is provided apparatus for generating digital waveforms for testing an array of logic gates, said apparatus including calculator means operable to receive a set of input values which form an argument of a generator equation and to create a sequence of digital output values each comprising the calculated result of the generator equation, and means for applying said digital output values to the array of logic gates under test. The means for applying the digital output values to the logic gate array could be simply a set of wires, buffered if necessary. The set of input values could be stored in a memory and clocked into the calculator means at a desired rate. Alternatively, the set of input values could be fed into the calculator means from an on-the-fly buffer / processor. One or more generator equations could be stored in a second memory to which the calculator means has access. Generation of waveforms based on the concept of calculating the results of an generator equation are described in detail in our co-pending European Patent Application; EP-A-509,713. Therein, certain generator equations are termed "Portmanteau functions", one example being, the inverse of a trigonometric function ie arc.cos(sin P). Herein, a "Portmanteau Function" can be any generator equation. Some embodiments of the invention will now be described, by way of example only, with reference to the drawings in which: Figure 1 illustrates, in block diagram form, apparatus for testing logic gates in accordance with the invention, and; Figures 2A and 2B show logic states relating to the outputs of the apparatus of Figure 1; In Figure 1, a calculator 1 has inputs from a memory 2 and a store 3. The calculator 1 has eight digital output lines 4 which are clocked out via a buffer 5 to an array of logic gates 6 under test. Although eight output lines are shown in the Figure, this is by no means a limitation, more lines or fewer lines may be chosen if desired. Also, the complexity of the gate array shown in Figure 1 and the number of gate array output lines is entirely arbitary. Each output line from the LSB through to the MSB is attached to a corresponding input line to the array 6. The output lines of the gate array 6 can be monitored by suitable data recording equipment or clocked into a register 7 for future scrutiny. The memory 2 has stored therein a generator equation (i.e. a "Portmanteau Function") and the store 3 contains discrete values of a parameter forming the argument of the Portmanteau Function. For example in a general case, say that the Portmanteau Function is y = f(P) i.e. y is some function of P, a number of discrete values of P being held in the store 3 and clocked into the calculator 1 in succession. The calculator 1 is pre-programmed with the necessary algorithms for calculating successive values of y for each value of P set between pre-chosen limits. Hence, the calculated values of y appear as a sequence of numbers, but in binary form (eight bits in this example), at the output of the calculator 1. The logic level on each of the eight lines at any instant is completely under the control of the user who, by choosing the specific generator equation, values and clocking rate of the calculator, can arrange for any specific digital stream to appear on each line and therefore activate the associated logic gate in the array 6. For example a periodic ramp Portmanteau Function; e.g. can provide ascending and / or descending bit streams. Alternatively, a single ramp waveform could also be generated using the simpler form: y=P over a suitable range of P. In a further example, arbitrary staircase generator equations can generate arbitary word streams. It can be shown that in the general case, a staircase waveform can be generated using the equation; y(P)=C 0 +C 1 sgn(P-P 1 )+C 2 sgn(P-P 2 )+C 3 sgn(P-P 3 )....C n sgn(P-P n ) ( i ) where the coefficients C 0 ,C 1 ,C 2 ,C 3 , etc. determine the word values, and shifts P 1 ,P 2 ,P 3 , etc. determine the point (i.e. the number of clock intervals) where each word state changes. The general solution for the amplitude coefficients C 0 -C n is as follows: C 1 = y 1 2 C 2 = y 2 - y 1 2 C n = y n - y n-1 2 where the y values are the actual required decimal word values. In a specific example, suppose there is a requirement for each gate to be held at a logic high level in succession i.e. that the bit streams on each of the eight wires comprising the calculator output should be as represented in Figure 2A and with the corresponding Boolean states and decimal word values shown in Figure 2B. Each Boolean state in succession corresponds therefore to the decimal words 0,1,2,4,8,16,32,64 and 128. This requirement can be achieved by choosing a generator equation, y=2 P for values of P equalling 0,1,2,3,4,5,6 and 7. The length of time for which each bit is held high can be controlled by the rate at which the P values are clocked out of the store 3 into the calculator 1.

Claims: Apparatus for generating digital waveforms for testing an array of logic gates (6), said apparatus including calculator means (1) operable to receive a set of input values which form an argument of a generator equation and to create a sequence of digital output values each comprising the calculated result of the generator equation, and means (4) for applying said digital output values to the array of logic gates (6) under test. Apparatus according to claim 1 in which the means for applying the digital output values to the array of logic gates is a set of wires (4). Apparatus according to claim 1 or claim 2 in which the means for applying the digital output values to the array of logic gates (6) includes a buffer (5). Apparatus according to any preceding claim and including a first memory (3) connected to the said calculator means (1) for storing the said received set of input values. Apparatus according to any preceding claim and including a second memory (2) connected to the calculator said means (1) for storing a generator equation. Apparatus according to any preceding claim in which the generator equation includes a term comprising the inverse of a trigonometric function. Apparatus according to claim 1 in which the generator equation has the form y(P)=C 0 +C 1 sgn(P-P 1 )+C 2 sgn(P-P 2 )+C 3 sgn(P-P 3 )....C n sgn(P-P n ) A method for generating digital waveforms for testing an array of logic gates (6), the method including the steps of; receiving a set of input values which form the argument of a generator equation, creating a sequence of output values in binary form, each output value comprising the calculated result of the generator equation corresponding to each input value, and outputting said sequence of output values to the array of logic gates (6) under test.

Inventors: HOLNESS PETER J, PATEL MUKESH, HOLNESS, PETER J., PATEL, MUKESH, HOLNESS, PETER J., BRITISH AEROSPACE DEFENCE LTD., PATEL, MUKESH, C/O JAYRESH R PATEL
Applicants: HOLNESS PETER JOHN, HOLNESS, PETER JOHN
Application year: 1994
Main classification: G06F11
IPC codes: G06F11