ARRANGEMENT FOR READING INFORMATION FROM A TRACK ON A RECORD CARRIER

Abstract: An arrangement for reading out an information signal from a magnetic record carrier is disclosed. The arrangement comprises a read head having a magneto-resistive (MR) element (Rm1 with a first terminal (3) connected to a first point (13) of constant potential and with a second terminal (4), a bias-current generator (2; 210, T20) having an output (5) for supplying a bias-current to the MR element and an amplifier circuit (1) having a first terminal (6) coupled to the output (5) of the bias-current generator (2) and a second terminal (7) coupled to the second terminal (4) of the magneto-resistive head (Rm1) so as to form a series arrangement of the bias-current generator, the amplifier circuit and the magneto-resistive element. At an output terminal (8) the information signal is available. The amplifier circuit (1) comprises a MOS transistor (T1) connected between the ouptut terminal (8) and the second terminal (7). A feedback circuit having a low cut-off frequency (F1; 206, C1) provides a bias voltage to the gate of the MOS transistor (T1) and forces the entire bias current of the bias current generator (2) to flow through the MR element. The arrangement is balanced and the cut-off capacitors C1 and C2 of the two individual amplifiers (1; 61) are cross-coupled to reduce noise.

Description: Arrangement for reading information from a track on a record carrier The invention relates to an arrangement for reading out an information signal from a magnetic record carrier, comprising - a read head having a magneto-resistive element with a first terminal connected to a first point of constant potential, and with a second terminal, - a first bias-current means for supplying a bias-current, - a first amplifier circuit comprising an output terminal for supplying the information signal, a first terminal coupled to the first bias-current means and to the output terminal, a second terminal coupled to the second terminal of the magneto-resistive head so as to form a series arrangement of the first bias-current means, the first amplifier circuit and the magneto- resistive element between a second point of constant potential and said first point of constant potential, the first amplifier circuit further comprising a first transistor, a first feedback circuit, a first load impedance and a first capacitor element, a first main flow terminal of the first transistor being connected to the second terminal of the first amplifier circuit, a second main flow terminal of the first transistor being coupled to the first terminal of the first amplifier circuit, a control terminal of the first transistor being coupled to the output terminal of the first amplifier circuit via the first feedback circuit, the first load impedance being coupled between the output terminal of the first amplifier circuit and a reference voltage terminal. Such an arrangement is known from United States Patent No. 5,270,882. In this known arrangement current biasing and current sensing of the magneto-resistive element is combined, thereby providing a low-noise amplification. It is an object of the invention to improve the noise behaviour of the known arrangement. In accordance with an aspect of the invention, the known arrangement is characterized in that the arrangement further comprises - a second bias-current means for supplying a bias-current, - a second amplifier circuit comprising an output terminal, a first terminal coupled to the second bias-current means and to the output terminal, a second terminal for coupling to a second terminal of the magneto-resistive head so as to form a series arrangement of the second bias-current means, the second amplifier circuit and the magneto-resistive element between the second point of constant potential and said first point of constant potential, the second amplifier circuit further comprising a second transistor, a second feedback circuit, a second load impedance and a second capacitor element, a first main flow terminal of the second transistor being connected to the second terminal of the second amplifier circuit, a second main flow terminal of the second transistor being coupled to the first terminal of the second amplifier circuit, a control terminal of the second transistor being coupled to the output terminal of the second amplifier circuit via the second feedback circuit, the second load impedance being coupled between the output terminal of the second amplifier circuit and a reference voltage terminal, and in that the control terminal of the second transistor is coupled to the second terminal of the first amplifier circuit via the second capacitor element, and the control terminal of the first transistor is coupled to the second terminal of the second amplifier circuit via the first capacitor element. The arrangement according to the invention provides a balanced version of the known arrangement wherein the first and second capacitor elements are cross-coupled to the second terminals of the individual amplifiers instead of to ground. The cross-coupling causes a shunting of the noise resistances of the first and second transistors and effects a reduced noise contribution of the first and second transistors. A further noise reduction is obtained in an arrangement which is characterized in that the first terminal of the first amplifier circuit is coupled to the output terminal of the first amplifier circuit via a cascode transistor having an first main flow terminal connected to the first terminal of the first amplifier circuit and a second main flow terminal coupled to the output terminal of the first amplifier circuit and in that the first terminal of the second amplifier circuit is coupled to the output terminal of the second amplifier circuit via a cascode transistor having an first main flow terminal connected to the first terminal of the second amplifier circuit and a second main flow terminal coupled to the output terminal of the second amplifier circuit. In order to obtain low noise, the first and second transistors should be large. By cascoding these large transistors the following advantages are obtained. The large first and second transistors and the first and second bias current generators can have a low output impedance, since they feed their respective currents into a very low-ohmic emitter of the cascode transistor. The drain-to-gate capacitance of the large first and second transistors is not Millered. The first and second bias current generators provide lower bias current and a corresponding lower noise because part of the total bias current for the magneto-resistive element is provided by the parallel arranged cascode transistor. The bias current generators feed current to a low voltage node, so that a maximum voltage range is available for the bias-current source, so as to enable the bias-current generator to be optimal for low noise, for example by using a current source transistor with a large emitter degeneration resistor. The above and other features and advantages of the invention will be apparent from the following description of exemplary embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 shows a known arrangement for reading information from a track on a record carrier, Figures 2A, 2B, 2C show versions of a feedback circuit for use in the arrangement of Figure 1, Figures 3A, 3B, 4A, 4B and 5 show versions of an amplifier circuit for use in the arrangement of Figure 1 , Figure 6 shows a balanced arrangement according to the invention, Figure 7 shows an arrangement having shielding means provided over the electrical connection between the MR element and the amplifier circuit, Figure 8 shows the reading of information from a track on a disk shaped record carrier, Figure 9A and 9B show circuit parts that can be coupled together so as to realize a multiplexed read out by means of two or more separate MR elements, Figure 10 shows the circuit part for realizing a multiplexed read out by means of two or more separate heads, each head having two MR elements, Figure 11 shows an amplifier for use in the balanced arrangement according to the invention, and Figure 12 shows an embodiment of a balanced arrangement according to the invention. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Figure 1 shows the basic circuit construction of the arrangement known from US patent spec. 5,270,882, which comprises a read head (not shown) having a magneto- resistive (MR) element R^, a bias-current generator 2 for generating a bias-current I bl , and an amplifier circuit 1. A first terminal 3 of the magneto-resistive element R ml is connected to a first point of constant potential 13, which is ground potential. An output 5 of the bias- current generator 2 is coupled to a first terminal 6 of the amplifier circuit 1. A second terminal of the bias-current generator 2 is coupled to a point of constant potential 12 (the positive supply voltage, denoted by +). A second terminal 7 of the amplifier circuit 1 is coupled to a second terminal 4 of the magneto-resistive element R ml . An output terminal 8,8' is available for supplying the information signal read out. The amplifier circuit 1 comprises a transistor T j , a feedback circuit F 1 and a capacitor element C 1 . The transistor T j is in the form of a MOSFET or a jFET. Its source terminal is coupled to the second terminal 7 of the amplifier circuit 1. Its drain terminal is coupled to the first terminal 6 of the amplifier circuit 1. Its gate terminal is coupled to the first point of constant potential 13, via the capacitor element C 1 . Further, the feedback circuit F j is coupled between the gate of the transistor T j and the terminal 6 of the amplifier circuit 1. The drain terminal of the transistor T j is further coupled to a reference point 10 via a load impedance R j . At the reference point 10 a voltage V ref is available, which needs not be a constant potential, but may vary, as will be explained later. At output terminal 8,8' the voltage occurring over the load impedance R j is present. The bias-current generator 2, the amplifier circuit 1, more specifically the transistor T 1 in the amplifier circuit 1, and the MR element R^ form a series arrangement between the terminals 3 and 12. As can be seen from the figure, the MR element R m] is connected to ground via its terminal 3. Further, when used in an arrangement for reading an information signal from a disk shaped record carrier (not shown), the disk is also preferably electrically connected to ground. This limits the possibility that a voltage difference can be built up between the head and the disk. This avoids electrical discharges that could otherwise occur between head and disk, which discharges could damage the head. The MR element R ml , the amplifier 1 and the bias-current generator 2 form a series arrangement between the two (supply) terminals 3 and 12. Thus, the current supplied by the bias-current generator 2 is fed to the MR element R ml so as to bias the MR element, as well as to the amplifier circuit 1. This bias current through the amplifier circuit results in a certain noise contribution, which is lower when the current through the amplifier circuit is higher. If the amplifier circuit would be in parallel to the MR element and the bias-current generator, a larger current would be needed to bias the MR element and to supply the input stage of the amplifier circuit with the current needed to obtain a low noise contribution in the amplifier circuit. Thus the arrangement of Figure 1 produces less noise and requires less bias current, with is a major advantage in the case of battery powered supply voltages. When the amplifier circuit has only one transistor, such as in the embodiment of Figure 1, instead of two in the case of a long-tailed pair, the amplifier circuit has a lower noise contribution. Variations in the magnetic field detected by the MR element R ml lead to variations in the resistance value of the MR element. The gate of transistor Υ 1 is coupled to ground for AC signals by means of the capacitor C l . This means that for AC signals, the terminal 4 of the MR element R,^ lies virtually to ground. As a result of this, variations in the resistance value of the MR element can only lead to variations in the current through the series arrangement. These current variations are fed via the load impedance R π to the terminal 10, and lead to a voltage variation across the load impedance R n . This voltage variation is detected at the terminals 8,8' as the output signal of the amplifier circuit. The feedback circuit F j realizes a low cut-off frequency. In order to enable integration of the capacitor C j , the resistance value of F j should be high. This results in the transistor ^ acting like a diode for DC signals, so that the bias-current I bl can be fed to the MR element R,^. The feedback circuit F j is an impedance network. In its most simple form, the feedback circuit can be a resistor. In order to make the arrangement suitable for use at low supply voltages applied to the terminals 3 and 12, it is necessary to make the voltage drop between the terminals 4 and 6 as small as possible, so that a maximum voltage range is available for the bias-current source (2), so as to enable the bias-current source to be optimal for low noise. Figure 2 A shows a further-elaborated version of the feedback circuit F l5 so as to make it high ohmic and to realize a voltage drop across the transistor T j which is as small as possible. The feedback circuit F j comprises a transistor T 3 , which is a MOS transistor, a bipolar transistor T 4 and a resistor R j . Both transistors T j and T 3 are of the same type, MOSfet or jFET. The gate terminal of the transistor T j is coupled to the terminal t j of the feedback circuit. The terminal t j is coupled to the gate terminal of the third transistor T 3 via the resistor R 1 # The source terminal of the third transistor T 3 is coupled to the emitter terminal of the fourth transistor T . The base terminal of the transistor T is coupled to the terminal t 2 of the feedback circuit, which terminal is coupled to the terminal 6 of the amplifier circuit. The gate and drain terminal of the transistor T 3 are interconnected so as to form a diode. Further, the interconnected gate and drain terminals are coupled to the point 12 of constant potential via a current source 21. The emitter of the transistor T 4 is coupled to the first point of constant potential 13 via a current source 24. Further, the collector of the transistor T 4 is coupled to the second point of constant potential 12. The current sources provide current supply for the transistors T 3 and T 4 . By means of the feedback part of Figure 2A, a voltage shift of -V ώ + V d is obtained between the terminals t j and t 2 , where V^ is the threshold voltage of a MOS transistor, such as the transistors T j and T 3 , and V d is the voltage across a bipolar diode. As a result, the voltage difference between the terminals 6 and 7 of the amplifier circuit of Figure 1, is roughly V d , or substantially 0.7 V. More specifically, the voltage difference between the terminals 6 and 7 is V d + W chl - V cll2 , where V chl and V ch2 are the channel voltages of the transistors Tj and T 3 respectively, which are dependent of the drain current through those transistors (V ch = V gs - Vtø, where V is the gate-source voltage and V Λ the threshold voltage of a transistor). Further, the impedance formed by the feedback circuit between the terminals t j and t 2 is high-ohmic so as to obtain the desired low value for the cut-off frequency of the lower band edge of the frequency characteristic of the amplifier circuit. The circuit of Figure 2 A has current sources coupled to both the positive (12) as the negative (13) supply voltage terminal. Figure 2B shows a further elaborated version of the feedback circuit of Figure 2A, which has current sources connected to the positive supply terminal only. The circuit of Figure 2B further comprises a diode arrangement 25 of one or more diodes, a bipolar transistor T 24 , a current source 22 and a resistor R 24 . The current source 22 is coupled between the point 12 of constant potential and the collector of the transistor T 4 , and is further coupled via the diode arrangement 25 to the base terminal of the transistor T 2 . The base terminal of the said transistor is also coupled to the point 13 of constant potential via the resistor R 24 . The emitter of the transistor T 24 is coupled to the point 13 of constant potential, and its collector is coupled to the interconnected emitter and source of the transistors T 4 and T 3 respectively. The circuit part formed by the elements 22, 25, R 2 and T 24 effectively replaces the current source 24 in Figure 2A. The circuits of the Figures 2 A and 2B further show a switch S j connected in parallel to the resistor R j . When activating the amplifier circuit of Figure 1, or when the current value through the MR element should be changed, the capacitor C j must initially be charged (or discharged) so that the amplifier circuit can settle to the new situation. In order to settle fast, the resistor R j is short-circuited by the switch S j under the influence of a switching signal applied to the control signal input 100, so that the current for charging the capacitor C j can be supplied by the current source 21, or discharging can take place via the current source 24. The charging time of the capacitor C : is thus limited by the maximum current that can be supplied by the current source 21, and the discharging time is limited by the maximum current that can be received by the current source 24. Replacing the current source 24 of Figure 2 A by the elements 22, 25, R 24 and T 24 in Figure.2B already offers a shortening of the discharge time, as the transistor T 24 can sink currents which are up to two orders of magnitude larger than the current through the current source 22. Figure 2C shows a feedback circuit in which the charging time of the capacitor C j can be shortened. The circuit of Figure 2C further comprises a MOS transistor T 5 , a bipolar transistor T 6 and a bipolar diode element 40. The gate and drain terminals of the transistor T 5 are interconnected and both coupled to the current source 21 and to a base terminal of the transistor T 6 via the diode element 40. The source terminals of the transistors T 3 and T 5 are interconnected. A collector terminal of the transistor T 6 is coupled to point 12 of constant potential. An emitter terminal of the transistor T 6 is coupled to the interconnected gate and drain terminals of the transistor T 3 . The circuit comprising the transistors T 3 , T 6 and T 5 and the diode element 40 form a class- A/B circuit and provides a quicker charging of the capacitor element C during initialisation of the arrangement by means of current supplied by the transistor T 6 . Figure 3A shows a further-elaborated version of the amplifier circuit 1 of Figure 1. The circuit of Figure 3 A comprises a bipolar transistor T 8 , which has its base terminal coupled to the source terminal of the transistor T j , its collector to the point 13 of constant potential, and its emitter coupled to the reference point 10. Further a current source 36 is coupled between the reference point 10 and the second point 12 of constant potential. This circuit has the advantage that the DC voltage present at the reference point 10 follows the DC voltage present at the terminal 7 of the amplifier circuit. This means that voltage variations occurring across the MR element R^ do not appear across the load resistor R . The voltage difference between the terminals 7 and 10 is equal to V d . If F j is one of the circuits of the Figures 2A, 2B or 2C, the voltage difference between the terminals 6 and 7 equals V + V clll - V ch2 , see above, so that the DC offset across the load resistor R n is low (V clll - V cll2 ). Only voltage variations in the transistor T j , resulting from the current variations through the transistor T l 5 still appear across the load resistor R n . A further improvement of the amplifier circuit of Figure 3A is disclosed in Figure 3B. The amplifier circuit 1 further has a MOS transistor T 10 and a bipolar transistor T j j . The gate of transistor T 10 is connected to the gate of the transistor T j , the drain is coupled to the point 12 of constant potential via a current source 54, as well as coupled to the base of the transistor T π via a diode arrangement 44 consisting of one or more series connected diodes. The source of the transistor T 10 is coupled to the collector of the transistor T n as well as to the base of the transistor T g . The emitter of the transistor T j j is coupled to the point 13 of constant potential. The voltage difference between the gate of the transistor T j and the terminal 10 equals V - V d , where V is the gate-source voltage of the transistor T 10 . If F j is again one of the circuits of the Figures 2A, 2B or 2C, the voltage difference between the gate of the transistor T j and terminal 6 equals V gs ' - V d , where V gs ' is the gate-source voltage of the transistor T 3 . The voltage across the load resistor R n now equals V ' - V . If the current through transistor T 10 is made equal to the current through the transistor T 3 , and further the transistors T 10 and T 3 have equal dimensions, the said voltage becomes practically zero, independent of the value of the MR bias current. It will be clear that, instead of the combination of the current source 54, the diode arrangement 44 and the transistor T n , a current source could have been coupled between the emitter of the transistor T j j and ground potential. Figure 4A shows a further improvement of the amplifier circuit of Figure 3A. The amplifier circuit comprises a bipolar transistor T 7 which is coupled between the drain terminal of the transistor T j and the terminal 6. Its base terminal is coupled to the point 12 of constant potential via the current source 36, and to the point 10 via a resistor R 5 . By means of the transistor T 7 , the transistor T j is cascoded in order to get a higher output impedance at the terminal 6 and to prevent the Millering of the drain-gate capacitance of transistor T j . Figure 4B shows an alternative of the amplifier circuit of Figure 4 A. It additionally comprises a transistor T 9 , resistors R 2 , R 3 and R and a current source 31. The base terminal of the transistor T 7 is connected to an emitter terminal of the transistor T 9 , a base terminal of which is coupled to the source terminal of the transistor T j via the resistor R 2 . The collector of the transistor T 9 is coupled to the point 13 of constant potential. The emitter of the transistor T 9 is further coupled to the point 12 of constant potential via the current source 31. The base of the transistor T 9 is coupled to the emitter of the transistor T 8 via the resistor R 3 , and to the reference point 10 via the resistors R 3 and R 4 . Further, the construction of the transistors T 7 and T 9 provides a voltage at the interconnection node 32 of the emitter of transistor T 7 and the drain of transistor T j , which is roughly half way between the voltages present on the terminals 7 and 6. This means that a voltage difference of V d /2 is present between the node 32 and the terminal 7, and between the nodes 32 and the terminal 6, as the voltage difference between the terminals 6 and 7 is V d , as explained previously. It should be noted that Figure 4A and Figure 4B are derived from Figure 3A by adding the cascode transistor T 7 , using different biasing schemes. The same cascode principles can be added to the circuit of Figure 3B. Figure 5 shows another embodiment of the amplifier circuit. The amplifier circuit of Figure 5 is a further elaboration of the circuit of Figure 3B. Also in this case cascoding can be applied. The amplifier circuit of Figure 5 differs from the amplifier circuit of Figure 3B in that it further comprises an impedance network 71. Further, diode 46 and a capacitor element C 3 are present. An emitter terminal of the transistor T 8 is coupled to the first terminal 6 of the amplifier circuit via the impedance network 71, as well as to an output terminal of the current source 36. The collector terminal of the transistor T 8 is coupled to a terminal of the load impedance R n '. From the Figure, it appears that the reference point 10 in Figure 3B has now become the reference point 10', which has the same potential as the first point 13 of constant potential, that is ground. The base terminal of the transistor T π is coupled via the diode 46 to the point 13 of constant potential. The base terminal of the transistor T 8 is coupled to the first point 13 of constant potential via the capacitor element C 3 . Signal currents I s generated by the MR element R^ flow from the MR element to the terminal 7, via the transistor T j , the impedance network 71 and the transistor T 8 to the load impedance R π , the terminals 48,48' now forming the output terminal of the arrangement. The capacitor element C 3 filters out a noise component that would otherwise be present in the output signal at the output terminal 48,48'. It should be noted that the embodiments of the Figures 3A, 3B, 4 A and 4B, where the output 8,8' of the amplifier circuit is connected to the terminals of the load impedance R n , are particularly suitable for use in an arrangement provided with only one MR element R ml . The embodiment of Figure 5, where the output of the amplifier circuit is formed by the terminals 48,48' is particularly useful in an arrangement having two MR elements R m j,R m2 - It should be further noted that likewise the circuits of the Figures 3A, 3B, 4A and 4B could have been provided with a load impedance R jj ' coupled between the collector of the transistor T 8 and the point 13 of constant potential, which is preferred for an arrangement having two MR elements. In such arrangements provided with two MR elements R ml and R m2 , see also the arrangement of Figure 6, each MR element is coupled to an amplifier circuit of a type as described above. The output of such an arrangement is then formed by the terminals 48 of each of the two amplifier circuits. Figure 6 shows an embodiment of an arrangement which is in the form of a balanced circuit, and comprises two MR elements. The arrangement comprises a read head having a first and a second magneto-resistive element R ml and R^ respectively. Both MR elements R mj and R m2 of the head scan the same track (not shown), so that they read the same signal from the track. The left hand part of the circuit shown in Figure 6 is largely identical to the circuit diagram shown in Figure 1. A first terminal 63 of the MR element R m2 is connected to the first point 13 of constant potential (ground). Further, a second bias- current generator 62 is available, having an output for supplying a second bias current (I b2 ). Another terminal of the bias-current generator 62 is coupled to the terminal 12, on which the positive supply voltage is available. The amplifier circuit 61 has a first terminal 66 coupled to the output of the second bias-current generator 62 and a second terminal 67 coupled to the second terminal 64 of the second magneto-resistive head R, n2 . The second bias-current generator 62, the second amplifier circuit 61 and the second magneto-resistive element R m2 form a series arrangement between the terminals 12 and 13. The second amplifier circuit 61 comprises a transistor T 2 , which is in the form of a MOS transistor, a load impedance R 12 , a feedback circuit F 2 and a capacitor element C 2 . The source terminal of the transistor T 2 is coupled to the second terminal 67 of the amplifier circuit 61. The drain terminal of the transistor T 2 is coupled to the first terminal 66 of the amplifier circuit 61. The gate terminal of the transistor T 2 is coupled to the first terminal 66 of the amplifier circuit 61, via the feedback circuit F 2 . Further, the gate terminal of the transistor T 2 is coupled to the source terminal of the transistor T j via the second capacitor element C 2 . Moreover, the gate terminal of the transistor T j is coupled to the source terminal of the transistor T 2 via the capacitor element C j . It is however also possible to couple both capacitor elements to the point 13 of constant potential (ground). However the cross-coupled connection of the capacitor elements, as shown in Figure 6, is preferred as it reduces the noise. A load impedance R 12 is coupled between the terminal 66 of the amplifier circuit 61 and a reference point 10", on which point a reference voltage V ref2 is available. The voltage V ref2 may differ from the voltage V refl , as the DC voltages across the MR elements R ml and R m2 can be different owing to mismatch of the resistance of the MR elements and/or unequal MR bias currents I bl and I b2 . Constructions similar to the feedback circuits of the Figures 2A, 2B or 2C can be used for the feedback circuit F 2 of Figure 6. It will further be clear that the amplifier circuits as shown in the Figures 3 A, 3B, 4A, 4B and 5 can be used for the amplifier circuit 61 of Figure 6. It has been said previously that the two MR elements read a signal from the same track. When the two output signals V lout and V 2out are added, an output signal which is the sum of both signals will appear, and systematic DC offset in both amplifier circuits 1 and 61 will cancel. This systematic DC offset is for example the term V clll -V ch2 between the nodes 6 and 10 (Figure 3A), discussed previously, or the DC voltage across the grounded load resistors, such as R n ' in Figure 5. Figure 7 shows a further improvement of the arrangement having only one MR element. Figure 7 shows the provision of an electro-magnetic shielding 75 over the electrical connection 76 connecting the terminal 4 of the MR element R,^ with the terminal 7 of the amplifier circuit 1. The shielding 75 is connected to ground via the electrical connection 77. This shielding prevents electro-magnetic stray fields from disturbing the signals read out by means of the head. The shielding can be realized by means of a kind of coaxial cable. However, also simpler constructions can be used for the shielding means, for instance by wrapping the ground conductor around the signal carrying conductor. Figure 8 shows a top view of the reading out of information from a track on the disk shaped record carrier 80, by means of a read head having two MR elements. Both MR elements R ml and R m2 are coupled together via an insulating layer 90 and both read the full width of the same track 81. The arrangements disclosed are preferably intended for hard disk applications, for low supply voltages, such as 3.3 V ± 10% and 5.0 V ± 10%. The bias current can be kept low, as the bias current is practically only needed for the MR element. A low-noise amplification of the signals read out can be obtained. The record carrier is preferably connected to ground via an electrical connection. Figures 9A and 9B show units that can be coupled together in order to realize a multiplexed read out of information from a track on a record carrier by means of two or more MR elements. Figure 9A shows the circuit part which is common to all MR elements and Figure 9B shows the circuit part for each MR element. Only one such circuit part for the MR element R ml is shown. For other MR elements the circuit part of Figure 9B should be copied. The common circuit part of Figure 9 A shows at the left side of the vertical broken line a circuit part indicated by the reference numeral 100, which circuit part is largely resembles the feedback circuit of Figure 2C. It lacks the resistor R j and the switch Sj, which are included in the circuit part shown in Figure 9B. At the right hand side of the broken line, the circuit part 101 largely resembles the amplifier circuits of Figure 4 A and 5. Two or more of the circuits of Figure 9B can be coupled to the common circuit of Figure 9A by interconnecting the terminal k j ' of the common circuit of Figure 9A with the terminals k j of the two or more circuit parts of Figure 9B. In the same way the terminals k 2 and k 2 ', k 3 and k 3 ', and k 4 and k 4 ' are interconnected. Multiplexing is realized by means of the switches S 2 in each of the circuits of Figure 9B. One of the switches S 2 of one of the circuits of Figure 9B coupled to the common circuit of Figure 9A, is opened and the switches S 2 of the other circuits of Figure 9B are closed. In that situation, all of the MR elements R ml are switched off except one, so that the signal read by that MR element is applied to and amplified by the circuit part of Figure 9A. Figure 10 shows the circuit part of a balanced version of the head, comprising two MR elements R ml and R m2 , in a fashion as shown in Figure 6, where multiplexing is made possible. Figure 10 shows the circuit part including the two MR elements that is separate for each of the heads comprising two MR elements. The circuit part is largely mirror symmetrical, where the left hand part, left from the vertical broken line in Figure 10, is the same as the circuit part of Figure 9B. The circuit part of the transistors T j and T 2 and the capacitors C j and C 2 is identical to the corresponding circuit part of those elements in Figure 6. The circuit part of Figure 9 A is doubled, so as to obtain the common circuit part for each of the heads. The circuit part of Figure 9 A is thus coupled to the left hand part of the circuit of Figure 10, as has been explained above for the interconnection between the circuits of Figure 9 A and 9B. The right hand circuit part of Figure 10 is coupled to a circuit part identical to the circuit part of Figure 10A. Switching the head of Figure 10 into the circuit means that both switches S 2 and S 3 are in the open position as shown. Consequently, the corresponding switches S 2 and S 3 of the other heads coupled to the common circuit are in their closed position. Switching the head off is realized by closing both switches S 2 and S 3 . Figure 11 shows an alternative further-elaborated version of the amplifier circuit 1 of Figure 1. By way of example the bias current generator 2 is implemented with a PNP transistor T 20 , having the emitter coupled to the point of constant positive potential 12 via degeneration resistor 210, the base connected to a reference point 200 which supplies a reference voltage V ref3 and the collector terminal to the output 5 of the bias current generator 2. The first terminal 6 of the amplifier circuit 1 is directly connected to the output 5. However, in contradistinction to Figure 1, the terminal 8, which interconnects the load impedance R n and the feedback circuit F l 5 is connected to the drain of the transistor T j via the collector-emitter path of a NPN transistor T 21 . The emitter of transistor T 21 is connected to the drain of transistor T j , the base is connected to a reference point 202 which supplies a reference voltage V ref and the collector is coupled to the load impedance R jj . The transistors T j and T 21 form a cascoded output stage. The collector of transistor T 21 may be connected to the load impedance R jj via the collector-emitter path of an optional further NPN cascode transistor T 22 , the base of which further transistor T 22 is connected to a reference point 204 which supplies a reference voltage V ref5 . The feedback circuit F j is a transconductance type stage 206 having differential voltage inputs connected to the terminal 8 and a reference point 208 which supplies a reference voltage V ref6 and having a high-ohmic current output coupled to the gate of transistor T j . The transconductance Gm of the transconductance stage 206 should have a low value as it determines the cut-off frequency of the feedback circuit F j . Transistor T 20 and emitter resistor 210 can be implemented with a programmable current output digital to analog converter (IDAC) for supplying the bias current of the magneto-resistive (MR) element. In the arrangement of Figure 11 the IDAC supplies the variable part of the MR element's bias current, for instance 0 mA to 15.5 mA in steps of 0.5 mA, whereas a fixed current, for example 5 mA, is provided by the low-ohmic cascode output stage T 21 . In order to obtain low noise, transistor T j should be large. The advantages of the arrangement of Figure 11 are: (1) the large low-noise MOS transistor T j and the IDAC can have a low output impedance, since they feed their respective currents into a very low-ohmic emitter of the cascode transistor T 21 ; (2) the drain-to-gate capacitance of the large transistor T j is not Millered; (3) the IDAC provide lower bias current and a corresponding lower noise; and (4) the IDAC feeds its current to a low voltage node, which permits the value of emitter resistor 210 to increase, resulting in a further reduction of noise. It is to be noted that the bias current generator 2 can be omitted entirely, if only the fixed bias current supplied by the cascode output stage T 21 is sufficient to bias the MR element. Figure 12 shows a balanced version of the arrangement of Figure 11. The two amplifiers 1 and 61, in particular the capacitors C j and the corresponding capacitor C 2 of the second amplifier 61, are interconnected in a similar fashion as shown in Figure 6. The degeneration resistor 212, the PNP transistor T 23 , the NPN transistor T 24 , the NPN transistor T 25 and the transconductance stage 214 of the second amplifier 61 correspond with the degeneration resistor 210, the PNP transistor T 20 , the NPN transistor T 21 , the NPN transistor T 22 and the transconductance stage 206 of the first amplifier 1 and are connected similarly. At high frequencies the capacitors C j and C 2 form short circuits and place the gate-source paths of the transistors T j and T 2 anti-parallel. The same applies to the two individual equivalent noise resistors R^ of the MOS transistors T j and T 2 . The noise resistance R n is about equal to R 0 , R 0 being the inverse of the transconductance of the transistors T j and T 2 . The total effective noise resistance in the first amplifier 1 of the arrangement of Figure 12 is R^ +R 0 /2 instead of R m l +R 0 of the first amplifier 1 of the arrangement of Figure 11. The balanced version thus provides a reduction of noise. One of the MR elements R^ or R m2 may be omitted in single stripe MR read heads. In that case terminal 7 or 67 is coupled to ground 13. In the embodiments as shown in the Figures, certain transistors, for example the transistors Tj, T 2 , T 3 , T 5 and T 10 are preferably unipolar MOS transistors; other transistors such as the transistors T 4 , T 24 , T 6 , T 7 , T 8 , T 9 , T π and T 21 , are preferably bipolar transistors. It is, however, possible to use bipolar transistors instead of unipolar transistors and vice versa, or to use only bipolar or only unipolar transistors. The first main flow terminal, the second main flow terminal and the control terminal of a transistor correspond to, respectively, the source terminal, the drain terminal and gate terminal of an unipolar transistor and to, respectively, the emitter terminal, the collector terminal and base terminal of a bipolar transistor.

Claims: Claims 1. Arrangement for reading out an information signal from a magnetic record carrier, comprising - a read head having a magneto-resistive element (R ml ) with a first terminal (3) connected to a first point (13) of constant potential, and with a second terminal (4), - a first bias-current means (2; T 20 ,T 21 ) for supplying a bias-current, - a first amplifier circuit (1) comprising an output terminal (8) for supplying the information signal (V out ), a first terminal (6) coupled to the first bias-current means (2; T 20 ,T 21 ) and to the output terminal (8), a second terminal (7) coupled to the second terminal (4) of the magneto-resistive head (R ml ) so as to form a series arrangement of the first bias-current means (2; T 20 ,T 21 ), the first amplifier circuit (1) and the magneto-resistive element (R mj ) between a second point (12) of constant potential and said first point (13) of constant potential, the first amplifier circuit (1) further comprising a first transistor (T j ), a first feedback circuit (F j ), a first load impedance (RJJ) and a first capacitor element (C j ), a first main flow terminal of the first transistor (T j ) being connected to the second terminal (7) of the first amplifier circuit (1), a second main flow terminal of the first transistor (T j ) being coupled to the first terminal (6) of the first amplifier circuit (1), a control terminal of the first transistor (T j ) being coupled to the output terminal (8) of the first amplifier circuit (1) via the first feedback circuit (F j ), the first load impedance (R u ) being coupled between the output terminal (8) of the first amplifier circuit (1) and a reference voltage terminal (12), characterized in that the arrangement further comprises - a second bias-current means (62; T 23 ,T 24 ) for supplying a bias-current, - a second amplifier circuit (61) comprising an output terminal (68), a first terminal (66) coupled to the second bias-current means (62; T 23 ,T 24 ) and to the output terminal (68), a second terminal (67) for coupling to a second terminal (64) of the magneto-resistive head so as to form a series arrangement of the second bias-current means (62; T 23 ,T 24 ), the second amplifier circuit (61) and the magneto-resistive element between the second point (12) of constant potential and said first point (13) of constant potential, the second amplifier circuit (61) further comprising a second transistor (T 2 ), a second feedback circuit (F 2 ), a second load impedance (R 12 ) and a second capacitor element (C 2 ), a first main flow terminal of the second transistor (T 2 ) being connected to the second terminal (67) of the second amplifier circuit (61), a second main flow terminal of the second transistor (T 2 ) being coupled to the first terminal (66) of the second amplifier circuit (61), a control terminal of the second transistor (T 2 ) being coupled to the output terminal (68) of the second amplifier circuit (61) via the second feedback circuit (F 2 ), the second load impedance (R 12 ) being coupled between the output terminal (68) of the second amplifier circuit (61) and a reference voltage terminal (12), and in that the control terminal of the second transistor (T 2 ) is coupled to the second terminal (7) of the first amplifier circuit (1) via the second capacitor element (C 2 ), and the control terminal of the first transistor (T j ) is coupled to the second terminal (67) of the second amplifier circuit (61) via the first capacitor element (C j ). 2. Arrangement as claimed in claim 1, characterized in that the first terminal (6) of the first amplifier circuit (1) is coupled to the output terminal (8) of the first amplifier circuit (1) via a cascode transistor (T 21 ) having an first main flow terminal connected to the first terminal (6) of the first amplifier circuit (1) and a second main flow terminal coupled to the output terminal (8) of the first amplifier circuit (1) and in that the first terminal (66) of the second amplifier circuit (61) is coupled to the output terminal (68) of the second amplifier circuit (61) via a cascode transistor (T 24 ) having an first main flow terminal connected to the first terminal (66) of the second amplifier circuit (61) and a second main flow terminal coupled to the output terminal (68) of the second amplifier circuit (61). 3. Arrangement as claimed in claim 2, characterized in that the second main flow terminal of the cascode transistor (T 21 ) of the first amplifier circuit (1) is coupled to the output terminal (8) of the first amplifier circuit (1) via a further cascode transistor (T 22 ) having a first main flow terminal connected to the second main flow terminal of said first mentioned cascode transistor (T 21 ) of the first amplifier circuit (1) and a second main flow terminal connected to the output terminal (8) of the first amplifier circuit (1) and in that the second main flow terminal of the cascode transistor (T 24 ) of the second amplifier circuit (61) is coupled to the output terminal (68) of the second amplifier circuit (61) via a further cascode transistor (T 25 ) having a first main flow terminal connected to the second main flow terminal of said first mentioned cascode transistor (T 24 ) of the second amplifier circuit (61) and a second main flow terminal connected to the output terminal (68) of the second amplifier circuit (61). 4. Arrangement as claimed in claim 1 , 2 or 3, characterized in that the first feedback circuit (F j ) comprises a transconductance stage (206) having differential voltage inputs coupled to the output terminal (8) of the first amplifier circuit (1) and a reference voltage terminal (208) and a current output terminal coupled to the control terminal of the first transistor T j and in that the second feedback circuit F 2 comprises a transconductance stage (214) having differential voltage inputs coupled to the output terminal (68) of the second amplifier circuit (61) and the reference voltage terminal (208) and a current output terminal coupled to the control terminal of the second transistor T 2 . 5. Arrangement as claimed in claim 1, 2, 3 or 4, characterized in that at least one of the first bias current means (2; T 20 ,T 21 ) and the second bias current means (62; T 23 ,T 24 ) comprises a bias-current generator (2; 62) having an output (5; 65) connected to the first terminal (6; 66)..

Inventors: VILA LOBOS RAMALHO JOAO NUNO, VOORMAN JOHANNES OTTO, VILA LOBOS RAMALHO, JOAO, NUNO, VOORMAN, JOHANNES, OTTO
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1994
Main classification: G01R33
IPC codes: G01R33, G11B5, H03F3