Solder ball connections and assembly process

Abstract: High melting temperature Pb/Sn 95/5 solder balls (18) are connected to copper pads on the bottom of a ceramic chip carrier substrate (10) by low melting temperature eutectic Pb/Sn solder. The connection is made by quick reflow to prevent dissolving Pb into the eutectic solder and raising its melting temperature. Then the module is placed on a fiberglass-epoxy circuit board with the solder balls on eutectic Pb/Sn solder bumps on copper pads of the board. The structure is reflowed to simultaneously melt the solder on both sides of the balls to allow each ball to center between the carrier pad and circuit board pad to form a more symmetric joint. This process results in structure that are more reliable under high temperature cycling. Also, to further improve reliability, the balls are made as large as the I/O spacing allows without bridging beam on balls; the two pads are about the same size with more solder on the smaller pad; the pads are at least 75% of the ball diameter; and the eutectic joints are made as large as possible without bridging between pads. For reliability at even higher temperature cycles or larger substrate sizes columns are used instead of balls.

Description: This invention relates to surface mount solder connections using HMT (high melting temperature) metal-balls between a grid of contacts on a component and a mirror image array of contacts of an electrical interconnect structure and more specifically to the composition of the HMT solder balls and LMT (low melting temperature) solder joining the balls to the contacts, the specific geometry of the connections, FR-4 (glass and epoxy) circuit boards and MLC (multi-layer ceramic) chip carriers for such interconnections, the processes for producing the boards and carriers, and the process for attaching the carriers to the boards. BACKGROUND OF THIS INVENTION Solder-ball connections have been used for mounting ICs (integrated computer chips) using the C-4 (controlled collapse chip connection) technology since first described in U.S. patents 3,401,126 and 3,429,040 by Miller. Packaging Electronic Systems by Dally ( McGraw-Hill 1990 p. 113) describes flip chip or C-4 connections. In Dally, "Chip bond pads are deployed in an area array over the surface of the chip. ... These bonding pads are 0,127 mm (5 mil) in diameter on 0,254 mm (10 mil) centers. Matching bonding pads are produced on a ceramic substrate so that the pads on the chip and the ceramic coincide. Spheres of solder 0,127 mm (5 mil) in diameter are placed on the ceramic substrate pads ... and the chip is positioned and aligned relative to the substrate. The assembly is heated until the solder spheres begin to soften and a controlled collapse of the sphere takes place as the solder simultaneously wets both pads. A myriad of solder structures have been proposed for mounting IC chips as well as for interconnection to other levels of circuitry and electronic packaging." "Ball Grid Arrays: The Hot New Package" by Terry Costlow and "Solder Balls Make Connections" by Glenda Derman both in : Electronic Engineering Times March 15, 1993, describe using solder balls to connect ceramic or flexible chip carriers to circuit boards. U. S. patent 4,132,341 to Bratschum describes the self-centering action of conductors spanning between solder pads of two components when both pads are simultaneously reflowed. U.S. patent 4,831,724 describes the self-centering of a component when it is vibrated during reflow. Fabrication of multi-layer ceramic chip carriers is described in U.S. patents 3,518,756; 3,988,405; and 4,202,007 as well as "A Fabrication Technique For Multi-Layer Ceramic Modules" by H.D. Kaiser et al., Solid State Technology, May 1972, pp. 35-40 and "The Third Dimension in Thick-Films Multilayer Technology" by W. L. Clough, Microelectronics, Vol. 13, No. 9 (1970), pp. 23-30. Fabrication of multi-layer circuit boards is described in U.S. patents 3,554,877; 3,791,858; and 3,554,877. Thin film techniques are described in U.S. patent 3,791,858. U.S. patent 4,604,644 to Beckham describes materials and structures for encapsulating C-4 connections. U.S. patents 4,701,482 to Itoh and 4,999,699 to Christie et al. disclose epoxies and guidance in selecting epoxies for electronic applications. Flexible film chip carriers (known in the art as ATAB) are described in U.S. patents 4,681,654; 4,766,670 and 5,159,535. In ATAB (area tape automated bonding) a flexible circuit board chip carrier is mounted on a circuit board using solder-ball connect. U.S. patent 5,147,084 to Behun, describes using a HMP (high melting point) solder ball in association with a LMP (low melting point) solder. FIG 1A of that patent is similar to FIG 4 of this application. "A part 10 is to be joined to a board 11. Part 10 has internal metallurgy 14 which terminates at the surface at a bonding pads 12. A ... LMP solder 16 is applied to a bonding pad 12. A ... HMP solder ball 18 is placed in contact with LMP solder 16 and the assembly is heated to reflow the LMP solder which then wets to the non-molten HMP solder ball. ... Board 11 is also illustrated with internal metallurgy 15, terminating on the surface bonding pad 17. ... the assembled part 10 ... is brought into contact with part 11 having pad 17 and LMP solder 13, and the two are heated to a temperature sufficient to reflow the LMP solder but not sufficient to melt the HMP solder ball. The LMP solder 13 which is attached to the bonding pad 17, on board 11, will wet the HMP ball and connection will be achieved." US-Patent 5,099,090, which represent the closest prior art over the invention, discloses methods of producing conductive traces on a circuit substrate which allows to fabricate interconnect structures. OBJECTS OF THIS INVENTION Therefore, it is an object of this invention to provide a process for manufacturing an improved reliable interconnect assembly using ball connection. SUMMARY OF THIS INVENTION This object is solved by the invention as set forth in the claims. In this invention of applicants, it was discovered that solder-ball connections between confronting metal contact grids on rigid substrates which were made using a process similar to that which was used for ATAB were not reliable due to thermal fatigue of the solder joints between the balls and the contacts. It was discovered that the joints were not all symmetrical due to mis-registration of contacts (allowable tolerances in contact location) causing misalignment between confronting contacts, and that the joints could be made more symmetrical and more reliable by simultaneously reflowing the top and bottom LMT solder joints between each HMP metal-ball and both respective contacts of the ball. This allows the balls to be moved by surface tension of the melted solder to more symmetrical positions between the centers of the contacts within the plane defined by the array of the solder balls. It was discovered that making the balls larger reduces fatigue, but that the size of the balls is constrained by the specified interconnection spacing and a nominal spacing between balls necessary to reliably prevent electrical connection from developing between the balls. Similarly, it was discovered that making the contacts larger reduces fatigue, but the size of the contacts are constrained by the specified interconnect spacing and the nominal spacing between contacts necessary to reliably prevent electrical connection from developing between contacts (e.g. solder bridging). For reliable interconnections fatigue is minimized by making the balls slightly smaller than the spacing between contacts and making the contacts slightly smaller than the balls. It was discovered that the reliability of the connections were affected by the relative size between the contacts on either side of each ball and that fatigue could be minimized by making the contacts equal sized. It was discovered that fatigue could be minimized, for different sized contacts on each side of the ball, by making the solder volume larger for the joint with the smaller contact. It was discovered that increasing the cross section of the solder joints reduced fatigue but the volume increase is constrained by the necessity to reliably prevent solder bridging from developing between adjacent balls and between adjacent contacts. Finally it was discovered that reducing the cross section of the solder joints below about 2/3 of the diameter of the ball has a remarkably deleterious effect on the fatigue life of the connection. The invention further uses a process for fabricating an interconnect structure, comprising the steps of: producing a fiberglass re-enforced epoxy board; drilling one or more holes through the board; plating the interior of the through-holes with conductive metal; forming lands of conductive metal around the holes on a major surface of the board; forming a rectangular array or grid of multiple, circular, conductive, metal contacts which are larger than the lands and positioned so that four contacts define a square that surrounds each of the lands; forming a conductor extending in a diagonal direction in relation to the square to one of the contacts between each respective land and one of the surrounding contacts. The process for fabricating an interconnect structure, in which the steps of plating the holes, forming lands, forming contacts and forming a conductor are performed simultaneously in an additive photo-lithographic process. The process for fabricating an interconnect structure, further comprising the step of depositing joining-material on the contacts. The immediately preceding process for fabricating an interconnect structure with deposited joining-material, further comprising the step of connecting to the joining-material, a metal-ball with a melting temperature substantially above the melting temperature of the joining-material. The immediately preceding process for fabricating an interconnect structure, further comprising the step of heating to melt the joining-material to reflow connect the balls onto the contacts and then cooling the joining-material to solidify it. The invention also uses a process for making an interconnect assembly, comprising the steps of: producing an FR-4 board with a multitude of wiring layers; forming circular copper lands in a wiring layer on a major surface of the board; making holes through the lands and through the board; selectively depositing copper after drilling to plate the through-holes for connecting the lands to other wiring layers; forming a rectangular array or grid of round copper contacts larger than the lands, about 0.7 mm diameter, and spaced at about 1.25 mm centers on the major surface and arranged so that four contacts define a square that surrounds each of the lands; forming a conductor which is narrower than the contacts and narrower than the lands which extend between each of the lands surrounded by contacts in a diagonal direction in relation to the square of surrounding contacts; depositing solder resist at least partially covering the conductor and the lands and extending between the contacts to prevent solder bridging; depositing a joining solder material containing about 37/63% Pb/Sn solder alloy on each of the contacts in the array on the board; producing multiple green sheets of glass/ceramic particles and an organic binder; forming via holes through the sheets; screen printing conductive material into the holes and onto one of the surfaces of the sheets to form a conductive pattern; stacking the sheets together; sintering the stack of sheets in an oven to form a multi-layer ceramic chip carrier with an array of copper contacts on a major surface which are about 0.7 mm wide, are spaced about 1.25 mm apart, and are arranged approximately mirror image to the array of contacts of the board; forming an array of round contacts on an exterior major surface of the carrier; depositing solder resist between the contacts to prevent solder bridging; depositing a joining solder material containing about 37/63% Pb/Sn solder alloy on each of the contacts in the array on the carrier; positioning a ball of about 90/10% Pb/Sn solder alloy and about 0.9 mm diameter in contact with the joining solder on each respective contact in the array of the carrier to define a plane of solder-balls; reflowing to melt the joining solder material deposited on the contacts of the carrier without melting the solder-balls in order to solder the balls to the contacts of the carrier and using the minimal temperature and time required to form reliable mechanical joints in order to minimize diffusion of Pb from the balls into the melted solder; cooling the carrier to solidify the joining solder; positioning the ceramic carrier parallel to the circuit board with the solder-balls about in contact with the joining solder deposited on the array of contacts on the board so that each solder-ball is between a pair of contacts; heating the substrates while positioned together to a temperature at which the solder deposited on the contacts of both the carrier and board are simultaneously melted and the solder-balls remain solid for moving the solder-balls by surface tension of the melted solder material in directions within the plane of the solder-balls to positions about midway between the centers of the pairs of contacts to produce symmetric connections between the substrates; and cooling the substrates below the melting temperature of the solder materials to solidify the solder material. The process for making an interconnect assembly, in which: each of the contacts on the board include a very thin extension over the solder resist; the solder is deposited on the contacts of the board, including the extensions, by wave soldering; and the holes are formed in the board by drilling and formed in the sheets by punching; and the process further comprises the steps of: reflowing the deposited joining solder on the carrier before positioning the solder balls; flattening the joining solder on the carrier before positioning the solder-balls on the carrier; depositing sticky flux on the flattened joining solder on the carrier before positioning the solder-balls on the carrier; reflowing the deposited solder on the board before positioning the carrier with the board; flattening the joining solder on the board before positioning the carrier with the board; and applying flux to the flattened joining solder for joining the balls to the board before positioning the carrier with the board. The invention also uses a fabricated interconnect structure comprising: a multi-layer substrate having a wiring layer on the surface of the substrate; a multitude of metal contacts in a matrix at positions defined by intersections of a grid of a multitude of parallel equally spaced lines in each of two perpendicular directions in a plane of the surface wiring layer; a multitude of conducting vias connecting between one or more other wiring layers of the substrate and the surface wiring layer at about the centers of squares defined by four of the contacts; a conductor of the surface wiring layer for each respective via, which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via. This invention will be described in greater detail in reference to the following drawing. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process diagram which illustrates producing an multi-layer ceramic chip carrier (MLC). FIG. 2 illustrates the process for producing an fiberglass-epoxy circuit board (FR-4). FIG. 3 illustrate the process for producing the connections between the MLC and FR-4. FIG. 4 is a schematic partial cross section of a specific embodiment showing part of an MLC chip carrier with solder balls attached to contacts and confronting mirror image contacts of an FR-4 circuit board. FIG. 5 shows the positioning of solder balls on the solder contacts prior to attachment to the MLC of FIG. 4. FIG. 6 shows the MLC and FR-4 of FIG. 4 positioned together. FIG. 7 shows the reflow connections of the MLC to the FR-4 of FIG. 4 in which only the joint between the solder balls and the FR-4 is melted during reflow. FIG. 8 illustrates the reflow connections of the MLC to the FR-4 of FIG. 4 in which both joints of each connection are simultaneously melted to provide a more symmetric connection. FIG. 9 is a schematic cross section through line 9-9 of FIG. 10, illustrating the "dog bone" connection between plated-through-hole via connection of this invention. FIG. 10 is a schematic plan view illustrating part of the array of metal contacts and "dog bone". connections between the plated through holes and contacts. FIG. 11 is larger view of the "dog-bone" arrangement of FIG. 10. FIG. 12 is another embodiment with different sized contacts and inversely proportional solder volumes. FIG. 13 is a plan view of a contact for providing sufficient solder volumes. FIG. 14 is a cross section of the contact of FIG. 13 through line 14-14. FIG. 15 schematically illustrates the information handling system of this invention. The Figures 1-8 and 12-14 relate to the background of the invention. Fig 16-17 illustrate the use of solder columms. DESCRIPTION OF EMBODIMENTS INCLUDING THE BEST MODE As illustrated in FIG 4, a first substrate 10 is produced with a planer array of contacts 12 and vias 14. In this application substrate refers to any component with a flat surface for interconnection which will be referred to as a major surface in contrast to a thin edge surface. Although the invention will increase the reliability of connecting flexible circuit boards such as ATAB (area tape automated bonding) components, preferably the first substrate is a component such as an FR-4, plastic, or ceramic chip carrier, and more preferably a MLC (multi-layer ceramic) chip carrier for which this inventions of this application are especially well suited. As illustrated in FIG. 1, step 101, in the manufacture of ceramic chip carriers, ceramic powders are mixed with binders, solvents and plasticizer and cast to form green sheets to form dielectric layers. In step 102, Vias are made preferably by punching and in step 103, conductive ink or paste (e.g. Mo frit and solvent) is screened to fill the vias. The wiring pattern may also be screened on the surface at this time and/or exterior wiring layers may be made later using a thin film process. For multi-layer ceramic, in step 104, green sheets are stacked and laminated.with heat and pressure into a monolithic structure. Then the green sheet(s) are sintered, in step 105, by firing in an oven with a reducing atmosphere. After sintering the exposed metal is coated for protection (not shown). A thin film process may be used to produce an exterior wiring layer (not shown). For example, conductive metal may be evaporated or sputtered onto the substrate followed by photolithographic patterning which may be followed by dialectic coating and additional thin film layering. The contacts 12 (FIG. 4) may be square or more preferably are approximately round to match the shape of the ball and to allow a closer spacing sufficient to reliably prevent solder bridging. The contacts may be made from any conductive substance, preferably a metal such as Al or Ti and more preferably are made from or covered with Cu, Ni, Au, Pd, or alloys of these. The material may be deposited by screening or a photolithographic process may be followed by chemical and/or electric deposition processes. In step 106 (FIG. 1), the contacts 12 are covered with a volume of a first joining-material 13, 16 respectively, such as a conductive thermoplastic or a solder alloy containing Sn, Pb, Bi, In, Ag to form solder contacts or solder bumps. In the preferred embodiment the joining-material is Pb/Sn solder with 20 to 75 % Sn and the balance mostly Pb and most preferably is about eutectic 63% Sn and 37% Pb. The solder may be deposited in the molten state by a mass soldering method such as wave soldering or may be screened as solder paste (metal particles in a organic carrier) or may be electrically and/or chemically deposited on the contacts following a photolithographic process. In step 107, as shown in FIG. 5, metal-balls are attached to the solder bumps preferably by applying a layer of sticky flux 20 on which the balls are positioned. The balls may be placed simultaneously by transfer from a vacuum die. The flux may be applied just on the contacts or in the entire area of the substrate interconnections. The balls 18 may be copper preferably coated to prevent oxidation, or more preferably are a HMT solder alloy with a melting temperature substantially more than that of the joining-material so that the balls may be reflow joined to the contacts in step 108 without melting the balls. Preferably the balls are Sn and 80 to 97 % Pb most preferably 90 - 95 % Pb. Preferably the attachment is made reliable by reflow heating to join the ball to the contact so the ball will not fall off during later processing. During reflow of the first joining-material 16, surface tension of the melted joining-material will precisely align balls 18 with contacts 12. Centering the balls on the pads of the first substrate helps align the balls with the pads of the second substrate. For solder joining-materials, during reflow, metal elements will dissolve or be transported between the LMT solder and the metal-balls. In order to prevent this the reflow attachment of the balls 18 to substrate 10 should be done at the lowest temperature and in shortest time required to center the balls and prevent losing the balls during subsequent processing. In step 109 the substrate is cooled to solidify the joining-material. A second substrate 11 is produced which also has vias 15 and a planer array of contacts 17. The array of contacts 17 is approximately a mirror image of the array of contacts 12. The second substrate may be a flexible circuit board (e.g. thin polyimide and copper layers), or more preferably a rigid board such as ceramic and is most preferably a multi-layer FR-4 printed circuit board. This inventions of this application are especially well suited to applications where there is a significant difference in the thermal coefficients between rigid first and second substrates. FIG. 2 illustrates the process of manufacturing fiberglass-epoxy circuit boards (FR-4). In step 120, one or more layers of fiberglass cloth are impregnated with epoxy resin solution to form a dielectric layer. For boards with multiple FR-4 layers the layers are only partially cured to form stable B-stage layers. In step 121, at least the internal layers are circuitized. FIG's 9 - 11 illustrate the surface wiring of this invention and is discussed in more detail later. This step includes forming a rectangular array of preferably round contacts forming lands for connection to the vias at the centers of squares defined by four surrounding contacts, and forming connections between the lands and contacts. Usually before drilling for vias that go through all the layers, the B-stage layers are laminated in step 122 with heat and pressure to fuse the layers and fully cure the board. Each layer is circuitized by screening or by a photolithographic process in which a metal foil covering is subtractively removed or metal is selectively chemically and/or electrically added to form a wiring layer on the surface of the layer. In step 123, holes are drilled at the lands, through one or more layers, and in step 124, the holes are internally plated with metal (preferably copper) to form vias for electrical interconnection between the wiring layers on each side of the dielectric layers. In step 125 joining-material is deposited on contacts in a similar manner as previously described for step 106 in the process of producing MLC. In step 131, substrates 10, 11 are moved into confronting position as shown in FIG. 4, and in step 132, are brought together as shown in FIG. 6. The accuracy of the placement machine is limited so that the substrates are not precisely aligned. FIG. 7 shows the results of reflow of only joining-material 13 which moves substrate 10 in the direction of arrow 40 relative to substrate 11 into precise alignment between the substrates. As illustrated, the connections, such as on either side of ball 42, are not symmetric due to tolerances in the positions of the contacts. Therefore, in step 133; as shown in FIG. 8, preferably both joining-materials 13 and 16 on either side of the solder balls 18 are simultaneously reflowed to produce more symmetric connections. When both joints 51 and 52 are simultaneously melted the surface tension of the joining-material will move the ball in the plane 53 of the balls toward a position halfway between the centers 54, 55 of the contacts resulting in a more symmetric connection. Such symmetric connections have a greater fatigue life than the non-symmetric connections of FIG. 7. In step 134, the substrates are cooled to solidify the joining-material of the connections. In step 135, the area between the first and second substrates around the metal-balls is filled with an encapsulant such as epoxy. It is critical to the solder connection configuration invention of applicant that the connections not be encapsulated until after simultaneous reflow of the top and bottom solder joints so that the solder balls can move into alignment between the contacts. After such alignment encapsulating the area between the substrates, around the balls, reduces fatigue stress during thermal cycling. When Balls 18 is reflow attached to contacts 12, some material will be exchanged between the ball and joining-material 16. For example if the ball is 10/90 Sn/Pb and the joining-material is eutectic 63/37 Sn/Pb then after reflow the joining-material will have a higher Pb content and therefore a higher melting temperature. If joining-material 13 is also eutectic Sn/Pb solder then during reflow for connecting the substrates the joints are going to have to be heated to the higher temperature to simultaneously melt. In order to use a minimum temperature for reflow joining-material 16 may have a lead content reduced below eutectic amounts so that during the first reflow it becomes eutectic and then the simultaneous melting during the second reflow is achieved at minimum temperatures. Most preferably the balls in FIG's 1-5 are as large as possible to minimize fatigue stress in the connections only limited by the requirement of reliably preventing bridging between the balls. Stresses in the joints on either side of the balls would be minimized by making the contacts the same size as the balls, however, to reliably prevent bridging between the contacts, the contacts have to be significantly smaller than the balls. As shown in FIG. 8, preferably a solder mask material 53, 54 which repels liquid solder is placed between the contacts to reduce solder bridging so the contacts may be made as close to the size of the balls as possible. For example, connections with 9 mm balls and round contacts of 7 mm diameter spaced at 1.25 mm centers may be reliably made without bridging. /* what are some typical solder mask materials */ Solder volumes should be as large as possible to reduce fatigue but are limited by the requirement to reliably prevent bridging and the cost or difficulty of depositing large volumes of solder. Most preferably, as shown in FIG. 9, in plane 62 defined as the cross section of minimum diameter of the joint 64, the diameter is at least 2/3 of the diameter of the ball 66. For example if the ball is 9 mm in diameter, the joint should be at least 6 mm in diameter in plane 62 and more preferably larger. For ceramic substrates through hole vias are usually filled with a HMP metal, and for thin film layers on ceramic, flex, or FR-4, vias are usually filled or are slightly depressed in relation with contacts that are not on vias. For multi-layer flexible and FR-4 substrates, wiring layers usually contain round lands of metal through which the via holes are formed and which are interconnected between wiring layers by plating the hole. Some of the contacts on FR-4 and flex substrates may occur on such plated vias. Since the diameter of the solder joint is critical, the volume of solder is critical, but the volume can not easily be controlled at such holes (even if previously filled with solder). FIG. 10 schematically shows an arrangement of plated through hole vias 71 each connected to a solder contact 72. This "dog bone" arrangement prevents the solder on contact 72 from flowing into the through hole 73. In this specific embodiment the centers of the contacts are about at the intersections of multiple equally spaced parallel lines 74 and multiple equally spaced parallel lines 75 which are perpendicular to lines 74. Vias 71 are located at the centers of squares 76 defined by four contacts 72 aground via 71. The vias are connected to the contacts through a wire 77 extending under a layer of solder mask 78. FIG. 11 schematically illustrates a single "dog bone" 80 of this invention prior to depositing joining-material on contact 82. A hole 81 (hidden) is made by mechanical or laser drilling into the substrate at least to another wiring layer, and metal is deposited to form contact 82, land 83, connecting wire 84 and to plate the hole 85 leaving opening 86. Solder mask 87 covers most of connecting wire 87 and the outer edge of land 83 as indicated by dashed lines to prevent solder bridging. FIG. 12 schematically illustrates an alternative embodiment in which metal contact 91 is larger than metal contact 92. In this case in order to reduce fatigue and increase fatigue life of the connection, a higher volume of joining-material 93 is placed between ball 94 and the smaller contact 92, than the volume of solder material 95 between the solder ball and larger contact 91. Thus the minimum cross sections of the joints on each side of the solder ball may be made about equal to equalize fatigue at each joint of the connection. FIG's 13 and 14 illustrate a technique to provide higher levels of solder deposited on a contact than can usually be deposited by wave soldering or electrical or chemical (electroless) deposition. Flash layer 130 extends out from contact pad 132 over the layer of solder resist 134 the thickness of the flash is exaggerated for illustration. Solder 136 is deposited electrically, chemically, or preferably by solder wave. The flash is a conductive substance for electrical deposition, a seed materials such as palladium for electroless plating, and may be a solder wettable material for wave soldering. The flash material is selected to dissolve during reflow resulting in all the solder migrating onto the contact pad. Preferably for wave soldering the flash is copper of tin which is sufficiently thick to survive during deposition, but thin enough to fully dissolve during reflow. The thickness of the solder deposited by molten solder wave generally increases as the size of the flash area increases. FIG. 15 shows an information handling system 150 in which computer assembly 151 includes central processor module 152 communicating through one or more wiring layers (not shown) in substrate 153 with computer memory module 154. Computer 152 communicates with computer assembly 155 through cable 156. Computer 155 also includes central processor module 152 communicating through one or more wiring layers (not shown) in substrate 158 with computer memory module 158. One or preferably both modules of each computer are connected to the substrate using the preferred solder ball or solder column connections of the invention. FIG. 16 illustrate solder columns 160 which are similar to the solder balls 18 (FIG. 4) and the previous discussion on materials, geometries, and methods of placement, reflow joining to the modules, reflow connection to the substrates are applicable. They have approximately semi-circular ends and are preferably from 1 to 20 times longer then their diameters. Fatigue is reduced by making the columns longer, but longer columns result in higher module profiles, reduced lead cooling and handling problems that militate against length exceeding that necessary to reliably prevent thermal fatigue failures. In this application the term solder-ball includes hemispherical ended solder columns. In order to join the columns to the module, columns may be reflow heated while attached to the bottom side of the module (i.e. inverted position). This results the columns being closely centered on the contacts and very accurately vertically aligned. In FIG. 17, columns 171 have square ends formed for example from cutting extruded solder wire. Vacuum die 172 includes a flat face 173 with recesses which fit the solder ball or solder column. The recesses communicate with a vacuum reservoir 175 through passages 176 which are significantly smaller than the solder balls or columns to reliably prevent the columns from entering vacuum reservoir 175 and prevent jamming. The vacuum die is used to position the balls or columns on the contacts of a substrate either as shown in FIG. 17 or in an inverted position. Either round or square end columns can be reflow joined in inverted position as in FIG. 16 or by holding the columns vertical during reflow preferably using the vacuum die. The vacuum can be turned off or even reversed during reflow allowing the columns to rest against the solder contacts. When the round or square columns are held in position during reflow joining with the contacts of substrate 178; the columns are not as well centered on the contacts, or as vertically aligned or vertically positioned as the joints formed by hanging. As shown in FIG. 18 when the module substrate is connected to another substrate 181 the joints are not symmetrical. When the simultaneous reflow of the invention is applied as shown in FIG. 19, the joints become much more symmetrical and more reliable.

Claims: A process for fabricating an interconnect structure comprising the steps of: producing a fiberglass-epoxy (FR-4) board (11); drilling holes through the board; plating the through holes (73) with conductive metal for heating vias (71) ; the process is further characterized by the steps of: forming lands of conductive metal around the holes (73) on a major surface of the board; forming a rectangular array or grid of multiple, circular, conductive, metal contacts (72) which are larger than the lands and positioned so that four contacts define a square that surrounds one or more of the lands; forming a conductor (77) extending in a diagonal direction in relation to the square to one of the contacts (72) between each respective land and one of the surrounding contacts (72) . The process of claim 1, further comprising the step of depositing joining-material (12, 13) on the contacts. The process of claim 2, further comprising the step of connecting to the joining-material, a metal-ball (18) with a melting temperature substantially above the melting temperature of the joining-material. The process of claim 3, further comprising the step of heating to melt the joining-material to reflow connect the balls onto the contacts and then cooling the joining-material to solidify it. A process for making an interconnect assembly comprising the steps of: producing an fiberglass-epoxy (FR-4) board with a multitude of wiring layers (11) ; the process is further characterized by the steps of: forming circular copper lands in a wiring layer on a major surface of the board; drilling holes (73) through the board through the lands; selectively depositing copper after drilling for platting the through holes (73) for heating vias (71) for connecting the lands to other wiring layers; forming a rectangular array or grid of round copper contacts (72) larger than the lands about .7 mm diameter and spaced at about 1.25 mm centers and positioned so that four contacts define a square (76) that surrounds each of the lands; forming a conductor (77) which is narrower than the contacts (72) and narrower than the lands which extending between each of the lands surrounded by contacts (72) in a diagonal direction in relation to the square of surrounding contacts (72) ; depositing solder resist at least partially covering the conductor (77) and the lands and extending between the contacts (72) to prevent solder bridging; depositing a joining solder material (13) containing about 63/37 Sn/Pb solder alloy on each of the contacts (72) in the array on the board; producing multiple green sheets (10) of glass/ceramic particles and an organic binder; forming via holes (14) through the sheets (10) ; screen printing conductive material into the via holes (14) and onto one of the surfaces of the sheets (10) to form a conductive pattern; stacking the sheets (10) together; sintering the stack of sheets (10) in an oven to form a multi-layer ceramic chip carrier with an array of copper contacts (12) on a major surface which are about .7 mm wide, are spaced about 1.25 mm apart, and are arranged approximately mirror image to the array of contacts (72) of the board; forming an array of round contacts on exterior major surface of the carrier; depositing solder resist (134) between the contacts to prevent solder bridging; depositing a joining solder material (136) containing about 63/37 Sn/Pb solder alloy on each of the contacts in the array on the carrier; positioning a ball (18) of about 90/10 Pb/Sn solder alloy and about .9 mm diameter in contact with the joining solder material (136) deposited on each respective contact in the array of the carrier to define a plane of solder balls; reflowing to melt the joining solder material (136) deposited on the contacts of the carrier without melting the solder balls (18) in order to solder the balls (18) to the contacts of the carrier and using the minimal temperature and time required to form reliable mechanical joints in order to minimize diffusion of Pb from the balls (18) into the melted solder (136) ; cooling the carrier to solidify the joining solder (136) ; positioning the ceramic carrier parallel to the circuit board with the solder balls (18) about in contact with the joining solder deposited on the array of contacts on the board (11) so that each solder ball (18) is between a pair of contacts (72) ; heating the substrates while positioned together to a temperature at which the solder deposited on the contacts of both the carrier and board (11) are simultaneously melted and the solder-balls (18) remain solid for moving the solder-balls by surface tension of the melted solder material in directions within the plane (53) of the solder-balls to positions about midway between the centers of the pairs of contacts to produce symmetric connections between the substrates; cooling the substrates below the melting temperature of the solder materials to solidify the solder material. The process of claim 5, in which: each of the contacts on the board include a very thin extension (130) over the solder resist; the solder is deposited on the contacts of the FR-4 board including the extensions by wave soldering; and the holes are formed in the FR-4 board by drilling and formed in the sheets by punching; and the process further comprises the steps of: reflowing the deposited joining solder on the carrier before positioning the solder balls; flattening the joining solder of the carrier before positioning the solder balls; depositing sticky flux (20) on the joining solder of the carrier before positioning the solder balls; reflowing the deposited solder on the board before positioning the carrier with the board; flattening the joining solder of the carrier before positioning the carrier with the board; applying flux for joining the balls to the board before positioning the carrier with the board. The process of one of the claims 3 to 6 wherein the smallest cross sectional area of each joining-material volume having a diameter at least about 2/3 of the diameter of the metal ball. The process of one of the claims 3 to 7, wherin metal columns (165, 171) are used instead of metal balls. A fabricated interconnect structure comprising: a multi-layer substrate (11) having a wiring layer on the surface of the substrate; the interconnect structure further charaterized by: a multitude of metal contacts (72) in a matrix at positions defined by intersections of a grid of a multitude of parallel equally spaced lines in each of two perpendicular directions in a plane of the surface wiring layer; a multitude of conducting vias (71) connecting between one or more other wiring layers of the substrate and the surface wiring layer at about the centers of squares defined by four of the contacts (72) ; a conductor (77) of the surface wiring layer for each respective via (71) , which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via. Information handling apparatus comprising: one or more central processing units connected in a network; random access memory communicating through a bus with each central processor unit; input/output means for communicating with computer peripherals; a multi-layer circuit board (11) in communication with one or more of the central processing units, having a wiring layer on the surface of the circuit board; the information handling apparatus further characterized by : a multitude of metal contacts (72) in a planer matrix pattern at positions defined by intersections of a grid of a multitude of parallel equally spaced lines in each of two perpendicular directions in a plane of the surface wiring layer; a multitude of conducting vias (71) connecting between one or more other wiring layers of the circuit board and the surface wiring layer at about the centers of squares defined by four of the contacts; a conductor (77) of the surface wiring layer for each respective via, which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via; a chip carrier (10) for one or more chips with a planer pattern of multiple, metal contacts on a major surface which is approximately a mirror image of a planer pattern of contacts on the circuit board to provide confronting pairs of contacts for interconnection between the carrier and the board; a metal-ball (18) for each respective pair of such contacts; a volume of a first joining-material (16) for each pair of contacts connected to a respective contact of the chip carrier and a volume of a second joining-material (13) for each pair of contacts connected to a respective contact of the circuit board (11) , with melting temperatures of both the first and second joining-material substantially less than the melting temperature of the metal-balls, with the first and second joining-materials of each pair of contacts soldered to diametrically opposite ends of the respective metal-ball.

Inventors: ACOCELLA JOHN, BANKS DONALD RAY, BENENATI JOSEPH ANGELO, CAULFIELD THOMAS, CORBIN JOHN SAUNDERS JR, HOEBENER KARL GRANT, WATSON DAVID P, ACOCELLA, JOHN, BANKS, DONALD RAY, BENENATI, JOSEPH ANGELO, CAULFIELD, THOMAS, CORBIN, JOHN SAUNDERS, JR., HOEBENER, KARL GRANT, WATSON, DAVID P.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1994
Main classification: B23K1
IPC codes: B23K1, H05K3, H01L21, H01L23