Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device

Abstract: According to a method of manufacturing a semiconductor device of this invention, a first lead frame portion (4) has a bed portion (8) for mounting a semiconductor element (9) and a plurality of inner (2) and outer leads (3). A second lead frame portion (4) has a bed portion (8) for mounting a semiconductor element (9) and a plurality of inner and outer leads (2, 3) as in the first lead frame portion (4) coupled to the second lead frame portion (4) through a coupling portion. The first and second lead frame portions (4, 4) are folded at the coupling portion and superposed each other such that the two semiconductor elements (9, 9) oppose each other. At this time, the plurality of inner and outer leads (2, 3) of the first and second lead frames (4, 4) are alternately and adjacently arranged. Each electrode of the semiconductor elements (9, 9) is connected to a corresponding inner lead (2). The superposed first and second lead frames (4, 4) are sealed with a mold resin (10) while leaving end portions of the plurality of outer leads (3) of the first and second lead frames (4, 4).

Description: The present invention relates to a lead frame and to a method of manufacturing a resin-sealed semiconductor device, which allows easy and correct positioning of semiconductor elements and lead frames. As a conventional semiconductor integrated circuit device which realizes a high-density assembly, for example, a device disclosed in Jpn. UM Appln. KOKAI Publication No. 2-54248, Jpn. Pat. Appln. KOKAI Publication No. 2-105450 or 1-257361 is known. Such a semiconductor device has a structure in which a plurality of lead frames, each prepared by mounting and bonding at least one semiconductor chip thereon, are superposed such that the surfaces on which the semiconductor chips are mounted oppose each other, and the leads of the lead frames are compressed and resin-sealed. However, in the above prior arts, a pair of lead frames to be superposed are positioned at every semiconductor chip. For this reason, the manufacturing process is complicated, and correct positioning is not necessarily uniformly performed for each product. Patent Abstracts of Japan 12 (256), (E-635) [3103] and JP-A-63044750 discloses a lead frame in accordance with the preamble of claim 1. There, a first lead frame carrying a semiconductor chip, and a second lead frame are stacked. The present invention has been made in consideration of the above situations. It is an object of the present invention to provide a lead frame usable in a method of manufacturing a resin-sealed semiconductor device. It is another object of the present invention to provide a method of manufacturing a resin-sealed semiconductor device, which can uniformly perform more correct positioning for each product not only every semiconductor chip but also when a plurality of semiconductor chips are simultaneously superposed. In order to achieve the above objects, according to the present invention, there is provided a lead frame according to claim 1. Further, there is provided a method of manufacturing a resin-sealed semiconductor device in accordance with claim 5. With the above arrangement, according to the method of manufacturing a resin-sealed semiconductor device of the present invention, when the continuous first and second lead frame portions having semiconductor elements mounted on their bed portions are folded at a coupling portion to be superposed, and the two semiconductor elements are opposed each other, easy and correct positioning can be performed for the two semiconductor elements and inner leads and corresponding outer leads. Especially, when a plurality of semiconductor elements are arranged in the longitudinal direction of the first and second lead frames, the lead frames are folded at the coupling portion. At this time, the plurality of semiconductor elements of the first and second lead frames, which are symmetrically placed on both sides of the coupling portion as a center line and to be opposed, and the inner and outer leads to be alternately arranged are correctly positioned at one time. Therefore, according to this resin-sealed semiconductor device, not only when a resin-sealed semiconductor device including a single semiconductor chip is manufactured, but also when a plurality of resin-sealed semiconductor devices are manufactured at one time, the semiconductor elements to be opposed and inner and outer leads to be alternately arranged can be correctly positioned. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view showing a lead frame for mounting a plurality of semiconductor elements according to the present invention; FIG. 2 is an enlarged plan view showing a pair of adjacent lead frame portions of the lead frame shown in FIG. 1; FIG. 3 is a side view showing the lead frame shown in FIG. 2; FIG. 4 is a plan view showing the lead frame having beds formed therein; FIG. 5 is a view for explaining that one of the lead frames having the beds is cut off from the external frame and folded in a direction indicated by an arrow; FIG. 6 is a plan view showing the arrangement of inner and outer leads when the adjacent lead frames are superposed; FIG. 7 is a side view showing a state in which the adjacent lead frames each having a semiconductor element mounted are superposed; FIG. 8 is a plan view showing a state in which the lead frames shown in FIG. 7 are molded with a resin; FIG. 9 is a plan view showing a state in which tiebar cutting is performed in the resin-molded lead frames shown in FIG. 8; FIG. 10 is a plan view showing a semiconductor device completed by performing cutting and lead forming for the lead frame shown in FIG. 9; FIG. 11 is a side sectional view showing the semiconductor device shown in FIG. 10; FIG. 12 is a schematic view showing the internal arrangement of the semiconductor device of the present invention; FIG. 13 is an enlarged perspective view showing end portions of the outer leads of the semiconductor device of the present invention; FIG. 14 is a plan view showing a lead frame according to another embodiment of the present invention; FIG. 15 is a plan view showing a lead frame according to still another embodiment of the present invention; and FIG. 16 is a plan view showing a lead frame according to still another embodiment of the present invention. An embodiment of the present invention will be described below with reference to the accompanying drawings. As shown in FIG. 1, a unit lead frame is a lead frame portion 4 comprising a portion 1 serving as a bed portion for mounting a semiconductor element, inner leads 2 radially connected to the portion 1, and outer leads 3. A plurality of unit lead frames are coupled to each other by an external frame 5 and arranged at substantially equal intervals to form a lead frame 6. FIG. 2 is an enlarged view showing frames for two semiconductor elements, which are extracted from the lead frame 6 shown in FIG. 1. The frame portions 4 are coupled to each other by the external frame 5. FIG. 3 is a view showing the lead frame 6 in FIG. 2 when viewed from its side surface. Press-molding is performed at a portion serving as a bed portion, and a recessed portion 7 is formed in the frame portion 4 at a position where the semiconductor element are mounted. As shown in FIG. 4, a bed is formed and one end portion of each inner lead 2 is cut off to form a bed portion 8. A semiconductor element 9 (to be described later in FIG. 12) is mounted and bonded on the bed portion 8. As shown in FIG. 5, except for the coupling portion between the two unit lead frame portions, the coupling portions between the external frame 5 and one of the unit lead frames 4 are cut off. The external frame portion 5 for coupling the two unit lead frame portions each having the semiconductor element 9 mounted is folded and superposed. FIG. 6 shows a state in which the inner leads and the outer leads are alternately arranged when the two unit lead frame portions 4 are superposed. The outer leads 3 of one unit lead frame portion 4 and the outer leads 3 of the other unit lead frame portion 4 are staggered. FIG. 7 is a side view showing a state in which the lead frame portions each having the semiconductor element 9 mounted on the bed portion are superposed. The superposed lead frame portions are molded with a resin 10, as shown in FIG. 8, while leaving the outer leads 3. As shown in FIG. 9, tie bar cutting is then performed. As shown in FIGS. 10 and 11, cutting of the coupling portions, lead forming, cutting of the distal ends of the outer leads, and cutting of suspension pins are performed, thereby completing a resin-sealed semiconductor device having a pair of semiconductor elements. FIG. 12 shows an enlarged view of the side view in FIG. 11. As described above, the lead frame portions are folded, the semiconductor elements 9 mounted on the bed portions 8 respectively oppose each other, and electrodes 11 of the semiconductor elements 9 are connected to the inner leads 2 through bonding wires 12, respectively. In addition to the bonding wire 12, a means for electrically connecting may be used. The outer leads 3 connected to the inner leads 2 and led from the mold resin 10 are staggered, as shown in FIG. 13. The end portions of the leads are linearly arranged by cutting the distal ends of the outer leads, as shown in FIG. 10. In FIGS. 2 and 13, an example of superposing a pair of unit lead frames 4 is explained for the sake of descriptive convenience. However, as shown in FIG. 14, when a plurality of unit lead frame portions 4 are coupled to each other at coupling portions and held by a common external frame, a plurality of pairs of unit lead frame portions 4 can be superposed at one time by folding a lead frame 6 at its center line C. In this case, when the lead frame 6 having first and second unit lead frame portions 4A and 4B alternately and adjacently arranged in the longitudinal direction of a frame member is folded at the center line C, the first and second unit lead frame portions 4A, ..., 4B and 4B alternately arranged in one direction from the center oppose the second and first unit lead frame portions 4B, 4A, ... and 4A alternately arranged in the other direction from the center. As a result, in a pair of opposed lead frame portions, a plurality of inner leads and outer leads of the second lead frame portion 4B are alternately arranged between a plurality of inner leads and outer leads of the first lead frame portion 4A. FIG. 15 shows an embodiment in which a unit constituted by two first lead frame portions 4A, 4A and a unit constituted by two second lead frame portions 4B, 4B are alternately arranged in the longitudinal direction of a lead frame 6. When the lead frame 6 is folded at the center line C, the unit constituted by alternately arranging the two first lead frame portions 4A, 4A and the two second lead frame portions 4B, 4B in one direction from the center opposes the unit constituted by alternately arranging the two second lead frame portions 4B, 4B and the two first frame portions 4A, 4A in the other direction from the center. The number of lead frame portions 4A and 4B constituting a unit is not limited to two. A unit may be constituted by three or more lead frame portions. FIG. 16 shows an embodiment in which two or more first lead frame portions 4A are coupled to each other at coupling portions and adjacently arranged in one direction from the center of a lead frame 6, and two or more second lead frame portions 4B are arranged in the other direction from the center at positions symmetrically with the first lead frame portions 4A. Also in this embodiment, when the lead frame 6 is folded at the center, a plurality of first lead frame portions 4A, 4A ... and 4A and a plurality of second lead frame portions 4B, 4B ... and 4B placed symmetrically with the first lead frame portions are superposed. In the above embodiments shown in FIGS. 14 to 16, a semiconductor element is mounted on the bed portion of each lead frame portion. When the lead frame is folded at a center line C, correct positioning can be performed and a plurality of semiconductor chips each having a pair of semiconductor elements opposed each other can be continuously obtained. As in the description of FIG. 8, the lead frame portions 4A and 4B having semiconductor elements mounted are superposed and molded with a resin while leaving the outer leads, thereby obtaining a resin-sealed semiconductor device.

Claims: A lead frame (6) comprising: first and second lead frame portions (4) arranged along a longitudinal direction of a lead frame member (5), said second lead frame portion being connected to said first lead frame portion through a coupling portion of said lead frame member (5), said first lead frame portion having a first bed portion (8) adapted for mounting a semiconductor element thereon and a first lead group comprising a plurality of first inner leads (2) extending radially from at least one side of said first bed portion (8) at substantially equal intervals and a plurality of first outer leads (3) respectively connected to said first inner leads (2); and said second lead frame portion having a second bed portion (8) adapted for mounting a semiconductor element thereon and a second lead group comprising a plurality of second inner leads (2) extending radially from at least one side of said first bed portion (8) at substantially equal intervals and a plurality of second outer leads (3) respectively connected to said second inner leads; characterized in that said first and second lead groups and said first and second bed portions are arranged such that when said lead frame (6) is folded at said coupling portion, said second bed portion is superposed on said first bed portion so as to oppose each other, and respective ones of said plurality of inner (2) and outer (3) leads of said first and second lead groups are arranged alternately. A lead frame according to claim 1, characterized in that at least one additional first or second lead frame portion is coupled to each of said first and second lead frame portions along said longitudinal direction of said lead frame member (5), such that when said lead frame is folded at said coupling portion each additional first lead frame portion is opposed by an additional second lead frame portion. A lead frame according to claim 2, characterized in that said additional lead frame portions are provided such that the first lead frame portions and the same number of second lead frame portions are alternately and adjacently arranged in the longitudinal direction of said lead frame member. A lead frame according to claim 2, characterized in that said additional lead frame portions are provided such that at least two first lead frame portions are adjacently arranged in the longitudinal direction from said coupling portion, and at least two second lead frame portions are adjacently arranged in the opposing direction to the longitudinal direction from said coupling portion at positions symmetrical with the first lead frame portions. A method of manufacturing a resin-sealed semiconductor device comprising the steps of: mounting first and second semiconductor elements (9) on said first and second bed portions (8), respectively, of a lead frame (6) according to claim 1, and electrically connecting electrodes of said first and second semiconductor elements (9) to corresponding ones of the plurality of first and second inner leads (2), respectively, folding said first and second lead frame portions (4) at said coupling portion to oppose said first and second semiconductor elements (9) and to superpose said first and second lead frame portions (4) such that said inner leads (2) and said outer leads (3) of said first and second lead groups are alternately arranged, and sealing said first and second lead frame portions (4) and said first and second semiconductor elements (9) with a mould resin (10), while leaving end portions of said outer leads (3) of said first and second lead frame portions (4) uncovered by said resin.

Inventors: HOSOKAWA RYUJI, YANAGIDA SATORU, HOSOKAWA, RYUJI, YANAGIDA, SATORU, HOSOKAWA, RYUJI, C/O INTELLECTUAL PROPERTY DIV., YANAGIDA, SATORU, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L23
IPC codes: H01L25, H01L23