A method and apparatus for error-control coding in a digital data communications system

Abstract: In order to ensure that a predetermined bit(s) of a bit sequence to be transmitted is correctly received by a receiver, the predetermined bit is extracted from the bit sequence. The extracted bit is encoded and then combined with a bit sequence which has not been extracted. The combined bit sequence is convolutionally encoded and then transmitted to the receiver. The bit sequence transmitted undergoes maximum-likelihood decoding using viterbi algorithm, wherein the information of the predetermined bit encoding is used to decode the predetermined bit. Subsequently, the encoded predetermined bit portion is extracted and subjected to block decoding.

Description: The present invention relates generally to a method and apparatus for implementing error-control coding in a digital data communications system, and more specifically to such a method and apparatus for correcting and/or detecting errors induced during data transmission. In order to correct and/or detect channel bit errors induced during digital data transmission, it is well known in the art to utilize error-control coding techniques. These techniques are disclosed in a book entitled "Essential of Error-coding Techniques' edited by Hideki IMAI and published 1990 by Academic Press, Inc., San Diego, California 92101, U.S.A., and a book entitled "Error Control Coding: Fundamentals and Applications' by Shu tin, et al., published 1983 by Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632, U.S.A., merely by way of example. Redundant bits are added to each binary code word to be transmitted in order to provide the code with the capability of combating the channel noises. A Viterbi algorithm is able to exhibit error correcting capability almost equally over the entire bits of a code word. However, it is sometimes required to transmit a special bit(s) of each code word with high reliability as compared with the remaining bits of the code word. In order to realize such a requirement, according to prior art, it has been inevitably required that a plurality of pairs of an encoder and decoder, having different error-control capability or functions, be provided. However, the above mentioned known techniques suffer from the drawback that an overall system is rendered large and complex. Further, the freedom of the system design is reduced. In an article by G. D'Aria, et al. entitled "Simulation and Performance of the Pan-European Land Mobile Radio System" in Vol. 41, No. 2, May 1992 of the IEEE Transactions on Vehicular Technology, New York, U.S.A., on pages 177 to 189, there is described the performance of the compact-spectrum constant-envelope modulation chosen by ETSI/GSM, together with concatenated block and convolutional coding, Viterbi adaptive equalization and soft-decision Viterbi decoding to cope with the severe time-and frequency-selective distortions caused by propagation phenomena, properly modelled for computer simulation. The specification of UK patent application number 2,238,933, which was published on June 12 1991, describes a low-overhead method of protecting multi-pulse speech coders from the effects of severe random or fading bit pattern errors which combines a standard error correcting code (convolutional rate ½ coding and Viterbi trellis decoding) for protection against random errors with cyclic redundancy code (CRC) error detection for fading errors. Protection, which is applied only to the perceptually significant bits in a transmitted frame, takes place within the speech coder. A specification which was published on December 15 1998 with International Patent Publication No. W088/9967 described a method of error correction in digitally encoded speech in which sub-band coding was preferably applied to an input signal, sample information, and side information. An error detection code was applied to at least a portion of the side information, and an error correction code was applied over the side information and the error detection code. A second error detection code was applied to the error correction code and the information signals and the error detection and correction codes were multiplexed. Features of arrangements to be described below, by way of example, in illustration of the present invention are that in error-control coding important bit(s) is/are selected from a bit sequence and then subjected to block encoding for correctly transmitting the same, and that apparatus for such error-control coding has means for selecting important bit(s) from a bit sequence and then subjecting them to block encoding for correct transmission. In one arrangement to be described below, by way of example, in illustration of the invention, in order to ensure that a predetermined bit or bits of a bit sequence to be transmitted are correctly received by a receiver, the predetermined bit is first extracted from the bit sequence. The extracted bit is then encoded and combined with a bit sequence which has not been extracted. The combined bit sequence is convolutionally encoded and then transmitted to the receiver. The transmitted bit sequence undergoes maximum-likelihood decoding using a Viterbi algorithm, wherein the information of the predetermined bit encoding is used to decode the predetermined bit. Subsequently, the encoded predetermined bit portion is extracted and subjected to block decoding. The following description and drawings disclose, by means of examples, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby. In the drawings:- Fig. 1 is a block diagram schematically showing a first arrangement illustrative of the present invention, Fig. 2A is a sketch schematically showing waveforms of an analog signal to be encoded, Fig. 2B is a diagram schematically showing burst digital signals to be transmitted, Fig. 3 is a block diagram schematically showing an arrangement of a block shown in Fig. 1, Fig. 4 is a known encoder state diagram by means of which the operations of the first arrangement are discussed, Figs. 5-7 each show a trellis diagram by means which the operations of the first arrangement are discussed, Fig. 8 is a block diagram schematically showing a transmitter of a second arrangement illustrative of the invention, Fig. 9 is a block diagram schematically showing a receiver of the second arrangement, Fig. 10 is a block diagram schematically showing a transmitter of yet a third arrangement illustrative of the invention, and Fig. 11 is a block diagram schematically showing a receiver of the third arrangement. The arrangement shown in Fig. 1 generally includes a transmitter 10 which is interconnected to a receiver 12 via a transmission channel 14. The transmitter 10 includes a message source 16, a source encoder 18, a bit selector 20, a block encoder 22, a bit combiner (or bit merger) 24, and a convolutional encoder 26, all of which are coupled as shown. On the other hand, the receiver 12 includes a maximum-likelihood decoder 28 which operates under a Viterbi algorithm, a bit selector 304 a block decoder 32, a bit combiner 34, and a source decoder 36, all of which are coupled as illustrated. Merely for the sake of a better understanding of the first arrangement, it is assumed that the message source 16 takes the form of an analog speech signal source. The wave form of the speech signal (denoted by "S1"), obtained from the source 16, is schematically shown in Fig. 2A. The speech signal S1 undergoes digital signal processing at the source encoder 18. That is, the speech signal is initially digitized at a time interval of 40 ms. (for example) which is called a frame. Subsequently, the digitized speech signal is compressed and then applied to the bit selector 20 as a bit sequence 52 in a burst mode, as best seen from Fig. 2B. If the bit rate of digitization is 4K bits/sec., it is readily appreciated that each frame of 40 ms. contains 160 bits. It is further assumed that the first bit of the burst signal is a mode bit indicating whether the corresponding frame is a voice frame or a silence frame. This mode bit appearing at the beginning of each frame is very important and hence has to be correctly transmitted to the receiver 12. The second to the last bit of each frame is not so important as compared with the mode bit. The bit selector 20 selects the above mentioned mode bit from the incoming frame data. This bit selection is carried out under the control of a bit select signal applied to the selector 20 from a central processor unit (CPU) (not shown) which supervises the overall operation of the transmitter 10. The other bits which have not been selected by the bit selector 20 are directly supplied to the bit combiner 24. The mode bit thus selected is fed to the block encoder 22 which, in this particular arrangement, outputs "01" and "10" when the applied mode bit assumes "0" and "1", respectively. The bit combiner 24 combines or merges the two outputs of the block encoder 22 and the bit selector 20 in this order. A bit sequence (depicted by "A") from the bit combiner 24 is applied to the convolutional encoder 26. In the foregoing, it is assumed that a given frame of the bit sequence S2 output from the source encoder 18 is represented by S2 = (0 0 0 1 . . . . ) As mentioned above, if the mode bit is "0" then the output of the block encoder 22 assumes "01". Thus, the combiner 24 issues the output A which is given by A = (0 1 0 0 1 . . . . ) Reference is made to Fig. 3 wherein the arrangement of the convolutional encoder 26 is shown in block diagram form. The encoder 26 is of a conventional type and includes three delay lines or shift registers (denoted by D n , D n-1 and D n-2 ), two modulo-2 adders 40a-40b, and a parallel/serial (P/S) converter 42, in this particular embodiment. Thus, the constraint length (K) of the encoder 26 is 3 (three) while the code rate (R) thereof is ½. The arrangement illustrated in Fig. 3 is well known in the art. Fig. 4 is a state diagram of the encoder 26. In Fig. 4, two consecutive bits within each of ovals indicates the bits held in the last two delay lines D n-2 and D n-1 , and indicates an encoder state. The encoder states (00), (01), (10) and (11) are connected or looped by solid and broken arrow lines. If a bit "l' is applied to the encoder 26, the encoder state is shifted to the other state or returned to the same state along the solid arrow. On the other hand, if a bit "0" is applied to the encoder 26 then the encoder state is shifted to the other state or returned to the same state along the broken arrow. The outputs of the convolutional encoder 26 are represented along the corresponding arrows such as (00), (01), (10) and (11). The encoder 26 is set to the state (00) before a burst type bit sequence is newly applied. Therefore, if the mode bit (viz., first bit) assuming "0" is applied to the encoder 26, the encoder state (00) remains unchanged. In this case, the output of the encoder 26 is (00). Following this, if the second bit assuming "1" is applied to the encoder 26, the encoder 26 takes the state (01) and outputs a two bits sequence (11). Thereafter, similar operations continue. Thus, if the bit sequence A of (0 1 0 0 1 . . .) is applied to the convolutional encoder 26 as mentioned in expression (2), the bit sequence C obtained from the encoder 26 and then sent over the channel 14 is given by C = (00 11 01 11 11 . . . .) The bit sequence C is transmitted over the channel 14 and applied to the receiver 12 as a bit sequence CC. It is assumed that the bit sequence C is subjected to bit errors during transmission and that the bit sequence CC is represented by CC = (01 11 01 01 11 . . . ) The operation of the maximum-likelihood decoder 28 of the receiver 12 will be discussed with reference to the trellis diagrams shown in Figs. 5-7. The above mentioned bit sequences A, C and CC, given by the expressions (2)-(4) are shown at the top portions of each of Figs. 5-7. It is well known that the trellis diagram represents the encoder states (see Fig. 4) along a time axis. It should be noted in Figs. 5-7 that numerals above the encoder states represent respectively "decimal numbers" indicating path metrics. Reference is made to Fig. 5. The decoder 28 is initialized such that the path metric of the encoder state (00) is set to 0 while each of the remaining path metrics of the other states (01), (10) and (11) is set to a sufficiently large number such as 10(decimal) in this particular embodiment. These path metrics are illustrated at the first time point (t=0). The decoder 28 initially decodes the first two bits (viz., encoded mode bit) using the previously known block code information (01 and 10). This information has been stored in a suitable memory in the receiver 12 and is applied to the decoder 28. The first bit sequences have been block encoded at the encoder 22, and thus it is appreciated that survivor paths at t=1 and t=2 are represented by two bold solid lines and two bold broken lines as illustrated. A bit sequence of the survivor path extending to the state (00) at t=2 is (00), and hence, this path is unable to be finally selected. Further, a bit sequence of the survivor path extending to the state (01) at t=2 is (11). Therefore, this path is expected to finally be selected. On the other hand, the survivor path extending to the state (10) at t=2 can be expected to be chosen for determining the decoded sequence, while the survivor path extending to the state (11) at t=2 can not be expected to be used to determine the decoded sequence. Therefore, in order to determine the following survivor paths, path metrics at the states (00) and (11), both at t=2, are set to a sufficiently large number, such as 10 (decimal) in this case, as shown in Fig. 6. This is to exclude the survivor paths which can not eventually be used for estimating the incoming bit sequence. Subsequently, conventional decoding, according to a Viterbi algorithm, is implemented which is well known in the art and thus will not be discussed for the sake of brevity. Survivor paths determined up to t=5 are illustrated by bold solid and broken lines in Fig. 7. The decoded bit sequence from the maximum-likelihood decoder 28 is then applied to the bit selector 30. This selector 30 implements the reverse operation of the counterpart thereof 20 in response to a bit select signal which has previously been stored in the receiver 12. The first two bits of the frame are applied to the block decoder 32 while the remaining bits are directly applied to the bit combiner 34. The bit selector 30 decodes the first two bits "0" or "1" and then applies the decoded bit to the bit combiner 34. The bit sequence aligned at the bit combiner 34 is applied to the source decoder 36 which produces an estimated message. In the above first arrangement, the mode information is a single bit. However, it is possible to set the mode information to two or more than two bits. Further, the bit combiner 24 is arranged to insert the output of the block encoder 22 into a given position of the bit stream applied thereto from the bit selector 20. Reference is now made to Figs. 8 and 9, wherein a second arrangement illustrative of the present invention is schematically shown in a block diagram. The second arrangement is an error-control coding apparatus which includes both error- correcting and error-detecting functions. Figs. 8 and 9 show respectively a transmitter and receiver of the second arrangement. The transmitter shown in Fig. 8 further includes a switch 60 and two error-detecting encoders 62a and 62b as compared with the counterpart of the first arrangement. Accordingly, the blocks of Fig. 8, which have been referred to in the first arrangement, will be described only if they are directly relevant to the second arrangement. The mode bit obtained from the bit selector 20 is applied to the switch 60 as a switch control signal. The remaining bits from the bit selector 20 is applied to the switch 60. If the mode bit assumes a logic "0", the switch 60 allows the incoming bit sequence to be applied to the error-detecting encoder 62a. Contrarily, if the mode bit assumes a logic "1" then the switch 60 applies the incoming bit sequence to the other encoder 62b. As is known, an error-detecting encoder is to add redundant bits to a bit sequence (viz., detection bits) applied thereto for the purpose of error detection. In the second arrangement, the encoders 62a and 62b add the same length of redundant bits to the bit sequences applied thereto. However, the two encoder 62a and 62b produce or arrange different redundant bits with each other. This is very preferable in the case in which significant bits are different depending on a logic level of the mode bit (viz., whether the frame data is a voice mode or not in this particular arrangement). The receiver shown in Fig. 9 includes a switch 64 and two error-detecting decoders 64a and 64b in addition to the receiver 12 of the first arrangement. Accordingly, the blocks of Fig. 9 which have been referred to in the first arrangement, will be described only if they are directly relevant to the second arrangement. The decoded mode bit obtained from the block decoder 32 is applied to the switch 64 as a switch control signal. The bit sequence except for the mode bit output from the bit selector 30, is applied to the switch 64. If the decoded mode bit (viz., switch control signal) assumes a logic "0", the switch 64 allows the incoming bit sequence to be applied to the error-detecting decoder 64a. Contrarily, if the decoded mode bit assumes a logic "1", the switch 64 applies the incoming bit sequence to the other decoder 64b. Each of the error detecting decoders 64a and 64b outputs an error detect bit indicating whether or not the received bit sequence includes an error. Further, the decoders 64a and 64b apply respectively the decoded bit sequences to the bit combiner 34. The following operations are essentially the same as those mentioned in connection with the first arrangement. Another feature of the second arrangement is that, if the mode bit is erroneously transmitted, each of the decoders 64a and 64b issues the error detect bit which indicates the presence of a transmission error. This is very advantageous in that the mode bit is the nature of being correctly transmitted as mentioned above. Reference is made to Figs. 10 and 11, wherein a third arrangement which illustrates the present invention is schematically shown in block diagram. The third arrangement is an error-control coding apparatus which includes both error-correcting and error-detecting functions. Figs. 10 and 11 show respectively a transmitter and receiver of the third embodiment. The transmitter shown in Fig. 10 further includes a bit selector 70 and an error-detecting encoder 72 as compared with the counterpart 10 of the first arrangement. Accordingly, the blocks of Fig. 10 which have been referred to in the first arrangement, will be described only if they are directly relevant to the third arrangement. The mode bit obtained from the bit selector 20 is applied to the bit selector 70 as a bit select signal. The remaining bits of a frame, output from the bit selector 20, are applied to the bit selector 70. The mode bit applied to the bit selector 70 determines which portion of the bit sequence applied thereto should be transferred to the error-detecting encoder 72. The number of consecutive bits selected, depending on the logic level of the mode bit, is usually different from that selected in response to the other logic level of the mode bit. This is very advantageous in the case in which significant bits are different in position depending on the logic levels of the mode bit (viz., whether the frame data is in a voice mode or not in this particular arrangement). The bit combiner 24 combines the outputs of the blocks 22, 70 and 72. Fig. 11 shows a receiver of the third arrangement. The operation of this arrangement is readily appreciated from the foregoing and thus, the description thereof will be omitted for brevity. It will be understood that the above disclosure is representative of only three possible arrangements, by way of example, and that variations and modifications, as well as other arrangements, may be conceived within the scope of the protection sought by the appended claims.

Claims: An apparatus for error-control coding, including: a selector (20) for selecting at least one bit from a bit sequence (S2) applied thereto, the at least one bit being selected to be transmitted with a higher reliability than the remaining bits of the bit sequence, and the at least one bit occupying any position within the bit sequence, a first encoder (22) for block encoding the at least one bit applied thereto from the selector, thereby forming a valid error-control sequence, the valid error- control sequence being adapted to become an invalid error-control sequence according to later transmission errors, a combiner (24) for combining the output of the first encoder and the bits in the bit sequence which have not been selected by the selector, a second encoder (26) for implementing convolutional encoding to the bit sequence output from the combiner, a first decoder (28) for implementing maximum-likelihood decoding to the bit sequence transmitted, and a second decoder (32) for block decoding the block encoded bit data. An apparatus for error-control coding, which includes a data transmitter (10) and a data receiver (12) interconnected via a transmission channel (14), the data transmitter including a first bit selector (20) for selecting at least one predetermined bit from a bit sequence (S2) applied thereto, the first bit selector (20) outputting the at least one predetermined bit and a first bit sequence which does not include the at least one predetermined bit, a first encoder (22), coupled to the first bit selector (20) for encoding the at least one predetermined bit and outputting a second bit sequence which corresponds to the at least one predetermined bit which has been encoded by the first encoder (22), first and second error detecting encoders (62a, 62b) which are connected in parallel with each other, a first switching means (60) coupled to receive the first bit sequence and the at least one predetermined bit, the first switching means (60) selectively applying the first bit sequence to one of the first and second error detecting encoders (62a, 62b) depending on the at least one predetermined bit, a first bit combiner (24) coupled to combine the second bit sequence and one of outputs of the first and second error detecting encoders (62a, 62b), the first bit combiner (24) outputting a combined bit sequence (A), and a second encoder (26) for convolutionally encoding the combined bit sequence into a third bit sequence which is transmitted to the data receiver (12) via the transmission channel (14). An apparatus as claimed in claim 2, wherein the data receiver includes a first decoder (28) for decoding the third bit sequence, applied thereto over the transmission channel, using a Viterbi algorithm, a second bit selector (30), coupled to the first decoder, for selecting a fourth bit sequence from an output of the first decoder, the fourth bit sequence corresponding to the second bit sequence, the second bit selector (30) outputting the fourth bit sequence and a fifth bit sequence which does not include the fourth bit sequence, a second decoder (32) coupled to decode the fourth bit sequence, the second decoder (32) outputting at least one bit which corresponds to the at least one predetermined bit, first and second error detecting decoders (64a, 64b) which are connected in parallel with each other, a second switching means (64) coupled to receive the fifth bit sequence and the at least one bit, the second switching means (64) selectively applying the fifth bit sequence to one of the first and second error detecting decoders (64a, 64b) depending on the at least one bit, and a second bit combiner (34) coupled to combine the at least one bit and an output of one of the first and second error detecting decoders (64a, 64b). An apparatus for error-control coding, which includes a data transmitter (10) and a data receiver (12) interconnected via a transmission channel (14), the data transmitter including, a first bit selector (20) for selecting at least one predetermined bit from a bit sequence (S2) applied thereto, the first bit selector (20) outputting the at least one predetermined bit and a first bit sequence which does not include the at least one predetermined bit, a first encoder (22), coupled to the first bit selector (20), for encoding the at least one predetermined bit and outputting a second bit sequence which corresponds to the at least one predetermined bit which has been encoded by the first encoder (22), a second bit selector (70) coupled to receive the first bit sequence and the at least one predetermined bit, the second bit selector (70) selecting a third bit sequence of a predetermined length from the first bit sequence depending on the at least one predetermined bit, the second bit selector (70) outputting a fourth bit sequence which does not include the third bit sequence, an error detecting encoder (72) which receives the third bit sequence and adds redundant bits thereto, the error detecting encoder (72) outputting a fifth bit sequence which includes the third bit sequence and the redundant bits, a first bit combiner (24) coupled to combine the second, fourth and fifth bit sequences, the first bit combiner (24) outputting a combined bit sequence, and a second encoder (26) for convolutionally encoding the combined bit sequence into a sixth bit sequence which is transmitted to the data receiver (12) via the transmission channel (14). An apparatus as claimed in claim 4, wherein the data receiver includes a first decoder (28) for decoding the sixth bit sequence applied thereto over the transmission channel (14), using a Viterbi algorithm, a third bit selector (30), coupled to the first decoder (28), for selecting a seventh bit sequence from an output of the first decoder (28), the seventh bit sequence corresponding to the second bit sequence, the third bit selector (30) outputting the seventh bit sequence and an eighth bit sequence which does not include the seventh bit sequence, a second decoder (32) coupled to decode the seventh bit sequence, the second decoder (32) outputting at least one bit which corresponds to the at least one predetermined bit, a fourth bit selector (74) coupled to receive the eighth bit sequence from the third bit selector (30) and receive the at least one bit from the second decoder (32), the fourth bit selector (74) selecting ninth and tenth bit sequences which respectively correspond to the fourth and fifth bit sequences, an error detecting decoder (76) arranged to decode the tenth bit sequence, and a second bit combiner (34) coupled to combine the at least one bit from the second decoder (32), the ninth bit sequence and an output of the error detecting encoder (76). A method for error-control including the steps of selecting at least one bit from an initial bit sequence (S2), the at least one bit occupying any position within the initial bit sequence encoding the at least one bit thereby forming an encoded bit, combining the encoded bit with bits in the initial bit sequence which are not selected thereby forming a second bit sequence (A), convolutionally encoding the second bit sequence thereby forming a third bit sequence (C), decoding the third bit sequence using maximum-likelihood decoding to form a fourth bit sequence, and decoding the fourth bit sequence. A method as claimed in claim 6, wherein the step of selecting includes a mode bit from the initial bit sequence. A method as claimed in claim 6, wherein the step of encoding encodes a logic "0" as "01" and encodes a logic '1' as "10".

Inventors: IKEKAWA MASAO, IKEKAWA, MASAO, IKEKAWA, MASAO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H04L1
IPC codes: H04L1, H03M13