Preamplifier circuit arrangements

Abstract: A preamplifier circuit arrangement for a magnetic or magneto resistive transducer, such as a record/replay head, in which a cascode preamplifier stage, and a stage providing a floating reference voltage for a following amplifier, are linked by an emitter coupled pair of transistors, one in each stage, such that the d.c. currents in the two stages flow in common through the transducer.

Description: The present invention relates to preamplifier circuit arrangements, and in particular to preamplifier circuit arrangements for use with magnetic or magneto resistive transducer or record/replay heads. Such magnetic or magneto-resistive heads commonly require a relatively high bias current in order to develop a usable output signal, and this requirement is in conflict with the desirability of keeping down the current levels and hence power dissipation in the preamplifier circuit arrangements to which the heads are connected. A prior art magnetic record reproducing system preamplifier is known from US-A-4 159 489. EP-A-0 283 593 discloses a Videoamplifier having a similar structure to that of the preamplifier shown in the accompanying drawing. According to the present invention a preamplifier circuit arrangement for a magnetic or magneto resistive transducer or record/replay head comprises an emitter-coupled pair of transistors having respective constant current sources in their collector circuits and bias circuit means to apply d.c. biases to their respective bases, means to connect said transducer or record/replay head between said coupled emitters and a point of ground potential, and means to connect one of said pair of transistors in common base mode to alternating signal currents flowing in said transducer or record/replay head, the arrangement being such that alternating output signals may be derived from the collector circuit of said one of said pair of transistors. Preferably the collector circuits of said emitter-coupled pair of transistors are connected to respective inputs of an amplifier providing differential output signals. A preamplifier circuit arrangement in accordance with the present invention will now be described by way of example with reference to the accompanying drawing, which shows the arrangement diagrammatically. Referring to the drawing any one of four magneto resistive heads 1 to 4 may be selected to receive a constant bias current I1 + I2 from sources 5 and 6 in dependence upon which of four transistors T5 to T8 is biassed into conduction by a head select circuit 7. The bias current sources 5 and 6 are connected in the collector circuits of an emitter coupled pair of transistors T3 and T4, the d.c. bias conditions of which are fixed by a biassing circuit comprising transistors T1 and T2 and resistors R1 to R4. By means of a capacitor C connected between the base of transistor T4 and ground transistor T4 is arranged to operate in common base mode with respect to any alternating currents which may flow in the selected magneto resistive head 1 to 4, the resultant alternating output voltages developed across resistor R2 being applied to one input of a differential output amplifier 8, the other input of which is connected for reference to the collector of the transistor T1. The circuit comprising the current source 6 and the transistors T2 and T4 applies amplified signals from the selected head 1 to 4 to one input of the amplifier 8, while the circuit comprising the current source 5 and the transistors T1 and T3 establishes a reference voltage for the other input of the amplifier 8. Since the currents I1 and I2 from the sources 5 and 6 are passed in common through the selected head 1 to 4, the circuit arrangement requires typically half the current of prior arrangements. The common ground connection enables head selection to be implemented efficiently, saving components and power, and requires fewer pins on the circuit package. Each of the heads 1 to 4 may have a resistance of the order of ten ohms, and the sum of the currents I1 and I2 may be of the order of fifteen to twentyfive milliamps. The resistors R1 and R2 may each be, say, eight hundred ohms while the resistors R3 and R4 may each be, say, one thousand six hundred ohms.

Claims: A preamplifier circuit arrangement for a magnetic or magneto resistive transducer or record/replay head (1,..,4) comprising an emitter-coupled pair of transistors (T3,T4) having respective constant current sources (5,6) in their collector circuits and bias circuit means (T1,R1,R3; T2,R2,R4) to apply d.c. biases to their respective bases, means to connect said transducer or record-replay head (1,...,4) between said coupled emitters and a point of ground potential, and means (C) to connect one (T4) of said pair of transistors in common base mode with respect to alternating signal currents flowing in said transducer or record/replay head, the arrangment being such that alternating output signals may be derived from the collector circuit or said one of said pair of transistors. A preamplifier circuit arrangement for any selected one of a plurality of magnetic or magneto resistive transducers or record/replay heads (1-4) comprising an emitter-coupled pair of transistors (T3,T4) having respective constant current sources (5,6) in their collector circuits and bias circuit means (T1,R1,R3; T2,R2,R4) to apply d.c. biases to their respective bases, respective switching means (T5-T8,7) to selectively connect any one of said transducers or record/display heads between said coupled emitters and a point of ground potential, and means (C) to connect one (T4) of said pair of transistors in common base mode with respect to alternating signal currents flowing in said one of said transducers or record/replay heads, the arrangement being such that alternating output signals may be derived from the collector circuit of said one of said pair of transistors. A preamplifier circuit in accordance with Claim 2 wherein said switching means comprises a respective switching transistor (T5,...,T8) connected between said coupled emitters and each of said transducers or record/replay heads (1,..4). A preamplifier circuit in accordance with Claim 1, Claim 2 or Claim 3 wherein the collector circuits of said emitter-coupled pair of transistors (T3,T4) are coupled to respective inputs of an amplifier (8) providing differential output signals.

Inventors: DAVIES RICHARD, DAVIES, RICHARD
Applicants: PLESSEY SEMICONDUCTORS LTD, PLESSEY SEMICONDUCTORS LIMITED
Application year: 1994
Main classification: H03F3
IPC codes: H03F3, G11B19, H03F1, G11B33, G11B5