Method and apparatus for displaying two video pictures simultaneously

Abstract: A method and an apparatus for simultaneously displaying two independent video signals are described. The apparatus comprises vedlo signal input terminals (2, 6) for receiving first and second video signals in PAL system having the field frequency of 50 Hz, Y/C processors (7, 8) connected to the video signal input terminals (2, 6), A/D converters (16, 24) connected to the Y/C processors two port field memories (17, 22) having a random block addressing mode for storing the digital Y/U/V signals from the A/D converters, a D/A converter (19) connected to an output of the field memories (17, 22) and deriving analog Y/U/V signals which are converted to R/G/B signals and supplied to a display (10), a write and read control signal generator (14; 20, 21) for generating first and second write control signals so that the first and second digital Y/U/V signals are written into the first and second field memories (17, 22) at a first predetermined frequency in sychronism with the synchronizing signals of the first and second video signals, respectively, and for generating frist and second read control signals so that the first and second digital Y/U/V signals are alternately linewise read-out from the first and second field memories (17, 22) at four times the first predetermined frequency in sychronism with a master sychronizing signal of either the first or second video signals and which are displayed each in an aspect ratio of 4:3 or 3:3 on the screen having a wide aspect ratio of 16:9 in a 100 Hz flickerless mode.

Description: The invention relates to a television receiver displaying two pictures on its screen simultaneously. It is well known to display two pictures, one as the main picture and the other as a sub-picture within the main picture, simultaneously on the screen of a television receiver by using a memory for the sub-picture. This feature is called as "picture in picture". However, since the sub-picture is displayed in a small size, the picture quality is not sufficient to show details of the picture. Therefore, it has been proposed to display two pictures in a same size simultaneously on the screen by using line memories, as known in Japanese laid open patent publications Nos. 61-193580, 61-208981 and 62-47280. However, such a double picture display by using line memories can be realized only if two video signals for the two pictures are synchronized with each other. On the other hand, it is also known to display a flickerless picture in a double of the normal field frequency by using a field memory. Hence, it has been considered to display two pictures in a same size simultaneously on the screen by using field memories. Patent Abstracts of Japan vol. 18 no. 246 (E-1546), 11 May 1994 & JP-A-06 030349 disclose a method and an apparatus for displaying video pictures of a first and a second video signal, in which a first video signal is stored in a first memory at a first predetermined frequency in synchronism with the synchronizing signal of the first video signal, a second video signal is stored in a second memory at said first predetermined frequency in synchronism with the synchronizing signal of the second video signal and the first and second video signals are read out from the first and second memories at a second predetermined frequency in synchronism with a master synchronizing signal and the pictures corresponding to the first and second video signals are displayed on a video screen. The object of the present invention is to provide a video display apparatus and method for displaying a single video picture of a first video signal in a first mode and for displaying a first and a second video picture of a first and a second video signal, respectively, in a second mode, which enable to display a first and a second picture of a first and a second video signal, respectively with substantially the same size in a second mode and to display one picture of one video signal on the basis of a double alternating read-out sequence of odd and even fields in a first mode in a simple and effective way. This object is achieved with the method according to claim 1 and the apparatus according to claim 2. With the video display method according to the invention it is possible to display the pictures of two independent video signals with approximately the same size. A television receiver according to the invention can display two pictures simultaneously on its screen in a same size or similar sizes. The invention will now be described by way of examples and with reference to the accompanying drawings in which: Fig. 1 is a schematic block diagram showing an example of a television receiver in accordance with the invention. Fig. 2 is an schematic black diagram showing a signal processor for 100 Hz flickerless picture mode and double picture mode in the picture processor of the television receiver shown in Fig. 1. Figs. 3A and 3B are timing charts of memory control in 100 Hz flickerless picture mode of the signal processor shown in Fig. 2. Fig. 4A and 4B are timing charts of examples of memory control in double picture mode of the signal processor shown in Fig. 2. Figs. 5A and 5B are schematic diagrams showing examples of display in double picture mode of the television receiver according to the invention. Fig. 6A is a schematic diagram showing a two port field memory having random block access mode which may be used in the signal processor in Fig. 2. Fig. 6B is a timing chart of a further example of memory control in double picture mode of the signal processor shown in Fig. 2. Figs. 7A, 7B, 7C and 7D are timing charts of further examples of memory control in double picture mode of the signal processor shown in Fig. 2. Referring to Fig. 1, the construction of the television receiver 1 is now explained. The television receiver 1 has an antenna input 2, which is connected to one or more tuners 3 and 4 each including a video IF signal demodulator and an audio signal demodulator so that one or more composite video signals and accompanying audio signals are obtained, respectively. The tuners 3 and 4 are connected to the audio and video signal switcher (hereinafter, AV switcher) 5 and provide the latter with the composite video signals and audio signals. Auxiliary audio and video signal inputs (hereinafter, AV input) 6 are also provided for selection by the AV switcher 5. Therefore, the AV switcher 5 supplies the following circuits with two composite video signals and accompanying audio signals selected among those input signals. One or more audio signals selected by the AV switcher 5 are supplied to a sound signal processor, though not illustrated. The audio signal is irrelevant to the invention and its explanation is omitted. Two composite video signals selected by the AV switcher 5 are supplied to the luminance and chrominance signal processors (hereinafter, Y/C processor) 7 and 8, respectively, in which the respective composite video signals are converted to respective luminance signals Y and color difference signals U and V (as a set of these signals Y, U and V, hereinafter, Y/U/V signals). A composite video signal which is selected by the AV switcher 5 to be displayed as a single picture in normal display mode or the main picture in picture-in-picture (hereinafter PIP) mode is supplied through the Y/C processor 7 and a fast switch S1 to the picture processor 9, in which the Y/U/V signals are subjected to necessary signal process and desired adjustments of picture quality, and from which the video picture signal in a RGB form is supplied to the display apparatus 10. One of the video signals supplied to the AV input 6 may be R/G/B signals. In this case, the R/G/B signals selected by the AV switcher 5 are directly supplied to the picture signal processor 9 in which a R/G/B to Y/U/V converter is provided, though it is not illustrated. If the PIP mode is selected, a composite video signal selected by the AV switcher 5 to be displayed as a sub-picture in the PIP mode is supplied through the Y/C processor 8 to the PIP processor 11, in which the video signal is subjected to such a signal process that the picture size is reduced to form the sub-picture. The Y/U/V signals for the main picture and the Y/U/V signals for the sub-picture are selectively supplied through the fast switches S1 under the control of a blanking signal accompanying the Y/U/V signals for the sub-picture to the picture signal processor 9. Accordingly, the sub-picture can be also displayed in a small size on a certain position within the main picture displayed on the screen simultaneously. The television receiver 1 is further provided with the remote controller 12 for controlling manipulation thereof. Therefore, the television receiver 1 has a remote control signal receiver 13 for receiving control signals RS from the remote controller 12 which are decoded and supplied to a controller 14 for generally controlling the television receiver 1. Television signal of the normal PAL system has the frame frequency of 25 Hz, the field frequency of 50 Hz, the effective line number of 575 in one frame, the line frequency of 15,625 kHz, the vertical or field scan speed of 20 ms/field and the line scan speed 64 µs/line. In this embodiment, however, the television receiver 1 can generate and display a flickerless picture at the field frequency of 100 Hz from a television signal of the normal PAL system. Fig. 2 shows a schematic block diagram of the signal processor 15 for 100 Hz flickerless picture mode, the main part of which is included in the picture processor 9 in Fig. 1. The signal processor 15 includes the analog to digital converter (hereinafter, ADC) 16, the field memory 17, the noise reduction circuit 18, the digital to analog converter (hereinafter, DAC) 19, the timing generator 20 and the micro processor 21. The last two may be included in the controller 14 in Fig. 1. A noise reduction circuit 18 is irrelevant to the invention and its explanation will be omitted. Analog Y/U/V signals having the field frequency of 50 Hz from the Y/C processor 7 are supplied to the ADC 16 to be converted into corresponding digital Y/U/V signals by sampling and digitizing each into 8 bits in accordance with a clock signal of 13.5 MHz for example supplied from the timing generator 20, though as an alternative, 16 MHz for example or other clock frequency may be chosen in accordance with system requirements. In practice, however, the luminace signal Y is digitized into 8 bits at the sampling frequency of 13.5 MHz and the color difference signals U and V are digitized into 8 bits at another sampling frequency of 13.5/4 MHz equal to 3.375 MHz, respectively in consideration of band width ratio of respective signals Y, U and V, 4:1:1. The digital color difference signals U and V are divided into four sets of 2 bits, respectively and combined with the digital luminance signal Y, so that each digital luminance signal Y of 8 bits, each divided 2 bits of the digital color difference signal U and each divided 2 bits of the digital color difference signal V constitute one word of 12 bits. Therefore, the analog Y/U/V signals for each effective line scan duration of 52 µs or more are digitized into around 704 or more words in case of the a clock signal of 13.5 MHz. The number of words are selected preferably as a multiple of four, for example 720 words, from the above reason. The ADC 16 may include three separate analog digital converters for processing the Y/U/V signals separately or one or two analog digital converters for processing the Y/U/V signals in a time sharing manner. The field memory 17 may be constructed as a dual port field memory operating like FIFO (First In First Out) serial register. The field memory 17 has, for example, a capacity of 245,760 words and can be written and read data asynchronously under the control of its write and read control signals. More specifically, the field memory 17 has terminals for signals for data input, data output, write control including reset write, input enable, write enable and write clock, and read control including reset read, output enable, read enable and read clock, respectively. After a reset operation for an internal write address pointer by the reset write signal, data provided to the data input terminal can be sequentially written into the storage cells designated by the write address pointer which is incremented in accordance with the write clock signal while the input enable and write enable signals are effective, and after a reset operation for an internal read address pointer by the reset read signal, the stored data can be sequentially read out to the data output terminal from the storage cells designated by the read address pointer which is incremented in accordance with the read clock signal while the output enable and read enable signals are effective. The digital Y/U/V signals of each field, for example, around 285 effective lines only which constitute 205,200 words in a case of the sampling frequency of 13.5 MHz are sequentially written into the field memory 17 for each 20 ms, as shown in the first line of Fig. 3A, with the write clock signal having the same frequency of the clock signal of the ADC 16 and supplied from the timing generator 20 and the same Y/U/V signals stored in the field memory 17 are sequentially read out for 10 ms, but twice for 20 ms, as shown in the second line of Fig. 3A, with the read clock signal of 27 MHz, which is a double of the frequency of the write clock signal, supplied from the timing generator 20, so that digital Y/U/V signals having the field frequency of 100 Hz are generated. While the digital Y/U/V signals of each odd field A are read out from the field memory 17 for the second time, simultaneously the digital Y/U/V signal of each even field B are written into the field memory 17 and vice versa as shown in the first and second lines of Fig. 3A. The digital Y/U/V signals read out from the field memory 17 are supplied through the noise reduction circuit 18 and the switch circuit S2, if provided, to the DAC 19 so as to be converted into analog Y/U/V signals having the field frequency of 100 Hz with a clock signal of 27 MHz, which is the same frequency of the read clock signal of the field memory 17, supplied-from the timing generator 20, though its timing chart is not shown in Fig. 3A. The analog Y/U/V signals are then converted to R/G/B signals and fed to the display apparatus 10 which scans horizontally each line at the line scan speed of 32 µs/line among which the effective line scan duration corresponding to the Y/U/V signals from the DAC 19 is 26 µs, the line frequency of 31.25 KHz and vertically each odd field twice for 20 ms and each even field twice for 20 ms at the field frequency of 100 Hz on its screen. The clock signal for the ADC 16, the write control signals and the read control signals for the field memory 17 and the clock signal for the DAC 19 are generated by the timing generator 20 and the micro processor 22 in synchronim with the horizontal and vertical synchronising signals of the composite video signal selected by the AV switcher 5 in Fig. 1, which are supplied to the timing generator 20 and the micro processor 22 as shown in Fig. 2. In practice, there may be small circuit delay in each operation, however it will be compensated in the total system. The above operation creates A, A, B and B sequence of fields. There are other types of sequence of fields, such as A, B, A and B sequence, in which pictures of each odd field A and each even field B are alternately displayed at the field frequency 100 Hz, and A, A*, B* and B sequence, in which a picture of each odd field A, a picture comprised of lines each having a median value of the corresponding line of each even field B and two lines of each odd field A prior to each even field B adjacent to the corresponding line, a picture comprised of lines each having a median value of the corresponding line of each odd field A and two lines of each even field B next to each odd field A adjacent to the corresponding line, and a picture of each even field B are sequentially displayed at the field frequency of 100 Hz for each frame of 25 Hz. According to the present invention, the signal processor 15 further includes, as shown in Fig. 2, the field memory 22 which may have the same construction as the field memory 17, the median filter 23, and the switch circuit S3, if provided. Similarly to the above example, the digital Y/U/V signals of each odd field A from the ADC 16 are written into the field memory 17 for 20 ms. The same signals are then read out from the field memory 17 for each first 10 ms within one frame of 40 ms according to the read clock signal of 27 MHz and supplied through the noise reduction circuit 18 and the switch circuit S2 to the DAC 19. At the same time, the digital Y/U/V signals of each odd field A read out from the field memory 17 are supplied through the switch circuit S3, if provided, to the field memory 22 and written thereinto. While the digital Y/U/V signals of each odd field A are read from the field memory 17, simultaneously the digital Y/U/V signals of each even field B from the ADC 17 are written into the field memory 17 for 20 ms. Followingly, the digital Y/U/V signals of each odd field A stored in the field memory 22 and the digital Y/U/V signals of each even field B stored in the field memory 17 are read out simultaneously therefrom for each second 10 ms within one frame of 40 ms and supplied through the noise reduction circuit 18 to the median filter 23, in which digital Y/U/V signals having respective median values between the digital Y/U/V signals of each adjacent two lines of each odd field A and the digital Y/U/V signals of each line of each even field B are produced in the manner as explained above and provided through the switch circuit S2 to the DAC 19. Subsequently, the digital Y/U/V signals of each even field B stored in the field memory 17 and the digital Y/U/V signal of each odd field A stored in the field memory 22 are read out simultaneously therefrom for each third 10 ms within one frame of 40 ms and supplied through the noise reduction circuit 18 to the median filter 23, in which digital Y/U/V signals having respective median values between the digital Y/U/V signals of each adjacent two lines of each even field B and the digital Y/U/V signals of each line of each odd field A are produced in the manner as explained above and provided through the switch circuit S2 to the DAC 19. At the same time, the digital Y/U/V signals of each even field B read out from the field memory 17 are supplied through the switch circuit S3, if provided, to the field memory 22 and written thereinto. While the digital Y/U/V signals of each even field B are read from the field memory 17 for the second time, simultaneously the digital Y/U/V signals of each odd field A are written into the field memory 17 for 20 ms. Finally, the digital Y/U/V signals of each even field B stored in the field memory 22 are read out therefrom for each fourth 10 ms within one frame of 40ms and supplied through the noise reduction circuit 18 and the switch circuit S2 to the DAC 19. The above sequence is repeated every frame of 25 Hz and the switch circuit S2 is so controlled by a switching signal generated by the timing generator 20 and the micro processor 21 that the right digital Y/U/V signals from the field memory 17, the median filter 23 or the field memory 22 can be provided to the DAC 19. Similarly to the A, A, B and B sequence, the digital Y/U/V signals provided to the DAC 19 are converted into analog Y/U/V signals having the field frequency of 100 Hz with the clock signal and then converted to R/G/B signals which are supplied to the display apparatus 10. If the A, A, B and B mode is performed by using also the field memory 22, similarly to the memory control in the A, A*, B* and B mode, memory control of the field memories 17 and 22 as shown in Fig. 3A can be used, though its explanation is omitted. Furthermore, if the A, B, A and B mode is performed, firstly the Y/U/V signals of each odd field A are read out from the field memory 17, secondary the Y/U/V signals of each even field B are read out from the field memory 17, thirdly the Y/U/V signals of each odd field A are read out from the field memory 22, and finally the Y/U/V signals of each even field B are read out from the field memory 22, respectively in Fig. 3B and the respective Y/U/V signals can be sequentially supplied to the DAC 19 as it is. The analog Y/U/V signals from the DAC 19 are then converted to R/G/B signals and supplied to the display apparatus 10 which scans horizontally each line at the line scan speed of 32 µs/line, the line frequency of 31.25 KHz and vertically each odd field for 10 ms and each even field for 10 ms alternately at the field frequency of 100 Hz on its screen. In the embodiment, double picture mode can be selected from an on screen menu displayed by manipulating certain keys of the remote controller 12 in a predetermined sequence. In the double picture mode, two different motion or still pictures can be simultaneously displayed in one screen. To realize this mode, in the signal processor 15, a further ADC 24 which is the same as or similar to the ADC 16 is connected to the field memory 22 through the switch circuit S3, if provided, as shown in Fig. 2, and supplied with analog Y/U/V signals from the Y/C processor 8 before the PIP processor 11 as shown in Fig. 1. Therefore, the analog Y/U/V signals from the Y/C processor 7 for the main picture I (hereinafter, picture I) selected by the AV switcher 5 in Fig. 1 are supplied to the ARC 16 and the analog Y/U/V signals from the Y/C processor 8 for the sub-picture II (hereinafter, picture II) selected by the AV switcher 5 in Fig. 1 are supplied to the ADC 24. In this embodiment, each of the ADCs 16 and 24 operates with the clock signals of 6.75 MHz for example to generate the digital Y/U/V signals, respectively, in the same manner as in 100 Hz flickerless picture mode described above, though as an alternative, 8 MHz for example or other clock frequency may be chosen in accordance with system requirements. Therefore, the analog Y/U/V signals for each effective line scan duration of 52 µs or more are digitized into around 352 or more words in case of the clock signal of 6.75 MHz. The number of words are selected preferably as a multiple of four, for example 360 words. The clock signals for the ADCs 16 and 24 are synchronized with the horizontal and vertical synchronizing signals of the composite video signal for the picture I and the picture II, respectively. As shown in Fig. 4A, the digital Y/U/V signals of each odd field IA and each even field IB for the picture I from the ADC 16 are then written into the field memory 17, alternately, for 20 ms. At the same time, the digital Y/U/V signals of each odd field IIA and each even field IIB for the picture II from the ADC 16 are, through the switch circuit S3, if provided, written into the field memory 22, alternately, for 20 ms. The write clock signals for the field memories 17 and 22 are also synchronized with the horizontal and vertical synchronizing signals of the composite video signal for the picture I and the picture II, respectively. The digital Y/U/V signals of each field IA or IB stored in the field memory 17 and the digital Y/U/V signals of each field IIA or IIB stored in the field memory 22 are then read out simultaneously, as shown in Fig. 4A, according to the read clock signals having a predetermined frequency which has a certain relationship with the clock frequency of the write clock signals thereof, as explained below. More precisely, the digital Y/U/V signals are read out in such a line-wise manner that the digital Y/U/V signals of each same line of each field of the picture I and each field of the picture II are alternately read out for the line scan duration. The read clock signals for the field memories 17 and 22 are synchronized with the horizontal and vertical synchronizing signals of the composite video signal for either the picture I or the picture II, in this case, the picture I. The digital Y/U/V signals read out from the field memories 17 and 22 are then supplied through the noise reduction circuit 18 and the switch circuit S2 to the DAC 19. In this case, the switch circuit S2 may be provided between the field memories 17 and 22 and the noise reduction circuit 18 instead of the location between the noise reduction circuit 18 and the DAC 19 as shown in Fig. 2. The DAC 19 then converts the digital Y/U/V signals into the analog Y/U/V signals in a reverse manner to the anolog to digital conversion of the ADCs 16 and 24 with the clock signal of the same predetermined frequency as the read clock signals for the field memories 17 and 22. The analog Y/U/V signals are then converted into R/G/B signals which are supplied to the display apparatus 10 to display two pictures on the screen. To display two pictures in 100 Hz flickerless picture mode, especially in the A, A, B and B sequence as described above, the digital Y/U/V signals of each odd field IA of the picture I and each odd field IIA of the picture II are read out from the field memories 17 and 22 twice for each 20 ms, respectively, in the above described manner so that the digital Y/U/V signals of each line are read out for each 13 µs. While the digital Y/U/V signals of each odd field IA and each odd field IIA are read out from the field memories 17 and 22 for the second time, simultaneously the digital Y/U/V signals of each even field IB and each even field IIB from the ADCs 16 and 24 are written into the field memories 17 and 22 for each 20 ms, respectively. The digital Y/U/V signals of each even field IB and each even field IIB are then read out from the field memories 17 and 22 twice for each 20 ms, respectively, in the same manner as described above. This sequence is repeated every 20 ms. The digital Y/U/V signals from the the field memories 17 and 22 are supplied to the DAC 19. The analog Y/U/V signals from the DAC 19 are finally converted into R/G/B signals which are supplied to the display apparatus 10. The display apparatus 10 scans horizontally each line at the line scan speed of 32 µs/line among which the effective line scan duration corresponding to the Y/U/V signals from the DAC 19 is 26 µs, the line frequency of 31.25 KHz and vertically each odd field twice for 20 ms and each even field twice for 20 ms at the field frequency of 100 Hz on its screen. Television receivers with the screen having a wide aspect ratio of 16:9 are becoming very popular now. If the television signal represents a picture having an aspect ratio of 16:9 in a letter box format, the picture can be displayed in the full size of a wide aspect screen of such a television, for example, by zooming. If the television signal is transmitted by the PAL-plus system which has been introduced recently, the picture can be displayed in the full size of the wide screen of a PAL-plus dedicated television receiver by scanning the full effective 575 lines. Figs. 5A and 5B shows two examples using such a wide screen having an aspect ratio 16:9 for displaying two pictures. If two pictures I and II of the aspect ratio of 4:3 are simultaneously displayed in the correct picture geometry as shown in Fig. 5A, the clock frequency of the read clock signals for the field memories 17 and 22 and the clock signal for the DAC 19 is 27 MHz for example which is four times of 6.25 MHz and the picture height is compressed to 2/3 by adjusting the vertical deflection of the display apparatus 10, for example. If each picture should be displayed in a larger size but in the correct picture geometry, it can be realized by cutting each picture at both left and right sides, decreasing the clock frequency of the read clock signals for the field memories 17 and 22 and the clock signal for the DAC 19 or increasing the clock frequency of the clock signal for the ADCs 16 and 24 and the write clock signals for the field memories 17 and 22 as much as each line length is shortened, and adjusting the vertical deflection of the display apparatus 10. For example, if two pictures I and II are simultaneously displayed in an aspect ratio of 3:3, respectively, as shown in Fig. 5B, each picture is cut by 1/8 at each side by not reading out the corresponding digital Y/U/V signals from the field memories 17 and 22. Accordingly, the clock frequency of the read clock signals for the field memories 17 and 22 and the clock signal for the DAC 19 may be selected 27 MHz which is less than four times of the frequency 8 MHz of the clock signals for the ADCs 16 and 24 and the write clock signals for the field memories 17 and 22, and the picture height is compressed to 8/9 by adjusting the vertical deflection of the display apparatus 10. Other arbitrary aspect ratios can be realized in similar manners. If the composite video signal for the picture I is missing, the horizontal and vertical synchronizing signals for synchronization of the read clock signal are also missing. In such a case, the horizontal and vertical synchronizing signals for the picture II is used by switching in the timing generator 20 and the micro processor 21 or by exchanging the composite video signals for the picture I and the picture II in the AV switcher 5 in Fig. 1. In the above described embodiment, the digital Y/U/V signals of each previous field of the pictures I and II in the field memory 17 and 22 are overwritten by the digital Y/U/V signals of each current field of the pictures I and II, respectively. If two composite video signals are not synchronized with each other in practice, the write timings of two sets of digital Y/U/V signals into the field memories 17 and 22 do not coincide with each other. If the digital Y/U/V signals of the picture II are read out from the field memory 22 earlier than the digital Y/U/V signals of each previous field of the picture II stored in the field memory 22 are over-written by the digital Y/U/V signals of each current field of the picture II more than the half field, the digital Y/U/V signals of two different fields IIA and IIB of the picture II are read out in same field, as shown in Fig. 4B. As a result, the interlace relationship in the picture II becomes incorrect and vertical resolution of the picture II is deteriorated. In order to solve this problem, a two port field memory which has a random block addressing mode is used for at least one of the field memories 17 or 22. In this embodiment, The field memory 17 is assigned as the master and the field memory 22 is assigned as a slave and the field memory 22 is constructed by a two port field memory which has the random block addressing mode. In the random block addressing mode, before starting the write and/or read operations, the initial values of the write and/or read address pointers can be designated in a block wise, for example, any one of 3072 blocks each including several words, for example, 80 words, so that the storage cells can be divided into one or more areas for different data. The random block addressing mode for the write address pointer and/or the read address pointer can be selected by providing special codes through the input enable and write enable terminals and/or the output enable and read enable terminals while the reset write signal and/or the read reset signal are effective, respectively. A start block can be then set by providing the data input terminal with a corresponding block address of 12 bits. In this embodiment, since the data rate of each digital Y/U/V signals of the pictures I and II in the double picture mode is approximately half of that in the normal 100 Hz flickerless picture mode, one field memory can be used for storing the digital Y/U/V signals of two fields. Therefore, the digital Y/U/V signals of each odd field IIA of the picture II are written into the first area M1 of the field memory 22 designated by the block address corresponding to the first block of the area M1 and the digital Y/U/V signals of each even field IIB of the picture II are written into the second area M2 of the field memory 22 designated by the block address corresponding to the first block of the area M2, separately as shown in Fig. 6A, without erasing the digital Y/U/V signals of each previous even field IIB and each previous odd field IIA, respectively. Accordingly, the digital Y/U/V signals of only odd field IIA of the picture II are read out from the first area M1 of the field memory 22 without mixed with the digital Y/U/V signals of even field IIB of the picture II and the digital Y/U/V signals of only even field IIB of the picture II are read out from the second area M2 of the field memory 22 without mixed with the digital Y/U/V signals of odd field IIB of the picture II, as shown in Fig. 6B, regardless of the read timing of the field memory 22, so that the above mentioned problem in the interlace relationship can be solved. However, even in this solution, there is still another remaining problem. The digital Y/U/V signals of each previous odd field IIA' of the picture II in the memory areas M1 of the field memory 22 will be overwritten by the digital Y/U/V signals of each current odd field IIA of the picture II and the digital Y/U/V signals of each previous even field IIB' of the picture II in the memory areas M2 of the field memory 22 will be overwritten by the digital Y/U/V signals of each current even field IIB of the picture II. If the digital Y/U/V signals of the picture II are read out from the field memory 22 earlier than the digital Y/U/V signals of each previous odd and even fields IIA' and IIB' of the picture II stored in the field memory 22 are overwritten by the digital Y/U/V signals of each current odd and even fields IIA and IIB of the picture II more than the half field, the digital Y/U/V signals of each previous and current odd fields IIA' and IIA or each previous and current even fields IIB' and IIB of the picture II are read out in same field, as shown in Fig. 6B. If the picture II is not a still picture but a relatively fast motion picture, two picture parts in different timings are displayed as one picture in the upper and lower parts on the screen, respectively, as shown in Fig. 6B, though here is no problem in the interlace relationship as mentioned above. In order to solve this problem, a two port field memory having a random block addressing mode is used for each of the field memories 17 and 22 so that the digital Y/U/V signals of each odd field IA and each even field IB of the picture I are written into the first area M1 and the second area M2 of the field memory 17, respectively, in the same manner as explanied in the above example of the field memory 22. In this embodiment, the field memory 17 is assigned as the master and the field memory 22 is assigned as a slave. In case that the signal phase d between the Y/U/V signals of the two pictures I and II are not larger than 1/2 frame or 20 ms, while the digital Y/U/V signals of each current odd field IA of the picture I are written into the area M1 of the field memory 17 for each 20 ms, the digital Y/U/V signals of each previous odd and even fields IA and IB of the picture I are sequentially read out from the areas M1 and M2 of the field memory 17 for 20 ms, and while the digital Y/U/V signals of each current even field IB of the picture I are written into the area M2 of the field memory 17 for each 20 ms, the digital Y/U/V signals of each previous even and odd fields IB and IA of the picture I are sequentially read out from the areas M2 and M1 of the field memory 17 for 20 ms. The digital Y/U/V signals of each field IIA or IIB of the picture II are read out from each area M1 or M2 of the field memory 22 twice for each 20 ms in same field phase as to read out the digital Y/U/V signals of the picture I as shown in Fig. 7A. In case that the signal phase d between the Y/U/V signals of the two pictures I and II are larger than 1/2 frame or 20 ms, if the above read out timing is maintained, the same problem as shown in Fig. 6B will happen. Therefore, in this case, while the digital Y/U/V signals of each current odd field IA of the picture I are written into the area M1 of the field memory 17 for each 20 ms, the digital Y/U/V signals of each previous even and odd fields IB and IA of the picture I are sequentially read out from the areas M2 and M1 of the field memory 17 for 20 ms, and while the digital Y/U/V signals of each current even field IB of the picture I are written into the area M2 of the field memory 17 for each 20 ms, the digital Y/U/V signals of each previous odd and even fields IA and IB of the picture I are sequentially read out from the areas M1 and M2 of the field memory 17 for 20 ms. The digital Y/U/V signals of each field IIA or IIB of the picture II are read out from each area M1 or M2 of the field memory 22 twice for each 20 ms in same field phase as to read out the digital Y/U/V signals of the picture I as shown in Fig. 7B. The signal phase d can be detected in the timing generator 20 or the micro processor 21 to control the above read out timing. It is possible to change the read out timing in response to whether the signal phase d is between 0 and 1/2 field or 10 ms (Fig. 7C), between 1/2 field or 10 ms and 1 field or 20 ms (Fig. 7A), between 1 field or 20 ms and 1+1/2 field or 30 ms (Fig. 7B), or between 1+1/2 field or 30 ms and 2 field or 40 ms (Fig. 7D). If some deterioration in picture quality is acceptable, other read out timings than the above can be also applied. Although the field memory 17 is assigned as the master and the field memory 22 is assigned as a slave with respect to the read out timing in the above embodiments, both of the field memories 17 and 22 can be assigned as slaves which are read out by read control signals independent from the write control signals of the field memories 17 and 22. In the above, the double picture display in 100 Hz flickerless picture mode of the A, A, B and B sequence was explained. However, the double picture display in the A, B, A and B sequence or A, A*, B*, and B sequence can be also realized by modifying the read out timing and/or sequence of the Y/U/V signals from the field memories 17 and/or 22 or by changing the memory type into frame memory, for example, if available. While the video signals for the pictures I and II are handled in a form of digital Y/U/V signals, it is possible to handle the video signals in form of analog Y/U/V signals, analog or digital R/G/B signals or other form of video signals. This invention can be applied not only to a television receiver with a wide aspect ratio but also to a television receiver with a normal aspect ratio such as 4:3, This invention can be also applied to a television receiver of normal PAL system having the field frequency of 50 Hz or to a television receiver of NTSC system having the field frequency of 60 Hz in a normal mode or 120 Hz in a flickerless mode. This invention can be further applied to a video monitor without tuner but with several video signal input terminals.

Claims: Method for displaying a single video picture of a first video signal in a first mode and for displaying a first and a second video picture of a first and a second video signal, respectively, in a second mode on a display device (10), comprising steps of: receiving said first and said second video signal, storing said first video signal in a first memory means (17) and a second memory means (22) in said first mode, generating, in said first mode, write control signals and read control signals controlling the first and the second memory means (17, 22) so that the first video signal is read from the first and the second memory means (17, 22) faster than it is written in, storing said first and said second video signal in the first memory means (17) and the second memory means (22), respectively, in said second mode, generating, in the second mode, a first write control signal controlling the first memory means (17) so that the first video signal is written into the first memory means (17) at a first predetermined frequency in synchronism with the synchronizing signals of the first video signal, a second write control signal controlling the second memory means (22) so that the second video signal is written into said second memory means (22) at the first predetermined frequency in synchronism with the synchronizing signal of the second video signal, and a master synchronizing signal controlling said first and said second memory means (17, 22) so that the first and second video signals are alternately linewise read out from said first and second memory means (17, 22) at the second predetermined frequency in synchronism with the master synchronizing signal so that a line scan duration of said display device (10) is composed of each same line of each field of the first video signal and each field of the second video signal, displaying a single picture corresponding to the first video signal in the first mode and simultaneously displaying a first and a second picture corresponding to the first and second video signal, respectively, in the second mode. Video display apparatus for displaying a single video picture of a first video signal in a first mode and for displaying a first and a second video picture of a first and second video signal, respectively, in a second mode on a display means (10), comprising: video signal input terminal means (2, 6) for receiving said first and second video signal, first memory means (17) and second memory means (22), whereby the first memory means (17) and the second memory means (22) store said first video signal in said first mode, and the first memory means (17) and the second memory means (22) store the first and second video signal, respectively, in said second mode, write and read control signal generating means (14, 20, 21) for generating, in said first mode, write control signals and read control signals controlling the first and the second memory means (17, 22) so that the first video signal is read from the first and the second memory means (17, 22) faster than it is written in, and for generating, in the second mode, a first write control signal controlling the first memory means (17) so that the first video signal is written into said first memory means (17) at a first predetermined frequency in synchronism with the synchronizing signals of the first video signal, a second write control signal controlling the second memory means (22) so that the second video signal is written into said second memory means (22) at the first predetermined frequency in synchronism with the synchronizing signal of the second video signal, and a master synchronizing signal controlling said first and second memory means (17, 22) so that the first and second video signals are alternately linewise read out from said first and second memory means (17, 22) at the second predetermined frequency in synchronism with the master synchronizing signal so that a line scan duration of said display means (10) is composed of each same line of each field of the first video signal and each field of the second video signal, said display means (10) being provided with the first video signal read out from said first memory means (17) and said second memory means (22) for displaying a single picture corresponding to the first video signal on the screen thereof in the first mode and provided with the first and second video signal read out from said first and second memory means (17, 22) for simultaneously displaying a first and a second picture corresponding to the first and second video signal, respectively, on a screen thereof in the second mode. A video display apparatus according to claim 2, characterized by Y/C processor means (7, 8) connected to said video signal input terminal means (2, 6) for converting the first and second video signals into first and second analog Y/U/V signals analog to digital converter means (16, 24) connected between said Y/V processor means (7, 8) and the input of said memory means (17, 22) for converting the first and second analog Y/U/V signals into first and second digital Y/U/V signals, and digital to analog converter means (19) connected to an output of said memory means (17, 22) for converting the first and second digital Y/U/V signals read out from said first and second memory means (17, 22) into analog Y/U/V signals. A video display apparatus according to claim 2 or 3, characterized in that said first and second memory means (17, 22) are field memory means. A video display apparatus according to claim 4, characterized in that said first and second field memory means (17, 22) are constructed as two port field memories. A video display apparatus according to claim 5, characterized in that at least one of the said first and second field memory means (17, 22) is constructed as two port field memory having a random block addressing mode. A video display apparatus according to one of claims 2 to 6 characterized in that the synchronizing signals of either of the first or second video signals are assigned as the master synchronizing signals. A video display apparatus according to one of claims 2 to 7, characterized in that the second predetermined frequency is four times the first predetermined frequency. A video display apparatus according to one of claims 2 to 8, characterized in that the first and second video signals are signals in PAL system each having the field frequency of 50 Hz and the two pictures corresponding to the first and second video signals are displayed on said screen at a field frequency of 100 Hz. A video display apparatus according to one of claims 2 to 9, characterized in that said screen has a wide aspect ratio of 16:9. A video display apparatus according to claim 10, characterized in that the two pictures are displayed on the screen in an aspect ratio of 4:3. A video display apparatus according to claim 10, characterized in that the two pictures are displayed on the screen in a aspect ratio of 3:3.

Inventors: ENDRESS WOLFGANG DIPL-ING, ENDRESS, WOLFGANG, DIPL.-ING.
Applicants: SONY WEGA PRODUKTIONS GMBH, SONY-WEGA PRODUKTIONS GMBH
Application year: 1994
Main classification: H04N5
IPC codes: H04N5