High-performance superconducting digital-to-analog converter employing double-junction SQUID flip-flops

Abstract: A high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low-power D/A conversion. The high-performance superconducting D/A converter includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit, which generates a series of discrete binary voltages, and a double-junction SQUID voltage selector circuit, which selects the binary voltages in accordance with a digital input signal. The currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input.

Description: BACKGROUND OF THE INVENTION This invention relates generally to digital-to-analog converters and, more particularly, to high-performance superconducting digital-to-analog converters. High-performance superconducting digital-to-analog (D/A) converters are required in a variety of applications for high-speed, low-power D/A conversion. One such application is digital superconducting flux-locked magnetometers, which provide highly sensitive detection of very small magnetic fields. Digital superconducting magnetometers have been proposed for use in such diverse areas as oil and mineral exploration, submarine and mine detection, and noninvasive medical diagnostic procedures. A superconducting magnetometer typically employs one or more superconducting quantum interference devices (SQUID's) for measuring the strength of a magnetic field. A SQUID is a superconducting loop having a Josephson tunnel junction as a weak link in the loop. The weak link functions as a flux gate to allow the amount of magnetic flux in the loop to change. The amount of magnetic flux in the superconducting loop is quantized, which means that the loop supports only integer multiples of a flux quantum. When a SQUID is placed in a magnetic field, a superconducting current flows around the loop to oppose any change in the magnetic flux. However, when the opposing current exceeds the critical current of the superconducting loop, the Josephson junction opens the loop and allows one or more flux quantum to enter. A superconducting magnetometer is constructed by adding a feedback path to a SQUID, thus allowing a current to be applied to the superconducting loop that cancels the current induced by the magnetic field. This maintains the magnetic flux in the loop constant, while the amount of current applied to the loop to balance out the induced current is a measure of the magnetic field. In a digital superconducting magnetometer, a superconducting D/A converter is required in the feedback path to convert the digital feedback signal to an analog current. The use of a superconducting D/A converter in a digital superconducting magnetometer is for example disclosed in EP 0 461 742 A2. Magnetometer SQUIDs can also be used to measure an input current. In this case, the input current is simply sent through a superconducting field coil and induces a magnetic flux in the magnetometer SQUID. The same principle is also used in the superconducting analog-to-digital converter disclosed in EP 0 414 426 A1. Here, an input current is inductively coupled to a double-junction SQUID. When the input current changes, flux quanta enter or leave the superconducting SQUID loop, thereby generating voltage pulses. Thus, the double-junction SQUID functions as a quantizer. A bidirectional binary counter having N stages of four-junction SQUID flip-flops counts the voltage pulses. In an alternative embodiment, the SQUID flip-flops are three-junction flip-flops. Conventional superconducting D/A converters typically employ a binary network of latching Josephson junctions and resistors which generates a set of reference voltages based on the current-voltage characteristics of the junctions. The voltage of a Josephson junction is zero in the superconducting or zero voltage state and equal to the energy gap voltage of the superconducting material in the nonsuperconducting or voltage state. An example for a superconducting D/A converter of this type is given in EP 0 222 470 A2. The digital-to-analog converter consists of multiple stages, from the stage corresponding to the least significant bit to the most significant. The least significant stage includes a single junction, the next stage uses two junctions in series, the next stage uses four junctions in series and the most significant stage uses 2 N junctions in series. The digital quantity to be converted is applied to the various stages, causing a transition of the junctions from the zero voltage state to the voltage state. Therefore, each stage functions as a voltage generator. The voltages are added together at a single adding junction for output from the converter. EP 0 222 470 A2 also discloses a second embodiment, where a single junction at each stage is used together with an appropriate resistive ladder in series to apply binary weighting to the stages. In the second embodiment, a precise matching of the resistive ladders is required. In all superconducting D/A converters using the energy gap voltage as the reference voltage, uniform Josephson junctions having steep conductances at the gap voltage are required. For example, in the first embodiment disclosed in EP 0 222 470 A2, the uniformity in the energy gap voltage must be 1/2 bit greater than 2 N , which, for 10 bits of resolution (N), requires less than a 5x10 -4 variation in the gap voltages of the Josephson junctions, or about one microvolt. A different approach is disclosed in US patent 5,128,675. In the system disclosed here, the gap voltage is not directly output as the analog signal. The switching of a Josephson junction causes a current to flow in an alternative line instead of flowing through the line containing the Josephson device. In particular, for each bit a stage is provided in which the current passes a first resistor and then a Josephson junction leading to a first output line or alternatively a second resistor leading to a second output line. To obtain switching, the bits are directly applied to the respective Josephson junction. In an alternative embodiment disclosed in US patent 5,128,675, in each stage, the current, after passing the first resistor, flows to the first output line via a second resistor and a first Josephson junction and to the second output line via a third resistor and a second Josephson junction. Here, the bits are applied to the respective first Josephson junction, and the inverse signal is applied to the second Josephson junction. The latching nature of conventional superconducting D/A converters also requires synchronous clocking to reset the junctions during each clock cycle, resulting in high power dissipation. Accordingly, there has been a need for a superconducting D/A converter that does not have these drawbacks. The present invention clearly fulfills this need. SUMMARY OF THE INVENTION The present invention resides in a high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low-power D/A conversion. The high-performance superconducting D/A converter includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit, which generates a series of discrete binary voltages, and a double-junction SQUID voltage selector circuit, which selects the binary voltages in accordance with a digital input signal. The currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input. The voltage divider circuit includes a reference oscillator or clock and N stages of double-junction SQUID flip-flops, where N is the number of bits of the digital input. The divider SQUID flip-flops are connected together in a cascade arrangement and divide a reference voltage V 0 into N-1 discrete binary voltages (V 0 /2, V 0 /4, V 0 /8, ..., V 0 /2 N-1 ). The reference voltage V 0 is generated in the most significant bit (MSB) divider SQUID flip-flop by inductively coupling the reference clock signal to the flip-flop. The induced clock signal generates the reference voltage V 0 by way of the AC Josephson effect, which fixes the reference voltage to the frequency of the clock signal. The clock frequency can be maintained with good accuracy, thus providing a stable and accurate reference voltage. The voltage selector circuit includes N stages of nonlatching double-junction SQUID flip-flops, where each bit of the digital input is inductively coupled from its bit line to its respective selector SQUID flip-flop. The high-performance D/A converter of the present invention operates asynchronously due to the use of nonlatching Josephson junctions in the voltage selector circuit. This asynchronous operation eliminates the need for a clock to reset the junctions, thus minimizing power dissipation and output transients due to input changes. The D/A converter operates at high speed, with the selector SQUID flip-flops being toggled at gigahertz rates. The D/A converter has a large dynamic range and requires only N equally matched resistors. It will be appreciated from the foregoing that the present invention represents a significant advance in the field of superconducting digital-to-analog converters. Other features and advantages of the present invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of the high-performance superconducting digital-to-analog converter of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in the drawings for purposes of illustration, the present invention is embodied in a high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low-power D/A conversion. As shown in Figure 1, the high-performance superconducting D/A converter of the present invention includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit 10, which generates a series of discrete binary voltages, and a double-junction SQUID voltage selector circuit 12, which selects the binary voltages in accordance with a digital input signal on bit line 14. The currents generated by the selected binary voltages are added together to produce an analog output current on line 16 that represents the digital input. The voltage divider circuit 10 includes a reference oscillator or clock 18 and N stages of double-junction SQUID flip-flops 20, where N is the number of bits of the digital input. The divider SQUID flip-flops 20 are connected together in a cascade arrangement and divide a reference voltage V 0 into N-1 discrete binary voltages (V 0 /2, V 0 /4, V 0 /8, V 0 /2 N-1 ). The reference voltage V 0 is generated in the most significant bit (MSB) divider SQUID flip-flop 20 by inductively coupling the reference clock signal to the flip-flop. The induced clock signal generates the reference voltage V 0 by way of the AC Josephson effect, which fixes the reference voltage to the frequency of the clock signal. The clock frequency can be maintained with good accuracy, thus providing a stable and accurate reference voltage. The reference voltage is Φ 0 υ, where υ is the clock frequency and Φ 0 is a single flux quantum (Φ 0 = h/2e= 2.07x10 -15 weber, where e is the electron charge and h is Planck's constant). The voltage selector circuit 12 includes N stages of nonlatching double-junction SQUID flip-flops 22, where each bit of the digital input is inductively coupled from the bit line 14 to its respective selector SQUID flip-flop 22. Each divider SQUID flip-flop 20 includes two Josephson tunnel junctions 24 and a center-tapped inductor 26 connected in a superconducting loop 28. One terminal of each of the Josephson junctions 24 is connected to a different end terminal of the inductor 26 and the other terminal of each of the Josephson junctions 24 is connected to ground. The reference clock signal is inductively coupled to the MSB divider SQUID flip-flop 20 by an inductor 30, and a constant gate current is injected through a resistor 32 into the center-tap terminal of the inductor 26 in the MSB divider SQUID flip-flop 20. The carry junction of each divider SQUID flip-flop 20, except the least significant bit (LSB) divider SQUID flip-flop, is connected through a resistor 34 to the center-tap terminal of the inductor 26 in the next lower-voltage divider SQUID flip-flop 20. The divider SQUID flip-flops 20 operate in the voltage state. Each selector SQUID flip-flop 22 includes two Josephson tunnel junctions 36 and a center-tapped inductor 38 connected in a superconducting loop 40. One terminal of each of the Josephson junctions 36 is connected to a different end terminal of the inductor 38 and the other terminal of each of the Josephson junctions 36 is connected to ground. A shunt resistor 42 is placed across each Josephson junction 36 so that the selector SQUID flip-flops 22 operate in the nonlatching mode. Each bit of the digital input signal is inductively coupled from the bit line 14 to its respective selector SQUID flip-flop 22 by an inductor 44. The noncarry junction of each divider SQUID flip-flop 20 is connected through a resistor 46 to the center-tap terminal of the inductor 38 in the corresponding selector SQUID flip-flop 22 and through an additional resistor 48 to the analog output on line 16. Each selector SQUID flip-flop 22 is activated by its respective bit on bit line 14. If the bit line is zero, the selector SQUID flip-flop 22 is flux biased at zero and its output voltage is zero volts. However, when the bit line is high, the selector SQUID flip-flop 22 is flux biased at its operating point and its output voltage is that of its corresponding divider SQUID flip-flop 20 divided by two. The voltage of each divider SQUID flip-flop 20 is cut in half by the selector SQUID flip-flop 22 because the two Josephson junctions 36 in the selector SQUID flip-flop 22 do not toggle at the same time when a pulse comes in on bit line 14. In an alternative embodiment of the present invention, each selector SQUID flip-flop 22 is replaced by a transmission gate, which is a single Josephson junction or SQUID that toggles at the same rate as the noncarry signal from the divider SQUID flip-flop 20. This increases the output voltage by a factor of two. The high-performance D/A converter of the present invention operates asynchronously due to the use of nonlatching Josephson junctions 36 in the voltage selector circuit 12. This asynchronous operation eliminates the need for a clock to reset the junctions, thus minimizing power dissipation and output transients due to input changes. The D/A converter operates at high speed, with the selector SQUID flip-flops 22 being toggled at gigahertz rates. The D/A converter has a large dynamic range and requires only N equally matched resistors. The device may be fabricated from niobium, niobium nitride, other low-temperature superconducting materials, or high-temperature superconducting materials.

Claims: A high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low power D/A conversion, comprising: a voltage divider circuit (10) for generating a series of discrete binary voltages from a reference voltage (V o ); and a voltage selector circuit (12) for selecting the binary voltages in accordance with a digital input signal; wherein currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input; and wherein the voltage divider circuit (10) comprises a reference clock (18) for generating the reference voltage by way of the AC Josephson effect using a reference clock signal, thus fixing the reference voltage to the frequency of the clock signal. The high-performance superconducting D/A converter according to claim 1, wherein the voltage divider circuit (10) includes at least one double-junction superconducting quantum interference device (SQUID) (20). A high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low power D/A conversion, comprising: a voltage divider circuit (10) for generating a series of discrete binary voltages from a reference voltage V o ; and a voltage selector circuit (12) for selecting the binary voltages in accordance with a digital input signal; wherein currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input; and wherein the voltage divider circuit (10) comprises at least one double-junction superconducting quantum interference device SQUID(20); and wherein the voltage selector circuit (12) comprises at least one double-junction superconducting quantum interference device SQUID (22). The high-performance superconducting D/A converter according to claim 3, wherein the voltage divider circuit (10) comprises a reference clock (18) for generating the reference voltage V 0 by way of the AC Josephson effect using a reference clock signal, thus fixing the reference voltage to the frequency of the clock signal. The high-performance superconducting D/A converter according to claim 2 or 3, wherein the voltage divider circuit (10) includes N stages of double-junction SQUID flip-flops (20), where N is the number of bits of the digital input; wherein the divider SQUID flip-flops (20) are connected together in a cascade arrangement and divide said reference voltage V 0 into N-1 discrete binary voltages (V 0 /2, V 0 /4, V 0/8 ..., V 0 / 2N-1 ). The high-performance superconducting D/A converter according to claim 4, wherein the voltage divider circuit includes N stages of double-junction SQUID flip-flops (20), where N is the number of bits of the digital input; wherein the divider SQUID flip-flops (20) are connected together in a cascade arrangement and divide said reference voltage V 0 into N-1 discrete binary voltages (V 0 /2, V 0 /4, V 0 /8 V 0 /2 N-1 ); and wherein the reference voltage V 0 is generated in the most significant bit (MSB) divider SQUID flip-flop by inductively coupling the reference clock signal to the flip-flop. The high-performance superconducting D/A converter according to claim 5 or 6, wherein each divider double-junction SQUID flip-flop (20) includes a center-tapped inductor (26) connected in a superconducting loop (28) with the two Josephson tunnels junctions (24) of the divider double-junction SQUID flip-flop (20), one terminal of each of the Josephson junctions (24) being connected to a different end terminal of the inductor (26) and the other terminal of each of the Josephson junctions (24) being connected to ground; and wherein a constant gate current is injected through a resistor (32) into the center-tap terminal of the inductor in the most significant bit (MSB) divider SQUID flip-flop and the carry junction of each divider SQUID flip-flop, except the least significant bit (LSB) divider SQUID flip-flop, is connected through a resistor (34) to the center-tap terminal of the inductor (26) in the next lower voltage divider SQUID flip-flop. The high-performance superconducting D/A converter according to one of the claims 5 to 7, wherein the voltage selector circuit (12) includes N stages of nonlatching double junctions SQUID flip-flops (22), each bit of the digital input being inductively coupled from a bit line (14) to its respective selector SQUID flip-flop (22). The high-performance superconducting D/A converter according to claim 8, wherein each selector double-junction SQUID flip-flop (22) includes a center-tapped inductor (38) connected in a superconducting loop (40) with the two Josephson tunnel junctions (36) of the double-junction SQUID flip-flop (22), one terminal of each of the Josephson junctions (36) being connected to a different end terminal of the inductor (38) and the other terminal of each of the Josephson junctions (36) being connected to ground; and wherein a shunt resistor (42) is placed across each Josephson junction (36) so that the selector double-junction SQUID flip-flops (22) operate in the nonlatching mode. The high-performance superconducting D/A converter according to claim 9, wherein the noncarry junction of each divider double-junctions SQUID flip-flop (20) is connected through a resistor (46) to the center-tap terminal of the inductor (38) in the corresponding selector SQUID flip-flop (22) and through an additional resistor (48) to the analog output (16).

Inventors: SANDELL ROBERT D, SANDELL, ROBERT D.
Applicants: TRW INC, TRW INC.
Application year: 1994
Main classification: H03M1
IPC codes: H03M1, H03K23