COATED BONDING WIRES IN HIGH LEAD COUNT PACKAGES

Abstract: A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip (137) is mounted upon a suitable leadframe (140) and the bonding pads (138) wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires (143) are first coated with an insulative material.

Description: COATED BONDING WIRES IN HIGH LEAD COUNT PACKAGES Background of the Invention High lead Gount semiconductor device packages require a very close spacing between the bonded wires that interconnect the IC chip bonding pads with the package leadframe. If a plastic package is to be created by conventional transfer molding, the plastic flow in the process will produce wire sweep in whiGh those wires running perpendicular to the flow will be "swept" or moved along with the flow. This can produce shorting between adjaoent wires whioh results in a defective product. As higher lead count packages are developed, the wires are doser together and wire sweep becomes more of a problem. Figure 1 shows a 132 lead package structure. The out¬ lines show the inner portions of a 132 lead pattern in a Lead- frame. The peripheral numbers identify the fingers starting at 1 at the vertical center and proceeding counterclockwise around the array. Every fifth finger is shown numbered. The four fingers 133 at the four array corners support the lead frame chip mounting pad 134, whioh will aGGomodate various sized IC Ghips. The lead wires that interconnect the IC ohip and the leadframe are identified as elements 143. Only two of the 130 wires shown are identified. Three IC chips are shown. The 1, 1.5 and 2 micron geometries, labeled 135, 136 and 137, shown are related to the IC feature size. It turns out that the smaller feature sizes result in smaller Ghip sizes. The following ohart shows the aGtual physical dimensions for the three fabrication geometries illustrated in figure 1. The upper numbers are in mils and the lower numbers are in miorons: The wire connections are shown only for the 2 micron die 137 fabrication size. Clearly, the smaller die sizes must involve closer bonding pad spacing and longer wires. In terms of wire sweep producing wire shorting, all of the figure 1 configura- tions are susceptible. The length to spacing ratio of the wires in the 2 micron geometry is almost 25:1. However, with the 1 micron geometry chip the 0.089 micron spacing and 6.65 micron length results in a ratio of almost 750:1. This large ratio is clearly much more susceptible to shorting. It would be desirable to avoid the wire shorting problems resulting from wire sweep due to molding compound flow. The most immediate solution to the problem would be to use insulated wire in the wire bonding machines. However, such insulation interferes with the machine operation and the insulation would have to be stripped from the ends of the wire being bonded, thus, making the wire bonding machines and wire handling excessively complex. Summary of the Invention It is an object of the invention to avoid shorting due to wire sweep during the transfer molding of high lead count semiconductor device packages. It is a further object of the invention to coat the bonded wires, in the fabrication of transfer molded high lead count semiconductor devioe paokages, with insulation after they are installed and befor ransfer molding. These and other objects are achieved as follows. A suitable polymer is dissolved in a solvent, or otherwise liquified, to produce a liquid having the desired viscosity. A lead frame with a mounted semiGonduGtc τ - deviGe is provided with wire bonds in the conventional mam . The lead frame is inverted so that the bond wires projeot downwardly and the bond wires immersed in the liquid polymer. As the assembly is then raised, the polymer will have coated the wires. Subsequent evaporation of the solvent will leave the wires with a polymer insulation that will avoid shortinα even if the wires are pushed together during transfer ing. Brief Description of the Drawing Figure 1 is a " plan view of the central portion of a conventional (prior art) leadframe pattern having a large lead count. Outlines of three different chip sizes are shown along with the bond wires that would be present for the largest chip. Figure 2 is a simplified edge view of a lead¬ frame with its mounted and wire bonded IC chip about to be dipped into a tank containing liquified polymer. Figure 3A is a simplified edge view of the figure 2 showing during the dipping operation. Figure 3B is a magnified showing in partial cross section of the circled portion of figure 2. Figure 4 is a block diagram showing the peooess of the invention. Figure 5A is an isometrio view of coated wires. Figure 5B is a magnified showing coating on wires. Description of the Invention With reference to figure 2 a lead frame segment 140 is shown along with a semiconductor chip 137 located upon chip mounting pad 134. Wires 143 are shown bonding to the chip bonding pads 138. A tank, shown schematically at 141, contains a quantity of liquid insulative material which will be used to coat the wires. It is preferred that the insulative material be composed of a liquified polymer that has the required physical characteristios. For example, a polymer can be employed in its monomeric form as a liquid or it can be dissolved in a suitable solvent. If desired, the insulative material can be heated to modify its viscosity. The preferred viscosity is in the range of about 2,000 to 5,000 centipoises. This viscosity range will produce a liquid flow which will coat the individual wires without forming a coating that spans the space between wires. This latter condition is to be avoided because such a coating would interfere with the flow of the subsequently applied molding compound. Too low a viscosity will result in a coating that is too thin and that may not fully adhere to the wires during dipping. As shown in figure 3A, the assembly 140 is dipped into the liquid insulative material so that the lead wire apexes are coated. Figure 3B is a magnified showing of the circled portion of 3A. The portions of the lead wires 143 that are immersed in the liquid insulative material 142 would be the por¬ tion of the lead wire that would be most likely to short to the adjacent wire during the lead sweep that occurs during transfer molding. Dipping, as shown, is the preferred method of coating the wires. Alternatively, the insulative material can be applied by way of a hollow needle that is located adjacent to lead wires 143. The needle would be translated around the mounted structure 140 to projeot the insulative material onto the wires. As showing in figures 5A/B, when assembly 140 is withdrawn from tank 141, the insulative material will cling to the to the wires thereby forming a coating thereon. The liquid is then solidified by solvent evaporation, polymizeration (if a monomer was used), or cooling (if thermal liquifaction was used). Typically, the assembly is passed through a heated furnace or chamber. The wires are now covered with an insulating film. Then the a embly 140, with the insulated wires in plaoe, is located in a transfer mold (not shown) and the assembly provided with a transfer molded plastic housing in the conventional manner. Figure 4 is a block diagram of the process that represents the preferred embodiment of the invention. In bloGk 145 the leadframe is formed, preferably in strip form, wherein a succession of suitable patterns is formed along the strip. Such a strip can be operated in the form of a continuous tape or in short tape segments that coicain only a few sue patterns. The IC chips are formed in block 146 to provide the desired circuit function whioh typically requires a high lead count package. Gate-array chips are typical. First, the ohips are secured (in blook 147) to the leadframe mounting pad, by soldering or conductive adhesive, and then, in block 148, the lead wires are applied. In block 149 the liquified insulative material is applied to the bonded wire preferably by controlled dipping. In bloGk 150, the insulative material clinging to the lead wires is solidified. Then, as shown in blook 151, the plastic package is applied by transfer molding wherein the wire coating obviates the shorting typically produced by wire sweep. Then, in blook 152, the packaged semicon¬ ductor device is exoised from the tape and thereafter treated as a oonventional packaged IC. The invention has been described and a preferred embodiment detailed. Alternatives have also been described. When a person skilled in the art reads the foregoing description, other alternatives and equivalents, within the spirit and intent of the' invention, will be apparent,. Accordingly, it is intended that the scope of the invention be limited only by the claims that follow.

Claims: We claim: 1. A high lead count ilded plastic semiconductor device housing comprising: a metal leadframe; a semiconductor device mounted upon said lead¬ frame; wires bonded to said semiconductor and to said leadframe to provide electrical interconnection therebetween; a molded plastic encapsulant surrounding said semiconductor and portions of said leadframe; and a coating of insulative material surrounding a portion of said wires. 2. The molded plastic semiconductor device housing of claim 1 wherein said coating of insulative material comprises a polymer applied to said wires in a location intermediate between said semiconductor device and said leadframe. 3. The process for forming a high lead count molded plastic semiconductor housing comprising the steps: forming a semiconductor device having a large number of bonding pads; forming a leadframe having metal finger patterns and an associated device mounting pad; bonding said semiconductor device to said mounting pad; bonding interconnection wires between said bonding pads and said metal finger patterns; applying an insulative coating to said wires; locating said leadframe along with said bonded semioonduotor device and said interconnection wires in a transfer mold; and transfer molding an encapsulating plastio around said semiconductor device and portions of said leadframe whereby said interconnection wires are swept in said molding step and said insulative ooating prevents said interconnection wires from shorting together. 4. The process of claim 3 wherein said step of applying an insulative ooating comprises the steps: 0 dissolving an insulative polymer in a solvent to form a liquid; applying said liquid to coat said wires; and heating said wires, thus ooated, to evaporate said solvent thereby solidifying said polymer. 5 5. The process of claim 3 wherein said step of applying an insulative ooating comprises the steps: produoing a liquid monomer form of said polymer; applying said liquid monomer to coat said wires; and o heating said wires to polymerize said monomer thereby solidifying said polymer. 6. The process of daim 4 wherein step of dis¬ solving is operated to produce a liquid having a viscosity of about 2,000 - 5,000 oentipoises.

Inventors: BURKE THOMAS S, WEILER PETER M, BURKE, THOMAS, S., WEILER, PETER, M.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1994
Main classification: H01L23
IPC codes: H01L21, H01L23