METHODS AND APPARATUS FOR PREVENTING ROUNDING ERRORS WHEN TRANSFORM COEFFICIENTS REPRESENTING A MOTION PICTURE SIGNAL ARE INVERSELY TRANSFORMED

Abstract: Mismatch error occur in the local decoder of a MPEG-standard compressor for a motion picture signal, and in an MPEG-standard expander for a compressed motion picture signal. This is because of the lack of a standard for rounding results of <*>.5 (<*> is an integer) obtained when a set of transform coefficients resulting from compressing the motion picture signal is inversely orthogonally transformed. The invention prevents mismatch errors by preprocessing the set of transform coefficients prior to the inverse othogonal transform (15). The transform coefficients in the set are summed (23A) and the parity (odd or even) of the sum is judged (21). When the parity of the sum is judged to be even, the parity of one of the transform coefficients in the set is inverted (28) to provide a parity-inverted transform coefficient. This makes the parity of the sum odd. Then, when the set of transform coefficients indluding the parity-inverted transform coefficient is inversely orthogonally transformed (15), none of the results of the orthogonal transform will have a value of <*>.5.

Description: DESCRIPTION Methods and Apparatus for Preventing Rounding Errors when Transform Coefficients Representing a Motion Picture Signal are Inversely Transformed TECHNICAL FIELD This invention relates to amethod and apparatusfor pre- processing transformcoefficients, a method and apparatus for performing inverse orthogonal transform, a method and apparatus for compressing an information signal, a method and apparatus for expanding a compressed information signal, and a recording medium. More particularly, the invention relates to a method and apparatus forpre-processing transform coefficients, a method and apparatus for performing inverse orthogonal transform, a method and apparatusfor compressing an information signal, a method and apparatus for expanding a compressed information signal, and a recording medium for a motion picture signal. BACKGROUND ART Orthogonal transforms are used in variousapplications in diverse digital signal processing systems. Orthogonal transforms permit signal processing to be carried out in the frequency domain. The Fast FourierTransform (FFT) and theDiscrete Cosine Transform (DCT), etc. arewidely knowntypes of orthogonal transform. An orthogonal transform analyzes, for example, a fragment of a signal in the time domain into frequency components (varying depending upon the orthogonal transform function applied) indicating the spectrum (i.e., the distribution of energy versus frequency) of the original signal fragment in the time domain. By processing in variousways the frequencycomponents (commonly called transform coefficients) resulting from orthogonally transforming the signal frapent, redundancy in the original signal fragment can be reduced. In other words, by orthogonally transforming the original signal fragment, and processing the resulting transform coefficients, the original signal fragment canbe represented usingfewer bits than were used to represent the original signal frapent. Moreover, by inversely orthogonally transforming the transform coefficients, the original signal frapent in the time domain can be recovered. Apparatus for compressing a motion picture signal and for expanding a compressed motion picture signal are common examples of digital signal processing systems that use orthogonal transform processing. It is known that the signal power of signals having a high correlation is concentrated at lower frequencies in the frequency domain. As the concentration of signal power on a specific coordinate axis (e.g., the frequencyaxis) increases, signal redundancy can beprogressively reduced, and the signal can be compressed more efficiently. Since a motion picture signal is generally highly correlated, both spatially, and in time, orthogonal transform processing can be applied to concentrate the signal power on a specific coordinate axis, and the motion picture signal can be compressed with high efficiency. Hitherto, an extremely large amount of information has been required to represent a motion picture, using, for example, an NTSC-standard video signal. Because of this, recording a motion picture signal has required arecording mediumwith a very high storage capacity if the medium is to provide an acceptably-long recordingtime. Moreover, the information rateat whichthe motionpicture signal is recorded on andreproduced from such amedium hasbeen very high. Physically large magnetic tapes or optical discs have therefore been required to store motion picture signals. If it is desired to record a motion picture signal on a more compact recording medium with an acceptably-long recording time, signal compression must be applied to the motion picture signal to reduce the amount of information that needs to be stored. In addition, an apparatus must be providedthat is capable of expandingthe compressed motion picture signal reproducedfrom the compact recording medium. To meet the requirements just described, various motion picture signal compression systems have been proposed that exploitthe correlationbetween andwithin the portions of themotion picture signal representing the pictures constituting the motion picture signal. For example, the motion picture signal compression systemproposedby theMoving Picture ExpertsGroup (MPEG) is widely known. Since the MPEG system has been widely described in various printed publications, a detailed explanation of the MPEG system will not be repeated here. The following descriptionwill refer frequently to a"picture." Since the signal processing techniques described herein relate to processing a motion picture signal representing a motion picture, it is to be understood that the word "picture," as generally used herein, refers to the portion of a motion picture signal that represents a picture of the motion picture. Moreover, a motion picture signal can represent a picture of the motion picture as a frame or a field. Unless stated otherwise, a "picture" means a field or a frame. TheMPEG systemfirst determinesthe differencesbetween thepictures constituting themotion picture signal to reduce the redundancy of the motion picture signal in the time domain. Then, the MPEG system reduces the redundancy of the motion picture signal in the spatial domain by applying orthogonal transform processing to blocks of inter-picture differences in the spatial domain. The MPEGsystem appliesdiscrete cosinetransform (DCT) processing as the orthogonaltransformprocessing. By reducing redundancy in both the time and spatial domains, the motion picture is compressed extremely efficiently. The compressed motion picture signal resulting from the compression process just describedmay then be recorded on arecording medium, or transmitted viaa suitable transmission medium. When the compressed motion picture signal is reproduced from the recording medium, or is received from the transmission medium, the blocks of transform coefficients resulting from the DCT transform are extracted from the compressed motion picture signal. The transform coefficients are processed using an inverse orthogonal transform (an inverse discrete cosine transform (IDCT) in the MPEG system) to recover blocks of inter-picture differences in the course of reconstructing the pictures of the original motion picture signal. An example of the construction of amotion picture signal compressor apparatus based on the MPEG system is shown in Figure 1. In the compressor shown in Figure 1, a digital motion picture signal is fed into the block formatting circuit 101, where it is converted from a standard video format, e.g., from the NTSC standard video signal format, into a block format to provide a blocked motion picture signal. In this, each picture of the motion picture signal is divided in the spatial domain, i.e., horizontally andvertically, intomacroblocks of, e.g., 16 x 16 pixels. Themacroblocks are also sub-divided into blocks of 8 x 8 pixels. The apparatus shown in Figure 1 compresses each picture of the motion picture signal block- by-block until all the blocks constituting the picture have been processed. The apparatus then processes another picture of the motion picture signal, which may or may not be the next picture in the sequence ofpictures constituting themotionpicture. The followingdescription of theapparatus shown in Figure 1, the compression of oneblock ofpixels in one picturewill be described. Theblock of pixels being compressed is the current picture block, which is a block of the current picture. The blocked motion picture signal is delivered to the motion predictor 102. The motion predictor feeds the current picture, including the current picture block SI, block-by-block to the difference block calculating circuit 103. Whenthe differenceblock calculatingcircuit 103 receivesthe currentpictureblockfrom the motion predictor 102, it also receives the matching block S2 corresponding to the current picture blockfrom themotion predictor 102. The matching block is derived from the reconstructed pictures storedin the picturememory block112by thepredictor 113. The difference blockcalculatingcircuit 103 determines the pixel-by-pixel difference between the current picture block SI and its correspondingmatching block S2. The resultingblock of differences, the difference block S3, is fed to the orthogonal transform circuit 104. The orthogonal transform circuit 104, which is normally a discrete cosine transform (DCT) circuit, appliesorthogonal transformprocessing to the difference blockS3, and feedsthe resulting block of transform coefficients to the quantizer 105. The quantizer 105 quantizes the block of transform coefficients to provide a block of quantized transform coefficients. The variable-length coder 106 subjects the block of quantized transformcoefficients from the quantizer 105 to variable- length coding, such as Huffman coding or run length coding, etc. The resulting block of coded transformcoefficients is then fed to, e.g., a digital transmissionpath, via the output buffer 107. A control signal indicating the number of bits stored in the output buffer 107 is fed back to the quantizer 105. The quantizer adjusts the quantizing step size in response to the control signal to prevent the output buffer from overflowing or underflowing. Increasing or decreasing the quantizing step size respectively decreases or increases the number of bits fed into the output buffer. The block of quantized transform coefficients isalso delivered fromthe quantizer 105 to the inverse quantizer 108, which forms part of the local decoder used in the compressor to derive from the quantized transformcoefficients the reconstructed pictures used in the prediction coding. The inverse quantizer 108 inversely quantizes the block of quantized transformcoefficients by performing processing complementary to the quantizing processing performedby the quantizer 105. The resulting block of transform coefficients is fed to the inverse orthogonal transform circuit 109, where it is inversely orthogonally transformedby processing complementary to the orthogonal transformprocessing performedby the orthogonal transformcircuit 104. The resulting restored difference block S4 is fed to the adder 110. The adder 110 also receives the matching block S2 for the current picture block SI from one of the picture memories in the picture memory group 112 selected by the predictor 113. The adder 110 performs pixel-by-pixeladdition between the restored difference block S4 from the inverse orthogonal transform circuit 109 and the matching block S2 from the picture memory group 112 to provide the reconstructed picture block S5. The reconstructed picture block is delivered to one of the picture memories 112A to 112D selected by the selector 111, where it is stored. The reconstructed picture block is stored in the selected picturememory, where it forms one block (corresponding to the current block) of the reconstructed picture being reconstructed, block-by-block, from reconstructedpicture blocks in the selected picture memory. When complete, the reconstructed picture will be used for deriving matching blocks for performing prediction coding to compress other pictures of the motion picture signal. The motion predictor 102 determines, for each macroblock of the current picture, a motion vectorbetween the macroblock of the currentpictures and different macroblocks of the other pictures of the motion picture signal stored therein. The motion predictor also generates a sum of the absolute values of the differences (the "difference absolute value sum") between the pixels in each macroblock of the current picture and the different macroblocks of the other pictures. Each difference absolute value sum indicates the degree of matching between each macroblock of the current picture and themacroblocks of the other pictures. The motion predictor feeds each motion vector and its corresponding difference absolute value sum to the prediction mode determining circuit 115. The prediction mode determining circuit 115 uses the data received from the motion predictor 102 to determine the prediction mode that will be used for prediction coding the current picture relative to one or more other reconstructed pictures. The current picture can be prediction coded using any of the following prediction modes: (1) Intra-picture mode, in which the picture is compressed by itself, without reference to any other pictures. A picture coded in this way is called an I-picture. (2) Forward prediction mode, in which prediction is carried out with reference to a reconstructedpicture occurringearlier in themotion picture. A picture coded in this way is called a P-picture. (3) Bidirectional prediction mode, in which block-by-block prediction is carried out with reference to a reference block derived from a reconstructed picture occurring earlier in the motion picture, a reconstructed picture occurring later in the motion picture, or by performing a pixel- by-pixel linear operation (e.g., an average value calculation) between an earlier reconstructed picture and a later reconstructed picture. A picture coded in this way is called a B-picture. In other words, an I-picture is apicture in which intra-picture coding is completed within thepicture. A P- picture is predicted from areconstructed I-picture or P-picture occurringearlier in the motion picture. A B-picture is predicted block-by-block using an earlier or a later reconstructed I-picture or P-picture or usinga blockobtained by performing a linear operationusing a reconstructed I-picture or P-picture occurring earlier in the motion picture and a reconstructed I-picture or P-picture occurring later in the motion picture. Thepredictionmodedeterminingcircuit 115delivers thepredictionmodeandthe corresponding motion vector to the predictor 113 and to the readout address generator 114. The readout address generator 114 provides readout addresses to the picture memory group 112 in response to the motion vector, whichcauses each picture memory 112A through 112D to read out a block of the reconstructed picture stored therein. The location ofthe read outblockin the reconstructed picture is designated by themotion vector. The predictor 113 selects one of the read outblocks from thepicture memories 112A to 112D in response to the prediction mode signal PM received from the prediction mode determiningcircuit 115. The selected read out block provides the matching block S2 for the current block SI. When the current block is part of a B-picture, the predictor also performs linear operations on the read out blocks rom the picture memories 112A though 112D to provide the required matching block. The predictor delivers the matching block S2 to the difference block calculating circuit 103 and the adder 110. Anexample ofthe constructionof a compressedmotion picture signal expander apparatusbased on the MPEG system is shown in Figure 2. In this, the compressed motion picture signal obtained directly from the compressor or by reproducing it from arecording medium is fedas abit stream into the input buffer 121, where it is temporarily stored. The compressed digital signal includes blocks of coded transform coefficients (including a block of coded transform coefficients representing the current block), andprediction modeinformation, quantizingstep-size information, andamotion vector for each block. The compressed motion picture signal is read out of the input buffer 121 one picture at a time, and is delivered to the inverse variable-lengthcoder (IVLC) 122. The inversevariable-length coder 122 applies inverse variable length coding to the compressed motion picture signal, and separates the compressed motion picture signal into its components, including blocks of quantized transform coefficients, and prediction mode information, step-size information, and a motion vector for each block. Each blockof coded transform coefficients is fed into the inverse quantizer 123, which uses the step-size information for the block to inversely quantize the block of quantized transform coefficients to provide a blockof transformcoefficients. The inverse orthogonal transform circuit 124 applies inverse orthogonal transform processing, normally IDCT processing, to the block of transform coefficients to derive a restored difference block. The inverse quantizer 123 and the inverse orthogonal transform circuit 124 respectively apply processing complementary to that applied by the quantizer 105 and orthogonal transform circuit 104 in the compressor shown in Figure 1. The readout addressgenerator 130provides areadout addressto the picture memories 128A to 128D in response to the motion vector for the current block received from the inverse variable- length coder 122. In response to the readout address, each of the picture memories 128A to 128D reads out a block of the reconstructed picture stored therein. The predictor 129 selects one of the read out blocks from the picture memories 128A to 128D in response to the prediction mode signal PM, also received from the inverse variable-length coder 122. The selected read out block provides the matching block for reconstructing the current block. When the current block is part of a picture coded as a B-picture, the predictor also performs linear operations on the read out blocks from the picture memories 112A though 112D to provide the matching block. The predictor 129 delivers the matching block to the adder 125. The adder 125 performs a pixel-by-pixel addition between the restored difference block from the inverse transform circuit 124 and the matching block from the predictor 129 to reconstruct the current picture block of the current picture. The selector 126 feeds the reconstructed current picture blockfor storage in the one of the picture memories 128A through 128D in which the current picture is being reconstructed. The reconstructed current picture block is stored in the selected picture memory in the position of the current picture block in the reconstructed current picture. When all the reconstructed blocks of the current picture have been stored in the selected picture memory 128A to 128D, the reconstructed current picture is readyfor reading out, and also for use as a reference picture for reconstructing other pictures occurring earlier or later in the motion picture. The reconstructed pictures stored in the picture memories 128A to 128D are read out as the output motion picture signal via the selector 126 in response to readout addresses generated by the display address generator 127. A scan converter (not shown) converts the output motion picture signal read out from the picture memories 128A through 128D to the raster format of the desiredvideo signal format, e.g., NTSC. The resulting output motion picture signal can then be displayed on a suitable display, e.g., a CRT, etc. In this example, the sync, signal generator 131 is locked to an external sync, source, and periodically generates a frame sync, signal for delivery to the display address generator 127. The display address generator 127 the generates readout addresses in synchronism with the frame sync, signal. The orthogonal transform circuits, for example, the DCT and the IDCT circuits used in the compressor and the expander described above, respectively perform arithmetic operations on pixel values and transformcoefficients representedby integers having a finite number of bits. Thus, the orthogonal transform operations performed by the orthogonal transform circuits can result in a truncation of the number of bits. For this reason, a difference in the accuracy of the orthogonal transform operation using real numbers, or a difference in the configuration of the circuit used to perform the orthogonal transform operation, can change the result of the orthogonal transform operation. This can lead to a mismatch between the compressor and the expander, and to mismatches between expanders expanding a common compressed signal. For example, in the compressor, thedifference block derivedfrom the motion picture signal is orthogonally transformed, and predetermined processing is applied to quantize the resulting transform coefficients in the course of generating the compressed motion picture signal. Then, in the expander, if the real number operational accuracy or the configuration of the inverse orthogonal transform circuit does not correspond to that of the compressor, then it is possible the output of the expander will differ from the input to the compressor. Hence, the output of the expander can depend on the accuracy and the configuration of the apparatus used for the expander. The operational accuracy or the configuration of an inverse orthogonal transform may vary dependingupon the apparatusused toperform the inverse orthogonal transform. For example, inversely transforming a blockof transformcoeficients using two different constructionsof the same type of inverse orthogonal transformcircuit mayproduce different results. Such a difference in the results is called an inverse orthogonal transform mismatch error (a "mismatch error"). The MPEG system defines the operational accuracy with which the DCT and the IDCT are to be performed,but doesnot define theoperationalmethod andtheconfiguration. This isbecause circuits andmethods for performing DCTs and IDCTs were developed before the MPEG standards were established. IntheMPEGsystem, as describedabove, the compressor implements,e.g., inter-picturemotion- compensated prediction coding to the motion picture signal. In this, the motion picture signal is dividedinto blocks, adifference blockis derived fromthe currentpictureblock andamatching block obtained by applying motion compensation to a reconstructed picture, the difference block is orthogonally transformed using DCT processing, the resulting transform coefficients are quantized, the quantized transform coefficients are subject to variable-length coding, and the coded transform coefficients are assembled together with prediction mode information, quantizing step size information, and motion vectors to provide the compressed motion picture signal. The expander applies inverse variable-length coding to the coded transform coefficients, inverse quantizing to the quantizedtransform coefficientsresulting from the inversevariable-length coding, and IDCTprocessing to the transformcoefficients resulting from the inverse quantizing. The resulting restored difference block is added to a matching block obtained by applying motion compensationto areconstructedpicture inresponse to themotion vector. The resultingreconstructed picture block is stored as ablock of a reconstructedpicture, which provides apicture of the motion picture output signal, and also is available for use as a reference picture. The compressor includes a local decoder that derives, from the quantized transform coefficients, reconstructedpictures for use in carrying out theprediction coding. The local decoder includes an inverse quantizer and an inverse orthogonal transform circuit. Ifthe configurationof IDCT circuit in the local decoder in the compressoris different from that of the IDCT circuit in the expander, there are instances in which the reconstructed pictures producedby the local decoder inthe compressorare different from the reconstructedpictures produced by the expander. The dependency of the IDCT processing on implementation can causeproblems when the compressed motion picture signal generated by a compressor conforming with the MPEG standard is recorded on a recording medium, such as an optical disc, etc., fordistribution to the public. When the compressed motion picture signal reproduced from the optical disc is expanded by expanders manufactured and soldby different makers, the reproducedpicture may be different from the original picture. Moreover, the differences may depend upon the actual expander used. Similar incompatibilitiesbetweendiferent expandersmayalso occurwhenthe compressedmotion picture signal is distributed by a distribution system such as terrestrial or satellite broadcasting, telephone system, ISDN system, cable or optical distribution system, etc. Mismatcherrorsareparticularlyproblematicalwheninter-picturepredictioncodingiscarried out. Inter-pictureprediction coding canbe inter-field coding or inter-frame coding. Inter-picture prediction coding can cause mismatch errors to accumulate to the extent that they result in fatal flaws in the reconstructed pictures. In the motion picture signal compression performed by the MPEG system, each video sequence is divided into Groups of Pictures (GOPs) of, for example, eight or twelve pictures. Each picture is classified as an I-picture, a P-picture, and a B-picture, as described above. A B-picture is not used as a reference picture in performing motion prediction. Hence, a mismatch error occurring in a B- picture does not lead to errors in other pictures. When a mismatch error occurs in a P-picture, the picture with the mismatch error is stored in the picture memory for use in carrying out prediction coding. Accordingly, when inter-picture prediction coding is carried out, the error in the P-picture stored in the picture memory gradually spreadsto the P-pictures andB-pictures derived from it by prediction coding. The erroraccumulates until the picture is replaced by an I- picture or a P-picture lacking such an error. Similarly, when a mismatch error occurs in an I-picture, the reconstructed picture with the mismatch error is stored in the picture memory for use in carrying out prediction coding. Accordingly, when inter-picture prediction coding is carried out, the error in the I-picture stored in the picturememory spreads to the P-pictures andB-pictures derivedfrom it by prediction coding. The error accumulates until the picture is replaced by a new I-picture lacking such an error. Erroraccumulationis illustratedin Figure 3. In Figure3, if themismatch errorin decoding an I-picture is El, and themismatch error indecoding the P-picture PI is EP1, the value of the error in the reconstructed P-picture PI is EI+EP1. Further, when the mismatch error in decoding the P-picture P2 is EP2, the value of the error in the reconstructed P-picture P2 is EI+EP1+ EP2. Even if the individual mismatch errors are small, the gradual accumulation of these errors will result in a large error. Mismatch errors produced by the IDCT processing used in the MPEG decoders in both the compressor and the expander can be classified into two distinct types: Type (1): Errors resulting from insufficient operational accuracy. Type (2): Errors resulting from systematic differences in rounding. The MPEG standard sets forth a requirement for operational accuracy. However, this requirement is not so stringent that it can guarantee that a mismatch error will not occur. Therefore, a Type (1) mismatch error can occur between IDCT devices whose operational accuracy satisfies the MPEG requirement. The outputs of the IDCT processing are integers. Hence, afterthe IDCT processing has been performed using real numbers, the processing results must be rounded. In general, the processing resultsare rounded to the nearest integer. However, a problem occurs when theprocessing result is *.5, where * is any integer. TheMPEG standard does not define howa processing result of *.5 should be rounded. Some IDCT devices round *.5 up, and other IDCT devices round *.5 down. Further, there are instances in which rounding up or rounding down depends on the sign of the processing result. Mismatch errors resulting from the systematic rounding errors just described are Type (2) mismatch errors. Type (1) mismatch errors differ from Type (2) mismatch errors in that Type (1) errors occur randomly, whereasType (2) errors are systematic. Because Type (1) errorsare random, positive errors and negative errors occur with roughly equal probability. Hence, when prediction coding is carried out over a long time, it can be assumed that Type (1) mismatch errors will cancel out. Ontheother hand, since Type (2) mismatch errorsare systematic, andare inherent in the IDCT processing itself, such errors consistently have the same polarity. Accordingly, when prediction coding is carried out over a long time, the mismatch error will be cumulative in one direction. Although each Type (2) mismatch error is only +1 or -1, if many mismatch errors accumulate in one direction, the cumulative mismatch error will be large. Since Type (1) mismatch errors, although temporarily generated, cancel out over time, Type (1) are relatively unproblematical. On the other hand, since Type (2) mismatch errors accumulate in one direction, Type (2) mismatch errorsare problematical. Because ofthis, itis desirable to prevent cumulative Type (2) mismatch errors from occurring. It has been proposed in the MPEG1 system to perform processing prior to the IDCT processing to prevent Type (2) mismatch errors from occurring. The processing sets the transform coefficients of all the components to an odd value, except for the transform coefficient of the component (0, 0) of a macroblock of an intra-picture coded picture (an "intra macroblock"). In an intra macroblock, the component (0, 0) is the DC component. As shown in Figure 4, for example, the transform coefficients of the components (0, 1), (7, 1), (2, 3), (5, 3), (1, 5), (6, 5), (3, 7), and (4, 7) are initially all 568. Since this is an even number, the pre-processing sets the values of these coefficients to an odd value, e.g., 567. When IDCT processing is applied to the pre-processed transform coefficients, fractional results never occur. Since the DC component of the intra macroblock is very important to the appearance of the picture derived from the compressed motion picture signal, its accuracy is only limited to 8 bits. It is not subject to conversion to an odd value, since this would degrade the accuracy of this important component. On the other hand, all of the transformcoefficients resultingfrom transforming amacroblock of a picture coded using inter-picture coding (a "non-intra macroblock") are subject to processing similar to that of the transform coefficients of the components, other than the DC component, of an intra macroblock to restrict the transform coefficients only to odd values. The processing in which the values of the transform coefficients subject to the IDCT processing are all set to an odd value is called oddification processing. By carrying out oddification processing, the IDCT processing in both the compressor and the expander will both perform rounding in accordance with a common rule. This will make it possible to maintain a consistent picture quality between different expanders. However, despite the above-describedoddification processing, the above-described cumulative Type (2) mismatch errors still occur in MPEG processors because the IDCT processing can still produce results of *.5, where * denotes an integer. The circumstances that lead to a result of *.5 will be described next using as an example the two-dimensional 8 x 8 IDCT used in the MPEG system. The two-dimensional 8 8 IDCT is expressed by the following equation: «M>= 7∑ Σ C(u)C(v)F(u,v) cos ( ( 2x 1 ' ) co S ( y÷D x i. ) ^ u=o v=o 1° -Lo u,v,x,y=0,l, ... ,7 • • • (1) =l(u . v*0) In the above equation, F(u, v) indicates the DCT coefficients subject to the two-dimensional IDCT. In equation (1), each output value of the IDCT is a real number, i.e., a rational number or an irrational number. Because *.5 is a rational number, making the output value of the IDCT an irrational number will prevent a cumulative mismatch error from occurring. On the other hand, when the output value is a rational number, it is possible for the output value to be *.5. The DCT coefficients F(0, 0) F(0, 4), F(4, 0), F(4, 4) are special DCT coefficients. When any one of these DCT coefficients has a non-zero value, the output value of the IDCT is a rational number. The output values of the IDCT in this case are expressed by equation (2). f( χ ,y)= ^ F( O . O ) A f(x,y)= -^ (4,0)cos-^iπ 4 2 f(x.y)= ^F(4,4)co__-^iπcos^^π 4 4 4 where •••(2) Thus, when only one of the special DCT coefficients F(0, 0), F(0, 4), F(4, 0), F(4, 4) hasa non-zero value that is a multiple of 4, but nota multiple of 8, the output value is equal to *.5. When the four special DCT coefficients are the only coefficientswith a non-zero value, the output value of the IDCT is expressed by equation (3). + ( ,4)cos-^^πcos^^iπ ••• (3) 4 4 4 Withdifferent combinations of xandy, f(x,y) in Equation (3) can havethe followingvalues: - [F(0,0)+F(0,4)+F(4,0)+F(4,4)] - [F(0,0)+F(0,4)-F(4,0)-F(4,4)] -i [F(0,0)-F(0,4)+F(4,0)-F(4,4)] (4) ~ [F(0,0)-F(0,4)-F(4,0)+F(4,4)] Thus, when the values of the four special coefficients are such that any of the expressions set forth in equation (4) is multiple of 4 but is not multiple of 8, a result of *.5 will occur. Thus, when the four special coefficients have non-zerovalues, there is highprobability that the output value of the IDCT will be equal to *.5. Also, various symmetricalpairs ofDCTcoefficients withnon-zero values, other than the four special coefficients just discussed, can produce an output value of *.5: (1) when thepair of coefficientsX(2n+1, 2m+l), X(2m+l, 2n+l) have the same non-zerovalues, and the value ismultiple of 4 but not multiple of 8, or (2) when the pair of coefficients X(2n+1, 2n+l), X(8-2n-l, 8-2n-l) have the same non-zero values, and the value ismultiple of 4 but not multiple of 8. In the above expressions, X(i, j) is the transform coefficient of one component of a two-dimensional 8 x 8 DCT. When an actual motion picture signal is compressed by a compressor according to the MPEG system, non-zero DCT coefficients are frequently produced in the patterns just mentioned, which can cause an IDCT output value equal to *.5. Moreover, the values of the four special coefficients are non- zero most of the time. Since the most common cause of a result of *.5 is the pattern of DCT coefficients inwhich thevalues of the four special coefficients arenon-zero, preventing a mismatch error fromoccurring in response to the four special coefficients will substantially reduce the probability of a mismatch error occurring. Theprocessing method by which an intramacroblock and anon-intra macroblock are inversely quantized in MPEG1 is shown in Figure 5. In Figure 5, QAC(i. j) is the (i, j)-th DCT coefficient, Wi(i, j) is the (i, j)-th element of a weighting matrix, mquant is the quantizing coefficient, and rec(i, j) is the (i, j)-th inversely-quantizedDCT coefficient. Theprocessing method iswritten in the syntax of the C programming language. The syntax of this language is set forth in Herbert Schildt, Using Turbo C, Osborne McGraw Hill (1988), especially at pages 83-87. The quantized DCT coefficients are inversely quantized, and the resulting DCT coefficients are then subject to IDCT processing. However, in MPEG1, the DCT coefficients having an even value have +1 or -1 added to them to ensure that the DCT coefficients subject to IDCT processing all have oddvalues. As a result of this operation, when, e.g., only the one of the four special coefficients F(0, 0) has a non-zero value, because a mismatch error occurs when F(0, 0) is multiple of 4 but is not multiple of 8, if the DCT coefficients are processed so that they all have an odd value, the result, when the DCT coefficient is subject to IDCT processing, cannot be equal to *.5. Similarly, when only oneof the others of the four special coefficients F(0, 4), F(4, 0), F(4, 4) hasa non-zero value, a mismatch error will not occur. However, when plural ones of the four special coefficients have a non-zero value, as can be seen from Figure 4, or when pairs of syranetrically arranged coefficients occur, as in cases (1) and (2) mentioned above, making all the DCT coefficients an odd value will not prevent a mismatch error occurring. Hence, the oddificationprocessing of MPEG1 will not prevent acumulative mismatcherror from occurringwhen two or more of theDCT coefficients have a non-zero value. Moreover, the oddification processing of MPEG1 reduces the resolution of the quantizedtransform coefficients by afactor of 2, since transform coefficients with even values are not allowed. This degrades the picture quality. If a high picture quality is required, this is problem. A better way of preventing cumulative mismatch errors than that proposed in the MPEG1 standard is clearly desirable. DISCLOSURE OF THE INVENTION With the above problems of the prior art in view, an object of this invention is to provide a method and an apparatus which effectively prevent cumulative mismatch errors from occurring when transform coefficients are inversely orthogonally transformed, and in which the resolution of the transform coefficients is not degraded. Particularly, an object of this invention is to provide amethod and apparatus forinversely orthogonally transforming transformcoefficients whicheffectively solvethe mismatch error problem. Particularly, an object of this invention is to provide a method and apparatus for pre¬ processing a block of transform coefficients prior to inversely orthogonally transforming the block of transform coefficients so that rounding errors are prevented when the block of transform coefficients is inversely transformed. In addition, an object of this invention is to provide motion picture signal compressor, a compressedmotion picture signal expander, andrecordingmedium foracompressedmotion picture signal in which mismatch errors are eliminated, and the measures to prevent the mismatch error cause as little deterioration of picture quality as possible. The object of this invention contemplates effectively and easily preventing mismatch errors which could not be prevented by the conventional approach. Accordingly, the invention provides a method of processing a set of transform coefficients to provide an error-immune set of transform coefficients for processing by an inverse orthogonal transform. The error-immune set of transform coefficients is immune to rounding errors when subject tothe inverse orthogonal transform. In the method, the transform coefficientsin the set are summed. The parity of the sum (i.e., whether the sum is odd or even) is judged. When the parity of the sum is judged to be even, the parity of one of the transform coefficients in the set is inverted to provide aparity-inverted transformcoefficient. The parity-invertedtransform coefficientmakesthe parity of the sum odd. Finally, the set of transform coefficients including the parity-inverted transform coefficient isprovided as the error-immune set. The invention also provides an apparatus for pre-processing a set of transform coefficients to provide an error-immune set of transform coefficients for processing by an inverse orthogonal transform. The error-immune set of transform coefficients is immune to rounding errors when subject to the inverse orthogonal transform. The apparatus comprises an accumulator. The accumulator receives each of the transform coefficients in the set and provides asum. Aparity judpent circuit receives the sumfrom the accumulator, and judges the parity of the sum. A parity inverting circuit operates when the parity judpent circuit judges that parity of the sum is even, and inverts the parity of one of the transformcoefficients to provide aparity-inverted transform coefficient. The parity-inverted transform coefficientmakes the parity of the sum odd. Finally, a circuit provides the set of transform coefficients including the parity-inverted transform coefficient as the error-immune set. The invention further provides a method of inversely orthogonally transforming a set of transform coefficients without incurring rounding errors. Each of the transform coefficients is represented by a binary number. In the method, the least-significant bit of each of the transform coefficients in the set is determined. The transform coefficients having aleast-significant bit of one in the set are counted to provide a count. Thecount is judged to determine when it is an even number. When the count is judged to be an even number, of the transform coefficients is changed to provide a changed transform coefficient. The changed transform coefficient makes the count an odd number. Finally, the set of transform coefficients including the changed transform coefficient is inversely orthogonally transformed. The invention also provides an apparatus for inversely orthogonally transforming a set of transform coefficients without incurring rounding errors. The apparatus comprises a circuit for summing the transform coefficients to provide a sum and a parity judging circuit that judges the parity of the sum. A sum oddifying circuit operates when the parity judging circuit judges that the parity of the sumis even, and inverts the parity of one of the transform coefficients to provide a parity-invertedtransform coefficient. The parity-inverted transformcoefficient makesthe sum odd. Finally, an inverse orthogonal transformcircuit receivesthe set oftransformcoefficients, including the parity-inverted transform coefficient, from the sum oddifying means. The invention also provides an apparatus for inversely orthogonally transforming a set of transformcoefficientswithout incurring roundingerrors. The apparatuscomprisesaleast significant bit judging circuit forjudging the state of the least-significant bit of each transform coefficient. A counting circuit provides a count by counting those transform coefficients that the least- significant bit judging circuit judges to have a least-significant bit of one. A count judging circuit judges when the countfrom the countingcircuit is an evennumber. Finally, acountoddifying circuitoperateswhen the count judgingcircuit judges that thecount is an even number to change one of the transform coefficients to provide a changed transform coefficient. The changed transform coefficientmakes thecount anodd number. Finally, an inverse orthogonal transformcircuit receives the set of transform coefficients, including the changed transform coefficient, from the count oddifying circuit. The inventionalso provides an apparatusforcompressing amotion picture signal. The motion picture signal including pictures, and each picture is divided into blocks. The apparatus comprises a predictive coder that predictively codes blocks of the motion picture signal by using matching blocks of a reference picture to form difference blocks. A difference block encodercompresses the difference blocksfrom thepredictive coder to form acompressed motionpicture signal. The difference block encoder includes an orthogonal transform circuit that orthogonally transformsthedifference block rom thepredictive codertoprovideblocksof transformcoefficients, and a quantizer that quantizes the blocks of transform coefficients from the orthogonal transform circuit to provide compressed signal blocks. The compressed motion picture signal is derived from the compressed signal blocks. The apparatus also includes a local decoder that expands the compressed signal blocks from the difference block encoder to provide restored difference blocks without incurring rounding errors whenthe compressed signal blocks are inversely orthogonallytransformed. The local decoder includes an inverse quantizerthat inversely quantizes the compressed signal blocks from the difference block encoder to provide blocks of restored transform coefficients. An accumulator sums the restored transformcoefficients in each block of transformcoefficients from the inverse quantizer to provide a sum, the parity of which is judged by a parity judging circuit. A sum oddifier operates when the parity judging circuit judges that the parity of the sum is even to invert the parity of one of the restored transformcoefficients in the blockto provide a parity-invertedtransform coefficient that makes the sum odd. Finally, an inverse orthogonal transform circuit receives the block of restored transform coefficients including the parity-inverted transform coefficient from the sum oddifying means. The inverse orthogonal transform circuit provides the restored difference blocks. The apparatus also includes a predictive decoder that predictively decodes the restored difference blocks from the local decoder to reconstruct picture blocks corresponding to the blocks of the motion picture signal. Finally, the apparatus includes a picture memory which stores the reconstructedpicture blocks from thepredictive decoderas blocks of a reconstructedpicture foruse as a reference picture for predictively coding other pictures of the motion picture signal. In the apparatus just described, the accumulator, parity judging circuit, and sum oddifier in the local decoder may be replaced by a least-significant bit determining circuit that determines the least-significant bit of each of the restored transform coefficients; a counter that provides a countbycounting the restored transformcoefficients in each blockthat havealeast-significant bits of one; a count judging circuit that judges when the count from the counter is an even number; and a count oddifying circuit operates when the count judging circuit judges that the count is an even number to change one of the restored transform coefficients in the block to provide a changed transform coefficient that makes the count an odd number. The invention also provides apparatus for expanding a compressed motion picture signal to provide amotion picture output signal. The compressedmotionpicture signalincludes signal portions each representing a picture of the motion picture output signal. The signal portions include variable-length coded compressed signal blocks. The apparatus comprises an inverse variable-length coder that applies inverse variable-length coding to the variable-length coded compressed signal blocks to provide compressed signal blocks. A decoder expands the compressed signal blocks from the inverse variable-length coder to provide restoreddifference blockswithout incurringroundingerrorswhen thecompressedsignal blocks are inversely orthogonally transformed. The decoder includes an inverse quantizer that inversely quantizes each compressed signal block from the difference block encoder to provide a block of restoredtransformcoefficients. An accumulatorsums the restored transformcoefficientsin theblock of transform coefficients from the inverse quantizerto provide asum, theparity of which is judged by aparity judging circuit. A sum oddifier operateswhen the parity judgingcircuit judges that the parity of the sum is even to invert the parity of one of the restored transform coefficients in the block to provide a parity-inverted transform coefficient that makes the parity of the sum odd. An inverse orthogonal transformcircuit receives the blockof restored transformcoefficients, including theparity-invertedtransform coefficient, from the sumoddifier and provides the restored difference blocks. The apparatus also includes a predictive decoder that predictively decodes the restored difference blocks from the decoder to reconstruct picture blocks, and a picture memory that stores the reconstructed picture blocks from the predictive decoder as blocks of a reconstructed picture. The reconstructed picture is for use as areference picture for predictively decoding other pictures of themotion picture signal. Finally the apparatus includes acircuit that reads themotion picture output signal out from the picture memory. In the expander apparatus just described, the accumulator, parity judging circuit, and sum oddifierin the decoder maybe replacedby aleast-signiicantbit determiningcircuit that determines the least-significant bit of each of the restored transform coefficients; a counter that provides a countby countingthe restoredtransformcoefficients in each blockthat havea least-significantbits of one; a count judging circuit that judges when the count from the counter is an even number; and a count oddifying circuit operates when the count judging circuit judges that the count is an even number to change one of the restored transform coefficients in the block to provide a changed transftffm coefficient that makes the count an odd number. The invention further provides a method of compressing a motion picture signal to provide a compressed motion picture signal. In the method, prediction coding and orthogonal transform processing are applied to blocks of the motion picture signal to provide blocks of transform coefficients from which the compressedmotion picture signal is derived. The blocks of transform coefficientsare sumoddifiedpriorto applyinginverse orthogonal transformprocessing andprediction decoding to provide blocks of a reconstructed picture for use as a reference picture in prediction coding other pictures of the motion picture signal. The invention also provides a method for compressing a motion picture signal to provide a compressedmotion picture signal. In the method, motion between blocks of a picture of the motion picture signal and blocks of a reconstructed picture signal serving as a reference picture is detected, and motion compensation is applied to the reference picture in response to the detected motion to derive matching blocks of the reference picture. The matching blocks of the reference picture are used to apply predictive coding to the blocks of the motion picture signal to provide block of differences. The blocks of differences are orthogonally transformed to provide blocks of transformcoefficients. The compressed signal is derived from the blocks of transform coefficients by applying quantizing and variable-length coding. Prior to applying inverse orthogonal transform processing to the blocks of transform coefficients to provide blocks of restored differences, each blockof transformcoefficients is sumoddified to prevent rounding errors in the inverse orthogonal transformprocessing. Finally, prediction decoding is applied to the blocks of restored differences to provide picture blocks of a reconstructed picture for use as a reference picture in applying predictive coding to other pictures of the motion picture signal. Finally, the invention provides a recording medium on which a compressed motion signal representing a motion picture is recorded. The compressed motion picture signal is derived from a motionpicture signal by applyingprediction coding andorthogonal transformprocessing to blocks of themotionpicture signal toprovideblocks of transformcoefficients fromwhichthecompressedmotion picture signal is derived. The blocks of transform coefficients are sum oddifiedprior to applying inverse orthogonal transform processing and prediction decoding to the blocks of transform coefficientsto provideblocks of areconstructed picture foruse as areference picture in prediction coding other pictures of the motion picture signal. The way in which the invention prevents cumulative mismatch errors will now be described. Examinationof equation (4) showsthat amismatch occurs when the expressions inthe equation produce a result of (2n+l)/2, where n is any integer. Equation (4) can be summarized as: f(x, y) = 1/8 ACC where ACC is the sum of all the coefficients. The most frequent mismatch pattern is: f(x, y) = 1/8 ACC = (2n+l)/2 = l/8(4*(2n+l) From this, it can be seen that, if ACC is made an odd number, a mismatch error will never occur. Accordingly, this invention employs a scheme to inversely quantize the DCT coefficients, and then, prior to the IDCT processing, to calculate the sum of the DCT coefficients. If the sum of DCT coefficients is an even value (i.e., the parity of the sum is even), the parity of one of the DCT coefficientsis changed to make the sumof the DCT coefficients an oddvalue (i.e., tomake the parity of the sum odd). It is sufficient to change the parity of only oneDCT coefficient to oddify the sum of the DCT coefficients. Moreover, the parity of the coefficient that has the least influence on the output value of IDCT can be changed. In other words, this invention, by checking the parity of the sum of the DCT coefficients prior to the IDCT processing, and, if the parity of the sum is even, by changing the parity of one of the DCT coefficients to oddify the sum of the DCT coefficient, effectively prevents mismatch errors from occurring. It must be stressed that, according to the invention it is sufficient to change the parity of only one DCT coefficient to oddif the sum of the DCT coefficients. MPEG1 oddifies all the DCT coefficients, which reduces the resolution of the DCT coefficients subject to IDCT processing by a factorof two. The mismatch errorprevention procedure according to the invention, on the otherhand, oddifies the sum of theDCT coefficients in away that does not substantiallydecrease the accuracies of the input and output values of the IDCT. When the method according to the invention is applied to a motion picture signal compressor, a compressed motion picture signal expander, or an apparatus for transmitting acompressed motion picture signal, degradation of the picture quality is minimized. In addition, when the method according to the invention is applied to the MPEG system, the minimumquantizing step can be 1, in contrast to the priorart method in which theminimum quantizing step was 2. BRIEF DESCRIPTION OF THE DRAWINGS Figure1 is ablockdiagram showing the configuration ofa conventional motionpicture signal compressor apparatus according to the MPEG system. Figure 2 is a block diagram showing the configuration of a conventional compressed motion picture signal expander apparatus according to the MPEG system. Figure 3 illustrates the sequence in which a motion picture signal is compressed in the MPEG system. Figure 4 shows actual examples of the values of DCT coefficients. Figure5 showstheprocessing stepsused toinverselyquantize bothintra macroblocksandnon- intra macroblocks in the conventional MPEG1 system. Figure 6 is a block diagram showing the configuration of a first embodiment of a motion picture signal compressor apparatus according to the invention. Figure 7 illustrates how a block of DCT coefficients is read using zigzag scanning. Figure 8 is a block diagram of a first practical embodiment of the sum oddifying circuit 14 shown in Figure 6. Figure 9 is a flow chart showing the operation of the sum oddifying circuit shown in Figure 8. Figure 10A is a block diagram of a second embodiment of the sum oddifying circuit shown in Figure 6. Figure 10B shows a variation on the second embodiment of the sum oddifying circuit shown in Figure 6. Figure11 is ablockdiagramshowinga irst embodiment oftheparity inverter shown in Figure 8. Figure 12 is a flow chart for explaining the operation of a second embodiment of the above- mentioned parity inverter. Figure13 is ablock diagramof the second embodiment of the above-mentionedparity inverter. Figure 14 is a flow chart for explaining the operation of a third embodiment of the above- mentioned parity inverter.. Figure 15 is ablock diagram of thethird embodiment of the above-mentionedparity inverter. Figure 16 is a flowchart for explaining the operation of a fourth embodiment of the above- mentioned parity inverter. Figure17 is ablock diagramof the fourth embodiment of the above-mentionedparity inverter. Figure 18 is a block diagram of a third embodiment of the sum oddifying circuit shown in Figure 6. Figure 19 is a diagram showing the configuration of the first embodiment of a compressed motion picture expander apparatus according to the invention. Figure 20 is a block diagram of the inverse quantizer and sum oddifier in the compressed motion picture signal expander apparatus shown in Figure 19. Figure21 is atiming chart explaining the operation ofthe above-mentionedinverse quantizer and sum oddifier. Figure 22 is a blockdiagram showing the configuration of a second embodiment of the motion picture signal compressor apparatus according to the invention. Figure 23 is ablock diagram showing a first embodiment of the sum oddifying circuit in the second embodiment of the motion picture signal compressor apparatus shown in Figure 22. Figure 24 is a blockdiagram showing asecond embodiment of the sum oddifying circuit in the second embodiment of the motion picture signal compressor apparatus shown in Figure 22. Figure 25 is ablock diagram showing a third embodiment of the sum oddifying circuit in the second embodiment of the motion picture signal compressor apparatus shown in Figure 22. Figure 26 is ablock diagram showing an embodiment ofthe parityinverter in the sum oddifying circuits shown in Figures 23-25. Figure 27 shows a first variation on the parity inverter shown in Figure 26. Figure 28 shows a second variation on the parity inverter shown in Figure 26. Figure 29 shows a third variation on the parity inverter shown in Figure 26. Figure 30 is a block diagram showing the configuration of a second embodiment of the compressed motion picture signal expander apparatus according to the invention. BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of an inverse discrete cosine transform method, an inverse cosine transformapparatus, amotion picture signal compressorapparatus, a compressed motionpicture signal expander apparatus, a recording medium, and a transmitting apparatus will now be described with reference to the drawings. The invention is applied to a hybrid coding system in which motion compensating prediction coding and discrete cosine transform (DCT) processing are combined. This hybrid coding system is describedin H.261 of ISO-IEC/JTC1/SC2/WG11 (popularly namedMPEG) ofthe Consultative Committee for International Telegraph and Telephone (CCITT), which is an international committee for promulgating standards for, inter alia, compressing motion picture signals, and for compressing motion pictures for storage on a recording medium. The basic configuration of theMPEG hybrid coding system is well known. The report of WG11 includes a useful glossary of the terms used herein. Motion-compensating prediction coding is a method for reducing the redundancy of a motion picture signal by exploiting the correlation of the motion picture signal in the time domain. Motion-compensating prediction of the current picture (i.e., the picture currently being coded) is performedusing another, already decoded, picture of the motion picture as a reference picture. The resulting motion-compensated prediction errors are included in the compressed signal together with amotion vector and a prediction mode, etc. This significantly reduces the amount of information in the compressedmotion picture signal required to represent the current picture. The motion-compensated prediction error signal is compressed using a signal compressor that exploits the spatial correlation of each picture constituting the motion picture. The difference signal compressor typically includes an orthogonal transform circuit, such as a DCT circuit, and a quantizer. The DCT is a form of orthogonal transform that concentrates the signal power in specific frequency components as a result of the intra-picture (frame or field) two-dimensional correlation of the picture. This way, only the concentrated and distributed coefficients are included in the compressed signal, either directly, or after additional compression. This further reduces the amount of information in the compressed motion picture signal required to represent the current picture. The inter-picturemotion-compensating prediction coding maybe carried outbetween frames of themotion picture signal. Alternatively, if the motion picture signal is an interlaced signal, the motion-compensatingprediction coding maybe carriedout between fields. In addition, inter-picture motion-compensatingpredictioncoding maybeadaptively switchedbetween inter-frame coding and inter- field coding depending upon the properties of the motion picture signal. 1. First Embodiment The practical configuration of the motion picture signal compressor apparatus to which the invention is applied is shown in Figure 6. In the apparatus shown in Figure 6, the motion picture signal is divided into pictures, and is compressed picture-by-picture. Each picture is divided into pictureblocks, andthepicture iscompressed block-by-block. Thepictureblock beingcompressed will be called the current picture block. The current picture block is a block of a picture called the current picture. Themotion picture signal, normally a video signal, is delivered to the firstpicture memory group 2, where plural pictures of the motion picture signal are temporarily stored. The memory controller 3 controls the reading of pictures from the first picture memory group 2 and the second picturememory group4. Thememory controller 3 also deliversthe slice start signal SSand themacro blockstart signal BS to the slice/macroblockcounter 5. Thememory controller respectively delivers these signals synchronously with each slice and each macroblock of each picture (e.g., the current picture) read out of the first picture memory group 2 for compression. A slice is a horizontal row of blocks covering the width of the picture. Themotion predictor 6 carriesout motion predictionby performing blockmatching betweenthe current picture block and multiple blocks of the prior and following pictures stored in the first picturememory group 2. The block matching is performed using blocks of, e.g., 16 x 16 pixels. The motion prediction reference picture indication signal generated by the memory controller 3 selects theblocks of the prior andfollowing pictures stored in the firstpicture memory group 2to be block matched with the current block. The motion predictor 6 then delivers to the motion compensator 7, as the motion vector MV, the position of ablock in one of the prior or following pictures stored in the first picture memory group for which the differences between the block and the current picture block, i.e., the motion prediction error, are minimum. In response to the motion vectorMV, the motion compensator 7 causes a block of each of the reconstructedpictures stored inthe second picturememory group4 to be read out apotential matching block. The position in the reconstructed pictures fromwhich the potential matching blocks are read is specified by the motion vector MV. The motion compensation reference picture indication signal from the memory controller 3 then selects one of the potential matching blocks read out rom the secondpicturememory group 4 as the matching blockfor the current block. The reconstructed pictures stored in the second picture memory group 4 are pictures that have been reconstructed by locally decoding the quantized DCT coefficients generated by the difference block encoder 9, which will be described below. The reconstructedpicture fromwhich the matching block isselected bythe motion compensation reference picture indication signal depends on the prediction mode of the current picture. In the forward prediction mode, the matching block is selected from a prior reconstructed picture. In the bidirectional prediction mode, the matching block is selected from a prior reconstructed picture, a future reconstructed picture, or can be generated by performing a linear operation (e.g., average value calculation) on blocks of a prior reconstructed picture and a future reconstructed picture. Finally, when the current picture is coded in the intra-picture coding mode, i.e., the picture is codedwithout prediction, a zero block, in which all the pixel values are set to zero, is used as the matching block. The matching blocks read out from the second picture memory group 4 are adaptively modifiedso that an optimally-matching matchingblock isselected for each blockof themotion picture signal. The motion compensator 7 selects the prediction mode for each picture by first calculating the sum of the absolute values of the pixel-by-pixel differences between the current picture block andpotential matching blocks generated in the different prediction modes. Then, motion compensator selects the prediction mode for which this sum is a minimum. The motion compensator feeds the prediction mode signal MM, which indicates the selected prediction mode, to the variable-length coder 17, which will be described below. The motion compensator 7 also causes the second picture memory group 4 to feed the matching block S2 for the selected prediction mode to the difference generating circuit 8. The difference generating circuit 8 also receives the current picture block SI of the motion picture signal read out from the first picture memory group 2, and calculates the pixel-by-pixel difference between the current picture block SI and the matching block S2. The difference generating circuit feeds the resulting difference block S3 to the difference block encoder 9. The difference block encoder 9 compresses the difference block S3 to form the block of quantized transform coefficients SC. The blockof quantizedtransform coefficients SC is fed into the local decoder 10, where it is expanded to provide the recovered difference blockS4. The local decoder 10 in the motion picture signal compressor apparatus has a configuration similar to the compressed motion picture signal expander apparatus, to be described below, but differs in detail. The difference block encoder 9 and the local decoder 10 will now be described. The difference block encoder 9 comprises the DCT circuit 11 and the quantizer 12, as shown in Figure 6. The DCT circuit 11 uses DCT processing to orthogonally transform the difference block S3 from the difference block generating circuit 8. The DCT circuit 11 feeds the resulting block of DCT coefficients to the quantizer 12. The quantizer 12 quantizes the block of DCT coefficients to provide the block of quantized DCT coefficients SC. The local decoder 10 comprises the inverse quantizer 13, the sumoddification circuit 14 and the IDCT circuit 15, as shown in Figure 6. The inverse quantizer 13 uses a quantizing table to inversely quantize the blockof quantizedDCT coefficientsSC from the quantizer 12. The oddification circuit performs a parity inversion operation on the resulting blockof DCT coefficients when the sum of the DCT coefficients is not an odd number. This prevents amismatch error from an occurring when the block of sum-oddified DCT coefficients is inversely orthogonally transformed. The IDCT circuit 15 performs inverse discrete cosine transform (IDCT) processing on the sum-oddified block of DCT coefficients from the oddifying circuit 14 to provide a recovered difference block. The quantizing performed by the quantizer 12 will now be described. Each block of 8 x 8 DCT coefficients is quantized. Each block of apicture compressed in the intra-picture coding mode (an I-picture) is called an intra macroblock. Each block compressed in a inter-picture coding mode is called a non-intra macroblock. When an intra macroblock is orthogonally transformed, the DCT coefficient of the (0, 0) component is the DC coefficient. The DC coefficient is quantized by dividing, with rounding, the DC coefficient by 8 when quantizing with 8-bit accuracy, by 4 when quantizing with 9-bit accuracy, by 2 when quantizing with 10-bit accuracy, and by 1 when quantizing with11-bit accuracy. The DC component of an intramacroblock is quantizedaccording to the following equations, which are written in the syntax of the C programming language: QDC = dc // 8 (8 bits) DC = dc // 4 (9 bits) DC = dc// 2 (10 bits) ••• (5) QDC = dc // 1 (11 bits) where dc is the DC coefficient and QDC is the quantized DC coefficient. The DCT coefficients, other than the DC coefficient, resulting fromorthogonally transforming an intramacroblock (the "AC components"), are quantized by determiningthe quantizing factors ac " (i, j) by weighting theDCT coefficients ac(i, j) by the weighting matrix Wi according to the following equation: ac " (i,j) = (16 * ac(i.j)) // Wi(i.j) ••• (6) The coefficients of the weighting matrix Wi are as follows: Wi = 816192226272934 1616222427293437 1922262729343438 2222262729343740 2226272932354048 ••• (7) 2627293235404858 2627293438465669 Then, using the following equation, the quantizing factors ac " (i, j) are quantized to determine the quantizing levels QAC(i, j) of the respective AC coefficients. Q A C( i , j ) - ac ~ ( i , j) +sign (ac- (i , j) ) * ( (p*mquant) //q) (2 *mguant) In the above equation, p and q are arbitrary fixed integers, for example, p=3 and q=4, and mquant is the quantizing coefficient. The DCT coefficients resulting from orthogonally transforming an inter-picture coding macroblock (a "non-intra macroblock") are quantized by determining the quantizing factors ac " (i, j) by weighting all the DCT coefficients obtained by transforming the non-intra macroblock by the weighting matrix Wn according to the following equation: ac " (i,j) = (16 * ac(i,j)) // Wn(i,j) ••• (9) The coefficients of the weighting matrix Wn are as follows: Wn = 1617181920212223 1718192021222324 1819202122232425 1920212223242627 2021222325262728 ••• (10) 2122232426272830 2223242627283031 2324252728303133 Then, using the following equation, the quantizing factors ac " (i, j) are quantized to determine the quantizing levels QAC(i, j) of the AC coefficients. QAC(i.j) = ac " (i,j) / (2*mquant) if (mquant=odd) = (ac " (i,j)+l / (2*mquant) if (mquant=even AND ac-.O) ••• (11) = (ac~(i,j)-l / (2*mquant) if (mquant=even AND ac->0) The resulting quantizing levels QAC(i, j) are fed to the variable-length coder 17 and to the local decoder 10 as the above-described block of quantized DCT coefficients SC. The variable-length coder 17 applies variable-length coding to the block of quantized DCT coefficients obtained by quantizing the block of DCT coefficients. The variable-length coder 17 determines differences between the quantized transform coefficients in the four luminance blocks constituting each macroblockand the DC coefficient of the respective intra macroblock. The variable length coder then uses a variable- length coding table to apply variable-length coding to the resulting difference values. This technique exploits the high correlation between the four adjacent luminance blocks, which means that the DC coefficients have substantially the same value. The variable-length coder 17 also determines the differences between the quantized coefficients of the two color difference blocks, and uses a variable-length coding table to apply variable-length coding to the resulting difference values. The variable-length coding table forthe luminance coefficients and that for the color differences are different from one another. The variable-length coder 17 applies variable-length coding to the block of quantized DCT coefficients by reading the block of quantized DCT coefficients in zigzag scan order, starting with the DCT coefficient of the component (0, 0), as shown in Figure 7. The block of quantized DCT coefficients is read in zigzag scan order because the non-zero DCT coefficients resulting from the DCTprocessing are generallyconcentrated in the vicinity of the (0, 0) component. Thus, readingthe DCT coefficients in zigzag scan order increases the efficiency of the variable-length coding by increasing the run of consecutive zero DCT coefficients read between each non-zero DCT coefficient. Thevariable-length coder 17 reads theDCT coefficients in zigzag scan order, and determines the value (in other words, the level) of each non-zero DCT coefficient, and the number (in other words, the run) of zero DCTcoefficients preceding it. This performs two-dimensional variable-length coding of the block ofDCT coefficients. After coding, the coefficients in the block are expressed by a number of run and level pairs. The variable-length coder also adds a 2-bit code, EOB, that indicatesthe non-zero DCTcoefficient that is the last non-zeroDCT coefficient. Thevariable-length coder 17 delivers to an address converter (not shown) the address of the last non-zero coefficient in zigzag scan order. The address converter converts the address in zigzag scan order to an address, E0B_adrs, in raster scan order. The variable-length coder feeds the address EOB_adrs to the sum oddification circuit 14. The sum oddification circuit 14 stores the address EOB_adrs in raster scan order in the register 25 shown, for example in Figure 8, which will be described below. The inverse quantizer 13 will nowbe described. The inverse quantizer 13 receives the block of quantizedDCT coefficients SC from the difference block encoder 10, inversely quantizesthe block of quantized DCT coefficients to provide a block of DCT coefficients. In practice, the inverse quantizer 13 inversely quantizes the quantized DC coefficients resulting from orthogonally transforming an intra macroblock using theprocessing definedin equation (12) to provide respective DCcoefficients. The inverse quantizer 13 alsoinversely quantizestheAC coefficients resultingfrom orthogonallytransforming an intramacroblockusing theprocessingdefined inequation (13). Finally, the inverse quantizer 13 inversely quantizes all the quantized coefficients resulting from orthogonally transforming a non-intra macroblock using the processing defined in equation (14). rec(0, 0) = 8 * QDC rec(0, 0) = 4 * QDC (9 bits) rec(0, 0) = 2 * QDC (10 bits) ••• (12) rec(0, 0) = 1 * QDC (11 bits) rec(i, j) = (mquant * 2 * QAC(i, j) * Wi(i, j)) / 16 if(QAC(i, j) == 0) rec(i, j) = 0 •■• (13) if(QAC(i,j) > 0) rec(i.j) = ((2*QAC(i,j)+l) mquant*Wn(i,j))/16 if(QAC(i,j) < 0) rec(i.j) = ((2*QAC(i,j)-l)*mquant*Wn(i,j))/16 if(QAC(i,j) =0) ••• (14) rec(i.j) = 0 The resulting block of DCT coefficients is fed from the inverse quantizer 13 to the sum oddifying circuit 14, a practical example of which is shown in Figure 8. The sum oddifying circuit 14 comprises the accumulator 23A, the parity judpent circuit 21, and the parity inverter 28. The accumulator 23A determines the sum of the DCT coefficients in the blockof DCT coefficients received from inverse quantizer 13. The parity judgment circuit 21 judges whether the sum of DCT coefficients determined by the accumulator 23A is an odd number or an even number, i.e., whether the parity of the sum of the DCT coefficients is odd or even. Only when the parity judpent circuit judges that the parity of the sumof the DCTcoefficients is even, the parity inverter 28changes theparity of at least one of the DCT coefficients in the block to make the parity of the sum of the DCT coefficients odd, i.e., the sum of the DCT coefficients is oddified. This prevents amismatch error from occurringwhen the blockof sum-oddified DCT coefficients from the sum oddification circuit 14 is inversely orthogonally transformed by the IDCT circuit 15. The counter 20 counts the number of DCTcoefficients received from the inverse quantizer 13, and feeds the resulting count coeff_adrs to the parity judpent circuit 21 and to the memory selector 22. The accumulator 23A comprises the adder 23 and the register 24. The adder 23 adds each DCT coefficient in a block of DCT coefficients received from the inverse quantizer 13 to the sum of the already-received DCT coefficients in the block stored in the register 24. The register 24 is reset after the sum hasbeen determined for each block of DCT coefficients. The resulting sum of the DCT coefficients is fedfrom the adder 23 to the register 24, and to the parity judpent circuit 21. The accumulator 23A need only sum the least significant bits of the DCT coefficients in the block to provide a result suitable forthe parity judpent circuit to judge whether the parity of the sum of the DCT coefficients is odd or even. The parity judpent circuit 21 judges whether theparity of the sum of the DCT coefficients in the block of DCT coefficients is odd or even in response to the count value coeff_adrs received from the counter 20. When all the DCT coefficients in the block have been delivered to the accumulator 23A, the value of coeff_adrs indicates that the accumulator 23A has determined the sum of all the DCT coefficients in the block. In response to the count value coeff_adrs, the parity judpent circuit 21 judges whether theparity of the sumof the DCT coefficients from the accumulator 23A is odd or even. For example, in the case of a two-dimensional 8 x 8 DCT transform, the parity judpent circuit 21 judges whether theparity of the sumof theDCT coefficients from the accumulator 23A is odd or even when the value of coeff_adrs indicates that all 64 DCT coefficients in the block have been delivered to the accumulator 23A. In practice, for example, when each DCT coefficient is represented by a binary number, the parityjudpent circuit 21 examines the least-significant bit (LSB) of the sumof theDCT coefficients received from the accumulator 23A. An LSB of zero indicates that the parity of the sum is even. In this case, the parity judpent circuit 21 feeds the processing request signal REQ1 to the parity inverter 28 to cause the parity inverter to carry out a parity inversion operation. In response to theprocessing requestsignal REQ1, theparity inverter 28 changes the parity of at least one (i.e., an oddnumber) of the DCTcoefficients to oddify the sum of the DCTcoefficients. On the otherhand, an LSBof one indicates that the parity of the sum is odd. In this case, the parity judpent circuit 21 does not provide theprocessing request signal REQ1, andthe parity inverter 28 leaves the parity of all the DCT coefficients in the block unchanged. Inthe practical circuit shown, the DCTcoefficients from the inverse quantizer 13are stored in the first memory 26 or the secondmemory 27 via the memory selector 22. The memory selector 22 operates in response to the count value coeff_adrs received from the counter 20. Thus, for example, when the memory selector 22 determines that all the DCT coefficients in the block have been stored in the first memory 26, the memory selector specifiesthe secondmemory, so that theDCT coefficients of the next block are stored in the second memory 27. Thus, consecutive blocks of DCT coefficients are stored alternately in the firstmemory 26 andthe secondmemory 27. When all theDCT coefficients in the block have been stored in the either the first memory 26 or the secondmemory 27, the memory inwhich allthe DCT coefficients in theblock is stored feeds thememory full signal FULL1 or FULL2 to the parity inverter 28. When the parity inverter 28 receives memory full signal FULL1 or memory full signal FDLL2, it feeds the read enable signal RD_EN1 or RD_EN2 to the memory that provided the memory full signal. This causes the block of DCT coefficients to be fed from the memory that generated the memory full signal to the parity inverter. The parity inverter operates on the block of DCT coefficients read out from the memory in one of two ways, depending on whether the parity judgment circuit 21 has generated the processing request signal REQ1. When the parity inverter 28 receives the processing request signal REQ1, it inverts the LSB of one of theDCT coefficients in the block, forexample, the last non-zero coefficient in zigzag scan order. The parity inverter identifies the DCT coefficient whose parity may be inverted using the address of the DCT coefficients whose parity may be inverted storedin the register 25. Forexample, Figure 8 showsthe address of the last non-zero coefficient, EOB_adrs, fed into the comparator 62. Hence, in this example, the DCT coefficient whose parity may be inverted is the last non-zero coefficient. When the parity inverter 28 inverts the parity of the DCT coefficient whose parity may be inverted, the parity of the sum of non-zero coefficients in the block from first to last is made odd. The parity inverter 28 feeds all the DCT coefficients other than the DCT coefficient with its LSB inverted to the IDCT circuit 15 with the state of their LSBs unchanged. The parity inverter 28 also feeds the DCT coefficient whose parity may be inverted to the IDCT circuit with the state of its LSB depending on whether the parity inverter received the request processing signal REQl. The parity inverter 28may be providedusing acomputer or digital signal processor operating in accordance with the flow chart shown in Figure 9, for example. In this example, the DCT coefficient whose parity may be inverted is the last non-zero coefficient. At step SI, the parity inverter 28 judges from the address E0B_adrs whether or not the DCT coefficient being processed is the DCT coefficient whose parity may be inverted by inverting its LSB. If the result at step SI is YES, execution proceeds to step S2. Otherwise, executionproceeds to step S5, which willbe described below. At step S2, the parity inverter 28 determines whether the processing request signal REQl has been received. If the result at step S2 is YES, indicating that the processing request signal REQl hasbeen received, executionproceeds to step S3. Otherwise, no processing request hasbeen received, and execution proceeds to step S5. At step S3, the parity inverter 28 inverts the LSB of the DCT coefficient whose parity may be inverted to invert itsparity, and hence to change the parity of the sumof theDCT coefficients. Execution passes to step S4, where the parity- inverted DCT coefficient is fed to the IDCT circuit 15 (Figure 10A). Then, execution returns to step SI, where the next DCT coefficient is processed. Execution passes to step S5 when the DCT coefficient being processed is not the DCT coefficient whose parity may be inverted, or when the DCT coefficient whose parity is to be inverted is not to have its parity inverted, i.e., when the processing request signal REQl has not been received. At step S5, the DCTcoefficient is fed to the IDCT circuit 15 without modification. Then, execution returns to step SI, where the next DCT coefficient is processed. When the DCT coefficients are represented by a 2's complement representation, the above-mentionedLSB is the LSB of the 2'scomplement representation. On the other hand, when the DCT coefficients are represented by a sign and an absolute value, the above-mentioned LSB is the LSB of the absolute value. The configuration of the sumoddifying circuit 14 is not limited to that shown in Figure 8. For example, in the sum oddifying circuit shown in Figure 10A, the LSB detector 29 is added, and the exclusive-OR gate 30 is substitutedfor the adder 23 in the sum oddifying circuit shown in Figure 8. Elements in the circuit shown in Figure 10A corresponding to those in the circuit shown in Figure 8 are indicated by the same reference numerals, and will not be described again here. In Figure 10A, the LSB detector 29 detects the LSB of each DCT coefficient in the block of DCT coefficients. The exclusive- OR gate 30 performs an exclusive-OR operation between each DCT coefficient in the block andthe exclusive logical sum, stored in the register 24, of the LSBs of the DCTs in the block that have already been processed. Thus, the exclusive-OR gate 30 and the register 24 derive the exclusive logical sum of the LSBs of the DCT coefficients in each block. The combination of the exclusive-OR gate 30 and the register 24 may also be regarded as counting the DCT coefficients having an LSB of one. Then, when all the DCT coefficient in the block have been received, the state of the output of the exclusive-OR gate 30 indicates to whether the count of the DCT coefficients having an LSB of one is odd or even. The parity judpent circuit 21 then issues the processing request signal REQl when the count of the DCT coefficients having an LSB of one is even. Figure 10B shows an alternative configuration that can be substituted for the exclusive-OR gate 30 and the register 24. In this, the LSBs of each DCT coefficient received from the inverse quantizer 13 is fedfrom the LSB detector 29 to the AND gate 88. The AND gate passes only those LSB's that are a one to the counter 89. The counter is reset at the beginning of each block of DCT coefficients, and counts each LSB of one that it receives. The LSB of the count COUNT from the counter 89 is fed to the parity judpent circuit 21. At the end of each block, the parity judgment circuit determines the parity of the LSB of the count COUNT from the counter 89. If the parity of the count COUNT is odd (i.e., the LSB of COUNT is aone), this indicates that there are an odd number of DCT coefficients with an LSB of one in the block, and that the parity of the sum of the DCT coefficients in the block is odd. On the other hand, if the parity of the count COUNT is even (i.e., the LSB of COUNT is a zero), this indicates that there are an even number of DCT coefficients with an LSB of one in the block, and that the parity of the sum of the DCT coefficients in the block is even. Apractical configuration of afirst embodiment ofthe parity inverter 28 in the sumoddifying circuits shown in Figures 8 and 10A will now be described with reference to Figure 11. The parity inverter 28 comprises the readout counter 61, the address comparator 62, the LSB inverter 63, the AND gates 64, 65, 67, and 68, the OR gates 66 and 69, and the inverters 71 and 72. The parity inverter 28 operates as follows. When the readout counter 61 receives the memory full signal FULL from the firstmemory 26 or the second memory 27, it delivers the read enable signal RD_EN to the first memory 26 or the second memory 27. The read enable signal causes the respective memory to sequentially feed the DCT coefficients in the block of DCT coefficients stored therein to the first AND gate 67 via the path marked RDATA. The memory full signal FULL also causes the readout counter 61 to start counting the DCT coefficients received, and to provide to the comparator 62 acount value indicating the number of DCT coefficients received. The comparator 62 compares the count valuewith the address received from the register 25 to determine whether the DCT coefficient received by the first AND gate 67 is the DCT coefficient whose parity may be inverted, i.e., the DCT coefficient whose LSB may be inverted. In the example shown in Figure 11, the DCT coefficient whose parity may be inverted is the last non-zero DCT coefficient, identified by the address EOB_adrs stored in the register 62. When the count value equalsthe address of the DCT coefficient whose parity may be inverted, inthis example, the EOB_adrs, the comparator 62 determines that the DCT coefficient is the DCT coefficient whose parity may be inverted, and changes the state of its output from a 0 to a 1. The output of the comparator 62 is fed directly to the second AND gate 68, and, via the inverter 72, to the first AND gate 67. Thus, when the count value is not equal to the address EOB_adrs, the first AND gate 67 is open, and the second AND gate circuit 68 is closed. Hence, the DCT coefficients pass unchanged through the first AND gate 67 and the OR gate 69 to the IDCT circuit 15. On the other hand, when the DCT coefficient delivered to the parity inverter 28 is the DCT coefficient whose parity may be inverted, and the count value equals the address of the coefficient whose parity may be inverted, in this example, E0B_adrs, the output of the comparator 62 changes state, as described above. This closes the first AND gate 67 and opens the second AND gate 68. As a result, the DCT coefficient with its LSB inverted received via the OR gate 66 is fed viathe second AND gate 68 and the OR gate 69 to IDCT circuit 15. The DCT coefficientwith itsLSB inverted is selectively deliveredto the IDCT circuit 15 in response to the processing request signal REQl by feeding the DCT coefficients received on the path RDATA into the third AND gate 64 andthe LSB inverter 63. The processing request signal REQl is fed from the parity judpent circuit 21 directly to the fourth AND gate 65, and, via the inverter 71, to the third AND gate circuit 64. The LSB inverter 63 inverts the LSB of each DCT coefficient received onthe path RDATA and feeds the resulting DCT coefficient with its LSB inverted to the fourth AND gate 65. Absence ofthe processing request signal REQl, i.e., the processingrequest signal in its zero state, indicatesthat the DCT coefficient whose parity may be inverted is to be deliveredto the IDCT circuit without itsLSB inverted. The processing request signal in its zero state the thirdAND gate 64 and closes the fourth AND gate 65. This feeds the DCT coefficient whose parity may be inverted with its LSB unchanged from the path RDATA to the IDCT circuit 15 via the third AND gate 64, the OR gate 66, the second AND gate 68 and the OR gate 69. On the other hand, presence of the processing request signal REQl, i.e., the processing request signal REQl in its one state, indicates that the DCT coefficient whose parity may be inverted is to be delivered to the IDCT circuit with its LSB inverted to change the parity of the sum of the DCT coefficients. The processing request signal in its one state closes the third AND gate 64 and opens the fourth AND gate circuit 65. This feeds the DCT coefficient whose parity may be inverted with itsLSB inverted from the LSB inverter 63 to the IDCT circuit 15 viathe fourth AND gate 65, the OR gate 66, the second AND gate 68, and the OR gate 69. A second embodiment of the parity inverter 28 will nowbe described with reference to Figure 12. When the second embodiment of the parity inverter 28 receives the processing request signal REQl, it oddifies the sum of the DCT coefficients by adding 1 to DCT coefficient whose parity may be inverted. The second embodiment of the parity inverter 28 may be provided by a computer or digital signalprocessor operating in accordance with the flow chart shown in Figure 12. The flow chart shown in Figure 12 is similar to the flow chart shown in Figure 9, except for the operation carried out at step S3. At step S3, the second embodiment of the parity inverter 28 oddifies the sum of the DCT coefficients by adding 1 to the DCT coefficient whose parity may be inverted, instead of inverting the LSB of the DCT coefficient whose parity may be inverted. The DCT coefficient whose parity may be inverted may be, for example, the last non-zero coefficient in the block, or the DCT coefficient of the highest-frequency component in the block. Apractical circuit configuration of the second embodiment of the parity inverter, in which one is added to the DCT coefficient whose parity may be inverted to oddify the sum of the DCT coefficients in the block of DCT coefficients, will now be described with reference to Figure 13. The second embodiment of the parity inverter shown in Figure 13 is similar to the first embodiment of the parity inverter 28 shown in Figure 11. Elements in the circuit shown in Figure 13 correspondingto those in the circuit shown in Figure11 are indicatedby the same reference numerals, and will not be described again here. Theparity inverter shown in Figure 13 includes the +1 adder 73 in lieu of the LSB inverter 63 shown in Figure 11. The +1 adder 73 adds one to each DCT coefficient read out from the first memory 26 or from the secondmemory 27 and received viathe path RDATA. One of the DCT coefficients with one addedto it is selected in response to the processing request signal REQl to oddify the sum of the DCT coefficients. Operation of the parity inverter shown inFigure 13 is identical to thatof the circuit shown inFigure 11, except that the +1 adder 73 adds one to each DCT coefficient receivedon the path RDATA. Also, when the processing request signal REQl is present, and the DCT coefficient whose parity may be inverted is detected, theDCT coefficient with one addedto it is fedfrom the +1 adder to the IDCT circuit 15 via the fourth AND gate 64, the OR gate 66, the second AND gate 68, and the OR gate 69. A third embodiment of the parity inverter 28 will now be describedwith reference to Figures 14 and 15. Whenthe thirdembodiment ofthe parity inverterreceives theprocessing request signal REQl, itoddifies the sumof the DCT coefficientsin the blockby replacing the DCT coefficient whose parity is to be inverted with the DCT coefficient whose parity is to be inverted from which one has subtracted when the sign of the DCT coefficient is positive, and to which one hasbeen addedwhen the sign of the DCT coefficient is negative. This processing not only inverts the parity of the DCT coefficient whose parity is to be inverted, but also reduces the magnitude of this DCT coefficient, i.e., makes the DCT coefficient whose parity is tobe inverted closer to zero. The processing applied to the DCT coefficient whose parity is to be inverted is defined by the following equation: if(rec > 0) rec = rec - 1 if(rec < 0) ••• (15) rec = rec + 1 where rec is the DCT coefficient whose parity is to be inverted. The third embodiment of the parity inverter 28 may be provided using a computer or digital signal processor operating according to the flow chart shown in Figure 14. At step SI, parity inverter28 judges from the addressEOB_adrs whether ornot theDCT coefficient is theDCT coefficient whose parity may be inverted. For example, the parity inverter judges whether or not the DCT coefficient is the last non-zero DCT coefficient. If the result at step SI is YES, and the DCT coefficient is the DCT coefficient whose parity may be inverted, execution proceeds to step S2. Otherwise, andthe DCTcoefficient is not the DCT coefficient whose parity may be inverted, execution proceeds to step S8. At step S2, the parity inverter 28 determines whether or not the processing request signal REQl has been received. If the result at step S2 is YES, indicating that the processing request signal REQl has been received, execution proceeds to step S3. Otherwise, no processing request has been received, and execution proceeds to step S8. Since a YES result at step S2 can only occur if aYES result is obtained at step SI, the YES result at step S2 indicates that the DCT coefficient is the DCT coefficient whose parity is to be inverted. Atstep S3, theparity inverter 28determines thepolarity oftheDCT coefficientwhoseparity is to be inverted. If the result at step S3 is YES, indicating that the polarity of the DCT coefficient is positive, execution proceeds to step S4. Otherwise, the polarity of the DCT coefficient is zero or negative, and execution proceeds to step S6. At step S4, the parity inverter 28 subtractsone from the DCT coefficient whose parity is to be inverted (i.e., adds -1 thereto), after which execution passes to step S5, where the parity-invertedDCT coefficient is fed to the IDCT circuit 15 (Figure 10A). Then, execution returns to step SI, where the next DCT coefficient is processed. Otherwise, at step S6, the parity inverter 28 adds one to the DCT coefficient whose parity is to be inverted, after which execution proceeds to step S7, where the parity-inverted DCT coefficient is fed to the IDCT circuit 15. Then, execution returns to step SI, where the next DCT coefficient is processed. Executionpasses to step S8 when theDCT coefficient is not the DCT coefficientwhose parity may be inverted, or when the DCT coefficient whose parity may be inverted is not have its parity inverted, i.e., when the processing request signal REQl has not been received. At step S8, the DCT coefficient is fedto the IDCT circuit 15 without modification. Then, execution returns to step SI, where the next DCT coefficient is processed. Figure 15 shows a practical example of the circuit configuration of the third embodiment of the parity inverter 28, in which the parity inversion is carried out to reduce the magnitude of the DCT coefficient whose parity is inverted, i.e., to make the DCT coefficient whoseparity is inverted closer to zero. The parity inverter shown in Figure 15 is similar to the parity inverter 28 shown in Figure 11. Elements in the circuit shown in Figure 15 correspondingto those in the circuit shown in Figure 11 are indicated by the same reference numerals, and will not be described again here. The parity inverter shown in Figure 15 differs from the parity inverter shown in Figure 11 in that it includes the magnitude reduction circuit 80 in lieu of the LSB inverter 63. The magnitude reduction circuit 80 determines the polarity of each DCT coefficient received from the first memory 26 or the second memory 27 via the path RDATA. When the polarity of the DCT coefficient is positive, the magnitude reduction circuit subtracts one from the DCT coefficient, whereas, when the polarity of the DCT coefficient is zero or negative, it adds one to the DCT coefficient. Theparity inverting circuit shown in Figure 15 oddifies the sumof the DCT coefficients in the block by selecting the DCT coefficient whose parity is inverted from the magnitude reduction circuit 80, and substituting the magnitude-decreased, parity-inverted DCT coefficient for the DCT coefficient whose parity is to be inverted. The magnitudereductioncircuit 80 comprisesthe polarityjudgement circuit 81, which controls the fifth AND gate 84 directly, and the sixth AND gate 85 via the inverter 87. The magnitude reduction circuit 80 also includes the -1 subtractor 82 andthe +1 adder 83 that respectively subtract one from and add one to each DCT coefficient received on the path RDATA. Either the output of the -l subtractor 82 or the output of the +1 adder 83 is selected by the fifth AND gate 84 or the sixth AND gate 85 in response to the output of the polarity judpent circuit 81. The outputs of the AND gates 84 and 85 feed the OR gate 86, which provides the selected magnitude-reduced DCT coefficient to the fourth AND gate 65. When theparity of the sum of the DCT coefficients in the block needs to be inverted, the fourth AND gate selects the magnitude-reduced, parity-inverted output of the magnitude reductioncircuit 80for feeding to the IDCT circuit 15 inlieu of theDCT coefficient whose parity may be inverted. Thepolarity judgment circuit 81 judges the polarity of each DCT coefficient in the block of DCT coefficients received on the path RDATA, and sets the state of its output to a one or a zero, depending upon whether the polarity of the DCT coefficient is positive or negative. Whenthe polarity judpent circuit judges that the polarity of the DCT coefficient is positive, the output of the polarity judpent circuit opens the fifthAND gate 84 and closes the sixth AND gate circuit 85. This feeds the output of the -1 subtractor 82, i.e., the DCT coefficient from which one has been subtracted, to the fourth AND gate 65 via the fifth AND gate 84 and the OR gate 86. On the other hand, when the polarity judpent circuit 81 judges that the polarity of the DCT coefficient is negative orzero, the output of thepolarity judpent circuit closes the fifth AND gate 84 and opens sixthAND gate 85. This feeds the output of the +1 adder 83, i.e., theDCT coefficient to which 1 has been added, to the fourth AND gate 65 via the sixth AND gate 85 and the OR gate 86. The fourth AND gate 65 feeds the parity-inverted, magnitude-reducedDCT coefficient from the magnitude reduction circuit 80 to the second AND gate 68 in response to theprocessing request signal REQl. When the comparator 62 determines that the DCT coefficient received on the path RDATA is the DCTcoefficientwhoseparitymaybe inverted, themagnitude-reduced, polarity-invertedDCTcoefficient is fed from the magnitude reduction circuit 80 to the IDCT circuit 15 (Figure 10A) in the manner described above with reference to Figure 11. On the other hand, when the third embodiment of the parity inverter shown in Figure 15 receives no processing request signal REQl, the DCT coefficient whose parity may be inverted is fed to IDCT circuit 15 unchanged. When the sum of the DCT coefficients is to be oddified, the third embodiment of the parity inverter 28 shown in Figure 15 feedsto the IDCT circuit 15 theDCT coefficient whoseparity has been ■ invertedby subtracting one from it when its polarity is positive, and feeds to the IDCT circuit 15 the DCT coefficient whoseparity has been be invertedby adding one to it when its polarity is zero or negative. This processing inverts the parity and reduces the magnitude of the DCT coefficient whose parity is to be inverted, and oddifies the sum of the DCT coefficients. Afourth embodiment of theparity inverter 28 willnow be describedwith reference to Figures 16 and 17. Whenthe fourth embodimentof theparityinverter receivestheprocessing request signalREQl, itoddifies the sumof theDCT coefficients inthe blockby replacingthe DCTcoefficientwhose parity is to be invertedwith the DCTcoefficient whose parity is to be invertedto which one hasadded when the sign of the DCT coefficient is positive, and from which one has been subtracted when the sign of theDCT coefficient is negative. Thisprocessing not only inverts theparity of the DCTcoefficient whoseparity is to be inverted, but also increases themagnitude of this DCT coefficient, i.e., makes theDCT coefficient whose parity is to be inverted further from zero. The processing applied to the DCT coefficient whose parity is to be inverted is defined by the following equation: if(rec > 0) rec = rec + 1 if(rec < 0) ••• (16) rec = rec - 1 where rec is the DCT coefficient whose parity is to be inverted. The fourth embodiment of theparity inverter 28 may be provided using a computer or digital signal processor operating in accordance with the flow chart shown in Figure 16. At step SI, parity inverter28 judges from the addressEOB_adrs whether ornot theDCTcoefficient is theDCTcoefficient whose parity may be inverted. For example, the parity inverter judges whether or not the DCT coefficient is the last non-zero DCT coefficient. If the result at step SI is YES, and the DCT coefficient is the DCT coefficient whose parity may be inverted, execution proceeds to step S2. Otherwise, andthe DCTcoefficient is not the DCTcoefficient whose parity may be inverted, execution proceeds to step S8. At step S2, the parity inverter 28 determines whether or not the processing request signal REQl has been received. If the result at step S2 is YES, indicating that the processing request signal REQl has been received, execution proceeds to step S3. Otherwise, no processing request has been received, and execution proceeds to step S8. Since a YES result at step S2 can only occur if aYES result is obtained at step SI, the YES result at step S2 indicates that the DCT coefficient is the DCT coefficient whose parity is to be inverted. At step S3, the parity inverter 28 determines the polarity of the DCT coefficient. If the result at step S3 is YES, indicating that thepolarity of the DCT coefficient is positive, execution proceeds to step S4. Otherwise, the polarity of the DCT coefficient is zero or negative, and execution proceeds to step S6. At step S4, the parity inverter 28 adds one to the DCT coefficient, after which execution passes to step S5, where the parity-inverted DCT coefficient is fed to the IDCT circuit 15 (Figure 10A). Then, execution returns to step SI, where the next DCT coefficient is processed. Otherwise, at step S6, the parity inverter 28 subtracts one from the DCT coefficient (i.e., adds-1 thereto), afterwhich executionproceeds tostep S7, where theparity-invertedDCTcoefficient is fed to the IDCT circuit 15. Then, execution returns to step SI, where the next DCT coefficient isprocessed. Executionpasses to step S8 when theDCT coefficient is not the DCT coefficientwhose parity may be inverted, or when the DCT coefficient whose paritymay be inverted is not to have its parity inverted, i.e., when the processing request signal REQl has not been received. At step S8, the DCT coefficient is fedto the IDCT circuit 15 without modification. Then, execution returns to step SI, where the next DCT coefficient is processed. Figure 17 showsa practical example of the circuit configuration of the fourth embodiment of theparity inverter 28, in which the parity inversion is carriedout to increase the magnitude of the DCT coefficient whose parity is inverted, i.e., to make the DCT coefficient whose parity is to be inverted further from zero. Theparity inverter shown in Figure 17 is similar to theparity inverter 28 shown in Figure 11. Elements in the circuit shown in Figure 17 correspondingto those in the circuit shown in Figure 11 are indicated by the same reference numerals, and will not be described again here. The parity inverter shown in Figure 17 differs from the parity inverter shown in Figure 11 in that it includes the magnitude increasing circuit 90 in lieu of the LSB inverter 63. Themagnitude increasing circuit 90 determines the polarity of each DCT coefficient received from the first memory 26 or the second memory 27, via the path RDATA. When the polarity of the DCT coefficient is positive, the magnitude increasing circuit adds one to the DCT coefficient, whereas, when the polarity of the DCT coefficient is zero or negative, it subtracts one from the DCT coefficient. The parity inverting circuit shown in Figure 17 oddifies the sum of the DCT coefficients in the block by selecting the DCT coefficient whose parity is to be inverted from the magnitude increasing circuit, and substituting the magnitude-increased DCT coefficient for the DCT coefficient whose parity is to be inverted. The magnitude increasing circuit 90 comprises the polarity judgement circuit 91, which controlsthe fifthAND gate 94 directly, andthe sixthAND gate 95 viathe inverter97. Themagnitude increasing circuit 90 also includes the +1 adder 92 and the -1 subtractor 93 that respectively add one to and subtract one from each DCT coefficient. Either the output ofthe +1 adder 92 or the output of the -1 subtractor 93 is selected by the fifthAND gate 94 or the sixth AND gate 95 in response to the output of the polarity judgment circuit 91. The outputs of the AND gates 94 and 95 feed the OR gate 96, whichprovides the selected magnitude-increased DCT coefficient to the fourth AND gate 65. When the parity of the sum of the DCT coefficients in the block needs to be inverted, the fourth AND gate selects the parity-inverted, magnitude-increased output of the magnitude increasing circuit 90 for feeding to the IDCT circuit 15 in lieu of the DCT coefficient whose parity may be inverted. The polarity judpent circuit 91 judges the polarity of each DCT coefficient in the block of DCT coefficients received on the path RDATA, and sets the state of its output to a one or a zero, dependingupon whether the polarity of theDCT coefficient is positive ornegative. Whenthe polarity judpent circuit judges that the polarity of the DCT coefficient is positive, the output of the polarity judgment circuit opens the fifthAND gate 94 andcloses the sixth AND gate circuit 95. This feeds the output of the +1 adder 92, i.e., the DCT coefficient to which one has been added, to the fourth AND gate 65 via the fifth AND gate 94, and the OR gate 96. On the other hand, when thepolarity judpent circuit 91 judges that the polarity of theDCT coefficient is negative orzero, the output of thepolarity judpent circuit closes the fifth AND gate 94 and opens sixth AND gate 95. This feeds the output of the -1 subtractor 93, i.e., the DCT coefficient from which one has been subtracted, to the fourth AND gate 65 via the sixth AND gate 95 and the OR gate 96. The fourth AND gate 65 feeds the parity-inverted, magnitude-increased DCT coefficient from the magnitude increasing circuit 90 to the secondAND gate 68 in response to the processing request signal REQl. When the comparator 62 determines that the DCT coefficient received on the path RDATA is the DCT coefficient whose parity may be inverted, the DCT coefficient is fed from the magnitude increasing circuit to the IDCT circuit 15 (Figure 10A) in the manner described above with reference to Figure 11. On the other hand, when the fourth embodiment of the parity inverter shown in Figure 17 receives no processing request signal REQl, the DCT coefficient whose parity may be inverted is fed to IDCT circuit 15 unchanged. When the sum of the DCT coefficients is to be oddified, the fourth embodiment of the parity inverter 28 shown in Figure 17 feeds to the IDCT circuit 15 the DCT coefficient whose parity has been inverted by adding one to it when its polarity is positive, and feeds to the IDCT circuit 15 the DCT coefficient whose parity has been inverted by subtracting one from it when its polarity is zero or negative. Thisprocessing inverts theparity andincreases the magnitude ofthe DCTcoefficient whose parity is inverted, and oddifies the sum of the DCT coefficients. Theparity inverters 28 shown in Figures 11, 13, 15 and 17, and operation in accordance with the flow charts shown in Figures 9, 12, 14, and 16 may be modified to oddify the sum of the DCT coefficients by changing theparity of a DCTcoefficient otherthan the last non-zero DCTcoefficient read out by the zigzag scan. For example, in a two-dimensional 8 8 DCT transform, the parity of one of the DCT coefficient of the DC component, the DCT coefficient of the (7, 7) component, i.e., the highest- frequency component, the DCT coefficient of the (7, 0) component at the upper-right corner, or the DCT coefficient of the (0, 7) component at the lower-left corner may be changed. Since, in particular, the DCTcoefficient of the (7, 7) component, which is the highest-frequency component, has a small influence on the picture quality, this component is particularly suitable for being the coefficient whose parity may be changed. Inthe parity inverters shownin Figures 11, 13, 15, and17, alternativeDCTcoefficients may be selectedas theDCT coefficientwhose parity may be changedby substituting the address of theDCT coefficient for the address EOB_adrs fedinto the comparator 62. Alternatively, if theparity of the DCT coefficient of the highest-frequency component is to be changed, the readout counter 61 and the comparator 62 may be omitted, and the memory full signal FULL may be used to identify the DCT coefficient of the highest-frequency component as the DCT coefficient whose parity may be changed. In a further alternative, the sum oddifying circuits 14 shown in Figures 6, 8, and 10 may determine the sum of specific DCT coefficients, for example, the DCT coefficients of the (0, 0) component, the (4, 0) component, the (0, 4) component and the (4, 4). Then, the sum oddifying circuit wouldcarry out a parity inversion operation to make the sum of the specific DCT coefficients an odd number. Figure 18 showsa variation on the sum oddifying circuit 14 shown in Figure 8. In this, the sum of specific DCT coefficients is determined to determine whether parity inversion is necessary. Elements in the circuit shown in Figure 18 corresponding to those in the circuit shown in Figure 8 are indicated by the same reference numerals, and will not be described again here. In the sum oddifying circuit shown in Figure 18, the selector 51 interrupts the line between the inverse quantizer 13 and the accumulator 23A. The selector 51 also receives from the counter 20 the countvalue coeff_adrs, which indicates thenumber ofDCTcoefficients inthe blockthat have been received from the inverse quantizer 13. Inresponse tothe countvalue coeff_adrsreceived fromcounter 20, the selector51 determines whether or not each DCT coefficient received from inverse quantizer 13 is one of the specific DCT coefficients, and is therefore to be included in the sum determined by the accumulator 23A. Thus, for example, the selector determines whether the count value coeff_adrs is a value corresponding to the (0, 0) component, the (4, 0) component, the (0, 4) component or the (4, 4) component. When the selector 51 determines that the DCT coefficient is one of the specific DCT coefficients, it delivers the DCT coefficient to the accumulator 23A. Accordingly, the sum oddifying circuit shown in Figure 18 determines the sum of specific DCT coefficients in the block, and, if the parity of the sum is even, changes the parity of at least one of the DCT coefficients to make the sum an odd number. The sumoddifying circuit shown in Figure 18 then feeds the block of parity-adjusted DCT coefficients to the IDCT circuit 15. The embodiment shown inFigure 18 may be modified in amanner similar tothat shown in Figure 10A to enable the circuit to determine the exclusive logical sum of the LSBs of the specific DCT coefficients. The circuit in Figure 18 is modified by replacing the adder 23 by the LSB detector 29 and the exclusive-OR gate 30 shown in Figure 10A. Returning nowto Figure 6, the DCT coefficients in the block of DCT coefficients are fed from the sumoddifying circuit 14 to the IDCT circuit 15, describedabove. The sumof theDCT coefficients from the sum oddifying circuit is an odd number. If the sum of the DCTcoefficients from the inverse quantizerwas an even number, the sum oddifying circuit 14 changed the parity of at least one of the DCT coefficients to oddify the sum of the DCT coefficients fed to the IDCT circuit 15. The IDCT circuit 15 applies IDCT processing to the DCT coefficients in the block to provide the recovered difference block S4. The recovered difference block is fed to the adder 16. The adder 16 performs pixel-by-pixel addition between the recovered difference block S4 and the matching block S2 received from second picture memory group 4. The resulting reconstructed picture block S5 is fed to the picture memory group 4, where it provides a block of the reconstructed picture stored in the one of the picture memories specified by the memory controller 3. The variable-length coder 17 applies variable-length coding, such as Huffman coding, etc., to each block of quantized DCT coefficients SC from the difference block encoder 9, and its motion vector MV, motion compensation mode MM, quantizing table data, etc. The variable-length coder also assembles the variable-length coded datawith the start codes andheader information of the respective layers of the MPEG standard to form the compressed motion picture signal. The slice/macro block counter 5 counts the slice start sipals SS and the macroblock start signals BS generatedby the memory controller 3 in synchronism with the start of each slice and each macroblock of the pictures read out from the first picture memory group 2 for processing. When its count value reaches predetermined value, the slice/macro block counter 5 generates the start signal SO, which is fed to the variable- length coder 17. In response to the start signal, the variable-length coder 17 feeds the compressed motion picture signal to the output buffer 19, where it is temporarily stored. Then, the compressed motion picture signal is read out of the output buffer as a bit stream with a predetermined bit rate. The bit stream of the compressed motion picture signal is fed to a complementary expander via a transmissionpath, or byrecording the bit steam ofthe compressed motionpicture signal ona suitable recording medium, such as an optical disc. The recording medium is a recording medium on which there is recorded the compressed motion picture signal derived from the motion picture signal by prediction coding and discrete cosine transform processing. Each block of each reconstructed picture used as a reference picture in the prediction coding is reconstructed by inversely quantizing a block of the quantized DCT coefficients included in the compressed motion picture signal, oddifying the sum of the DCT coefficients in the resulting block of DCT coefficients, and inversely orthogonally transforming the sum-oddified block of DCT coefficients. A transmitting apparatusaccordingto the invention can include acompressor accordingto the invention, as described above. It may be thought that it would be better to carry out the sum oddifying operation in the difference blockencoder 9 in the compressor. The sum oddifyingoperation wouldcause the sumof the DCTcoeficients ineach blockof quantizedDCTcoefficients included in the compressedmotionpicture signal to be an oddnumber. It might be thought that processing the compressedmotion picture signal in this way would make it unnecessary to oddify the sum of the DCT coefficients in the expander. However, with such an arrangement, afterthe DCT coefficients have been quantizedin the compressor, and inversely quantized in the expander, the sum of the DCT coefficients entering the IDCT circuit in the expander mayno longer be an odd number. Hence, sum oddification processing must be carried out prior to the IDCT processing in the expander to ensure that a mismatch error will not occur. A compressedmotion picture signal expander to which this invention is applied will now be describedwith reference to Figure 19. In Figure19, the compressedmotion picture signal is received as a bit stream viaa transmission line from the compressor, or by reproducing the compressedmotion picture signal from a suitable recording medium, such as an optical disc. Thebit stream is fed into the input buffer 31, where it is temporarily stored, and whence it is read out, picture-by-picture, intothe inverse variable-lengthcoder (the "IVLC") 32. The inversevariable-length coder 32 extracts from the compressed motion picture signal the header information of respective layers of the MPEG coding, and from the header information, extracts thepicture decoding control information PH, which it feeds to the memory controller 33. The IVLC 32 applies inverse variable-length coding to the blocks of variable-length coded DCT coefficients to provide blocks of quantized DCT coefficients including the current block of quantized DCT coefficients Cb. The block of quantized DCT coefficients Cb is delivered to the difference block decoder 34. The difference block decoder 34 decodes the block of quantized DCT coefficients Cb to provide the restoreddifference block BS, andfeeds the restored difference block to the adder 39. The IVLC 32 extracts from the compressedmotion picture signal themotion vector MV and the motion compensation mode MM for the block of quantized DCT coefficients Cb, and feeds them to the motion compensator 37. Themotion compensator 37 causes amatching block forthe restored difference block BS to be read from the picture memory group 38. The picture memory block includes several picture memories, each of which stores one already-reconstructedpicture. The matching blockBS is a block of the reconstructed picture stored in one of the picture memories at an address specified by the motion vector MV. The picture memory inthe picture memory group 38 storing the reconstructedpicture from which the matching block is read is specified by the memory controller 33. As mentionedabove, a picture can be coded by prediction from a prior reconstructed picture, by prediction from a following reconstructed picture, and by prediction from a block obtained by performing a pixel-by-pixel linear operation on a prior reconstructed picture and a following reconstructed picture. Finally, a picture may be coded using no prediction at all. In this case, the matching block provided by the picture memory group 38 is a zero block, i.e., a block in which all the pixel values are set to zero. The motion-compensated matching blocks provided by the picture memorygroup 38 are adaptively modified, and the optimumone is selectedfor each block. This process is carried out using a block having a block size of 16 x 16 pixels. Eachmatching blockprovided by the picture memorygroup 38 is fed tothe adder 39. The add.r 39 performs a pixel-by-pixel addition between the restored difference block BS received from the difference block decoder 34, and the matching block provided by the picture memory group 38. The result of this addition is a reconstructed picture block, which is stored in the one of the picture memories in the picture memory group 38 specified by the memory controller 33. The reconstructed picture blocks produced by the adder 39 are stored one-by-one in the selected picture memory, overwriting the reconstructed picture previously stored in the picture memory, to form a new reconstructed picture. The reconstructed pictures stored in the picture memory group 38 are read out in a sequence controlled by an output picture indication signal provided by the memory controller 33. The read out pictures are fed, as a reproduced motion picture signal, to a suitable picture display, e.g., avideo monitor. The picture display displays amotion picture in response to the reproducedmotion picture signal. The difference block decoder 34 will now be described with reference to Figure 19. The difference block decoder 34 comprises the inverse quantizer 40, the sum oddifying circuit 35, and the inverse discrete cosine transform circuit 36. The inverse quantizer 40 uses a quantizing table to inversely quantize the block of quantized transform coefficients Cb received from the inverse variable-length coder 32. The sum oddifying circuit 35 receives the resulting block of DCT coefficients from the inverse quantizer 40, andprevents mismatch errors from occurring in the IDCT processing by the IDCT circuit 36. The IDCT circuit 36 applies IDCT processing to the block of sum-oddified DCT coefficients from the sum oddifying circuit 35. Figure 20 shows an example of the construction of the inverse quantizer 40. The main components of the inverse quantizer 40 are the run/level decoder 41, the address counter 47, the address converter 48, the selector 49, the first blockmemory 42, the second block memory 43, and the inverse quantizing circuit (the "IQ circuit") 46. The run/level decoder 41 receives the block of quantizedDCT coefficients Cb from the inverse variable-length coder 32. The run/level decoder decodes the run/level coding that was applied to the quantized DCT coefficients in the variable-length coder in the compressor. The resulting block of quantized DCT coefficients are fed to the first block memory 42 or to the second block memory 43 in zigzag scan order. The first block memory 42 and the second blockmemory 43 each store one block of quantized DCT coefficients. The addresscounter 47 andthe addressconverter48 respectively generate write addresses and the read addresses for the first blockmemory 42 and the second blockmemory 43. Blocks of quantized DCT coefficients are alternately written into and read out of the first block memory and the second blockmemory. Each blockof quantizedDCT coefficients is written into one of the blockmemories in zigzag scan order in response to the addresses provided by the address counter 47, and is read out of the block memory in raster scan order in response to the addresses provided by the address converter 48. The different order of the addresses between writing and reading converts the order of the quantized DCT coefficients in the block from zigzag scan order to raster scan order. The address counter generates 47 the writing addresses in zigzag scan order. The address converter 48 receives the addresses in zigzag scan order from the address counter anduses an address conversion table to convert the addresses to addresses in raster scan order. The addresses generated by the address counter 47 and the address converter 48 are selected by the selector 49 for feeding to the first block memory 42 and the secondblock memory 43 as the addresses adrsl and adrs2. When a block of quantized DCT coefficients rom the run/level decoder 41 is written into the first block memory 42 or the second block memory 43, the respective addresses adrsl and adrs2 areprovided by the address counter 47 via the selector 49 in zigzag scan order. When the block of quantized DCT coefficients is read out rom the first block memory 42 or the second block memory 43 to the inverse quantizer 46, the respective addresses adrsl and adrs2 are providedby the address converter 48 via the selector 49 in raster scan order. When all the quantized DCT coefficients in the block have been stored in the first block memory 42 or the second block memory 43, the block of DCT coefficients is read out in raster scan order to the inverse quantizer (the "IQ") 46. The IQ 46 inversely quantizes the quantized DCT coefficients in the block, and feeds the resulting block of DCT coefficients to the sum oddifying circuit 35. The inverse quantizing performed by the IQ 46 is the same as the inverse quantizing performed by the inverse quantizer 13 in the local decoder in the motion picture signal compressor shown in Figure 6. When the sum oddifying circuit 35 determines that the parity of the sum of the DCT coefficients in the block of DCT coefficients from the inverse quantizer 40 is even, it operates on at least one DCT coefficient in the block to make the sumof the DCT coefficients in the blockan odd number. The sum oddifying circuit 35 feeds the block of sum-oddified DCT coefficients to the IDCT circuit 36. The sum oddifying operationperformed by the sumoddifying circuit 35 is the same as the sum oddifying operation performed by the sum oddifying circuit 14 in the local decoder in the motion picture signal compressor shown in Figure 6. The IDCT circuit 36 performs IDCT processing on the block of sum-oddified DCT coefficients to provide the restored difference block BS, which is fed to the adder 39. The practical operation of the inverse quantizer 40 shown in Figure 20 is illustratedby the timing chart shown in Figures 21A through 211. The inverse variable-length coder 32 extracts the block of quantized DCT coefficients Cb from the compressed motion picture signal. The inverse variable-length coder generates the event enable signal EV_EN, shown in Figure 21A, which instructs the run/level decoder 41 to read the block of quantizedDCT coefficients. The quantized DCT coefficientsin the block ofquantized DCT coefficients Cb are run/level coded. The IVLC 32 also provides the event number signal EVENT_N0 to the run/level decoder 41, as shown in Figure 21B. The event number signal indicates the number of run/level pairs in the blcck of quantized DCT coefficients Cb, i.e., the number of pairs of data indicating run and level. When the run/level decoder 41 receives the event number signal EVENT_NO, it feeds a readout request signal RE_REQ for each run/level pair back to the inverse variable-length coder 32, as shown in Figure 21C. Each time it receives the readout request signal RE_REQ, the inverse variable-length coder 32 feeds one run/level pair to the run/level decoder41, as shown in Figures 21D and21E. Thus, the IVLC 32 feeds to the run/level decoder 41 the number of run/level pairs corresponding to the number of readout request signals it receives. The run/level decoder 41 decodes the run/level coding of the run/level coded quantized DCT coefficients to deliver a block of quantized DCT coefficients in zigzag scan order as WDATA to the first block memory 42, as shown in Figure 21G. At the same time, as shown in Figure 21F, the address counter 47 counts the quantized DCT coefficients from the run/length decoder and feeds the address signal adrsl in zigzag scan order, indicating the write address of each quantized DCT coefficient, via the selector 49 to the first block memory 42. When the run/level decoder 41 receives the EOB code from the IVLC 32, indicating that it has received the last non-zero DCT coefficient, the run/level decoder sets the quantizedDCT coefficient corresponding to the EOB code, and all the following quantized DCT coefficients to zero, and feeds these zero DCT coefficients into the first block memory 42. Also when it receives the EOB code, the run/level decoder 41 feeds the signal EOBJN to the position registers (POS REG) 44 and 45, as shown in Figure 21H. The EOBJN signal indicates to the position registers that the EOB code has been received. The position registers also receive, from the address counter 47 via the address converter 48, the address of each quantized DCT coefficient fed to the first and second block memories 42 and 43. When the run/level decoder receives the EOB code, the address generatedby the addresscounter 47 is the addressof the last non-zero coefficient. The EOBJN signalcauses the address, EOBJOS, of the last non-zero coefficient, converted toa raster scan address by the converter 48, to be written into the position register of the block memory into which the block of quantized DCT coefficients is being written. One of POS registers44 and 45 thus stores the address of the last non-zero coefficient of the block of quantized DCT coefficient. When the run/level decoder 41 has fedthe complete blockof quantized DCTcoefficients into the first block memory 42 or the second block memory 43, the address counter 47 feeds the bank switching signal BANK to the first block memory 42 and the second block memory 43. The BANK signal switches over the mode of the blockmemories, so that the first block memory, which formerly was in write mode, is switched to readmode, and the second block memory is switched to write mode. Thus, when the run/level decoder 41 decodes the next block of quantized DCT coefficients, the resulting quantized DCT coefficients will be written into the second block memory 43. The BANK signal also switches over the selector 49, so that the addresses fed to the block memory in write mode are the addresses in zigzag scan order from the addresscounter 47, and the addresses fedto theblock memory in read mode are the addresses in raster scan order from the address converter 48. Also, when the run/level decoder 41 has fedthe complete blockof quantizedDCT coefficients into the first block memory 42, the first block memory 42 feeds the memory full signal FULL1 to the inverse quantizer 46. The memory full signal indicates that all the quantized DCT coefficients in the block have been stored. When the IQ 46 receives the memory full signal FULL1, it sends the readout request signal RDJN to the first block memory 42. The readout request signal causes the first block memory to read out the quantized DCT coefficients stored therein in response to the addresses adrsl provided in raster scan order by the addressconverter 48 via the selector 49. Consequently, the quantizedDCT coefficients in the block are read out of the firstblock memory 42. TheDCT coefficients read out in response to each address is fed into the inverse quantizer 46. Atthe same time as the quantized DCTcoefficients in theblock are read from the firstblock memory 42, the quantizedDCT coefficients in the next blockare written in zigzag scan order into the second block memory 43 in response to addresses from the address counter 47. The inverse quantizer 46 inversely quantizes the quantized DCTcoefficients in the block of quantizedDCT coefficients a manner similar to the inverse quantizer 13 in the motion picture signal compressor described above with reference to Figure 6. The resulting block of DCT coefficients is fed to the sum oddifying circuit 35. When the parity of the sum of the DCT coefficients in the block is an even number, the sum oddifyingcircuit 35 operates on at least one of the DCT coefficients in the block to oddify the sum ofthe DCTcoefficients in the blockin amanner similar to the sum oddifyingcircuit 14 in the motion picture signal compressor described above. The resulting block of sum-oddified DCT coefficients is fed to the IDCT circuit 36. For example, the sum oddifying circuit 35 may refer to the POS registers 44 and 45 to determine whether or not the current DCT coefficient is the last non-zero coefficient in zigzag scan order so that the sum oddifying circuit can change the parity of the last non-zero DCT coefficient to oddify the sum of the DCT coefficients in the block. Alternatively, the sum oddifying circuits 35 may operate on the DCT coefficient of the highest frequency component to oddify the sum of the DCT coefficients. Inverting the parity of the DCT coefficient of the highest-frequency component may be preferable because the highest-frequency component has a small influence on the picture quality, and there is no necessity to determine which of the DCT coefficients is the last non-zero coefficient. This is also true in the case when the scan order is other than zigzag scan order. It must be stressed that, to avoidmismatch errors, the sum oddifying operations carriedout in the motion picture signal compressor and in the compressed motion picture signal expander must be identical to one another. 2. Second Embodiment The configuration of a second embodiment of a motion picture signal compressor is shown in Figure 22. The second embodiment is the preferred embodiment of the invention. The configuration of the sum oddifying circuit 50 of the motion picture signal compressor shown in Figure 22 is shown inFigure 23. Elements of the second embodiment ofthe motionpicture signalcompressor corresponding to those in the first embodiment of the motion picture signal compressor shown in Figure 6 are indicatedby the same reference numerals, andwill not be describedagain here. The second embodiment differs from the first embodiment in the configuration of the sum oddifying circuit 50. Inthe sumoddifyingcircuit 50 shown in detail in Figure23, the counter 20 counts the number of DCT coefficients received from the inverse quantizer 13, and feeds the resulting count value coeff_adrs to the parity judpent circuit 21. The accumulator 23A comprises the adder 23 and the register 24. The adder 23 adds each DCT coefficient in a block of DCT coefficients received rom the inverse quantizer 13 to the sum of the already-received DCT coefficients in the block stored in the register 24. The register 24 is reset after the sum has been determined for each block of DCT coefficients. The resulting sum of the DCT coefficients is fedfrom the adder 23 to the register 24, and to the parity judpent circuit 21. The accumulator 23A needs only sum the least significant bits of the DCT coefficients in the block to provide a result suitable for the parity judgment circuit to judge whether the parity of the sum of the DCT coefficients is odd or even. The parity judgment circuit 21 operates in response to the count value coeff_adrs received from the counter 20 as follows. When the countvalue indicates that all the DCT coefficients in the blockhave been summed by the accumulator 23A, the parity judpent circuit 21 determines whether the parity of the sum of the DCT coefficients received from the accumulator 23A is odd or even. For example, in the case of a two-dimensional 8 x 8 DCT transform, when the count value indicates that the sum of the 64 DCT coefficients in the block has been determined, the parity judpent circuit 21 determines whether the parity of the sum of the DCT coefficients received from the accumulator 23A is odd or even. Inpractice, whenthe DCT coefficients are representedby binary numbers, the parity judpent circuit 21 examines the least-significant bit (LSB) of the sum of the DCTcoefficients received from the accumulator 23A. An LSB of zero indicates that the parity of the sum is even. In this case, the parityjudpent circuit 21feeds theprocessing request signal REQl to theparity inverter 53to cause the parity inverter to carry out a parity inversion operation. In response to the processing request signal REQl, the parity inverter 53 changes the parity of at least one (i.e., an odd number) of the DCT coefficients in the block to oddify the sum of the DCT coefficients. On the other hand, an LSB ofone indicates that the parity of the sum is odd. In thiscase, the parity judpent circuit 53 does not provide the processing request signal REQl, and the parity inverter 53 leaves the parity of all the DCT coefficients in the block unchanged, because the parity of the sum of the DCT coefficients is already odd. The blockof DCT coefficients isfedfrom the inverse quantizer 13 not onlyto the accumulator 23A, but also to the parity inverter 53 via the delay circuit 52. The delay circuit 52 delays the DCTcoeficients in the blockby atime correspondingto theprocessing timesof the accumulator 23A andthe parity judgment circuit 21, such that the last DCT coefficient, i.e., the highest-frequency coefficient (e.g., theDCT coefficient of the (7, 7) component in an 8 x 8 DCT transform) arrives at the parity inverter 53 at the same time as the processing request signal REQl. Thus, the parity inverter 53 feeds all the DCT coefficients except for the highest-frequency coefficient to the IDCT circuit 15 unchanged. When the parity judpent circuit 21 has not generated the processing request signal REQl, the parity inverter 53 also feeds the highest-frequency DCT coefficient to the IDCT circuit unchanged. Only when the parity judgment circuit 21 has generated theprocessing request signal REQl doesthe parityinverter 53 invert the LSBof the highest-frequency DCT coefficient, and feed the parity-inverted highest-frequencyDCT coefficient to the IDCT circuit 15. Thus, when the parity judgment circuit 21 indicates that the parity of the sum of the DCT coefficients in the block is even, the parity inverter 53 operates on the highest-frequency DCT coefficient (e.g., the DCT coefficient of the (7, 7) component in an 8 x 8DCTtransform)in the block. The parity inverter inverts the parity of the highest-frequency DCT component, and hence oddifies the sum of the DCT coefficients in the block of DCT coefficients fed to the IDCT circuit 15. Thus, the parity of the sum of the DCT coefficients in the block of DCT coefficients is always odd. The DCT coefficient of the (7, 7) component is the coefficient that has the least influence on the output values of the IDCT. Furtherpractical examples of the sum oddifyingcircuit 50 of thepreferred embodimentof the invention will now be described. Figure 24 shows an example in which the LSB detector 29 and the exclusive OR (EXOR) gate 30 are substituted for the adder 23 in Figure 23. Elements in the circuit shown in Figure 24 corresponding to those in the circuit shown in Figure 23are indicatedby the same reference numerals, and will not be described again here. The LSB detector detects the LSB of each DCT coefficient in the block, and the EXOR circuit 30 and the register 24 together determine the exclusive logical sum of the LSBs of the DCT coefficients in the block. The parity of the exclusive logical sum is determined by the parity judgment circuit 21, as described above with reference to Figures 10A and 23. Alternatively, the AND gate 88 and counter 89 shown in Figure 10Bcan be substituted for the exclusive-OR gate 30 and the register 24 shown in Figure 24. Another example is shown in Figure 25. In this, the selector 51 is inserted between the inverse quantizer 13 and the accumulator 23A in the sum oddifying circuit 50 shown in Figure 23. Elements in the circuit shown in Figure 25 corresponding to those in the circuit shown in Figure 23 are indicatedby the same reference numerals, andwill not be describedagainhere. The circuit shown in Figure 25 determines the sum of the DCT coefficients of only specific coefficients, e.g., the (0, 0) component, the (4, 0) component, the (0, 4) component, and the (4, 4) component, to determine whether sum oddifying is required. The selector 51 receives the count value coeff_adrs from the counter 20 to determine whether or not each DCTcoefficient received from inverse quantizer 13 is one of the specific coefficients, and is therefore to be summed. When the selector determines that the DCT coefficient is one of the specific coefficients and is to be summed, i.e., the count value coeff_adrs has a value corresponding to, e.g., the (0, 0) component, the (4, 0) component, the (0, 4) component, or the (4, 4) component, the selector51 delivers the DCT coefficient to the accumulator 23A. The selector 51 causes the sum oddifying circuit shown in Figure 25 to determine the sum of specific coefficients. The parity inverter 53 then operates on at least one of the specific DCT coefficients, if necessary, to make the sum of the specific DCT coefficient an odd number. The block of sum-oddified DCT coefficients is then fed to the IDCT circuit 15. In another alternative, the selector 51 shown in Figure 25 may be inserted into the line between the inverse quantizer 13 and the LSB detector 29 in the circuit shown in Figure 24. The circuit shown in Figure 24, modified in this way, would determine the exclusive logical sum of the LSBs of the specific DCT coefficients selected by the selector. In a further alternative embodiment of the sum oddifying circuit 50, when the last DCT coefficient received from the inverse quantizer 13 is theDCT coefficient of DC component, i.e., when the order of the raster scan is opposite to that in the embodiments described above, the DCT coefficient to which the parity inversion operation applied is not the highest-frequency DCT component, but DCT coefficient of DC component. An example of the practical circuit configuration of the parity inverter 53 will now be describedwith reference to Figure 26. The parity inverter 53 is a simplified version of the above- described parity inverter 28 shown in Figure 11. The parity inverter 53 includes the LSB inverter 63, the third and fourth AND gates 64 and 65, the OR gate 66, and the inverter 71. In theparity inverter 53, the LSB inverter 63 inverts the LSB ofeach DCT coefficient in the block of DCT coefficients received from the inverse quantizer 13. This inverts the parity of each DCTcoefficient. Normally, the processing request signal REQl is absent, so the parity inverter feed each DCT coefficient received to the IDCT circuit 15 (Figure 23) via the third AND gate 64 and the OR gate 69. When the highest-frequency DCT coefficient in the block is received by the sum oddifying circuit 50 (Figure 23), the count value coeff_adrs from the counter 20 indicates to the parity judpent circuit 21 that the value receivedby the parity judpent circuit is the sumof all theDCT coefficients in the block. In response, the parity judgment circuit determines whether the parity of the sum of the DCT coefficients is odd oreven. When the parity judpent circuit 21 determines that the parity of the sum of the DCT coefficients in theblock is even, it feeds theprocessing request signal REQl to the parity inverter 53. Theprocessing request signal arrivesat theparity inverter 53 via the delay 52 at the same time as the highest-frequency DCT coefficient. The processing request signal REQl changes the states of the third and fourth AND gates 64 and 65. This feeds the LSB-inverted highest-frequency DCT coefficient from the LSB inverter 63 to the IDCT circuit 15, via the fourth AND gate 65 and the OR gate 69. The LSB-inverted highest-frequency DCT coefficient is fed to the IDCT circuit in lieu of thenormal highest-frequencyDCTcoefficient to oddifythe sumof theDCTcoefficients fed tothe IDCT circuit. On the other hand, when theparity judgment circuit 21 determines that theparity of the sum of theDCT coefficients in the blockis odd, it does notgenerate the processing request signal. The parity inverter 53 feeds the normal highest- frequency DCT coefficient to the IDCT circuit 15, via the AND gate 64 and the OR gate 69, since no sum oddifying of the block of DCT coefficients is required. Modificationsto thepractical example of theparity inverter 53 shown in Figure 26 are shown in Figures 27 through 29. Figure 27 showsthe +1 adder 73, similarto the +1 adder shown in Figure 13, substitutedfor the LSB inverter 63 in the parity inverter shown in Figure 26. The circuit is otherwise unchanged. Theparity inverter modified as shown in Figure 27 inverts the parity of each DCT coefficient in the block by adding one to it. Thus, when the parity judpent circuit 21 feeds the processing request signal REQl to the parity inverter, the parity inverter feeds to the IDCT circuit 15 the highest- frequency DCT coefficient with one added to it in lieu of the normal highest-frequency DCT coefficient. This substitution oddifies the sum of the DCT coefficients in the block. Asshown in Figure 28, themagnitude reducing circuit 80 shown in Figure 15may besubstituted for the LSB inverter 63 in the circuit shown in Figure 26. The circuit shown in Figure 26 is otherwise unchanged. The parity invertershown in Figure 26, modified asshown in Figure 28, oddifies the sum of the DCT coefficientsaccording to equation (15), describedabove. When the parity judpent circuit 21 generates the processing request signal REQl, the sumof the DCT coefficients in the block is oddified by feeding the highest-frequency DCT coefficient with its parity inverted to the IDCT circuit 15. The parity of the highest-frequency DCT coefficient is inverted in one of two ways: one is subtracted from the highest-frequency DCT coefficient by the -1 subtractor 82 when the highest-frequency DCT coefficient is positive, or one is added to the highest-frequency DCT coefficient by the +1 adder 83 when the highest-frequency DCT coefficient is zero or negative. As shown in Figure 29, the magnitude increasing circuit 90 shown in Figure 17 may be substituted forthe LSB inverter 63 in the circuit shown in Figure 26. The circuit shown in Figure 26 is otherwise unchanged. The parity inverter shown in Figure 26, modified as shown in Figure 29, oddifiesthe sum of the DCT coefficientsaccording to equation (16), describedabove. Whenthe parity judpent circuit 21 generates the processing request signal REQl, the sum of the DCT coefficients in the block is oddified by feeding the highest-frequency DCT coefficient with its parity inverted to the IDCT circuit 15. The parity of the highest-frequency DCT coefficient is inverted in one of two ways: one is subtracted from the highest-frequency DCT coefficient by the -1 subtractor 93 when the highest-frequencyDCT coefficient is zero or negative, or one is added to the highest-frequency DCT coefficient by the +1 adder 92 when the highest-frequency DCT coefficient is positive. A second embodiment of the compressed motion picture signal expander will nowbe described. In the second embodiment of the compressed motion picture signal expander, the sumoddifying circuit 50 is substituted forthe sum oddifying circuit 35 in the first embodiment of the compressed motionpicture signaldecoder shown in, and describedabovewith reference to, Figure 19. The circuit shown in Figure 19 is otherwise unchanged. In the second embodiment of the compressed motion picture signal expander, the processing to oddify the sum of the DCT coefficients is carried out in a manner similar to the processing carried out by the sum oddifying circuit in the second embodiment of the motion picture signal compressor shown in, and described above with reference to, Figure 22. Thus, in the second embodiment of the compressed motion picture signal expander, it is unnecessary to feed the address EOB_adrs from the inverse variable-length coder 32 to the sum oddifying circuit 50. The invention described above makes it possible to realize an inverse discrete cosine transform method and an inverse cosine transform apparatus, a motion picture signal compressor, a compressed motion picture signal expander, and a transmitting apparatus for a compressed motion picture signal in which the probability of a mismatch error occurring in the course of inverse discrete cosine transform processing is reduced to the point at which mismatch errors do not occur in practice. Further, the invention makes it possible to realize a recording medium in which no mismatch error occurs when a compressed motion picture signal is reproduced from the medium and is expanded by processing including an inverse orthogonal transform. When a discrete cosine transform is used in compressing the motion picture signal and an inverse discrete cosine transform is used in expanding the compressed motion picture signal, the invention makes it possible to prevent inverse discrete cosine transform mismatch errors from occurring. This prevents deterioration of picture quality. Accordingly, in a motion picture signal compressor anda compressed motion-picture signal expander to which this invention is applied, there is nopossibility that the locally-decoded pictures in the compressor, and the pictures reconstructed by the expander are different from each other. Thus, a high picture quality can be provided. Although illustrative embodiments of the invention have been describedherein in detail, it is to be understood that the invention is not limitedto theprecise embodiments described, and that various modifications may be practiced within the scope of the invention defined by the appended claims.

Claims: CLAIMS 1. A method of processing a set of transform coefficients, each of the transform coefficients having parity, to provide an error-immune set of transform coefficients for processing by an inverse orthogonal transform, the error-immune set of transformcoefficients being immune to rounding errors when subject to the inverse orthogonal transform, the method comprising the steps of: summing the transform coefficients to provide a sum, the sum having parity; judging the parity of the sum; whenthe parity of the sum iseven, inverting the parity of one of the transform coefficients to provide a parity-inverted transformcoefficient, the parity-inverted transformcoefficient making the parity of the sum odd; and providingthe transform coefficients including the parity-invertedtransform coefficient as the error-immune set. 2. The method of claim 1, wherein: themethodis forprocessing transformcoefficients resultingfroma two-dimensional discrete cosine transform; the set of transform coefficients includes a transform coefficient representing a DC component; and in the step of inverting the parity of one of the transform coefficients, the parity of one of the transform coefficients other than the transform coefficient representing the DC component is inverted. 3. The method of claim 2, wherein: the set of transform coefficients also includes a transform coefficient representing a highest-frequency component; and in the step of invertingthe parity of one of the transform coefficients, the parity of the transform coefficient representing the highest-frequency component is inverted. 4. The method of claim 3, wherein: each transform coefficient in the set is represented by binary number having a least- significant bit; and in the step of inverting the parity of one of the transform coefficients, the least significant bit of the one of the transform coefficients is inverted. 5. The method of claim 2, wherein: each transform coefficient in the set has a polarity; and the step of inverting the parity of one of the transform coefficients includes the steps of: determining the polarity of the one of the transform coefficients, when the polarity is negative, adding a predetermined odd value to the one of the transform coefficients, and when thepolarity is positive, subtracting the predeterminedodd value from the one of the transform coefficients. 6. The method of claim 2, wherein: themethod additionally includes the step of receiving the transform coefficients in the set in serial order, the transform coefficients including a last-received transform coefficient; and in the step of inverting the parity of one of the transform coefficients, parity of the last-received transform coefficient is inverted. 7. Themethod of claim 1, wherein the transform coefficients in the set all have a value other than zero. 8. The method of claim 1, wherein: each transform coefficient in the set is represented by binary number having a least-significant bit; and in the step of summing the transform coefficients, only the least-significant bit of each transform coefficient is summed. 9. The method of claim 1, additionally comprising the step of selecting the transform coefficients in the set from a block of transform coefficients. 10. An apparatus for pre-processing a set of transform coefficients, each of the transform coefficients having parity, to provide an error-immune set of transform coefficients for processing by an inverse orthogonal transform, the error-immune set of transform coefficients being immune to rounding errors when subject to the inverse orthogonal transform, the apparatus comprising: an accumulator, the accumulator receiving each of the transform coefficients in the set and providing a sum havingparity; parity judpent means, receivingthe sum from the accumulator, for judgingthe parity of the sum; parity inverting means, operating when the parity judpent means judges that parity of the sum is even, for inverting the parity of one of the transform coefficients to provide a parity- inverted transform coefficient, the parity-inverted transform coefficient making the parity of the sum odd; and means for providing the transform coefficients including the parity-inverted transform coefficient as the error-immune set. 11. The apparatus of claim 10, wherein: the apparatus is for preprocessing a set of transform coefficients generated by a two- dimensional discrete cosine transform; the set of transform coefficients includes a transform coefficient representing a DC component; and the parity inverting means is for inverting the parity of one of the transform coefficients other than the transform coefficient representing the DC component. 12. The apparatus of claim 11, wherein: the set of transform coefficients also includes a transform coefficient representing a highest-frequency component; and the parity inverting means is for inverting the parity of the transform coefficient representing the highest-frequency component. 13. The apparatus of claim 12, wherein: each transform coefficient in the set is represented by binary number having a least- significant bit; and the parity inverting means includes means for invertingthe least significant bit of the one of the transform coefficients. 14. The apparatus of claim 10, wherein: each transform coefficient in the set is represented by binary number having a least- significant bit; and the accumulator includes means for summing only the least-significant bit of each transform coefficient. 15. The apparatus of claim 10, additionally comprising means for selecting the transform coefficients in the set from a block of transform coefficients. 16. A method of inversely orthogonally transforming a set of transform coefficients without incurring rounding errors, each of the transform coefficients being represented by a binary number having a least-significant bit, the method comprising the steps of: determining the least-significant bit of each of the transform coefficients; countingthe transformcoefficients having a least-significant bit of one to provide acount; judging when the count is an even number; when the count is an even number, changing one of the transform coefficients to provide a changedtransform coefficient, the changed transformcoefficient making the count an odd number; and inverselyorthogonally transforming the set of transform coefficients including the changed transform coefficient. 17. An apparatusfor inversely orthogonally transforming aset of transformcoefficients without incurring roundingerrors, each of the transformcoefficientshaving parity, the apparatuscomprising: means for summing the transform coefficients to provide a sum, the sum having parity; parity judging means for judging the parity of the sum; sum oddifying means, operating when the parity judging means judges that the parity of the sum is even, for inverting the parity of one of the transform coefficients to provide a parity- inverted transform coefficient, the parity-inverted transform coefficient making the sum odd; and aninverse orthogonaltransformcircuit receivingtheset of transformcoefficients, including the parity-inverted transform coefficient, from the sum oddifying means. 18. The apparatus of claim 17, wherein the sum oddifying means adds one to the one of the transform coefficientswhen the parity judging means judges that the parity of the sum is even. 19. The apparatus of claim 17, wherein: each transform coefficient has a polarity; and the sum oddifying means includes: polarity determining means for determining the polarity of each transform coefficient, means, operatingin response tothe, foradding one tothe transform coefficient when thepolarity determining meansdetermines that the polarity of the transform coefficient is positive, andforsubtractingonefrom the transformcoefficientwhenthepolaritydetermining means determines that the polarity of the transform coefficient is negative. 20. The apparatus of claim 17, wherein: each transformcoefficient in representedby a binary number having aleast-significant bit; and the parity judging means comprises: LSB detecting means for detecting the least-significant bit of each transform coefficient; anexclusive logical OR gate includingafirst input receivingthe least-significant bit ofeach transformcoefficient from the LSBdetectingmeans, asecond input, andanoutput; a register having an input connected to the output of the exclusive-OR gate and an output connected to the second input of the exclusive-OR gate; and a parity judging circuit connected to the output of the register. 21. An apparatusfor inversely orthogonally transforming aset of transformcoefficients without incurring rounding errors, each of the transform coefficients being represented by a binary number including a least-significant bit having a state, the apparatus comprising: least significant bit judgingmeansforjudgingthe state of the least-significant bit of each transform coefficient; counting means for providing a count by counting the transform coefficients, the least- significantbit whereof are judged by the least-significant bit judging meansto be in the one state; count judging means for judging when the count from the counting means is an even number; count oddifyingmeans, operatingwhenthe count judgingmeansjudges thatthecount isan even number, for changing one of the transform coefficients to provide a changed transform coefficient, the changed transform coefficient making the count an odd number; and an inverse orthogonal transform circuit, receiving the set of transform coefficients, including the changed transform coefficient, from the count oddifying means. 22. An apparatus for compressing a motion picture signal, the motion picture signal including pictures, each picture being divided into blocks, the apparatus comprising: predictive coder means forpredictively coding blocks of the motion picture signal by using matching blocks of a reference picture to form difference blocks; difference block encoding means for compressing the difference blocks from the predictive codermeansto for a compressedmotion picture signal, the difference blockencodingmeans including: orthogonal transform means for orthogonally transforming the difference block from the predictive coder means to provide blocks of transform coefficients; quantizing means for quantizing the blocks of transform coefficients from the orthogonaltransformmeanstoprovide compressedsignalblocks wherefromthecompressedmotion picture signal is derived; local decoding means for expanding the compressed signal blocks from the difference block encoding means to provide restored difference blocks without incurring rounding errors when the compressed signalblocks are inverselyorthogonally transformed, the local decoding means including; inverse quantizing means for inversely quantizing the compressed signal blocks from the differenceblockencodingmeansto provide blocksof restoredtransformcoefficients, each of the restored transform coefficients having parity, means for summing the restored transform coefficients in each block of transform coefficients from the inverse quantizingmeans to provide a sum, the sum having parity, parity judging means for judging the parity of the sum, sumoddifying means, operating when the parity judgingmeans judges that the parity of the sum is even, for inverting the parity of one of the restored transform coefficients intheblocktoprovide aparity-invertedtransformcoefficient, theparity-invertedtransform coefficient making the sum odd, and an inverse orthogonal transform circuit, receiving theblock of restored transform coefficients, including the parity-inverted transform coefficient, from the sum oddifying means, the inverse orthogonal transform circuit providing the restored difference blocks; predictive decoder means for predictively decoding the restored difference blocks from the local decoding meansto reconstruct picture blocks corresponding to the blocks of the motion picture signal; and a picture memory, the picture memory storing the reconstructed picture blocks from the predictive decoding means as blocks of a reconstructed picture for use as a reference picture for predictively coding other pictures of the motion picture signal. 23. The apparatus of claim 22, wherein: the apparatus is additionally for recording the compressed motion picture signal on a recording medium; and the apparatus additionally comprises: meansfor applying variable-lengthcoding to thecompressed signal blocks to derive the compressedmotion picture signal; meansforderivinga recording signalfrom the compressedmotionpicture signal; and means for recording the recording signal on the recording medium. 24. The apparatus of claim 22, wherein: the apparatus is additionally for transmitting the compressed motion picture signal via a transmission medium; and the apparatus additionally comprises: meansfor applying variable-lengthcoding to the compressed signal blocks to derive the compressedmotion picture signal; meansfor deriving atransmission signal from the compressedmotion picture signal; and means for transmitting the transmission signal via the transmission medium. 25. The apparatus of claim 22, wherein thepicturememory is asecondpicturememory, and the apparatusadditionally comprisesfirst picture memory, the first picture memory temporarily storing the motion picture signal; thepredictivecodermeans is orpredictively codingblocks ofthemotion picture signal read out from the first picture memory; the apparatus additionally comprises: variable length coding means for deriving the compressed motion picture signal by applying variable length coding to the compressed signal blocks from the difference block encoder means, and motion compensator means for detecting motion between the reconstructed pictures storedin the second picturememory andthe motionpicture signal stored inthe first picture memory, for applying motion compensation to already-reconstructed pictures stored in the second picture memory in response to the detected motion to derive blocks of one of the reconstructedpictures selected as a reference picture, and for providing the blocks of the reference picture to the predictive coder means. 26. The apparatus of claim 25, wherein: the apparatus is additionally for recording the compressed motion picture signal on a recording medium; and the apparatus additionally comprises: meansforderivinga recording signalfrom thecompressedmotionpicture signal, and means for recording the recording signal on the recording medium. 27. The apparatus of claim 25, wherein: the apparatus is additionally for transmitting the compressed motion picture signal via a transmission medium; and the apparatus additionally comprises: meansfor deriving a transmission signal from the compressed motion picture signal, and means for transmitting the transmission signal via the transmission medium. 28. An apparatus for compressing a motion picture signal, the motion picture signal including pictures, each picture being divided into blocks, the apparatus comprising: predictive coder means forpredictively coding blocks of the motion picture signal by using matching blocks of a reference picture to form difference blocks; difference block encoding means for compressing the difference blocks from the predictive codermeans to form acompressedmotionpicture signal, the difference blockencoding means including: orthogonal transformmeans fororthogonally transforming the difference blocks from the predictive coder to provide blocks of transform coefficients; quantizing means for quantizing the blocks of transform coefficients from the orthogonaltransformmeanstoprovide compressedsignalblocks wherefromthecompressedmotion picture signal is derived; local decoding means for expanding the compressed signal blocks from the difference block encoding means to provide restored difference blocks without incurring rounding errors when the compressed signalblocks are inverselyorthogonally transformed, the local decoding means including; inverse quantizing means for inversely quantizing the compressed signal blocks from the difference block encoder to provide blocks of restored transform coefficients, each of the restored transform coefficients being represented by a binary number including a least- significant bit, least-significant bit determining means for determining the least-significant bit of each of the restored transform coefficients, countingmeans forprovidingacount by countingthe restoredtransform coefficients having a least-significant bits of one in each block, count judging means for judging when the count from the counting means is an even number, count oddifying means, operating when the count judging meansjudges that the count is an even number, for changing one of the restored transform coefficients in the block to provide a changed transform coefficient, the changed transformcoefficient making the count an odd number, and an inverse orthogonal transform circuit, receiving each blockof restored transform coefficients, including the changed transform coefficient, from the count oddifying means, the inverse orthogonal transform circuit providing the restored difference blocks; predictive decoder means for predictively decoding the restored difference blocks from the local decoding means to reconstruct picture block corresponding to the blocks of the motion picture signal; and a picture memory, the picture memory storing the reconstructed picture blocks from the predictive decoding means as blocks of a reconstructed picture for use as a reference picture for predictively coding other pictures of the motion picture signal. 29. The apparatus of claim 28, wherein: the apparatus is additionally for recording the compressed motion picture signal on a recording medium; and the apparatus additionally comprises: meansfor applying variable-length coding to the compressed signal blocks to derive the compressedmotion picture signal, meansforderivinga recordingsignalfrom the compressedmotionpicture signal, and means for recording the recording signal on the recording medium. 30. The apparatus of claim 28, wherein: the apparatus is additionally for transmitting the compressed motion picture signal via a transmission medium; and the apparatus additionally comprises: meansfor applying variable-length coding to the compressed signal blocks to derive the compressed motion picture signal, means for deriving a transmission signal from the compressed motion picture signal, and means for transmitting the transmission signal via the transmission medium. 31. The apparatus of claim 28, wherein the picturememory is a second picture memory, and the apparatus additionally comprises first picture memory, the first picture memory temporarily storing the motion picture signal; thepredictivecodermeans is orpredictively codingblocks ofthe motion picture signal read out from the first picture memory; the apparatus additionally comprises: variable-length coding means for deriving the compressed motion picture signal by applying variable-length coding to the compressed signal blocks from the difference block encoder means, and motion compensator means for detecting motion between the reconstructed pictures storedin the second picturememory andthe motionpicture signal stored inthe first picture memory, for applying motion compensation to already-reconstructed pictures stored in the second picture memory in response to the detected motion to derive blocks of one of the reconstructedpictures selected as a reference picture, and for providing the blocks of the reference picture to the predictive coder means. 32. The apparatus of claim 31, wherein: the apparatus is additionally for recording the compressed motion picture signal on a recording medium; and the apparatus additionally comprises: means for derivinga recording signalfrom the compressed motionpicture signal, and means for recording the recording signal on the recording medium. 33. The apparatus of claim 31, wherein: the apparatus is additionally for transmitting the compressed motion picture signal via a transmission medium; and the apparatus additionally comprises: means for deriving atransmission signal from the compressed motion picture signal, and means for transmitting the transmission signal via the transmission medium. 34. An apparatus for expanding a compressed motion picture signal to provide a motion picture output signal, the compressed motion picture signal including signal portions each representing a picture of the motion picture output signal, the signal portions including variable-length coded compressed signal blocks, the apparatus comprising: an inverse variable-length coding means for applying inverse variable length coding to the variable-length coded compressed signal blocks to provide compressed signal blocks; decoding means for expanding the compressed signal blocks rom the inverse variable-length coding means to provide restored difference blocks without incurring rounding errors when the compressed signal blocks are inversely orthogonally transformed, the decoding means including; inverse quantizing means forinversely quantizing each compressed signal block from the difference block encoding means to provide a block of restored transform coefficients, each of the restored transform coefficients having parity, means for summing the restored transform coefficients in the block of transform coefficients from the inverse quantizingmeans to provide a sum, the sum having parity, parity judging means for judging the parity of the sum, sumoddifying means, operating when the parity judgingmeans judges that the parity of the sum is even, for inverting the parity of one of the restored transform coefficients intheblocktoprovideaparity-invertedtransformcoefficient, theparity-invertedtransfon- coefficient making the parity of the sum odd, and an inverse orthogonal transform circuit, receiving theblock of restored transform coefficients, including the parity-inverted transform coefficient, from the sum oddifying means, the inverse orthogonal transform circuit providing the restored difference blocks. 35. The apparatus of claim 34, wherein: the variable-length decoding means additionally provides a motion vector and motion compensation mode data; and the apparatus additionally comprises : predictive decoder means for predictively decoding the restored difference blocks from the decoding means to reconstruct picture blocks, apicture memory, the picture memory storing the reconstructed picture blocks from the predictive decoding means as blocks of a reconstructed picture for use as a reference picture for predictively decoding other pictures of the motion picture signal, means, operatingthe response to the motion vector and the motion compensation mode data from the inverse variable-length coding means, for performing motion compensation on already-reconstructed pictures stored in the picture memory to derive, from one of the already-reconstructed pictures selected as a reference picture, a block of the reference picture and to provide the block of the reference picture to the predictive decoder means, and means for reading the motion picture output signal from the picture memory. 36. An apparatus for expanding a compressed motion picture signal to provide a motion picture output signal, the compressed motion picture signal including signal portions each representing a picture of the motion picture output signal, the signal portions including a variable-length coded compressed signal blocks, the apparatus comprising: an inverse variable-length coding means for applying inverse variable length coding to the variable-length coded compressed signal blocks to provide compressed signal blocks; decoding means for expanding the compressed signal blocks from the inverse variable-length coding means to provide restored difference blocks without incurring rounding errors when the compressed signalblocks are inverselyorthogonally transformed, the local decodingmeans including; inversequantizing means for inversely quantizing each compressed signal block from the difference block encoderto provide ablock of restored transform coefficients, each of the restored transform coefficientsbeing represented by a binarynumber including a least- significant bit having a state, least-significantbit judging means for judging the state of the least-significant bit of each of the restored transform coefficients, counting means for providing a count by counting the transformcoefficients in the block, the least-significant bits whereof are judged by the least-significant bit judging means to be in the one state, count judging means for judging when the count from the counting means is an even number, count oddifying means, operating when the count judging meansjudges that the count is an even number, for changing one of the restored transform coefficients to provide a changed transform coefficient, the changed transform coefficient making the count an odd number, and an inverse orthogonal transform circuit, receiving theblock of restored transform coefficients, including the changed transform coefficient, from the count oddifying means, the inverse orthogonal transformcircuitprovidingthe restored difference block, the inverse orthogonal transform circuit providing the restored difference blocks. 37. The apparatus of claim 36, wherein: the variable-length decoding means additionally provides a motion vector and motion compensation mode data; and the apparatus additionally comprises : predictive decoder means for predictively decoding the restored difference blocks from the decoding means to reconstruct picture blocks, a picturememory, the picture memory storing the reconstructed picture blocks from the predictive decoding means as blocks of a reconstructed picture for use as a reference picture for predictively decoding other pictures of the motion picture signal, means, operatingthe response to the motion vector and the motion compensation mode data from the inverse variable-length coding means, for performing motion compensation on already-reconstructed pictures stored in the picture memory to derive, from one of the already-reconstructed pictures selected as a reference picture, a block of the reference picture and to provide the block of the reference picture to the predictive decoder means, and means for reading the motion picture output signal from the picture memory. 38. Amethodof compressingamotion picture signalto provide acompressedmotionpicture signal, the method comprising the steps of: applyingpredictioncoding andorthogonaltransformprocessing toblocks ofthenotionpicture signal to provide blocks of transform coefficientswherefrom the compressed motion picture signal is derived; and sum oddifying the blocks of transform coefficients prior to applying inverse orthogonal transformprocessingand predictiondecoding to theblocksof transformcoefficients to provideblocks of a reconstructedpicture for use as a reference picture in prediction coding other pictures of the motion picture signal. 39. Themethodof claim38, wherein the stepof sumoddifyingtheblocks of transformcoefficients comprises the steps of: summingthe transformcoefficients in each blockto provide asum, each transformcoefficient having parity, to provide a sum, the sum having parity; judging when the parity of the sum is even; and when theparity of the sum is judged to be even, inverting theparity of one of the transform coefficients in the block to make the parity of the sum odd. 40. The methodof claim 38, wherein: each transform coefficient is represented by a binary number including a least-significant bit; and the step of sum oddifying the blocks of transform coefficients comprises the steps of: determining the least-significant bit of each of the transform coefficients, counting the transform coefficients in the block having a least-significant bit of one to provide a count, and when the count is an even number, changing one of the transform coefficients in the block by one. 41. The method of claims 38, 39, or 40, wherein: the method is additionally for recording the compressed motion picture signal on a recording medium; and the method additionally comprises the steps of: providing a recording medium, deriving a recording signal from the compressed motion picture signal, and recording the recording signal on the recording medium. 42. The method of claims 38, 39, or 40, wherein: the method is additionally for transmitting the compressed motion picture signal via a transmission medium; and the method additionally comprises the steps of: providing a transmission medium, deriving a transmission signal from the compressed motion picture signal, and feeding the transmission signal into the transmission medium. 43. A method for compressing a motion picture signal to provide a compressed motion picture signal, the method comprising the steps of: detecting motion between blocks of a picture of the motion picture signal and blocks of a reconstructed picture signal serving as a reference picture; applying motion compensation to the reference picture in response to the detected motion to derive matching blocks of the reference picture; usingthe matching blocks of the reference picture to apply predictive coding to the blocks of the motion picture signal to provide block of differences; orthogonally transforming the blocks of differences to provide blocks of transform coefficients; deriving the compressed signal from the blocks of transform coefficients by applying quantizing and variable-length coding; prior to applying inverse orthogonal transform processing to the blocks of transform coefficients to provide blocks of restored differences, sum oddifying each block of transform coefficients to prevent rounding errors in the inverse orthogonal transform processing; and applying prediction decoding to theblocks of restored differences to providepicture blocks of a reconstructed picture for use as a reference picture in applying predictive coding to other pictures of the motion picture signal. 44. Themethodof claim43, wherein the stepof sumoddifyingtheblocks of transformcoefficients comprises the steps of: summingthe transformcoefficients in each blockto provide asum, each transformcoefficient having parity, to provide a sum, the sum having parity; judging when the parity of the sum is even; and when theparity of the sum is judged to be even, inverting theparity of one of the transform coefficients in the block to make the parity of the sum odd. 45. The method of claim 43, wherein: each transform coefficient is represented by a binary number including a least-significant bit; and the step of sum oddifying eachblock of transform coefficientscomprises the steps of: determining the least-significant bit of each of the transform coefficients, counting the transform coefficients having a least-significant bit of one in the block to provide a count, and when the count is an even number, changing one of the transform coefficients in the block by one. 46. The method of claims 43, 44, or 45, wherein: themethod is additionally for recordingthe compressedmotion picture signal on arecording medium; and the method additionally comprises the steps of: providing a recording medium, deriving a recording signal from the compressed motion picture signal, and recording the recording signal on the recording medium. 47. The method of claims 43, 44, or 45, wherein: the method is additionally for transmitting the compressed motion picture signal via a transmission medium; and the method additionally comprises the steps of: providing a transmission medium, deriving a transmission signal from the compressedmotion picture signal, and feeding the transmission signal into the transmission medium. 48. A recording medium whereon a compressed motion signal representing a motion picture is recorded, the compressed motion picture signal being derived from a motion picture signal by: applyingpredictioncoding andorthogonal transformprocessing toblocks ofthe motionpicture signal to provide blocks of transform coefficients wherefrom the compressed motion picture signal is derived; and sum oddifying the blocks of transform coefficients prior to applying inverse orthogonal transformprocessingand predictiondecoding to theblocksof transformcoefficients to provide blocks of a reconstructedpicture for use as a reference picture in prediction coding other pictures of the motion picture signal. 49. The recording medium of claim 48, wherein the blocks of transform coefficients are sum oddified by: summing the transformcoefficients in each blockto provide a sum, each transformcoefficient having parity, to provide a sum, the sum having parity; judging when the parity of the sum is even; and when the parity of the sum is judged to be even, inverting the parity of one of the transform coefficients in the block to make the parity of the sum odd. 50. The recording medium of claim 48, wherein each transform coefficient is represented by a binary number including a least- significant bit, and the blocks of transform coefficients are sum oddified by: determining the least-significant bit of each of the transform coefficients; counting the transform coefficients in the block having a least-significant bit of one to provide a count, and when the count is an even number, changing one of the transformcoefficients in the block by one.

Inventors: OKAZAKI TORU, SUDO TATSUYA, SUZUKI TERUHIKO, YAGASAKI YOICHI, OKAZAKI, TORU, SUDO, TATSUYA, SUZUKI, TERUHIKO, YAGASAKI, YOICHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: H04N7
IPC codes: G06F17, G06T9, H03M7, H04N1, H04N5, H04N7