Integrated logic circuit with a single ended input logic gate

Abstract: A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Description: The invention relates to an integrated logic circuit with differential pairs of inputs for supplying complementary signals. US patent No. 3,655,998 discloses a circuit with two input transistors, each having a control electrode coupled to a logic input from a different differential pair of inputs. Current from a current source is conducted either through the main current channel of a reference transistor or through main current channels of the input transistors, dependent on the logic signals at the control electrodes of the input transistors. The complements of the signals used to control the control electrodes of the input transistors are used to control the voltage at the control electrode of the reference transistor. If any one of those logic signals makes the main current channel of the corresponding input transistor conduct, the voltage at the control electrode of the reference transistor is made to change in the opposite direction, so as to make the reference transistor less conductive. This circuit is susceptible to noise when the voltage level at the inputs may vary, even if the logic state of the input signals (their difference) remains substantially the same. Another circuit is known from US 4,877,977 and is shown in Figure 1. This circuit furthermore comprises a first resistor, the main current channel of the reference transistor being coupled to the supply voltage terminal via the first resistor. A node between this main current channel and the first resistor forms an output O of the circuit. The main current channels of the input transistors may be coupled to the supply voltage terminal via a second resistor, a node between these main current channels and the second resistor forming a further output, complementary to the first mentioned output. In operation, when the voltage level at any one of the input connections A-D of this circuit becomes higher than that (V REF ) at the reference input REF, the voltage at the output O will become logic high. Hence the circuit may be used as an OR gate. This circuit is susceptible to noise, especially from the voltage supply. In this case, although the logic state of the signals at the inputs A-D does not change, the voltage level at these inputs A-D may vary, for example when the voltage supply relative to which they are defined varies. This problem is aggravated in the case of high-speed logic in which small signal-swings are required. As a more complicated alternative, use is made of Current-mode logic (CML) circuitry, such as shown in Colace, Electronic Product Design, January 1986, pages 43-46; Millman et al, "Pulse Digital, and Switching Waveforms", McGraw Hill Book Company, New York, 1965, pages 358-359; and Hamilton et al, "Basic Integrated Circuit Engineering", McGraw-Hill Book Company, New York, 1975, pages 492-497. CML is shown in Figure 2. The multi-level CML of Fig. 2 uses differential signal paths and is therefore hardly susceptible to noise due to variations in the voltage supply. However, CML requires different logic levels for inputs A,A and B,B. Emitter followers can be used to translate from the top level to the bottom level as shown in Fig. 2. The current-mode logic (CML), illustrated in Figure 2, offers high speed, but the required stacking of logic levels limits performance. This performance limitation is especially noticeable when a low voltage supply operation is necessary. For operation below two volts, for example, only two logic levels can be used. A four-input gate must be realized with a cascade of two-input gate leading to several gate delays and extra level shifts. Amongst others, it is an object of the invention to provide new logic circuitry operating under a low voltage at high-speeds. In particular, the new logic circuitry of the present invention enables operation with a supply voltage of 1 volt, while retaining differential logic with fewer devices and lower operating current. The logic integrated circuit according to the invention is characterized, in that at least one of the logic inputs is part of a differential pair of inputs, for supplying logically complementary signals to inputs of differential amplifier means, the differential amplifier means having an output coupled to a control electrode means of the reference transistor means, for driving a voltage level at said control electrode means to change in a direction opposite to a change in a voltage level at the logic input, as detected on the differential pair of inputs. Thus, if the logic input is high, the voltage introduced at the control electrode of the reference transistor is reduced, which together makes the main current channel of the reference transistor non-conductive. If none of the inputs of the input transistors is high the voltage at the control electrode of the reference transistor will be high. Accordingly the main channel of the reference transistor will conduct. The change in voltage level at the control electrode of the reference transistor increases the margin for noise in the voltage level at the logic input. The change in the voltage at the control electrode of the reference transistor itself depends on a differential signal and is therefore hardly susceptible to noise. Such new logic circuit operates at the high speed and low noise offered by CML circuitry, but with lower supply voltages. This structure enables a significantly increased speed advantage with less current and power-delay enhancement of multiple amounts. An embodiment of the circuit according to the invention is characterized, in that each of the logic inputs is part of a respective differential pair of inputs, each for supplying logically complementary signals to inputs of respective differential amplifier means, outputs of the respective differential amplifier means being coupled to the control electrode means for driving the voltage level at said control electrode means to change in a direction opposite to a change in a voltage level at the logic input, as detected on the differential pair of inputs of that respective differential amplifier means. Thus the effect of noise on any of the inputs is reduced. For the case when several logic inputs to the input transistors are high, then the differential amplifier means drive the transistor to duplicate the logic function with a single one of the logic inputs being high. The only difference is that with several logic inputs being high the amount of change of the voltage level at the control electrode of the reference transistor is increased. Preferably, the reference transistor means consist of a reference transistor, whose control electrode forms the control electrode means. But in principle, noise reduction can also be obtained if the reference transistor is replaced by a plurality of reference transistors with their main current channels connected in parallel, each differential amplifier means driving the control electrode of a respective reference transistor. This requires more circuitry than when the amplifier means are all connected to the control electrode of the same transistor, but may cause fewer saturation problems. Another embodiment of the invention is characterized, in that the differential amplifier means comprise a differential pair of transistors, with interconnected first main electrodes, the input connections of the differential pair of input connections being coupled to control electrodes of respective transistors of the differential pair of transistors, a second main electrode of the transistor of the differential pair of transistors which is coupled to the input of the single ended input logic gate being coupled to the control electrode means. The differential pair provides for a simple implementation of the differential amplifier means, which can operate at low supply voltages. For the case when several of the inputs to the input transistors are high, the voltage of the control electrode of the reference transistor can be pulled low enough to saturate common ones of the differential pairs of transistors, so that the speed of the logic will deteriorate. If necessary to prevent saturation it is therefore preferred to provide for limiting means to limit the amount of change of the voltage level at the control electrode of the reference transistor. A Schottky diode is preferably used to limit the voltage level change. Several single ended input logic gates with differential amplifier means connected thereto according to the invention may be cascaded in order to form more complicated logic circuits. The invention will be described in more detail with reference to the drawing figures in which: Figure 1 shows a prior art example of single-ended input logic which suffers from various problems; Figure 2 represents a prior art showing of a two input gate CML; Figure 3 is a circuit diagram of the new logic family of the present invention; and Figure 4 is an expanded version of the new logic family of the present invention. By way of example, the integrated circuit according to the invention will be illustrated as a new logic family implemented using bipolar transistors. The new logic family of the present invention operates within a supply range of 1 V BE plus 1 V CESAT , allowing a single-cell battery application. In Figure 3 the minimum operating voltage for one input transistor, such as Q 1 receiving V CC , is V BES + V I2 (the voltage across current source I 2 ). The voltage across I 2 can be as low as V CESAT , which may be approximately 0.1 to 0.2 volts. For V BE equal to 0.6 to 0.7 volts, the minimum V CC = 0.7 to 0.9 volts. This is only the lower supply limit, and the current can function up to the breakdown voltage of current sources I 1 and I 2 . The single-cell battery application can operate over the voltage 1.1 to 1.5 volts. The new-logic family of the present invention will operate properly with this supply, but the multilevel CML of the prior art will not. In the structure of the present invention, as illustrated in Figure 3, differential logic is maintained, however, fewer devices and less operating current are required. This is distinctive from the cascaded CML of the prior art. Figure 3 shows a schematic circuitry of a two-input version of the new logic. Transistors Q 1 Q 2 , and Q 3 form a structure similar to the single-ended logic of Figure 1. In the new logic of Figure 3, however, the voltage at the base of transistor Q 3 is driven by differential pairs of transistors Q 4 , Q 5 and Q 6 , Q 7 . This gate requires one more transistor than a two-input CML gate including second level buffers, but it can operate off of a lower supply voltage. The gate can be expanded to n inputs by adding input transistors in parallel with transistors Q 1 and Q 2 and adding differential pairs of transistors in parallel with transistor pair Q 6 , Q 7 . In Figure 3, if the input A to transistor Q 1 is high and the input B to transistor Q 2 is low, then current will flow through transistors Q 5 and Q 7 of the respective differential pairs of transistors Q 4 , Q 5 and Q 6 , Q 7 . The current through transistor Q 5 also flows through resistance R 3 to reduce the voltage at the base of transistor Q 3 . Since the voltage at the base of the transistor Q 1 , is high and the voltage at the bases of transistors Q 2 and Q 3 are low, then transistor Q 1 conducts and output O will be high and output O will be low. Outputs O and O are the logic gate outputs and can be connected to the inputs of the other gates in the desired logic design. This analysis is the same if input A is low and input B is high. If neither input A nor input B is high, then current flows through transistors Q 4 and Q 6 and the voltage at the base of the transistor Q 3 will be high. Then, where transistors Q 1 and Q 2 are off and transistor Q 3 is conducting, the output O will be low and the output O will be high. For both inputs A and B being high, then transistors Q 5 and Q 7 will conduct, duplicating the logic function that occurs with either input A or B being high. The only difference is that with both inputs being high, the voltage across R 3 is doubled. As more logic inputs are added, for example, inputs C and D in Figure 4, the voltage across R 3 increases with multiple high inputs. Eventually, the voltage at the base of transistor Q 3 can be pulled low enough to saturate transistors Q 5 , Q 7 , etc., and the speed of the logic will deteriorate. The Schottky diode D 1 may be used to limit voltage across R 3 to prevent saturation of the transistors. The Schottky diode may also be included across the resistance R 3 to limit swing. Figure 4 shows a schematic circuit diagram of the new logic family with a four-input gate. This circuit includes two additional input transistors Q 8 , Q 9 together with additional differential pairs of transistors Q 10 , Q 11 and Q 12 , Q 13 . These additional differential pairs of transistors are included with differential pairs of transistors Q 4 , Q 5 and Q 6 , Q 7 to drive transistor Q 3 and are coupled through transistor Q 3 to multiple inputs A, B, C, D for the respective transistors Q 1 , Q 2 , Q 8 , Q 9 . Operation of this circuitry is similar to that of Figure 3, but shows an increased input and driving arrangement for the new logic family. Further, it shows that any number n of input transistors with a similar number n of differential driving transistors will operate the circuitry. Ring oscillators may be used to compare the logic family performance of the prior art and the present invention. A nine-stage CML ring (representing three cascaded, four-input gates of the CML logic of Figure 2) may be compared to a seven stage ring of the new logic gate. The results are shown by comparison in the TABLE to provide a 36% speed advantage using 45% less current for the new logic. Since the CML gates of the prior art require a 2 volt supply versus a 1 volt supply for the new logic, a power-delay enhancement of 5.7 times is achieved. These advantages are achieved in addition to a more than 50% gate-area reduction due to fewer required devices in the new logic. INPUT GATE COMPARISON ITEM CML NEW LOGIC COMPARISON No of Stages 3 7 Osc. FREQUENCY 130 MHz 86 MHz Gate Delay 1.29 nSec 0.83 nSec 36% less delay CURRENT/GATE 165µA 90µA 45% less current Power-Delay Product 4.24pJ 0.745pJ 5.7X Supply voltage 2V 1V transistors/gate 27 18 resistors/gate 15 8 Additional speed can be obtained by combining the devices with common collectors into single tubs to reduce capacitance. For typical bipolar processing, the term "tubs" are known as isolated epitaxial pockets or diffusion areas for semiconductor manufacture. For example, from Figure 3, the transistors Q1 and Q2 can be combined in semiconductor manufacture of the logic, as well as the transistors Q5 and Q7 and Q4 and Q6. The Schottky diode also can be included in the Q5, Q7 tub. If the diode is not required to prevent saturation due to smaller swings or lower common-mode inputs, for example, then its removal can improve speed in the circuitry. Although the invention has been described in terms of bipolar transistors, it will be clear that it can also be realized using for example MOS FETs (more properly IGFETs).

Claims: An integrated logic circuit with differential pairs of inputs for supplying complementary signals ((A,_A), (B,_B)), the circuit comprising a single ended input gate comprising a current source (I1); at least two input transistors (Q1, Q2), each having a control electrode coupled to a logic input from a respective one (A,B) of the pairs of inputs; a reference transistor (Q3), main current channels of the reference transistor and the input transistor being coupled in parallel with each other between the current source and a voltage supply terminal; the circuit comprising a logic combination circuit (I2, I3, Q4, Q5, Q6, Q7, R3, D1) coupled to a control electrode of the reference transistor (Q3), for generating voltage level changes corresponding to a logic NOR of signals (A,B) at the logic inputs of the respective ones of the pairs of inputs and supplying said logic level changes to the control electrode of the reference transistor (Q3); characterized in that the logic combination circuit comprises differential amplifiers (I2, Q4, Q5), (I3,Q6, Q7), each differential pair of inputs ((A,_A), (B,_B)) being coupled to a respective one of the amplifiers (I2, Q4, Q5), (I3,Q6, Q7), outputs of the differential amplifiers (I2, Q4, Q5), (I3,Q6, Q7) being coupled together to form said voltage level changes. An integrated circuit according to Claim 1, characterized in that the differential amplifiers (I2, Q4, Q5), (I3,Q6, Q7) comprise a differential pair of transistors (Q4, Q5, Q6, Q7), with interconnected first main electrode, the input connections of the differential pair of input connections being coupled to control electrodes of respective transistors of the differential pair of transistors (Q4, Q5, Q6, Q7), a second main electrode of the transistor (Q5, Q7) of the differential pair of transistors which is coupled to the input (A, B) of the single ended input logic gate being coupled to the control electrode of the reference transistor (Q3). An integrated logic circuit according to Claim 2, characterized in that it comprises limiting means (D1, R3), connected to the control electrode of the reference transistor (Q3), for limiting an amount of change of the voltage level at said control electrode so as to prevent that any of the differential pairs of transistors becomes saturated. An integrated circuit according to Claim 3, wherein the limiting means comprise a Schottky diode (D1) connected in parallel to a resistor (R3) between the control electrode and the voltage supply terminal. An integrated circuit according to any one of the Claims 1 to 4 wherein the main current channel of the reference transistor (Q3) is coupled to the voltage supply terminal via a first resistor (R2), a first node between the main current channels of the reference transistor and the first resistor forming a first output of the single ended input logic gate. An integrated circuit according to Claim 5 wherein the main current channels of the input transistors (Q1, Q2) are coupled to the voltage supply terminal via a second resistor (R1), a second node between the main current channels of the input transistors (Q1, Q2) and the second resistor (R1) forming a second output of the single ended input logic gate, the first and second output forming the differential pair of inputs of a further single ended input logic gate circuit with further differential amplifiers connected thereto according to any one of the Claims 1 to 5. An integrated circuit according to any one of the Claims 1 to 6, the transistors being bipolar transistors.

Inventors: BLAUSCHILD ROBERT, LINEBARGER DANIEL, BLAUSCHILD, ROBERT, LINEBARGER, DANIEL
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1994
Main classification: H03K19
IPC codes: H03K19