a method of manufacturing a semiconductor device with a buried junction

Abstract: A method is disclosed for forming a first region (32) with conductivity of a first type (N) and second, buried region (30) with conductivity of a second type (P) which forms a junction with the first region (32). By first and second doping steps, impurities of a first (As) and a second (B) type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first (32) and second (30) regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region (32), and such that the concentration in the second region (30) will be substantially due to the second implantation step only. This process is compatible with a CMOS-process. The buried junction can be used for a Zener diode, a vertical bipolar transistor or a JFET.

Description: This invention relates to processes for manufacturing semiconductor devices, and in particular, to a method as defined in the preamble of claim 1. The present trend toward increased integration has led to designing integrated circuits which include, on a single semiconductor material chip, a large variety of electronic components having structural and functional features which may be widely different from one another. Thus, monolithic structures have been provided, including CMOS (Complementary Metal Oxide Semiconductor) circuits basically for processing digital signals, bipolar circuits basically for amplifying analog signals, power components of both the DMOS (Diffused Metal Oxide Semiconductor) and the bipolar types, for generating and controlling high voltages and large currents. Such structures are formed in large numbers on the same semiconductor material slice by means of several successive chemiophysical treatments which include, in a known manner, high-temperature treatments, deposition of insulative and conductive layers, chemical etching, implantation of dopants, etc.. In view of that each of the above steps is bound to contribute manufacturing faults in varying degrees, and increases the risk of breaking the slice, an important designer's task is to provide the largest possible number of components using a minimum of variations in the manufacturing process. In certain cases, a complex integrated circuit may require that buried Zener diodes, high-speed bipolar transistors, field-effect junction transistors, and other components be formed which need a buried region wherein the concentration and/or depth of the impurities can be determined with great accuracy and as independently as possible of variations in the processing parameters. To fill these demands, specific masking and doping steps should be employed, additionally to those already required for the formation of the other components of the integrated circuit. To avoid this, some compromising is occasionally accepted. For instance, in a process for manufacturing an integrated circuit which includes field-effect complementary transistors of the MOS (CMOS) type, a plurality of steps are provided for forming the N-type source and drain regions of the N-channel MOS transistors in the CMOS pairs, and a plurality of steps for forming the P-type source and drain regions of the P-channel MOS transistors in the CMOS pairs. In particular, this involves forming a mask to define the source and drain areas of the two transistors, implanting impurities of a first type such as arsenic, implanting impurities of a second type such as boron, and a thermal treatment, possibly in several successive steps to meet specific process requirements, in order to allow the implanted impurities to diffuse and to obtain N and P regions having specified depths and concentrations. To add Zener-type diodes, i.e. diodes with a predetermined reverse breakdown voltage, to an integrated circuit, it has been proposed of using, in overlapping relationship, the same N and P implants as mentioned above, in the same order in which they follow each other to form the source and drain regions of the CMOS transistors, based on the fact that boron has a greater coefficient of diffusion through silicon than arsenic. In actual practice, the following operations are performed: the mask that defines the source and drain areas of the N-channel transistors is also apertured to define the areas for the cathode regions of the diodes; arsenic atoms are implanted into the silicon through these apertures the same way as through the source and drain apertures; a heating step is carried out at a high temperature to initially diffuse the arsenic atoms; the mask which defines the source and drain areas for the P-channel transistors is also apertured to define areas for doping the anode regions of the diodes within the cathode areas; through these apertures, boron atoms are implanted in the silicon the same way as through the source and drain apertures for the P-channel transistors; and finally, a heating step is carried out at a high temperature to further diffuse the arsenic atoms and diffuse the boron atoms through the arsenic and underlying silicon until a buried region of the P type, which constitutes the active anode region of the diode is obtained, which forms a junction with the N region which constitutes the cathode region of the diode. It has been found that the Zener diodes thus obtained have a reverse breakdown voltage which varies within very broad limits, e.g. in the 5 V to 8 V range, according to such uncontrollable process parameters as the thickness of the thin isolation oxide which is usually grown on the silicon surface prior to the boron implantation, the concentration of arsenic atoms in the N region, and the boron implantation energy. In order to reduce this eccessive dependence of the breakdown voltage on the process parameters, it has been proposed of increasing the depth of the boron penetration into the N region by increasing the implantation dosage and/or energy. This yields, however, diodes which have a fairly gradual reverse breakdown characteristic due to a marked reverse current contribution from a tunneling effect at a low reverse voltage (2-4 V), and at all events, the source and drain regions of the P-channel transistors, which are formed by the same implantation, must also be modified, thereby introducing a deviation from the ideal design parameters of the CMOS pair. Similar problems to the above are encountered where high-speed bipolar transistors or junction field-effect transistors (JFET) are to be formed in the same integrated circuit without adding new process steps. A method according to the preamble of claim 1 is known from EP-A-0 160 919. Document EP-A-0160919 discloses a method for making a buried Zener diode wherein, first, a deep implant of p++ boron is made through a first chip area, next, a shallower p+ boron implant is made through a second area including the first area and, finally, an n++ arsenic implant is made through a third area including the first area and included in the second area. From document DE-A-2753704 a method is known for forming junction regions comprising an n-type doping step forming an n+ region, a deep, low dosage p-type implant forming an underlying p region and a shallow, high dosage p-type implant forming a p+ region; the two p-type implants are made into an area which includes the n+ region entirely. Document US-A-4536945 discloses a method wherein arsenic and boron are implanted together into a p-type region in an epitaxial layer and wherein boron diffuses through the p-type region to form a buried junction with the epitaxial layer. Another method is known from document EP-A-0250869 wherein three boron implants are provided with different doses and energies to form a plurality of p regions and wherein an n+ region is formed in some of the p regions. From document EP-A-0231811 a method is known wherein a first boron implant is made followed by an arsenic implant into the boron implanted region. It is the object of this invention to provide a method as indicated in the introduction, whereby a buried region can be obtained whose concentration and/or depth is only weakly dependent on process parameters, and therefore, a junction which has exact and reproducible electric characteristics. This object is achieved, according to the invention, by a method as defined and characterized in the first of the appended claims to this specification. The invention and its advantages can be more clearly understood from the following description of three structures of semiconductor devices obtained with the inventive method. This description should be taken by way of example and not of limitation with reference to the accompanying drawings, in which: Figure 1 is a sectional view through a portion of a chip, formed in a silicon wafer, showing a structure which includes a Zener diode obtained with the inventive method; Figures 2a-2e are sectional views showing a portion of the structure in Figure 1 through successive steps of the inventive method; and Figures 3 and 4 are sectional views showing the structure of a high-speed bipolar transistor of the NPN type and the structure of a junction field-effect transistor (JFET) obtained with the inventive method, respectively. The main steps of the process for forming the partly conventional structure shown in Figure 1, are briefly reviewed herein below with reference to Figure 1. A substrate, denoted by 10, of P-type monocrystalline silicon is implanted with impurities of the N type in some predetermined areas and impurities of the P type in other predetermined areas; a layer of N silicon, denoted by 11, is grown epitaxially at a high temperature on the substrate 10; during this step, the N- and P-type impurities implanted during the previous step will diffuse to form buried N+ regions, denoted by 12, and deep isolation P regions, denoted by 13. The epitaxial layer 11 may be enriched, if necessary, by means of subsequent doping and diffusing steps of N-type impurities; areas to be isolated from one another at the surface are defined using a local oxide growing technique (LOCOS); impurities of the P type and the N type are implanted in selected areas of the epitaxial layer 11; silicon dioxide regions, denoted by 19, are grown at a high temperature using the LOCOS technique, thereby isolating the previously defined area from one another; during this step, P+ regions, denoted by 20, are formed by diffusion of the impurities implanted in the previous step to complete the isolation regions, while delimiting portions of the epitaxial layer 11 therein, in this example two portions 11' and 11''; additional P-type regions are formed by implantation followed by diffusion to contain the N-channel transistor of the CMOS pair and the Zener diode, as respectively denoted by 15 and 17; and the gate isolators 22 and gate electrodes 23 of the transistors in the CMOS pair are formed from a thin layer of silicon dioxide, as obtained by thermal oxidation of the silicon, and a layer of polycrystalline silicon deposited over the thin oxide layer, respectively. At this stage, the process is continued through some characteristic steps of this invention which will be described in detail hereinafter with reference to Figures 2a to 2e, and which can be summarized as follows: in a first doping step, there are formed the source and drain N+ regions, denoted by 31, for the N-channel transistor in the CMOS pair; a cathode N+ region, denoted by 32, for the Zener diode; and an N+ region, denoted by 33, for contacting the area 11'' of the epitaxial layer in which the Zener diode is formed; and in a second doping step, there are formed the source and drain P+ regions, denoted by 27, for the P-channel transistor in the CMOS pair; an anode contact region 29 in the containment P region 17 for the Zener diode; and a buried region 30 which forms, together with the cathode N+ region 32, the active junction of the Zener diode. The process is then continued through the usual steps for forming an insulating layer and metallic contacts. In particular: an insulating layer 34 is formed which is apertured in selected areas for contacting a number of regions of the previously formed components; from a metallic layer previously deposited over the insulating layer 34, electrodes are formed in ohmic contact with said selected areas, including the anode 35A and cathode 35K electrodes and an additional electrode 35S of the Zener diode, and electric connection patterns, not shown, are formed between various circuit components; and a protective passivation layer and metallic areas for connecting the integrated circuit to external terminals, not shown, are formed. The characteristic steps of the inventive method will be described with reference to Figures 2a to 2e, where Figure 2a shows that area of the chip which is to accommodate the Zener diode, as it appears after the containment P region 17 is formed. The surface resistivity of this region, to be obtained by boron implantation and subsequent diffusion, has a value in the 1000 to 3000 ohm/square range, preferably in the 1500 ohm/square range. A photoresist mask 40 extends across the surface of the region 17 to leave an area, denoted by 36, exposed for accommodating the cathode region, as well as an area, denoted by 37, for accommodating an additional region of the diode, and extends over the remainder of the structure, not shown in Figure 2a, to leave but those areas exposed through which impurities of the N type are to be introduced, specifically the areas intended to accommodate the source and drain regions of the N-channel transistors in the CMOS pairs. The wafer surface is then subjected to implantation of arsenic ions at a dosage in the 1x10 15 to 1x10 16 ions/cm 2 range, preferably of 2x10 15 ions/cm 2 , and energy of around 50 keV. Notice that, before the masking and implantation steps, it may be convenient, as a rule, to form a thin layer of silicon dioxide over the areas to be implanted. The mask 40 is then removed, and the wafer is subjected to a thermal treatment, e.g. at 1000°C for a 20 min period, to promote an initial diffusion of the arsenic through the silicon until a layer resitivity in the 20 to 60 ohm/square range is obtained. During this step, which is carried out in the presence of oxygen, a thin layer 41 of silicon dioxide forms. e.g. 50 nm thick as shown in Figure 2b, which also shows in broken lines the N+ regions formed by this initial diffusion. A further photoresist mask 42 is then formed which leaves a portion of the area 36 and other areas, not shown in Figure 2c, exposed through which impurities of the P type shall have to be introduced, in particular the areas for the source and drain regions of the P-channel transistors of the CMOS pairs. Thereafter, the wafer surface is subjected to a doping operation which is comprised of two successive steps, namely: a first step wherein boron ions (B) at a high dosage and low energy are implanted, as depicted in Figure 2c, e.g. 1x10 15 to 5x10 15 ions/cm 2 at 10 to 35 keV, preferably 2x10 15 at 20 keV, and a second step of boron implantation at a low dosage and high energy, as depicted in Figure 2d, e.g. 1x10 14 to 2x10 15 ions/cm 2 at 55 to 100 keV, preferably 1x10 15 ions/cm 2 at 70 keV. The wafer is then subjected to a further thermal treatment, e.g. at 1000°C for a 15 min period, preferably in the course of the operation for reflowing the vapor-phase deposited isolating layer 34 of silicon dioxide, thereby to form the buried P+ region 30, as shown in Figure 2e. According to the invention, the dosages for implantation are selected to avoid a compensation, or even a reversal, in the conductivity of the N+ region obtained by implantation and diffusion of arsenic. In particular, the first implanting step is adjusted to provide the layer resistivity sought and, hence, a low contact resistance in those areas where a ohmic contact is to be established between the P+ region and metal for the electrodes, as well as not to contribute toward the formation of the junction. The retarding action on the boron diffusion of arsenic at a high concentration is utilized for the purpose, so that most of the implanted boron atoms will be confined within the cathode region, which is an inactive region of the diode, that is one that bears no active influence on the production of the reverse breakdown voltage. On the other hand, the second implantation step, being a high energy one, allows boron atoms to be introduced beyond the implanted and pre-diffused N+ area. Such atoms are, therefore, unaffected by the retarding action of the high-concentration arsenic atoms during the diffusion, and little affected by the process parameters. Thus, the concentration can be accurately controlled in the P+ region, which is the active region of the diode, to accurately determine the reverse breakdown voltage. As may be appreciated, this is accomplished using no additional masking, since the two implantation steps can be carried out through the one aperture in the same mask as is used to form other integrated circuit components as well, such as the source and drain regions of the P-channel transistor of the CMOS pairs. Notice that the two implantations add together here to result in diffused regions which are quite similar to those to be obtained with a single implantation carried out at a dosage equal to the sum of the dosages used in the two implantation steps. It should be understood, moreover, that the two boron implantation steps may be reversed, to obtain the same result, and if necessary, divided in turn into two or more sub-steps at different dosages and/or energies, in order to better control the concentration and depth of the buried region or to take account of special doping requirements of some regions of the integrated circuit, for example. As for the additional electrode 35S, it functions to pick up any stray currents arising in the device while in operation. Specifically, notice that the N+ region 32 and region 11'' respectively constitute the emitter and collector regions of an NPN transistor whose base is formed by the regions 30 and 17. In order to control this transistor, the additional electrode 35S should be biased by connecting it, according to individual applications, to the anode electrode 35A or the cathode electrode 35K or a voltage source of suitable value. In the example shown in Figure 3, the method of this invention has been used to produce a high-speed bipolar transistor of the NPN type. In this case, the implantation and diffusion step which results in the containment P region of the N-channel CMOS transistor and the containment region of the Zener diode being formed as shown at 15 and 17, respectively, in Figure 1, is utilized to form a guard ring, denoted by 45 in Figure 3, the operations which result in the source and drain regions of the N-channel CMOS transistor and the cathode region 31 and 32, respectively, being formed, are utilized to form the emitter region 46 and collector contact region 47 of the transistor, and the operations which yield the source and drain regions 27 of the P-channel CMOS transistor, the buried region 30 of the diode, and the diode anode contact region 29 are utilized to provide the buried base region 48 and base contact region 49 of the high-speed NPN transistor. The emitter E, base B and collector C electrodes are formed by the same operations as are carried out to form the other contact electrodes of the integrated circuit. Likewise, in the example of Figure 4, the inventive method is used to produce a junction field-effect transistor (JFET). In this case, through the same operations as are required to make the region 15 of Figure 1, two regions, 50 and 51, are obtained which constitute the source and drain regions, respectively, of the JFET transistor; through the same operations as are required to make the cathode region 32 of the diode, the gate region 52 is formed; and the same operations as are required to make the buried region 30 of the diode in Figure 1 are also utilized to provide the channel region 54 of the JFET transistor. The source, drain and gate electrodes are denoted by S, D and G, respectively. It will be appreciated that the base region 48 of the high-speed NPN transistor in Figure 3 and the channel 54 of the JFET transistor in Figure 4 can also be formed, for the same reasons as have been discussed in connection with the diode of Figure 1, with the same great accuracy and excellent repeatibility characteristics as the anode region 30 of the diode. However, since the three components have widely different functional characteristics, it may happen that process parameters, in particular the implantation dosages and energies for forming the N+ and P+ regions, once selected to impart optimum characteristics to one of the three components, are not appropriate to ensure as optimum characteristics for the other two components as well. In such cases, therefore, said parameters would have to be adjusted for an acceptable compromise. While only three possible applications of the inventive method have been described hereinabove, it should be understood that this method could also be used for other applications, namely, to produce any components requiring that a buried junction of the same kind as described be formed in a highly accurate and repeatible manner.

Claims: A method of forming, on a chip of semiconductor silicon material, a structure which includes a first region (32) having n-type conductivity bounded by a major surface of the chip and a second region (30) having p-type conductivity, being buried in the chip under said first region and forming a buried junction with the first region (32), which method comprises: a first doping step of implanting arsenic into a predetermined area of the major surface of the chip; a second doping step of implanting boron into a portion of said area comprising at least one sub-step of implanting boron at a high dosage and low energy, and at least one sub-step of implanting boron at a low dosage and high energy; and a high-temperature treatment step for diffusing the arsenic and boron introduced by the first and second steps through the chip, thereby forming said first (32) and second (30) regions; wherein the second doping step and the high-temperature treatment step are also utilized to form a third region (29) with p-type conductivity bounded by the major surface of the chip and separated from the first region (32); and is characterized in that the second doping step is carried out after the first doping step, the dosages and energies are selected such that the n-type conductivity of the first region (32) is neither compensated nor reversed by the second doping step, and such that the concentration of impurities in the second region (30) is substantially due to the low dosage, high energy implantation sub-step(s) only, and the high-temperature treatment step comprises a first sub-step subsequent to the first doping step and preceding the second doping step, and a second sub-step following the second doping step. A method according to Claim 1, wherein, prior to the first and second doping steps, a containment region (17) with p-type conductivity is formed which is bounded by the major surface of the chip and adapted to contain said first, second and third regions; and wherein first (35K) and second (35A) electrodes are formed in ohmic contact with the chip surface, in the first (32) and third (29) regions thereof, respectively, to provide terminals of a diode having a predetermined reverse breakdown voltage. A method according to Claim 2, wherein said containment region (17) is formed in a chip region (11'') with n-type conductivity; wherein the first doping step and the high-temperature treatment step are also utilized to form a fourth region (33) with n-type conductivity bounded by the major surface of the chip and separated from the containment region (17); and wherein a third electrode (35S) is formed in ohmic contact with the chip surface in the fourth region (33) thereof. A method according to Claim 1, wherein, prior to the first and second doping steps, a guard region (45) with p-type conductivity is formed which is bounded by the major surface of the chip surrounding the first region (46) and contacting the second region (48); wherein the third region (49) is located in the guard region (45); wherein the first doping step and the high-temperature treatment step are also utilized to form a fourth region (47) with n-type conductivity bounded by the major surface of the chip and separated from the guard region (45); and wherein electrodes are formed in ohmic contact with the chip surface in the first region (46), the third region (49), and the fourth region (47) forming the emitter (E), base (B) and collector (C) terminals, respectively, of a bipolar transistor. A method according to Claim 1, wherein, prior to the first and second doping steps, two regions (50, 51) with p-type conductivity are formed which are bounded by the major surface of the chip, along two opposed sides of the first region (52) and in contact with the second region (54); wherein the second doping step and the high-temperature treatment step are also utilized to form a fifth region (56) bounded by the major surface of the chip together with said third region (55), each in one of said two regions on the first region (52) sides; and wherein electrodes are formed in ohmic contact with the chip surface in the first region (52) thereof, and in each of the third and fifth regions (55, 56) forming the gate (G), source (S) and drain (D) terminals, respectively, of a junction field-effect transistor (JFET).

Inventors: DEPETRO RICCARDO, PALMIERI MICHELE, DEPETRO, RICCARDO, PALMIERI, MICHELE
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27