Data interface for closed-loop accelerometer

Abstract: A closed-loop accelerometer (10) has a rebalance loop (14) controlled by a first clock and the output of which loop is supplied to a utilization circuit (24) controlled by a second clock (22). The loop and the utilization circuit are coupled by a converter which converts the output of the loop into a stream of pulses distributed over one accelerometer rebalance-cycle period, these pulses being sampled over the period of the second clock and counted to produce a count which is delivered to the utilization circuit (24). There are means (29) responsive to the output of the second clock (22) for gating the pulse count to the utilization circuit (24).

Description: The present invention relates to apparatus and methods for facilitating utilization of the acceleration data output of a closed-loop accelerometer. More particularly, this invention pertains to apparatus for converting the acceleration output to a form that is compatible with output data rates whose frequency is unrelated to the period of the accelerometer rebalance loop. Many accelerometers include a pendulous proofmass for sensing acceleration relative to inertial space. Motion of the proofmass relative to the body of the accelerometer (and the object attached thereto) is induced by acceleration and the displacement of the proofmass provides a measure of the acceleration force. Such systems are known from, for example, US-A-5235330 and US-A-4282470. The displacement versus acceleration characteristic of an accelerometer may be highly nonlinear. Such nonlinearity may be due to a number of factors. For example, in a silicon accelerometer that employs a hinged floating element between a pair of conductive plates, an inverse square relationship governs the force exerted upon the pendulous mass as it travels through the gap between charged conductive plates. Nonlinearities may also be introduced through the bending characteristics of the hinges that attach the pendulous mass to the body of the accelerometer. Such second order effects can produce a nonlinear stiffness response in the bent hinge as the pendulous mass is deflected through the gap. In order to improve the accuracy of such accelerometers, they are therefore often operated in a closed-loop fashion. The force then required to maintain the null position of the pendulous mass, rather than displacement, provides the measure of acceleration. A so-called rebalance loop is employed for this purpose and many rebalance techniques are feasible. Generally, the most effective techniques would employ a modulation and forcing process that takes place at a specific frequency. The output of the accelerometer may be represented by a digital value that is equal to the duty cycle of the voltage rebalance waveform in voltage rebalance schemes. Alternatively, the digital value may represent the number of charge quanta applied in charge rebalance schemes. Systems of the above type are often subject to problems arising from inconsistencies between the accelerometer rebalance-cycle period and the data rate of the output utilization circuit. The rebalance-cycle period is fixed as is the output data rate and the resulting mismatches can lead to severe synchronization problems. According to one aspect of the present invention, there is provided apparatus for converting the output of a closed-loop accelerometer of the type that includes a rebalance loop of a first rebalance-cycle period to a form for use in a utilization circuit of a second cycle period and in which the accelerometer output is a value comprising a number of digital data bits representing acceleration during at least one accelerometer rebalance-cycle period, said apparatus being characterised by: a) means for receiving said value; b) means for converting said value into a stream of pulses distributed over one accelerometer rebalance-cycle period; c) means for sampling said stream of pulses over said second cycle period; d) means for counting said sampled pulses; and e) means for delivering said pulse count to said utilization circuit. The receiving means may comprise a register for receiving the value, which register includes a plurality of stages arranged to store respective digital data bits of the value. The means for converting may include a plurality of divide-by-two counters. There may be a plurality of gates arranged to control the passage of respective divide-by-two counter outputs in accordance with the state of the stage of the register. A trigger circuit may be provided for providing pulses of predetermined duration in response to the outputs of the gates. A pulse counter may be provided as the counting means for the pulses. The means for delivering the pulse count to the utilization circuit may include means responsive to the output of a second clock, which controls the second predetermined period of the utilization circuit, for gating the counts of the counter. It is noted that, in this example, the first predetermined rebalance-cycle period is controlled by a first clock while the second predetermined cycle period of the utilization circuit is controlled by a second clock. According to another aspect of the invention, there is provided a method of converting the output of a closed-loop accelerometer of the type that includes a rebalance loop of a first rebalance-cycle period to a form for use in a utilization circuit of a second cycle period and in which the accelerometer output is a value comprising a number of digital data bits representing acceleration during at least one prior accelerometer rebalance-cycle period, said method being characterised by the steps of: a) receiving said value; b) converting the received value into a stream of pulses distributed over one accelerometer rebalance-cycle period; c) sampling said stream of pulses over said second cycle period; d) counting the sampled pulses; and e) delivering the resulting pulse count to said utilization circuit. The value may be received in a register which includes a plurality of stages, the value being arranged within the register so that the digital data bits are stored in respective register stages. The value may be converted into a stream of pulses distributed over one accelerometer rebalance-cycle period by means of an arrangement that includes (i) a plurality of divide-by-two counters, (ii) a plurality of gates, arranged to control the passage of respective divide-by-two counter outputs in accordance with the state of the stages of the register and (iii) a trigger circuit that provides predetermined duration in response to the outputs of the gates. The pulse count may be delivered to the utilization circuit by gating the count of the counting means in response to the output of a second clock, when such second clock is provided for control of the second predetermined cycle period while a first clock controls the first rebalance-cycle period. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, wherein: Figure 1 is a block diagram of a closed-loop accelerometer in accordance with the prior art; Figure 2 is a block diagram of an accelerometer incorporating apparatus in accordance with the invention; Figure 3 is a schematic diagram of a converter of the apparatus of Figure 2; and Figures 4(a) through 4(k) show a set of waveforms for illustrating the operation of the accelerometer of Figure 2 with particular reference to the digital-to-pulse converter of Figure 3. Figure 1 is a block diagram of a closed-loop accelerometer arrangement in accordance with the prior art. As shown, acceleration in the direction of a sensitive axis of an accelerometer is sensed by means of a hinged pendulous mass 10, tending to cause deflection thereof from a predetermined null position. Such deflection is sensed by a pick-off arrangement 12 that may comprise any of a number of well known optical, magnetic, electro-static or like devices. The pick-off arrangement 12 acts as a transducer, providing an electrical error signal to a rebalance loop 14 that is driven by a clock 16 of fixed frequency f 1 . The rebalance loop 14 determines an appropriate rebalance force, in accordance with the error signal output of the pick-off 12, for actuating a rebalance forcer 18 which may comprise any of a number of conventional mechanical, electrical or magnetic devices to return the pendulous mass 10 to null. The same signal that drives the forcer 18 also provides the acceleration measurement to an output port 20. Such signal contains a number in digital format (i.e. a sequence of digital data bits) representing the value of acceleration during an accelerometer rebalance cycle. The number is descriptive of the measured force calculated by the rebalance loop 14. For example, in the event that pulse-width modulation of the pendulous mass is employed, the number would describe the duration or period of the forcing or nulling signal for driving the forcer 18. Each accelerometer rebalance cycle is generally divided into two periods. These include a measurement and computation period for the rebalance loop 14 to calculate the rebalance signal (equal, of course, to the measure of acceleration in a closed loop system) and a second period during which the forcer 18 is energized by the modulation signal to act upon the pendulous mass 10. The latter period may end some time prior to the end of the rebalance cycle if, for example, the calculated duration of actuation of the forcer 18 (in a pulse-width modulated system) is less than the duration of the remaining accelerometer-rebalance cycle. This type of cycle is repeated over and over as the pendulous mass 10 is continually returned to the null position despite the presence of an acceleration force. As mentioned above, a problem often arises as a result of the a.c. driving of the rebalance loop 14. The rebalance cycle of the rebalance loop 14 often differs from, and is not an integer multiple of, the output data rate of the utilization circuit (not shown in Figure 1). Accordingly, severe synchronization problems, producing noise and jitter, will periodically occur as the utilization circuit employs the data output from the accelerometer. Figure 2 is a block diagram of an accelerometer that includes a converter 26 in accordance with one example of the invention for converting accelerometer data output, taken periodically over predetermined accelerometer rebalance cycles, to a form that is compatible with output utilization circuitry of a second predetermined period clocked by a clock 22 of frequency f 2 which may or may not equal, or bear a rational relationship to, f 1 . Without the converter 26, the acceleration data provided to the utilization circuit 24 would be inherently in error, causing jitter and noise therein. Further, such error would be periodically cumulative as the disparity between the time of measurement and calculation of the acceleration data and the time of utilization thereof would periodically increase. In this example, the converter 26 formats the accelerometer output data so that, regardless of the accelerometer rebalance cycle, the utilization circuit 24 will be continually provided with data representative of only that portion of acceleration that took place during a period of length equal to the utilization cycle of the utilization circuit 24 rather than during a "complete" accelerometer rebalance cycle. Returning to Figure 2, the conversion of data is accomplished by means of a digital-to-pulse converter 26 that accepts the digital output of the accelerometer and transforms it into a stream of pulses equal in number to the digital accelerometer output and spread over one accelerometer rebalance cycle. The output of the converter 26 is then fed to a counter 28 through a high speed system sampling switch 30 controlled by the utilization circuit clock 22. Upon passage of the pulse stream to the counter 28, a digital word or count is then generated. This digital value is provided to the utilization circuit 24 by a sampling means 29 controlled by the output of a divide-by-N counter 31. The divide by-N counter 31 establishes the data rate of the utilization circuit 24 by dividing the clock 22 frequency f 2 by a predetermined value N. When closed (upon arrival of an "end of cycle" signal from the counter 31) the switch 29 latches the state of the counter 28 and provides the contents of counter 28 to the utilization circuit 24. After such instantaneous closure, the switch 29 returns to an open state, thereby resetting the counter 28. Figure 3 is a schematic diagram of the digital to-pulse converter 26 that is incorporated within the apparatus. The converter 26 includes a register 32 that is clocked by the accelerometer clock 16 and receives the digital words from the rebalance loop 14 that represent the signal applied to the forcer 18 and, consequently, the value of acceleration measured during the prior accelerometer rebalance cycle. A bank 34 of divide-by-two counters receives the output of the accelerometer clock 16. As will be discussed below, the plurality of counters is arranged serially to accept the output of the clock 16 and thereby to provide a plurality of signals of differing frequencies which, when gated (through a network 36 of gates) by the digital word stored in the register 32 on a stage-by stage basis, generates the signal for actuating a trigger circuit 38 that outputs the stream of pulses to the switch 30 of Figure 2. A discussion of the operation of the digital to-pulse converter 36 will follow in which reference is simultaneously made to the structure illustrated in Figure 3 and to the set of waveforms shown in Figures 4 (b) through 4 (k). More particularly, the discussion of the converter will be simplified by considering only limited portions of the register 32, the bank 34 of counters and the gate network 36. In the example that follows, reference will be made to the initial divide-by-two counters 40, 42 and 44 of the bank 34, stages 46, 48 and 50 of the register 32 and gates 52, 54 and 56 of the gate array 36 only. However, it will be evident from the discussion that the mode of operation of the digital-to pulse converter 26 can be straightforwardly and readily extended to registers, gate arrays and banks of counters of greatly increased sizes, provided that equal numbers of register stages, gates and counters are available for effecting the processes illustrated. Of course, "excess" register stages and the like, though non-functional in terms of the operation of the converter, may be present in the equipment actually employed for performing the described functions. Figures 4(a) through 4(k) provide an illustration of the manner in which the value representing force as determined by the rebalance loop 14 is converted by the digital-to-pulse converter 26 to a form that is compatible with the period of the utilization circuit 24 to thereby eliminate the problems of noise and jitter due to mismatch between the accelerometer rebalance cycle and the period of the utilization circuit 24. (For purposes of illustration only, it shall be assumed that the clock frequencies f 1 and f 2 are identical. This assumption affects only the portion of the discussion that accompanies Figure 4(k) and it will be readily appreciated that the relationship between the clock frequencies f 1 and f 2 is not central to the application, it being understood that this design arises from a need to deal with a mismatch between the accelerometer rebalance cycle and the period of the utilization circuit.) Since the sets of waveforms, for purposes of clarity, relate solely to the first three elements of the register 32, the counter bank 34 and the gate array 36, in Figure 4(a) there is illustrated the three states of the stages 46, 48 and 50 of the register 32 taken over three consecutive rebalance cycles. Each state comprises a number defining the value of modulation calculated by the rebalance loop 14 and applied by the forcer 18 to the pendulous mass 10. The three modulation values are "2", "4", and "5" respectively and the corresponding binary representations thereof, loaded into the first three stages of the register 32, are shown in Figure 4(a). Assuming that pulse-width modulation is employed by the closed loop system, each modulation value defines the duration of the driving pulse applied to the forcer 18. The waveforms of Figure 4(b) illustrate the modulation pulses 58, 60 and 62 for driving the forcer 18 during accelerometer rebalance-cycles 1, 2 and 3 respectively. The three pulses represent at the same time the calculated acceleration force of the closed-loop system. It may be noted that, for each accelerometer rebalance cycle, there exists an initial "dead" period for computation of modulation that precedes the application of the modulation signal to the forcer 18. The waveform 64 of Figure 4(c) represents the output of the accelerometer clock 16 which, as mentioned earlier, is of frequency f 1 and period 1/f 1 . In the illustrated example, the period of the clock 16 is one eighth that of an accelerometer rebalance cycle as there exist eight clock pulses per acceleration rebalance cycle. The waveforms 66, 68 and 70 shown in Figures 4(d) through 4(f) represent the outputs of the divide-by-two counters 40 through 44 respectively. Each of such serially-arranged counters divides the frequency of a signal originating with the output of the clock 16 in half, such division beginning with the counter 40. The frequencies of the resultant waveforms 66, 68 and 70 output by the counters 40, 42 and 44 are 4, 2 and 1 square waves per accelerometer rebalance cycle respectively. The waveform output by each of the counters comprises a regularly-spaced pattern. Downwardly-directed arrows at the trailing edge of each square wave of Figures 4(d) through 4(f) indicate the points in time for actuating the trigger circuit 38 to output a pulse (discussed below). Figures 4(g), 4(h) and 4(i) comprise a set of waveforms that illustrate the outputs of the gates 52, 54 and 56 respectively. The sets of vertical lines 72 and 74 of Figures 4(g) and 4(h) along with the single vertical line 76 of Figure 4 (i) illustrate and locate the downgoing or triggering edges of pulses transmitted through the gates 52, 54 and 56 respectively. (For purposes of clarity, only the downgoing or triggering edge of each pulse transmitted through a gate is shown since, as discussed above, only downgoing edges serve to actuate the trigger 38 to output individual pulses of a pulse train for application to the counter 28 shown in Figure 2.) Referring back to Figure 3, each of the gates 52, 54 and 56 accepts both an output stream from the bank of counters 34 and a state from a stage of the register 32, each gate defining a unique correspondence therebetween. As such, the gate 52 accepts the outputs of the "first" divide-by two counter 40 and the "first" register stage 46, the gate 54 accepts the outputs of the "second" divide-by-two counter 42 and the "second" register stage 48 and the gate 56 accepts the outputs of the "third" divide-by-two counter 44 and the "third" register stage 50. The pulse waveform 78 of Figure 4 (j) indicates the stream of pulses output by the pulse trigger 38. It is noted that, during accelerometer rebalance-cycle 1, the gate 52 receives only a "low" (or "O") output from the stage 36 of the register 32 which, for purposes of convention, blocks the output of the associated divide by-two counter 40. This is in contrast to the operation of the gate 52 during accelerometer rebalance-cycle 2. During that cycle, a "high" or "1" signal from the stage 46 of the register 32 gates through the output of the divide-by-two counter 40. As a result, four pulse triggering, downgoing edges from the square waveform illustrated in Figure 4(d) pass through the gate 52 during that rebalance cycle and, for the same reason, another four pulse-triggering edges from the waveform of Figure 4(d) pass through the gate 52 during accelerometer rebalance cycle 3. Referring to Figure 4(h) which illustrates the output of the gate 54, two downgoing, pulse-triggering, edges, taken from the output of the divide-by-two counter 42, pass through that gate during accelerometer rebalance cycle 1 as a consequence of the high state of the stage 48 of the register 32. The low states of that stage during accelerometer rebalance-cycles 2 and 3 act to block passage of the waveform output, and, consequently, pulse triggering-edges, from the divide-by-two counter 42 during those latter cycles. Finally, referring to 4(i), the low states of the stage 50 block the passage of pulse triggering, downgoing edges through the gate 56 during accelerometer rebalance cycles 1 and 2. However, the high state of the stage 50 during accelerometer rebalance cycle 3 controls the gate 56 to output a single downgoing pulse-triggering edge from the counter 44 (waveform illustrated in Figure 4(f)) during accelerometer rebalance cycle 3. The above-identified downgoing pulse-triggering edges are applied in parallel to the pulse trigger 38. As shown in Figure 4(j) each of these edges causes the trigger circuit 38 to output a pulse. As can be seen by counting the number of pulses in Figure 4(j), two (2) pulses appear at the output of the trigger circuit 38 during accelerometer rebalance-cycle 1 (corresponding to the binary value (010) stored in the register 32 during the accelerometer rebalance cycle). Examining accelerometer rebalance-cycle 2, a total of four pulses is output, corresponding to the binary "100" stored in the register 32 during that rebalance cycle. Finally, a total of five (5) pulses is output from the trigger circuit 38 during accelerometer rebalance-cycle 3, corresponding to the binary value "lOl" that is stored in the register 32 during the rebalance cycle. The accumulation of the counter 28 in response to the input of pulses from the trigger circuit 38 is illustrated in Figure 4(k). The pulses output by the trigger circuit 38 of the digital-to-pulse converter 26 are fed to the counter 28 through the high speed system sampling clock 30. The rebalance cycle of the utilization circuit 24 is controlled by the combination of the utilization circuit clock 22 and the divide-by-N counter 31. A utilization circuit 24 period equal to six times the clock period (N = 6) is employed in the example. The sequence of numbers written between the lines that define the boundaries of the utilization circuit cycles indicate the instantaneous count of the counter 28 with circled numbers denoting the count values actually gated through the switch 29 at the time that an "end of cycle" signal arrives from the divide-by-N counter 31. As can be seen from the above, the digital-to pulse converter 26, in conjunction with subsequent apparatus, converts the accelerometer measurements taken over an eight clock period accelerometer rebalance cycle to a six clock pulse utilization circuit period. In the process, the accelerometer rebalance cycle sequence "2", "4", "5" is converted to the utilization circuit sequence "1", "3", "3", "4". In order to compare the values obtained by the utilization circuit to the desired case, it should be considered that, ideally, the values computed in each accelerometer rebalance cycle should be uniformly spread over the entire cycle. Thus, for example, in accelerometer rebalance cycle 1, there are two (2) counts per eight (8) clocks or 1/4 count per clock. In accelerometer rebalance cycle 2, there are four (4) counts per eight (8) clocks or 1/2 count per clock. Finally, in accelerometer rebalance cycle 3, there are five (5) counts per eight (8) clocks or 5/8 count per clock. Utilization circuit period 1 encompasses the first six (6) clocks of accelerometer rebalance cycle 1. Thus, the desired value is 6 x 1/4 = 1.5 counts. This may be compared to the actual count (1) obtained. Utilization rebalance-cycle 2 overlaps two (2) clocks from accelerometer rebalance-cycle 1 and four (4) clocks from accelerometer rebalance-cycle 2. Thus, the desired value is 2 x (1/4) + 4 x (1/2) = 2.5 counts which is compared to the three (3) counts actually obtained. Utilization cycle 3 spans four (4) clocks from accelerometer circuit period 3 and two (2) clocks from accelerometer rebalance 4. The desired value is 4 x (1/2) + 2 x 5/8 = 3.25 counts in contrast to the three (3) counts actually obtained. Finally, utilization circuit period 4 spans six (6) clocks from accelerometer rebalance-cycle 4 leading to a desired value of 6 x 5/8 = 3.75 counts. This is to be compared to the four (4) counts that were obtained. In all cases, the value obtained is within one count of the desired value. This is a significant property of the digital to pulse conversion scheme described. Thus it is seen that there is provided a data interface that readily overcomes problems inherent in the provision of data generated by a closed loop accelerometer to a utilization circuit. The use of such an interface significantly reduces problems of noise and jitter that arise from mismatches between the cycle time of the accelerometer rebalance loop and the cycle time of the utilization circuit. By employing the described data conversion apparatus and method one is able to eliminate the need for synchronous operation while retaining most of the benefits of such operation. Drastic, intrinsic, modifications of existing equipment are avoided as well as significant costs, both economic and in terms of lost performance value. While the invention has been described with reference to its presently preferred embodiment, it is not limited thereto.

Claims: Apparatus for converting the output of a closed-loop accelerometer (10) of the type that includes a rebalance loop (14) of a first rebalance-cycle period to a form for use in a utilization circuit (24) of a second cycle period and in which the accelerometer output is a value comprising a number of digital data bits representing acceleration during at least one accelerometer rebalance-cycle period, said apparatus being characterised by: a) means (32) for receiving said value; b) means (34, 36, 38) for converting said value into a stream of pulses distributed over one accelerometer rebalance-cycle period; c) means (30) for sampling said stream of pulses over said second cycle period; d) means (28) for counting said sampled pulses; and e) means (29) for delivering said pulse count to said utilization circuit. Apparatus according to Claim 1, arranged for conversion when said rebalance loop is controlled by a first clock (16) and said utilization circuit is controlled by a second clock (22). Apparatus according to Claim 1 or 2 wherein said means (32) for receiving said value comprises a register (32) having a plurality of stages (46, 48, 50) arranged to store respective digital data bits of said value. Apparatus according to Claim 1, 2 or 3 wherein said means for converting includes a plurality of divide-by-two counters (40, 42, 44). Apparatus according to Claims 3 and 4 and including a plurality of gates (36), each of which is arranged to control passage of a divide-by-two counter output in accordance with the state of a stage of said register (32). Apparatus according to Claim 5, when appended to Claim 2, wherein said divide-by-two counters (36) are serially coupled and the first of said serial coupled arrangement of divide-by-two counters is arranged to receive the output of said first clock (16). Apparatus according to Claim 5 or 6 wherein said means for converting includes a trigger circuit (38) arranged to receive the outputs of said gates (36). Apparatus according to Claim 7 wherein said trigger circuit (38) is operable to provide pulses of predetermined duration in response to the outputs of said gates. Apparatus according to Claim 7 or 8 wherein the counting means comprises a pulse counter (28) for receiving the output of said trigger circuit. Apparatus as defined in Claims 2 and 9 wherein said means (29) for delivering said pulse count comprises means (29) for detecting the output of said pulse counter and the state of which means (29) is responsive to the output of said second clock (22). Apparatus as claimed in Claim 9 or 10 wherein said means for delivering said pulse count comprises: means for sampling; means responsive to said second clock for measuring said second predetermined cycle period; and the state of said means for sampling is responsive to said means for measuring said second predetermined cycle period. A closed-loop accelerometer comprising a rebalance loop, a utilization current and an apparatus according to any one of the preceding claims coupling the loop and the utilization circuit. A method of converting the output of a closed-loop accelerometer of the type that includes a rebalance loop of a first rebalance-cycle period to a form for use in a utilization circuit of a second cycle period and in which the accelerometer output is a value comprising a number of digital data bits representing acceleration during at least one prior accelerometer rebalance-cycle period, said method being characterised by the steps of: a) receiving said value; b) converting the received value into a stream of pulses distributed over one accelerometer rebalance-cycle period; c) sampling said stream of pulses over said second cycle period; d) counting the sampled pulses; and e) delivering the resulting pulse count to said utilization circuit. A method according to Claim 13 wherein the value is received in a register that includes a plurality of stages, the method comprising: arranging said value within said register so that the digital data bits of said value are stored in respective stages of said register; and converting said value into a stream of pulses distributed over one accelerometer rebalance-cycle period by means of an arrangement including (i) a plurality of divide-by-two counters, (ii) a plurality of gates, arranged to control the passage of respective divider-by-two counter outputs in accordance with the state of the stages of said register and (iii) a trigger circuit for providing pulses of predetermined duration in response to the outputs of said gates. A method according to Claim 13 or 14 wherein the first rebalance-cycle period is controlled by a first clock and the second cycle period is controlled by a second clock, the pulses are counted by means of a pulse counter and the pulse count is delivered to said utilization circuit by gating the count of said counter in response to the output of said second clock.

Inventors: MARK JOHN G, MCLANE DANIEL P, TAZARTES DANIEL A, WYSE STANLEY F, MARK, JOHN G., MCLANE, DANIEL P., TAZARTES, DANIEL A., WYSE, STANLEY F.
Applicants: LITTON SYSTEMS INC, LITTON SYSTEMS, INC.
Application year: 1994
Main classification: G01P15
IPC codes: G01P15