Insulated gate semiconductor device and method of fabricating the same

Abstract: In an insulated gate semiconductor device such as a 16BT, MCT or power MOSFET, a loss is suppressed and a short-circuit tolerance as well as a latch-up tolerance are improved. By adding a channel region of high threshold (32A) between the emitter region (4) and the channel region of low threshold (3), the saturation current I CE (sat) and the short-circuit tolerance tw are reduced without much influencing a collector-emitter saturation voltage V CE (sat). When the sheet resistance of the n type emitter region (4) is in the range between 40Ω/□ and 150Ω/□, 10 µ sec or more of the short-circuit tolerance, which is practically sufficient, is ensured while the collector-emitter saturation voltage V CE (sat) is suppressed to practically small 2.4V or less. Both the collector-emitter saturation voltage V CE (sat) and the saturation current I CE (sat) are restrained small, thereby realizing an enhanced short-circuit tolerance. Also disclosed is a highly-doped gate electrode and methods of making the same.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) and a method of fabricating the same. More particularly, the invention relates to an improvement in short-circuit tolerance. Description of the Background Art 1. Structure of Conventional Device Fig. 40 is a plan view of a conventional N-channel IGBT 100. The IGBT 100 comprises a multiplicity of IGBT elements (hereinafter referred to as IGBT unit cells) 110 connected in parallel, only one of which is illustrated. An emitter electrode 7 and an oxide film 8 to be described later with reference to Fig. 41 are not illustrated in Fig. 40. The configurations of various mask patterns to be used in the process steps for fabricating the IGBT 100 are also shown in Fig. 40. Figs. 41 and 42 are cross-sectional views of one of the IGBT unit cells 110 taken along the lines A-A and B-B of Fig. 40, respectively. A circuit diagram of an equivalent circuit of the IGBT unit cell 110 is also illustrated in Fig. 41. Referring to Figs. 41 and 42, the IGBT unit cell 110 includes a p-type collector layer 1 which is a p-type semiconductor substrate and an n-type epitaxial layer 2. The layers 1 and 2 form a semiconductor body 120. A p-type base region 3 is formed in a partial region in the top major surface of the n-type epitaxial layer 2 or the semiconductor body 120 by selective diffusion of p-type impurities. In a partial region in the top major surface of the semiconductor body 120 are also formed n-type emitter regions 4 by selective diffusion of n-type impurities. A gate insulating film 5 is formed to cover the top surface of the p-type base region 3 between the top surface of the n-type epitaxial layer 2 and the top major surface of the n-type emitter regions 4. The gate insulating films 5 for adjacent IGBT unit cells 110 are integrally formed on the top surface of the n-type epitaxial layer 2. A gate electrode 6 made of, for example, polycrystalline silicon (hereinafter referred to as polysilicon) is formed on the gate insulating film 5. The emitter electrode 7 made of, for example, aluminum is formed such that it is electrically connected to both the p-type base region 3 and the n-type emitter regions 4. The gate electrode 6 and the emitter electrode 7 are insulated from each other by an oxide film 8 serving as inter-layer insulating film, and are electrically connected in common in and between all of the IGBT unit cells 110. A high-concentration p-type semiconductor region 31 is formed in the p-type base region 3 through diffusion of p-type impurities at high concentration in a pattern which surrounds the n-type emitter regions 4. A collector electrode 9 made of metal is formed on the bottom major surface of the p-type collector layer 1 integrally for all of the IGBT unit cells 110. As shown in Fig. 40, the IGBT cell 110 has regions in which the n-type emitter regions 4 are relatively wide as viewed from the top and regions in which they are relatively narrow. The region around the line A-A is one of the former regions while the region around the line B-B is one of the latter regions. The dotted lines of Fig. 40 represent a mask pattern 51 to be used for formation of the gate electrode 6, a mask pattern 52 to be used for formation of the high-concentration p-type semiconductor region 31, and a mask pattern 53 to be used for formation of the n-type emitter regions 4 in a process of fabricating the IGBT 100. 2. Operation of Conventional Device Referring to Fig. 41, the IGBT unit cell 110 includes an insulated gate field effect transistor MOS, which may be a metal-oxide-semiconductor transistor and is hereinafter referred to as an MOSFET, a pnp bipolar transistor Trl, an npn bipolar transistor Tr2, and a resistance Rb. These elements are equivalently connected to each other as shown in the equivalent circuit diagram of Fig. 41. When a gate voltage V GE is applied across the gate and emitter electrodes 6 and 7 with a collector voltage V CE applied across the collector and emitter electrodes 9 and 7, the p-type semiconductor in the top surface of the p-type base region 3 between the n-type emitter regions 4 and n-type epitaxial layer 2 is inverted into an n-type semiconductor to form n-type channels. Then conduction is permitted between the n-type epitaxial layer 2 serving as a drain of the MOSFET and the n-type emitter regions 4 serving as a source thereof, and an electronic current flows from the n-type emitter regions 4 through the n-type channels into the n-type epitaxial layer 2. The electronic current serves as a base current for the transistor Trl. In response to the electronic current, holes are introduced from the p-type collector layer 1 into the n-type epitaxial layer 2. Some of the introduced holes are recombined with the carrier electrons in the n-type epitaxial layer 2, and the other holes flow through the p-type base region 3 into the emitter electrode 7 to provide a hole current. As a result, the IGBT 100 conducts or turns on, that is, conduction is permitted across the collector and emitter electrodes 9 and 7. The IGBT 100, a voltage-controlled transistor having insulated gates (MOS gates) like the MOSFET, is advantageous in that a drive circuit of the IGBT 100 is constructed more simply than that of bipolar transistors and in that a collector-emitter saturation voltage (ON-voltage) lower than that of the MOSFET is achieved. The latter advantage is provided because the holes introduced from the p-type collector layer 1 into the n-type epitaxial layer 2 cause a conductivity modulation so that the resistance of the n-type epitaxial layer 2 effectively becomes low. When the gate voltage V GE is a zero voltage or is zero-biased or when it is a negative voltage or is negatively biased, the MOSFET enters a cut-off state so that the electronic current stops flowing. As a result, the IGBT 100 is cut off. However, accumulated holes remain in the n-type epitaxial layer 2 during the transition period in which the transition from ON to OFF starts. A certain period of time (turn-off time) is required for the holes accumulated in the course of the transition to disappear. During the turn-off period, the hole current continues flowing while decaying. The accumulated holes are useful for achieving a low saturation voltage when the IGBT 100 is on but are a factor prolonging the turn-off time when the IGBT 100 turns off. Hence the amount of holes to be introduced in the ON-state or the lifetime thereof should be optimized. The IGBT unit cell 110 includes a parasitic thyristor formed by the n-type emitter regions 4, the p-type base region 3, the n-type epitaxial layer 2 and the p-type collector layer 1. The parasitic effect which is turn-on of the parasitic thyristor associated with the operation of the IGBT 100 sometimes prevents the original function of the IGBT 100. It is therefore necessary to suppress the parasitic effect. One of the effective approaches for suppression of the parasitic effect is to decrease the lateral resistance Rb of a part of the p-type base region 3 which lies just under the n-type emitter regions 4. For decrease in the resistance Rb, there has been proposed an arrangement shown in Figs. 41 and 42 in which the high-concentration p-type semiconductor region 31 is provided just under the n-type emitter regions 4, which is disclosed in JP-A-60 196 974 (&GB-A-2 156 151), for example. As illustrated in Figs. 41 and 42, the high-concentration p-type semiconductor region 31 is formed on the inside of the n-type emitter regions 4 for the purpose of exerting no influence on a gate threshold voltage. That is, the high-concentration p-type semiconductor region 31 is formed such that the region 31 itself is not included in the n-type channels to be formed in the p-type base region 3 when the gate voltage V GE is applied. Document DE 35 19 389 Al discloses an insulated gate semiconductor device with a semiconductor body comprising a first semiconductor region, a second semiconductor region located in a top surface of the first semiconductor region, a fourth semiconductor region and a third semiconductor region embedded in the fourth semiconductor region, wherein the third semiconductor region defines a pattern on the top major surface of the semiconductor body including a pair of strip areas arranged in parallel separated by a central area. Moreover, document DE 37 11 033 A1 discloses a semiconductor device with a MOSFET structure having an improved turn-on resistance and a high resistivity against the second breakthrough. However, the third semiconductor regions, i.e. n+-regions, are located beside the fourth semiconductor region, i.e. p+-region. Finally, document EP-A-0 561 267 which falls within the terms of Art. 54(3) EPC, discloses an insulated gate semiconductor device comprising a semiconductor body having a top major surface and a bottom major surface, a first semiconductor region, a second semiconductor region and a third semiconductor region. The third semiconductor region forms a pattern on the top major surface while a fourth semiconductor region is located in a top surface portion of the semiconductor body. Moreover, an insulating layer is located on the top major surface while a control electrode layer is buried in an insulating layer overlying the portions of the top surfaces. The first main electrode layer is formed in an opening of the insulating layer while a second main electrode is formed on the bottom major surface of the semiconductor body. However, this document is silent with respect to the specific sheet resistance of the third semiconductor region. 3. Disadvantage of Conventional Device Referring again back to Fig. 40 the IGBT 100 is often used for an inverter device and the like. It is hence necessary that the IGBT 100 is not broken down when the inverter device is short-circuited or when the IGBT 100 turns on with a short-circuit voltage applied thereto. The resistance to short-circuit of the IGBT 100 (short-circuit tolerance) decreases in proportion to the product of the voltage and the current when the IGBT 100 is short-circuited and a short-circuit time. The IGBT 100 having a small chip area, in particular, has a low short-circuit tolerance. The voltage at the time of short-circuit and the short-circuit time are determined by the conditions under which the IGBT 100 is used, e.g., the operating conditions of the inverter. Since the IGBT 100, when short-circuited, is saturated, the current at the time of the short-circuit is just a saturation current I CE (sat) of the IGBT 100. The establishment of a low saturation current I CE (sat) is effective for improving the short-circuit tolerance. The saturation current I CE (sat) is determined by: I CE ( sat ) ∝ 1 2·(1-α pnp ) ·C ox ·µ n · W L ·( V GE - V GE ( th )) 2 where: αpnp is a current transfer ratio of the pnp transistor; C ox is a gate capacitance; µn is a surface mobility; W is a channel width; L is a channel length; V GE is the gate voltage; and V GE (th) is the gate threshold voltage. For reduction in losses where the IGBT 100 is applied as a switching element to the inverter and the like, a small collector-emitter saturation voltage V CE (sat) is required. One of the effective schemes for decrease in collector-emitter saturation voltage V CE (sat) is to improve the electrical characteristics of a portion corresponding to the MOSFET (the portion MOS of Fig. 41) in the IGBT unit cell 110 to reduce a drop voltage when the MOS is conducting. For example, a shallow diffusion is carried out in a diffusing step for forming the p-type base region 3 to shorten the channel length L of the MOS. Otherwise, the IGBT unit cell 110 is reduced in size and increased in density by reducing the width of the p-type base region 3 (the whole lateral width of the p-type base region 3 of Figs. 41, 42), to thereby relatively increase the total of the channel widths W for the whole IGBT 100. However, either shortening the channel length L or increasing the channel width W for reduction in collector-emitter saturation voltage V CE (sat) is accompanied by increase in saturation current I CE (sat) as will be understood from Formula (1). Then the parasitic thyristor causes latch-up to brreak down the IGBT 100, or otherwise the product of the voltage and current at the time of short-circuit grows large, so that the short-circuit tolerance falls off. The conventional IGBT 100 is, therefore, disadvantageous in that low losses when used as a switching element cannot coexist with high short-circuit tolerance. It is therefore an object of the present invention to provide an insulated gate semiconductor device and a method of fabricating the same which has high short-circuit tolerance and improved latch-up tolerance with low losses. According to the present invention this object is achieved, concerning the insulated gate semiconductor device, by the features indicated in present independent claim 1 and, concerning the method of fabricating the insulated gate semiconductor device, by the measures indicated in present claim 14. Particularly by embedding the third semiconductor region within the fourth semiconductor region and selecting a specific sheet resistance of the third semiconductor region out of a specific range the saturation current I CE(sat) is reduced, thereby providing a higher short-circuit tolerance while still showing a reduction of the latch-up effect with low losses. The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings, of which: Fig. 1 is a plan view of an N-channel IGBT according to a first preferred embodiment of the present invention; Fig. 2 is a cross-sectional view taken along the line A1-A1 of Fig. 1; Fig. 3 is a cross-sectional view taken along the line B1-B1 of Fig. 1; Fig. 4 is a plan view of a variation of the N-channel IGBT according to the first preferred embodiment of to the present invention; Fig. 5 is a cross-sectional view taken along the line A1a-A1a of Fig. 4; Fig. 6 is a cross-sectional view taken along the line C1a-C1a of Fig. 4; Fig. 7 is a graph showing the result of measurements of the IGBT of Figs. 4 to 6; Figs. 8 to 21 are cross-sectional views showing process steps for fabrication of the IGBT of Fig. 1; Fig. 22 is a plan view of an N-channel IGBT according to a second preferred embodiment of to the present invention; Fig. 23 is a cross-sectional view taken along the line A2-A2 of Fig. 18; Figs. 24 and 25 are cross-sectional views showing process steps for fabrication of the IGBT of Fig. 18; Fig. 26 is a plan view of an N-channel IGBT according to a third preferred embodiment of the present invention; Fig. 27 is a cross-sectional view taken along the line A3-A3 of Fig. 26; Fig. 28 is a cross-sectional view taken along the line B3-B3 of Fig. 26; Figs. 29 to 34 are cross-sectional views showing process steps for fabrication of the IGBT of Fig. 26; Fig. 35 is a plan view of an N-channel IGBT according to a fourth preferred embodiment of the present invention; Fig. 36 is a cross-sectional view taken along the line A4-A4 of Fig. 35; Figs. 37 and 38 are cross-sectional views showing process steps for fabrication of the IGBT of Fig. 35; Fig. 39 is a front sectional view of a modification of the N-channel IGBT according to the present invention; Fig. 40 is a plan view of a conventional N-channel IGBT; Fig. 41 is a cross-sectional view taken along the line A-A of Fig. 40; Fig. 42 is a cross-sectional view taken along the line B-B of Fig. 40; Fig. 43 is a plan view showing a structure of an N-type channel IGBT according to a fifth preferred embodiment of the present invention; Fig. 44 is a graph plotting device characteristics against the emitter bypass ratio e in the fifth preferred embodiment of the present invention; Fig. 45 is a graph plotting device characteristics against a sheet resistance of an n-type emitter region in the fifth preferred embodiment of the present invention; Fig. 46 is a graph plotting a turn-on loss against a sheet resistance of a gate electrode 6 in the fifth preferred embodiment of the present invention; and Figs. 47 to 49 are cross-sectional views showing process steps for fabricating the IGBT of the fifth preferred embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. First Preferred Embodiment 1-1. Structure of Device Fig. 1 is a plan view of an N-channel IGBT 200 according to a first preferred embodiment of the present invention. The IGBT 200 comprises a multiplicity of IGBT unit cells 210 connected in parallel. Although the IGBT 200 has an emitter electrode 7 and a oxide film 8 as described later, they are not illustrated in Fig. 1. The configurations of various mask patterns to be used in process steps for fabricating the IGBT 200 are depicted in Fig. 1. Figs. 2 and 3 are cross-sectional views of one of the IGBT unit cells 210 taken along the lines A1-A1 and B1-B1 of Fig. 1, respectively. Since the respective IGBT unit cells 210 have substantially the same structure, the constitution of the whole IGBT 200 will be understood from Figs. 1 to 3. Like reference numerals and characters are used to designate parts corresponding to those of the conventional device of Figs. 40 to 42. With reference to Figs. 2 and 3, the IGBT 200 comprises a p-type collector layer 1 which is a p-type semiconductor substrate, and an n-type epitaxial layer 2. The layers 1 and 2 form a semiconductor body 220. A p-type base region 3 is formed in a partial region in the top major surface of the n-type epitaxial layer 2 or the semiconductor body 220 by selective diffusion of p-type impurities. In a partial region in the top major surface of the semiconductor body 220 are also formed n-type emitter regions 4 by selective diffusion of n-type impurities. The n-type emitter regions 4 are exposed in a pair of substantially parallel strip areas BA separated from each other by a central area CA. A gate insulating film 5 is formed to cover the top surface of the p-type base region 3 between the top surface of the n-type epitaxial layer 2 and the top major surface of the n-type emitter region 4. The gate insulating films 5 for adjacent IGBT unit cells 210 are integrally formed on the top surface of the n-type epitaxial layer 2. A gate electrode 6 made of, for example, polysilicon is formed on the gate insulating film 5. The emitter electrode 7 made of, for example, aluminum is formed such that it is electrically connected to both the p-type base region 3 and n-type emitter regions 4. The gate electrode 6 and emitter electrode 7 are insulated from each other by the oxide film 8 serving as a layer insulating film, and are electrically connected in common in and between all of the IGBT unit cells 210. The oxide film 8 has an opening or window WD in a region covering part of the strip areas BA and at least part of the central area CA as shown in Figs. 2 and 3. A high-concentration p-type semiconductor region 32 is formed in the p-type base region 3 by diffusion of p-type impurities at high concentration in a certain pattern. A collector electrode 9 made of metal is formed on the bottom major surface of the p-type collector layer 1 integrally for all of the IGBT unit cells 210. As shown in Fig. 1, the IGBT unit cell 210 includes first regions R1 in which the n-type emitter regions 4 are relatively wide as viewed from the top and second regions R2 in which they are relatively narrow as viewed from the top. The line A1-A1 crosses one of the first regions R1 while the line B1-B1 crosses one of the second regions R2. The dotted lines of Fig. 1 represent a mask pattern 51 to be used for formation of the gate electrode 6, a mask pattern 53 to be used for formation of the n-type emitter regions 4, a mask pattern 54 to be used for formation of the high-concentration p-type semiconductor region 32, and a mask pattern 55 to be used in a contact process step of removing the oxide film 8 for electrical connection of the p-type base region 3 and n-type emitter regions 4 to the emitter electrode 7, in the fabrication process. As shown in Figs. 1 and 2, first parts 32A of the high-concentration p-type semiconductor region 32 in the first regions R1 extends widely enough to protrude outwardly over the n-type emitter regions 4 but does not reach the n-type epitaxial layer 2 over the p-type base region 3. On the other hand, as shown in Figs. 1 and 3, second parts 32B of the high-concentration p-type semiconductor region 32 in the second regions R2 are relatively narrow and the outer edges thereof are coincident with the outer edges of the n-type region 4. Correspondingly, the mask pattern 54 is wider on the first regions R1 than on the second regions R2. 1-2. Operation and Characteristic of Device When a positive gate voltage V GE is positively applied across the gate and emitter electrodes 6 and 7 with a collector voltage V CE applied across the collector and emitter electrodes 9 and 7, the p-type semiconductor in the top surface of the p-type base region 3 between the n-type emitter regions 4 and n-type epitaxial layer 2 is inverted into an n-type semiconductor to form n-type channels. Then, conduction is permitted between the n-type epitaxial layer 2 serving as a drain of an MOSFET equivalently formed in the IGBT unit cell 210 and the n-type emitter regions 4 serving as a source thereof, and an electron current flows from the n-type emitter regions 4 through the n-type channels into the n-type epitaxial layer 2. The electron current serves as a base current for a pnp bipolar transistor equivalently formed by the p-type collector layer 1, n-type epitaxial layer 2, and p-type base region. In response to the electron current, holes are introduced from the p-type collector layer 1 into the n-type epitaxial layer 2. Some of the introduced holes are recombined with carrier electrons in the n-type epitaxial layer 2, and the other holes flow through the p-type base region 3 into the emitter electrode 7 in the form of a hole current. As a result, the IGBT 200 conducts (turns on), that is, conduction is permitted across the collector and emitter electrodes 9 and 7. When the gate voltage V GE is a zero voltage or is zero-biased or when it is a negative voltage or is negatively biased, the equivalently formed MOSFET enters the off-state, so that the electron current stops flowing. As a result, the IGBT 200 is turned off. Since the high-concentration p-type semiconductor region 32 is of the above-mentioned configuration in the first regions R1, the n-type channels defined between the n-type emitter regions 4 and n-type epitaxial layer 2 by the application of the positive gate voltage V GE includes series connection of the inverted layer of the p-type base region 3 and the inverted layer in the first part 32A of the high-concentration p-type semiconductor region 32. On the other hand, since the second parts 32B of the high-concentration p-type semiconductor region 32 is formed on the inside of the n-type emitter regions 4 as viewed from the top, the n-type channels are formed by only the inverted layer of the n-type base region 3. A gate threshold voltage V GE (th) that is the level of the gate voltage required for the formation of the inverted layers is higher in the high-concentration p-type semiconductor region 32 than that in the p-type base region 3. Thus the gate threshold voltage V GE (th) is a relatively high voltage V GE (th-High) in the first regions R1, and is a relatively low voltage V GE (th-Low) in the second regions R2. The n-type channels to be formed between the n-type emitter regions 4 and n-type epitaxial layer 2 are formed by parallel connection of the n-type channels having the relatively high gate threshold voltage V GE (th-High) and the n-type channels having the relatively low gate threshold voltage V GE (th-Low). The gate threshold voltage V GE (th) for the whole IGBT 200 is defined by the gate voltage V GE when a collector current Ic (a current flowing between the collector electrode 9 and emitter electrode 7) starts rising from zero as the gate voltage V GE increases. In other words, it is the gate voltage V GE when the collector current Ic reaches a certain specified level established considerably lower than its rated value which is a maximum value in normal use. For this reason, the gate threshold voltage V GE (th) is mainly determined by the relatively low gate threshold voltage V GE (th-Low) and is approximately equal thereto. In the device 200 according to the first preferred embodiment, the provision of the n-type channels having the relatively high gate threshold voltage V GE (th-High) has little influence on the gate threshold voltage V GE (th) for the whole IGBT 200. The provision of the n-type channels having the relatively high gate threshold voltage V GE (th-High) has a small influence on a collector-emitter saturation voltage V CE (sat) in the structure of Figs. 1 to 3, but has a relatively significant influence on a saturation current I CE (sat) to be described below. The impurity concentration of the high-concentration p-type semiconductor region 32 in the IGBT 200 is selected such that the relatively high gate threshold voltage V GE (th-High) becomes lower than the predetermined gate voltage V GE when the IGBT 200 turns on, that is, as given by: V GE ( th-Low ) < V GE ( th-High ) < V GE in the ON-state When the gate threshold voltage V GE (th) is the ON-state voltage under the conditions of the Formula (2), a large degree of inversion occurs in the n-type channels having the relatively low gate threshold voltage V GE (th-Low) and a small degree of inversion occurs in the high-concentration p-type semiconductor region 32 in the n-type channels having the relatively high gate threshold voltage V GE (th-High). As an example, the gate threshold voltage V GE (th-High) of about 10 V is selected where the gate threshold voltage V GE (th-Low) is about 5 V and the ON-state gate voltage V GE is 15 V. From Formula (1) is derived: I CE ( sat ) ∝ W ·( V GE -V GE ( th )) 2 From the Formula (3), the saturation current I CE (sat) flowing when the IGBT 200 is short-circuited decreases as the proportion of the n-type channels having the relatively high gate threshold voltage V GE (th-High) in the width W of the n-type channels increases. Thus, the device 200 according to the first preferred embodiment achieves low collector-emitter saturation voltage V CE (sat), low saturation current and, accordingly, high short-circuit tolerance by optimization of the proportion of the n-type channels having the relatively high gate threshold voltage V GE (th-High) in the whole n-type channels even when the IGBT unit cells 210 are reduced in size and increased in density. The device 200 according to the first preferred embodiment including the first regions R1 and the second regions R2 has the advantage of size reduction in the IGBT unit cells 210 with an ensured insulator breakdown voltage across the gate and emitter electrodes 6 and 7 and an ensured electrical connection of the n-type emitter regions 4 and high-concentration p-type semiconductor region 32 to the emitter electrode 7. In addition, since the high-concentration p-type semiconductor region 32 is widely formed in the first regions R1, the device 200 provides the advantage of effective suppression of the parasitic thyristor effect. 1-3. Measurements of Characteristics of Device Description will be given on the measurements of electrical characteristics of the IGBT 200 of the first preferred embodiment. For decreasing the collector-emitter saturation voltage V CE (sat) of the IGBT 200, it is effective to improve the characteristics of the MOSFET region to be equivalently formed in the IGBT unit cell 210 as above described. One of the improvements is to make the p-type base region 3 as narrow as possible for size reduction and density increase of the IGBT unit cell 210 and, accordingly, to relatively increase the channel width W of the MOSFET region. For reducing the width of the p-type base region 3, it is preferable that the IGBT unit cell 210 includes a teeth-like n-type emitter pattern as shown in Fig. 4 in which the opposed n-type emitter regions 4 are connected with each other and form a lattice shape. Fig. 4 schematically shows the pattern of the p-type base region 3 and n-type emitter regions 4 on the top major surface of the semiconductor body 220 where the pattern is made fine. A multiplicity of IGBT unit cells 210a shown in Fig. 4 are connected in parallel to form an IGBT 200a as well as the IGBT unit cells 210 of Fig. 1. There are shown in Fig. 4 an n-type emitter region 4a, a high-concentration p-type semiconductor region 32a, a mask pattern 53a, and a mask pattern 54a, which correspond to the n-type emitter regions 4, the high-concentration p-type semiconductor region 32, the mask pattern 53, and the mask pattern 54 of the IGBT unit cell 210, respectively. In the IGBT unit cell 210a, the two strip portions of the n-type emitter region 4a are linked together not only in first regions R1 in which the high-concentration p-type semiconductor region 32a is wide but also part of the second regions R2. Figs. 5 and 6 are cross-sectional views taken along the lines A1a-A1a and C1a-C1a of Fig. 4, respectively. The cross-sectional structures of Figs. 5 and 6 are identical with those of Figs. 2 and 3 except that the n-type emitter region 4a is not divided into two regions. The cross-section taken along the line B1a-B1a of Fig. 4 is identical with that of Fig. 3. We introduce an emitter bypass ratio e generally defined as the ratio of the area A1 of the n-type emitter region 4 electrically contacting the emitter electrode 7 to the sum of the area A1 and the area A2 of the high-concentration p-type semiconductor region 32 in contact with the emitter electrode 7. Thus, the emitter bypass ratio e is given by a formula: e = A1 A1 + A2 In the n-type emitter pattern of Fig. 4, a width X is the width of the n-type emitter region 4a, and a width Y is the width of a region other than the n-type emitter region 4a or part of the high-concentration p-type semiconductor region 32a which is exposed at the top major surface of the semiconductor body 220. In this IGBT 200a having the particular n-type emitter pattern shown in Fig. 4, the emitter bypass ratio e is simultaneously expressed by another formula: e = X X + Y Formula (4) provides the general definition of the emitter bypass ratio e , whereas Formula (4a) gives the specific one for IGBT 200a. On the top major surface of the semiconductor body 220 of Fig. 4, a length H is the length of a portion in which the high-concentration p-type semiconductor region 32a lies between the n-type emitter region 4a and the n-type epitaxial layer 2, and a length L is the length of a portion in which the n-type emitter region 4a and n-type epitaxial layer 2 are isolated from each other only by the p-type base region 3 without the high-concentration p-type semiconductor region 32a. A high gate threshold voltage region percentage g is defined using the lengths H and L as: g = H ( H + L ) The lengths H and L are the n-type channel widths having the relatively high gate threshold voltage V GE (th-High) and the relatively low gate threshold voltage V GE (th-Low), respectively. As the emitter bypass ratio e increases and, equivalently, the area of the n-type emitter region 4a increases, the sheet resistance of the n-type emitter region 4a decreases. This is equivalent to decrease in source resistances connected equivalently in series in the MOSFET region, which is a factor of increase in electron current in the MOSFET region. This enables the short-circuit current of the IGBT to increase. As a result, the short-circuit tolerance is reduced. Fig. 7 is a graph showing measurements of the collector-emitter saturation voltage V CE (sat), saturation current I CE (sat) and short-circuit tolerance t w with respect to the emitter bypass ratio e . The values plotted in the form of curves are the result of measurement where the high gate threshold voltage region percentage g is 20 %. In the graph of Fig. 7, there are also shown values measured where the emitter bypass ratio e is 36 % and the high gate threshold voltage region percentage g is 0 %. The short-circuit tolerance t w is defined as the time interval from the beginning of the short-circuit of the output of the IGBT to the breakdown of the IGBT. Comparison is made between the measurement where e = 36 % and g = 0 % and the measurement where e = 36 % and g = 20 %. It is understood from the comparison that the provision of the high-concentration p-type semiconductor region 32a makes little difference in the collector-emitter saturation voltage V CE (sat) but largely suppresses the saturation current I CE (sat) when the device is short-circuited, accompanied by a large improvement in the short-circuit tolerance t w . This fact supports the foregoing qualitative analysis. The short-circuit tolerance t w required when the IGBT is used for an inverter device is about 10 µs or more. The short-circuit tolerance t w required for an IGBT including a circuit for detecting a short-circuit current flowing when it is short-circuited to execute shot-circuit protection is about 5 µsec or more. For satisfying such short-circuit tolerance, it is necessary that the emitter bypass ratio e is 50 % or less and the high gate threshold voltage region percentage g is 20 % or more as may be found from the measurements of Fig. 7. For convenience of measurement, the measurements have been performed only for the IGBT 200a shown in Figs. 4 to 6. However, the same results of the measurements are sufficiently expected also for the IGBT 200 as the emitter bypass ratio e of IGBT 200 is defined by the general Formula (4). 1-4. Process Steps for Fabrication of Device Figs. 8 to 21 are front sectional views of the IGBT unit cell 210 in respective process steps for fabrication of the IGBT 200. Referring to Figs. 8 to 21, the process steps of the first preferred embodiment will be described hereinafter. Initially provided is a p-type silicon substrate corresponding to the p-type collector layer 1 (Fig. 8). The n-type epitaxial layer 2 is formed on the p-type collector layer 1 by epitaxial growth technique. The p-type collector layer 1 and n-type epitaxial layer 2 form the semiconductor body 220. The illustration of the structure underlying the n-type epitaxial layer 2 will be omitted in Figs. 9 to 19 and 21. In the step of Fig. 9, a silicon oxide film 71 is formed on the n-type epitaxial layer 2, i.e., on the top major surface of the semiconductor body 220. Polysilicon is formed over the silicon oxide film 71, and a resist layer is in turn formed over the polysilicon. Photolithography process is carried out on the resist layer using a mask 72 having a pattern corresponding to the mask pattern 51 of Fig. 1 to provide a resist pattern 73 corresponding to the mask pattern 51. The polysilicon is selectively etched using the resist pattern 73 as a mask to form the gate electrode 6 on the silicon oxide film 71. The n-type epitaxial layer 2 is selectively implanted with boron using the resist pattern 73 and gate electrode 6 as a mask to provide a p-type semiconductor region 74 (Fig. 10). The resist pattern 73 is removed, and the boron in the p-type semiconductor region 74 is diffused into part of the n-type epitaxial layer 2 which underlies the gate electrode 6 by drive-in process to provide the p-type base region 3 as shown in Fig. 11. In the process step of Fig. 12 (a cross-section taken along the line A1-A1 of Fig. 1) and Fig. 13 (a cross-section taken along the line B1-B1 of Fig. 1), a resist layer is provided over the gate electrode 6 and silicon oxide film 71. Photolithography process is carried out on the resist layer using a mask 75 having a pattern corresponding to the mask pattern 54 of Fig. 1 to provide a resist pattern 76 corresponding to the mask pattern 54. The p-type base region 3 is selectively implanted with boron with relatively high concentration using the resist pattern 76 and gate electrode 6 as a mask to provide a high-concentration p-type semiconductor region 77. The resist pattern 76 is removed, and the boron in the high-concentration p-type semiconductor region 77 is diffused by drive-in process to provide the high-concentration p-type semiconductor region 32 as shown in Fig. 14 (a cross-section taken along the line A1-A1 of Fig. 1) and Fig. 15 (a cross-section taken along the line B1-B1 of Fig. 1). Since the mask pattern 54 used in the step of Figs. 12 and 13 is shaped so that it is wide around the line A1-A1 of Fig. 1 and narrow around the line B1-B1 of Fig. 1, the high-concentration p-type semiconductor region 32 extends to the part of the p-type base region 3 which underlies the gate electrode 6 around the line A1-A1(Fig. 14) but is confined only to the inside of an opening 6a of the gate electrode 6 around the line B1-B1 (Fig. 15). The diffusion step of the high-concentration p-type semiconductor region 77 is carried out such that the high-concentration p-type semiconductor region 32 to be formed thereby does not reach the n-type epitaxial layer 2 over the p-type base region 3 around the line A1-A1. In the step of Fig. 16 (a cross-section taken along the line A1-A1 of Fig. 1) and Fig. 17 (a cross-section taken along the line B1-B1 of Fig. 1), a resist layer is provided over the gate electrode 6 and silicon oxide film 71. The resist layer is patterned by photolithography using a mask 78 having a pattern corresponding to the mask pattern 53 to provide a resist pattern 79. The silicon oxide film 71 is selectively etched using the resist pattern 79 and gate electrode 6 as a mask to form the gate insulating film 5 and an oxide film pattern 80. As shown in Fig. 18 (a cross-section taken along the line A1-A1 of Fig. 1) and Fig. 19 (a cross-section taken along the line B1-B1 of Fig. 1), the resist pattern 79 is removed, and the high-concentration p-type semiconductor region 32 in its top surface portion is selectively implanted with arsenic using the oxide film pattern 80, gate insulating film 5 and gate electrode 6 as a mask. This permits the n-type emitter regions 4 to be formed in the top major surface of the high-concentration p-type semiconductor region 32. Since the mask pattern 53 used in the step of Figs. 16 and 17 is shaped so that it is wide around the line A1-A1 of Fig. 1 and narrow around the line B1-B1 of Fig. 1, the n-type emitter regions 4 extends wider on the inside of the opening 6a of the gate electrode 6 around the line A1-A1 (Fig. 18) but is confined only to the inside of the opening 6a of the gate electrode 6 adjacent an opening end 6b of the gate electrode 6 around the line B1-B1 (Fig. 19). In the step of Fig. 20 (a cross-section taken along the line A1-A1 of Fig. 1) and Fig. 21 (a cross-section taken along the line B1-B1 of Fig. 1), a relatively thick silicon oxide film is provided over the structure hereinabove obtained. The silicon oxide film is selectively etched off using a mask 81 having a pattern corresponding to the mask pattern 55 to form the oxide film 8 having an opening 8a. An opening end 8b of the oxide film 8 is located above the n-type emitter regions 4 around the line A1-A1 (Fig. 20) but above the high-concentration p-type semiconductor region 32 around the line B1-B1 (Fig. 21). An aluminum film is formed over the structure hereinabove obtained to form the emitter electrode 7 shown in Figs. 2 and 3. Part of the emitter electrode 7 which lies inside the opening 8a electrically short-circuits the p-type base region 3 and n-type emitter regions 4. Then, a Ti-Ni-Au film is formed over a bottom major surface S1 of the semiconductor body 220 to form the collector electrode 9 shown in Figs. 2 and 3. 2. Second Preferred Embodiment 2-1. Structure of Device Fig. 22 is a plan view of an N-channel IGBT 300 according to a second preferred embodiment of the present invention. The IGBT 300 comprises a multiplicity of IGBT unit cells 310 connected in parallel as well as the IGBT 200 of the first preferred embodiment. The emitter electrode 7 and oxide film 8 are not illustrated in Fig. 22. The dotted lines of Fig. 22 represent the configurations of various mask patterns to be used in the process steps for fabricating the IGBT 300. A mask pattern 56 is used for formation of a high-concentration p-type semiconductor region 33. Fig. 23 is a cross-sectional view of one of the IGBT unit cells 310 taken along the line A2-A2 of Fig. 22. As shown in Fig. 22, the n-type emitter regions 4 are relatively wide as viewed from the top around the line A2-A2 as well as the line A1-A1 of the first preferred embodiment and relatively narrow as viewed from the top around the line B2-B2 as well as the line B1-B1 of the first preferred embodiment. In the IGBT unit cell 310, a high-concentration p-type semiconductor region 33 formed by diffusion of p-type impurities at high concentration in a pattern which surrounds the n-type emitter regions 4 and extends over the p-type base region 3 into the n-type epitaxial layer 2 around the line A2-A2. Around the line B2-B2, the high-concentration p-type semiconductor region 33 is formed such that it does not extend to the outside of the n-type emitter regions 4, as was already described regarding the high-concentration p-type semiconductor region 32 of Fig. 3 or the high-concentration p-type semiconductor region 31 of Fig. 42. A cross-section taken along the line B2-B2 of Fig. 22 is provided by replacing the high-concentration p-type semiconductor region 32 of Fig. 3 with the high-concentration p-type semiconductor region 33, and the illustration thereof will be omitted herein. 2-2. Characteristic of Device In the IGBT 300 of the second preferred embodiment, the n-type channels to be formed between the n-type emitter regions 4 and n-type epitaxial layer 2 around the line A2-A2 have a high gate threshold voltage V GE (th) by the influence of the high-concentration p-type semiconductor region 33 and a long channel length L. The channel length of the n-type channels formed by the inverted layer of the second preferred embodiment is longer than that of the n-type channels formed by the inverted layer of the high-concentration p-type semiconductor region 32 of the IGBT 200 around the line A1-A1 of the first preferred embodiment. Hence the device of the second preferred embodiment is advantageously more effective for reduction in saturation current I CE (sat) than the device of the first preferred embodiment. 2-3. Process Steps for Fabrication of Device Figs. 24 and 25 are cross-sectional views of the IGBT unit cell 310 taken along the line A2-A2 of Fig. 22 in process steps for fabrication of the IGBT 300. Referring to Figs. 24 and 25, description will be given on the process steps for fabricating the IGBT 300 of the second preferred embodiment. The same process steps as those of Figs. 8 to 11 for the IGBT 200 are carried out. Then the process proceeds to the step of Fig. 24. A resist layer is formed over the gate electrode 6 and silicon oxide film 71. Photolithography process is carried out on the resist layer using a mask 82 having a pattern corresponding to the mask pattern 56 of Fig. 1 to provide a resist pattern 83 corresponding to the mask pattern 56. The p-type base region 3 and n-type epitaxial layer 2 are selectively implanted with boron with high energy with high concentration using the resist pattern 83 as a mask to provide a high-concentration p-type semiconductor region 84. Then the process proceeds to the step of Fig. 25. The resist pattern 83 is removed, and the boron in the high-concentration p-type semiconductor region 84 is diffused by drive-in process to provide the high-concentration p-type semiconductor region 33. Since the mask pattern 56 used in the step of Fig. 24 is shaped so that it is wide around the line A2-A2 of Fig. 22 and narrow around the line B2-B2 of Fig. 22, the high-concentration p-type semiconductor region 33 extends to the part of the n-type epitaxial layer 2 which underlies the gate electrode 6 around the line A2-A2, but is confined only to the inside of the opening 6a of the gate electrode 6 around the line B2-B2 as well as the high-concentration p-type semiconductor region 32 of the first preferred embodiment shown in Fig. 15. The succeeding process steps are the same as the process steps of Figs. 16 to 22 of the first preferred embodiment. 3. Third Preferred Embodiment 3-1. Structure of Device Fig. 26 is a plan view of an N-channel IGBT 400 according to a third preferred embodiment of the present invention. The IGBT 400 comprises a multiplicity of IGBT unit cells 410 connected in parallel as well as the IGBT 200 of the first preferred embodiment shown in Fig. 1. The emitter electrode 7 and oxide film 8 are not illustrated in Fig. 26. The dotted lines of Fig. 26 represent the configurations of various mask patterns to be used in the process steps for fabricating the IGBT 400. A mask pattern 57 is used for formation of a high-concentration p-type semiconductor region 34. Figs. 27 and 28 are cross-sectional views of one of the IGBT unit cells 410 taken along the lines A3-A3 and B3-B3 of Fig. 26, respectively. Around the line A3-A3 as well as the line A1-A1 of the first preferred embodiment, the n-type emitter regions 4 are relatively wide as viewed from the top. Around the line B3-B3 as well as the line B1-B1 of the first preferred embodiment, the n-type emitter regions 4 are relatively narrow as viewed from the top. In the devices of the first and second preferred embodiments, the high-concentration p-type semiconductor regions 32 and 33 to be formed for providing the n-type channels having the relatively high gate threshold voltage V GE (th-High) are formed by diffusion also just under the n-type emitter regions 4 and have the function of suppressing the parasitic thyristor effect. In the IGBT 400 of the third preferred embodiment, a high-concentration p-type semiconductor region 35 for providing the n-type channels having the relatively high gate threshold voltage V GE (th-High) is diffused shallowly as shown in Figs. 27 and 28 independently of the high-concentration p-type semiconductor region 34 for suppressing the parasitic thyristor effect. As shown in Fig. 26, the configuration of the high-concentration p-type semiconductor region 35 as viewed from the top is similar to that of the high-concentration p-type semiconductor region 32 of the first preferred embodiment shown in Fig. 1. On the other hand, the high-concentration p-type semiconductor region 34 for suppressing the parasitic thyristor effect is formed by diffusion more deeply than the high-concentration p-type semiconductor region 35 just under the n-type emitter regions 4. As shown in Figs. 27 and 28, the high-concentration p-type semiconductor region 34 is formed on the inside of the n-type emitter regions 4 so as not to affect the gate threshold voltage V GE (th) around the line A3-A3 as well as around the line B3-B3. The higher concentration of the p-type impurity in the high-concentration p-type semiconductor region 34 brings the higher latch-up tolerance with both the collector-emitter saturation voltage V CE (sat) and the saturation current I CE (sat) unchanged. On the other hand, the excessively high concentration of the impurity in the high-concentration p-type semiconductor region 35 gives rise to such a high gate threshold voltage V GE (th) that the IGBT 400 can not turn on any more. Thus, there is an upper limit on the concentration of the impurity in the high-concentration p-type semiconductor region 35, whereas the concentration of the impurity is not restricted in the high-concentration p-type semiconductor region 34. It is, therefore, desirable that the concentration of the impurity is higher in the high-concentration p-type semiconductor region 34 than in the high-concentration p-type semiconductor region 35. The high-concentration p-type semiconductor region 35 may be absent around the line B3-B3. 3-2. Characteristic of Device Since the IGBT 400 of the third preferred embodiment is constructed as above described, the configuration and boron concentration of the high-concentration p-type semiconductor region 34 are optimized for suppression of the parasitic thyristor effect, while the configuration and boron concentration of the high-concentration p-type semiconductor region 35 are optimized for reduction in the saturation current I CE (sat). Since the structures providing the optimization for the two purposes can be selected independently, the IGBT 400 is advantageously more effective for the respective purposes. 3-3. Process Steps for Fabrication of Device Figs. 29 to 34 are front sectional views of the IGBT unit cell 410 in process steps for fabrication of the IGBT 400. Referring to Figs. 29 to 34, description will be given on the process steps for fabrication of the IGBT 400 of the third preferred embodiment. The same process steps as those of Figs. 8 to 11 for the IGBT 200 are carried out. Then the process proceeds to the step of Fig. 29 (a section taken along the lines A3-A3 and B3-B3). A resist layer is provided over the gate electrode 6 and silicon oxide film 71. Photolithography process is carried out on the resist layer using a mask 85 having a pattern corresponding to the mask pattern 57 of Fig. 26 to provide a resist pattern 86 corresponding to the mask pattern 57. The p-type base region 3 is selectively implanted with boron with high concentration using the resist pattern 86 as a mask to provide a high-concentration p-type semiconductor region 87. Then the process proceeds to the step of Fig. 30 (a section taken along the lines A3-A3 and B3-B3). The resist pattern 86 is removed, and the boron in the high-concentration p-type semiconductor region 87 is diffused by drive-in process to provide a high-concentration p-type semiconductor region 88. Since the sections of the mask pattern 57 used in the step of Fig. 29 taken along the lines A3-A3 and B3-B3 are of the same configuration, there is no difference in process between the two sections. The configuration of the mask pattern 57 and the conditions of diffusion of the high-concentration p-type semiconductor region 87 are suitably determined so that the high-concentration p-type semiconductor region 88 is located on the inside of the opening 6a of the electrode 6 (Fig. 30). The step of Fig. 31 (a section taken along the line A3-A3) and Fig. 32 (a section taken along the line B3-B3) is carried out in the same fashion as the step of Figs. 12 and 13 of the first preferred embodiment. Specifically, the resist pattern 76 is formed using the mask pattern 54, and the p-type base region 3 and high-concentration p-type semiconductor region 88 are selectively implanted with boron with relatively high concentration using the resist pattern 76 and gate electrode 6 as a mask to provide a high-concentration p-type semiconductor region 89. In the step of Fig. 33 (a section taken along the line A3-A3) and Fig. 34 (a section taken along the line B3-B3), the resist pattern 76 is removed, and the boron in the high-concentration p-type semiconductor region 89 is diffused by drive-in process to provide the high-concentration p-type semiconductor region 35 of Figs. 27 and 28. At this time, the boron in the high-concentration p-type semiconductor region 88 is also diffused to provide the high-concentration p-type semiconductor region 34. The succeeding process steps are the same as the process steps of Figs. 16 to 22 of the first preferred embodiment. 4. Fourth Preferred Embodiment 4-1. Structure of Device Fig. 35 is a plan view of an N-channel IGBT 500 according to a fourth preferred embodiment of the present invention. The IGBT 500 comprises a multiplicity of IGBT unit cells 510 connected in parallel as well as the IGBTs of the first to third preferred embodiments. The emitter electrode 7 and oxide film 8 are not illustrated in Fig. 35. The dotted lines of Fig. 35 represent the configurations of various mask patterns to be used in the process steps for fabrication of the IGBT 500. Fig. 36 is a cross-sectional view of one of the IGBT unit cells 510 taken along the line A4-A4 of Fig. 35. The device of the fourth preferred embodiment has a combination of the features of the devices of the second and third preferred embodiments as shown in Figs. 35 and 36. Similarly to the device of the third preferred embodiment, a high-concentration p-type semiconductor region 36 to be formed for providing the n-type channels having the relatively high gate threshold voltage V GE (th-High) is formed independently of the high-concentration p-type semiconductor region 34 for suppression of the parasitic thyristor effect. Similarly to the device of the second preferred embodiment, the high-concentration p-type semiconductor region 36 extends over the p-type base region 3 into the n-type epitaxial layer 2 around the line A4-A4 where the n-type emitter regions 4 are relatively wide as viewed from the top. The cross-section taken along the line B4-B4 is of the same configuration as the cross-section taken along the line B3-B3 of the third preferred embodiment. That is, the cross-section taken along the line B4-B4 (not shown) is provided by replacing the high-concentration high-concentration p-type semiconductor region 35 of Fig. 28 with the p-type semiconductor region 36. 4-2. Characteristic of Device The IGBT 500 of the fourth preferred embodiment constructed as above described has a combination of the characteristics of the devices of the second and third preferred embodiments. The channel length of the n-type channels having the relatively high gate threshold voltage V GE (th-High) formed by the high-concentration p-type semiconductor region 36 in the same manner as the second preferred embodiment is longer than the channel lengths of the first and third preferred embodiments, so that the device of the fourth preferred embodiment is advantageously more effective for reduction in saturation current I CE (sat). Furthermore, the high-concentration p-type semiconductor region 34 for reduction in saturation current I CE (sat) and the high-concentration p-type semiconductor region 36 for suppression of the parasitic thyristor effect are optimized independently in the same manner as the third preferred embodiment, so that the device of the fourth preferred embodiment is more effective for both of the purposes. 4-3. Process Steps for Fabrication of Device Figs. 37 and 38 are cross-sectional views of the IGBT unit cell 510 taken along the line A4-A4 of Fig. 35 in a process step for fabrication of the IGBT 500. Referring to Figs. 37 and 38, description will be given on the process steps for fabricating the IGBT 500 of the fourth preferred embodiment. The same process steps as those down to the step of Fig. 30 of the third preferred embodiment are carried out. The process then proceeds to the step of Fig. 37. A resist layer is provided over the gate electrode 6 and silicon oxide film 71. Photolithography process is carried out on the resist layer using the mask 82 having a pattern corresponding to the mask pattern 56 of Fig. 35 to provide the resist pattern 83 corresponding to the mask pattern 56. The high-concentration p-type semiconductor region 88, p-type base region 3 and n-type epitaxial layer 2 are selectively implanted with boron with high energy with high concentration using the resist pattern 83 as a mask to provide a high-concentration p-type semiconductor region 90. The process then proceeds to the step of Fig. 38. The resist pattern 83 is removed, and the boron in the high-concentration p-type semiconductor region 90 is diffused by drive-in process to provide the high-concentration p-type semiconductor region 36. At this time, the boron in the high-concentration p-type semiconductor region 88 is also diffused to provide the high-concentration p-type semiconductor region 34. Since the mask pattern 56 used in the step of Fig. 37 is shaped so that it is wide around the line A4-A4 of Fig. 35 and narrow around the line B4-B4 of Fig. 35, the high-concentration p-type semiconductor region 36 extends to the part of the n-type epitaxial layer 2 which underlies the gate electrode 6 around the line A4-A4. The cross-section taken along the line B4-B4 after this process step is provided by replacing the high-concentration p-type semiconductor region 35 in the cross-section taken along the line B3-B3 of the third preferred embodiment shown in Fig. 34 with the high-concentration p-type semiconductor region 36. The high-concentration p-type semiconductor regions 34 and 36 are confined to the inside of the opening 6a of the gate electrode 6. The succeeding process steps are the same as the process steps succeeding the step of Figs. 33 and 34 of the third preferred embodiment. 5. Modifications of First to Fifth Preferred Embodiment (1) In the above-mentioned preferred embodiments, the high-concentration p-type semiconductor regions 32, 33, 35 and 36 in which the n-type channels having the relatively high gate threshold voltage V GE (th-High) are to be formed are provided in the regions R1 in which the n-type emitter regions 4 are relatively wide as viewed from the top for the purpose of causing the high-concentration p-type semiconductor regions 32, 33, 35 and 36 to effectively function to suppress the parasitic thyristor effect. The parts of the high-concentration p-type semiconductor regions in which the n-type channels having the rclatively high gate threshold voltage V GE (th-High) are to be formed may be provided in the other regions. In this case, the effect of reducing the saturation current I CE (sat) is obtained. (2) Although the devices of the above-mentioned preferred embodiments are the N-channel IGBT, the present invention may be applied to a P-channel IGBT having the semiconductor layers of reverse polarities. Fig. 39 illustrates a device comprising the semiconductors having the polarities reverse to those of the first preferred embodiment. Fig. 39 is a front sectional view of an IGBT unit cell in a corresponding position to Fig. 2. The polarities of the semiconductor layers 1a to 4a and 32a of Fig. 39 are reverse to those of the semiconductor layers 1 to 4 and 32 of Fig. 2. (3) In the above-mentioned preferred embodiments, the gate voltage V GE is larger than the gate threshold voltage V GE (th-High). The impurity concentration of the high-concentration p-type semiconductor regions 32 and 33 may be increased so that the gate voltage V GE is not larger than the gate threshold voltage V GE (th-High). In this case, the effect for reduction in collector-emitter saturation voltage V CE (sat) is lessened to some degree, however, the effect for reduction in saturation current I CE (sat) is enhanced to provide a higher short-circuit tolerance. (4) The region having the high gate threshold voltage V GE (th) need not be located uniformly in all of the IGBT unit cells but may be located in a particular portion in the IGBT chip. For example, the location of the region such that the concentration of the collector current Ic is suppressed on the patterns of the IGBT chip provides for a similarly improved effect. (5) The present invention is not limited to IGBTs but may be applied to general insulated gate semiconductor devices (e.g., power MOSFETs, ESTs, MCTs). 5. Fifth Preferred Embodiment Characteristic of Device An IGBT according to a fifth preferred embodiment of the present invention will be hereinafter described which has a similar cross-sectional structure to those of the IGBTs 200 to 500 and 200a of the precedent respective preferred embodiments. The emitter bypass ratio e is optimized in the IGBT of the fifth preferred embodiment. Fig. 43 is a plan view showing the structure of the IGBT 200a used in a measurement in order to find optimal parameters. A number of IGBT unit cells each constructed as an IGBT unit cell 210a of Fig. 43, when connected parallel to each other, form the IGBT 200a, which feature being the same as in the case of the IGBT unit cell 210 of Fig. 1. An n-type emitter region 4a, a high-concentration p-type semiconductor region 32a, a mask pattern 53a and a mask pattern 54a correspond to the n-type emitter region 4, the high-concentration p-type semiconductor region 32, the mask pattern 53 and the mask pattern 54 of the IGBT unit cell 210, respectively. This IGBT unit cell 210a is different from the IGBT unit cell 210a of Fig. 4 in that at a region other than where the high-concentration p-type semiconductor region 32a has a wide width (i.e., except for the region around the line A1a-A1a), two n-type emitter regions 4a which are arranged like two strips running parallel to each other do not have a mutually-connected portion (i.e., the portion in the vicinity of the line C1a-C1a in Fig. 4). The cross-sectional structures of the IGBT unit cell 210a taken along the line A1a-A1a and the line B1a-B1a are as shown in Figs. 5 and 3, respectively. Referring to the width of the n-type emitter region 4a as a width X and referring to the width of a region otherwise, i.e., the exposed portion of the p-type base region 3 at the top major surface of the semiconductor body 220 as a width Y in the n-type emitter pattern shown in Fig. 43, the emitter bypass ratio e is defined by Formula (4a) as described before. In the top major surface of the semiconductor body 220, the region where the high-concentration p-type semiconductor region 32a exists between the n-type emitter region 4a and the n-type epitaxial layer 2 has a length H, while the region where the n-type emitter region 4a is isolated by the p-type base region 3 alone without any intervening high-concentration p-type semiconductor region 32a has a length L as shown in Fig. 43. Here, as described earlier, the high gate threshold voltage region percentage g is defined by Formula (5) using these lengths H and L. A decrease in the emitter bypass ratio e reduces the area size and hence the emitter resistance of the n-type emitter region 4a. This is equivalent to an increase in the source resistances which are connected equivalently in series to each other in the MOSFET region, and therefore suppresses the flow of an electron current in the MOSFET region. This in turn would reduce the short-circuit current of the IGBT, which would improve the short-circuit tolerance. On the other hand, an increased high gate threshold voltage region percentage g would suppress the short-circuit current as described earlier, thereby improving the short-circuit tolerance. In the IGBT 200a of Fig. 43, if the ratio of the width X to the width Y is changed, the ratio of the length H to the length L accordingly changes with an approximately the same gradient. That is, when the emitter bypass ratio e increases, the high gate threshold voltage region percentage g accordingly increases with an approximately the same gradient. More precisely, by measuring the short-circuit tolerance of the IGBT 200a while changing the ratio of the width X to the width Y and hence the ratio of the length H to the length L, it is possible to find which one would more efficiently improve the short-circuit tolerance a decreased emitter bypass ratio e or an increased high gate threshold voltage region percentage g. Fig. 44 is a graph showing measurements of the collector-emitter saturation voltage V CE (sat), the saturation current density (i.e., load short-circuit current density) J CE (sat) and the short-circuit tolerance tw with respect to the emitter bypass ratio e in the IGBT 200a of Fig. 43. Although not shown in Fig. 44, with an increase and a decrease in the emitter bypass ratio e, the high gate threshold voltage region percentage g increases and decreases accordingly as mentioned above. The rated values of the collector-emitter voltage V CE and the collector current I CE of the IGBT 200a used in the measurement are 600V and 100A, respectively. The collector-emitter saturation voltage V CE (sat) falls to its minimum value while the saturation current density J CE (sat) approaches its maximum value as the emitter bypass ratio e increases. On the other hand, with an increase in the emitter bypass ratio e, the short-circuit tolerance tw monotonously decreases while reaching saturation. In an area where the emitter bypass ratio e is large, an increase in the emitter bypass ratio e reduces the saturation current density J CE (sat). In other words, in this area, the high gate threshold voltage region percentage g has a larger control of the saturation current density J CE (sat) than the emitter bypass ratio e. The fact to be noted here, however, is that nevertheless in this area, the short-circuit tolerance tw decreases against an increase in the emitter bypass ratio e. This means that the emitter bypass ratio e has a larger control of the saturation current density J CE (sat) than the high gate threshold voltage region percentage g. Hence, in order to achieve the short-circuit tolerance tw of a desired level, a suppressed emitter bypass ratio e is more effective than an increased high gate threshold voltage region percentage g. A practical competent short-circuit tolerance tw is equal to or larger than 10 µ s. Adding an extra 2 µ s to this value, 12 µ s is the practical lower limit of the short-circuit tolerance tw. In the graph of Fig. 44, tw=12 µ s is equivalent to e=25%. It then follows that the practically needed value of the short-circuit tolerance tw is obtained if the emitter bypass ratio e is 25% or less. On the other hand, there is a practical desirable upper limit to the collector-emitter saturation voltage V CE (sat), which is about 2.4V. In the graph of Fig. 44, the emitter bypass ratio e which corresponds to this practically desirable upper limit of the collector-emitter saturation voltage V CE (sat) is about 5%. Hence, the practically desired lower limit of the emitter bypass ratio e is 5%. The fact indicated in Fig. 44 that the emitter bypass ratio e has a strong influence over the short-circuit tolerance tw leads one to reach to a general assumption that the emitter resistance has a strong influence over the short-circuit tolerance tw. Fig. 45 is a graph showing measurements which verify this assumption. In short, the measurements shown in Fig. 45 are values of the respective characteristics against changes in the sheet resistance of the n-type emitter region 4a in the IGBT 200a which has a certain structure in which the collector-emitter saturation voltage V CE (sat) is minimum as in Fig. 44 (That is, the emitter bypass ratio e is 16.7%). As assumed above, the short-circuit tolerance tw has a strong dependence on the value of the sheet resistance. More particularly, with an increase in the sheet resistance of the n-type emitter region 4a, the short-circuit tolerance tw proportionally increases. The saturation current density J CE (sat) keeps decreasing, which is also the same as expected. On the other hand, the collector-emitter saturation voltage V CE (sat) shows almost no dependence on the sheet resistance. Hence, by setting the sheet resistance of the n-type emitter region 4a at a large value, the short-circuit tolerance tw can be reduced to a desired amount almost without influencing a loss at the regular device operation. In the graph of Fig. 45, the emitter sheet resistance which corresponds to the practically desirable short-circuit tolerance tw of 10 µ sec is 40Ω/□. The emitter sheet resistance which corresponds to the practically needed collector-emitter saturation voltage V CE (sat) of 2.4V is 150Ω/□. Therefore, a practically desirable value of the sheet resistance is in the range between 40Ω/□ and 150Ω/□. More preferably, the sheet resistance is somewhere between 60Ω/□ and 120Ω/□. A large sheet resistance at the n-type emitter region 4a extends the transition period between the device turn-on and turn-off, whereby a loss at switching operation of the device is somewhat increased. To deal with this, the transition period is reduced by reducing the resistance value at the gate electrode 6. A smaller resistance value at the gate electrode 6 which is made of polysilicon is achieved by introducing an n-type impurity such as As. Fig. 46 is a graph showing the sheet resistance at the polysilicon gate electrode 6 against a loss due to the device turn-on. From Fig. 46, it is understood that the loss becomes smaller as the sheet resistance decreases. The practically competent upper limit of the loss is around 5.6mJ/pulse. In Fig. 46, a value of the sheet resistance which corresponds to this upper limit is 250Ω/□. Thus, the practically competent value of the sheet resistance is 250Ω/□ or less. More preferably, the sheet resistance is 200Ω/□ or less. Manufacturing Method of IGBT A method of fabricating the IGBT of the fifth preferred embodiment will be described as an IGBT 200 which has a similar cross-sectional structure to that of the IGBT 200 of Fig. 1. Example 1 of Manufacturing Method Fig. 47 is a cross-sectional view of the IGBT unit cells 210 taken along the line B1-B1 as it is during the first example of the manufacturing method of the IGBT 200. The manufacturing processes of the IGBT 200 of the fifth preferred embodiment will be described with Fig. 47. First, process steps similar to those shown in Figs. 8 to 15 with respect to the IGBT 200 of the first preferred embodiment are carried out, followed by the process step shown in Fig. 47 where a resist layer is formed all over the polysilicon gate electrode 6 and the silicon oxide film 71. Through a mask 82 which includes a mask pattern 56 which is configured similarly to the mask pattern 54 of Fig. 1, a resist pattern 83 corresponding to the mask pattern 56 is then printed by a photolithographic technique. Further, an amount of As is selectively injected into the gate electrode 6 through the resist pattern 83 to thereby suppress the sheet resistance of the gate electrode 6 in advance. The resist pattern 83 is then removed, and process steps similar to those shown in Figs. 16 to 21 are carried out. At the process steps shown in Figs. 18 and 19, an impurity is introduced into the gate electrode 6 again at the same time that the impurity is introduced into a top major surface of a semiconductor body 1. The amount of the impurity introduced at this stage is appropriately set so that the n-type emitter region 4 as desired will be defined in the top major surface of the semiconductor body 1. Hence, the amount of the impurity which is introduced into the gate electrode 6 at the process step shown in Fig. 47 is adjusted in advance so as to ensure that the gate electrode 6 has a predetermined sheet resistance when all the process steps are complete. Example 2 of Manufacturing Method Fig. 48 is a cross-sectional view of the IGBT unit cells 210 taken along the line B1-B1 as it is during the second example of the manufacturing method of the IGBT 200. The manufacturing processes of the IGBT 200 of the fifth preferred embodiment will be described with Fig. 48. First, process steps similar to those shown in Figs. 8 to 19 with respect to the IGBT 200 of the first preferred embodiment are carried out. Next, a process step shown in Fig. 48 is executed where a resist layer is formed all over the polysilicon gate electrode 6 and the silicon oxide film 71 (i.e., the oxide film pattern 80 which is left remaining in the gate insulating film 5 and the central area). Through a mask 82 which includes a mask pattern 56 which is configured similarly to the mask pattern 54 of Fig. 1, a resist pattern 83 corresponding to the mask pattern 56 is then printed by a photolithographic technique. Further, an amount of As is selectively injected into the gate electrode 6 through the resist pattern 83 to thereby suppress the sheet resistance of the gate electrode 6. The resist pattern 83 is then removed, and process steps similar to those shown in Figs. 20 and 21 are carried out. At the process steps shown in Figs. 18 and 19, an impurity is introduced into the gate electrode 6 in advance at the same time that the impurity is introduced into the top major surface of the semiconductor body 1. The amount of the impurity introduced at this stage is appropriately set so that the n-type emitter region 4 as desired will be defined in the top major surface of the semiconductor body 1. Hence, the amount of the impurity which is introduced into the gate electrode 6 again at the process step shown in Fig. 48 is adjusted so as to ensure that the gate electrode 6 has a predetermined sheet resistance when all the process steps are complete. Example 3 of Manufacturing Method Fig. 49 is a cross-sectional view of the IGBT unit cells 210 as it is during the third example of the manufacturing method of the IGBT 200. The manufacturing processes of the IGBT 200 of the fifth preferred embodiment will be described with Fig. 49. First, process steps similar to those shown in Figs. 8 and 9 with respect to the IGBT 200 of the first preferred embodiment are carried out, followed by the process step shown in Fig. 49 where the polysilicon gate electrode 6 is disposed all over the silicon oxide film 71. Next, a predetermined amount of As is injected into the gate electrode 6 so that the sheet resistance of the gate electrode 6 is reduced beforehand. Following this, process steps similar to those shown in Figs. 10 to 21 are carried out. At the process steps shown in Figs. 18 and 19, an impurity is introduced into the gate electrode 6 again at the same time that the impurity is introduced into a top major surface of a semiconductor body 1. The amount of the impurity introduced at this stage is appropriately set so that the n-type emitter region 4 as desired will be defined in the top major surface of the semiconductor body 1. Hence, the amount of the impurity which is introduced into the gate electrode 6 at the process step of Fig. 49 is adjusted in advance so that the gate electrode 6 has a predetermined sheet resistance when all the process steps are complete. Alternatively, the gate electrode 6 may be formed by such polysilicon which is doped in advance with phosphorus or other suitable impurities (i.e., doped polysilicon), instead of being formed by introduction of the impurity thereinto as is done at the process step of Fig. 49. In such a case, the concentration of the doping impurity is adjusted beforehand so that the gate electrode 6 has a predetermined sheet resistance when all the process steps are complete. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention as defined by the appended claims.

Claims: An insulated gate semiconductor device comprising: (a) a semiconductor body (220) having a top major surface and a bottom major surface and comprising; (a-1) a first semiconductor region (2) of a first conductivity type exposed at said top major surface of said semiconductor body (220); (a-2) a second semiconductor region (3) of a second conductivity type located in a top surface portion of said first semiconductor region (2) and exposed at said top major surface of said semiconductor body (220), the exposed top surface of said second semiconductor region (3) having a peripheral edge portion; (a-3) a third semiconductor region (4) of the first conductivity type located in a top surface portion of said second semiconductor region (3) and exposed at said top major surface of said semiconductor body (220) inside said peripheral edge portion of the exposed top surface of said second semiconductor region (3), wherein said third semiconductor region (4) forms a pattern on said top major surface of said semiconductor body (220), said pattern including a pair of strip areas (BA), said strip areas (BA) being arranged in parallel and separated by a central area (CA); (a-4) a fourth semiconductor region (32, 33, 34, 35, 36) of the second conductivity type having an impurity concentration higher than the impurity concentration of said second semiconductor region (3), wherein said fourth semiconductor region (32, 33, 34, 35, 36) is located in a top surface portion of said semiconductor body (220), said third semiconductor region (4) is located in said fourth semiconductor region (32, 33, 34, 35, 36), and said fourth semiconductor region (32, 33, 34, 35, 36) comprises a first portion (32B) exposed at said top major surface of said semiconductor body (220) in said central area and extending beneath the third semiconductor region (4) so that outer edges of said first portion (32B) with respect to said central area (CA) are coincident with outer edges of said third semiconductor region (4) with respect to said central area (CA), and a second portion (32A) exposed at said top major surface of said semiconductor body (220) in an outer area located between said pair of strip areas (BA) and the exposed top surface of said first semiconductor region (2); (b) an insulating layer (5, 8) located on said top major surface of said semiconductor body (220) and having an opening (WD) on a region covering part of said pair of strip areas (BA) and at least part of said central area (CA); (c) a control electrode layer (6) buried in said insulating layer (5, 8) and overlying the portions of the exposed top surfaces of said second semiconductor region (3) and said second portion (32A) of said fourth semiconductor region (32, 33, 34, 35, 36) located between said pair of strip areas (BA) of said third semiconductor region (4) and the exposed top surface of said first semiconductor region (2); (d) a first main electrode layer (7) formed in said opening (WD) of said insulating layer (5, 8) and electrically connected to a portion of said top major surface of said semiconductor body (220) exposed in said opening (WD); and (e) a second main electrode layer (9) formed on said bottom major surface of said semiconductor body (220) and electrically connected to said semiconductor body (220), wherein a sheet resistance of said third semiconductor region (4) is equal to or larger than 40 Ω/□. The insulated gate semiconductor device of claim 1, characterized in that, said pair of strip areas (BA) includes first and second strip areas, and said pattern further includes first and second teeth projecting from said first and second strip areas toward said central area, respectively. The insulated gate semiconductor device of claim 2, characterized in that, said first and second teeth are connected to each other, whereby said pattern defines a ladder pattern. The insulated gate semiconductor device of claim 2, characterized in that, said outer area is aligned with said first and second teeth. The insulated gate semiconductor device of claim 4, characterized in that, said second portion of said fourth semiconductor region (33, 36) projects from over said second semiconductor region (3) into the area in which said first semiconductor region (2) is exposed to said top major surface of said semiconductor body (220). The insulated gate semiconductor device of claim 4, characterized in that, said fourth semiconductor region (32) comprises: (a-4-1) a third portion (35, 36) exposed to said top major surface of said semiconductor body (220); and (a-4-2) a fourth portion (34) projecting from a bottom of said first portion (35, 36) into said second semiconductor region (3). The insulated gate semiconductor device of claim 6, characterized in that, said fourth portion (34) has an impurity concentration higher than the impurity concentration in said third portion (35, 36). The insulated gate semiconductor device of claim 1, characterized in that, said semiconductor body (220) further comprises: (a-5) a fifth semiconductor region (1) of the second conductivity type formed under said first semiconductor region (2) and exposed at said bottom surface of said semiconductor body (220). The insulated gate semiconductor device of claim 1, characterized in that, said first main electrode layer (7) contacts exposed top portions of said third (4) and fourth (32, 33, 34, 35, 36) semiconductor regions in said opening (WD), and the exposed portions of said third semiconductor region (4) contacting said first main electrode layer (7) having an area Al, the exposed portions of said fourth semiconductor region (32) contacting said first main electrode layer (7) having an area A2, the ratio A1/(A1 + A2) is less than 50 %. The insulated gate semiconductor device of claim 9, wherein said ratio A1/(A1+A2) is 5 % to 25 %. The insulated gate semiconductor device of claim 1, characterized in that, said outer area comprises a plurality of outer area portions periodically aligned at a period (H+L) in an elongated direction of said pair of strip areas (BA), and the ratio of the length (H) of each outer area portion in said elongated direction of said pair of strip areas (BA) to said period (H+L) is not less than 20 %. The insulated gate semiconductor device of claim 1, characterized in that said sheet resistance of said third semiconductor region (4) is in the range between 40Ω/□ and 150Ω/□. The insulated gate semiconductor device of claim 1, characterized in that a sheet resistance of said control electrode layer (6) is not more than 250Ω/□. A method of fabricating an insulated gate semiconductor device of claim 1, comprising the steps of: (a) providing a semiconductor body (220) having a top major surface and a bottom major surface and including a first semiconductor region (2) of a first conductivity type exposed at a top major surface of said semiconductor body; (b) forming an oxide film (71) on said top major, surface of said semiconductor body (220); (c) forming a control electrode layer (6) having a first opening (6a) of a substantially strip configuration on said oxide film (71) over said first semiconductor region (2); (d) obtaining a second semiconductor region (3) of a second conductivity type under said first opening (6a), wherein said second semiconductor region (3) extends to a part of said semiconductor body (220) underlying said control electrode layer (6); (e) selectively providing a mask pattern (76) on said oxide film (71) and said control electrode layer (6), said mask pattern being provided with a second opening partially overlapped with said first opening (6a); (f) obtaining in said semiconductor body under said second opening a further semiconductor region (32, 33, 34, 35, 36) of the second conductivity type having a impurity concentration higher than the impurity concentration of said second semiconductor region (3), wherein said further semiconductor region (32, 33, 34, 35, 36) extends to a part of said semiconductor body (220) underlying said control electrode layer (6); (g) selectively removing a portion of said oxide film (71) lying under said first opening to obtain a pair of strip windows arranged substantially in parallel and an oxide region (80) remaining on a central area (CA) defined between said pair of strip windows; (h) selectively introducing a first impurity of the first conductivity type into said top major surface of said semiconductor body (220) using said oxide region (80) and said oxide film (5) lying under said control electrode layer as a mask to obtain a third semiconductor region (4) of the first conductivity type in said further semiconductor region (32, 33, 34, 35, 36), said third semiconductor region (4) being exposed to said top major surface to define a pair of strip areas (BA) on said top major surface, wherein a dose of said first impurity introduced into said top major surface of said semiconductor body is such that a sheet resistance of said third semiconductor region (4) is equal to or larger than 40Ω/□; (i) removing said oxide region (80); (j) forming an insulating layer (8) having a third opening (8a) on a region of said top major surface of said semiconductor body (220), said insulating layer (8) covering part of said pair of strip areas (BA) and at least part of said central area (CA), said insulating layer (8) also covering side and top surfaces of said control electrode layer (6); (k) providing in said third opening (8a) a first main electrode layer (7) electrically connected to said top major surface of said semiconductor body (220); and (l) forming on a bottom major surface of said semiconductor body (220) a second main electrode layer (9) electrically connected to said bottom major surface of said semiconductor body (220). The method of claim 14, wherein said step (d) comprises the steps of: (d-1) selectively introducing a second impurity (74) of the second conductivity type into said top major surface of said semiconductor body (220) through said first opening (6a); and (d-2) selectively diffusing said second impurity (74) into a part of said semiconductor body (220) underlying said control electrode layer (6), thereby obtaining said second semiconductor region (3). The method of claim 15, wherein said step (f) comprises the steps of: (f-1) selectively introducing a third impurity (77) of the second conductivity type into said top major surface of said semiconductor body (220) through said second opening; and (f-2) selectively diffusing said third impurity (77) into a part of said semiconductor body (220) underlying said control electrode layer (6) thereby obtaining said further semiconductor region (32, 33, 34, 35, 36). The method of claim 16, wherein said step (g) comprises the step of: (g-1) selectively removing said portion of said oxide film (71) such that said pair of strip areas (BA) includes first and second strip areas (BA) and first and second teeth windows projecting from said first and second strip areas (BA) toward said central area (CA), respectively. The method of claim 14, wherein at said step (c), said control electrode layer (6) is made of a semiconductor, said method further comprising the step of (m) selectively introducing an impurity of the first conductivity type into said control electrode layer (6), and wherein said impurity is introduced at said step (m) in such a manner that a sheet resistance of said control electrode layer (6) is equal to or smaller than 250Ω/□ after both said step (h) and said step (m). The method of claim 18, wherein said step (m) is carried out prior to said step (j), and said step (m) comprises the steps of: (m-1) forming a second mask pattern for preventing introduction of an impurity, said second mask pattern covering said first opening (6a) on said top major surface of said oxide film; (m-2) selectively injecting an impurity of the first conductivity type into said control electrode layer (6) through said second mask pattern; and (m-3) removing said second mask pattern. The method of claim 14, wherein said step (c) comprises the steps of: (c-1) forming on said oxide film (71) a semiconductor layer comprising an impurity of the first conductivity type; and (c-2) forming a substantially strip-shaped first opening (6a) on said oxide film (71) in said semiconductor layer to thereby form said control electrode layer (6) from said semiconductor layer, wherein said impurity of the first conductivity type is such that a sheet resistance of said control electrode layer is equal to or smaller than 250Ω/□ after said step (h). The method of claim 20, wherein said step (c-1) comprises the steps of: (c-1-1) forming a semiconductor layer on said oxide film (71); and (c-1-2) introducing an impurity of the first conductivity type into said semiconductor layer.

Inventors: HAGINO HIROYASU, TOMOMATSU YOSHIFUMI, YAMAGUCHI HIROSHI, HAGINO, HIROYASU, TOMOMATSU, YOSHIFUMI, YAMAGUCHI, HIROSHI, HAGINO, HIROYASU, C/O MITSUBISHI DENKI K. K., TOMOMATSU, YOSHIFUMI, C/O FUKURYO SEMICONDUCTOR, YAMAGUCHI, HIROSHI, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H01L29
IPC codes: H01L29, H01L21