Byte erasable EEPROM fully compatible with a single power supply flash-EPROM process

Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLAS-EPROM process is composed by a matrix of FLASH-EPROM cells organized in an n number of bytes each of an m number of bits addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistors. EEPROM functionality is obtained without any modification of the standard FLASH-EPROM fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.

Description: The present invention relates to the realization on the same chip containing a FLASH-EPROM memory of a byte erasable memory block, that is with the same functionality of a conventional EEPROM memory, in a fully compatible manner with a normal fabrication process of a FLASH-EPROM memory. device with single. supply, without requiring any additional process steps. The development of nonvolatile memories based on the principle of trapping an electrical charge in an isolated (floating) gate of a field effect transistor (cell) in order to modify its turn-on threshold, has had and continues to have an extremely important role in the achievement of ever increasing levels of compactness and of speed of integrated systems. The development of such memories is strictly tied to a parallel development of suitable fabrication technologies and to the physical mechanisms that can be practically exploited for injecting electrical charges in a floating gate through an isolating dielectric, which often constitutes also the gate dielectric of the (transistor) cell. The physical mechanisms that are normally exploited are the following: the so-called Fowler-Nordheim tunnelling mechanism that is operative with relatively thick oxide layers and requires a strong electric field; the direct tunneling mechanism that is operative with relatively thin oxide layers and with a relatively strong electric field; a "modified" Fowler-Nordheim tunnelling mechanism that is operative with a thin dielectric layer and with an electric field of medium intensity ; the charge-trap assisted injection mechanism wherein charge trapping sites are rearranged at the interface between the conductor and the dielectric and which is effective with thin dielectrics and with a relatively low electric field intensity; the channel hot carriers injection mechanism that is operative throughout an ample range of dielectric thicknesses and of electric field intensities. Of course, the tunnelling mechanisms may theoretically be exploited also for extracting (discharging) electric charges from the floating gate, that is for "erasing" the cell, even though the voltages that are required must be compatible with the physical-electrical structure of the cell. It is evident how the charge and discharge mechanisms of the floating gate condition the structure of the memory cell as well as the overhead (ancillary) circuitry, with a particular regard to writing, reading and eventually also erasing circuits of the memory, by posing case-by-case precise requisites of voltage and current levels necessary for programming and eventually erasing data stored in the memory, beside those that are required during a reading phase. The requirement of altering the content of the memory by single bytes (herein intended to constitute a unit of information composed by a certain number of bits, for example 8, 16, 32, etc.) without having to reprogram the entire memory as in the case of the so-called EPROM memories, and therefore the requirement of being able to erase certain selected cells while leaving unchanged the information content of other cells, had led to develop so-called EEPROM or E 2 PROM cells, both acronyms of Electrically Erasable and Programmable Read Only Memory. Typically, the problem tied to the necessity of biasing the floating gate through its capacitive coupling with a control gate and the semiconducting substrate in order to charge the floating gate and eventually discharge the electrical charge stored therein, has been satisfied by realizing' a capacitive coupling zone between the floating: gate and a drain region of the semiconducting substrate through a thin tunnelling oxide. Through such a tunnelling window, the flow of electrons from the isolated gate and the drain region of the substrate and vice-versa, during an erasing phase and during a programming phase, is obtained through a Flowler-Nordheim tunnelling mechanism by applying a sufficiently high voltage of one sign or of the opposite sign. Byte erasability of EEPROM memories is achieved with a penalty in terms of compactness of the matrix of memory cells. Overall the cells are from three to four times larger than an EPROM cell, for the same fabrication technology, because they require a select transistor associated with each cell. The fabrication process of an EEPROM memory is notably much more complex of an EPROM process and the EEPROM memory requires a relatively more complex overhead circuitry as well as the integration of voltage multipliers. A schematic cross section of an EEPROM cell is shown in Fig. 1, while an electrical scheme of an EEPROM memory array is shown in Fig. 2, which contains also a table showing the typical operation voltages. On the other hand, the improvement of fabrication technologies has allowed a further reduction of the thickness of the isolation dielectric between a floating gate and the monocrystal silicon. substrate while' reliably ensuring a substantial absence of defects with an average growth thickness of the oxide of about 12nm (120A). This has permitted the development of the so-called FLASH-EPROM or more simply FLASH memories. The FLASH memory cell is programmable through a mechanism of injection in the floating gate of hot channel electrons, by biasing the gate (control gate) with a positive voltage sufficiently high (for example in the order of 12V) and the drain with a voltage of about 6V, in order to produce in the channel zone of the monocrystalline silicon substrate of the cell a strong electric field suitable to generate a current of highly energetic (hot) electrons within the silicon, capable of overcoming the potential barrier at the interface with dielectric and of being thereafter attracted toward the floating gate by the electric field. By virtue of the extreme thickness of the dielectric, by applying a relatively high voltage (12V) to the source region and maintaining the other electrodes to ground potential, the electrons that have been injected in the floating gate are able to cross the dielectric according to a Flowler-Nordheim tunnelling mechanism and "discharge" in the source region, during an erasing phase. The possibility of electrically erasing the memory device without removing it from the printed circuit card for exposing it to UV light, has solved a most severe problem of traditional EPROM memories. With the overcoming of this limitation, all the intrinsic advantages and potentialities of this type of memories, such as their extreme compactness, speed and above all their relatively low cost, have opened an extremely vast field of application. On the other hand, being the FLASH memory cells without any select transistor, during an erasing phase, some cells rather than others, may reach a depletion state, assuming in practice a negative threshold. If this occurs, during a reading phase of the memory, being all wordlines grounded with the exception of the wordline to be read, not all the other cells of the addressed bitline would be nonconducting if any of these happened to have been depleted during a preceding erasing (a logic "zero" being the information stored in such cells) and this would cause reading errors. For this reason, the erasing process of FLASH memories is intrinsically a critical process and is commonly carried out through a succession of pulses of an erasing bias voltage followed by a check until completing the erasing of all the cells of the memory while avoiding to inadvertently bring some of the cells to a depletion state. This erasing process engages in a nonnegligeable manner the microprocessor that is called to supervise the erasing process of the FLASH memory. Upon completing the erasing of the memory, differently from EEPROM cells which because they are provided of a select transistor ensure in any condition a uniform threshold, identical to the threshold of a virgin cell, individual FLASH-EPROM cells assume a threshold of a value that is not uniform and constant but is normally contained within a certain range of variation. In other words there is a "dispersion" or spread of the threshold values of erased cells, the breath of which is tied also to parameters of the fabrication process. Such a spread of the threshold values of the cells must be taken into account by the circuitry that manages the memory. For obviating to this drawback of FLASH-EPROM memories, a particular cell structure has been proposed, wherein each control gate line (wordline) of the memory array overlies (is capacitively coupled) only for a portion of its width, the relative floating gates of the cells of the row, while with a portion of its width the wordline constitutes the gate of as many select transistors, each associated to a respective memory cell of the row. In this way, though with a penalty in terms of compactness, a select transistor is associated to each cell, thus making uniform the threshold voltage of all the cells once the erasing of the memory array is performed. This technique is described in the paper entitled "A 128K FLASH-EEPROM using Double Polysilicon Technology" by George Samachisa, Chien-Sheng Su, Yu-Sheng Kao, George Smarandoiu, Ting Wong, Chenming Hu, presented at the IEEE International Solid-State Circuits Conference of February 25, 1987. Nothwithstanding the relatively low cost, speed and compactness of FLASH-EPROM memories, there are particular areas of application of memory devices, wherein, a need of associating to a FLASH memory also a memory block (typically of much lower capacity) of the EEPROM type in which to store data that need to be frequently altered (updated) remains. These requirements generally insist on systems wherein only a small portion of the data stored in a permanent (nonvolatile) manner is destined to repeated updatings, differently from a vast mass of data destined to remain unvaried in time or to be modified only after relatively long intervals of time or only in consequence of exceptional events. Situations of this type are common in the field of automatic control, regulation, selfdiagnostic systems 'and the like that are increasingly being employed in the car industry and' in similar industries, wherein periodically it is necessary to modify/update certain data relative to tests, maintenance, modification of the values of certain parameters of operation and so forth. Block-erasable FLASH-EPROM memories have been proposed to meet these market demands. According to one of these techniques, the possibility of erasing the memory array by blocks is obtained by segmenting the source lines (source diffusions), the use of a further level of metal to define a further order of metal lines to which the portions or segments of source lines are connected through interconnection vias and the realization of an additional decoder for selecting the blocks of the memory array to be erased. A .system' of this type is disclosed in US-A-5,289,423. These techniques are intrinsically unflexible to meet in an optimum way, different requirements of users and imply a remarkable complication of the layout of the memory array because of the increased number of metal levels and of the need to form a large number of "by-passes" at cross points between orthogonal lines of the same level. In the majority of cases, the requirements of the users could be satisfied in an optimum way by realizing an EEPROM memory block of sufficient size, in the same chip containing the FLASH-EPROM memory, typically of much larger capacity, thus avoiding the need of employing two distinct memory devices. On the other hand, it is evident the difficulty of compatibly integrating in the same device a FLASH-EPROM memory and an EEPROM memory because of their structural diversity and of the different requisites in terms of voltage levels and current handling capacity of the ancillary circuitry. Problems of compatibility that are even more marked in case of "single supply processes" and which therefore would require different integrated charge pumps and voltage multipliers in order to generate the relatively high voltages that are respectively needed during programming and erasing phases. Even assuming to be able to overcome compatibility problems through an adequate complication of the fabrication process (e.g. by recourse to numerous additional masking steps) and duplication or multiplication where necessary of the circuitry needed for generating the different voltages that are necessary during write, read and erase phases of the two different memory arrays, the yield of such a complicated process and therefore the cost of the devices would be discouraging with the present technology. Alternative solutions that offer a pseudo EEPROM performance, though substantially realizing a FLASH-EPROM memory, by exploiting software methods based on momentarily shifting the data on a different support, their correction and rewriting in the previously erased FLASH-EPROM memory array, are also burdensome in terms of the time that is required to the system's microprocessor. US Patent No. 5,033,023 describes a high density EEPROM employing staked gate cells having the ability of being erased and programmed by byte, by employing select lines and a pass-gate transistor for selectively biasing the common source of the cells belonging to a selected byte of a row of matrix cells. EP-A-0 405 140 discloses a byte or block erasable array of EEPROM cells wherein cells may be erased singularly for implementing an erasing (and reprogramming) by single byte of the information stored in the memory. US patent No. 5,077,691 discloses a FLASH-EEPROM cell array wherein erasure is performed by applying a, negative voltage to the control gate of a row or of a plurality of rows of cells selected for erasing them, the source of which is biased at a comparatively reduced positive voltage with respect to the substrate potential that is normally grounded. Limiting source/substrate voltage during erasing alleviates the risk of breakdowns and of entrapments of charges at the source/substrate interface and related undesired effects. US Patent No. 4,949,309 describes an EEPROM using single transistor cells with byte erase and flash or total erase capabilities. Therefore there is a clear need and/or utility of being able to realize on a same chip an EEPROM type memory block in. a totally compatible manner with a FLASH-EPROM memory, through a standard single supply FLASH-EPROM fabrication process, without any modification thereof. Also in case of stand alone EEPROM type (i.e. erasable by bytes) memory devices, that is not necessarily integrated on the same chip together with a FLASH-EPROM memory, the possibility of realizing them by a standard FLASH-EPROM fabrication process, may in many cases represent a great advantage in terms of standardization of fabrication processes and production economy for families of devices or for complementary devices. This important objective is fully met by the present invention which is defined by the annexed claims and which offers also other important advantages. Fundamentally, the invention provides a way to realize a byte erasable (EEPROM) memory array that employs an array of FLASH-EPROM cells organized in rows and columns and individually addressable (during a programming and a reading phase) through a plurality of wordlines and bitlines, according to a normal architecture of nonvolatile memories. Therefore the mechanism of programming (writing) the cells remains that of a normal FLASH-EPROM cell, that is injection of hot electrons from the channel region into the floating gate of the cell that takes place in, a zone close to the drain diffusion, while in an erasing phase the mechanism used is the Fowler-Nordheim tunnelling mechanism, that takes place in an overlap zone of the floating gate on the source region of the cell. Byte erasability of the memory array is provided by realizing an auxiliary byte selection structure that comprises a byte selection transistor, to a first current terminal of which are connected in common the sources of the cells of a row of the matrix that compose a certain byte, and which has its other current terminal connected to a respective line of a plurality of source biasing lines that are individually selectable by the control circuitry of the memory array. The select transistors of the bytes arranged along the same row of the array have their gate driven in common through a respective line of a number of select lines identical to the number of wordlines of the memory array. Erasing of a certain byte takes place by biasing, through the byte select transistor connected in series with the sources of the memory cells of the selected byte to be erased, the sources of the cells and the relative wordline (control gate of all the cells of the row containing the byte selected for erasing) with a voltage sufficient to generate a Fowler-Nordheim (FN) tunnelling current of electrons from the floating gate of the cells to their respective source region, while fractioning the applied voltage. In practice, to the particular wordline is applied a negative voltage having a value insufficient to cause soft-erasing disturbances on the other unselected memory cells of the same wordline, while a positive , "complementary", voltage is applied to the sources, through the byte, select transistor, that is a positive voltage whose value if related to the tunnelling voltage, is reduced by the absolute value of the negative voltage that is applied to the control gate (multiplied by the capacitive ratio of the floating gate cell structure). During an erasing phase, the drains of the cells may be kept at ground potential or be left floating. According to the parameters of a typical fabrication process of a FLASH memory device, the voltage applied to a wordline during an erasing phase may be of about -5V while the voltage applied to the sources of the cells of the byte to be erased may be comprised between about 8V and 9V. In this way, a voltage difference of about 12V-13V is realized while reducing the electrical stress on the other cells of the wordline down to a level that has been found tolerable for the entire period necessary to sequentially erase all the bytes of a wordline. A voltage of about 3V may concurrently by applied to all the other (unselected) wordlines. Viceversa, programming of the cells may take place by applying the same voltages as in a normal FLASH-EPROM memory. Normally, a positive voltage of about 12V is applied to the wordline (control gate) while to the drain of the cells to be programmed a positive voltage comprised between 5V and 6V may be applied through the relative bitlines of the memory matrix. The common source of the cells of the byte selected for programming is grounded through the byte select transistor, while the sources of all the other cells of the same wordline may advantageously be biased, through their respective byte select transistors, at a positive voltage of an intermediate value, for example of about 3V, to help inhibit soft programming disturbances on unselected cells of the same wordline. In practice, in case of FLASH-EPROM devices, the byte erasable memory block (that is having an EEPROM type functionality) may employ the same charge pump or voltage muliplier circuits that are required for the operation of the FLASH-EPROM memory and that therefore are already present in the chip. The only additional requirement is the integration of a charge pump for generating a negative voltage comprised between about -5V and -8V, in order to "split" the voltage difference that must be imposed between the control gate and the source of the cells selected for erasing, according to the above described manner. On the other hand, this additional negative voltage pump has substantially negligeable power requisites, being destined to bias a control gate (wordline). Of course, also the charge pump used for generating the positive voltage for biasing the control gates (wordlines) during programming, which may be of about 12V, is also an essentially low absorption charge pump, while. the charge pump for generating the positive voltage of about 5V-6V to be applied to the bitlines of the selected cells for programming, in case of a single supply device designed for operation with relatively low supply voltage (for example about 3V in the case of battery operable systems) must be designed so as to satisfy the required power requirements. In fact, in this case, the biasing of the drain of a selected cell for programming to a level sufficient to accelerate the channel charge carriers up to sufficiently high kinetic levels (i.e. production. of channel hot electrons), produces a current through the cell's channel of a nonnegligeable value. In case of single supply (for example a 5±10%V or a 3.3±10%V device), such a power requisite may be satisfied directly from the supply. During a programming phase of the cells, considerations tied to the voltage drops along the current path may impose to limit the programming to few bits at the time, for example to only two bits at the time. In fact, the resistance of the programming current path, for example to the "farthest" cell of an octet of cells constituting a selected byte for programming, may have 'reached one to several hundreds ohms and the voltage drop, in consideration of the relatively high current (in the vicinity of about 100-500µA per cell), could become excessive if all the cells of the byte are written in parallel. Nevertheless the EEPROM memory block may offer an "ERASE ALL" function, in a completely compatible way. The increased power needed for implementing an erase all function of the EEPROM memory block may be provided by exploiting either the supply or the high power. charge pump circuit destined to generate the voltage of about 5V-6V necessary for biasing the drain during the writing of the cells for biasing through the respective byte select transistors the sources and incrementing the absolute value of the negative voltage for biasing the wordlines from the value of about -5V used for byte erasing to a value of about -8V, thus ensuring also during an ERASE ALL phase a voltage difference of about 12V between the source and the control gate of the memory cells. The use of a byte select transistor functionally connected in series with the source of the memory cells (instead of being connected in series with their drain) produces also the important result of ensuring a perfect uniformity of the threshold of the erased cells by preventing them from assuming a negative threshold because of the reaching by any. of them of a depleted state during an erasing phase. This greatly simplfies the erasing process by reducing the burden of supervision of the microprocessor and makes the management of the memory block substantially similar to that of a matrix of EEPROM cells. Another important aspect of the architecture of the EEPROM block of the invention resides on the fact that each select line to which the gates of all the byte select transistors of the bytes arranged along the same row of FLASH-EPROM memory cells are connected, is always selected together with the respective wordline of the row of memory cells, during any phase of operation of the memory block. This eliminates the need of implementing an additional logic decoder for selecting the select lines (i.e. the byte select transistors) by being able to employ for this purpose the same logic decoder of the wordlines. Of course, to the wordline and to the respective select line that may be logically selected by a single decoder, different voltages will be applied during the various phases of operation of the memory. The different aspects and advantages of the invention will become even more clear through the following description of several important embodiments and by reference to the annexed drawings, wherein: Figures 1 and 2 show the cross section of a single cell and the electrical scheme of an EEPROM memory array of a known type, respectively, as already described above; Figure 3 is a circuit diagram of an EEPROM memory block, organized in bytes each of 8 bits, according to the present invention; Figure 4 is a schematic cross section of a single memory cell; Figure 5 schematically shows the layout of a memory block of the invention according to an embodiment thereof. The architecture of an EEPROM memory block of the invention, employing a matrix of FLASH-EPROM cells, is depicted in Fig. 3. The portion of the array of Fig. 3 shows four bytes, each of a 8 bits, for a matrix that. may have relatively large dimensions. Four wordlines (WL) and eight bitlines (BL0 ... BL7) of the four bytes shown are identified in the circuit diagram. The entire array would be an expansion in the two "orthogonal" directions of wordlines and of bitlines, respectively, of the portion depicted in Fig. 3. It is also understood that the particular unit of information (byte) that is individually erasable (and programmable), may also be composed by a lesser or a larger number of bits and be referred to as for instance a "word" etc.. In the present context, the expression "byte" is not to be taken as identifying a unit of information necessarily of eight bits. On the contrary, it may also be composed of a number of bits equal or smaller than eight. The single FLASH-EPROM memory cells are identified by the relative graphical symbol of a transistor having a double gate. the drains of the cells arranged along each column of the matrix are connected by pairs of adjacents cells to a respective bitline, through drain contacts. The wordlines WL constitute the control gates of cells arragend along the same row of the matrix. The sources of all the eight cells of a row that form a byte are connected in common and to a first current terminal of a byte select transistor (Tb1, Tb2, Tb3 and Tb4). Contrary to a common FLASH-EPROM memory architecture wherein the source node, typically common to all the cells of the matrix, may be constituted by a single source diffusion having no solution of continuity along the parallel lines relative to the rows of cells of the matrix; in the case of the EEPROM block of the invention, the source diffusions are in the forms of segments, each "segment" pertaining to the cells belonging to a certain byte, along a certain wordline (row) of the matrix. Preferably though not necessarily, in a geometric middle position of the row-wise length of a particular source diffusion pertaining to a relative byte, a byte select transistor is formed, through which the source common to the (eight) cells of the byte may be biased at a certain voltage, during the different phases of operation of the memory. A first current terminal of each byte select transistor (Tb1 ... Tb4) is connected to the source diffusion of the cells of the respective byte while the other current terminal is connected, through a contact, to a source biasing line Vs. To the same source biasing line Vs may be connected the relative current terminals of all the byte select transistors (Tb1, Tb2, Tb3, Tb4 ...) pertaining to all the bytes that are arranged along a column-wise direction of the memory array. Of course, the source biasing lines Vs are individually selectable by a suitable decoder, made according to common techniques. As shown, the connection of the byte select transistors to a respective source biasing line Vs may be realized through a single source contact (C2) for every two adjacent bytes along a column-wise direction. The resistance of the conductive path through the cell of a selected bit may be reduced and differences among the paths of the various cells that compose a certain byte may be minimized by realizing the byte select transistor at a middle position in relation to the number of cells that form the byte and realizing the byte select transistor with an incremented size (width) as compared with the width of the floating gate cells. Preferably, the byte select transistor has a width that is a multiple of the width of the cells by a factor equivalent to the number of bits of the bytes. In the depicted examples, the byte select transistors Tb1 ... Tb4, should be made. about eight times larger than the memory cells. As a consequence, during a programming-by-bits phase the sequential selection of the bits to be programmed will be implemented in an optimal way by selecting two bits at a time, one from one side (on the left side according to the diagram of Fig. 3) and the other on the other side (on the right side according to the scheme of Fig. 3) of each source contact (i.e. of the node of connection of the byte select transistor to the respective biasing line Vs). In this way, also during a , write (programming) phase, the. resistance of the current path through the single cells of the same byte will be minimum. The cross section of each memory cell coupled with a byte select transistors in series with its source is schematically depicted in Fig. 4. The source biasing voltage Vs is applied through a source contact to a drain (n + ) region of the byte select transistor, whose gate Vsg may be constituted by the relative select line SEL, or be connected thereto. The byte select transistor constitutes the select switch for the respective byte, thus allowing to bias the source region (n + ) of the FLASH-EPROM memory cells, the drain region of which may be biased at a drain voltage Vd through a respective contact. The control gate Vcg of the memory cell may be constituted by the relative wordline itself WL or be connected thereto. According to a common fabrication process of FLASH-EPROM memory arrays with self-aligned source diffusion, a schematic layout of the portion of the memory array depicted in Fig. 3 is shown in Fig. 5. The accompanying list of the various symbols used in the illustration facilitates the reading of the layout scheme. In the following table are indicatively shown for purely illustrative purposes, the biasing voltages used in programming and in erasing the EEPROM memory block of the invention. operation node selected byte other bytes on selected word line other bytes on selected bit lines any other byte program select gate (Vsg) 12V 12V GND GND control gate (Vcg) 12V 12V 3V 3V source (Vs) GND 3V OPEN OPEN drain (Vd) 5V OPEN (3V) 5V OPEN (3V) erase select gate (Vsg) 12V 12V GND GND control gate (Vcg) -5V -5V GND GND source (Vs) 8-9V GND OPEN OPEN drain (Vd) OPEN OPEN OPEN OPEN Of course, the voltage levels indicated in the above table refer to a sample embodiment and may be varied in function of the thicknesses of dielectrics used and of the cell's size. During a programming phase, the drain of the cells of the deselected bytes of the same wordline and of the bytes corresponding to deselected bitlines may not be forced to any externally applied voltage. In case of deselected cells of the selected wordline and of the other deselected cells of the matrix, the drain will assume the fractionary voltage (3V) that is applied to the source in view of the fact that the cells are conductive. The invention meets the main objective of allowing realization in a fully compatible way on the same chip of a memory block having an EEPROM type functionality together with a FLASH-EPROM memory, without altering in any way the fabrication process and susbtantially without duplicating many of the control circuits of a FLASH-EPROM memory in. order to satisfy different requisites of an EEPROM memory block. In reaching these important results, the architecture of the invention produces other important advantages 'as. the elimination of problems relative to the threshold dispersion of erased FLASH-EPROM cells of the EEPROM memory block in connection with the relatively frequent erasing processes that the cells are subject to, beside ensuring an "ERASE ALL" function, without requiring realization of distinct charge pump circuits for satisfying the different requisites of bias voltages and current absorption. According to a preliminary estimate based on a layout as the one depicted in Fig. 5, the equivalent cell size for a byte erasable memory block that can be fabricated in a completely compatible manner on the same chip containing a FLASH-EPROM memory for single supply, overall would be equal to about three times the size for a FLASH-EPROM memory of identical storage capacity. In other terms, a byte erasable memory block (having an EEPROM type functionality) with a capacity of 128Kbyte, compatibly realized with a FLASH-EPROM process with a line width of 0.6µm, would require an integration area of 30mm 2 . The block may be procured at the single supply voltage of the FLASH-EPROM device which commonly is of about 5V(±10%), though in future applications the supply voltage is contemplated to be in the vicinity of about 3.3V(±10%). The typical programming time would be of about 5µsec/bit, while the typical erasing time would be of about 5msec/byte. Reliability may be estimated in over 100K erasing/programming cycles.

Claims: A single supply voltage byte erasable EEPROM block comprising an array of FLASH-EPROM memory cells organized in an integer number n greater than one of byte, each composed of an integer number m greater than one of bits individually selectable through a plurality of wordlines (WL) and of bitlines (BL) , compatibly integrated with a FLASH-EPROM fabrication process in a device containing a single supply voltage FLASH-EPROM, comprising an auxiliary selection structure composed of said integer number n of byte select transistors (Tb) , a plurality of individually selectable source biasing lines (Vs) , a plurality of select lines (SEL) in a number identical to the number of said wordlines (WL) , each byte select transistor (Tbi) having a first current terminal connected to a respective source biasing line (Vs) , a second current terminal connected to the sources connected in common of the memory cells that compose a respective byte and a gate connected to a respective, individually selectable select line (SEL) , a wordline (WL) and associated select line (SEL) of said matrix of memory cells being selected in pairs by a single logic decoder, means for biasing, during a programming phase, a selected bitline (BL) of the selected byte at a drain biasing voltage (5V) while biasing a selected wordline (WL) and associated select line ( SEL ) of said matrix at a first positive voltage (12V) , the sources of the memory cells of the selected byte at ground potential (GND) through a respective byte select transistor (Tb) , the other wordlines (WL) at a second positive voltage (3V) of a fractionary value of said first voltage (12V) , the other select lines (SEL) to ground potential (GND) , and the sources of the cells of the other bytes of said wordline at said second positive voltage (3V) of fractionary value and during a byte erasing phase, the other wordlines (WL) at ground potential (GND) , said associated select line at said first positive voltage (12V) and the other select lines and the sources of the cells of the deselected bytes of said wordline to ground potential (GND) , the sources of the cells of the selected byte at a third positive voltage (8-9V) through said respective byte select transistor (T b ) characterized in that during said byte erasing phase the selected wordline (WL) is biased at a negative voltage (-5V) having an absolute value lower than the absolute value of said first positive voltage (12V) and said third positive voltage (8-9V) has an intermediate value between said first positive voltage (12V) and said second fractionary value voltage (3V) . An EEPROM block as defined in claim 1, wherein during an erase-all phase of operation of the EEPROM block, said means bias the source of all cells at said drain biasing voltage used during a programming phase, said drain biasing voltage being provided by a respective voltage multiplier capable of delivering a certain current through all the cells of the bitlines that are selected during a programming phase, and said means bias the wordlines of the memory at a negative voltage of an absolute value sufficient to provide for a given potential difference between the source and a control gate of each single cell. An EEPROM block as defined in claim 1, wherein said byte select transistors have a width that is at least an integer number p greater than one times greater than the width of said FLASH-EPROM cells. An EEPROM block as defined in claim 4, wherein each of said byte select transistors is formed mid way along the length of a common source diffusion of the memory cells that compose the respective byte. An EEPROM block as defined in claim 5, wherein a single contact connects a current terminal of two byte select transistors of two column-wise adjacent bytes of said matrix to a respective source biasing line.

Inventors: CAPPELLETTI PAOLO, CASAGRANDE GIULIO, CAPPELLETTI, PAOLO, CASAGRANDE, GIULIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G11C16
IPC codes: G11C17, G11C16, H01L27, H01L29, H01L21