Voltage booster circuit

Abstract: A booster circuit which can cancel the back bias effect, can prevent the increase of the surface area of the circuit and the power consumption, prevent the complication of the clock generation circuit, and prevent lowering of the current capability, wherein a boosting stage is constituted by forming an nMOS transistor NT for carrying the charges and nMOS transistor NTB for transferring the voltage inside a p-well formed inside an n-well which is formed on a p-type semiconductor substrate and biased to a predetermined potential, constituted so that the source voltage of the nMOS transistor NT for carrying the charges which rise at the boosting is transferred via the nMOS transistor NTB for transferring the voltage to the substrate, that is, the p-well, whereby the back bias effect is suppressed.

Description: BACKGROUND OF THE INVENTION 1. Field of the invention The present invention relates to a booster circuit used for a semiconductor memory device etc. 2. Description of the Related Art A semiconductor memory device, for example, a flash memory, is provided with a voltage booster circuit which boosts the reference power source voltage, for example, 5V, to a high voltage of 12 to 20V and a negative high voltage of -6V to -20V and supplies the resultant voltage to a predetermined functional block. Figure 1 is a circuit diagram showing a general voltage booster circuit of a positive voltage for obtaining an output of 20V by boosting a power source voltage of for example +5V. In Fig. 1, V cc denotes a power source voltage; 1 denotes a voltage feeding line of the power source voltage; NT 0 to NT 4 (5 to 9) denote n-channel MOS (metal oxide semiconductor) transistors (hereinafter, referred to as nMOS transistors); C 1 to C 4 (17 to 20) denote capacitors for pumping; ND 0 to ND 4 (11 to 15) denote nodes; T OUT (21) denotes an output terminal; V OUT denotes an output signal; and  1 (2) and  1- (3) denote clock signals of mutually complementary levels; respectively. The nMOS transistors NT 0 to NT 4 (5 to 9) are connected in a form of cascade, the drain of the nMOS transistor NT 0 (5) is connected to the line 1 of the power source voltage V CC , and the source of the nMOS transistor NT 4 (9) is connected to the output terminal T OUT (21). The node ND 0 (11) is constituted by a point of connection between the line 1 of the power source voltage V CC and the nMOS transistor NT 0 (5); the node ND 1 (12) is constituted by the point of connection between the source of the nMOS transistor NT 0 (5) and the drain of the nMOS transistor NT 1 (6); the node ND 2 (13) is constituted by the point of connection between the source of the nMOS transistor NT 1 (6) and the drain of the nMOS transistor NT 2 (7); the node ND 3 (14) is constituted by the point of connection between the source of the nMOS transistor NT 2 (7) and the drain of the nMOS transistor NT 3 (8); and the node ND 4 (15) is constituted by the point of connection between the source of the nMOS transistor NT 3 (8) and the drain of the nMOS transistor NT 4 (9); respectively. The nMOS transistors NT 0 to NT 4 (5 to 9) are "diode-connected", with the drains and gates being connected. Namely, the node ND 0 (11) and the gate of the nMOS transistor NT 0 (5) are connected; the node ND 1 (12) and the gate of the nMOS transistor NT 1 (6) are connected; the node ND 2 (13) and the gate of the nMOS transistor NT 2 (7) are connected; the node ND 3 (14) and the gate of the nMOS transistor NT 3 (8) are connected; and the node ND 4 (15) and the gate of the nMOS transistor NT 4 (9) are connected. The nodes ND 1 to ND 4 (12 to 15) are connected to the pumping capacitors C 1 to C 4 (17 to 20), respectively; the capacitors C 1 (17) and C 3 (19) are connected to an input line of the clock signal  1 (2); and the capacitors C 2 (18) and C 4 (20) are connected to the input line of the clock signal  1- (3). The clock signals  1 (2) and  1- (3) are complementary signals which alternately take the power source voltage V CC level and "0" V level in a predetermined cycle. Accordingly, when the clock signal  1 is at the V CC level, the nodes ND 1 (12) and ND 3 (14) are boosted (raised up) by the amount of for example the voltage V c by the capacitance connection of the capacitors C 1 (17) and C 3 (19). At this time, since the clock signal  1- (3) is at "0" V, the nodes ND 2 (12) and ND 4 (15) are pulled down (lowered in level). On the other hand, when the clock signal  1 (2) is at "0" level, the nodes ND 1 (12) and ND 3 (13) are lowered in level. At this time, since the clock signal  1- (3) is at the V CC level, the nodes ND 2 (13) and ND 4 (15) are raised up by the amount of the voltage V C by the capacitance connection of the capacitors C 2 (18) and C 4 (20). Figure 3 is a waveform diagram showing the process of boosting of the nodes ND 1 (12) and ND 2 (13) in the positive booster circuit of Fig. 1. As shown in Fig. 3, in the booster circuit of Fig. 1, by inputting the clock signals  1 (2) and  1- (3) taking complementary levels to the pumping capacitors C 1 to C 4 (17 to 20), a current is passed toward the output side, so that the charges of the capacitors C 1 to C 4 (17 to 20) are sequentially transported. More specifically, in the period a shown in the diagram, the clock signal  1 (2) is at the V CC level and input to the capacitor C 1 (17), and the clock signal  1- (3) is at the "0" V and input to the capacitor C 2 (18). Accordingly, the node ND 1 (12) is boosted (raised) by the amount of the voltage V C by the capacitance connection of the capacitor C 1 (17), while the node ND 2 (13) is lowered by the amount of the voltage V C . Along with the boosting of the node ND 1 (12), the voltage V C is applied to the nMOS transistor NT 1 (6), and therefore a current i 1 is passed toward the node ND 2 (13) of the next stage, and the charges of the capacitor C 1 (17) are transported to the node ND 2 (13). Along with this, the voltage V 2 of the node ND 2 (13) slightly rises at the point of time at which the period a is ended. In the next period b , the clock signal  1 (2) is input to the capacitor C 1 (17) at "0" V, and the clock signal  1- (3) is input to the capacitor C 2 (18) at the V CC level. Accordingly, the capacitance connection of the capacitor C 1 (17) is not carried at the node ND 1 (11). This is lowered by the amount of the voltage V C , and the node ND 2 (13) is raised by the amount of the voltage V C . Accordingly, the voltage V 2 at the node ND 2 (13) becomes the next value obtained by adding the amount of the rising voltage (+)α by the inflow of the current i 1 : V 2 = V C + α By this, the nMOS transistor NT 1 (6) becomes the OFF state and the current i 1 no longer flows, so that the charges are transported to the node ND 2 (12) of the next stage, which means that the voltage V 2 of the node ND 2 (12), that is, the source voltage of the nMOS transistor NT 1 (6), rises. Along with the boosting of the node ND 2 (13), the voltage (V C + α) is applied to the gate of the nMOS transistor NT 2 (7), and therefore the current i 2 flows toward the node ND 3 (14) of the next stage, and the charges of the capacitor C 2 (18) are transported to the node ND 2 (12). Along with this, the voltage of the node ND 3 (14) further rises at the point of time when the period b is ended. An operation similar to the above is repeated, and the predetermined high voltage output V OUT appears at the output terminal T OUT (21). Where the charges are transported to the node ND 2 (13) of the next stage via for example the nMOS transistor NT 1 (6) in this booster circuit, that is, when the current i 1 flows, the source voltage of the nMOS transistor NT 1 (6) = drain voltage of the nMOS transistor NT 1 (6) = gate voltage of the nMOS transistor NT 1 (6) = V 1 stands, and therefore it is necessary to satisfy the following relationship: V 1 - V 2 > V th Here, V th indicates the threshold voltage of the nMOS transistor. Accordingly, a condition with which the current i 1 flows and the charges are transported becomes as follows if the voltage at which the nodes ND 1 (12) and ND 2 (13) are raised/lowered by the capacitors C 1 (17) and C 2 (18) as mentioned above is V C : (V 1 + V C ) - (V 2 - V C ) > V th(1) Namely, 2V C - V th(1) > V 2 - V 1 A circuit of Fig. 1 satisfying this condition can sequentially shift the charges of the capacitors C 1 to C 4 (17 to 20) to the output terminal T OUT (21) through the node ND 1 (11) to the node ND 4 (15) using the complementary clock signals  1 (2) and  1- (3) and can boost the power source voltage V CC to the desired voltage. Figure 4 is a circuit diagram showing a negative booster circuit for obtaining a negative high voltage. The point of difference of this circuit from the positive booster circuit of Fig. 1 resides in a fact that pMOS transistors PT 0 to PT 4 (40 to 44) are used in place of the nMOS transistors NT 0 to NT 4 (5 to 9) and in that the node ND 10 (31) is grounded in place of the power source voltage V CC . In the case of this negative booster circuit, the current flows from the output side toward the ground, a charge shift is performed along with the input of the clock signals  2 (52) and  2- (53) to the capacitors C 11 to C 14 (47 to 50), and the negative voltage is gradually accumulated in the output terminal T OUT (36), so that the negative high voltage output V OUT is obtained. The threshold voltage V th of the MOS transistor is susceptible to the influence of a so-called back bias effect wherein the threshold voltage is increased when the source voltage rises. Here, when it is assumed that the threshold voltage V th when the substrate voltage = source voltage = 0V is "0.8V", the threshold voltage V th when the source voltage is 10 or so volts becomes about 2V. For this reason, there is a problem in that as the number of boosting stages is increased and the voltage becomes higher, so the efficiency per stage is degraded. In the above-mentioned equation (3), when it is assumed that there is no back bias effect and V C = 4V, the following stands: V 2 - V 1 < 8 - 0.8V = 7.2V but when the threshold voltage V th becomes equal to 2V by the back bias effect, the following stands: V 2 - V 1 < 8 - 2 = 6V When it is assumed that the operation must be performed even at 2.5V so as to guarantee the operation of the power source voltage 3.0V, if V C = 2V, the following comes to stand: V 2 - V 1 < 4 - 2 = 2V Conventionally, so as to avoid the influence by this back bias effect, a countermeasure in which the threshold voltage V th of the transistors of a part of a higher level of the stages, for example, nMOS transistors NT 3 (8) and NT 4 (9) of Fig. 1, is lowered and brought to 0V has been carried out. By taking this countermeasure, however, there is a problem in that the manufacturing process becomes cumbersome etc. Moreover, there has also been proposed a voltage booster circuit constituted so that the gate voltage is raised by the amount of increase of the threshold voltage V th by the back bias effect as shown in Fig. 11 and Fig. 13 of the document entitled the IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 11, 1992, pp 1540 to 1546. Figure 5 is a circuit diagram showing the positive booster circuit disclosed in Fig. 13 of this document. This circuit is constituted in that, in addition to the circuit of Fig. 1, the capacitors CG 1 to CG 4 (87 to 90) for boosting the gates are connected to the gates of the respective nMOS transistors NT 20 to NT 23 (12 to 75); the nMOS transistors NTG 0 to NTG 3 (61 to 64) are inserted and connected between the respective nodes ND 20 to ND 23 (66 to 69) and the gates of the nMOS transistors NT 20 to NT 23 (72 to 75); and the gates of the respective nMOS transistors NTG 0 to NTG 3 (61 to 64) are connected to the nodes ND 21 to ND 24 (67 to 70) of the one later stage. So as to actuate this circuit, four phase clock signals  5 to  8 set up at the timing as shown in Fig. 6 are input to the respective capacitors C 21 to C 24 (93 to 96) and CG 1 to CG 4 (87 to 90) at a predetermined timing. Specifically, the clock signal  7 is input to the node pumping capacitors C 5 and C 7 , the clock signal  5 is input to the capacitors C 21 (93) and C 24 (96), respectively, the clock signal  6 is input to the gate pumping capacitors CG 1 (87) and CG 3 (89), and the clock signal  8 is input to the capacitors CG 2 (89) and CG 4 (90), respectively. Here, for simplification, a case where for example the clock signal  5 is input to the capacitor C 22 (94) at the V CC level and the clock signal  7 is input to the capacitor C 23 (95) at "0" V is assumed. In this case, the node ND 22 (68) is in the boosting state, and the node ND 23 (69) is in the lowered state. Accordingly, the gate voltage of the nMOS transistor NTG 2 (63) is at the same level as the level of the node ND 23 (69), and therefore the nMOS transistor NTG 2 (63) is retained in the OFF state. In this state, when the clock signal  6 becomes the V CC level, by the capacitance connection of the capacitor CG 3 (89), the gate voltage of the nMOS transistor NT 22 (74) is raised to a level that can cancel the back bias effect. For this reason, the charges of the capacitor C 22 (94) are transferred well to the node ND 23 (69) via the nMOS transistor NT 22 (68). Next, when the clock signal  5 is switched to "0" V and the clock signal  8 is switched to the V CC level, the node ND 22 is lowered, and the node ND 23 is boosted. At this time, the clock signal  6 is switched to "0" V. Since the node ND 23 (69) is in the boosting state, also the gate voltage of the nMOS transistor NTG 2 (63) becomes the high level, and the nMOS transistor NTG 2 (63) becomes the ON state. By this, the node ND 22 (68) and the node NG 2 (83) on the gate side of the nMOS transistor NT 22 (74) become the same potential, and therefore a current is not passed from the node ND 23 (69) to the node ND 22 (68). However, the circuit of Fig. 5 has the following problem. Namely, since a voltage higher than the output voltage is applied on the gate of the nMOS transistor, it is necessary to increase the gate voltage resistance by that amount in consideration of the transition state etc. Accordingly, processing for making the gate oxide film thicker is necessary. Also, since four phase clock signals  5 to  8 are used, the clock generation circuit becomes complex, and since the gate pumping capacitors CG 1 to CG 4 (87 to 90) are necessary, an increase of the surface area of the circuit and power consumption is induced. Since the ratio between the pumping capacitors of the respective nodes and the parasitic capacitance becomes bad, operation with low voltage source is difficult. Namely, the maximum voltage for boosting the gate is the power source voltage times the above-described capacitance ratio, and therefore 2.0V is the limit even if the capacitance ratio is brought to 80% where the power source voltage is 2.5V, and thus it is not possible to cancel the amount of increase of the threshold voltage V Th by the back bias effect. Also, it is a so-called non-overlap type four phase pulse, and therefore it is not possible to raise the frequency that high, which consequently lowers the current capability. SUMMARY OF THE INVENTION The present invention was made in consideration with such a circumstance and has as an object thereof to provide a booster circuit with which the back bias effect can be cancelled and the prevention of increase of the surface area of the circuit and power consumption, the prevention of complication of the clock generation circuit, and the prevention of the lowering of the current capability can be achieved. To solve this object the present invention provides a booster circuit as specified in any one of claims 1 to 4. A preferred embodiment of the invention is described in claim 5. Prior art document EP-A-O 485 016 discloses an integrated charge pump circuit comprising one or more diode type voltage multiplier stages, with each stage having a diode-connected NMOS transistor. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. According to an embodiment of the present invention, the above-described first conductivity type is set to an n-type and the above-described second conductivity type is set to a p-type. According to the present invention, when for example the first node is boosted by the boosting element, and the second node is raised up, along with the boosting of the first node, a high voltage is applied to the gate of the first transistor, and therefore the first transistor becomes the ON state, so that the current is passed from the first node toward the second node, and the charges of for example the boosting element are transported to the second node. Along with this, the voltage of the second node gradually rises. At this time, a high voltage of the boosted first node is applied to the gate of the second transistor, and therefore the second transistor becomes the ON state. As a result, the voltage of the second node and the voltage of the substrate well become the same level. Here, when the first node is lowered and the second node is raised, the voltage of the second node becomes a value obtained by adding the amount of the voltage plus a certain margin raised by the inflow of the current to the voltage boosted by the boosting element. By this, the first transistor and the second transistor become the OFF state since the gate voltage is lowered, and the current no longer flows. Also, the voltage on the connection end side with the substrate well of the second transistor becomes the differential voltage between the gate voltage of the second transistor, that is, the first node voltage, and the threshold voltage V th . The voltage on the connection end side of the second transistor at this time and the voltage of the substrate well are equal, and therefore the threshold voltage V th of the first transistor is not susceptible much at all to the influence of the back bias effect. According to the present invention, even in a construction in which the first node and the substrate well are operationally connected by the second transistor, and the second node is connected to the gate of the second transistor, the influence of the back bias effect is avoided. BRIEF DESCRIPTION OF THE DRAWINGS The above objects and features and other objects and features of the present invention will be apparent from the description with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing one example of the conventional positive booster circuit; Fig. 2 is a view indicating an example of a waveform of the clock signal; Fig. 3 is a waveform diagram for explaining the operation of the booster circuit of Fig. 2; Fig. 4 is a circuit diagram showing one example of the conventional negative booster circuit; Fig. 5 is a circuit diagram showing another example of the conventional positive booster circuit; Fig. 6 is a view indicating the example of the waveform of the four phase clock signal used in the booster circuit of Fig. 5; Fig. 7 is a circuit view indicating a first embodiment of a booster circuit according to the present invention; Figs. 8A and 8B are views for explaining a well-in-well construction according to the present invention, in which Fig. 8A is a schematic cross-sectional view and Fig. 8B is a view indicating the structure of Fig. 8A using circuit symbols; Fig. 9 is a schematic cross-sectional view showing one example of constituting the principal part of the circuit of Fig. 7 by adopting the well-in-well construction; Fig. 10 is a view for explaining the basic operation of the booster circuit according to the present invention; Fig. 11 is a circuit diagram showing a second embodiment of the booster circuit (positive booster circuit) according to the present invention; Fig. 12 is a circuit diagram showing a third embodiment of the booster circuit (negative booster circuit) according to the present invention; Fig. 13 is a circuit diagram showing a fourth embodiment of the booster circuit (negative booster circuit) according to the present invention; Fig. 14 is a circuit diagram showing a fifth embodiment of the booster circuit (positive booster circuit) according to the present invention; and Fig. 15 is a view indicating the simulation results of the first circuit (product of the present invention) and the conventional circuits. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 7 is a circuit diagram showing a first embodiment of a booster circuit according to the present invention. NT 0W to NT 4W (125 to 129) denote the nMOS transistors for carrying the charges; NTB 0W to NTB 4W (105 to 109) denote the nMOS transistors for transferring the voltage; ND 30 to ND 35 (117 to 122) denote nodes; C 31 to C 34 (111 to 114) denote capacitors for pumping the nodes; V CC denotes the power source voltage; T OUT (122) denotes the output terminal; V OUT denotes the output voltage; and  10 and  10- denote the clock signals taking the mutually complementary levels; respectively. The nMOS transistors NT 0W to NT 4W (125 to 129) and NTB 0W to NTB 4W (105 to 109) used in the present circuit are formed inside the same p-well having a so-called well-in-well (double well) construction. Here, an explanation will be made of a fundamental structure of the well-in-well construction. Figure 8 diagrammatically shows the fundamental structure of the well-in-well construction adopted in the present embodiment, in which Fig. 8A of the figure is a schematic cross-sectional view; and Fig. 8B of the figure is a view expressing the nMOS transistor adopting the well-in-well construction using the circuit symbols. In Fig. 8A, 131 denotes a p-type semiconductor substrate; 132 denotes an n-well; 133 denotes a p-well; 134 to 136 denote n + diffusion layers; 137 denotes a p + diffusion layer; and 138 denotes a gate electrode; respectively. In the present structure, an n-well 132 which is the substrate side diffusion layer is formed on the surface of the semiconductor substrate 131 constituted by a grounded single crystal silicon substrate, etc., and the n + diffusion layer 134 is formed on the surface of the n-well 132. Further, in the present structure, the p-well 133 is formed inside the n-well 132. On the surface inside the p-well 133, n + diffusion layers 135 and 136 which are the element side diffusion layers and the p + diffusion layer 137 for the takeout electrode are formed. Then, the nMOS transistor is constituted by the n + diffusion layers 135 and 136 and the gate electrode 138. For example, the n + diffusion layer 135 functions as the drain and the n + diffusion layer 136 functions as the source. Figure 8B shows the nMOS transistor adopting such a well-in-well construction as mentioned above using the circuit symbols and shows the same using the same symbols as those in Fig. 7. In the circuit of Fig. 7, the nMOS transistors NT 0W (125) and NTB 0W (105), NT 1W (126) and NTB 1W (106), NT 2W (127) and NTB 2W (107), NT 3W (128) and NTB 3W (108), and NT 4W (129) and NTB 4W (109) are formed inside the same p-well 133, respectively. Figure 9 diagrammatically shows this construction. In the circuit of Fig. 7, for example as shown in Fig. 9, the nMOS transistor NT for carrying charges and the nMOS transistor NTB for transferring the voltage are constituted in such a manner that three n + diffusion layers 155, 156a, and 156b and one p + diffusion layer 157 are formed inside one p-well 153, the gate electrodes 158a and 158b are formed on a space between the n + diffusion layer 155 and 156a and on the space between the n + diffusion layers 156a and 156b, and the n + diffusion layer 156b and p + diffusion layer 157 constituting the nMOS transistor NTB for transferring the voltage are connected, whereby one boosting stage is constituted. Five such p-wells 153 are formed inside the n-well 152 via the selective oxide element isolation region 159, and the n + diffusion layer 154 of the n-well 152 is connected to the terminal retained at a predetermined potential, for example, the output terminal T OUT , whereby a principal part excluding the pumping capacitor of the circuit of Fig. 7 is constituted. An explanation will be made below of the relationship of connection of the circuit of Fig. 7 using the nMOS transistor adopting the well-in-well construction as mentioned above. The nMOS transistors NT 0w to NT 4W (125 to 129) are connected in cascade, the drain of the nMOS transistor NT 0W (125) is connected to the line 100 of the power source voltage V CC , and the source of the nMOS transistor NT 4W (129) is connected to the output terminal T OUT . The node ND 30 (117) is constituted by a point of connection between the line 100 of the power source voltage V CC and the nMOS transistor NT 0W (125); the node ND 31 (118) is constituted by the point of connection between the source of the nMOS transistor NT 0w (125) and the drain of the nMOS transistor NT 1W (126); the node ND 32 (119) is constituted by the point of connection between the source of the nMOS transistor NT 1W (126) and the drain of the nMOS transistor NT 2W (127); the node ND 33 (120) is constituted by the point of connection between the source of the nMOS transistor NT 2W (127) and the drain of the nMOS transistor NT 3W (128); the node ND 34 (121) is constituted by the point of connection between the source of the nMOS transistor NT 3W (128) and the drain of the nMOS transistor NT 4W (129); and the node ND 35 is constituted by the point of connection between the source of the nMOS transistor NT 4W (129) and the output terminal T out ; respectively. Also, the respective nMOS transistors NT 0w to NT 4W (125 to 129) are "diode-connected" with the drain and gate connected. Namely, the node ND 30 (117) and the gate of the nMOS transistor NT 0w (125) are connected; the node ND 31 (118) and the gate of the nMOS transistor NT 1w (126) are connected; the node ND 32 (119) and the gate of the nMOS transistor NT 2w (127) are connected; the node ND 33 (120) and the gate of the nMOS transistor NT 3w (128) are connected; and the node ND 34 (121) and the gate of the nMOS transistor NT 4w (129) are connected. The nodes ND 31 to ND 34 (118 to 121) are connected to the pumping capacitors C 31 to C 34 (111 to 114), respectively; the capacitors C 31 (111) and C 33 (113) are connected to an input line 101 of the clock signal  10 ; and the capacitors C 32 (112) and C 34 (114) are connected to an input line 102 of the clock signal  10- . Further, at each boosting stage, the drain of the nMOS transistor NTB 0W (105) is connected to the node ND 31 (118), the gate is connected to the node ND 30 (117), and the source is connected to the substrate well of the nMOS transistor NT 0W (125), that is, the p-well 153 of Fig. 9, and connected to the p + diffusion layer 157. The drain of the nMOS transistor NTB 1W (106) is connected to the node ND 32 (119), the gate is connected to the node ND 31 (118), and the source is connected to the substrate well of the nMOS transistor NT 1W (126), that is, the p-well 153 of Fig. 9, and connected to the p + diffusion layer 157. The drain of the nMOS transistor NTB 2W (107) is connected to the node ND 33 (120), the gate is connected to the node ND 32 (119), and the source is connected to the substrate well of the nMOS transistor NT 2W (127), that is, the p-well 153 of Fig. 9, and connected to the p + diffusion layer 157. The drain of the nMOS transistor NTB 3W (128) is connected to the node ND 34 (121), the gate is connected to the node ND 33 (120), and the source is connected to the substrate well of the nMOS transistor NT 3W (128), that is, the p-well 153 of Fig. 9, and connected to the p + diffusion layer 157. The drain of the nMOS transistor NTB 4W (129) is connected to the node ND 35 (122), the gate is connected to the node ND 34 (121), and the source is connected to the substrate well of the nMOS transistor NT 4W (129), that is, the p-well 153 of Fig. 9, and connected to the p + diffusion layer 157. Also, the n + diffusion layer 154 in the n-well 152 of Fig. 9 is connected to the node ND 35 (122), and the n-well 152 is biased to a predetermined potential. As explained above, the constitution is made using an nMOS transistor NT for carrying the charges having the well-in-well construction and the nMOS transistor NTB for transferring the voltage at each boosting stage, whereby an influence by the back bias effect of the nMOS transistor NT for carrying the charges can be effectively cancelled. An explanation will be made below of the reason why the influence by the back bias effect can be cancelled using Fig. 10 showing the fundamental structure of one boosting stage. First, in Fig. 10, where the node ND D (171) is boosted and the node ND S (173) is lowered, the relationship between the voltage V D of the node ND D (171) and the voltage V S of the node ND S (173) becomes as follows: V D > V S This voltage V D of a high level is supplied to the gate of the nMOS transistor NTB for transferring the voltage, and therefore the nMOS transistor NTB becomes the ON state and the voltage V S of the node ND S (173) and the voltage V B of the node ND B (176) become the same level ( V S = V B ). Next, where the node ND D (171) is lowered and the node ND S (173) is boosted, the relationship between the voltage V D of the node ND D (171) and the voltage V S of the node ND S (173) becomes as follows: V D < V S Accordingly, the voltage V B of the node ND B (176) becomes the gate voltage of the nMOS transistor NTB (177), that is, the differential voltage between the voltage V D and the threshold voltage V th as indicated next. V B = V D - V th The voltage of the source of the nMOS transistor NTB (177) and the voltage of the substrate (p-well) at this time are equal, and therefore the threshold voltage V th of the nMOS transistor NT (172) is no longer susceptible much to the influence of the back bias effect. This is true even for a high boosting stage. When considering this referring to the circuit of Fig. 7, the present circuit adopts a structure in which the voltages V 1 to V 4 of the nodes ND 31 to ND 34 (118 to 121) are changed in synchronization with the clock signals  10 and  10- and fluctuate between for example V 1 > V 2 and V 1 < V 2 ; the nMOS transistors NTB 0W to NTB 4W (125 to 129) for transferring the voltage transfer the lower voltage; and (AND logics) between V 0 and V 1 , V 1 and V 2 , V 2 and V 3 , V 3 and V 4 and V 4 and V 5 are taken, in other words, the source voltage is determined by the lower voltage. An explanation will be made next of the operation by the above-described structure by taking as an example a case where the nodes ND 31 (118) and ND 32 (119) are complementarily boosted. For example, when the clock signal  10 (101) is input to the capacitor C 31 (111) at the V CC level, and the clock signal  10- is input to the capacitor C 32 (112) at "0" V, the node ND 31 (118) is boosted (raised) by the amount of the voltage V C by the capacitance connection of the capacitor C 31 (111), and the node ND 32 (119) is lowered by the amount of the voltage V C . Along with the boosting of the node ND 31 (118), the voltage V C is applied to the gate of the nMOS transistor NT 1w (126), and therefore the nMOS transistor NT 1w (126) becomes the ON state, the current i 2 flows toward the node ND 32 (119) of the next stage, and the charges of the capacitor C 31 (111) are transported to the node ND 32 (119). Along with this, the voltage V 2 of the node ND 32 (119) gradually rises. At this time, a high voltage V 1 of the boosted node ND 31 (118) is applied to the gate of the nMOS transistor NT 1W (126), and therefore the nMOS transistor NTB 1W (106) becomes the ON state. As a result, the voltage V 2 of the node ND 32 (119), that is, the voltage of the source of the nMOS transistor NT 1W (126), and the voltage of the substrate well (source voltage of the nMOS transistor NTB 1W (126) become the same level. Here, when the clock signal  10 (101) is input to the capacitor C 31 (111) at "0" V, and the clock signal  10- (102) is input to the capacitor C 32 (112) at the V CC level, the node ND 31 (118) is lowered by the amount of the voltage V C since the capacitance connection of capacitor C 31 (111) is not carried out, and the node ND 32 (119) is raised by the amount of the voltage V C . Accordingly, the voltage V 2 of the node ND 32 (119) becomes the value obtained by adding the amount of the voltage plus a certain margin which rose by the inflow of the current i 1 . On the other hand, the nMOS transistor NT 1W (126) and the nMOS transistor NTB 1W (106) become the OFF state since the gate voltage is lowered, and the current i 1 no longer flows. Accordingly, the source voltage of the nMOS transistor NTB 1W (106) becomes the differential voltage between the gate voltage of the nMOS transistor NTB 1W (106), that is, the voltage V 1 , and the threshold voltage V th , i.e., (V 1 - V th ). The voltages of the source of the nMOS transistor NTB and the substrate well at this time are equal, and therefore the threshold voltage V th of the nMOS transistor NT 1W (126) is not susceptible much to the influence of the back bias effect. An operation similar to the above is successively repeated, and the predetermined high voltage output V OUT appears at the output terminal T OUT . As explained above, according to the present first embodiment, each boosting stage is constituted by forming the nMOS transistor NT for carrying the charges and the nMOS transistor NTB for transferring the voltage inside the p-well formed inside the n-well which is formed on the p-type semiconductor substrate and biased to the predetermined potential, and constituted so that the source voltage of the nMOS transistor NT for carrying the charges rising at the boosting is transferred via the nMOS transistor NTB for transferring the voltage to the substrate, that is, the p-well, and therefore it is possible to suppress the back bias effect. Accordingly, a circuit which can perform boosting to a high voltage by a small number of stages can be realized. Also, the maximum value of the gate voltage can be made a low one of about the output voltage +0.8V, which is lower than the conventional output voltage +2 to 3V, and thus it is advantageous for the setting of the gate voltage resistance. Further, since a capacitor for pumping the gates is unnecessary, the increase of the surface area of the circuit and the power consumption can be prevented, and since it is sufficient if there are two phases of  and  - taking the complementary levels, there are advantages such that a circuit which is excellent in the current capability and has a wide operation range in the low voltage source direction can be realized. Figure 11 is a circuit diagram showing a second embodiment of the booster circuit according to the present invention. The point of difference between the present embodiment and the above-described first embodiment is that the drain is connected to the input side node and the gate is connected to the output side node in place of having the drains of the voltage transfer nMOS transistors NTB 10W to NTB 14W (190 to 194) connected to the node of the output side of the boosting stage, and the gate connected to the input side node. Namely, the drain of the nMOS transistor NTB 10W (190) is connected to the node ND 40 (197), and the gate is connected to the node ND 41 (198). The drain of the nMOS transistor NTB 11W (191) is connected to the node ND 41 (198), and the gate is connected to the node ND 42 (199); the drain of the nMOS transistor NTB 12W (192) is connected to the node ND 42 (199), and the gate is connected to the node ND 43 (200); the drain of the nMOS transistor NTB 13W (193) is connected to the node ND 43 (200), and the gate is connected to the node ND 44 (201); and the drain of the nMOS transistor NTB 14W (194) is connected to the node ND 44 (201), and the gate is connected to the node ND 45 (202). The rest of the structure is similar to that of the first embodiment, and an effect the same as the effect of the above-mentioned first embodiment can be obtained. Figure 12 is a circuit diagram showing a third embodiment of the booster circuit according to the present invention. The point of difference between the present embodiment and the above-described first embodiment is that, so as to constitute the negative booster circuit in place of the positive booster circuit, the gates of the respective charge carrying nMOS transistors NT 20W to NT 24W (235 to 239) are connected to the nodes on the source side in place of the nodes of drain side, the node ND 50 (226) is grounded in place of the connection to the positive power source voltage V CC , and further the n + diffusion layer 154 of the n-well having the well-in-well construction is grounded in place of connection to the node ND 55 (231). Namely, the gate of the nMOS transistor NT 20W (235) is connected to the node ND 51 (227); the gate of the nMOS transistor NT 21W (236) is connected to the node ND 52 (228); the gate of the nMOS transistor NT 22W (237) is connected to the node ND 53 (229); the gate of the nMOS transistor NT 23W (238) is connected to the node ND 54 (230); and the gate of the nMOS transistor NT 24W (239) is connected to the node ND 55 (231). In the present negative booster circuit also, in the same way as the above-mentioned first and second embodiments, the influence of the back bias effect can be effectively cancelled, and a negative high voltage of for example -20V can be obtained by a small number of stages. Figure 13 is a circuit diagram showing the third embodiment of the booster circuit according to the present invention. The point of difference between the present embodiment and the above-described second embodiment is that, so as to constitute the negative booster circuit in place of the positive booster circuit, the gates of the respective charge carrying nMOS transistors NT 30W to NT 34W (275 to 279) are connected to the nodes on the source side in place of the nodes of the drain side, the node ND 60 (266) is grounded in place of the connection to the positive power source voltage V CC , and further the n + diffusion layer 154 of the n-well having the well-in-well construction is grounded in place of connection to the node ND 65 (271). Namely, the gate of the nMOS transistor NT 30W (275) is connected to the node ND 61 (267); the gate of the nMOS transistor NT 31W (276) is connected to the node ND 62 (268); the gate of the nMOS transistor NT 32W (277) is connected to the node ND 63 (269); the gate of the nMOS transistor NT 33W (278) is connected to the node ND 64 (270); and the gate of the nMOS transistor NT 34W (279) is connected to the node ND 65 (271). In the present negative booster circuit also, in the same way as the above-mentioned second embodiment, the influence of the back bias effect can be effectively cancelled, and a negative high voltage of for example -20V can be obtained by a small number of stages. Figure 14 is a circuit diagram showing a fifth embodiment of the booster circuit according to the present invention. The point of difference between the present embodiment and the above-described first embodiment is that the nMOS transistors NTP 11 to NTP 14 (321 to 324) for precharging the respective nodes ND 71 to ND 74 (306 to 309) of the boosting stage are provided. The sources of the respective nMOS transistors NTP 11 to NTP 14 (321 to 324) are connected to the power source voltage V CC ; the drain of the nMOS transistor NTP 11 (321) is connected to the node ND 71 (306); the drain of the nMOS transistor NTP 22 (322) is connected to the node ND 72 (307); the drain of the nMOS transistor NTP 13 (323) is connected to the node ND 73 (308); the drain of the nMOS transistor NTP 14 (324) is connected to the node ND 74 (309); and the bases of the respective nMOS transistors NTP 11 to NTP 14 (321 to 324) are connected to the input line 301 of the control signal CTL. In this way, by providing the precharging nMOS transistors NTP 11 to NTP 14 (321 to 324), the following effects are obtained in addition to the effect of the first embodiment mentioned above. Namely, where there is no nMOS transistor for precharging, for example, the voltage of node ND 74 starts from 0V, but when the clock signal  14- is input to the capacitor C 74 (329) at 0V at this time, the node ND 74 (309) is lowered to the negative voltage. This can be prevented by providing the nMOS transistor NTP 14 (324) for precharging. Also, where the precharging is not carried out, the gate voltage of the capacitor C 74 (329), that is, the voltage V 4 of the node ND 74 (309), does not exceed the threshold voltage V th , and therefore there is a minus function such that all of the capacitance of the capacitor C 74 (329) is not seen as the capacitance, but this can be prevented by providing the nMOS transistor NTP 14 (324) for precharging. Figure 15 is a view showing the results of a simulation for actually finding the number of the boosting stages and the result of the boosting voltage using the booster circuit according to the present invention and the conventional booster circuit. In Fig. 15, an abscissa shows the number of the boosting stages and an ordinate shows the boosting voltage. The upper portion shows the results of simulation when the positive booster circuit is used, and the lower portion shows the results of simulation when the negative booster circuit is used. In the diagram, a curve indicated by a mark "o" shows the results of simulation by the product of the present invention, and the curves indicated by the marks "Δ" and "x" show the results of simulation of two products, i.e., the conventional product 1 and the conventional product 2. As concrete circuits, a circuit shown in Fig. 14 was used as the product of the present invention of the positive booster circuit, a circuit of Fig. 5 was used as the conventional product 1, and a circuit obtained by adding the precharging function to the circuit structure of Fig. 1 was used as the conventional product 2. Also, as the product of the present invention of the negative booster circuit, a circuit obtained by adding the precharging function to the circuit structure shown in Fig. 13 was used, a circuit constituted by applying the nMOS transistor to the circuit structure of Fig. 5 was used as the conventional product 1, and a circuit obtained by adding the precharging function to the circuit of Fig. 4 was used as the conventional product 2. As seen from Fig. 15, the product of the present invention can perform boosting to a high voltage by a smaller number of stages in comparison with the conventional products 1 and 2. As explained above, according to the present invention, the back bias effect can be suppressed. Accordingly, boosting to the high voltage can be carried out by a small number of stages. Also, the maximum value of the gate voltage can be lowered to about +0.8V, which is lower than the conventional output voltage +2 to 3V, which is advantageous in the setting of the gate voltage resistance. Since the gate pumping capacitor is unnecessary, the increase of the surface area of the circuit and the power consumption can be prevented. Further, it is sufficient even if the clock signal has only two phases, and therefore there are advantages such that, not only can complication of the clock generation circuit be prevented, but also the current capability is excellent and the operation range is wide in the low voltage source direction.

Claims: A booster circuit comprising: a first transistor (126) operatively connecting a first node (118) and a second node (119) which are connected to a boosting element (111,112) and which are complementarily boosted and a second transistor (106) which operatively connects the second node (119) and a substrate well of said first transistor (126), said first node (118) being connected to a gate of said first transistor (126) and a gate of said second transistor (106), and said substrate well of said first transistor and said substrate well of said second transistor being connected. A booster circuit comprising: a first transistor (206) operatively connecting a first node (198) and a second node (199) which are connected to a boosting element (211,212) and which are complementarily boosted and a second transistor (191) which operatively connects said first node (198) and a substrate well of said first transistor (206), said first node (198) being connected to a gate of said first transistor (206), said second node (199) being connected to a gate of said second transistor (191), and said substrate well of said first transistor (206) and said substrate well of said second transistor (191) being connected. A booster circuit comprising: a first substrate well (152) comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well (153) comprising a second conductivity type semiconductor region formed in the first substrate well (152); first, second, third, and fourth diffusion layers (155, 156a, 156b) of the first conductivity type formed inside the second substrate well (153); a fifth diffusion layer (157) of the second conductivity type formed inside the second substrate well (153); a first gate electrode (158a) formed on a space between said first and second diffusion layers (155, 156a); and a second gate electrode (158b) formed on the space between said third and fourth diffusion layers (156a, 156b), said first diffusion layer (155) being connected to said first and second gate electrodes (158a, 158b), said second diffusion layer (156a) being connected to said third diffusion layer (156a), and said fourth diffusion layer (156b) being connected to said fifth diffusion layer (157). A booster circuit comprising: a first substrate well (152) comprising a first conductivity type semiconductor region biased to a predetermined potential; a second substrate well (153) comprising a second conductivity type semiconductor region formed in the first substrate well (152); first, second, third, and fourth (155, 156a, 156b) diffusion layers of the first conductivity type formed inside the second substrate well (153); a fifth diffusion layer (157) of the second conductivity type formed inside the second substrate well (153); a first gate electrode (158a) formed on a space between said first and second diffusion layers (155, 156a); and a second gate electrode (158b) formed on the space between said third and fourth diffusion layers (156a, 156b), said first diffusion layer (153) being connected to said third diffusion layer (156a) and first gate electrode (158a), said second diffusion layer (156a) being connected to said second gate electrode (158b), and said fourth diffusion layer (156b) being connected to said fifth diffusion layer (157). A booster circuit as set forth in claim 3 or 4, wherein said first conductivity type comprises an n-type and said second conductivity type comprises a p-type.

Inventors: ARAKAWA HIDEKI, ARAKAWA, HIDEKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: G11C5
IPC codes: H02M3, G11C5, G11C17, G11C11, G11C16