Semiconductor memory having a high speed sense amplifier

Abstract: A semiconductor memory comprises a memory cell array including a plurality of digit lines, a plurality of word lines, a plurality of memory cells located at intersections between the digit lines and the word lines, and a column selection circuit for selecting one digit line from the digit lines in accordance with a selection signal. A sense amplifier includes a first P-MOS transistor for precharging a digit line selected by the column selection circuit, an inverting amplifier having an input connected to receive a signal on the selected digit line, and a second P-MOS transistor having a gate and a drain connected to an output and an input of the inverting amplifier, respectively. A gate-grounded third P-MOS transistor maintained in a conductive condition is connected at its source to a voltage supply voltage and at its drain connected to a source of the P-MOS second transistor. The third P-MOS transistor has an on-resistance larger than that of the second transistor and substantially the same current driving capability as that of the second transistor.

Description: Background of the Invention Field of the invention The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory including a sense amplifier for reading out binary information stored in a memory cell in the form of a conductive/non-conductive condition. Description of related art In most of semiconductor memories so configured as to read out information stored in a memory cell which is connected between a digit line and a reference voltage point and which is adapted to store binary information in the form of whether an electric condition between the digit line and the reference voltage point is conductive or non-conductive, a sense amplifier for amplifying a signal corresponding to information stored in the memory cell is of a current detection type Referring to Figure 1, there is shown one example of this type conventional semiconductor memory incorporating therein the current detection type sense amplifier. The shown semiconductor memory comprises a memory cell array 10 including a plurality of digit lines DL 1 , DL 2 , ···, a plurality of word lines WL 1 , WL 2 , ··· isolated from the plurality of digit lines and intersecting the plurality of digit lines, a plurality of memory cells MC 11 , MC 12 , ···, MC 21 , MC 22 , ···, ··· respectively located at intersections between the digit lines DL 1 , DL 2 , ··· and the word lines WL 1 , WL 2 , ···. Each of the memory cells is connected at its one end to a corresponding digit line and at its other end to ground, and constructed to store binary information in such a manner that when a corresponding word line (gate) is at a selection level, if a diffusion layer has been formed between the one end and the other end of the memory cell, the memory cell is conductive, and if a diffusion layer has not been formed between the one end and the other end of the memory cell, the memory cell is non-conductive. The semiconductor memory also includes a column selection circuit 20 having N-channel field effect transistors Tr 11 , Tr 22 , ··· each having a source connected to a corresponding digit line DL 1 , DL 2 , ··· and a drain connected in common to a common node N 1 . A gate of each of the transistors Tr 11 , Tr 22 , ··· is connected to receive a corresponding selection signal Y 1 , Y 2 , ···, so that one digit line is selected from the plurality of digit lines DL 1 , DL 2 , ··· by one transistor Tr 11 , Tr 22 , or ··· receiving an active selection signal Y 1 , Y 2 , or ···. Furthermore, the semiconductor memory includes a sense amplifier 30, which comprises a first field effect transistor Tr 31 of a P-channel type having a source connected to a voltage supply voltage V DD and a drain connected to the common node N 1 . A gate of the transistor Tr 31 is connected to receive a precharge signal P, so that the transistor Tr 31 operates to precharge the common node N 1 , hence, a digit line selected by the column selection circuit 20, to a predetermined potential at a predetermined timing in response to the precharge signal P. The sense amplifier 30 also comprises an inverting amplifier IV 31 having an input connected to receive a signal on the common node N 1 (connected to selected digit line) and outputting an inverted signal of the received signal, and a second field effect transistor Tr 32X of the P-channel type having a source connected to the voltage supply voltage V DD , a gate connected to an output (node N 2 ) of the inverting amplifier IV 31 and a drain connected to the input of the inverting amplifier IV 31 . This second transistor Tr 32X cooperates with the inverting amplifier IV 31 so as to maintain a signal level on each of the input and the output of the inverting amplifier IV 31 . The sense amplifier 30 furthermore comprises an inverting amplifier IV 32 receiving an output signal from the inverting amplifier IV 31 for outputting an inverted output signal OUT. Now, operation of the above mentioned semiconductor memory will be described with reference to Figure 2. First, explanation will be made on the case of reading out information stored in the memory cell MC 12 in which a diffusion layer is not formed. The precharge signal P is brought from a high level to a low level, and the column selection signal Y 1 is brought from a low level to a high level (selection level). At this time, the column selection signal Y 2 and the word lines WL 1 , WL 2 , ··· are maintained at a low level (non-selection level). Therefore, the transistors Tr 31 and Tr 21 are turned on, so that the input (node N 1 ) of the inverting amplifier IV 31 is brought to a voltage supply voltage level V DD , and the digit line DL 1 is precharged to a level of {the voltage supply voltage level V DD minus a threshold of Tr 21 }. Thereafter, the precharge signal P is brought to the high level so as to stop the precharging, and on the other hand, the word line WL 2 is brought to a high level (selection level), so that the memory cells MC 12 , MC 22 , ··· connected to the word line WL 2 are put into a selected condition. At this time, depending upon a content (conductive condition or non-conductive condition) stored in each of the memory cells MC 12 , MC 22 , ···, the level of each of the digit lines DL 1 , DL 2 , ··· either assumes a ground potential level (in the case of the conductive condition) or remains at the same level as that in a just preceding condition (in the case of the non-conductive condition). In this example, since the digit line DL 1 is selected by the column selection circuit 20, a content stored in the memory cell MC 12 selected by the digit line DL 1 and the word line WL 2 is transmitted to the inverting amplifier IN 31 . Since no diffusion layer is formed in the memory cell MC 12 as mentioned above, the condition between the digit line DL 1 and the ground is non-conductive. Accordingly, the digit line DL 1 and the node N 1 are maintained at the precharge potential (a high level substantially corresponding to the voltage supply voltage level V DD ), and the output signal OUT of the voltage supply voltage level V DD (high level) is outputted through the inverting amplifiers IV 31 and IV 32 . At this time, if a leak current flows out of the digit line DL 1 , the level of the digit line DL 1 is inclined to gradually lower from the precharged level. However, since the transistor Tr 32X receiving at its gate the low level output of the inverting amplifier IV 31 is turned on so as to maintain the node N 1 at the voltage supply voltage level V DD . Namely, the transistor Tr 32X functions to compensate for the leak current. Next, explanation will be made on the case of reading information stored in the memory cell MC 22 in which a diffusion layer has been formed. The precharge signal P is brought to the low level, and the column selection signal Y 2 is brought from the high level (selection level). The node N 1 and the digit line DL 2 are precharged to the voltage supply voltage level V DD and a level of {the voltage supply voltage level V DD minus a threshold of Tr 22 }, respectively. Thereafter, the precharge signal P is brought to the high level so as to stop the precharging, and on the other hand, the word line WL 2 is brought to a high level (selection level). Since the diffusion layer is formed in the selected memory cell MC 22 , the condition between the digit line DL 2 and the ground is conductive. Accordingly, the digit line DL 2 is discharged to the ground potential level, and therefore, the node N 1 and hence the output signal OUT are brought to a low level (ground level). As would be understood from the above, it is sufficient if the transistor Tr 32X has an extremely small current driving capability at such a degree as to be able to compensate for the leak current from the digit line connected to the selected memory cell which is in a non-conductive condition (in which no diffusion layer is formed). On the other hand, when the memory cell in the conductive condition (in which the diffusion layer is formed) is selected, it is necessary to make the node N1 and the corresponding digit line as close to the ground potential as possible. Namely, the transistor Tr 32X is required to have a sufficiently large on-resistance. Thus, the transistor Tr 32X has been designed to have a small channel width and a long channel length so as to have a small current driving capability and a large on-resistance. In the above mentioned conventional semiconductor memory, since the transistor Tr 32X has been designed to have a small channel width and a long channel length, a gate capacitance of the transistor Tr 32X is large, and therefore, the inverting amplifier IV 31 having the output connected to the gate of the transistor Tr 32X becomes to have a large load capacitance. As a result, the read-out operation takes a substantial time. EP-A-0 447 277 discloses a semiconductor memory device comprising a sense amplifier. In this memory device a series connection of a first and second transistor is connected between a power supply line and the input of an inverter. The output of the inverter is connected to the control electrode of one of said two transistors. On the other side, US-A-5 303 194 discloses a further semi-conductor memory device, in which, in order to avoid through current through a cell transistor, a pull-up transistor is connected in series with a second transistor. The other end of the second transistor is connected with the input of an inverter, the control electrode of the second transistor is provided with the output of the inverter. The pull-up transistor is turned on by a signal, after a cell transistor has been activated. Summary of the Invention Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a sense amplifier for a semiconductor memory, capable of speeding up the read-out operation. Accordingly, the invention provides a semiconductor memory according to claim 1. The dependent claims are related to different advantageous aspects of the present invention. In one embodiment, a gate of the third transistor is biased to a predetermined fixed voltage, for example, a ground potential level. Alternatively, in another embodiment, the sense amplifier also includes a fourth transistor having a source connected to the predetermined voltage and a drain and a gate connected in common to a constant current source, the gate of the fourth transistor being connected to a gate of the third transistor, so that a current mirror circuit is constituted by the third and fourth transistors so as to control an electric current flowing through the third transistor. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of a conventional semiconductor memory incorporating therein the current detection type sense amplifier, Figure 2 is a timing chart illustrating an operation of the semiconductor memory shown in Figure 1; Figure 3 is a circuit diagram similar to that of Figure 1 but illustrating a first embodiment of the semiconductor memory in accordance with the present invention; and Figure 4 is a circuit diagram similar to that of Figure 1 but illustrating a second embodiment of the semiconductor memory in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 3, there is shown a circuit diagram similar to that of Figure 1 but illustrating a first embodiment of the semiconductor memory in accordance with the present invention. In Figure 3, elements similar to those shown in Figure 1 are given the same Reference Numerals, and explanation thereof will be omitted for simplification of the description. As seen from comparison between Figures 1 and 3, the first embodiment shown in Figure 3 has the same memory cell array 10 as that of the conventional example shown in Figure 1 and the same column selection circuit 20 as that of the conventional example shown in Figure 1. The first embodiment shown in Figure 3 has a sense amplifier 40 different from the sense amplifier 30 of the conventional example shown in Figure 1. As also seen from comparison between Figures 1 and 3, the sense amplifier 40 is different from the sense amplifier 30 in that a pair of P-channel field effect transistors Tr 32 and Tr 33 is provided in place of the transistor Tr 32X in the sense amplifier 30 shown in Figure 1. A gate of the transistor Tr 32 is connected to the output of the inverting amplifier IV 31 , and a drain of the transistor Tr 32 is connected to the input of the inverting amplifier IV 31 . This transistor Tr 32 has as the shortest channel length as possible. On the other hand, a source of the transistor Tr 33 is connected to the voltage supply voltage V DD , and a drain of the transistor Tr 33 is connected to a source of the transistor Tr 32 . In addition, a gate of the transistor Tr 33 is connected to ground. This transistor Tr 33 has a long gate length so as to have a sufficiently large on-resistance. In the above mentioned first embodiment, it is sufficient if each of the series-connected transistors Tr 32 and Tr 33 has an extremely small current driving capability at such a degree as to be able to compensate for the leak current from the digit line connected to the selected memory cell which is in a non-conductive condition (in which no diffusion layer is formed). Accordingly, each of the transistors Tr 32 and Tr 33 can be constructed to have a small current driving capability at substantially the same degree as that of the transistor Tr 32X in the conventional example. On the other hand, in order to ensure that when the memory cell in a conductive condition is selected, the digit line and the node N1 connected to the selected conductive memory cell can be brought to a level sufficiently near to the ground level, by action of only the on-resistance of the transistor Tr 33 , the on-resistance of the transistor Tr 33 is set to be sufficiently large. With this arrangement, the gate length of the transistor Tr 32 can be made to the shortest length which can be realized in a current manufacturing technology. As a result, the gate capacitance of the transistor Tr 32 connected to the output of the inverting amplifier IN 31 , namely, a load capacitance of the inverting amplifier IN 31 can be made small, and therefore, the read-out operation velocity can be speeded up. The other fundamental operation of the first embodiment is similar to that of the conventional example shown in Figure 1, and therefore, explanation will be omitted. Referring to Figure 4, there is shown a circuit diagram similar to that of Figure 1 but illustrating a second embodiment of the semiconductor memory in accordance with the present invention. In Figure 4, elements similar to those shown in Figures 1 and 3 are given the same Reference Numerals, and explanation thereof will be omitted for simplification of the description. As seen from comparison between Figures 3 and 4, the second embodiment is characterized by comprising a modified sense amplifier 40A in place of the sense amplifier 40 provided in the first embodiment. The sense amplifier 40A is different from the sense amplifier 40 in that the sense amplifier 40A includes, in addition to the sense amplifier 40, a constant current source I 1 for flowing therethrough a predetermined current, and a P-channel transistor Tr 34 having a source connected to the voltage supply voltage V DD , and a drain and a gate connected in common through the constant current source I 1 to the ground. The gate of the transistor Tr 34 is connected to the gate of the transistor Tr 33 so that the transistor Tr 34 cooperates with the transistor Tr 33 so as to constitute a current mirror circuit and therefore to control the current flowing trough the transistor Tr 33 . For example, assuming that the current of the constant current source I 1 is 1 mA, and also assuming that the channel length and the channel width of the transistor Tr 34 are 1 µm and 1000 µm, respectively, and the channel length and the channel width of the transistor Tr 33 are 1 µm and 10 µm, respectively, the current flowing through the transistor Tr 33 becomes 10 µA (= 1 mA × 10/1000). Thus, by adjusting a ratio in the channel width (and/or the channel length) between the transistors Tr 33 and Tr 34 , it is possible to easily control the current flowing through the transistor Tr 33 . In the above mentioned embodiments, if it is assumed that the transistor Tr 32 has a minimum size which can be manufactured under a present manufacturing technology, the gate capacitance of the transistor Tr 32 becomes 0.025 pF, which is remarkably smaller than 0.11 pF of the gate capacitance of the transistor Tr 32X in the conventional example. Accordingly, assuming that a rising-up speed and a falling-down speed of the inverting amplifier IV 31 in the conventional example are about 10 ns, the rising-up speed and the falling-down speed of the inverting amplifier IV 31 in the above mentioned embodiments become about 2.2ns. As seen from the above, the present invention is characterized by adding, in series with a transistor having a control electrode and its one main current path end respectively connected to an output and an input of an inverting amplifier receiving a signal on a selected digit line in a sense amplifier, a second transistor having its one main current path end connected to the other main current path end of the first named transistor and its other main current path end connected to a voltage supply potential point, the second transistor having an on-resistance much larger than that of the first named transistor and a current driving capability substantially equal to that of the first named transistor. With this arrangement, the first named transistor can have a minimum gate length which can be manufactured under a present manufacturing technology, and therefore, the gate capacitance of the first named transistor, namely, the load capacitance of the inverting amplifier can be made as small as possible. Accordingly, the read-out operation can be speeded up. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A semiconductor memory comprising: a memory cell array (10) including a plurality of digit lines, a plurality of word lines (WL 1 , WL 2 ), a plurality of memory cells (MC 11 , MC 12 MC 21 , MC 22 ) located at intersections between said digit lines and said word lines; a column selection circuit (20) coupled to said memory cell array (10), for selecting one digit line from the digit lines in accordance with a selection signal; and a sense amplifier (40) including a first transistor (TR31) having a main current path connected between a supply voltage and a digit line selected by said column selection circuit (20), said first transistor (TR31) having a control electrode receiving a precharge signal for precharging said digit line selected by said column selection circuit (20), an inverting amplifier (IV31) having an input connected to a connection node between said first transistor and the selected digit line, and a second transistor (TR32) of a P-channel field effect type having a control electrode connected to an output of said inverting amplifier (IV31), one end of a main current path of said second transistor (TR32) being connected to said input of said inverting amplifier (IV31), characterized in that said sense amplifier (40) further includes a third transistor (TR33) maintained in a conductive condition, one end of a main current path of said third transistor (TR33) being connected to the other end of said main current path of said second transistor (TR32), the other end of said main current path of said third transistor (TR33) being connected to said supply voltage, said third transistor (TR33) having an on-resistance larger than that of said second transistor (TR32) and substantially the same current driving capability as that of said second transistor (TR32). A semiconductor memory claimed in Claim 1 wherein a control electrode of said third transistor (TR33) is biased to a predetermined fixed voltage. A semiconductor memory claimed in Claim 1 wherein said third transistor (TR33) is a P-channel field effect transistor, and a gate of said third transistor is biased to a ground potential level. A semiconductor memory claimed in claim 1 wherein said sense amplifier (40) also includes a fourth transistor (TR34) having a main current path one end of which is connected to said supply voltage, and a control electrode and the other end of said main current path of said fourth transistor (TR34) being in common through a constant current source to ground, said control electrode of said fourth transistor (TR34) being connected to a control electrode of said third transistor (TR33), so that a current mirror circuit is constituted by said third and fourth transistors (TR33, TR34) so as to control an electric current flowing through said third transistor (TR33). A semiconductor memory claimed in claim 4 wherein said fourth transistor is a P-channel field effect transistor.

Inventors: NAKASHIMA YASUHIRO, NAKASHIMA, YASUHIRO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: G11C7
IPC codes: G11C7, G11C17, G11C16