Sense amplifier with hysteresis

Abstract: The differential input stage of a sense amplifier is provided with a positive feedback for introducing a predefinable hysteresis that will prevent spurious switchings of the output of the sense amplifier, enhancing noise immunity. The positive feedback is realized by employing an inverting amplifying stage, which will introduce an hysteresis on one of the two switching phases. The thresholds of the sense amplifier may be made symmetric by modifying the area ratio of the load transistors.

Description: The present invention relates generally to read circuits of memory devices, and in particular to a read comparator (differential sense amplifier) having improved noise immunity which is particularly suited for redundance memory systems and in presence of relatively large capacitances of bitlines and of redundance columns. During a bitline precharging phase that precedes the sensing phase and the read phase proper during which a logic datum read off a memory cell is produced on an output, the bitlines and the input nodes of the read comparator (typically a differential amplifier) are properly equalized. Notwithstanding this, in presence of bitlines with a large capacitance and of redundance columns, where they exist, the input nodes of the sense amplifier and reading may be subject to oscillations and therefore even relatively small differences of potential may be sufficient to cause spurious switchings of the output of the sense amplifier. These phenomena cause a lenghtening of the time necessary to ensure that a definitive stabilization of the output datum of the read circuitry has occured. EP-A-0 594 305 discloses a comparator circuit having a hysteresis that can be precisely controlled. IBM TECHNICAL DISCLOSURE BULLETIN, vol. 30, no. 11, April 1988, New York, US, pages 368-369: "CMOS Differential Amplifier With Wide Hysteresis" discloses a CMOS differential amplifier in which a certain hysteresis is provided by way of an N-channel field effect feedback transistor connected in parallel with one of the differential pair FET devices. The gate of feedback transistor is coupled to the output node so that the hysteresis varies with the output state. It is therefore a main object of the present invention to provide an improved sense amplifier having means for ensuring an enhanced noise immunity, so as to curb or exclude the occurrence of spurious output switchings. Basically, the invention rests on the inplementation of a predefinible hysteresis in the operating characteristics of the sense amplifier, such as to ensure that its output may undergo a transition only in presence of a sufficiently ample separation of the potentials of its input nodes of differential stage, thus ensuring an enhanced immunity to disturbances. As set forth in claim 1, this important result is obtained by implementing a positive feedback during a certain switching phase of the differential sense amplifier. Such a positive feedback is realized by an inverting amplifying stage which may be formed by a single transistor, functionally connected between an output node of the differential input stage and an intermediate node thereof, as will be described more in detail further on in this description. The amplitude of the hysteresis band that is introduced may be easily set by suitably dimensioning the feedback amplifier, that is the size and characteristics of the feedback transistor. In view of the fact that the system is such as to introduce a hysteresis on a certain switching phase of the differential input stage (for example during the phase of switching its output from a high state to a low state), the necessary equalization of the input nodes of the sense amplifier (equalization of the levels or of the switching thresholds) may be re-established by realizing the dynamic load devices of the transistors pair of the differential input stage, with an appropriate ratio between each other areas. The different aspects and advantages of the invention will become more evident through the following description of an important embodiment and by referring to the attached drawings, wherein: Figure 1 schematically shows a read circuit of a memory device employing a sense amplifier or reading comparator provided with means capable of introducing a predefined hysteresis, according to the present invention; Figure 2 shows simulation diagrams of the circuit of Fig.1; Figure 3 shows the timing signals of the circuit; Figure 4 shows simulation diagrams of an equivalent circuit made according to the prior art, for comparison purposes. By referring to the diagram of Fig. 1, a memory reading circuitry is typically composed of clocked selection, precharge and equalization circuits (shown as a whole in the form of a circuit block in Fig. 1) and by a discriminating and reading comparator. The comparator is composed essentially of a differential stage, which may be either provided or not with an output logic buffer. The two outputs loadr and loadm of the selection, precharge and equalization circuitry, constitute the input nodes on a differential input stage of the reading comparator, which is commonly composed of a differential input pair of transistors M9 and M3 and a pair of dynamic load transistors M5 and M0, forming a current mirror. An inverting stage I1 may be employed as an output logic buffer. In the depicted example, the input transistors M9 and M3 are p-channel MOS transistors, having their respective sources connected in common and to a supply node, while their respective loads M5 and M0 are n-channel MOS transistors, preferably "natural" transistors (having a particularly low threshold). According to a basic aspect of the invention, an inverting amplifying stage, which in the depicted example is formed by a single transistor M2, is employed for introducing a positive feedback during a switching phase of the comparator. In the shown example, the switching phase is from a high to a low state of the output of the differential stage. Also the feedback transistor M2 may be a natural, n-channel, MOS transistor, as shown. In the example shown, by assuming high the output of the differential stage, for the output level to switch from high to low, it is necessary that the transistor M0 be turned on. This may occur if the potential present on the gate potential of the M0 transistor rises above the turn-on threshold value of the M0 transistor. On the other hand, the gate voltage of M0 coincides with the voltage drop across the diode (diode connected transistor) M5, which constitutes the dynamic load of the other transistor M9 of the differential input pair. Due to the fact that when the state of the output of the differential stage is high, the positive feedback transitor M2 is conducting, the transistor M9 must reach a more enhanced state of conduction before being capable of forcing a current sufficient to cause the turn-on of the M0 transistor. In practice, this means having introduced an hysteresis in the switching phase from a high to a low state of the output of the differential input stage of the reading comparator. The amplitude of the introduced hysteresis may be predefined by appropriately dimensioning the feedback transistor M2. With the dimension shown in the circuit diagram of Fig. 1, the hysteresis that is introduced is of about 800 mV. Dimensions are indicated in a conventional way by the pair of values L/W, expressed in micrometers (µ). As a consequence of the introduction of an hysteresis in one switching phase (from high to low in the shown example) of the output of the differential input stage of the reading comparator, the operating point of the comparator may be re-equalized by modifying the area ratio between the two dynamic load elements (transistors) M5 and M0, as shown in the diagram of Fig.1. The effect of the positive feedback introduced by the inverting stage M2, may be clearly observed in the simulation diagrams of the sense amplifier shown in Fig. 2, according to the timing signals shown in Fig. 3. A possible timing scheme of the signals, which may be observed from the diagrams of Fig. 3, would be the following: ym0: selection of the preceeding column; ym2: selection of a column; yr2: selection of redundance column; ck: precharge-equalization signal. By observing the simulation diagrams of Fig. 2, it may be observed that, during switching, the redundance cell is selected for few nanoseconds, however no spurious switching of the output (hist) occurs. Viceversa, in the case of a reading comparator made according to the prior art and substantially without the feedback stage M2, the same timing scheme produces a circuit behaviour as depicted in the diagrams of Fig. 4. As may be observed, the inversion of the input nodes that may occur during a precharge, produces a spurious switching a glitch "std" of the output, which by contrast is totally absent in the case of a similar circuit, modified according to the present invention by introducing an hysteresis. It is evident that the circuit of the invention may be realized in different ways, for example: the amplifying feedback stage M2 may also be implemented by employing an amplifier. The configuration of the comparator may be different from the one depicted, for example by inverting the conductivity type of the transistors used, and so forth.

Claims: A sense amplifier having a differential input pair of transistors (M9, M3) of a first type of conductivity and a second pair of load transistors (M5, M0) of a second type of conductivity connected in a current mirror configuration and positive feedback means (M2) active during one switching phase, introducing a certain hysteresis, characterized in that said pair of load transistors (M5, M0) have an area ratio between each other such to make the switching thresholds of the sense amplifier symmetric, notwithstanding the hysteresis introduced by said positive feedback means (M2) in one of the two switching phases. The sense amplifier as defined in claim 1, wherein said positive feedback means (M2) during a switching phase are constituted by an inverting amplifying stage (M2) having an input connected to the connection node of one of the differential input pair transistors and the associated load transistor and an output coupled to the connection node of the other transistor (M9) of said differential input pair of transistors to the other load transistor (M5) that constitutes the input branch of said current mirror (M5, M0). The sense amplifier as defined in claim 2, wherein said inverting amplifying stage is formed by a single transistor (M2) of said second type of conductivity having a control terminal connected to the output node of the differential stage, a first current terminal connected to a common supply node (GND) and a second current terminal connected to said connection node. The sense amplifier according to claim 3, wherein said input pair is composed of p-channel MOS transistors (M9, M3) having respective sources connected in common to a supply node (Vdd) and said load transistors (M5, M0) are n-channel MOS transistors and wherein the load transistor (M0) connected to the drain of the transistor (M3) of said input pair that constitutes the output node of the differential stage has a greater area than the other load transistor (M5), that is configured as a diode and connected to the drain of the other transistor (M9) of said input pair. The sense amplifier according to claim 4, wherein said n-channel MOS load transistors and said positive feedback transistor (M2) are natural threshold transistors. The sense amplifier according to any of the preceding claims, characterized by comprising an output logic buffer (I1).

Inventors: BARCELLA ANTONIO, BARCELLA, ANTONIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G11C7
IPC codes: G11C17, G11C16, G11C7