A multi-layer wiring board and a manufacturing method thereof

Abstract: A multi-layer wiring board has at least one stacking block with an insulating hard substrate, a grounding layer being provided in the insulating hard substrate. A plurality of wiring layers are provided over upper and lower major surfaces of the insulating hard substrate. A plurality of throughholes are provided in the insulating hard substrate for connecting wiring layers on the top and bottom surfaces of the substrate. A base block has an insulating base board, and at least one wiring layer provided over one major surface of the insulating base board. Connections electrically and mechanically connect the at least one stacking block and the base block. The stacking block and the base block may be simultaneously manufactured in parallel with others. The stacking block and the base block may be adhered to each other by an adhesive layer. Each electrical connection between the stacking block and the base block may be achieved with bumps and pads.

Description: The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a multi-layer wiring board having multiple wiring layers using polyimide resin for inter-layer insulation, and a manufacturing method thereof. Multi-layer printed wiring boards have been used heretofore as wiring boards on which to mount LSI chips. A multiple printed wiring board has copper-sputtered stacked plates as a core and prepregs as a adhesive for connection between the copper-sputtered stacked plates, and the copper-sputtered stacked plates and prepregs are alternately stacked and integrated by thermal press processes. Electrical connections between the copper-sputtered stacked plates are achieved by forming penetrating throughholes with a drill after the copper-sputtered stacked plates and prepregs are integrated, and coating the inner walls of the penetrating throughholes with copper. Furthermore, in recent years, multi-layer wiring boards using polyimide resin over ceramic substrates for inter-layer insulation have come to be used as wiring boards for high performance computer use, where greater density than that of multi-layer printed wiring boards is required. A polyimide ceramic multi-layer wiring board which has polyimide resin insulating layers and multiple wiring layers is formed by the repetition of the following two processes. Polyimide resin insulating layers are formed by supplying polyimide precursor varnish over a ceramic substrate, drying it and forming via holes in this coating film over the ceramic substrate. Multiple wiring layers are formed by photolithographic methods, vacuum evaporation methods, and metal plating methods. On the other hand, there also is a method to form a polyimide ceramic multi-layer wiring board by forming conductor lines as a signal layer over polyimide sheets, aligning these sheets over a ceramic substrate, and successively alternately stacking and pressing the sheets over the ceramic substrate. However, the above-mentioned multi-layer wiring boards have some disadvantages as follows. For the above-mentioned multiple printed wiring board, since electrical connections between the copper-sputtered stacked plates are achieved by penetrating throughholes which are formed through from the top printed wiring board to the bottom printed wiring board with a drill, it is impossible to form physically minute penetrating throughholes in the signal wiring layer part of the multiple printed wiring board, and accordingly it is impossible to form many conductor lines between the penetrating throughholes over the copper-sputtered stacked plates. Furthermore, one penetrating throughhole is always needed for electrical connection between each of the stacked plates, so that the capacity to accommodate signal conductor lines is reduced by an increase in the number of stacked layers, resulting in the disadvantage that it is difficult to form multiple printed wiring boards having high wiring density. On the other hand, since the above-mentioned polyimide ceramic multi-layer wiring board is always formed by the repetition of the processes of applying polyimide precursor varnish over the ceramic substrate, drying it, forming via holes in the coating film and curing it as many times as the number of polyimide insulating layers stacked over the ceramic substrate, the stacking process of the polyimide resin insulating layers takes an extremely long time, Moreover, since the above-mentioned polyimide resin insulating layers are always formed by the repetition of the processes of applying polyimide precursor varnish over the ceramic substrate, drying it, forming via holes in the coating film and curing it, the thermal stress of the curing process which is repeated many times is applied on polyimide resin in the lower layer part of the polyimide resin insulating layers. Therefore, it is difficult to improve the manufacturing yield of polyimide resin insulating layers because of deterioration of the lower layer part of the polyimide resin insulating layers due to thermal stress of the curing process. On the other hand, since the above-mentioned polyimide ceramic multi-layer wiring board is always formed by forming conductor lines as a signal layer over polyimide sheets, aligning these sheets over a ceramic substrate, and successively alternately stacking and pressing the sheets over the ceramic substrate, the thermal stress of the stacking and pressing processes is applied on polyimide resin in the lower layer part of the polyimide resin insulating layers many times, and the polyimide resin in the lower layer part of the polyimide resin insulating layers is deteriorated and the stacking process of the polyimide resin insulating layers takes an extremely long time as a result. US-A-5 350 886 discloses a mounting substrate with a ceramic substrate, a thin-film wiring layer and an LSI connected to the thin-film wiring layer by solder balls. US-A-4 803 595 discloses an interposer chip technique for the interconnection of semiconductor chips. Ceramic interposer substrates are located between the chips and a common substrate. US-A-5 146 674 forms a multilayer wiring board comprising a plurality of stacking blocks having wirings on the major surfaces thereof, a ground plane within the blocks and throughholes connecting the wirings, however excludes the use of a ceramic board or glass ceramic board of the insulating hard substrate for the stacking blocks. It is therefore an object of the present invention to eliminate the above-mentioned disadvantages and provide a multi-layer wiring board and a manufacturing method thereof which prevent the polyimide resin insulating layers from heat deterioration. It is another object of the present invention to eliminate the above-mentioned disadvantages and provide a multi-layer wiring board and a manufacturing method thereof which shortens the manufacturing time, and improves the manufacturing yield. The present invention provides a multi-layer wiring board as defined in claim 1. The invention further provides a manufacturing method for a multi-layer wiring board as defined in claim 6. The above objects and features of this invention will become more apparent from the following detailed description when taken in conjunction with the attached drawings. Fig. 1 is a cross-sectional view of a stacking block; Fig. 2 is a cross-sectional view of an embodiment of the structure of multi-layer wiring boards according to the present invention; Fig. 3 is a cross-sectional view of another embodiment of the structure of multi-layer wiring boards according to the present invention; Figs. 4A through 4G are cross-sectional views illustrating part of the process sequence of an embodiment of the manufacturing method for multi-layer wiring boards according to the present invention; Figs. 5A through 5F are cross-sectional views illustrating part of the process sequence of an embodiment of the manufacturing method for multi-layer wiring boards according to the present invention; Figs. 6A through 6E are cross-sectional views illustrating part of the process sequence of an embodiment of the manufacturing method for multi-layer wiring boards according to the present invention; Fig. 7 is an illustrative diagram for mutually adhering each block obtained according to Figs. 4A through 6E; and Fig. 8 is a cross-sectional view of the structure of multi-layer wiring boards obtained by the manufacturing method according to Figs. 4A through 7. In the drawings, the same reference numerals respectively denote the same structural elements. Next will be described embodiments of the present invention with reference to the drawings, Referring to Fig. 1, showing an example of a stacking block, a stacking block 100 has a substrate 1, a grounding layer 2 formed therein, and throughholes for mutual connection between multiple signal wiring layer parts 4A and 4B over the upper and lower surfaces of the substrate 1. The multiple signal wiring layer parts 4A and 4B formed over the upper and lower surfaces of the substrate 1 each have signal wiring layers and polyimide resin insulating layers as will be described indetail hereinafter with reference to Figs. 5 and 6. The substrate 1 as an insulating hard substrate is a ceramic board or glass ceramic board having a Rockwell hardness of 70 RCA or more. Referring to Fig. 2, according to an embodiment of the present invention, a multi-layer wiring board comprises the stacking block 100 shown in Fig. 1 and a base block 200. The stacking block 100 is stacked over the base block 200. In this case, an insulating base substrate 10, which may be made of baked alumina ceramic, of the base block 200 has input/output pins 20, molybdenum metal wiring layers 11 and 13 formed over one major surface thereof, and further polyimide resin layers 12 and 15 formed for insulating between the molybdenum metal wiring layers 11 and 13. It is also possible to provide hard heat-resistant organic resin or glass ceramic as materials of the insulating base substrate 10. The signal wiring layer 12 of the base block 200 may be a gold-coated wiring of preferably about 25 µm in wiring width and about 7 µm in wiring thickness. The polyimide resin used for the polyimide resin layers 12 and 15 is for instance, if it is non-photosensitive, PIQ produced by Hitachi Chemical, PYRALYN produced by Du Pont, SEMICOFINE (trademark) produced by Toray or the like or, if it is photosensitive, PL-1200 (trademark) produced by Hitachi Chemical, PI-2702P (trademark) produced by Du Pont, PHOTONEITH (trademark) produced by Toray. PIMEL (trademark) produced by Asahi Chemical or the like, and the film thickness between the wiring layers is preferably about 20 µm. The number of signal wiring layers is two, including the layer 13 and a wiring layer 41B on the underside of the block 100. A connecting pad 41A is formed on the top layer by copper coating for connecting LSI chips by soldering. Whereas the structure of this embodiment comprises two blocks 100 and 200, each block is electrically tested when it is completed, and selected for use if it is satisfactory, followed by advance to the next inter-block connecting process. Connections between the blocks are accomplished with an adhesive 14, bumps 5 and pads 19. Tight adhesion between the blocks is achieved with the adhesive 14. The adhesive 14 may be polyimide resin excelling in heat resistance. The film thickness of the adhesive layer 14 is preferably about 10 µm. Electrical connections between the blocks are achieved by using the bumps 5 and the pads 19 formed in via holes in the adhesive layer 14. The materials for the bumps 5 and the pads 19 may be a gold-tin multi-layer coating, gold coating and the like, and their dimensions may be 50 to 300 µm 2 . They are preferably formed in film thicknesses of about 10 to 50 µm. Referring to Fig. 3, according to still another embodiment of the present invention, a multi-layer wiring board comprises a base block 200 and three stacking blocks 100, 101 and 102, and these stacking blocks 100, 101 and 102 are stacked over the base block 200. In this case, the insulating base substrate 10 of the base block 200 may be a baked alumina ceramic substrate, having internal wiring layers 11 and 13 of molybdenum metal over one major surface. It is also possible to provide hard heat-resistant organic resin or glass ceramic as materials of the insulating base substrate 10. The signal wiring 13 is preferably gold-coated wiring of about 25 µm in wire width and about 7 µm in wire thickness. The polyimide resin used for the polyimide resin layers 12 and 15 is for instance, if it is non-photosensitive, PIQ produced by Hitachi Chemical, PYRALYN produced by Du Pont, SEMICOFINE produced by Toray or the like or, if it is photosensitive, PL-1200 produced by Hitachi Chemical, PI-2702D produced by Du Pont, PHOTONEITH produced by Toray. PIMEL produced by Asahi Chemical or the like, and the film thickness between the wiring layers is preferably about 20 µm. In this case, the number of signal wiring layers is six, having a basic configuration in which each of a signal wiring layer and an electrode layer is located on the topside and underside of the ceramic substrate 1 having a grounding layer and throughholes within, and three blocks 100, 101 and 102, each consisting of this configuration, are stacked over the base block 200. A connecting pad 41A is formed on the top layer of the ceramic substrate 1 having a grounding layer and throughholes within (the stacking block 100) by copper coating for connecting LSI chips by soldering. Each block is electrically tested when it is completed, and selected for use if it is satisfactory, followed by advance to the next inter-block connecting process. Connections between the blocks are accomplished with an adhesive 14-1, 14-2 and 14-3. bumps 5 and pads 19. Tight adhesion between the blocks is achieved with the adhesive 14-1 through 14-3. The adhesive 14 may be polyimide resin excelling in heat resistance. The film thickness of the adhesive layer 14 is preferably about 10 µm. Electrical connections between the blocks are achieved by using the bumps 5 and the pads 19 formed in via holes in the abhesive layers 14-1 through 14-3. The materials used for the bumps 5 and the pads 19 may be a gold-tin multi-layer coating, a gold coating and the like, and their dimensions are preferably about 50 to 300 µm 2 . They are formed in film thicknesses of preferably about 10 to 50 µm. Next will be described a manufacturing method for a multi-layer wiring board structure according to an embodiment of the present invention by using Figs. 4A through 8. First will be described the procedure of manufacturing a base block 200 with reference to Figs. 4A through 4G. First, as shown in Fig. 4A, a wiring layer is patterned by photolithography using a photoresist over the surface of the insulating base substrate 10 containing a conductor layer within, and electrolytic gold coating is carried out to form the wiring layer 11 of 10 µm in thickness. Next, as shown in Fig. 4B, photosensitive polyimide varnish is applied over the insulating base substrate 10 over which the wiring layer 11 has been formed, exposed to light and developed, and via holes 18 are formed in prescribed positions. Then precuring and curing are conducted to selectively form the polyimide resin layer 12 of 10 µm in film thickness, and as shown in Fig. 4C, the signal wiring layer 13 of 10 µm in thickness is formed over the polyimide resin layer 12 by a similar method to the case of Fig. 4A. As shown in Fig. 4D, polyimide varnish is applied, precured and cured to form a polyimide resin layer 15 of 10 µm in thickness. Adhesive including some kind of polyimide is applied over the polyimide resin layer 15 and cured to form the adhesive layer 14 of 10 µm in thickness. Next, an etching pattern is formed over the adhesive layer 14 by photolithography using a photoresist 16 to bore parts for electrical connection with other blocks. Since the photoresist 16 serves as a mask for processing by an excimer laser in a subsequent process, it is formed of about 50 µm in thickness. As shown in Fig. 4E, scanning with an excimer laser beam 17 is conducted over the photoresist 16 to form, as shown in Fig. 4F, via holes 18 through the polyimide resin layer 15 and the adhesive layer 14. In this case, a KrF excimer laser is preferably oscillated at a frequency of 200 Hz to form the via holes 18 through the polyimide resin layer 15 and the adhesive layer 14 at selected locations determined by the photoresist 16. The scanning speed of the KrF excimer laser is adjusted for optimizing the shape of the via holes 18, which should have vertical walls. After that, the remaining dust of the photoresist 16, the adhesive layer 14 and the polyimide resin layer 15 are treated with plasma to be completely cleaned up. The bore of the via holes 18 is preferably about 200 µm at this time. As shown in Fig. 4G, connecting pads 19 are formed on the signal wiring layer 13 in the via holes 18 to achieve electrical connection with the multiple wiring layers of other blacks. The pads 19 are patterned by photolithography using a photoresist, and formed by multi-layer coating including electrolytic nickel coating and electrolytic gold coating. This nickel coating is used to prevent gold/tin soldering metal from diffusing to the signal wiring layer 13 including the electrolytic gold coating. The nickel coating and gold coating are preferably about 3 µm and 10 µm in thickness, respectively, and the size of the pads 19 is preferably about 150 µm. Thus the block 200 which constitutes the base block is obtained by continuing the above-mentioned manufacturing process. Next will be described the procedure of manufacturing the blocks 101 and 102 shown in Fig. 3 with reference to Figs. 5A through 5F. One layer of the signal wiring layer 41A and the electrode layer 41B having pads or bumps for electrical connection with other blocks are formed by the following manufacturing processes over the topside and the underside of the ceramic substrate 1 having the grounding layer 2 and the throughholes 3 within, respectively. By alternately performing the stacking on the topside and the underside of the substrate 1, the stresses acting on the ceramic substrate attributable to the multiple polyimide wiring layers are cancelled with each other to reduce the warp of the ceramic substrate. As shown in Fig. 5A, the signal wiring layer 41A and the electrode 41B are patterned by photolithography using a photoresist over the surfaces of the ceramic substrate 1 having the grounding layer 2 and the throughholes 3 within, and electrolytic gold coating is carried out to form the signal wiring layer 41A and the electrode 41B of preferably about 10 µm in thickness. Next, as shown in Fig. 5B, polyimide varnish is applied over both sides of the ceramic substrate 1, precured and cured to form polyimide resin layers 42A and 42B of preferably about 10 µm in thickness. Next, as shown in Fig. 5C, adhesive including some kind of polyimide is applied over the polyimide resin layers 42A and 42B and cured to form adhesive layers 14 of preferably about 10 µm in thickness. Next, as shown in Fig. 5D, an etching pattern is formed over the adhesive layers 14 by photolithography using a photoresist 45 to bore parts for electrical connection with other blocks. Since the photoresist 45 serves as a mask for processing by an excimer laser in a subsequent process, it is formed of about 50 µm in thickness. Scanning with an excimer laser beam 17 is conducted over the photoresist 45 to form via holes 46A and 46B through the polyimide resin layers 42A and 42B and the adhesive layers 14 as shown in Fig. 5E. In this case, an KrF excimer laser is oscillated at a frequency of 200 Hz to form the via holes 46A and 46B through the polyimide resin layers 42A and 42B and adhesive layers 14. The scanning speed of the KrF excimer laser is adjusted for optimizing the shape of the via holes 46A and 46B, which should have vertical walls. After that, the remaining dust of the photoresist 45, the adhesive layers 14 and the polyimide resin layers 42A and 42B are treated with plasma to be completely cleaned up. The bore of the via holes 46A and 46B is preferably about 200 µm at this time. As shown in Fig. 5F, connecting pads 47A are formed on the signal wiring layer 41A in the via holes to achieve electrical connection with the multiple wiring layers of other blocks. The connecting pads 47A are patterned by photolithography using a photoresist, and formed by multi-layer coating including electrolytic nickel coating and electrolytic gold coating. This nickel coating is used to prevent gold/tin soldering metal from diffusing to the signal wiring layer 41A which includes the electrolytic gold coating. The nickel coating and gold coating are preferably formed of about 3 µm and 10 µm in thickness, respectively, and the size of the connecting pads 47A is preferably about 150 µm. At the same time, connecting bumps 47B are formed on the signal wiring layers 41B in the via holes 46B to achieve electrical connection with the multiple wiring layers of other blocks. The connecting bumps 47B are patterned by photolithography using a photoresist, and formed by multi-layer coating including electrolytic nickel coating, electrolytic gold coating, electrolytic tin coating and electrolytic gold coating in order. This nickel coating is used to prevent gold/tin soldering metal from diffusing to the signal wiring layer 41B which includes the electrolytic gold coating. The coating thickness is preferably about 3 µm for nickel, about 8 µm for gold, about 11 µm for tin and about 8 µm for gold, respectively, and the size of the connecting bumps 47B is preferably about 100 µm. At this time, the gold and tin coating are formed in the weight ratio of 4:1. Next will be described the procedure of manufacturing the block 100 shown in Fig. 3 with reference to Figs. 6A through 6E. As shown in Fig. 6A, connecting pads 41A for connecting LSI chips by soldering are patterned by photolithography using a photoresist over the surface of the ceramic substrate 1 having the grounding layer 2 and the throughholes 3 within, and formed by multi-layer coating including electrolytic nickel coating and electrolytic copper coating, The electrolytic nickel coating is used as a barrier layer against solders by which LSI chips are connected on the connecting pads 41A. A signal wiring layer 41B and an electrode layer having connecting bumps for electrical connection with other blocks are formed over the underside of this ceramic substrate 1 by the following manufacturing processes. As shown in Fig. 6B, a signal wiring layer 41B is patterned by photolithography using a photoresist over the underside of the ceramic substrate 1, and an electrolytic gold coating is carried out to form a signal wiring layer 41B of about 10 µm in thickness. Next, polyimide varnish is applied over the underside of the ceramic substrate 1, precured and cured to form a polyimide resin layer 42B preferably of about 10 µm in thickness. Adhesive including some kind of polyimide is applied over this polyimide resin layer 42B and cured to form an adhesive layer 14 preferably of about 10 µm in thickness. As shown in Fig. 6C, an etching pattern is formed over the adhesive layer 14 by photolithography using a photoresist 45 to bore parts for electrical connection with other blocks. Since the photoresist 45 serves as a mask for processing by an excimer laser in a subsequent process, it is formed of about 50 µm in thickness. As shown in Fig. 6D, scanning with an excimer laser beam 17 is conducted over the photoresist 45 to form via holes 46B through the polyimide resin layer 42B and the adhesive layer 14. In this case, a KrF excimer laser is oscillated at a frequency of 200 Hz to form the via holes 46B through the polyimide resin layer 42B and the adhesive layer 14. The scanning speed of the KrF excimer laser is adjusted for optimizing the shape of via holes 46B, which should have vertical walls. After that, the remaining dust of the photoresist 45, the adhesive layer 14 and the polyimide resin layer 42B are treated with plasma to completely clean up. The bore of the via holes 46B is preferably about 200 µm at this time. As shown in Fig. 6E, connecting bumps 47B are formed on the signal wiring layer 41B in the via holes 46B to achieve electrical connection with the multiple wiring layers of other blocks. The connecting bumps 47B are patterned by photolithography using a photoresist, and formed by multi-layer coating including electrolytic nickel coating, electrolytic gold coating, electrolytic tin coating and electrolytic gold coating in order. This nickel coating is used to prevent gold/tin soldering metal from diffusing to the signal wiring layer 41B including the electrolytic gold coating. The coating thickness is preferably about 3 µm for nickel, about 8 µm for gold, about 11 µm for tin and about 8 µm for gold, respectively, and the size of the connecting bumps 47B is preferably about 100 µm. At this time, the gold and tin coating are formed in the weight ratio of 4:1. Next will be described the procedure of manufacturing a multi-layer wiring board structure by using the block 100 shown in Figs. 6A through 6E, the blocks 101 and 102 shown in Figs. 5A through 5F, and the block 200 shown in Figs. 4A through 4G. For this example, it will be assumed that a multi-layer wiring board has a total of 6 signal wiring layers as shown in Fig. 7. The manufacturing process for such a multi-layer wiring board will be described below. First, the two blocks 101 and 102 formed by the processes shown in Figs. 5A through 5F are aligned over the base block 200 formed by the processes shown in Figs. 4A through 4G. After that, the two blocks 101 and 102 and the base block 200 are stacked and adhered with temporary adhesive 48 to adhere one to another. Second, the block 100 formed by the processes shown in Figs. 6A through 6E is similarly aligned over the block 101. After that, the block 100 and the block 101 are stacked and adhered with temporary adhesive 48 to form one integrated board. In this case, it takes about 2 minutes at normal temperature under a pressure of 1 kg/cm 2 to adhere them to each other with the temporary adhesive 48. Moreover, this laminated board is subjected to pressurizing and heating in a vacuum within an auto-clave apparatus for finally adhering the polyimide adhesive layers 14 with each other and adhering the electrodes (the connecting pads 19 and 47A and the connecting bumps 47B) with each other, formed on the top layer of each block. In this case, it takes about 30 minutes at 350°C under a pressure of 20 kg/cm 2 for achieving adhesion with the polyimide adhesive layers 14. Since polyimide adhesive is fluidized under these conditions, and the polyimide adhesive layers 14 become integrated with each other, it is possible to achieve firm and tight adherence between the blocks. At the same time, the connecting bumps 47B formed by multi-layer coating including electrolytic gold coating and electrolytic tin coating become melted at 280°C, which is their eutectic point, and become connected to the corresponding connecting pads 19 and 47A. It is thereby possible to achieve sufficient electrical connection between the blocks after pressing as shown in Fig. 8. Finally, input/output pins and power supply pins 20 are assembled in their respectively prescribed positions on the underside of the insulating base substrate 10 to complete the multi-layer wiring board structure shown in Fig. 3. Incidentally, although the hard substrate of each block may be made of ceramic in the above-described embodiments, it is evident that glass ceramic can be used in the hard substrate, and solders which are alloys of gold can be used besides only gold as the materials for the pads and bumps for inter-block connection. Furthermore, the number of multiple wiring layers is not limited to those in the above-described embodiments, and the number of blocks to be stacked also permits various modifications. As heretofore described, according to the present invention, by composing an insulating hard substrate having a grounding layer and throughholes within, and a plurality of wiring layers formed over the topside and the underside thereof into one block, stacking a plurality of such blocks into a laminated structure, adhering the blocks by adhesion between adhesive layers formed over the top layers, on the upper and lower sides, of each block, and achieving electrical connection between the blocks by connection between the soldered electrodes formed on the surfaces of each block, the penetrating throughholes, which are physically roughly formed through from the top printed wiring board to the bottom printed wiring board with a drill in a conventional multiple printed wiring board, are dispensed with due to the formation of the penetrating throughholes with a drill in only the insulating base substrate of the base block, and it is pcssible to achieve a large accommodation capacity for the signal wiring, a greater number of multiple wiring layers and high-density wiring since a minute pattern can be formed in the signal wiring layer parts. Moreover, the multiple repetition of the curing process required for conventional polyimide ceramic multi-layer wiring boards is dispensed with to make it possible to reduce the time required for the manufacture of wiring boards, to prevent thermal deterioration of polyimide resin by the multiple repetition of the curing process, and to enable satisfactory blocks to be selected for stacking since it is possible to electrically test the wiring layers block by block. Furthermore, since a ceramic substrate or a hard organic resin substrate is used as the base substrate within the base block, even if the required number of layers for the multiple wiring layer part is increased, it is possible to reduce such troubles as cracks in the polyimide resin insulating layer of multiple wiring layer part or its coming off the ceramic substrate or the hard organic resin substrate due to the thermal deterioration and deformation of the polyimide resin insulating layer of the multiple wiring layer part by the multiple repetition of the heat supplying process. Therefore, the present invention has the effect to enable multi-layer wiring boards of high quality, increased in the number of multiple layers, and of high density to be manufactured in a smaller number of days and, moreover, in a high manufacturing yield. Although the present invention has been fully described by way of a preferred embodiment thereof with reference to the accompanying drawings, various changes and modifications falling within the scope of the present invention as defined in the appended claims will be apparent to those having skill in this field.

Claims: A multi-layer wiring board, comprising: a base block (200) having an insulating base substrate (10), and at least one wiring layer (11, 13) formed over one major surface of said insulating base substrate (10), and a polyimide resin layer (12, 15) formed for insulating between said wiring layers; at least one stacking block (100, 101, 102), being stacked over said base block, having an insulating hard substrate (1), a grounding layer (2) formed in said insulating hard substrate (1), and throughholes (3) extending from one major surface of said insulating hard substrate (1) to the other, wherein the uppermost stacking block (100) of the multilayer wiring board has connecting pads (41 A) provided on the upper major surface of the insulating hard substrate and a wiring layer (41 B) over the lower major surface thereof, and any stacking blocks (101, 102) located between said uppermost stacking block and said base block have wiring layers (41A, 41B) provided over each major surface of the insulating hard substrate thereof, said throughholes electrically connecting the connecting pads or wiring layer over the upper major surface of the insulating hard substrate of the at least one stacking block to the wiring layer over the lower major surface of said insulating hard substrate thereof; and connecting means (5, 14, 19) formed on the upper major surface of said base block (200) and on those major surfaces of said at least one stacking block which include a wiring layer, for electrically and mechanically connecting said blocks to each other, said connecting means comprising an adhesive (14); wherein said insulating hard substrate is a ceramic board or glass ceramic board having a Rockwell hardness of at least 70 RCA. The structure as claimed in claim 1, wherein said insulating base substrate (10) is a hard heat-resistant organic resin. The structure as claimed in claim 1 or 2, wherein said insulating base substrate (10) is a ceramic. The structure as claimed in claim 1 or 3, wherein said insulating base substrate (10) is a glass ceramic. The structure as claimed in any one of claims 1 to 4, wherein said connecting means comprises at least one bump (5) and at least one pad (19). A method of manufacturing a multi-layer wiring board comprising the steps of (a) providing a base block (200) by forming at least one wiring layer (11, 13) over one major surface of an insulating base substrate (10) and forming a polyimide resin layer (12, 15) for insulating between said at least one wiring layer; (b) providing at least one stacking block (100, 101, 102) by forming an insulating hard substrate (1) with a grounding layer (2) therein and throughholes (3) extending from one major surface of said insulating hard substrate to the other; (c) providing one stacking block (100) with connecting pads (41A) over the upper major surface of the insulating hard substrate and a wiring layer (41 B) on the lower major surface of said insulating hard substrate and providing any other stacking blocks (101, 102) with wiring layers (41 A, 41 B) over each major surface of the insulating hard substrate thereof, said throughholes electrically connecting the connecting pads or wiring layer (41A) over the upper major surface of the insulating hard substrate of the at least one stacking block to the wiring layer (41B) over the lower major surface of said insulating hard substrate thereof; (d) forming connecting means (5, 14, 19) including an adhesive layer (14) on the upper major surface of said base block and on those major surfaces of said at least one stacking block which include a wiring layer; and (c) laminating said at least one stacking block over said base block bonding each to the other using said connecting means including said adhesive layer, to mechanically and electrically connect said blocks to each other, wherein said insulating hard substrate is a ceramic board or glass ceramic board having a Rockwell hardness of at least 70 RCA.

Inventors: ISHIDA HISASHI, ISHIDA, HISASHI, ISHIDA, HISASHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H01L23
IPC codes: H01L23, H05K3, H05K1, H01L21