CMOS circuit for implementing boolean functions

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption. The circuit according to the present invention may be employed in a number of logic applications such as simple OR/NOR or AND/NAND circuits, generalized parallel/serial logic networks, comparators, etc.. When employed in a chain, such as in a generalized parallel/serial logic network, NMOS circuit elements may be employed together with gate coupling circuitry to ensure high speed operation with minimum size.

Description: This invention relates to an electronic circuit according to the preamble of claim 1, i.e. to circuits which implement Boolean functions. Many software and hardware applications require the implementation of Boolean functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR, etc. Most Boolean functions may be implemented by interconnecting a plurality of transistors in such a way that binary signals representing input values are applied to control terminals of the transistors and the result of the logical expression is output from a node somewhere within the circuit. The circuits are often classified as static or dynamic. For example, Fig. 1 is a schematic diagram of a static circuit 10 known from EP-A-0 647 029 for implementing a NOR function ( A+B ). Circuit 10 comprises PMOS transistors 14, 18 and NMOS transistors 22, 26. The binary signal representing the A value is applied to a gate terminal 30 of PMOS transistor 14 and to a gate terminal 34 of NMOS transistor 26 The binary signal representing the B value is applied to a gate terminal 34 of PMOS transistor 18 and to a gate terminal 38 of NMOS transistor 22. A source terminal 42 of PMOS transistor 14 is coupled to a V DD potential, and a drain terminal 46 of PMOS transistor 14 is coupled to a source terminal 50 of PMOS transistor 18 at a node 54. A drain terminal 58 of PMOS transistor 18 is coupled to an ( A+B ) output line 62 at a node 64. Drain terminals 68, 72 of NMOS transistors 22, 26 respectively are coupled to ( A+B ) output line 62 at respective nodes 76 and 78. Source terminals 82, 84 of NMOS transistors 22 and 26 are coupled to a ground potential. From inspection of circuit 10, it should be readily apparent that when both A and B are low, then transistors 14 and 18 conduct current into node 64. At this time transistors 22 and 26 are nonconducting. Thus, output line 62 is pulled high. On the other hand, if either A or B are high, then the respective PMOS transistor 14 or 18 is rendered nonconducting. Simultaneously, one or both of NMOS transistors 22 or 26 conducts current away from node 64, and output line 62 is pulled low. One problem with circuit 10 is that, since PMOS transistors are not as conductive as NMOS transistors for a given size, PMOS transistors 14 and 18 typically must have a considerably larger size than transistors 22 and 26. Not only does this consume valuable chip area, but the logic elements which generate the A and B signals must therefore drive more input capacitance. Another problem, shared by all static circuits of this type (and those described below), is that half the circuit becomes nonconducting at any transition (e.g., when A and B go high, PMOS transistors 14, 18 are off and NMOS transistors 22, 26 are on). The nonconducting transistors act as an unnecessary load to the inputs as well as the outputs. Furthermore, the series connection of PMOS transistors 14 and 18 creates unwanted delay through the circuit. Since there must be a series connected PMOS transistor for every input signal, the complexity and delay of the circuit becomes unacceptable very quickly as the number of inputs increase. The same would be true for a NAND circuit although in that case delay and complexity would be caused by serially connected NMOS transistors. Fig. 2 is a schematic diagram of a circuit 100 also known from EP-A-0 647 029 which attempts to overcome the problems of circuit 10 shown in Fig. 1. Circuit 100 comprises PMOS transistors 104, 108 and NMOS transistors 120, 122, 124 and 126. The A input signal is applied to a gate terminal 128 of NMOS transistor 120, and the B input signal is applied to a gate terminal 130 of NMOS transistor 122. The complement of the A input signal is applied to a gate terminal 132 of NMOS transistor 124, and the complement of the B input signal is applied to a gate terminal 134 of NMOS transistor 126. A source terminal 138 of PMOS transistor 104 is coupled to V DD , and a drain terminal 140 of PMOS transistor 104 is coupled to an ( A+B ) output line 144 at a node 142. A source terminal 146 of PMOS transistor 108 is also coupled to V DD , and a drain terminal 148 of PMOS transistor 108 is coupled to an (A+B) output line 152 at a node 150. A gate terminal 154 of PMOS transistor 104 is coupled to node 150, and a gate terminal 158 of PMOS transistor 108 is coupled to node 142. Drain terminals 160, 162 of NMOS transistors 120 and 122, respectively, are coupled to ( A+B ) output line 144 at respective nodes 164 and 142. Source terminals 168, 170 of NMOS transistors 120 and 122 are coupled to a ground potential. A drain terminal 172 of NMOS transistor 124 is coupled to node 150, and a source terminal 174 of NMOS transistor 124 is coupled to a drain terminal 176 of NMOS transistor 126 at a node 180. A source terminal 184 of NMOS transistor 126 is coupled to a ground potential. When either A or B are high, then one or both of NMOS transistors 120 or 122 conduct current away from their respective nodes 164 or 142, which tends to pull ( A+B ) output line 144 low. Additionally, one or more of NMOS transistors 124 or 126 are rendered nonconducting and prevent current flow away from node 150. As node 142 is pulled low, PMOS transistor 108 begins conducting current into node 150, thus pulling (A+B) output line 152 high. The high signal at node 150 renders transistor 104 nonconducting, and the circuit reaches a final state where ( A+B ) output line 144 is low and (A+B) output line 152 is high. If both A and B are low, then NMOS transistors 120 and 122 are both rendered nonconducting and NMOS transistors 124 and 126 conduct current away from node 152. The result is then a high signal at ( A+B ) output line 144 and a low signal at (A+B) output line 152. While circuit 100 eliminates the serially connected stack of PMOS transistors shown in circuit 10 of Fig. 1, it is not without its own disadvantages. For example, circuit 100 requires both the A and B signals and their complements as inputs, thus requiring an inverter stage between NMOS transistors 120, 122 and NMOS transistors 124, 126. This, in turn, adds delay to the circuit and doubles interconnect routing as the inverted signals are fed to their corresponding inputs. Also, there must be as many serially coupled NMOS transistors coupled to node 150 as there are inputs, thus providing further delay in the circuit operation. Furthermore, circuit 100 relies on NMOS transistors 120, 122 to overcome any current flow from PMOS transistor 104 to pull ( A+B ) output line 144 low and change the existing state of the circuit when PMOS transistor 104 is conducting and PMOS transistor 146 is nonconducting. Similarly, NMOS transistors 124 and 126 must overcome any current flow from PMOS transistor 108 to pull (A+B) output line 152 low and change the existing state of the circuit when PMOS transistor 104 is nonconducting and PMOS transistor 146 is conducting. The fight between the PMOS transistors attempting to pull up their respective nodes and the NMOS transistors attempting to pull down their respective nodes prevents the circuit from responding quickly to input signal transitions. Thus, on the one hand, one cannot size PMOS transistors 104 and 108 too large or else they may prevent NMOS transistors 120 and 122 or NMOS transistors 124 and 126 from performing their function. On the other hand, PMOS transistors 104 and 108 cannot be sized too small or else any high signal on ( A+B ) output line 144 or (A+B) output line 152 will take too long to generate. A circuit similar to the one shown in Fig.2 is also known from EP-A-0 440 514 Fig. 3 is a schematic diagram of a circuit 200 also known from EP-A-0 647 029 which attempts to overcome some of the problems of circuit 100 showr in Fig. 2. Circuit 200 is an improvement of circuit 100, and the components which remain the same are numbered identically. Briefly, circuit 200 is the same as circuit 100 with the addition of NMOS transistors 204, 208, 212 and 216. The complement of the A input signal is applied to a gate terminal 220 of NMOS transistor 204, the complement of the B input signal is applied to a gate terminal 224 of NMOS transistor 208, the A input signal is applied to a gate terminal 228 of NMOS transistor 212, and the- & input signal is applied to a gate terminal 232 of NMOS transistor 216 for reasons discussed below. A drain terminal 236 of NMOS transistor 204 is coupled to V DD , and a source terminal 240 of NMOS transistor 204 is coupled to a drain terminal 242 of NMOS transistor 208 at a node 244. A source terminal 248 of NMOS transistor 208 is coupled to ( A+B ) output line 144 at a node 250. Drain terminals 254, 256 of NMOS transistors 228, 232, respectively, are coupled to V DD , and source terminals 258 and 260 of NMOS transistors 212, 216, respectively, are coupled to ( A+B ) output line 152 at respective nodes 262 and 264. If A or B is high, then one or both of NMOS transistors 204 or 208 are nonconducting, and ( A+B ) output line 144 is pulled low by whichever NMOS transistor 120 or 122 is conducting at the time. This tends to turn on PMOS transistor 108. At the same time, one or both of NMOS transistors 124 or 126 are nonconducting while one or both of NMOS transistors 212 or 216 are conducting current into (A+B) output line 152, thus aiding PMOS transistor 108 in pulling (A+B) output line 152 high. On the other hand, if A and B are both low, then NMOS transistors 212, 216 are nonconducting, and (A+B) output line 152 is pulled low by NMOS transistors 124, 126. This tends to turn on PMOS transistor 104. At the same time, NMOS transistors 120, 122 are nonconducting, while NMOS transistors 204, 208 conduct current into ( A+B ) output line 152, thus aiding PMOS transistor 104 in pulling ( A+B ) output line 144 high. While the addition of NMOS transistors 204, 208, 212, and 216 may overcome the sizing limitations of PMOS transistors 104 and 108, they do not eliminate the requirement of generating both the original input signal and its complement, and serially connected NMOS transistors (one per input) must still be coupled to node 150. In fact, circuit 200 exacerbates the problem by adding serially connected NMOS transistors 204, 208 to node 250. Furthermore, the added transistors 204, 208, 212 and 216 consume additional chip area. Figure 4 is a schematic diagram of a dynamic circuit 300 known from EP-A-0 647 029 which attempts to overcome the problems noted in circuits 10, 100 and 200. Circuit 300 comprises a PMOS transistor 304, NMOS transistors 308, 312, 316 and an inverter 320. The A input signal is applied to a gate terminal 324 of NMOS transistor 308, and the B input signal is applied to a gate terminal 328 of NMOS transistor 312. A precharge signal is applied to a gate terminal 332 of PMOS transistor 304 and to a gate terminal 336 of NMOS transistor 316. A source terminal 340 of PMOS transistor 304 is coupled to V DD , and a drain terminal 344 of PMOS transistor 304 is coupled to an input terminal 348 of inverter 320 at a node 352. An output terminal of inverter 320 functions as an (A+B) output line 356. Drain terminals 360, 364 of NMOS transistors 308, 312, respectively, are coupled to node 352, and source terminals 368, 372 of NMOS transistors 308, 312 are coupled to a drain terminal 376 of NMOS transistor 316 at a node 380. A source terminal 384 of NMOS transistor 316 is coupled to a ground potential. In operation, a low signal is applied to gate 332 of PMOS transistor 304 and to gate terminal 336 of NMOS transistor 316 during a precharge cycle, thus rendering PMOS transistor 304 conductive while rendering NMOS transistor 316 non-conductive. This, in turn, allows node 352 to be precharged to a high potential regardless of the state of the A and B input signals applied to gate terminals 324, 328 of NMOS transistors 308, 312, respectively. Thereafter, a high signal is applied to gate 332 of PMOS transistor 304 and to gate terminal 336 of NMOS transistor 316 during an evaluate cycle, thus rendering PMOS transistor non-conductive and rendering NMOS transistor conductive. If one or both of the A or B signals are high, then one or both of NMOS transistors 308 or 312 are rendered conductive, thus pulling node 352 low, which results in a high signal on (A+B) output line 356. On the other hand, if both A and B are low, then NMOS transistors 308 and 312 remain non-conductive, node 352 remains at a high potential, and a low signal remains on (A+B) output line 356. While circuit 300 overcomes some of the problems of the previous discussed circuits, such as one set of transistors attempting to overcome the operation of another set of transistors, it too has disadvantages. For example, Fig. 5 (known from EP-A-0 647 029) shows a series of NMOS transistors 410A, 410B, ..., 410N, each having their drain terminals 412A, 412B, ..., 412N coupled to an input terminal 414 of an inverter 416 at respective nodes 418A, 418B, ..., 418N. Source terminals 420A, 420B, ..., 420N are coupled to a ground potential or to some other current sink. A precharge circuit 424 is coupled to input terminal 414 at a node 426 for precharging input terminal 414 to a high potential as with input terminal 348 of circuit 300. As is known in the art, inverter 416 has a capacitance 430 associated with it, and each NMOS transistor 410A, 410B, ..., 410N has respective capacitances 434A, 434B, ..., 434N associated with it. When the number of NMOS transistors are small, then capacitance 430 associated with inverter 416 is the primary capacitance in the system and it is easily precharged by precharge circuit 424 and discharged by the NMOS transistors. However, as the number of NMOS transistors become large, the aggregate capacitances associated with the plurality of NMOS transistors becomes so large that it becomes the dominant capacitance and degrades performance to an unacceptable level as individual NMOS transistors attempt to discharge the very large capacitance. The problem cannot be solved by increasing the size of the NMOS transistors, because then the associated capacitances also increase. Known from US-A-4 692 639 is a CMOS type programmable logic array comprising a regenerative strobe circuit with an output node, a first transistor connected between said output node and a first potential level, a second transistor having a source connected to said first potential level, and a gate connected to a strobe signal, a third transistor connected between a gate of said first transistor and a second potential level, with a gate of said third transistor connected to a signal related to said strobe signal and a complementary transistor inverter connected between said second transistor and said second potential level, the complementary transistor inverter having common gates connected to said output node, and common drains connected to said gate of said first transistor. The invention is defined in claim 1. It is directed to a family of high-speed, compact logic gates which lends itself well to more complex logic. The circuit accommodates any number of inputs while minimizing size or delay through the circuit. In one embodiment of the present invention, a first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first circuit node is at a first voltage potential and a second circuit node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second circuit nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transition at the first and second circuit nodes toward final values, and maintains the first and second circuit nodes at their final voltage potentials for implementing a desired Boolean function. An initializing circuit (hereinafter also referred to as biasing or precharge circuit) is coupled to the first and second circuit nodes for initializing the first and second circuit node. A potential altering circuit is coupled to the first and second circuit nodes for selectively altering the voltage potential at the first and second circuit nodes. When the voltage potential at the first and second circuit nodes are altered, the first and second transistors become conductive and accelerate the voltage transition at the first and second circuit nodes toward their final values. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption. The circuit according to the present invention may be employed in a number of logic applications such as simple OR/NOR or AND/NAND circuits, generalized parallel/serial logic networks, comparators, etc.. When employed in a chain, such as in a generalized parallel/serial logic network, NMOS circuit elements may be employed together with gate coupling circuitry to ensure high speed operation with minimum size. Figures 1-4 are schematic diagrams showing alternative embodiments of prior art circuits for implementing a Boolean function; Figure 5 is a schematic diagram of a known comparator circuit; Figure 6 is a schematic diagram of a known logic circuit for implementing an OR/NOR function; Figure 7 is a schematic diagram of a known logic circuit for implementing an AND/NAND function; Figure 8 is a schematic diagram of known a comparator ; Figure 9 is a schematic diagram of an alternative embodiment of the circuit shown in Fig. 6; Figure 10 is a schematic diagram of the circuit shown in Fig. 6 including a particular embodiment of a precharge circuit according to the present invention; Figure 11 is a schematic diagram of an alternative embodiment of the circuit shown in Fig. 10; Figure 12 is a schematic diagram of a particular embodiment of a parallel/serial logic network Figure 13 is a schematic diagram showing a current path in the circuit of Fig. 12; Figure 14 is a schematic diagram of an alternative embodiment of the circuit shown in Fig. 12; and Figure 15 is a schematic diagram showing a current path in the circuit of Fig. 14. Figure 6 is a schematic diagram of a logic circuit 500 known from EP-A-0 647 029 for implementing an OR/NOR function. Circuit 500 comprises a PMOS transistor 502 and an NMOS transistor 504. Circuit 500 also comprises NMOS transistors 506, 508, 510 and 512. An A input signal is applied to gate terminals 514, 515 of NMOS transistors 506, 510 respectively, and a B input signal is applied to gate terminals 516, 517 of NMOS transistors 508, 512, respectively. PMOS transistor 502 has a source terminal 520 coupled to a high voltage potential and a drain terminal 524 coupled to an (A+B) output line 526 at a node 528. NMOS transistor 504 has a source terminal 532 coupled to a low voltage potential and a drain terminal 536 coupled to an ( A+B ) output line 540 at a node 544. As used herein, a high voltage potential may be any potential above the voltage threshold of the transistor to which it is coupled to and may be, for example, V DD . A low voltage potential may be any voltage potential below the voltage threshold of the transistor to which it is connected and may be, for example, a ground potential. A gate terminal 548 of PMOS transistor 502 is coupled to node 544, and a gate terminal 552 of NMOS transistor 504 is coupled to node 528. NMOS transistors 506, 508 each have source terminals 560, 562, respectively, coupled to (A+B) output line 526 at respective nodes 564 and 528, and drain terminals 570, 572 coupled to the high voltage potential. NMOS transistors 510 and 512 each have drain terminals 574, 578, respectively, coupled to ( A+B ) output line 540 at respective nodes 544 and 580, and source terminals 584 and 588 coupled to the low voltage potential. A precharge or initializing circuit 592 is coupled to node 528 through a line 593 for initializing node 528 to a low voltage potential, and a precharge circuit 595 is coupled to node 544 through a line 596 for initializing node 544 to a high voltage potential. If desired, a transistor may be coupled in series with NMOS transistors 506, 508, 510 and 512 much like NMOS transistor 316 in Fig. 4 to guarantee the integrity of the precharge operation. In operation precharge circuit 592 initializes node 528 to a low voltage potential, and precharge circuit 595 initializes node 544 to a high voltage potential during a precharge cycle. Thereafter, NMOS transistors 506, 508, 510 and 512 are selectively rendered conductive during an evaluate cycle by the A and B input signals applied to their respective gates. If one or both of the A and B signals are high, then one or both of NMOS transistors 506 or 508 are rendered conductive, and one or both of NMOS transistors 510 and 512 are rendered conductive. As a result, the voltage potential at node 528 rises, and the voltage potential at node 544 falls. When the potential at node 528 rises to the threshold voltage of NMOS transistor 504, then NMOS transistor 504 begins conducting and accelerates ( A+B ) output line 540 to a low voltage potential. Similarly, when the voltage at node 544 falls to the voltage threshold of PMOS transistor 502, then PMOS transistor 502 begins conducting and accelerates (A+B) output line 526 to a high voltage potential . The resulting signals at nodes 528 and 544 latch PMOS transistor 502 and NMOS transistor 504 in a conducting state and maintains nodes 528 and 544 in their final high and low states, respectively. It should be noted that circuit 500 operates by turning on both PMOS transistor 502 and NMOS transistor 504 from an initial non-conductive state. Once the threshold voltage of PMOS transistor 502 and NMOS transistor 504 is reached, PMOS transistor 502 and NMOS transistor 504 are essentially decoupled from NMOS transistors 506, 508, 510 and 512 and work independently of those transistors. Since NMOS transistors 506, 508, 510 and 512 do not have to overcome current flow from either PMOS transistor 502 or NMOS transistor 504, PMOS transistor 502 and NMOS transistor 504 may be fabricated in any desired size. For example, PMOS transistor 502 and NMOS transistor 504 may be sized large enough to overcome self-loading of a circuit having a large number of input transistors. Additionally, all the input transistors are coupled in parallel, so the delay inherent in the serially coupled transistors of prior art circuits is eliminated. Finally, since the circuit changes state simply by charging node 528 and discharging node 544, very little net current flows through the circuit, thus making the circuit very efficient. Figure 7 is a schematic diagram of a logic circuit 600 known from EP-A-0 647 029 for implementing an AND/NAND function. The circuit elements which are the same as OR/NOR circuit 500 are labeled the same. From inspection, it is readily apparent that the circuit is constructed the same, except the complement of the A and B input signals are used (because a NAND gate is the same as an OR gate with inverted inputs). The circuit operates the same as circuit 500 except ( A*B ) appears on line 526 and (A*B) appears on line 540. Figure 8 is a schematic diagram of a circuit 600 known from EP-A-0 647 029 which avoids the problem of self-loading experienced with the circuit shown in Fig. 5. Circuit 600 includes a plurality of NMOS transistors 610A, 610B, ..., 610N, each having their drain terminals 612A, 612B, ..., 612N coupled to a line 614 at respective nodes 616A, 616B, ..., 616N, their source terminals 618A, 618B, ..., 618N coupled to a low voltage potential, and their gate terminals 619A, 619B, ..., 619N coupled to respective signal lines 621A, 621B, ..., 621N at respective nodes 623A, 623B, .., 623N. A plurality of NMOS transistors 620A, 620B, ..., 620N have their drain terminals 622A, 622B, ..., 622N coupled to a high voltage potential, their source terminals 624A, 624B, ..., 624N coupled to a line 625 at respective nodes 626A, 626B, ..., 626N, and their gate terminals 627A, 627B, ..., 627N coupled to nodes 623A, 623B, ..., 623N, respectively. An NMOS transistor 630 has a drain terminal 634 coupled to line 614 and to a gate terminal 636 of a PMOS transistor 638 at a node 640. A PMOS transistor 638 has a drain terminal 642 coupled to line 625 and to a gate terminal 644 of NMOS transistor 630 at a node 648. A source terminal 650 of NMOS transistor 630 is coupled to a low voltage potential, and a source terminal 652 of PMOS transistor 638 is coupled to a high voltage potential. A precharge circuit 660 has a first precharge line 664 coupled to node 640 and a second precharge line 668 coupled to node 648. In operation, precharge circuit 660 precharges node 640 to a high voltage potential and precharges node 648 to a low voltage potential during the precharge cycle. If one or more of the signals on lines 621A, 621B, ..., 621N is high, then the NMOS transistors to which they are attached begin conducting. Consequently, the voltage at node 640 falls, and the voltage at node 648 rises. When the voltage at node 640 falls to the threshold voltage of PMOS transistor 638, then PMOS transistor 638 begins conducting and accelerates node 64 to a high voltage potential. Similarly, when the voltage at node 648 rises to the threshold voltage of NMOS transistor 630, then NMOS transistor begins conducting and accelerates node 640 to a low voltage potential. The resulting signals a nodes 640 and 648 latch NMOS transistor 630 and PMOS transistor 638 in a conducting state and maintains nodes 640 and 648 at their final low and high states, respectively. Figure 9 is a schematic diagram of a circuit 500A known from EP-A-0 647 029 similar to circuit 500 shown in Fig. 6. The only difference is the substitution of PMOS transistors 700 and 704 for NMOS transistors 506 and 508, respectively. Gate terminals 708, 710 receive the complements of the A and B input signals, respectively. The circuit operates in the same manner as circuit 500 in Fig. 6. Figure 10 is a schematic diagram of the circuit shown in Fig. 6 including a particular embodiment of circuitry 700 for initializing nodes 528 and 544 according to the present invention. Circuitry 700 includes inverters 704, 708, NMOS transistors 712, 716, and PMOS transistors 720, 724. Clock signal CLK is communicated to an input terminal 728 of inverter 704. An output terminal 732 of inverter 704 is coupled to an input terminal 736 of inverter 708, to a gate terminal 740 of NMOS transistor 712, and to a gate terminal 744 of PMOS transistor 720. A source terminal 746 of NMOS transistor 712 is coupled to a low voltage potential, and a drain terminal 750 of NMOS transistor 712 is coupled to line 593. A source terminal 754 of PMOS transistor 720 is coupled to a high voltage potential, and a drain terminal 758 of PMOS transistor 720 is coupled to source terminal 520 of PMOS transistor 502. An output terminal 762 of inverter 708 is coupled to a gate terminal 766 of NMOS transistor 716 and to a gate terminal 770 of PMOS transistor 724. A source terminal 774 of NMOS transistor 716 is coupled to a low voltage potential, and a drain terminal 778 of NMOS transistor 716 is coupled to source terminal 532 of NMOS transistor 504. A source terminal 782 of PMOS transistor 724 is coupled to a high voltage potential, and a drain terminal 784 of PMOS transistor 724 is coupled to line 596. During the precharge cycle, NMOS transistor 712 and PMOS transistor 724 become conductive for initializing their corresponding nodes 528 and 544 to their low and high voltage potentials, respectively. At the same time, PMOS transistor 720 and NMOS transistor 716 become nonconductive for inhibiting current flow through PMOS transistor 502 and NMOS transistor 504, respectively. Since no current can flow through PMOS transistor 502 and NMOS transistor 504 at this time, NMOS transistor 712 and PMOS transistor 724 quickly establish the proper potentials at their respective nodes with minimal power loss. Without some method for inhibiting current flow through PMOS transistor 502 and NMOS transistor 504, NMOS transistor 712 and PMOS transistor 724 would have to draw more current than PMOS transistor 502 and NMOS transistor 504 to overcome their conductive states. NMOS transistor 712 and PMOS transistor would then have to be made very large, and excessive power consumption would result. By using the teachings of the present invention, NMOS transistors 712, 716 and PMOS transistors 720, 724 may be made very small, and power consumption is minimized. Figure 11 is a schematic diagram of an alternative embodiment of the circuit shown in Fig. 10, including circuitry 700A for initializing nodes 528 and 544. In this embodiment, PMOS transistor 720 and NMOS transistor 716 are eliminated. In their place, source terminal 532 of PMOS transistor 502 is coupled to output terminal 762 of inverter 708, and source terminal 532 of NMOS transistor 504 is coupled to output terminal 732 of inverter 704. Circuit 700A also operates to inhibit current flow through PMOS transistor 502 and NMOS transistor 504 during the precharge cycle, but more efficiently than using the serially connected PMOS transistor 720 and NMOS transistor 716 as in Fig. 10. Figure 12 is a schematic diagram of a particular embodiment of a parallel/serial logic network 800. Network 800 performs the functions F_H = (W 0 + W 1 + ... + W k ) (X 0 + X 1 + ... + X m ) ... (Z 0 + Z 1 + ... + Z n ) and F_L = (NOT F_H) = (W 0 W 1 ...W k ) + (X 0 X 1 ...X m ) + (Z 0 Z 1 ...Z n ). Signals (W 0 , X 0 , ..., Z 0 ) are coupled to gate terminals 804(W-Z) of respective PMOS transistors 808(W-Z); signals (W 1 , X 1 , ..., Z 1 ) are coupled to gate terminals 812(W-Z) of respective PMOS transistors 816(W-Z); and signals (W k , X m , ..., Z n ) are coupled to gate terminals 820(W-Z) of respective PMOS transistors 824(W-Z). Source terminals 826WS of PMOS transistors 808W, 816W, ..., and 824W are coupled to a high voltage potential (e.g., VDD). Drain terminals 826WD of PMOS transistors 808W, 816W, ..., and 824W are coupled to source terminals 826XS of PMOS transistors 808X, 816X, ..., and 824X. In general, the drain terminals of each PMOS transistor in the chain is coupled to the source terminal of the succeeding PMOS transistor in the chain and to node 528 of its corresponding circuit 500. Drain terminals 826ZD of PMOS transistors 808Z, 816Z, ..., and 824Z are coupled to an input terminal 850 of an inverter 854 and to node 528 of the last circuit 500 in the chain. An output terminal 856 of inverter 854 provides the F_L signal. Similarly, signals (W 0 , X 0 , ..., Z 0 ) are coupled to gate terminals 828(W-Z) of respective PMOS transistors 832(W-Z); signals (W 1 , X 1 , ..., Z 1 ) are coupled to gate terminals 836(W-Z) of respective PMOS transistors 840(W-Z); and signals (W k , X m , ..., Z n ) are coupled to gate terminals 844(W-Z) of respective PMOS transistors 848(W-Z). Source terminals 866WS of PMOS transistors 832W, 840W, ..., and 848W are coupled to a low voltage potential (e.g., ground). Drain terminals 866WD of PMOS transistors 832W, 840W, ..., and 848W are coupled to source terminals 866XS of PMOS transistors 832X, 840X, ..., and 848X. In general, the drain terminals of each PMOS transistor in the chain is coupled to the source terminal of the succeeding PMOS transistor in the chain and to node 544 of its corresponding circuit 500. Drain terminals 866ZD of PMOS transistors 832Z, 840Z, ..., and 848Z are coupled to an input terminal 870 of an inverter 874 and to node 544 of the last circuit 500 in the chain. An output terminal 876 of inverter 874 provides the F_H signal. From inspection of Fig. 12 it is apparent that at least one transistor in each stage must be rendered conductive in order to change the signal at the output terminals of inverters 854 and 874. For example, if nodes 528 of each circuit 500 are initialized to a low potential, then if PMOS transistors 808W, 816X, ..., and 824Z are rendered conductive, then a current path forms to charge nodes 528 high, and a low signal appears at the output terminal 856 of inverter 854. Of course, NMOS transistors 832W, 840X, ..., and 848Z would also be rendered conductive for producing a high signal at the output terminal 876 of inverter 874. The equivalent circuit, using PMOS transistors 808W, 816X, ..., and 824Z is shown in Fig. 13 (where the high signal is assumed to be Vdd and the low signal is assumed to be ground). For size and speed considerations, it would be desirable to replace the PMOS transistors in each switching stage with NMOS transistors as shown in Fig. 14 to produce a circuit 800A. In circuit 800A, the PMOS transistors have been replaced by NMOS transistors 908(W-Z), 916(W-Z), and 924(W-Z). Since NMOS transistors are being used, complements of the original input signals are not necessary. In addition, NMOS transistors 930 are coupled to the gate terminals of each NMOS transistor 908(W-Z), 916(W-Z), ..., and 924(W-Z). The reason for this is as follows. Figure 15 is a schematic diagram showing a current path in circuit 800A when NMOS transistors 908W, 916X, ..., and 924Z are rendered conductive. Assume the high signal is equal to VDD. Each NMOS transistor attempts to pull its corresponding node high, but the VDD signal drops by VT at each node. This signal degradation is unacceptable in most applications. By adding transistors 930, the signal at the gate terminal of each transistor 908W, 916X, ..., and 924Z is allowed to float, and gate coupling increases the signal at each node. For example, if gate coupling causes the signal at gate terminal 904W to rise to VDD + 1/2 VDD, then the signal at node 950 rises to VDD-VT+1/2VDD. This causes the next NMOS transistor in the chain to become strongly conductive, increasing both speed and signal strength (as a result of further gate coupling in each transistor) as the signal ripples through the chain.

Claims: An electronic circuit comprising: a first and a second input node for receiving a first and a second input signal (A, B, A , B ), respectively; a first and a second output node for providing a first and a second output signal (A+B, A+B ; A*B, A*B ), respectively; a dock input node for receiving a clock signal (CLK) defining a precharge and an evaluation period; a first transistor (502) having a gate terminal (548) connected to a drain terminal (536) of a second transistor (504) at a first circuit node (544) and having a drain terminal (524) connected to a gate terminal (552) of the second transistor (504) at a second circuit node (528), the first and second circuit nodes (544, 528) coupled to the first and second output nodes, respectively, and the first and second transistors (502, 504) being of complementary type; initializing circuitry (592, 595) coupled to the clock input node, to the first circuit node (544) and to the second circuit node (528) for biasing, during the precharge period, the first circuit node (544) to a first voltage potential and the second circuit node (528) to a second voltage potential, the first and second voltage potentials being different; potential altering circuitry (506, 508, 510, 512) coupled to the first circuit node (544), to the second circuit node (528) and to the input nodes, for biasing, during the evaluation period, said first and second transistors (502, 504) to a conductive state by altering the voltage potential at the first circuit node (544) from the first voltage potential to the second voltage potential in response to the input signals (A, B, A , B ) and by altering the voltage potential at the second circuit node (528) from the second voltage potential to the first voltage potential in response to the input signals (A, B, A , B ); characterized by current inhibiting circuitry coupled to the clock input node and connected to a source terminal (520) of the first transistor (502) and to a source terminal (532) of the second transistor (504) for inhibiting current flow through said first and second transistors (502, 504) during the precharge period. The circuit according to claim 1, characterized in that the current inhibiting circuitry includes means for coupling the source terminal (520) of the first transistor (502) to a third voltage potential when the initializing circuitry (592, 595) is biasing the first circuit node (544) to the first voltage potential and for coupling the source terminal (532) of the second transistor (504) to a fourth voltage potential when the second circuit node (528) is being biased to the second voltage potential. The circuit according to claim 2, characterized in that the first voltage potential is equal to the third voltage potential, and in that the second voltage potential is equal to the fourth voltage potential. The circuit according to claim 2, characterized in that the initializing circuitry (700; 700A) comprises: a first initializing transistor (724) having a gate terminal (770) and a source terminal (784) coupled to the first circuit node (544); a second initializing transistor (712) having a gate terminal (740) and a source terminal (750) coupled to the second circuit node (528); means, coupled to the source terminal (520) of the first transistor (502) and to the gate terminal (770) of the first initializing transistor (724), for applying the third voltage potential to the source terminal (520) of the first transistor (502) and to the gate terminal (770) of the first initializing transistor (724) when the first circuit node (544) is being biased to the first voltage potential; and means, coupled to the source terminal (532) of the second transistor (504) and to the gate terminal (740) of the second initializing transistor (712), for applying the fourth voltage potential to the source terminal (532) of the second transistor (504) and to the gate terminal (740) of the second initializing transistor (712) when the second circuit node (528) is being biased to the second voltage potential. The circuit according to claim 4, characterized in that the first voltage potential is equal to the third voltage potential, and in that the second voltage potential is equal to the fourth voltage potential.

Inventors: DRAPER DONALD A, PARTOVI HAMID, DRAPER, DONALD A., PARTOVI, HAMID
Applicants: INTERGRAPH CORP, INTERGRAPH CORPORATION
Application year: 1994
Main classification: H03K19
IPC codes: H03K19