Improvements in video data formatters

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j). One of each channel signal processors (22a) through (22d) may be coupled to two of first in-first out buffer memories (34a) through (34j). Additionally, each formatter (24a) through (24c) may comprise channel data format units (38a) through (38d), each associated with a channel of, for example, display (24a). Channel data format units (38a) through (38d) are coupled to appropriate of first in-first out buffer memories (34a) through (34j) via multiplexers (36a) through (36d). Each formatter (24a) through (24c) may remove overlap between channels of system (10) and may format the processed video signal into appropriate channels for displays (26a) through (26c).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to the field of electronic devices. More particularly, this invention relates to video data formatter for a digital television system. A digital television system is described in European Patent Application No. 94116984, published as EP-A-0 651 577 and assigned to Texas Instruments Incorporated. SUMMARY OF THE INVENTION In designing the digital television system a heretofore unrecognized problem was discovered. The digital television system may comprise a plurality of processing channels each containing a predetermined number of pixels. Each channel may overlap by, for example, one to five pixels with an adjacent channel for processing purposes. Additionally, the display of the digital television system may have a number of channels having a different pixel width from the processing channels such that the channels of the display are incompatible with the processing channels. The teachings of the present invention relate to a system and method for formatting video data for a digital display of a digital television system. More specifically, the present invention provides a video data formatter having a plurality of input channels, comprising the features of claim 1. The invention further provides a method of formatting video data comprising the steps of claim 13. It is a technical advantage of the present invention to provide a video data formatter for a digital television system that removes overlap between adjacent channels before a processed video signal is displayed. The digital television system processes a video signal in a plurality of parallel channels. The channels of the system may correspond to vertical strips of a video frame. Each channel may contain an overlap of, for example, one to five pixels with an adjacent channel. The overlap between channels may allow horizontal processing of pixels on the end of a channel. The overlapping pixels may be removed before the processed video signal is displayed such that redundant pixels are not displayed. It is another technical advantage of the present invention to reformat the processed video data for a display. The display may have a plurality of associated channels that differ in pixel width from the processing channels. The processing channels may be altered to match the pixel without the channels of the display. It is another technical advantage of the present invention to provide one bit plane of data for each bit of video data associated with a pixel to a display of a digital television system. The display may provide 2 x intensity levels for each video signal in response to the bit planes formed from the video data wherein X is the number of bits for each pixel. The first bit plane, corresponding to the most significant bit for each pixel, may control the display for one-half of the time for one frame. Successive bit planes may each control the display for a period of time proportionate to the position of the bits of that bit plane in the pixels making up that bit plane. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein: FIGURE 1 illustrates a digital television system constructing according to the teachings of the present invention; FIGURE 2 illustrates four vertical strips created by the system of FIGURE 1; FIGURE 3 illustrates the overlap in pixels between adjacent channels created by the system of FIGURE 1; FIGURE 4 illustrates an embodiment of a formatter of FIGURE 1 constructed to the teachings of the present invention; FIGURE 5 illustrates a formatter constructed according to the teachings of the present invention; FIGURE 6 is a timing diagram that illustrates how data is stored in the formatter of FIGURE 5 for a system comprising four processing channels; FIGURE 7 is a timing diagram that illustrates how data stored according to the timing diagram of FIGURE 6 is formatted for channels of a display of FIGURE 1; FIGURE 8 is a timing diagram that illustrates how data is stored in the formatter of FIGURE 5 for a system comprising five processing channels; FIGURE 9 is a timing diagram that illustrates how data stored according to the timing diagram of FIGURE 8 is formatted for channels of a display of FIGURE 1; FIGURE 10 illustrates an embodiment of a channel data format unit of FIGURE 5 constructed according to the teachings of the present invention; FIGURE 11 illustrates another embodiment of a formatter constructed according to the teachings of the present invention; and FIGURE 12 illustrates another embodiment of a formatter constructed according to the teachings of the present invention. DETAILED DESCRIPTION OF THE INVENTION FIGURE 1 illustrates a digital television system indicated generally at 10 and constructed according to the teachings of the present invention. System 10 comprises a parallel architecture wherein input video signals may be divided into channels to be processed in parallel. For example, system 10 may implement appropriate functions such that a standard video signal may be used to provide a high definition video display. Alternatively, system 10 may sample and display a high definition video signal. System 10 may receive video signals in composite or component form. For example, system 10 may receive an analog composite video signal, an analog video signal in component form, or a digital video signal. System 10 may convert a composite video signal into a plurality of video signals for processing. For example, an analog composite video signal in the format established by the National Television Standards Committee (hereinafter "NTSC") may be separated into a luminance signal, identified by the symbol Y, and two color difference signals, identified by the symbols I and Q. Alternatively, system 10 may separate other standard composite video signals into appropriate video signals for processing according to Table 1 below. Input Video Format Color Space Domain NTSC Y, I, Q PAL and SECAM Y, U, V SMPTE 240M, SMPTE 260M Y, Pr, Pb It is noted that the other standard video formats include: Phase Alternating Line, hereinafter "PAL"; Sequential Color with Memory, hereinafter "SECAM"; and Society of Motion Picture Engineers, hereinafter "SMPTE". Each of these standard video signals comprise a luminance signal, hereinafter "luma" or "Y", and a chrominance signal, hereinafter "chroma" or "C". The chroma signal may be further divided into appropriate color difference signals as shown in Table 1. For clarity, each of the standard video signals may hereinafter be referred to as providing a video signal in a "color difference color space" or a "Y-I-Q color space." As an alternative to the standard video signals of Table 1, a video source may be coupled to system 10 to provide a red video signal, hereinafter "R", a green video signal, hereinafter "G", and a blue video signal, hereinafter "B". Such a video source may hereinafter be refereed to as providing a video signal in an "R-G-B color space." System 10 prepares a video signal for parallel processing in receiving circuitry 12, and line slicer 14. Receiving circuitry 12 may receive, for example, a composite video signal in the NTSC format from an external source (not explicitly shown). Alternatively, receiving circuitry 12 may receive separate Y and C video signals. Furthermore, receiving circuitry 12 may receive separate video signals in an R-G-B color space. The format of the video signal is indicated to receiving circuitry 12 by a mode select input. Receiving circuitry 12 comprises composite video interface and separation circuit 16 coupled to analog to digital converter circuit 18. Composite video interface and separation circuit 16 may separate a composite video signal into, for example, three separate video signals. Analog to digital converter circuit 18 may convert each of the separate video signals into ten bit digital video signals. Analog to digital converter circuit 18 of receiving circuitry 12 is coupled to provide three ten bit digital video signals to line slicer 14. Additionally, a digital video signal may be coupled directly to line slicer 14. Line slicer 14 divides each digital video signal into a plurality of separate channels for each line of composite video signal. For example, line slicer 14 may divide each digital video signal into four, five or another appropriate number of channels. The number of channels may depend on the number of pixels in a line of video signal, and the number of pixels that may be simultaneously processed by a video signal processor of system 10. Line slicer 14 may provide appropriate overlap between the various channels for processing as described below. System 10 processes the digital video signals in processing circuitry 20. Processing circuitry 20 is coupled to line slicer 14. Processing circuitry 20 comprises a plurality of channel signal processors 22a through 22d. The number of channel signal processors 22 may be equal to the number of channels provided by line slicer 14. Each channel signal processor 22a through 22d receives all three 10 bit digital video signals for the channel corresponding to that signal processor 22a through 22d. Processing circuitry 20 may convert each line of digital video signal into two lines of digital video signal output. Each channel signal processor 22a through 22d, therefore, may have six separate outputs, for example, two ten bit red outputs, two ten bit green outputs, and two ten bit blue outputs. Additionally, processing circuitry 20 may perform the following functions: color space conversion, gamma correction, and picture quality control. System 10 reconnects and displays the processed video data. A plurality of formatters 24a through 24c reconnect the video data and a plurality of displays 26a through 26c display the video data. One formatter 24a through 24c and one display 26a through 26c operate on a different digital video signal as indicated in FIGURE 1. For example, formatter 24a and display 26a may operate on a red video signal. Formatter 24b and display 26b may operate on a green video signal. Finally, formatter 24c and display 26c may operate on a blue video signal. Two ten bit outputs of each channel signal processor 22a through 22d are coupled to an appropriate formatter 24a through 24c. Formatters 24a through 24c remove overlap between adjacent channels, reconnect the channels, and prepare the reconnected digital video signals for display on displays 26a through 26c. Formatters 24a through 24c each provide 128 bit words in four 32 bit channels to displays 26a through 26c. Displays 26a through 26c may comprise, for example, a Spatial Light Modulator (hereinafter "SLM") such as a 2 x 128 pin Digital Micromirror Device (hereinafter "DMD") produced by TEXAS INSTRUMENTS INCORPORATED. However, displays 26a through 26c are not limited to digital displays. It is within the scope of the teachings of the present invention for the processed video signal to be displayed on an analog display. Timing and control circuit 28 is coupled to composite video interface and separation circuit 16, analog to digital converter circuit 18, line slicer 14, processing circuitry 20, formatters 24a through 24c, and displays 26a through 26c. Timing and control circuit 28 is operable to control the timing of each aspect of system 10. The timing of system 10 may be accomplished through use of a synchronization (hereinafter "sync") signal supplied to timing and control circuit 28 by composite video interface and separation circuit 16. Additionally, timing and control circuit 28 is operable to accept user inputs to control the timing of various functions of system 10. In operation, system 10 may prepare a standard video signal to produce a high definition display. As described previously, system 10 may receive analog or digital video signals in composite or separated form. For conciseness, the operation of system 10 is described in conjunction with receiving an analog composite video signal. System 10 separates a composite video signal into video signals, divides the video signals into a plurality of channels, and processes the channels in parallel. An advantage of using a parallel architecture in system 10 is that system 10 is able to process the video signals at a low speed while providing a high definition display. Consequently, system 10 may incorporate existing video processor components. Composite video interface and separation circuit 16 separates the composite video signal into, for example, three separate video signals. Composite video interface and separation circuit 16 may, for example, separate a composite video signal into Y, I, and Q video signals of the NTSC standard. Analog to digital converter circuit 18 may sample each video signal at a frequency of, for example, 71.1 MHz. The appropriate sampling rate may depend on the number of pixels allocated for a line of video on displays 26a through 26c, and the time for one line of video signal to be received by receiving circuitry 12. Therefore, the sampling rate may be adjusted to create a predetermined number of pixels for each line of video signal. Analog to digital converter circuit 18 may comprise, for example, Analog to Digital Converter board AD9060 produced by ANALOG DEVICES. Alternatively, analog to digital converter circuit 18 may comprise another appropriate analog to digital converter device operable to sample data at an appropriate sampling rate on the order of 75 MHz. Line slicer 14 divides each digital video signal into a plurality of separate channels for each line of video signal. For example, line slicer 14 may divide each line of the digital video signal into four channels so that the video signal may be processed in parallel. By dividing each line of digital video signal in the same manner, each channel signal processor 22a through 22d effectively processes one vertical strip of each video frame. FIGURE 2 shows the four vertical strips processed by channel signal processors 22a through 22d for the embodiment of FIGURE 1. Alternatively, line slicer 14 may divide a line on a pixel by pixel basis or line slicer 14 may divide a video frame into horizontal strips. An advantage of dividing a video frame into vertical strips is that the related processing steps performed by processing circuitry 20 are simplified. Additionally, line slicer 14 may provide for overlap between the vertical channels by providing common pixels to adjacent channels as shown in FIGURE 3. The overlap may comprise, for example, from one to five pixels. The overlapping pixels may be used to provide appropriate data for each channel to perform the various functions described below as called for by processing circuitry 20. The amount of overlap between channels may be varied depending of the specific functions implemented in processing circuitry 20. System 10 processes the digital video signals in processing circuitry 20. Processing circuitry 20 may perform the progressive scan function (hereinafter "proscan"). Proscan "de-interlaces" a video signal by creating an entire video frame from a single or multiple video fields at the field rate. As described previously, a standard video signal may comprise two fields of video data for each frame. Additionally, processing circuitry 20 may convert the digital video signals into a different color space. For example, processing circuitry 20 may convert digital video signals from a color difference color space to an R-G-B color space. Furthermore, processing circuitry may remove a gamma curve from a standard video signal. Finally, processing circuitry 20 may control the quality of a video display in response to user inputs such as inputs for adjustments to brightness, hue, contrast, sharpness and saturation. System 10 reconnects and displays the processed digital video signal using formatters 24a through 24c and displays 26a through 26c. Formatters 24a through 24c remove overlap between adjacent channels. Additionally, formatters 24a through 24c prepare the reconnected digital video signals for display on displays 26a through 26c. For example, formatters 24a through 24c may produce a plurality of bit planes from the reconnected digital video signals. Each bit plane may correspond to a particular bit for each pixel in a particular video frame. In the embodiment of FIGURE 1, formatters 24a through 24c each may produce 10 bit planes of video data for each separate video signal that are to be provided to displays 26a through 26c in 128 bit words. Based on the output of formatters 24a through 24c, displays 26a through 26c may project appropriate images corresponding to the processed video signals on, for example, a screen (not shown). The combination of the different video signals output by displays 26a through 26c result in a single, appropriately colored, image. It should be understood that system 10 may be operable to be programmed to accept any appropriate standard analog or digital video signal. Alternatively, system 10 may be preprogrammed to accept only a limited number of appropriate standard analog or digital video signals. FIGURE 4 illustrates an embodiment of a formatter indicated generally at 24' and constructed according to the teachings of the present invention. One formatter 24' of the type illustrated in FIGURE 4 may be used for each of formatters 24a through 24c of FIGURE 1. For conciseness, formatter 24' will be described in terms of formatter 24a of FIGURE 1. It is understood that formatter 24' is not so limited, but may be used for formatters 24b and 24c as well. Formatter 24' comprises line segment mapper 30 and data format unit 32. Line segment mapper 30 is coupled to two output lines from each channel signal processor 22a through 22d of FIGURE 1. For example, line segment mapper 30 may be coupled to the two output lines corresponding to the red component video signal from each channel signal processor 22a through 22d. Line segment mapper 30 is coupled to provide a number of outputs equal to the number of inputs to data format unit 32. Data format unit 32 provides four 32 bit output signals to display 26a of FIGURE 1. In operation, line segment mapper 30 receives processed video data for one of the component video signals, such as, for example, the red component. The video signals received from channel signal processors 22a through 22d of FIGURE 1 contain some overlap due to the manner in which line slicer 14 divides the input video signals as described previously with respect to FIGURE 1. Line segment mapper 30 operates to remove the overlap in the various channels caused by line slicer 14. Once the overlap has been removed, the video signal is formatted, for example, for display 26a of FIGURE 1 by data format unit 32. For example, data format unit 32 may create a series of bit planes wherein one bit of data in each bit plane corresponds to each pixel of display 26a. Data format unit 32 may provide these bit planes to display 26a in 128 bit words as described below. FIGURE 5 illustrates a formatter indicated generally at 24' and constructed according to the teachings of the present invention. System 10 may comprise one formatter 24' for each formatter 24a through 24c. For conciseness, formatter 24' will only be described with respect to formatter 24a. It is understood that the description of formatter 24' is equally applicable to formatters 24b and 24c. As described previously with respect to FIGURE 1, line slicer 14 may provide, for example, two or three pixels of overlap between adjacent channels for processing circuitry 20. Formatter 24' may be used to remove this overlap such that a line of video displayed on displays 26a through 26c does not display redundant pixels. Additionally, displays 26a through 26c may be divided into a plurality of channels. The pixel width of the channels of displays 26a through 26c may be different from the pixel width of the channels of processing circuitry 20. Formatter 24' may reorganize the channels of processing circuitry 20 of FIGURE 1 to provide an appropriate plurality of channels for displays 26a through 26c of FIGURE 1. Formatter 24' may comprise, for example, line segment mapper 30' and data format unit 32'. Line segment mapper 30' may comprise, for example, a plurality of first in-first out buffer memories 34a through 34j. Formatter 24' may comprise five separate input channels labelled A through E. Input channels A through E of formatter 24' may be coupled to appropriate channels of processing circuitry 20 of FIGURE 1. For example, input channels A, B, D and E may be coupled to channel signal processors 22a through 22d of FIGURE 1 respectively. Alternatively, in an embodiment of processing circuitry 20 comprising five channel signal processors, each channel signal processor may be coupled to an appropriate input channel A, B, C, D or E. Each input channel A through E may be coupled to two first in-first out buffer memories 34a through 34j of line segment mapper 30'. With each channel A through E coupled to two first in-first out buffer memories, line segment mapper 30' may move a plurality of pixels from one end of one input channel to the opposite end of a display channel. In the embodiment of FIGURE 5, input channel A is coupled to first in-first out buffer memories 34a and 34c. Input channel B is coupled to first in-first out buffer memories 34b and 34d. Input channel C is coupled to first in-first out buffer memories 34e and 34f. Input channel D is coupled to first in-first out buffer memories 34g and 34i. Input channel E is coupled to first in-first out buffer memories 34h and 34j. Each input channel A through E may be coupled to two lines of output from processing circuitry 20 of FIGURE 1. Data format unit 32' may comprise a plurality of channels each corresponding to an appropriate channel of display 26a of FIGURE 1. For example, data format unit 32' may be divided into four separate channels to provide four separate 32 bit outputs to display 26a of FIGURE 1. Data format unit 32' may comprise, for example, a plurality of multiplexers 36a through 36d, and a plurality of channel data format units 38a through 38d. Each multiplexer 36a through 36d is associated with an appropriate channel data format unit 38a through 38d. Each multiplexer 36a through 36d comprises three inputs. The inputs of multiplexer 36a are coupled to first in-first out buffer memories 34a and 34b and a constant zero input. Multiplexer 36b is coupled to first in-first out buffer memories 34c through 34e. Multiplexer 36c is coupled to first in-first out buffer memories 34f through 34h. Multiplexer 36d is coupled to first in-first out buffer memories 34i and 34j and a constant zero input. Each multiplexer 36a through 36d is coupled to an appropriate channel data format unit 38a through 38d. It is noted that the embodiment of formatter 24' illustrated in FIGURE 5 may be used in a system having four or five parallel processing channels. However, the teachings of the present invention are not intended to be limited to a system having four or five channels. The teachings of the present invention encompass a system having less than four channels as well as a system having more than five channels. In operation, formatter 24' stores a line of video data in line segment mapper 30'. FIGURE 6 is a timing diagram that illustrates how the data received from the channels of system 10 are stored in first in-first out buffer memories 34a through 34j. The timing provided for by FIGURE 6 allows formatter 24' to remove overlap between adjacent channels and to prepare appropriate channels for display 26a. Each time unit of FIGURE 6 corresponds to the time for storing one pixel of data in a first in-first out buffer memory 34a through 34j. Beginning at a time 1 in FIGURE 6, channels B, D and E each discard the first pixel of video data for their respective channels. The first pixel of each of these channels corresponds to an overlapping pixel as shown in FIGURE 3. At time 1, channel A begins storing pixels in first in-first out buffer memories 34a. At time 2, channels B, D and E each discard the second pixel of their respective channels. At time 3, channels B, D and E each begin storing pixels in first in-first out buffer memories 34d, 34g, and 34h respectively. At time 38, channel E switches to storing pixels in first in-first out buffer memory 34j. Channel E is switched to compensate for differences in pixel width between the channels of processing circuitry 20 and the channels of display 26a. This function allows a portion of channel E to be combined with channel D. At time 442, channel A switches to storing pixels in first in-first out buffer memory 34c to compensate for differences in pixel width between the channels of processing the circuitry 20 and the channels of display 26a. At time 478, channels A, B, D and E stop storing pixels. Thereby, pixels 479 and 480 of each channel are discarded to remove overlap between the channels. At time 480, the period for storing data for a particular line of video signal in line segment mapper 30' terminates. It is noted that the timing shown in FIGURE 6 may be adjusted to control the number of pixels that are removed from the various channels. For example, channel A may begin storing pixels at time 4 thereby removing pixels, 1, 2 and 3. Additionally, the time at which a channel is switched from one buffer memory to another may be altered to provide appropriate channels for display 26a. Thus, the overlapping pixels are removed from channels A through E and channels A through E are prepared to be combined into appropriate channels for display 26a. FIGURE 7 is a timing diagram that illustrates how data is received from first in-first out buffer memories 34a through 34j to create appropriate channels for display 26a. The pixels stored in first in-first out buffer memories 34a through 34j are communicated to channel data format units 38a through 38d by multiplexers 36a through 36d, respectively. Multiplexer 36a provides a constant zero input to channel data format unit 38a from time 1 through time 70. Therefore, the first 70 pixels of each line correspond to a black strip on a first side of a displayed video frame. Multiplexer 36a provides the pixels stored in first in-first out buffer memory 34a to channel data format unit 38a from time 71 through 512 thereby completing a channel of display 26a. Multiplexer 36b provides pixels from channels A and B to channel data format unit 38b. Pixels stored in first in-first out buffer memory 34c from channel A are provided to channel data format unit 38b from time 1 through time 36. Beginning at time 37, pixels stored in first in-first out buffer memory 34d from channel B are provided to channel data format unit 38b. In this manner, pixels from channel A are combined with pixels from channel B to form another channel for display 26a. Multiplexer 36c combines pixels from channel D with pixels from channel E to form another channel for display 26a. Beginning at time 1, multiplexer 36c provides pixels stored in first in-first out buffer memory 34g to channel data format unit 38c. At time 476, multiplexer 36c switches to provide pixels from first in-first out buffer memory 34h channel to data format unit 38c. Multiplexer 36d provides pixels from channel E to channel data format unit 38d. From time 1 through time 442, multiplexer 36d provides pixels stored in first in-first out buffer memory 34j to channel data format unit 38d. Beginning at time 443, multiplexer 36d provides a constant zero input to channel data format unit 38d. The last 70 pixels of each line of video thereby correspond to a black strip on a second side of a displayed video frame. Thus, formatter 24' reformats the channels of processing circuitry 20 for use with the channels of display 26a. FIGURE 8 is a timing diagram that illustrates how data from a system 10 comprising 5 channels is stored in first in-first out buffer memories 34a through 34j. The timing provided for by FIGURE 8 allows formatter 24' to remove overlap between adjacent channels and to prepare appropriate channels for display 26a. Each time unit of FIGURE 8 corresponds to the time for storing one pixel of data in a first in-first out buffer memories 34a through 34j. Beginning at time 1 in FIGURE 8, channels A through E each discard the first pixel of video data for their respective channels. The first pixel of channel A may be removed because it is an edge pixel that was not fully processed. As for channels B through E, the first pixel corresponds to an overlapping pixel. At time 3, channels B through E begin storing pixels in first in-first out buffer memories 34b, 34e, 34g, and 34j respectively. In this manner, channels B through E remove the second pixel of their respective channels. At time 4, channel A begins storing pixels in first in-first out buffer memory 34a thereby removing pixels 2 and 3 from channel A. At time 105, channel B switches to storing pixels in first in-first out buffer memory 34d. Channel B switches to compensate for differences between the channels of processing circuitry 20 and the channels of display 26a. Similarly, at time 207, channel C switches to store pixels in first in-first out buffer memory 34f. Finally, at time 309, channel D switches to store pixels in first in-first out buffer memory 34i. At time 411, channel E stops storing pixels thereby removing pixels 412 through 414 from channel E. Similarly, channels A through D stop storing pixels at time 412 thereby removing pixels 413 and 414 from channels A through D respectively. As with FIGURE 6, it is noted that the timing shown in FIGURE 8 may be adjusted to control the number of pixels that are removed from the various channels. Additionally, the time at which a channel is switched from one buffer memory to another may be altered to provide appropriate channels for display 26a. Thus, the overlapping pixels are removed from channels A through E and channels A through E are prepared to be combined in appropriate channels for display 26a. FIGURE 9 is a timing diagram for retrieving data from first in-first out buffer memories 34a through 34j to create appropriate channels for display 26a. Multiplexer 36a combines pixels from channel A and channel B to produce a single channel for display 26a. Multiplexer 36a provides the pixels stored in first in-first out buffer memory 34a to channel data format unit 38a from time 1 through time 409. Multiplexer 36a also provides the pixels stored in first in-first out buffer memory 34b to channel data format unit 38a from time 410 through time 512. Multiplexer 36b combines pixels from channels B and C to form a single channel for display 26a. Multiplexer 36b provides pixels stored in first in-first out buffer memory 34d to channel data format unit 38b from time 1 through time 307. Multiplexer 36b provides pixels from first in-first out buffer memory 34e to channel data format unit 38b from time 308 through time 512. Multiplexer 36c combines pixels from channels C and D to form a single channel for display 26a. Multiplexer 36c provides pixels from first in-first out buffer memory 34f to channel data format unit 38c from time 1 through time 205. Multiplexer 36c provides the pixels stored in first in-first out buffer memory 34g to channel data format unit 38c from time 206 to time 512. Multiplexer 36d combines pixels from channels D and E to form a single channel for display 26a. Multiplexer 36d provides pixels stored in first in-first out buffer memory 34i to channel data format unit 38d from time 1 through time 103. Multiplexer 36d provides pixels from first in-first out buffer memory 34j to channel data format unit 38d from time 104 through time 512. Thus, formatter 24' reformats the channels of processing circuitry 20 for use with the channels of display 26a. FIGURE 10 illustrates an embodiment of a channel data format unit indicated generally at 38' and constructed according to the teachings of the present invention. Data format units 38a through 38d may comprise a data format unit 38' of FIGURE 10. For conciseness, however, channel data format unit 38' will be described in terms of the location of data format unit 38a of FIGURE 5. Additionally, channel data format unit 38' will be described in terms of display 26a of FIGURE 1. It should be understood that channel data format unit 38' is not so limited, but may be used as channel data format unit 38b through 38d and may be used with display 26b or 26c. Data format unit 38' comprises buffer memory 40 and a plurality of multiplexers 42. Plurality of multiplexers 42 may comprise, for example, 32 multiplexers controlled by a bit select signal from timing and control circuit 28 of FIGURE 1. Buffer memory 40 is coupled to multiplexer 36 as shown in FIGURE 5. Buffer memory 40 comprises a plurality of memory locations 44 equal in number to the number of pixels in one channel of display 26a. Memory locations 44 may, for example, be oriented in 16 rows, each comprising 32 columns. Each multiplexer 42 may be coupled to an output of buffer memory 40 corresponding to a column of memory locations 44. In operation, one channel, for example, a channel of display 26a associated with channel data format unit 38a, of an individual line of video signal may be sequentially received and stored in memory locations 44 of buffer memory 40. Each memory location 44 comprises 10 bits of video data for one pixel in a single channel of a line of a video frame. The video data may be communicated to a channel of display 26a of FIGURE 1, for example, one line at a time to form 10 bit planes. A bit plane corresponds to one bit of data for each pixel in a video frame. Therefore, the first bit plane, for example, may correspond to the most significant bit for each pixel and the tenth bit plane may correspond to the least significant bit for each pixel. Once the data for a channel of a first line of a video frame is stored in buffer memory 40, channel data format unit 38' may create the first line of the appropriate bit planes for one channel of display 26a. Channel data format unit 38' may communicate the first line of the ten bit planes for the one channel of display 26a in 32 bit words to display 26a of FIGURE 1. For example, the first 32 bit word used in forming a channel of the first line of the first bit plane may correspond the bottom row of memory locations 44 of buffer memory 40. The first bit of each memory location 44 in successive rows of buffer memory 40 may be used to create successive 32 bit words to fill out the first line of the first bit plane for the channel of display 26a. The first line of a first bit plane for the channel is complete once all of the first bits stored in all of the rows of memory locations 44 have been used. This process may be repeated for successive bits in each memory location 44 until all of the data for a channel of a single line of video signal has been communicated to display 26a of FIGURE 1. Thereby, the first line of each of the 10 bit planes of data for a channel of a single frame of video signal are communicated to display 26a of FIGURE 1. The remaining lines of each of the ten bit planes associated with a frame of video may be communicated to display 26a of FIGURE 1 by repeating the above process for each line in the video frame. FIGURE 11 illustrates an alternative embodiment of a formatter indicated generally at 24''. Formatter 24'' comprises a single multiplexer 36' in place of multiplexers 36a through 36d of FIGURE 5. Multiplexer 36' may comprise a single output line coupled to digital to analog converter 46. Digital to analog converter 46 may be coupled to an appropriate analog display such as a cathode ray tube (CRT) device 48. In operation, first in-first out buffer memories 34a through 34j may store video data as described above with respect to FIGURES 5, 6, and 8. Video data may be read out of first in-first out buffer memories 34a through 34j by multiplexer 36' so as to provide a single stream of video data for CRT 48. The output of multiplexer 36' may be converted to an appropriate analog signal for CRT 48 by digital to analog converter 46. The timing of digital to analog converter 46 and multiplexer 36' is controlled by timing and control circuit 28. FIGURE 12 illustrates an alternative embodiment of a formatter indicated generally at 24'''. Formatter 24''' comprises a single multiplexer 36'' in place of multiplexers 36a through 36d of FIGURE 5. Mutliplexer 36'' may comprise an appropriate number of output lines coupled to liquid crystal display (LCD) 50. In operation, first in-first out buffer memories 34a through 34j may store video data as described above with respect to FIGURES 5, 6, and 8. Video data may be read out of first in-first out buffer memories 34a through 34j by multiplexer 36'' so as to provide an appropriate stream of video data for LCD 50. The timing of multiplexer 36'' is controlled by timing and control circuit 28.

Claims: A video data formatter (24'; 24''; 24''') having a plurality of input channels, comprising: a line segment mapper (30; 30') responsive to the plurality of input channels and operable to remove pixels from adjacent input channels that are common to both channels, said line segment mapper (30; 30') further being operable to divide each of said input channels into two or more segments; and a data format unit (32; 32') responsive to said line segment mapper (30; 30') and operable to couple said segments so as to create at least one stream of video data for a display. The video data formatter of claim 1, wherein said line segment mapper (30') comprises a plurality of buffer memories (34). The video data formatter of claim 1 or claim 2, wherein said line segment mapper (30') comprises two buffer memories (34) for each said input channel. The video data formatter of any preceding claim, wherein said line segment mapper (30') comprises a plurality of first in-first out buffer memories (34). The video data formatter of any preceding claim, wherein said line segment mapper (30') comprises two first in-first out buffer memories (34) for each said input channel. The video data formatter of any preceding claim, wherein said data format unit (32') comprises a multiplexer (36; 36'; 36'') operable to output said segments of the input channels. The video data formatter of claim 6, wherein said data format unit further comprises a digital to analog converter (46) responsive to said multiplexer (36') and operable to provide an analog output to an analog display (48). The video data formatter of claim 6, wherein said data format unit (32') further comprises a plurality of said multiplexers (36) and a plurality of data format units (38) responsive to said multiplexers (36) and operable to store video data such that said stored video data of each data format unit (38) corresponds to a vertical strip of an image. The video data formatter of any preceding claim, wherein said data format unit (32') comprises two additional inputs receiving a blanking signal and operable to center the video data from the input channels on the display. A video system including a video data formatter according to any of claims 1 to 9. A television system including a video data formatter according to any of claims 1 to 9. A television system of claim 11 in the form of a digital television system. A method of formatting video data, comprising the steps of: processing video data in a plurality of parallel signal processing channels, each signal processing channel having a predetermined width in pixels and having a predetermined pixel overlap with an adjacent signal processing channel; storing the processed video data in a first plurality of buffer memories (34) such that the overlapping pixels are removed; and multiplexing the stored video data into a second plurality of buffer memories (38) to reformat the plurality of signal processing channels to provide at least one stream of output video data to a display. The method of claim 13, wherein the step of storing the processed video data further comprises the step of storing the processed data in a plurality of first in-first out buffer memories (34). The method of claim 13, wherein the step of storing the processed video data further comprises the step of storing the processed data in a plurality of first in-first out buffer memories (34) having two buffer memories associated with each signal processing channel such that each signal processing channel may be separated into two parts. The method of any of claims 13 to 15, wherein the step of multiplexing the stored video data further comprises the step of combining portions of adjacent signal processing channels to produce a plurality of vertical image strips of a digital display.

Inventors: DOHERTY DONALD B, GOVE ROBERT J, HEIMBUCH SCOTT D, MARKANDEY VISHAL, MARSHALL STEPHEN W, MEYER RICHARD C, URBANUS PAUL M, DOHERTY, DONALD B., GOVE, ROBERT J, HEIMBUCH, SCOTT D., MARKANDEY, VISHAL, MARSHALL, STEPHEN W., MEYER, RICHARD C., URBANUS, PAUL M.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1994
Main classification: H04N7
IPC codes: H04N5, H04N7