Multiple source power supply and method of selecting a power source from among multiple sources of power

Abstract: A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer. Also included is a disclosure of circuitry to protect the switch against a reverse connected battery charger.

Description: This invention relates to a bidirectional current blocking MOSFET and in particular to use of such a device in a battery disconnect circuit. Users of battery-powered devices such as notebook computers require that the devices be usable for long periods of time between battery recharges. This requirement has led to cascaded battery arrangements, in which a primary battery, a secondary battery, etc., are connected to the device in succession. Frequently an AC/DC converter is also provided to allow the user to conserve battery power when he is near a source of AC power. A connection for an external backup battery may also be provided. Such an arrangement is illustrated in Fig. 1 wherein a primary battery B1 and a secondary battery B2 are connected via switches S1 and S2, respectively, to a load L, which could be a DC/DC converter supplying, for example, a notebook computer. The supply connections are made through a bus which is designated B. Also connected to bus B is an AC/DC converter C3 which supplies power through a switch S3. The voltage supplied by primary battery B1 is designated V 1 , the voltage supplied by secondary battery B2 is designated V 2 , and the voltage supplied by AC/DC converter C3 is designated V 3 . The voltage at bus B is designated V bus . A backup battery B4 is also connected to bus B. Backup battery B4 provides power to some supervisory circuits and memory functions (not shown) when primary battery B1 and secondary battery B2 are discharged. To ensure that it is present when needed, backup battery B4 is not switched. In the operation of this multiple battery arrangement, only one of switches S1, S2, and S3 would normally be closed at any given time. The remaining switches would be open. When power is supplied by primary battery B1, for example, switch S1 is closed and switches S2 and S3 are open. As the power sources are switched in and out, the voltage across switches S1, S2, and S3 can vary both in magnitude and direction.- This is illustrated in Figs. 2A-2C. As shown in Fig. 2A, for example, the output V 2 of battery B2 might be 14 V at a given point in time. If battery B2 is then supplying power, the voltage V bus would also equal 14 V. If battery B1 is fully charged, its output voltage V 1 might be 18 V. In this case, the left side of switch S1 would be positively charged. On the other hand, assume the same situation except that battery B1 is discharged, so that V 1 is 6 V. In this case, the right side of switch S1 is positively charged, as shown in Fig. 2B. A third alternative is illustrated in Fig. 2C where battery B1 is discharged, battery B2 is fully charged, and bus B is supplied by AC/DC converter C1. In the example, V 1 is shown as equalling 6 V, V 2 is shown as equalling 17 V, and V 3 is shown as equalling 12 V. In this case, the right side of switch S1 is positively charged, and the left side of switch S2 is positively charged. In summary, any of switches S1-S3 may have to withstand a voltage in either direction. The only thing known for certain is that all of the voltages applied to these switches will be above ground. The device may also be equipped with an internal battery charger, as illustrated in Fig. 3. A battery charger C5 is connected to battery B1 via a switch S4 and to battery B2 via a switch S5. Battery charger C5 may be supplied from the output of AC/DC converter C3 or (optionally) directly from the power main. As illustrated in Fig. 4, battery charger C5 may deliver a voltage as high as 24 V for quick battery charging. In the condition illustrated in Fig. 4, battery B2 is being charged, and the V 1 output of battery B1 is equal to 12 volts. Switch S4 therefore must withstand a voltage difference of 12 V. However, since deep discharging of a rechargeable battery is known to extend its life, V 1 could drop to below 6 V, in which case switch S4 would need to withstand over 18 V, with its left side being positively charged. On the other hand, when battery charger C5 is not operative it may have a shorted or leaky characteristic, and switches S4 and S5 would then have to block voltages in the other direction. Therefore, switches S4 and S5 must also be bidirectional current blocking. The foregoing would not represent a problem if switches S1-S5 were mechanical switches. However, it is preferable to use semiconductor technology, and in particular MOSFET technology, in fabricating these switches. Power MOSFETs are typically fabricated with a source-body short to ensure that the intrinsic bipolar transistor (represented by the source, body and drain regions) remains turned off at all times. The prior art teaches generally that a good source-body short is fundamental to reliable parasitic-bipolar-free power MOSFET operation. See, for example, "Power Integrated Circuits", by Paolo Antognetti, McGraw-Hill, 1986, pp. 3.27-3.34. The use of a source-body short has the effect of creating a diode across the drain and body terminals of the MOSFET which is electrically in parallel with the MOSFET. For a P-channel device, the cathode of the diode is connected to the drain; for an N-channel device, the anode of the diode is connected to the drain. Thus, a MOSFET must never be exposed to voltages at its source-body and drain terminals which would cause the "antiparallel" diode to become forward-biased. Figs. 5A-5D illustrate the polarity of the antiparallel diode (shown in hatched lines) for a vertical N-channel DMOS device (Fig. 5A), a vertical P-channel DMOS device (Fig. 5B), a lateral N-channel device (Fig. 5C), and a lateral N-channel DMOS device (Fig. 5D). Accordingly, conventional MOSFETs are not suitable for switches S1-S5 because they are not capable of blocking bidirectional currents. In Figs. 2A-2C, for example; the antiparallel diodes across switches S1 and S2 are shown in hatched lines, with their anode and cathode terminals arranged so as would be required to block the flow of current through the switches. If the polarity of the voltages across the switches were reversed, the antiparallel diodes would become forward-biased. One possible solution to this problem would be to connect two MOSFETs in a back-to-back arrangement, as illustrated schematically in Figs 6A-6C. Fig. 6A illustrates a pair of NMOS devices having a common source, Fig. 6B illustrates a pair of NMOS devices having a common drain, and Fig. 6C illustrates a pair of PMOS devices having a common source. These back-to-back arrangements double the on-resistance of the switches, however, and therefore detract significantly from the amount of power delivered to the computer or other device. Moreover, when a battery charger is used in the arrangement, the connections between the battery charger and the battery may become reversed. For example, some of the connectors used for battery chargers have interchangeable polarities, and some battery chargers contain a switch which allows the polarity of the output to be reversed. In such situations, a battery disconnect switch may be exposed to a negative rather than a positive voltage. Accordingly, what is needed is a bidirectional current blocking semiconductor switch which has the on-resistance of a normal MOSFET and yet does not contain an antiparallel diode across its drain and body terminals. Preferably, the bidirectional current blocking semiconductor switch should also be able to withstand a reversed battery charger condition. US 4 857 984 A describes a four terminal MOSFET switch and addresses the problem of undesirable parasitic transistor action. The described MOSFET comprises a semiconductor substrate; a first region of a first conductivity type and a second region of said conductivity type formed in said semiconductor substrate, and being connected to first and second terminals respectively; a body region of a second conductivity type formed in the semiconductor substrate, the second conductivity type being different from the first conductivity type, the body region being at a body voltage, the body region comprising a channel region located between the first and second regions, the body region not being shorted to either of the first and second regions, a junction between the first region and the body region forming a first diode and a junction between the second region and the body region forming a second diode. In said MOSFET switch the body voltage is kept at a voltage in such a relationship with the first voltage and the second voltage to prevent the said first diode and the said second diode from being forward biased independently of whether the first voltage is higher or lower than the second voltage. A multiple source power supply in accordance with one aspect of this invention is described in claim 1 enclosed herein. The source and body regions of the MOSFET are not shorted together, and voltages that are applied to the source and drain terminals are both either higher than (for an N-channel device) or lower than (for a P-channel device) a voltage at wich the body region is maintained. The source, body and drain voltages are established such that the source-body and drain-body junctions of the device are never forward biased. The multiple source power supply according to claim 1 uses a bidirectional current-blocking switching arrangement. According to a second aspect of this invention there is provided a method of selecting a power source from among multiple sources of power, as described in claim 4 enclosed herein. The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 illustrates a schematic drawing of a multiple source power supply arrangement, including disconnect switches. Figs. 2A, 2B and 2C illustrate possible voltage differences encountered by the disconnect switches shown in Fig. 1. Fig. 3 illustrates a schematic diagram of a multiple source power supply arrangement, including a battery charger. Fig. 4 illustrates possible voltage differences encountered by the disconnect switches shown in Fig. 3. Figs. 5A-5D illustrate, respectively, a vertical N-channel double-diffused MOSFET (DMOS), a vertical P-channel DMOS MOSFET, a lateral N-channel MOSFET, and a lateral N-channel DMOS MOSFET, all of which contain a source-body short. Figs. 6A-6C illustrate bidirectional current blocking switches consisting of back-to-back MOSFETs. Fig. 7 illustrates a multiple source power supply arrangement in accordance with the invention containing disconnect switches. Fig. 8 illustrates schematically the general case of a multiple source power supply arrangement according to this invention. Fig. 9 illustrates a multiple source power supply arrangement with disconnect switches consisting of drifted MOSFETs which are capable of switching higher voltage differences. Figs. 10A and 10B illustrate schematically the off-state and the on-state, respectively, of the switches illustrated in Figs. 7 and 8. Figs. 11A-11D illustrate conceptually the reduced on-resistance which is obtained using a bidirectional blocking switch. Fig. 12A illustrates a battery disconnect switch with no protection against a reversed battery charger, and Figs. 12B-12G illustrate the difficulties with several possible ways of protecting a battery disconnect switch against a reversed battery charger. Figs. 12A-12G do not form part of the invention. Figs. 13A and 13B illustrate test results of a protective circuit. Fig. 7 illustrates a multiple source power supply arrangement in accordance with the invention containing bidirectional current blocking switches 70 and 71. Switch 70 is connected to a battery 72, which supplies a voltage V 1 , and switch 71 is connected to an AC/DC converter 73 or another battery, which supplies a voltage V 2 . Switches 70 and 71 connect into a bus 74, which supplies an output voltage V out to a load. While two power sources and two switches are illustrated in Fig. 7, it will be apparent that any number of batteries or other power sources could be included in the arrangement. Switch 70 is a lateral MOSFET which is illustrated in cross section. MOSFET 70 is preferably formed in either a stripe or cellular pattern in a substrate 75, which in this embodiment is formed of P-type semiconductor material. N+ regions 76 and 77 are formed at the surface of P substrate 75, separated by a channel region 78. A gate 79 is formed over channel region 78, separated from channel region 78 by an oxide layer 80. A terminal 81 connects N+ region 76 to battery 72 and a terminal 82 connects N+ region 77 to bus 74. Gate 79 is supplied by a gate voltage V G1 . It will be noted that switch 70 is a symmetrical device, and regions 76 and 77 are not referred to as source or drain regions, since either of them can be biased positively or negatively relative to each other. The junction between P substrate 75 and N+ region 76 is represented by a diode D, and the junction between P substrate 75 and N+ region 77 is represented by a diode D 2 . In a conventional manner, the gate voltage V G1 is held low when switch 70 is turned off, and is raised to a positive voltage when switch 70 is turned on. Since P substrate 75 is grounded, and since the voltage at terminals 81 and 82 can only be positive, it is apparent that one of diodes D 1 and D 2 is always reverse-biased when switch 70 is turned off. Accordingly, when switch 70 is off it blocks current whether the voltage at terminal 81 is higher or lower than the voltage at terminal 82. Neither N+ region 76 nor N+ region 77 is shorted to P substrate 75. Despite the lack of a source-body short, the NPN transistor represented by N+ regions 76 and 77 and P substrate 75 will not become activated, provided that the on-off transitions at gate 79 are fast relative to the reaction time (capacitance) of the load. Since this circuit acts like a follower, i.e., a common drain configuration relative to the most positive side, an on-state bipolar transistor immediately develops a reverse-biased source voltage which keeps the bipolar transistor turned off. In other words, at the onset of conduction, the formation of the channel in the MOSFET causes the voltage on both sides of the MOSFET to normalize to approximately the same voltage. Presuming that the more negative potential is from a discharged battery or load and the more positive potential is from a power source or fully-charged battery, the more negative potential will rise to a voltage near the positive value when the switch is activated. At the outset of conduction, even if the more negative terminal is at zero volts, the beginning of conduction will immediately raise the more negative potential to a voltage above ground, thereby reverse-biasing the junction. The gate should be driven rapidly to minimize the duration of the switching transition. The fact that neither N+ terminal (i.e., source or drain) is permanently tied to ground is a distinguishing feature of the bidirectional blocking switch. Another distinguishing characteristic is its possible connection to voltage sources of limited energy, such as batteries, where voltage decays with time. The bidirectional blocking switch is therefore not a "high side" switch (permanently tied to a fixed positive supply rail, present whenever circuit operation is desired), since batteries and even AC adapters may discharge or be unplugged. Likewise, it is not a "low side" switch because neither side is tied permanently to ground. Instead, it acts like a reversible source follower when conducting, with the more positive voltage acting as the drain and the more negative voltage as the source. Switch 71 is identical to switch 70 but has terminals designated 83 and 84 and is controlled by a gate voltage V G2 . Thus, whatever the voltages applied to terminals 81-84, switches 70 and 71 will block currents whenever their respective gate voltages V G1 and V G2 are low, provided that the voltage differences across the switch remain below the breakdown voltage of the internal diodes. The breakdown voltages of the internal diodes would normally be in the range of 8 V to 12 V to 14 V. Switches 70 and 71 can therefore be controlled to selectively connect or isolate battery 72 and AC/DC converter 73 without concern that an antiparallel diode in the switches will become forward-biased. Such Switches can be used for any of switches S1-S5 shown in Figs. 1 and 4. It should be noted that, while switches 70 and 71 appear in cross section to be conventional lateral N-channel MOSFETS, each of them has a large gate width W in order to achieve a low on-resistance, typically below 200 mΩ and as low as 60 mΩ. Moreover, in the operation of a conventional MOSFET, it is not common to subject both the source and drain terminals to voltages originating from more than one power source, nor is it common to operate a conventional MOSFET as a bidirectional source follower, i.e., without specifying which terminal acts as the higher (drain) terminal (in an NMOS device) which supplies current and which terminal acts as the lower (source) terminal, which sinks current to ground through a load. Conventional source followers, for example, have one terminal connected directly or indirectly to a power supply or a bus while the other terminal is always the output of the follower. In other words, there is a permanent directional relationship between the battery (or bus) voltage, the drain voltage, and the source voltage (in ascending order). This relationship is not valid in a disconnect switch since either side may be higher at any given time. Similarly, switches 70 and 71 are unlike an N-channel transmission gate in logic arrays (referred to as pass-transistor logic), since in such logic arrays only one supply is present. Fig. 8 illustrates schematically the general case of a bidirectional blocking switch S 0 connected between power sources P 10 and P 20 . Power sources P 10 and P 20 generate voltages V 10 and V 20 . Switch S 0 will block current whether V 10 > V 20 or V 20 > V 10 , and will conduct current from P 10 to P 20 or from P 20 to P 10 . Source P 20 may be disconnected entirely from the circuit via a second switch S 0 '. Fig. 9 illustrates a drifted version of switches 70 and 71, which is capable of withstanding higher voltage differences (for example, 15 V, 18 V or 24 V). A switch 90 contains N-drift regions 92 and 93, which serve to limit the strength of the electric field across oxide region Drift regions are described more fully in U.S. Patent No. 5,237,193, to Williams, issued August 17, 1993. Since the gate must be biased sufficiently positive relative to ground to allow the device to conduct over the specified operating range, the oxide separating the gate from the channel region must be thick enough to accommodate the maximum gate voltage reliably. Since either side of switch 90 may serve as the "drain" in a given situation, a drift region must be provided on both sides of the channel region. The drifted embodiment illustrated in Fig. 9 is useful if the voltage across the switch is above about 14 V. In such situations the drift region prevents the gate oxide from exposure to high electric fields. To turn the switch on, the gate voltage of switch 90 may either be fixed or may be a voltage slightly higher than V 1 . If the gate voltage is a fixed value relative to ground (for example, 30 V) a standard gate oxide thickness (2·10 -8 - 4·10 -8 m) will not support the gate-to-substrate bias at the moment of turn on, and a thicker gate (for example, over 7·10 -8 m) must be used. If the gate potential is limited to 10 V above the more negative terminal voltage and rises with that voltage, then the thicker oxide is not needed. Figs. 10A and 10B illustrate an example of the two states of switch 70 shown in Fig. 7. In Fig. 10A, the gate of switch 70 is grounded and switch 70 is turned off, isolating battery 72 from AC/DC converter 73. This would be the situation, for example, when AC/DC converter is supplying the load. Assuming that V 2 is greater than V 1 , diode D 2 blocks current from flowing through switch 70. Fig. 10B illustrates the situation when the gate of switch 70 is biased at least one volt above ground. Switch 70 is then turned on, allowing battery 72 to supply a load 95, which includes a capacitance C load and resistance R load. Figs. 11A-11D illustrate a further advantage of bidirectional current blocking switches, namely, their significantly improved on-resistance. Fig. 11A shows an area A which represents the surface area of a lateral or vertical N-channel MOSFET. The on-resistance associated with the area A is designated R n , which is typically 1 milliohm for each square cm in area A. A single P-channel device exhibits a resistance which is approximately 2.5R n because of hole mobility which is poor relative to electron mobility. At voltages below about 20 V, the resistance per unit area is about the same whether the device is a vertical or lateral MOSFET. Even though the number of cells per unit area in a lateral MOSFET is nearly double that of a vertical DMOS, (because no area need be wasted on source-body shorts) half the cells in the lateral MOSFET are drain cells, whereas in the vertical DMOS the drain is on the bottom of the substrate. Returning to Figs. 11A-11D, Fig. 11B represents the resistance of back-to-back N-channel DMOS devices, which occupy an area 2A. This resistance is shown as 2R n because the devices must be connected in series. As shown in Fig. 11C, for P-channel devices, the resistance of back-to-back devices is equal to about 5R n . Fig. 11D illustrates that, the MOSFETS are connected in parallel rather than in series. A pair of parallel N-channel MOSFETS has a resistance equal to R n /2, which is only one-fourth the resistance of the back-to-back N-channel arrangement shown in Fig. 11B, and one-tenth the resistance of the back-to-back P-channel arrangement shown in Fig. 11C The parallel connection permits a dramatic reduction in the on-resistance, as compared with a back-to-back MOSFET arrangement. The resistance of the single N-channel MOSFET disconnect switch is assumed to be low because its gate drive is increased in relation to the voltage on its more negative terminal in order to maintain a constant channel resistance. Fig. 12A illustrates the problem that may occur if the battery charger C5 shown in Figs. 3 and 4 is connected in reverse to bidirectional current blocking switch S4, which includes a non source-body shorted N-channel MOSFET M. A diode D8 represents the junction between the body and source regions of MOSFET M. Battery charger C5 is assumed to deliver an output as high as 14 V, and battery B1 is assumed to deliver an output, for example, of 4 V. Accordingly, if battery charger C5 is reversed, the voltage at the source terminal of MOSFET M is -14 V, and a total voltage of 18 V appears across switch S4. In this condition, both MOSFET M and its intrinsic bipolar transistor are turned on, and switch S4 will be destroyed. (The intrinsic bipolar transistor within MOSFET M is shown as transistor Q3 in Fig. 12E.) Figs. 12B-12F illustrate the problems with several unsuccessful techniques for solving this problem. In Fig. 12B, a Schottky diode SD1 is connected between the body and source terminals of MOSFET M. A resistor R B limits the current through the Schottky diode SD1. Schottky diode SD1 effectively limits the base-emitter voltage of the intrinsic bipolar transistor to 0.2 V, thereby preventing the bipolar transistor from completely turning on. Resistor R B limits the current through Schottky diode SD1. Nonetheless, MOSFET M turns fully on because of the high gate-to-source voltage, i.e., 14 V, and switch S4 may be destroyed due to excessive current. In Fig. 12C, Schottky diode SD1 is connected between ground and the source of MOSFET M. In this arrangement, excessive currents are generated through Schottky diode SD1, and Schottky diode SD1 may therefore be destroyed. If resistor R B is connected in series with Schottky diode SD1, Schottky diode SD1 will fail to perform its function of turning MOSFET M off. In Fig. 12C, a diode D9 represents the junction between the body and drain regions of MOSFET M. As above, diode D8 represents the junction between the body and source regions of MOSFET M. In the arrangement shown in Fig. 12D, a bipolar transistor Q1 and a Schottky diode SD2 are connected between the gate and source terminals of MOSFET M. A second bipolar transistor Q2 is connected between the body and source terminals of MOSFET M. Herein, the terminal of MOSFET M which is connected to the battery charger is referred as the source terminal, and the terminal of MOSFET M which is connected to the battery is referred to as the drain terminal. Since the base of transistor Q2 is at about 4 V, transistor Q2 is turned on, and transistor Q2 provides a V cc (sat) of about 0.2 V between the body and source of MOSFET M. This prevents the intrinsic bipolar transistor within MOSFET M from turning completely on. However, the combination of transistor Q1 and Schottky diode SD2 allows the gate to source voltage (V GS ) of MOSFET M to rise to about 0.5 V, and this may allow MOSFET M to turn on. Thus the arrangement shown in Fig. 12D does not maintain the switch S4 in an off condition when the battery charger C5 is reverse connected. Transistors Q1 and Q2 are saturated because their base-to-collector and emitter-to-base junctions are both forward-biased in this condition. As shown in Figs. 12E and 12F, these problems intensify as the temperature of switch S4 increases, as is likely when significant amounts of current are flowing through switch S4. In a high-temperature condition, the gain of the bipolar transistor within MOSFET M increases, and the threshold voltage of MOSFET M decreases. In addition, the "antibody effect", a reduction in threshold due to the partial forward-biasing of the source-to-body junction (diode D8), also makes it easier to turn MOSFET M on. Figs. 12E and 12F show switch S4 as containing an intrinsic bipolar transistor Q3. Fig. 12G illustrates a series of curves showing the relationship between the current I D through switch S4 as a function of the drain-to-source voltage V DS of MOSFET M. In Fig. 12G, V GS represents the gate-to-source voltage of MOSFET M, and V B represents the source-to-body voltage of MOSFET M. As is apparent from Fig. 12G, when V GS equals 0.5 V and V B equals 0.2 V, the current I D increases rapidly in the vicinity of a V DS of 18 V. In other words, the device is in a region bordering on massive currents, and any variations in fabrication or temperature may cause it to be destroyed. Ideally, the "square" I-V characteristics of the V GS = 0, V B = 0 curve are desired. Figs. 13A and 13B illustrate the response of the gate voltage V G and body voltage V B of MOSFET M to the connection and disconnection of a reversed battery charger. In Fig. 13A, MOSFET M is off prior to the reversed charge connection, with its gate at 0 V and its body at +4 V. The connection is made at t = 0 and the disconnection at t = 30 ms. The switching transients are rapid and free from ringing. Fig. 138 shows a similar transition when MOSFET M is on prior to the reversed charger transient. In such a case, both V G and V B are biased at +4 V and are immediately switched to -14 V at t = 0. In Fig. 13B the gate drive voltage V z is biased to +4 V instead of +7 V. The foregoing examples are intended to be illustrative and not limiting. Many additional and alternative embodiments according to this invention will be apparent to those skilled in the art. All such embodiments are intended to be covered within the scope of this invention, as defined in the following claims.

Claims: A multiple source power supply comprising: a first source (P10, V1) having a first terminal at ground voltage and a second terminal, and connected through its second terminal and a first MOSFET switch (S O , 70) to a bus (B), the first power source supplying a first voltage which can vary; a second power source (P20, V2, C3) having a first terminal at ground voltage and a second terminal, and connected through its second terminal and a second MOSFET switch (S' O , 71) to the bus, the second power source supplying a second voltage which can vary; wherein each of the first and second MOSFET switches comprises: a semiconductor substrate (75); a first region (76) of a first conductivity type and a second region (77) of said conductivity type formed in said semiconductor substrate (75), and being connected to first (81, 83) and second (82, 84) terminals respectively, the first terminal of the first MOSFET switch being connected with the first power source, the first terminal of the second MOSFET switch being connected with the second power source, the second terminal of the first MOSFET switch being connected with the second terminal of the second MOSFET switch, the second terminals of the first and second MOSFET switches being connected with the bus; a body region of a second conductivity type formed in the semiconductor substrate, the second conductivity type being different from the first conductivity type, the body region being at a body voltage, the body region comprising a channel region (78) located between the first and second regions (76, 77), the body region not being shorted to either of the first and second regions (76, 77), a junction between the first region (76) and the body region forming a first diode (D1) and a junction between the second region (77) and the body region forming a second diode (D2); and a gate (79) overlying the channel region (78); wherein the second power source is connected through its second terminal with the bus when the channel region of the first MOSFET switch is non-conductive, and the first power source is connected through its second terminal with the bus when the channel region of the second MOSFET switch is non-conductive; and wherein the body voltage of the first MOSFET switch and of the second MOSFET switch is kept at ground voltage and in such a relationship with the first voltage and the second voltage to prevent the first diode (D1) and the second diode (D2) of the first and second MOSFET switch from being forward biased independently of whether the first voltage is higher or lower than the second voltage. The power supply of claim 1, wherein each of the first and second MOSFET switches further comprises a first drift region (92) between the first region (76) and the channel region (78) and a second drift region (93) between the second region (77) and the channel region (78), the first and second drift regions being of the same conductivity type as and being doped more lightly than the first and second regions. The power supply of any one of the previous claims, wherein the bus is connected to a load (95). A method of selecting a power source from among multiple sources of power, the method comprising: providing a first power source (P10, V1), the first power source having a first terminal at ground voltage and a second terminal, and supplying a first voltage which can vary; providing a second power source (P20, V2, C3), the second power source having a first terminal at ground voltage and a second terminal, and supplying a second voltage which can vary; connecting the second terminals of the first and second power sources to a bus (B) through a first and second MOSFET switch, respectively; wherein each of the first and second MOSFET switches comprises: a semiconductor substrate (75); a first region (76) of a first conductivity type and a second region (77) of said conductivity type formed in said semiconductor substrate (75), and being connected to first (81, 83) and second (82, 84) terminals respectively, the first terminal of the first MOSFET switch being connected with the first power source, the first terminal of the second MOSFET switch being connected with the second power source, the second terminal of the first MOSFET switch being connected with the second terminal of the second MOSFET switch, the second terminals of the first and second MOSFET switches being connected with the bus; a body region of a second conductivity type formed in the semiconductor substrate, the second conductivity type being different from the first conductivity type, the body region being at a body voltage, the body region comprising a channel region (78) located between the first and second regions (76, 77), the body region not being shorted to either of the first and second regions (76, 77), a junction between the first region (76) and the body region forming a first diode (D1) and a junction between the second region (77) and the body region forming a second diode (D2 ); and a gate (79) overlying the channel region (78); connecting the second power source through its second terminal with the bus when the channel region of the first MOSFET switch is non-conductive, and connecting the first power source through its second terminal with the bus when the channel region of the second MOSFET switch is non-conductive; and maintaining the body voltage of the first and second MOSFET switches at ground voltage and in such a relationship with the first voltage and the second voltage to prevent the first diode (D1) and the second diode (D2) from being forward biased, independently of whether the first voltage is higher or lower than the second voltage. The method of claim 4, wherein the first MOSFET switch is made non-conductive by connecting the gate (79) of the first MOSFET switch to ground. The method of claim 4, wherein as the first voltage source a battery (B1) is used. The method of claim 4 or 6, wherein as the second voltage source an AC/DC converter is used. The method of any one of claims 4-7 wherein the bus is connected to a load (95). The method of claim 8 wherein a transition time between a condition where the channel region (78) of the first or second MOSFET switches is conductive and a condition where the channel region (78) of the first or second MOSFET switches is non-conductive is fast relative to a capacitive reaction time of the load (95). The method of claim 4 further comprising a step of providing a battery charger circuit (C5). The method of any one of claims 4-10, wherein, in each of the first and second MOSFET switches, a first drift region (92) between the first region (76) and the channel region (78) and a second drift region (93) between the second region (77) and the channel region (78) are used, the first and second drift regions being of the same conductivity type as and being doped more lightly than the first and second regions.

Inventors: WILLIAMS RICHARD K, WILLIAMS, RICHARD K.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1994
Main classification: H03K17
IPC codes: H01L29, H03K17, H02J1, H02J7, H02J9