A high speed and low drift charge pump circuit

Abstract: A device for converting binary logic pulses into an output current and the output current being switchable between a positive and negative polarity. The device provides a charge pump circuit which is suitable for the phase-detector stage in a phase-locked loop (PLL) circuit. The charge pump circuit comprises an input stage for the "UP" binary logic pulses and a second stage for the "DOWN" binary logic pulses. The input stages comprise emitted-coupled transistor pairs. The circuit includes current sources and current sinks for generating the output current in the input stages in response to the binary logic pulses. The circuit features a pair of commutating diodes between the outputs of the input stages. The commutating diodes control the output current and the leakage current in the idle state. The circuit also includes a clamping circuit to limit the voltage swing across the commutating diodes. The charge pump circuit according to the present invention exhibits a fast response time, a symmetrical response to the binary logic pulses, and virtually zero leakage current in the idle state. The charge pump circuit utilizes non-complimentary bipolar processes and is suitable for a monolithic integrated circuit implementation.

Description: FIELD OF THE INVENTION This invention relates to a charge pump circuit commonly used in phase-locked loop circuits. More particularly, the present invention relates to a charge pump topology utilizing non-complementary bipolar processes that is suitable for a monolithic integrated circuit implementation. BACKGROUND OF THE INVENTION A charge pump is an electronic circuit block which is commonly used in phase-locked loop circuits. A phase-locked loop (PLL) is a frequency-selective device comprising a phase detector, a loop filter, an amplifier, and a voltage controlled oscillator (VCO) interconnected in known manner to form a feedback system. The charge pump converts the logic level pulses generated by the phase detector into current pulses which are fed to the loop filter. The loop filter integrates the current pulses to produce a control voltage for the voltage controlled oscillator. The logic level pulses used by the charge pump are commonly referred to as "PUMP UP" or "UP" pulses and "PUMP DOWN" or "DOWN" pulses. In response to these pulses, the charge pump produces an output current I O . In known manner, the output current I O is generated according to a logic truth table comprising the "PUMP UP" and "PUMP DOWN" logic pulses. In addition to the static relationship between the logic pulses and the output current I O , there is a requirement that the total charge supplied to the loop filter by the charge pump be an accurate reflection of the pulse widths of the UP and DOWN logic signals. For an UP pulse having a width of time T UP , the charge produced by the charge pump should be I*T UP coulombs. For a DOWN pulse having a width of time T DOWN , the charge pump should produce a charge of I*T DOWN coulombs. However, in practical charge pump implementations, the pulses of output current I O cannot be perfectly square due to the limitations of non-zero rise and fall times. Thus, the actual charge supplied by the charge pump to the loop filter will be less than the ideal quantity discussed above. It therefore becomes important that the non-ideality for the DOWN and UP charge pulses be the same for both the UP and DOWN signals so that UP and DOWN logic input pulses having equal width result in a net charge or current of zero. This condition should also hold true if the UP and DOWN pulses overlap or are coincident in time. Another problem experienced in practical implementations of charge pumps concerns the output leakage current, i.e. a non-zero output current when zero output current is desired. According to the logic level truth table for a charge pump, there are two conditions calling for zero output current, i.e. UP = DOWN = logic level 0 and UP = DOWN = logic level 1. Of the two conditions, the first condition UP = DOWN = logic level 0 is the most critical since this is the idle condition. Any leakage current in the idle condition will cause the control voltage output from the loop filter to vary and hence the voltage controlled oscillator frequency to drift. It will be appreciated by those skilled in the art that in some systems utilizing a phase-locked loop, a relatively long time may be spent in the idle state and therefore even modest levels of leakage current can cause the phase-locked loop to jitter or even lose frequency lock. Some conventionally known charge pump circuits such as the one disclosed in EP-A-405,523 alternately connect a positive source voltage power terminal through the source-drain paths of two p-channel FETS to an output terminal and the output terminal to circuit ground through two n-channel FETS. This charge pump circuit provides unsymmetric positive and negative current outputs due to the fact that the circuit utilizes both p-channel and n-channel transistors. Other conventionally known charge pump circuits such as the circuit disclosed in EP-A-484,059, alternately trigger a first input differential transistor stage to connect a current source through a suitably matched resistance into an inverting input of an operational amplifier and trigger a second input differential stage to connect the inverting input of the operational amplifier to a current sink of the same magnitude as the current source. This charge pump circuit provides increased symmetry between positive and negative output currents due to the fact that circuit can be wholly fabricated out of npn transistors. In summary, the practical charge pump should exhibit fast response time, symmetrical response to the input logic level pulses, and virtually zero idle state output leakage current. BRIEF SUMMARY OF THE INVENTION In a first aspect, the present invention provides a device for converting binary logic pulses into an output current, the output current being switchable between a positive and a negative polarity, said device comprising (a) a first input stage for inputting a first binary logic pulse, said first input stage having an output and means for generating a first current component at said output in response to said first binary logic pulse; (b) a second input stage for inputting a second binary logic pulse, said second input stage having an output and means for generating a second current component at the output of said second input stage in response to said second binary logic pulse; (c) current drive means for producing and controlling a third current component, said current drive means having an output for said third current component coupled to the output of said first input stage; and being characterised by (d) commutating means responsive to said first, second and third current components for producing the output current, said commutating means including first and second switches and an output port for the output current, said first switch having an input coupled to the output of said first input stage and an output and means for sourcing a constant output current at said output in response to said first and third current components, and said second switch having an output coupled to the output of said second input stage and having an input coupled to the output of said first switch and including means for sinking a constant output current at said input in response to said second current component, said output port being formed from the output of said first switch and the input of said second switch, and (e) clamping means for limiting the voltage swing across said first and second switches, said clamping means being coupled to the output of said second input stage and to the output of said current drive means. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings which show a preferred embodiment of the present invention. Figure 1 shows a phase-locked loop which utilizes a charge pump according to the present invention; Figure 2 shows in schematic form a charge pump according to the present invention; Figure 3 shows the charge pump according to the present invention operating in the idle state; Figure 4 shows the charge pump according to the present invention operating in the "PUMP UP" state; Figure 5 shows the charge pump according to the present invention operating in the "PUMP DOWN" state; and Figure 6 shows the charge pump according to the present invention operating in an alternate idle state. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 shows a standard phase-locked loop circuit. The phase-locked loop (PLL) is one of the fundamental circuit blocks of communications systems. The PLL is a frequency-selective circuit comprising a phase detector 10, a loop filter 12, an amplifier 14, and a voltage controlled oscillator 16. As shown in Figure 1, the phase detector 10, the loop filter 12, and the amplifier 14 are connected to a form feedback system with the voltage controlled oscillator 16. A charge pump 18 according to the present invention is incorporated into the phase detector 10 to convert logic level pulses generated by the phase detector 10 into an output current I O (current pulses) which are then fed to the loop filter 12. Reference will now be made to Figure 2 which shows in detail a charge pump topology 18 according to the present invention. The charge pump topology 18 utilizes only NPN devices for current switching, and therefore is well suited for a monolithic integrated circuit implementation. As shown in Figure 2, the charge pump topology 18 according to the present invention comprises an UP logic pulse input stage 20, a DOWN logic pulse input stage 22, a commutating stage 24, a buffer stage 26, a clamping circuit 28, a current drive stage 30, a loop filter output terminal 32 and a voltage controlled oscillator input terminal 34. The output terminal 32 allows the charge pump 18 (and output current I 0 ) to be coupled to the loop filter 12. The loop filter 12 typically includes an integrating capacitor C which converts the output current I 0 from the charge pump 18 into a voltage signal for controlling the voltage controlled oscillator stage 16. Considering first the UP logic pulse input stage 20 shown in Figure 2, the UP pulse input stage 20 comprises a pair of NPN transistors Q 1 and Q 2 , which are emitter coupled to form a differential pair current switch. As is known in the art, the emitter-coupled transistor topology offers high speed operation because the transistors do not operate in the saturation region. The base of the first transistor Q 1 provides a non-inverted UP logic pulse input terminal 36, and the base of the second transistor Q 2 is an input terminal 38 for the inverted UP (UP*) logic pulse input. In known manner, the input stage 20 includes a current source I 1 and a current sink I 2 . Current source I 1 connects to the collector of transistor Q 2 and produces an internal current I. Current sink I 2 connects to the coupled emitters of transistors Q 1 and Q 2 and sinks a current (2I) which flows in the emitters of the two transistors Q 1 and Q 2 when they are switched on. The collector of transistor Q 2 provides an output for the UP pulse input stage 20. Referring still to Figure 2, the DOWN pulse input stage 22 is very similar to the UP pulse input stage 20 described above. The DOWN pulse input stage 22 comprises two transistors Q 3 and Q 4 which are also emitter-coupled to form a differential pair current switch. The base of transistor Q 3 provides an input 40 for the non-inverted DOWN pulse, and the base of transistor Q 4 provides an input 42 for the inverted DOWN pulse. The DOWN input stage 22 also includes a current source I 3 and a current sink I 4 . In known manner, the current source I 3 connects to the collector of transistor Q 3 and produces an internal current I which flows into the collector of transistor Q 3 . The current sink I 4 connects to the coupled emitters of transistors Q 3 and Q 4 and sinks a current 21 which flows from the emitters of the transistors Q 3 and Q 4 . The collector of transistor Q 3 provides an output from the DOWN pulse input stage 22. The commutating stage 24 comprises two diodes which can be formed from two diode-connected transistors Q 5 and Q 6 . The function of the diodes (diode-connected transistors) Q 5 and Q 6 in the commutating stage 24 is to correct leakage or drift current when the charge pump is in one of the idle states (i.e. UP = DOWN =logic 0 or UP = DOWN = logic 1). The two diode-connected transistors Q 5 and Q 6 are coupled between the collector of transistor Q 2 and the collector of transistor Q 3 . The anode of diode Q 5 is connected to the collector of transistor Q 2 and the cathode of diodeis connected to the anode of diode Q 6 . The cathode of diode Q 5 is connected to the collector of transistor Q 3 . The loop filter output terminal 32 connects to the node formed by the connection of the cathode of diode Q 5 and the anode of diode Q 6 . Referring still to Figure 2, the current drive stage 30 comprises a drive transistor Q 10 , a current source I 6 and a diode-connected transistor Q 9 (diode Q 9 ). The emitter of the drive transistor Q 10 is connected to the collector of transistor Q 2 and the anode of diode Q 5 , and the collector of transistor Q 10 is connected to the positive supply rail V CC . The base of transistor Q 10 is connected to the anode of diode Q 9 and the output of the current source I 6 . The current source I 6 produces a current I which as will be explained is used to generate the output current I O . The cathode of diode Q 9 is connected to the voltage controlled oscillator terminal 34 and the output of the buffer stage 26. As shown in Figure 2, the buffer stage 26 is connected between the loop filter output 32 and the VCO terminal 34. In the preferred embodiment, the buffer stage 26 comprises a unity gain amplifier 44 having a very high input impedance. The function of the buffer stage 26 is to buffer the voltage level on the filter output 32 for use by the drive stage 30 and the clamping circuit 28 to limit the voltage swing across the diodes Q 5 and Q 6 in the commutating stage 24. The clamping circuit 28 is coupled between the collector of transistor Q 3 (i.e. the output of the DOWN pulse input stage) and output of the buffer stage 26 as shown in Figure 2. The function of the clamping circuit 28 is to limit the voltage swing across the diodes Q 5 and Q 6 to a Voltage of one V BE where V BE is the forward voltage drop across a base-emitter junction. The clamping circuit 28 comprises a diode-connected transistor Q 7 , a transistor Q 8 and a current sink I 5 . The anode of diode Q 7 is connected to the cathode of diode Q 6 and the cathode of diode Q 7 is connected to the emitter of transistor Q 8 . The collector of transistor Q 8 is connected to the positive supply rail V CC , and the base is connected to the VCO terminal 34 (and cathode of diode Q 9 ). The current sink I 5 is connected to the emitters of transistors Q 7 and Q 8 and is designed to sink a current of magnitude 2I. Typical charge pumps provide an output current I 0 of predetermined polarity in response to the UP and DOWN logic pulses according to the following truth table: As shown in truth table, the charge pump produces the output current I O (which feeds the loop filter) in two states. The first state occurs when the UP pulse is logic level 0 and the DOWN pulse is logic level 1. This state is know as the PUMP DOWN state and results in the charge pump producing a negative output current -I O . The other state is the PUMP UP state and occurs when the UP pulse is a logic level 1 and the DOWN pulse is at logic level 0. In the PUMP UP state, the charge pump produces a positive output current I O . The remaining two states are idle states and in theory the output current I O should be zero. However in practical implementations, there will be a leakage current which flows in the output terminal 32. The remainder of the description will explain the operation of the charge pump 18 according to the present invention in each of the four states shown in truth table. Reference is first made to Figure 3 which shows the operation of the charge pump 18 for the idle condition (i.e. UP = DOWN = 0). When the UP input 36 is at logic level 0, transistor Q 1 is off and transistor Q 2 is on, which results in a current of magnitude 2I (where I is the desired output current pulse amplitude) flowing in the collector of the transistor Q 2 . The current source I 1 provides half of the collector current 2I for transistor Q 2 . Transistor Q 10 must provide the other half (i.e. I) of the collector current in transistor Q 2 . As can be shown using Kirchoff's well-known voltage law, transistor Q 10 is turned on because the voltage level at the emitter of transistor Q 10 is at voltage V C , where V C is the voltage at the output of the buffer stage 26, and therefore the voltage at the base of transistor Q 10 is always V C + V BE . This results in a bias voltage across diode Q 5 which is very close to zero, (i.e. V C + V BE9 - V BE10 = V C ), hence the current flowing in diode Q 5 will be practically nil. Since the DOWN 40 input is at logic level zero in this state, transistor Q 3 is also off, and hence the current I produced by current source I 3 will flow in diode Q 7 (the cathode of commutating diode Q 6 cannot sink current). The operation of the clamping circuit 28 (i.e. current sink I 5 ) causes a current of magnitude I to flow in diode Q 7 and an equal current I to flow in the collector of transistor Q 8 . This equal splitting of the collector currents in diode Q 7 and transistor Q 8 produces base voltages which are equal to voltage V C and this results in an approximately zero voltage bias across the diodes Q 5 and Q 6 which keeps the diodes Q 5 and Q 6 in the non-conductive state. In the non-conduction state, the diodes Q 5 and Q 6 block any flow of the output current I O to the loop filter 32 which results in extremely low idle state leakage current which is independent of the output current I O . Reference is next made to Figure 4 which shows the operation of the charge pump 18 for the "PUMP UP" state, i.e. UP = logic level 1 and DOWN = logic level 0. Since the DOWN input 40 is at logic level 0, the zero bias condition of diode Q 6 is set up in the same fashion as for the idle condition discussed above. However if the UP input 36 is at logic level 1, transistor Q 2 is turned off, and therefore the current I from current source I 1 will flow into the diode Q 5 since the emitter of Q 10 opposes the direction of current flow from current source I 1 . This causes the voltage level at the emitter of transistor Q 10 to be V C + V BE . Thus transistor Q 10 is zero biased (i.e. turned off) and therefore provides essentially no current to diode Q 5 . Since diode Q 6 is turned off, the output current I O having a magnitude of I will flow through diode Q 5 to the loop filter output 32 and feed the loop filter 12. It will be appreciated by one skilled in the art that the voltage at the collector of the transistor Q 2 is required to slew through a voltage level of 1 V BE to turn on the diode Q 5 and allow it to conduct the output current I O . In the PUMP UP state, diode Q 6 remains turned off because it is reversed biased by the voltage V C . Reference is now made to Figure 5 which shows the operation of the charge pump 18 in the "PUMP DOWN" state. In the PUMP DOWN state, the UP input 36 is at logic level 0 and the DOWN input 40 is at logic level 1. Since the logic level on the UP* 36 input is one, transistor Q 2 is turned on and the current sink I 2 sinks a current 2I (i.e. current source I 1 supplies I and Q 10 supplies I). The zero forward bias condition for diode Q 5 is set up in the same fashion as for the idle condition discussed above. The logic level 0 at the DOWN* input 42 keeps transistor Q 4 turned off, hence the current sunk by current sink I 4 must flow through transistor Q 3 . The current source I 3 supplies half of this quantity, i.e. I, and diode Q 6 sources the remainder, i.e. I to produce current 2I. This follows because diode Q 7 cannot source current at its anode. Referring still to Figure 5, when diode Q 6 turned on, the voltage at its emitter is V C - V BE where V BE is the voltage drop across the base-emitter junction of the diode-connected transistor Q 6 . This voltage produces an essentially zero bias condition for diode Q 7 , and therefore diode Q 7 remains turned off and provides no conduction path for additional current flow. Since diode Q 5 is off and diode Q 6 is on, it follows that the output current I O will flow into diode Q 6 resulting in a negative output current I O being supplied to the loop filter 12. It will be appreciated that the voltage at the collector of transistor Q 3 is required to slew through a voltage of V BE to bring diode Q 6 into conduction (as was the case for transistor Q 2 in the "PUMP UP" state discussed above). It will be appreciated by one skilled in the art that net current available to charge the nodes at the respective collectors of transistors Q 2 and Q 3 is current I. Therefore, to preserve symmetry of response for both UP and DOWN pulses, the parasitic loading at these nodes must also be essentially the same for both nodes. Referring to Figure 5, the node at the collector of transistor Q 2 has a tally of 2 collectors (Q 2 and Q 5 ), 1 emitter (Q 10 ), and 1 current source (I 1 ) which produces a current with magnitude I. The tally for the node at the collector of transistor Q 3 is also 2 collectors (Q 3 and Q 7 ), 1 emitter (Q 6 ) and 1 current source (I 3 ). Figure 6 shows the situation when the UP and DOWN pulses are both active high. This is referred to as "ALT IDLE" (alternate idle). Although both logic pulses are active high, the charge pump is expected to produce no output current I 0 . This situation only occurs with certain implementations of phase/frequency detectors, and is much less critical for output leakage performance than the true idle condition (UP = DOWN = 0) discussed above. In ALT IDLE state, the output current I 0 is the difference between the currents flowing in diode Q 5 and diode Q 6 , and consequently the output current I 0 which leaks will not be as low as for the idle state discussed above. However, for most applications, this resulting leakage current does not present a problem, It will be appreciated that various changes may be made within the scope of the appended claims.

Claims: A device (18) for converting binary logic pulses into an output current, the output current being switchable between a positive and a negative polarity, said device (18) comprising: (a) a first input stage (20) for inputting a first binary logic pulse, said first input stage (20) having an output and means for generating a first current component at said first output in response to said first binary logic pulse; (b) a second input stage (22) for inputting a second binary logic pulse, said second input stage (22) having an output and means for generating a second current component at the output of said second input stage (22) in response to said second binary logic pulse; (c) current drive means (30) for producing and controlling a third current component, said current drive means (30) having an output for said third current component coupled to the output of said first input stage (20); and being characterised by (d) commutating means (24) responsive to said first, second and third current components for producing the output current of said commutating means (24) including first and second switches (Q 5 , Q 6 ) and an output port for the output current, said first switch (Q 5 ) having an input coupled to the output of said first input stage (20) and an output and means for sourcing a constant output current at said output in response to said first and third current components, and said second switch (Q 6 ) having an output coupled to the output of said second input stage (22) and having an input coupled to the output of said first switch (Q 5 ) and including means for sinking a constant output current at said input in response to said second current component, said output port being formed from the output of said first switch and the input of said second switch, and (e) clamping means (28) for limiting the voltage swing across said first and second switches (Q 5 , Q 6 ), said clamping means (28) being coupled to the output of said second input stage (22) and to the output of said current drive means (30). The device (18) as claimed in claim 1, wherein said first input stage (20) comprises differential switching means having a first input port for receiving said first binary logic pulse, a second input port for receiving a complement of said first logic pulse, a control port, and an output port forming the output for said first input stage (20) and being coupled to said first switch (Q 5 ). The device (18) as claimed in claim 1, wherein said second input stage (22) comprises differential switching means having a first input port for receiving said second logic pulse, a second input port for receiving a complement of said second logic pulse, a control port, and an output port forming the output for said second input stage (22) and being coupled to said second switch (Q 6 ). The device (18) as claimed in claim 1, wherein said clamping means (28) includes first and second input ports, a control port, said first input port being coupled to the output of said second input stage (22) and to the output of said second switch (Q 6 ), and said second input port being coupled to said current drive means (30) and to a voltage control input port. The device (18) as claimed in claim 4, wherein said clamping means (28) comprises first and second transistors (Q 7 , Q 8 ), and a current sink, said first and second transistors (Q 7 , Q 8 ) each having a collector, a base and an emitter, the collector and the base of said first transistor (Q 7 ) being connected to the output of said second switch (Q 8 ) and to the output of said second input stage (22), the emitters of said first and second transistors (Q 7 , Q 8 ) being connected to said current sink, and the base of said second transistor (Q 8 ) being connected to said voltage control input port through a buffer (26), so that said clamping means (28) are referenced to at voltage level on said output port of the device (18) thereby limiting the voltage swing across the first and second switches (Q 5 , Q 6 ). The device (18) as claimed in claim 2, wherein said first input stage (20) includes a current source and said differentia switching means comprises first and second transistors (Q 1 , Q 2 ), and a current sink, said first and second transistors (Q 1 , Q 2 ) each having a collector output, a base input and an emitter output and the emitter output of said first and second transistors (Q 1 , Q 2 ) being coupled to each other and to said current sink, the collector of said second transistor (Q 2 ) being coupled to said current source and providing the output for said first current component, and the base inputs of said first and second transistors (Q 1 , Q 2 ) providing said respective first and second input ports for receiving the said first binary logic pulses. The device (18) as claimed in claim 1,2 or 3 further including means for coupling to a loop filter (12) stage, said loop filter (12) stage being part of a phase-locked loop circuit, and said loop filter (12) stage including means (C) for converting said output current into a voltage signal. The device (18) as claimed in claim 7, wherein said means for converting (C) comprises an integrating capacitor, said integrating capacitor being coupled to said output port and producing said voltage signal in response to said output current. A charge pump circuit (18) suitable for integration in a phase-detector stage (10) in a phase-locked loop circuit, the phase-locked loop circuit also including a loop filter (12) having an integrator (44) which is coupled to said charge pump (18), said charge pump (18) comprising: (a) a first input stage (20) for inputting a first binary logic pulse, said first input stage (20) having an output and means for generating a first current component at said output in response to said first logic pulse, (b) a second input stage (22) for inputting a second binary logic pulse, said second input stage (22) having an output and means for generating a second current component at the output of said second input stage (22) in response to said second logic pulse; (c) current drive means (30) for producing and controlling a third current component, said current drive means (30) having an output for said third current component coupled to the output of said first input stage (20); and being characterised by (d) commutating means (24) responsive to said first, second and third current components for producing the output current, said commutating means (24) including first and second switches (Q 5 , Q 6 ) and an output port, said first switch (Q 5 ) having an input coupled to the output of said first input stage (20) and an output and means for sourcing a constant output current at said output in response to said first and third current components, and said second switch (Q 6 ) having an output coupled to the output of said second input stage (22) and having an input coupled to the output of said first switch (Q 5 ) and including means for sinking a constant output current at said input in response to said second current component, and said output port being formed from the output of said first switch (Q 5 ) and the input of said second switch (Q 6 ); (e) clamping means (28) for limiting the voltage swing across said first and second switches, said clamping means (28) being coupled to the output of said second input stage (22) and to the output of said current drive means (30); and (f) said output port being coupled to the integrator (C) in the loop filter (12) stage and said integrator (C) having means for converting the output current into a voltage signal.

Inventors: WEBSTER STEPHEN, WEBSTER, STEPHEN
Applicants: GENNUM CORP, GENNUM CORPORATION
Application year: 1994
Main classification: H03L7
IPC codes: H03L7, H02M3, G05F3