Multiplier capable of calculating double precision, single precision, inner product and multiplying complex numbers

Abstract: An AND gate (7A) inputs the most significant bit of a lower word (Y₃₋₀) of an multiplicand or "0" to an input terminal of the least significant bit of Booth's decoders (1A and 1B) to which an upper word (Y₇₋₄) of the multiplicand is inputted based on a control signal (S₁). An AND gate (7B) replaces a part (P₀₃ to P₀₀, P₁₃ to P₁₀) of a partial products with "0" based on the control signal (S₁). A selector (10) replaces other part (P₂₈ to P₂₅, P₃₈ to P₃₅) of the partial products with partial products (P₂₄ and P₃₄) of the lower bits than the other part of the partial products. Whereby, a plurality of pairs of data can be multiplied at one time.

Description: The invention relates to a multiplier using Booth's algorithm for multiplying a multiplier and a multiplicand according to the preamble of claim 1 as known from EP 0 239 899. Furthermore, EP 209 446 describes a parallel multiplier using Booth's decoding technique. A dividing means in response to a control signal passes either zero or the most significant bit of a lower portion to the least significant bit of the higher portion of the multiplicand. FIGS. 1A and 1B show a conventional parallel multiplier using Booth's algorithm. In FIGS. 1A and 1B, reference numeral 1 is a Booth's decoder, 2: a Booth's selector, and 3: a parallel adding circuit for adding partial products. FIG. 2 shows an example of a circuit forming the Booth's decoder 1 of FIG. 1A. In FIG. 2, reference numeral 4 is an NAND gate, 5: an NOR gate, 6: an OR gate, 7: an AND gate, and 8: an inverter. FIG. 3 shows an example of a circuit forming the Booth's selector 2 of FIG. 1A. In FIG. 3, reference numeral 9 is an exclusive NOR gate. Regarding the parallel adding circuit 3, the parallel adding circuit, which is disclosed in Japanese Patent Application KOKAI Publication No. 63-55627, can be used. Booth's algorithm is algorithm for multiplying a multiplier X and a multiplicand Y, which are expressed by twos complement, together at high speed as shown in equations (1) and (2). In this algorithm, as shown in equation (3), if a value of the multiplicand Y is decoded every three bits by the decoder 1, and each bit of the multiplier X is selected by the selector 2 in accordance with the decoding result, a partial product Pm is generated. A product Z can be obtained by adding the partial products Pm from m = 0 to m = (n/2)-1 as shown in equation (4). According to this algorithm, since the number of the partial products can be reduced to a half of the case in which an array multiplier using an AND gate to generate the partial products, the calculating speed can be increased. Normally, a value of y 2m-1 is set to 0 when m = 0. Multiplier X = -2 n-1 x n-1 + 2 n-2 x n-2 + ... + 2x 1 + x 0 Multiplicand Y = -2 n-1 y n-1 + 2 n-2 y n-2 + ... + 2y 1 + y 0 PARTIAL PRODUCTS Pm = X (-2y 2m+1 + y 2m + y 2m-1 ) 2 2m wherein y -1 = 0. In recent years, a portable data communication apparatus has been widely used. As an LSI, which is mounted on the apparatus, an LSI whose consumption of electrical power is low is required so as to prolong a life of a battery. Moreover, in order to deal with noise and an insufficiency of a communication channel capacity, the digital processing is essential, and an LSI for digital signal processing, that is, a digital signal processor (DSP) is mounted on the above apparatus. By mounting the digital signal processor on the data communication apparatus, highly sophisticated processing can be realized. However, as the processing becomes sophisticated, the following problem rises. More specifically, the principle of the operation of the digital signal processor is substantially the same as that of a general purpose microprocessor. Due to this, the more the processing becomes complicated, the more the processing time is increased. However, since the processing time has an upper limit, a frequency of an operation clock must be increased in the portable data communication apparatus in which a real time operation is required. However, if the clock frequency is increased, the consumption of electrical power is increased. The above problem does not meet the requirement of the LSI mounted on the portable data communication apparatus. As means for preventing such a problem, there is a parallel processing. The parallel process is that a plurality of processings are executed in parallel. An amount of processing within the unit time can be increased without increasing the clock frequency. However, the basic calculation of the digital signal processing is an operation in which the calculation of the sum of products, that is, the multiplied results are cumulatively added. Therefore, both the multiplier and the adder are built in the digital signal processor. Moreover, the above-mentioned convention multiplier can multiply only a pair of data at one time. Due to this, for executing the calculation of the sum of products at a double speed by the parallel processing, two multipliers must be built in the digital signal processor. Also, for cumulatively adding the multiplied results, at least two adders must be built therein. Moreover, for obtaining the final result of the cumulative addition, the results, which are separately added, must be added. Due to this, one more adder must be built in the digital signal processor, or two sets of registers (accumulators) for saving the results, which are separately added, must be prepared. Furthermore, a compiler having an optimization function is indispensable for using such a paralleled architecture. However, since an object conversion efficiency of the compiler does not suffice, the programming of the digital signal processor is executed by use of a common assembler. Due to this, the paralleled architecture applies an optimization load to the programmer, and efficiency of developing the software is dropped. Moreover, in the digital signal processing, a problem of a calculation precision always follows. Particularly, this problem is brought about when the DSP for fixed-point calculation is used. An error included in the result of the multiplication is accumulated by the cumulative addition, and the operation of the entire system becomes unstable. If the double precision calculation is used, the problem of the precision is improved. However, the circuit scale of the double precision multiplier is four times as large as that of the single precision multiplier, an area occupacy ratio of the double precision multiplier to the LSI is increased. In addition, the conventional multiplier is used, the plurality of the multipliers are needed in parallel processing for the above-mentioned reason. Therefore, such multipliers are not suitable in practical use. As mentioned above, the conventional multiplier has the following disadvantages. The more the processing becomes complicated, the more the clock frequency must be increased, and the consumption of the electrical power is increased. The provision of the parallel processing enlarges the circuit scale of the digital signal processor. The paralleled architecture applies an optimization load to the programmer. The object of the present invention is to provide a multiplier, which can multiply a plurality of pairs of data at one time without increase in the consumption of electrical power and increase in the circuit scale. This object is solved by a multiplier according to claim 1. Further embodiments of the invention are listed in the dependent claims. According to a first aspect of the present invention, there is provided a multiplier using Booth's algorithm comprising a first Booth's decoder for inputting a host word of a multiplicand thereto; a second Booth's decoder for inputting a lower word of the multiplicand thereto; multiplicand dividing means for inputting the most significant bit of the lower word of the multiplicand or "0" to an input terminal of the least significant bit of the first Booth's decoder; zeroising means for replacing a part of partial products with "0"; and bit extension means for replacing the other part of the partial products with one bit of the partial products of lower bits than the other part of the partial products. The most significant bit of the lower word of the multiplicand is inputted to an input terminal of the least significant bit of the first Booth's decoder by the multiplicand dividing means, and the zeroising means and the bit extension means are not functioned, whereby multiplying a single precision or that of a double precision. When a 1 and a 0 are inputted to the host word of the multiplier and the lower word, respectively, b 0 and b 1 are inputted to the host word of the multiplicand and the lower word, respectively, "0" is inputted to the input terminal of the least significant bit of the first Booth's decoder by the multiplicand dividing means, and the zeroising means and the bit extension means are functioned, whereby obtaining inner products of vector A = (a 0 , a 1 ) and vector B (b 0 , b 1 ). According to a second aspect of the present invention a multiplier using Booth's algorithm comprises: a first Booth's decoder for inputting a host word of a multiplicand thereto; a second Booth's decoder for inputting a lower word of the multiplicand thereto; multiplicand complementing means for inputting "0" or "1" to an input terminal of the least significant bit of the second Booth's decoder, and for inputting the lower word of the multiplicand or the reversed signal to the second Booth's decoder; multiplicand dividing means for inputting the most significant bit of the lower word of the multiplicand or "0" to the input terminal of the least significant bit of the first Booth's decoder; zeroising means for replacing a part of partial products with "0"; and bit extension means for replacing the other part of the partial products with one bit of the partial products of lower bits than the other part of the partial products. When, b and a are inputted to the host word of the multiplier and the lower word of the multiplier, respectively, c and d are inputted to the host word of the multiplicand and the lower word of the multiplicand, respectively, "1" is inputted to the input terminal of the least significant bit of the second Booth's decoder by the multiplicand complementing means, the reversed signal of the lower word of the multiplicand is inputted to the second Booth's decoder by the multiplicand complementing means, "0" is inputted to the input terminal of the least significant bit of the first Booth's decoder by the multiplicand dividing means, and the zeroising means and the bit extension means are functioned, whereby a real part of the products of two complex numbers F = a + jb and G = c + jd is calculated. When, a and b are inputted to the host word of the multiplier and the lower word of the multiplier, respectively, c and d are inputted to the host word of the multiplicand and the lower word of the multiplicand, respectively, "0" is inputted to the input terminal of the least significant bit of the second Booth's decoder by the multiplicand complementing means, the lower word of the multiplicand is inputted to the second Booth's decoder by the multiplicand complementing means, "0" is inputted to the input terminal of the least significant bit of the first Booth's decoder by the multiplicand dividing means, and the zeroising means and the bit extension means are functioned, whereby an imaginary part of the products of two complex numbers F = a + jb and G = c + jd is calculated. According to a third aspect of the present invention, a multiplier using Booth's algorithm comprises: a first Booth's decoder for inputting a host word of a multiplicand thereto; a second Booth's decoder for inputting a lower word of the multiplicand thereto; multiplicand dividing means for inputting the most significant bit of the lower word of the multiplicand or "0" to the input terminal of the least significant bit of the first Booth's decoder; reversing means for inputting the host word of the multiplicand or the reversed signal to the first Booth's decoder; zeroising means for replacing a part of partial products with "0"; and bit extension means for replacing the other part of the partial products with one bit of the partial products of lower bits than the other part of the partial products. When, a and b are inputted to the host word of the multiplier and the lower word of the multiplier, respectively, d and c are inputted to the host word of the multiplicand and the lower word of the multiplicand, respectively, a reserved signal of the host word of the multiplicand is inputted to the first Booth's decoder by the multiplicand complementing means, "1" is inputted to the input terminal of the least significant bit of the first Booth's decoder by the multiplicand reversing means, and the zeroising means and the bit extension means are functioned, whereby a real part of the products of two complex numbers F = a + jb and G = c + jd is calculated. When, a and b are inputted to the host word of the multiplier and the lower word of the multiplier, respectively, c and d are inputted to the host word of the multiplicand and the lower word of the multiplicand, respectively, the host word of the multiplicand is inputted to the first Booth's decoder by the multiplicand reversing means, "0" is inputted to the input terminal of the least significant bit of the first Booth's decoder by the multiplicand dividing means, and the zeroising means and the bit extension means are functioned, whereby an imaginary part of the products of two complex numbers F = a + jb and G = c + jd is calculated. According to the above-mentioned aspects of the present invention, the part of the partial products generated in the multiplier is zeroising, and the other part of the partial products is replaced with one bit of the partial products lower than the other part of the partial products, whereby the plurality of pairs of data can be multiplied by one multiplier. Moreover, since multiplication of a plurality of pairs of data can be performed at one time, not only normal multiplication but also the double precision multiplication, the inner product of the vector, and the complex multiplication can be performed by one multiplier. In a case that the multiplier of the present invention is incorporated into the processor, the above all calculations can be performed by a single machine cycle, so that the number of steps of program can be reduced. Particularly, the number of steps can be reduced to about 1/2 of the conventional case in the signal processing program in which the calculation of the sum of product is mainly performed. Moreover, in a case where the calculation through put is the same, the machine cycle is set to be longer than the conventional case, and the consumption of the electrical power of the entire processor can be reduced. Particularly, in the digital signal processor in which the signal processing is dedicatedly performed, the consumption of the electrical power can be reduced to about 1/2 of the conventional case. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIGS. 1A and 1B are block diagrams showing a conventional multiplier; FIG. 2 is a circuit diagram showing one example of a Booth's decoder 1 used in the conventional multiplier; FIG. 3 is a circuit diagram showing one example of a Booth's decoder 2 used in the conventional multiplier; FIGS. 4A and 4B are block diagrams showing a multiplier of a first embodiment of the present invention; FIG. 5 is a circuit diagram showing one example of a selector 10 used in the multiplier of the present invention; FIGS. 6A and 6B are block diagrams showing a multiplier of a second embodiment of the present invention; and FIGS. 7A and 7B are block diagrams showing a multiplier of a third embodiment of the present invention. The multiplier of the present invention will be explained with reference to the drawings. [A] First Embodiment FIGS. 4A and 4B show a multiplier of a first embodiment of the present invention. In FIGS. 4A and 4B, 1A to 1D are Booth's decoders, 2: a Booth's selector, 3: a parallel addition circuit for adding partial products, 7A and 7B: AND gates, and 10: a selector. FIG. 5 is a circuit diagram showing one example of the selector 10 used in the multiplier of the present invention. In FIG. 5, 5: a NOR gate, 7C and 7D: AND gates, and 8: an inverter. Host words Y 7 to Y 4 of an multiplicand are inputted to the Booth's decoders 1A and 1B. More specifically, the respective bits Y 7 to Y 5 of the multiplicand are inputted to the Booth's decoder 1A, the respective bits Y 5 to Y 4 of the multiplicand are inputted to the Booth's decoder 1B. The AND circuit (multiplicand dividing means) 7A serves to input the most significant bit Y 3 of the lower words Y 3 to Y 0 of the multiplicand or "0" to an input terminal of the least significant bit of the Booth's decoder 1B. A control signal S 1 controls to output whether the most significant bit Y 3 of the lower words of the multiplicand or "0." The lower words Y 3 to Y 0 of the multiplicand are inputted to the Booth's decoders 1C and 1D. More specifically, the respective bits Y 3 to Y 1 of the multiplicand are inputted to the Booth's decoder 1C, the respective bits Y 1 to Y 0 of the multiplicand and "0" are inputted to the Booth's decoder 1D. The AND circuit (zeroising means) 7B replaces a part of the partial products, for example, P 03 to P 00 , P 13 to P 10 , with "0." In other words, if the control signal S 1 is set to "0", all output signals of the NAND circuit 7B are "0", and the part of the partial products (P 03 to P 00 , P 13 to P 10 ) are changed to "0." The selector (bit extending means) 10 replaces the other part of the partial products, for example, P 28 to P 25 with one bit of the partial products (P 24 ) of the lower bits. Moreover, the selector 10 replaces the other part of the partial products, for example, P 38 to P 35 with one bit of the partial products (P 34 ) of the lower bits. In other words, when the control signal S 1 is "0", the selector 10 selects a multiplier X 3 , and outputs the multiplier X 3 . As a result, the other part of the partial products (P 28 to P 24 , P 38 to P 34 ) are changed to X 3 or X 3 . The following will explain an operation of the multiplier of FIGS. 4A and 4B. As shown in equations (5) and (6), each of the multiplier X and the multiplicand Y is divided to the host word and the lower word. (Multiplier) X = X H + X L (Multiplicand) Y = Y H + Y L At this time, a product Z can be expressed by equation (7) (Product) Z = (X H + X L ) (Y H + Y L ) = X H Y H + X H Y L + X L Y H + X L Y L The host word X 7-4 of the multiplier of FIG. 4 corresponds to X H , and the lower word X 3-0 corresponds to X L . The host word Y 7-4 of the multiplicand of FIGS. 4A and 4B corresponds to Y H , and the lower word X 3-0 corresponds to Y L . Also, S 1 is a control signal. According to this embodiment, input data is processed word by word, and the control signal S 1 is switched, thereby making it possible to execute three types of multiplications, that is, a single precision, a double precision, and an inner product. The following will explain the multiplications of the single, double precision, and inner product in order. [Single Precision] First of all, the lower words X L and Y L of the multiplier and the multiplicand are set to X L = "0" and Y L = "0", second to fourth terms of equation (7) are all "0." To obtain X L = "0" and Y L = "0", the lower word X 3-0 of the multiplier and the lower word Y 3-0 of the multiplicand may be respectively set to "0" wherein the control signal S 1 = "1" in FIGS. 4A and 4B. At this time, the product Z can be expressed by the following equation (8). (Single precision) Z = X H Y H When the control signal S 1 = "1", the multiplier of this embodiment performs the same operation as the conventional multiplier of FIGS. 1A and 1B. In other words, each selector 10 selects input data X 7 , X 6 , X 5 , and X 4 , and each of the AND gates 7A and 7B directly outputs the level of the other input signal since the control signal S1, which is inputted to one input terminal, is "1." Under this state, if the host word X H of the multiplier and the host word Y H of the multiplicand, that is, X 7-4 and Y 7-4 are set to 4 bit single precision data, the multiplication result of the single precision can be obtained. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 14 and Z 13 . When input data is integer data, the position of the decimal point of output data is placed between Z 8 and Z 7 . [Double Precision] The calculation is directly performed based on equation (7). If the control signal S 1 = "1", the multiplier of this embodiment performs the same operation as the conventional multiplier of FIGS. 1A and 1B. Due to this, if X 7-0 and Y 7-0 are set to 8 bit double precision data, respectively, the multiplication result (output data) of the double precision can be obtained. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 14 and Z 13 . When input data is integer data, the position of the decimal point of output data is placed right below Z 0 . [Inner Product] The inner products of two vectors, A = (a 0 , a 1 ) and B = (b 0 , b 1 ) can be calculated as follows. First of all, in equation (7), the multiplication is performed in the following condition (equation (9)). X H = a 1 , X L = a 0 , Y H = b 0 , Y L = b 1 As a result, the following equation (10) can be obtained. Z = a 1 b 0 + a 1 b 1 + a 0 b 0 + a 0 b 1 In equation (10), if the first and fourth terms are set to "0" in the multiplier, the following equation (11) can be obtained and the inner products of the vectors A and B are calculated. (Inner Product) Z = a 1 b 1 + a 0 b 0 In order to execute equation (9), a 1 and a 0 are inputted to the host word X 7-4 of the multiplier and the lower word X 3-0 , respectively, as four bit data. Moreover, b 0 and b 1 are inputted to the host word Y 7-4 of the multiplicand and the lower word Y 3-0 , respectively, as four bit data. The operation in which the first and fourth terms are set to "0" in the multiplier in equation (10) corresponds to the point that the signal control is set to S 1 = "0." At this time, the AND gates 7A and 7B output "0", and the selector 10 outputs an sign bit X 3 of the lower word X L of the multiplier. Therefore, both right and left input signals L and R of the selector 2 of the Booth's, which generates the partial products P 03 to P 00 , P 13 to P 10 corresponding to the X L Y L = a 0 b 1 , become "0." Moreover, both right and left input signals L and R of the Booth's selector 2 which generates the partial products P 28 to P 24 , P 38 to P 34 corresponding to the X H Y H = a 1 b 0 , become the sign bit X 3 or X 3 . Moreover, in place of Y 3 , "0" is inputted to the input terminal of the least significant bit input Y m-1 of the Booth's decoders 1A and 1B to which the host word Y H = b 0 of the multiplicand Y is inputted. Due to this, the host word Y H = b 0 of the multiplicand Y and the lower word Y L = b 1 are decoded as an independent 4-bit value. As a result, the first and fourth terms of equation (7), that is, the first and fourth terms of equation (10) become "0", and the value of equation (11) is outputted. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 10 and Z 9 . When input data is integer data, the position of the decimal point of output data is placed between Z 4 and Z 3 . The above point means that no overflow is generated in the calculation of the inner product. More specifically, in general, there is possibility that overflow will be generated one bit in the multiplication and one bit in addition. Since two multiplications and one addition are performed in the calculation of the inner product, the number of digits of the overflow is 3 bits in all. According to the present invention, the sign extension of the host bit rather than the sign bit is performed by the number of bits of each of host and lower words. Therefore, if the number of bits of each word is larger than two bits, no overflow is generated. [B] Second Embodiment FIGS. 6A and 6B show a multiplier of a second embodiment of the present invention. In FIGS. 6A and 6B, reference numeral 11 is an exclusive OR gate, and S 2 is a control signal. The same reference numerals are added to the same structural elements as FIGS. 4A and 4B, and the explanation is omitted. The host words Y 7 to Y 4 of the multiplicand are inputted to the Booth's decoders 1A and 1B. More specifically, the respective bits Y 7 to Y 5 of the multiplicand are inputted to the Booth's decoder 1A, and the respective bits Y 5 to Y 4 of the multiplicand are inputted to the Booth's decoder 1B. The AND circuit (multiplicand dividing means) 7A serves to input the most significant bit Y 3 of the lower words Y 3 to Y 0 of the multiplicand or "0" to the input terminal of the least significant bit of the Booth's decoder 1B. The control signal S 1 controls whether the AND circuit 7A outputs whether the most significant bit Y 3 of the lower words of the multiplicand or "0." The lower words Y 3 to Y 0 of the multiplicand and a control signal S 2 are inputted to the Booth's decoders 1C and 1D. More specifically, the respective bits Y 3 to Y 1 of the multiplicand are inputted to the Booth's decoder 1C, and the respective bits Y 1 to Y 0 of the multiplicand and the control signal S 2 are inputted to the Booth's decoder 1D. The control signal S 2 ("0" or "1") is inputted to the input terminal of the least significant bit of the Booth's decoders 1C and 1D. The exclusive OR gate (multiplicand complementing means) 11 has a function for inputting the lower words Y 3 to Y 0 of the multiplicand or the reverse signal are inputted to the Booth's decoders 1C and 1D. The exclusive OR gate 11 is controlled by the control signal S 2 . The AND circuit (zeroising means) 7B replaces a part of the partial products, for example, P 03 to P 00 , P 13 to P 10 , with "0." In other words, if the control signal S 1 is set to "0", all output signals of the AND circuit 7B are "0", and the part of the partial products (P 03 to P 00 , P 13 to P 10 ) are changed to "0." The selector (bit extending means) 10 replaces the other part of the partial products, for example, P 28 to P 25 with one bit of the partial products (P 24 ) of the lower bits. Moreover, the selector 10 replaces the other part of the partial products, for example, P 38 to P 35 with one bit of the partial products (P 34 ) of the lower bits. In other words, when the control signal S 1 is "0", the selector 10 selects the multiplier X 3 , and outputs the multiplier X 3 . As a result, the other part of the partial products (P 28 to P 24 , P 38 to P 34 ) are changed to X 3 or X 3 . The following will explain an operation of the multiplier of FIGS. 6A and 6B. According to the multiplier of this embodiment, when the control signal S2 is "0", the same operation as the multiplier of FIG. 4A and 4B is performed. However, when the control signal S2 is "1", the code of the lower word YL of the multiplicand Y is reversed. By use of this point, the complex multiplication is executed. It is assumed that the product of the following two complex numbers will be calculated. F = a + jb G = c + jd [Real part] A real part of the product can be calculated as follow. First of all, in equation (7), the multiplication is performed in the following condition (equation (12)). X H = b, X L = a, Y H = c, Y L = -d. As a result, the following equation (13) can be obtained. Z = bc + b (-d) + ac + a (-d) If the first and fourth terms of equation (13) are set to "0" in the multiplier, the following equation (14) can be obtained, and the real part of the product of the complex numbers F and G is calculated. (Real part) Z = ac - bd In order to execute equation (12), b is inputted to the host word X 7-4 of the multiplier, a is inputted to the lower word X 3-0 , c is inputted to the host word Y 7-4 of the multiplicand, and d is inputted to the lower word Y 3-0 of the multiplicand, respectively, as four bit data. Moreover, S 2 may be set to S 2 = "1." If the control signal S 2 is set to "1", the code of each bit of the lower word Y 3-0 (Y L = d) of the multiplicand is reversed by the exclusive OR gate 11, and S 2 = "1" is inputted to the least significant bit Y m-1 of the Booth's decoders 1C and 1D to which the lower word Y 3-0 of the multiplicand is inputted. In other words, the code of the lower word Y 3-0 (Y L = d) of the multiplicand is reversed to Y L = -d. The above method for reversing the code of the multiplicand is disclosed in, for example, United States Patent No. 4,813,008. The operation of setting the first and fourth terms of equation (13) to "0" corresponds to the operation of setting the control signal S 1 of the internal of the multiplier to "0." At this time, the AND gates 7A and 7B output "0", and the selector 10 outputs the code bit X 3 of the lower word X L of the multiplier. Therefore, "0" is inputted to each of the right and left inputs L and R of the Booth's selector 2 for generating the partial products P 03 to P 00 and P 13 to P 10 corresponding to X L Y L = a (-d). Also, code bit X 3 is inputted to each of the right and left inputs L and R of the Booth's selector 2 for generating the partial products P 28 to P 24 and P 38 to P 34 corresponding to X H Y H = bc. Moreover, in place of Y 3 , "0" is inputted to the least significant bit input Y m-1 of the decoders 1A and 1B of the Booth's to which the host words Y 7 to Y 4 of the multiplicand are inputted. Therefore, the host word Y H = c of the multiplicand and the lower word Y L = d are decoded as an independent four bit value. As a result, the first and fourth terms of equation (7), that is, the first and fourth terms of equation (13) become "0", and a value of equation (14) is outputted. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 10 and Z 9 . When input data is integer data, the position of the decimal point of output data is placed between Z 4 and Z 3 . In this case, the sign extension of the host bit rather than the sign bit is performed by the number of bits of each word. Therefore, if the number of bits of each word is larger than two bits, no overflow is generated. [Imaginary part] An imaginary part of the product can be calculated as follow. First of all, in equation (7), the multiplication is performed in the following condition (equation (15)). X H = a, X L = b, Y H = c, Y L = d. As a result, the following equation (16) can be obtained. Z = ac + ad + bc + bd If the first and fourth terms of equation (16) are set to "0" in the multiplier, the following equation (17) can be obtained and the imaginary part of the products of the complex numbers F and C are calculated. (Imaginary part) Z = ad + bc In order to execute equation (15), a is inputted to the host word X 7-4 of the multiplier, b is inputted to the lower word X 3-0 of the multiplier, c is inputted to the host word Y 7-4 of the multiplicand, and d is inputted to the lower word Y 3-0 of the multiplicand, respectively, as four bit data. Moreover, S 2 may be set to S 2 = "0." If the control signal S 2 is set to "0", the exclusive OR gate 11 directly outputs the level of the lower word Y 3-0 of the multiplicand, and S 2 = "0" is inputted to the least significant bit Y m-1 of the Booth's decoders 1C and 1D to which the lower word Y 3-0 of the multiplicand is inputted. In other words, the code of the lower word Y 3-0 (Y L = d) of the multiplicand is not reversed. The operation of setting the first and fourth terms of equation (16) to "0" corresponds to the operation of setting the control signal S 1 of the internal of the multiplier to "0." At this time, the AND gates 7A and 7B output "0", and the selector 10 outputs the code bit X 3 of the lower word X L of the multiplier. Therefore, "0" is inputted to both right and left inputs L and R of the Booth's selector 2 for generating the partial products P 03 to P 00 and P 13 to P 10 corresponding to X L Y L = bd. Also, code bit X 3 is inputted to both right and left inputs L and R of the Booth's selector 2 for generating the partial products P 28 to P 24 and P 38 to P 34 corresponding to X H Y H = ac. Moreover, in place of Y 3 , "0" is inputted to the least significant bit input Y m-1 of the Booth's decoders 1A and 1B to which the host words Y H of the multiplicand is inputted. Therefore, the host word Y H = c of the multiplicand and the lower word Y L = d are decoded as an independent four bit value. As a result, the first and fourth terms of equation (7), that is, the first and fourth terms of equation (16) become "0", and a value of equation (17) is outputted. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 10 and Z 9 . When input data is integer data, the position of the decimal point of output data is placed between Z 4 and Z 3 . In this case, if the number of bits of each word is larger than two bits, no overflow is generated. [B] Third Embodiment FIGS. 7A and 7B show a multiplier of a third embodiment of the present invention. In FIG. 7A and 7B, reference numeral 6 is an OR gate, and S 2 is a control signal. The same reference numerals are added to the same structural elements as the multiplier of FIGS. 4 and 6, and the explanation is omitted. The host words Y 7 to Y 4 of the multiplicand are inputted to the Booth's decoders 1A and 1B. More specifically, the respective bits Y 7 to Y 5 of the multiplicand are inputted to the Booth's decoder 1A, and the respective bits Y 5 to Y 4 of the multiplicand are inputted to the Booth's decoder 1B. The OR circuit (multiplicand dividing means) 6 and the AND circuit (multiplicand dividing means) 7A serve to input the most significant bit Y 3 of the lower words Y 3 to Y 0 of the multiplicand or "0" to the input terminal of the least significant bit of the Booth's decoder 1B. The control signals S 1 and S 2 control whether the AND circuit 7A outputs whether the most significant bit Y 3 of the lower words of the multiplicand or "0." The lower words Y 3 to Y 0 of the multiplicand and "0" are inputted to the Booth's decoders 1C and 1D. More specifically, the respective bits Y 3 to Y 1 of the multiplicand are inputted to the Booth's decoder 1C, and the respective bits Y 1 to Y 0 of the multiplicand and "0" are inputted to the Booth's decoder 1D. The exclusive OR gate (multiplicand complementing means) 11 has a function for inputting the host words Y 7 to Y 4 of the multiplicand or the reverse signal are inputted to the Booth's decoders 1A and 1B. The exclusive OR gate 11 is controlled by the control signal S 2 . The AND circuit (zeroising means) 7B replaces a part of the partial products, for example, P 03 to P 00 , P 13 to P 10 , with "0." In other words, if the control signal S 1 is set to "0", all output signals of the AND circuit 7B are "0", and the part of the partial products (P 03 to P 00 , P 13 to P 10 ) are changed to "0." The selector (bit extending means) 10 replaces the other part of the partial products, for example, P 28 to P 25 with one bit of the partial products (P 24 ) of the lower bits. Moreover, the selector 10 replaces the other part of the partial products, for example, P 38 to P 35 with one bit of the partial products (P 34 ) of the lower bits. In other words, when the control signal S 1 is "0", the selector 10 selects the multiplier X 3 , and outputs the multiplier X 3 . As a result, the other part of the partial products (P 28 to P 24 , P 38 to P 34 ) are changed to X 3 or X 3 . The following will explain an operation of the multiplier of FIGS. 7A and 7B. According to the multiplier of this embodiment, when the control signal S 2 is "0", the same operation as the multiplier of FIGS. 4A and 4B is performed. However, when the control signal S 2 is "1", the code of the lower word Y L of the multiplicand Y is reversed. By use of this point, the complex multiplication is executed. It is again assumed that the product of the following two complex numbers will be calculated. F = a + jb G = c + jd [Real part] A real part of the product can be calculated as follow. First of all, in equation (7), the multiplication is performed in the following condition (equation (18)). X H = a, X L = b, Y H = -d, Y L = c. As a result, the following equation (19) can be obtained. Z = a (-d) + ac + b (-d) + bc If the first and fourth terms of equation (19) are set to "0" in the multiplier, the following equation (20) can be obtained, and the real part of the products of the complex numbers F and G are calculated. (Real part) Z = ac - bd In order to execute equation (18), a is inputted to the host word X 7-4 of the multiplier, b is inputted to the lower word X 3-0 , d is inputted to the host word Y 7-4 of the multiplicand, and c is inputted to the lower word Y 3-0 of the multiplicand, respectively, as four bit data. Moreover, S 2 may be set to S 2 = "1." If the control signal S 2 is set to "1", each bit of the host word Y 7-4 (Y H = d) of the multiplicand is reversed by the exclusive OR gate 11, and the output (= "1") of the OR gate 6 is inputted to the least significant bit Y m-1 of the Booth's decoder 1 to which the host word Y 7-4 of the multiplicand is inputted. In other words, the code of the host word Y 7-4 (Y H = d) is reversed to Y H = -d. The operation of setting the first and fourth terms of equation (19) to "0" corresponds to the operation of setting the control signal S 1 of the internal of the multiplier to "0." At this time, the AND gates 7A and 7B output "0", and the selector 10 outputs the code bit X 3 of the lower word X L of the multiplier. Therefore, "0" is inputted to each of the right and left inputs L and R of the Booth's selector 2 for generating the partial products P 03 to P 00 and P 13 to P 10 corresponding to X L Y L = bc. Also, code bit X 3 is inputted to each of the right and left inputs L and R of the selector 2 of the Booth's for generating the partial products P 28 to P 24 and P 38 to P 34 corresponding to X H Y H = a(-d). Moreover, in place of Y 3 , "1" is inputted to the least significant bit input Y m-1 of the Booth's decoder to which the host words Y 7 to Y 4 of the multiplicand are inputted. Therefore, the host word Y H = d of the multiplicand and the lower word Y L = c are decoded as an independent four bit value. As a result, the first and fourth terms of equation (7), that is, the first and fourth terms of equation (19) become "0", and a value of equation (20) is outputted. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 10 and Z 9 . When input data is integer data, the position of the decimal point of output data is placed between Z 4 and Z 3 . If the number of bits of each word is larger than two bits, no overflow is generated. [Imaginary part] An imaginary part of the product can be calculated in the same manner as the embodiment of FIG. 6. First of all, in equation (7), the multiplication is performed in the following condition (equation (15')). X H = a, X L = b, Y H = c, Y L = d. As a result, the following equation (16') can be obtained. Z = ac + ad + bc + bd If the first and fourth terms of equation (16') are set to "0" in the multiplier, the following equation (17') can be obtained and the imaginary part of the products of the complex numbers F and C are calculated. (Imaginary part) Z = ad + bc In order to execute equation (15'), a is inputted to the host word X 7-4 of the multiplier, b is inputted to the lower word X 3-0 of the multiplier, c is inputted to the host word Y 7-4 of the multiplicand, and d is inputted to the lower word Y 3-0 of the multiplicand, respectively, as four bit data. Moreover, S 2 may be set to S 2 = "0." If the control signal S 2 is set to "0", the exclusive OR gate 11 directly outputs the level of the lower word Y 3-0 of the multiplicand, and S 2 = "0" is inputted to the least significant bit Y m-1 of the Booth's decoders 1C and 1D to which the lower word Y 3-0 of the multiplicand is inputted. In other words, the code of the lower word Y 3-0 (Y L = d) of the multiplicand is not reversed. The operation of setting the first and fourth terms of equation (16') to "0" corresponds to the operation of setting the control signal S 1 of the internal of the multiplier to "0." At this time, the AND gates 7A and 7B output "0", and the selector 10 outputs the code bit X 3 of the lower word X L of the multiplier. Therefore, "0" is inputted to both right and left inputs L and R of the Booth's selector 2 for generating the partial products P 03 to P 00 and P 13 to P 10 corresponding to X L Y L = bd. Also, code bit X 3 is inputted to both right and left inputs L and R of the Booth's selector 2 for generating the partial products P 28 to P 24 and P 38 to P 34 corresponding to X H Y H = ac. Moreover, in place of Y 3 , "0" is inputted to the least significant bit input Y m-1 of the Booth's decoders 1A and 1B to which the host words Y H of the multiplicand is inputted. Therefore, the host word Y H = c of the multiplicand and the lower word Y L = d are decoded as an independent four bit value. As a result, the first and fourth terms of equation (7), that is, the first and fourth terms of equation (16') become "0", and a value of equation (17') is outputted. When input data is fixed-point data, the position of the decimal point of output data is placed between Z 10 and Z 9 . When input data is integer data, the position of the decimal point of output data is placed between Z 4 and Z 3 . In this case, if the number of bits of each word is larger than two bits, no overflow is generated. According to the present invention, the number of pairs of data to be multiplied is not limited to two pairs, and three or more pairs of data may be multiplied. According to the multiplier of the present invention, since multiplication of a plurality of pairs of data can be performed at one time, not only normal multiplication but also the double precision multiplication, the inner product of the vector, and the complex multiplication can be performed by one multiplier. In a case that the multiplier of the present invention is incorporated into the processor, the above all calculations can be performed by a single machine cycle, so that the number of steps of program can be reduced. Particularly, the number of steps can be reduced to about 1/2 of the conventional case in the signal processing program in which the calculation of the sum of product is mainly performed. Conversely, in a case where the calculation through put is the same, the machine cycle is set to be longer than the conventional case, and the consumption of the electrical power of the entire processor can be reduced. Particularly, in the digital signal processor in which the signal processing is dedicatedly performed, the consumption of the electrical power can be reduced to about 1/2 of the conventional case.

Claims: A multiplier using Booth's algorithm for multiplying a multiplier (X) and a multiplicand (Y) each including a predetermined number of bits, said multiplier and said multiplicand each consisting of a lower word (X3-X0; Y3-Y0) including a first subset (X3-Y0; Y3-Y0) of bits counted from the least significand bit (X0, Y0) and of a host word (X7-X4; Y7-Y4) including the bits of said multiplier and multiplicand not contained in the respective first subset of bits, comprising: a) a first Booth's decoder (1A, 1B) receiving as input said host word of said multiplicand; b) a second Booth's decoder (1C, 1D) receiving as input the lower word of said multiplicand; c) a first to fourth Booth's selector arrays (P00-P03, P10-P13; P04-P08, P14-P18; P20-P23, P30-P33; P24-P28, P34-P38), c1) said first Booth's selector array (P00-P03; P10-P13) including first selectors (2) adapted to produce partial products (P00-P03; P10-P13) dependent on the output of said second Booth's decoder (1C, 1D) and the bits of said lower word (X3-X0) of said multiplier; c2) said second Booth's selector array (P04-P08, P14-P18) including second selectors (2) adapted to produce partial products (P04-P08, P14-P18) dependent on the output of said second Booth's decoder (1C, 1D) and the bits of said host word (X7-X4) of said multiplier; c3) said third Booth's selector array (P20-P23, P30-P33) including third selectors (2) adapted to produce partial products (P20-P23, P30-P33) dependent on the output of said first Booth's decoder (1A, 1B) and the bits of said lower word (X3-X0) of said multiplier; and c4) said fourth Booth's selector array (P14-P28, P34-P38) including fourth selectors (2) adapted to produce partial products (P24-P28, P34-P38) dependent on the output of said first Booth's decoder (1A, 1B) and the bits of said host word (X7-X4) of said multiplier; characterized by d) a multiplicand dividing means (7A) for receiving a control signal (S1) and for inputting to an input terminal of said first Booth's decoder (1A, 1B), where the least significant bit (Y4) of the host word is input the most significant bit (Y3) of said lower word (Y3-Y0) of said multiplicand when said control signal (S1) has a first level ( 1 ), and "0" when said control signal (S1) has a second level ( 0 ); e) a zeroising means (7B) for receiving said control signal (S1) and for applying a "0" to the first selectors (2) of said first Booth's selector array (P03-P00; P13-P10), when said control signal (S1) has said second level (0); f) a bit extension means (10) for receiving said control signal (S1) and for applying to the fourth selectors (2) of said fourth Booth's selector array (P24-P28, P34-P38) the most significant bit (X3) of the lower word (X3-X0) of said multiplier (X7-X0), when said control signal (S1) has said second level (0); wherein g) all said generated partial products (P00-P38) are provided to an adder (3) for addition in order to obtain the multiplication result (Z0-Z14). A multiplier using Booth's algorithm according to claim 1, characterized in that when said control signal (S1) has said first level (1) and said multiplicand dividing means (7A) inputs the most significant bit (Y3) of said lower word (Y3-Y0) of said multiplicand to said input terminal of said first Booth's decoder (1A, 1B) where the least significant bit (Y4) of the host word is input, said adder (3) outputs a single precision or double precision multiplication result (Z). A multiplier using Booth's algorithm according to claim 1, characterized in that when a set of bits a 1 and a set of bits a 0 are input to the host word and the lower word of said multiplier, respectively, and a set of bits b 0 and a set of bits b 1 are input to the host word and the lower word of said multiplicand, respectively, and said control signal (S1) has said second level (0) and said multiplicand dividing means (7A) inputs "0" to said input terminal of said first Booth's decoder (1A, 1B) where the least significant bit (Y4) of the host word is input, said adder (3) outputs as a multiplication result (Z) an inner product of the vector A =(a 0 , a 1 ) and B =(b 0 , b 1 ). A multiplier using Booth's algorithm according to claim 1, characterized by a multiplicand complementing means (11) for inputting "0" or "1" to an input terminal of the least significant bit of said second Booth's decoder, and for inputting the lower word of the multiplicand or the reversed signal to said second Booth's decoder (1C, 1D). A multiplier using Booth's algorithm according to claim 4, characterized in that when a set of bits b and a set of bits a are input to the host word and the lower word of said multiplier, respectively, and a set of bits c and a set of bits d are input to the host word and the lower word of said multiplicand, respectively, "1" is input to the input terminal of the least significant bit of said second Booth's decoder (1C, 1D) by said multiplicant complementing means (11), the reversed signal of the lower word of the multiplicand is input to the second Booth's decoder (1C, 1D) by said multiplicand complementing means (11), "0" is input to the input terminal of the least significant bit of said first Booth's decoder (1A, 1B) by said multiplicant dividing means (7A) and said control signal (S1) has said second level (0), said adder (3) outputs as a multiplication result (Z) the real part of a multiplication of the two complex numbers F = a + jb and G = c + jd. A multiplier using Booth's algorithm according to claim 4, characterized in that when a set of bits a and a set of bits b are input to the host word and the lower word of said multiplier, respectively, and a set of bits c and a set of bits d are input to the host word and the lower word of said multiplicand, respectively, "0" is input to the input terminal of the least significant bit of said second Booth's decoder (1C, 1D) by said multiplicand complementing means (11), the lower word of the multiplcand is input to said second Booth's decoder by said multiplicand complementing means (11), "0" is input to the input terminal of the least significant bit of said first Booth's decoder (1A, 1B) by said multiplicand dividing means (7A) and said control signal (S1) has said second level (0), said adder (3) outputs as a multiplication result (Z) the imaginary part of a multiplication of the two complex numbers F = a + jb and G = c + jd. A multiplier using Booth's algorithm according to claim 1, characterized by a multiplicand reversing means (11, 6) for inputting the host word of the multiplicand or the reversed signal to said frist Booth's decoder. A multiplier using Booth's algorithm according to claim 7, characterized in that when a set of bits a and a set of bits b are input to the host word and the lower word of said multiplier, respectively, and a set of bits d and a set of bits c are input to the host word and the lower word of said multiplicand, respectively, a reversed signal of said host word of the multiplicand is input to said first Booth's decoder (1A, 1B) by said multiplicant reversing means (11, 6), "1" is input to the input terminal of the least significant bit of said first Booth's decoder (1A, 1B) by said multiplicand reversing means (11,6) and said control signal (S1) has said second level (0), said adder (3) outputs as a multiplication result (Z) the real part of a multiplication of the two complex numbers F = a + jb and G = c + jd. A multiplier using Booth's algorithm according to claim 7, characterized in that when a set of bits a and a set of bits b are input to the host word and the lower word of said multiplier, respectively, and a set of bits c and a set of bits d are input to the host word and the lower word of said multiplicand, respectively, said host word of the multiplicand is input to said first Booth's decoder (1A, 1B) by said multiplicand reversing means (11, 6), "0" is input to the input terminal of the least significant bit of said first Booth's decoder (1A, 1B) by said multiplicand dividing means (7A) and said control signal (S1) has said second level (0), said adder (3) outputs as a multiplication result (Z) the imaginary part of a multiplication of the two complex numbers F = a + jb and G = c + jd.

Inventors: SHIRAISHI MIKIO, SHIRAISHI, MIKIO, SHIRAISHI, MIKIO, C/O INTELLECTUAL PTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: G06F7
IPC codes: G06F7