DIGITALLY PHASE MODULATED CLOCK EXHIBITING REDUCED RF EMISSIONS

Abstract: A modulator for a clock pulse generator receives clock pulses from a clock pulse source (18, 32), which clock pulses exhibit a reference phase. Delay circuitry (10) is connected to the clock pulse source (18) and includes n tap connections (20, 22, 24, 40), each connection providing a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer (34) is connected to each of the n tap connections (20, 22, 24, 40) and provides an output manifesting the clock pulses. A selector circuit (26) controls the multiplexer (34) to sequentially connect any sequence of different ones of the n tap connections (20, 22, 24, 40) to the multiplexer's output (28), whereby the output (28) manifests a series of clock pulses which have different phase displacements from the reference phase.

Description: This invention relates to digital clock frequency generating circuits and, more particularly, to a modulator for modulating the output of a clock generator in such a manner as to cause a reduction in emitted radio frequency interference. Radio frequency interference (RFI) is a known problem in digital circuitry and efforts are continually being addressed to its reduction. RFI is known to be generated by higher harmonics of the basic clock frequency. In such case, the clock frequency energy is distributed and segregated into specific, narrow bands about each harmonic frequency. It is known that RFI can be reduced by causing the energy in the higher harmonics of the clock frequency to be more evenly distributed about the side bands adjoining the harmonic frequencies. Such distribution can be achieved by varying the phase of succeeding clock pulses so as to assure a continued modulation thereof and a resultant distribution of harmonic energy into adjacent sidebands. Voltage controlled oscillators have been utilized to generate master clock signals. The prior art has attempted to reduce the RFI of such clock signals by modulating the voltage controlled oscillator so as to cause a variation in the system clock frequency. This modulation causes a spreading of the clock signal energy across the spectrum, with the extent of the sidebands defined by the modulating frequency. However, since the voltage controlled oscillator is not locked to a specific reference, its output center frequency tends to wander as a result temperature and other environmental affects. To prevent such frequency variation, voltage controlled oscillators have been locked to a crystal controlled frequency source; however, this prevented the use of an RFI reduction technique. Phase locked loops have been employed to accomplish phase modulation of the output of a voltage controlled oscillator. Such phase locked loops generally require the use of external pins on a semiconductor chip to enable connection to circuit elements that are not integrated into the chip. In certain types of digital logic, phase locked loop circuits are not available (e.g. circuits configured in gate array formations). Further, excess pins are, often not available in such circuit configurations. US-A-5,022,056 relates to a method and a structure for digital phase synchronisation. The structure comprises a circuit having a plurality of delay means which serve to provide delayed versions of a clock signal applied to a terminal. The plurality of delayed clock signal is applied to associate ones of a plurality of flip flops via leads. A data input signal is applied to a data input lead and applied in common to all flip flops. The receiver clock signal is delayed by the delay means and the appropriate one of the delayed clock signal is selected by a selector. The circuit provides a plurality of delayed reference clock signals and determines which of those clock phases is most in-phase with received data and then selects that clock phase that is most in-phase for use a clock signal for the data. The clock signal is not used for spreading out the energy at higher harmonics of the clock frequency. Starting from this prior art it is the object of the present invention to provide an improved clock pulse generator for a clock frequency source which enables phase variation of the clock frequency and is in entirely implemented in digital logic. This object is achieved by a clock pulse generator according to claim 1. Fig. 1 is a diagram of a clock phase modulator constructed in accordance with the invention; and Fig. 2 is a chart showing logical inputs to a selector in the circuit of Fig. 1, which logical outputs control the phase output of the circuit. DETAILED DESCRIPTION OF THE INVENTION The clock frequency modulator circuit diagram is shown in Fig. 1 and comprises three main components. The first component is a delay chain 10 of logic gates 12, 14, 16, etc. Delay chain 10 is implemented by appropriate digital logic circuits such as AND gates, which gates are connected serially to introduce additive delays into delay chain 10. Each connection between succeeding gates (e.g. 12, 14, ) is a "tap" for delay chain 10. As is known, each gate circuit 12, 14, etc. has an inherent delay such that a clock pulse applied at input 18 will propagate through line 20 with no delay, through line 22 with one gate delay, through line 24 with two gate delays, etc. To employ AND gates as the delay elements, plural inputs to each AND gate are tied together and serve as a single input to the AND gate. The second component of the circuit is a selector module 26 that functions to select one of the taps in delay chain 10 to be connected to output 28 of the modulator. Selector module 26 selectively energizes one of its outputs 30 in accordance with either a predetermined or a random pattern. One of output lines 30 is rendered active by selector module 26 upon the occurrence of each clock input (applied via input line 32). Selector module 26 may be configured as an up/down counter; a logical tree which converts a three input binary value from a controlling processor (not shown) to a one of eight output on lines 30; a circuit that includes a random number generator which produces a one of eight output of lines 30 in accordance with a random value calculation, etc. Assuming that selector module 26 is an up/down counter, the pattern of outputs on lines 30 will appear as shown in Fig. 2, with each one of lines 30 being made active in sequence, initially in a first direction and then in a second, reverse direction. The third component of the invention is a multiplexer circuit 34 that is comprised of a plurality of AND gates 36 and connected OR gates 38. Multiplexer circuit 34 receives an input from selector module 26 (via lines 30) and in accordance therewith connects a particular tap in delay chain 10 to output line 28. Multiplexer circuit 34 is constructed as a balanced multiplexer so that a delay path from any tap in delay chain 10 to clock signal output 28 is equal. This assures that the only difference in phase between succeeding clock pulses on output line 28 is determined by the delay to a particular selected tap. In operation, selector module 26 renders active one of its output lines 30 upon the occurrence of each clock input applied via line 32. Depending upon which output line 30 is rendered active, one of AND gates 36 is partially selected. The partially selected AND gate 36 will be fully selected when the same clock pulse applied to input terminal 18 arrives at a tap that is connected to the AND gate. At that point, the clock pulse will have been delayed by n AND gates and the fully selected AND gate 36 provides a pulse output which propagates through OR circuits 38 to output line 28. No other AND gate is fully selected for the duration of that clock pulse. Upon the occurrence of a next clock pulse, selector module 26 renders active another one of lines 30 and the process repeats. By causing selector module 26 to assure that a different output line 30 is rendered active upon each clock cycle, the clock pulses appearing at output line 28 are assured of having different phase relations with the reference phase of the originally applied clock signal. Such a phase variation results in a spreading of the energy at the higher harmonics of the clock frequency. As an example, assume that each AND gate in delay chain 10 manifests a delay of 300 picoseconds. Because delay chain 10 has seven AND gates, the total delay therethrough, from input line 20 to output tap 40, is 2.1 nanoseconds. Since a 50MHz signal has a clock period of 20 nanoseconds, 2.1 nanoseconds is approximately 10 percent thereof and thus delay chain 10 manifests a total phase delay of approximately 36 degrees (at the fundamental frequency). At 50 MHz, this equates to a plus/minus 18 degree change in phase. By contrast, at the 10th harmonic (500MHz), the phase change is 10x18 degrees or 180 degrees. This clearly evidences the substantial energy spread that is achieved by the circuit of Fig. 1 at the higher harmonics which contribute most heavily to the RFI. It should be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention as defined in the appended claims.

Claims: A clock pulse generator for producing phase-displaced clock pulses, said clock pulse generator comprising: a clock pulse (18) source for producing clock pulses exhibiting a reference pulse; a delay means (10) connected to said clock pulse source (18) and including n connections (20,22,24,40), each connection (20,22,24,40) providing a clock pulse that is delayed by a different phase delay from said reference phase; multiplexer means (34) connected to each of said n connections (20,22,24,40) and providing an output (28) manifesting a series of clock pulses, each clock pulse of said series having a different phase displacement from said reference phase than other clock pulses of said series, wherein such a phase variation results in a spreading of the energy at the higher harmonics of the clock frequency; and selector means (26) for controlling said multiplexer means (34) to sequentially connect a sequence of different ones of said n connections (20,22,24,40) to said output (28), whereby said output (28) is enabled to manifest said series of clock pulses, each of which has a different phase displacement from said reference phase. The clock pulse generator as recited in claim 1 wherein said selector means (26) controls said multiplexer means (34) to connect, once each clock pulse, a different one of said n connections to said output (28). A clock pulse generator as recited in claim 1, wherein said selector means (26) comprises: circuit means having a plurality of outputs (30) connected to said multiplexer means (34), said circuit means coupled to said clock pulse source (32) and providing a different control output state on said outputs (30) to said multiplexer means (34) upon each clock pulse occurrence, each said control output state causing said multiplexer means (34) to interconnect a different one of said n connections (20, 22, 24, 40) to said output (28) from said multiplexer means (34). The clock pulse generator as recited in claim 3, wherein said control output states vary in a regular and sequential order across said plurality of outputs (30) of said circuit means. A clock pulse generator as recited in claim 3 wherein said control output states occur in a random order across said plurality of outputs (30) of said circuit means. The clock pulse generator as recited in claim 1 wherein said delay means (10) comprises a series of connected logic gates (12, 14, 16), said n connections (20, 22, 24, 40) occurring at connection points between to said logic gates (12, 14, 16). A clock pulse generator as recited in claim 6 wherein said logic gates (12, 14, 16) comprise a plurality of series-connected AND gates. A clock pulse generator as recited in claim 3 wherein said multiplexer means (34) comprises: a plurality of input AND gates (36), each said input AND gate (36) having an input connected to one of said n connections (20, 22, 24, 40) in said delay means (10) and another input connected to one of said outputs (30) from said selector means (34); and logic means (38) connecting outputs of all said AND gates (36) to said output (28).

Inventors: KNEE DEREK L, LUQUE PHILLIP R, RUST ROBERT, KNEE, DEREK L., LUQUE, PHILLIP R., RUST, ROBERT
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1994
Main classification: H03K3
IPC codes: H03K7, H03K5