SEMICONDUCTOR DEVICE

Abstract: A semiconductor circuit which realizes a read-only memory cell having zero standby-by power consumption and capable of non-volatile storage of multiple-valued or analog data. This semiconductor device is comprised of at least a single n-channel or p-channel MOS transistor in a source-follower circuit configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential.

Description: Semiconductor Device Technical Field The present invention relates to a semiconductor device, and in particular to a high- performance MOS circuit. Background Art Source-follower circuits are frequently used to drive impedance loads, especially in applications employing analog or multiple-valued signals. Such a circuit is depicted in Fig. 1. This diagram indicates a source-follower circuit comprised of one NMOS transistor (abbreviated as "NMOS") (MIO) and a load capacitance (CIO); when VΓ (101) is greater than Vx (the threshold voltage of MIO), current flows to increase Vouτ (102) until VOVT = VIN - VT. (1) If the gate electrode of an NMOS in a source-follower configuration is made floating, and several input gates are capacitively coupled to the floating gate, as shown in Fig. 2, then the potential of the floating gate (ΦF) (201) becomes a linearly weighted summation of the voltages applied to the inputs: C λ V l + C 2 V 2 + -* - - + C n V n ΨF = " . > (2) where n is the number of input gates, C i to C are the coupling capacitances to the floating gate, and C t o t a l is the sum of all coupling capacitances. Therefore, by adjusting the coupling capacitance ratios and the input voltages, the floating gate potential can assume any desired voltage. In this circuit, V OUT (202) will rise until it equals φp - V-r-. One application of this circuit is the simple 2-bit digital-to-analog (D/A) converter depicted in Fig.3. By setting the coupling ratio C .C = 1:2, and applying 0 V or 5 V to the input gates V i (301) and V 2 (302), four possible states are obtained on the floating gate (303), as shown in Table 1. In this manner, the digital signals at Vi and V are converted into analog signals at VODT (304). Disclosure of the Invention The present invention discloses a semiconductor circuit comprising at least a single n- channel or p-channel MOS transistor in a source-follower configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential, provided that Vj ~ 0 in Equation 1. The above semiconductor device realizes a single-transistor, read-only memory cell capable of non-volatile storage of multiple-valued or analog data. The data is programmed into the cell by a single masking step during the fabrication process. This cell can be replicated into a matrix of several rows and columns, with all cells in one row sharing a common word line and all cells in one column sharing a common bit line, thus achieving a high-density memory-cell array. Furthermore, this cell does not consume any standby-by power. Brief Description of the Drawings Figure 1 is a circuit diagram showing a typical NMOS source-follower circuit. Figure 2 is a circuit diagram showing an NMOS source-follower circuit with multiple input gates capacitively coupled to its floating gate electrode. Figure 3 is a circuit diagram showing a 2-bit digital-to-analog converter using a floating-gate NMOS source follower. Figure 4 is a circuit diagram showing the circuit of Embodiment 1, for the case of storing the data value "2". Figure 5 is a circuit diagram showing the circuit of Embodiment 2, for the case of storing the data value "2". Figure 6 is a circuit diagram showing the circuit of Embodiment 3, for the case of storing the data value "2". Figure 7 is a circuit diagram showing a sample array of cells described by Embodiment 3. Figure 8 shows measured operation data of the circuit of Embodiment 3. Figure 9 is a photomicrograph of 4- valued and 8- valued fabricated test cells. Figure 10 is a schematic diagram of the top-view and cross-section of the invention. Figure 11 is a circuit diagram showing the circuit of Embodiment 4, for the case of storing the data value "2". Figure 12 is a circuit diagram showing 8-valued cells which compares programming with (a) binary-weighted capacitors and (b) variably-weighted capacitors of Embodiment 5. Best Mode for Carrying Out the Invention Herein below, the present invention will be explained in detail based on embodiments; however, the present invention is of course not limited to these embodiments. (Embodiment 1) The single-transistor, 2-bit D/A converter of Fig. 3 can be converted into a memory cell by simply adding a select transistor (M40), as shown in Fig. 4. Table 1 lists the four possible state on the floating gate of the 2-bit digital-to-analog converter of Fig.3. Fig. 4 depicts a four-valued cell which stores the data value "2". Different values can be programmed into the cell by changing the connections of electrodes 401 and 402 to either VDD or 0 V. This is done by a single masking step in the device fabrication process. In this manner, varying states are obtained on the floating gate (403), as given by Equation (2). To read data from the cell, the bit line (404) is pre-charge to 0 V, and M40 is turned on by setting the word line (405) high. Therefore, current from the source-follower (M41) raises the bit line voltage. If the threshold voltage of M41 is zero, then the bit line voltage will rise until it equals the floating gate potential ΦF- (Embodiment 2) The cell of Embodiment 1 requires two transistors; however, this cell can be reduced to a single transistor, as depicted in Fig. 5. If the input gates are connected to either the word line (502) or 0 V, then M50 does not turn on unless the word line is high. Therefore, current does not flow from the cell unless the word line is selected, eliminating the need for a separate select transistor. (Embodiment 3) In Embodiment 2, a separate line (501) must carry the VDD voltage supply to all the cells in the memory array. The circuit shown in Fig. 6 presents an alternative that further decreases the cell area. By connecting the drain electrode (601) of M60 to the word line, the VDD line can be eliminated. Figure 7 shows an example of an array of four cells. This figure explains how the cells can be arranged in a high density array by sharing common word lines (701 and 702), 0- V lines (703 and 704), and bit lines (705 and 706). Experimental data for the operation of the circuit in this embodiment is shown in Fig. 8. This data was taken from the fabricated 4-valued test devices shown in Fig. 9. The micrograph in Fig. 9 shows 4-valued and 8-valued cells. Figure 10 shows a schematic top-view and cross-section of a four-valued cell. The first polysilicon layer forms the floating gate, and the second polysilicon layer forms the input coupling gates. However, the implementation of this invention is not limited to this particular device structure. In Embodiments 1, 2, and 3, the bit line is reset to 0 V before each read operation, and an NMOS transistor is used in as a source-follower circuit. Alternatively, the bit line could be pre-charged to VDD . and a PMOS source-follower could be used to lower the bit line voltage. Furthermore, in the above embodiments, leakage currents may flow in unselected cells due to subthreshold currents in the transistor. This happens when Vj « 0 V and can lead to erroneous data readings. To solve this problem, a positive threshold voltage (for example, Vj = 0.5 V) could be used instead. In this case, the output voltage will only rise until φp - 0.5 V. However, it is possible to employ sensing circuitry which detects the reduced voltage level and restores the original data, namely, φp. (Embodiment 4) The NMOS source-follower of Embodiment 1 could be replaced by a CMOS source - follower circuit, consisting of an NMOS (Ml 11) and a PMOS (Ml 12), as depicted in Fig. 11. In this case, the bit line need not be pre-charged since the CMOS source-follower can drive the bit line to both low and high levels, depending on the floating gate potential. (Embodiment 5) The number of possible values stored by this cell can be altered by changing the number of binary-weighted input gates. For n binary-weighted input gates, it is possible to store 2" values in the cell. From Equation 2, the floating gate potential in the cell for the case of n binary-weighted input gates is C,Vι + C 2 V 2 + * - ' + C n V„ V 1 + 2V 2 • ■ l γ 1 '2 r 2 -71 ' n _ ' / T " 2 T + ' " + τ 2^ (n - v > V r „ φp = « (3) ' 'ttonttaall 2 2 1 + - - + 2 (w - 1) Alternatively, the number of possible values stored by this cell can be altered by using variably-weighted coupling capacitances. In this manner, an infinite number of states can be obtained on the floating gate by using only two input gates and adjusting their coupling ratio. For this case, the floating gate potential is given by WO 95/22145 _-_ PCT/JP94/00217 6 CJVJ + C 2 V 2 V ] + kV 2 0 - V Cj + C X = 1 , + k , . * = ττ (4 ) Since any floating gate potential can be obtained by simply adjusting the ratio k, this cell is capable of storing analog data. Figure 12 depicts 8-valued cells implemented by (a) binary-weighted capacitors and (b) variably-weighted capacitors. Furthermore, in the embodiments above, it is possible that charge will be unintentionally injected onto the floating gate, thus shifting φp undesirably. To reset the remove the injected charge and reset the floating gate potential, a switch may be attached to the floating gate. When the cell is in standby mode, the switch can be turned on to reset the floating gate. When the cell is reading out data, the switch must be off. Furthermore, the embodiments described above can be implemented by using fuses or anti-fuses to program the multivalued data in the cell after the completion of the fabrication process. This can be done instead of mask programming. Industrial Applicability By means of the present invention, it is possible to realize the non-volatile storage of multiple-valued or analog data in a read-only memory cell. This cell can be replicated into a matrix of many rows and columns to achieve a high-density memory array. This invention is especially suitable in systems dealing with multiple-valued or analog information, such as image processors or multiple-valued microprocessors. Value v. v 2 ΦF 0 0 0 0.00 1 WL 0 1.67 2 0 WL 3.33 3 WL WL 5.00

Claims: Claims What is claimed is: 1. A semiconductor device comprising of at least one NMOS transistor connected in a source-follower configuration, wherein the drain electrode of said NMOS transistor is connected to a first signal line, the source of said NMOS transistor is connected to a bit line which is initially pre-charged to a low potential, the gate electrode of said NMOS transistor is a floating gate, and said floating gate is capacitively coupled to at least two input gates which are connected to a second signal line or 0 V. 2. A semiconductor device in accordance with Claim 1, wherein the source of said NMOS transistor is connected to the bit line via at least one NMOS or PMOS transistor whose gate electrode is connected to the word line. 3. A semiconductor device in accordance with Claim 1, wherein said first signal line is the VDD supply voltage, and said second signal line is the word line. 4. A semiconductor device in accordance with Claim 1, wherein both said first signal line and said second signal line are the word line. 5. A semiconductor device comprising of at least a PMOS transistor connected in a source - follower configuration, wherein the drain electrode of said PMOS transistor is connected to a first signal line, the source of said PMOS transistor is connected to a bit line which is initially pre-charged to a high potential, the gate electrode of said PMOS transistor is a floating gate, and said floating gate is capacitively coupled to at least two input gates which are connected to a second signal line or 0 V. 6. A semiconductor device in accordance with Claim 5, wherein the source of said PMOS transistor is connected to the bit line via at least one NMOS or PMOS transistor whose gate electrode is connected to the word line. 7. A semiconductor device in accordance with Claim 5, wherein said first signal line is the Vss supply voltage, and said second signal line is the word line. 8. A semiconductor device in accordance with Claim 5, wherein both said first signal line and said second signal line are the word line.

Inventors: AU RITA, OHMI TADAHIRO, SHIBATA TADASHI, AU, RITA;, OHMI, TADAHIRO, SHIBATA, TADASHI
Applicants: AU RITA, OHMI TADAHIRO, SHIBATA TADASHI, AU, RITA;, OHMI, TADAHIRO, SHIBATA, TADASHI
Application year: 1994
Main classification: G11C11
IPC codes: G11C11, G11C16, G11C17, G11C27