Voltage elevator of the charge pump type

Abstract: The present invention relates to a charge pump MOS voltage booster and to two applications where said type of booster can find advantageous use. The voltage booster comprises instead of the classical diodes, which exhibit undesired voltage drop, four MOS transistors and, instead of the classical single-output oscillator with associated charge transfer condenser, an oscillator with two outputs and two corresponding charge transfer condensers. In this manner there are practically no undesired voltage drops and the ripple is reduced without complicating the circuitry structure.

Description: The present invention relates to a charge pump voltage booster and to two applications where said type of booster can find advantageous use. The ever more urgent requirement for devices operating in equipment for which is available only one continuous very low power voltage (down to 1V) as much telecommunications line equipment, portable units, etc., imposes the need to have efficient and simple continuous voltage boosters. One well known structure of a charge pump doubler is illustrated in FIG. 1. It comprises an oscillator OSC typically with square wave and powered with a continuous power voltage VS and connected to ground GND and having an output O. The output O is connected to the first terminal of a first charge transfer condenser TC1. The second terminal of the charge transfer condenser TC1 is connected to the cathode of a diode D2. The anode of the diode D2 is connected to the power voltage VS. The cathode of the diode D2 is also connected to the anode of another diode D1. The cathode of the diode D1 is connected to the output OUT of the doubler and to the second terminal of a charge accumulation condenser SC whose first terminal is connected to ground GND. In this circuit the output voltage (without load) is equal to double the power voltage decreased by double the starting voltage (approximately 0.7V) of the diodes D1 and D2. When the power voltage is very low, e.g. between 1.2V and 3.5V, this reduction becomes significant and unacceptable. To solve this problem it has bee proposed, e.g. in French patent application FR-A-2 321 144, to replace the diodes D1 and D2 with two MOS transistors M1 and M2 as shown in FIG. 2. Naturally threshold transistors M1 and M2 need to be appropriately piloted. This was achieved, as shown in said document, by means of two other MOS transistors M3 and M4. Said circuit of FIG. 2 solves the problem of voltage drop on the diodes since the voltage drop on the channel of the MOS transistors is extremely small but exhibits, as also the circuit of FIG. 1, a certain ripple at the output OUT. Known from the UK Patent Application No. GB-A-2 261 307 is a memory including a circuit for pumping a supply voltage. However, such a known circuit should be provided with a supplemental voltage compensation circuit that compensate the falling of the desired output voltage. Also known from the US Patent No. 4,029,973 is a voltage booster circuit, comprising a first and a second charge accumulation condenser, in order to obtain a greater negative voltage starting from a negative power voltage. For this purpose, the NMOS transistors are driven by means of a ground-connected circuit, in a so called "half side" configuration. However, the ground-connected configuration of such voltage booster doesn't allow a chain connection of a plurality of such booster, in order to obtain an N-grade voltage multiplier. The purpose of the present invention is to supply a voltage booster with simple, efficient circuitry and without large voltage drops in relation to the theoretical high value and with ripple limited at the output. Said purpose is achieved through the doubler having the characteristics set forth in claims 1 or 4 or the booster having the characteristics set forth in claim 10. Additional advantageous aspects of the present invention are set forth in the dependent claims. By using in the doubler or elevator an oscillator having two outputs in phase opposition and two corresponding charge transfer condensers in addition to a bridge of controlled switches it is possible to charge the accumulation condenser during a first half-period through one of the two condensers and during the following half-period charge the accumulation condenser by means of the other of the two condensers and reduce ripple at the output. Advantageously, instead of using four other MOS transistors, the second charge transfer condenser can be connected directly to the first four transistors symmetrically in relation to the first charge transfer condenser. In accordance with another aspect the present invention concerns also an electrical circuit in accordance with claim 17 and a voltage regulator in accordance with claim 18, both comprising and using such a voltage booster. The invention is clarified by the description given below with reference to the annexed drawings. In the drawings: FIG. 1 shows a diode voltage booster in accordance with the known art, FIG. 2 shows an MOS-transistor voltage booster in accordance with the known art, FIG. 3 shows a voltage doubler in accordance with the present invention, FIG. 4 shows a voltage booster in accordance with the present invention, FIG. 5 shows a loading section to be used in the voltage booster of FIG. 4, and FIG. 6 shows a voltage regulator in accordance with the present invention. The circuit of FIG. 3 is quite similar to that of FIG. 2 but differs therefrom in some important elements. The oscilloscope OSC exhibits, in addition to the first output 01, a second output 02 in phase opposition in relation to the first. Said second output is connected to the first terminal of a second charge transfer condenser TC2. The second terminal of said second condenser is connected directly to the four transistors M1,M2,M3,M4 symmetrically in relation to the first condenser TC1. The transistors M1,M2,M3,M4 thus give rise to two inverters connected together in a loop so as to form a flip-flop having respective inputs connected to the second terminals of the condensers TC1 and TC2 which are negative power terminals connected together to the voltage VS and positive power terminals connected together to the second terminal of the condenser SC. The signal generated by the oscillator OSC varies between the potential of the reference GND and the potential of the continuous power voltage VS in accordance with a square wave both at the output 01 and the output 02. Such an oscillator can consist of an oscillator having a single output referred to the potential reference GND, in particular ground, from an inverting buffer and from a non-inverting buffer having virtually equal delays. FIG. 3 shows the bulk diodes D1,D2,D3,D4 of the four MOS transistors M1,M2,M3,M4 respectively. The cathodes of D1 and D3 are connected to the output OUT of the doubler and the anodes of D2 and D4 are connected to the continuous power voltage VS. These connections are very important for correct starting of the circuit and subsequent rated operation as explained more clearly in the following description. Naturally, considering the perfect symmetry of the circuit thus achieved, the inverters consisting of the transistors M1,M2,M3,M4 must be preferably equal. To explain the operation of this circuit it is necessary to follow the evolution of the voltage at the output OUT of the doubler from the time power voltage is applied to achievement of rated operating voltage. At the instant the power voltage is applied the accumulation condenser SC is discharged and the output moves to potential VS - 2 * VD where VD is starting voltage of the bulk diodes of the MOS transistors and is approximately 0.7V. During this first phase the four MOS transistors are all extinguished and the condenser SC charges through the bulk diodes. When the difference between voltage at output and power voltage becomes greater than the threshold voltage of the MOSes, even the transistors M1,M2,M3,M4 begin to conduct and cooperate in "pumping" charge into the condenser SC until replacing completely the bulk diodes at rated operation. Operation during the transient is as follows. During the half-period in which the output 01 of the oscillator OSC is low, i.e. grounded, the first condenser TC1 charges through the diode D2 while the output 02 is high and such that the charge transfer condenser TC2 supplies its own energy to the condenser SC through the diode D3. During the half-period in which the output 01 of the oscillator OSC is high, i.e. at power potential, the condenser TC1 supplies its energy to the condenser SC through the diode D1 and the charge transfer condenser TC2 charges through the diode D4. In the absence of the MOSes (hence only in the presence of the bridge of the diodes (D1,D2,D3,D4) the voltage at the output OUT would rise to: [1] 2 * VS - 2 * VD - 2 * RD * IL - IL * T / C ; where RD is the series resistance of the bulk diodes, IL is the average current absorbed by the load, T is the period of the square wave generated by the oscillator OSC, and C is the capacity of the condensers TC1 and TC2 assumed equal. This is true only if SC >> TC1 and SC >> TC2 so as to disregard ripple. The first of the three contributions subtracted is due to the diode starting voltage and is present even when no current is absorbed by the load, e.g. in "High Side Driver" applications where the load to be piloted is a MOS transistor, i.e., a pure capacity. The second contribution is due to the potential drop on the series resistance of said diodes. By appropriately dimensioning the diodes this contribution is almost always negligible. The third contribution is due to the loss of charges of the condensers TC1 and TC2. This contribution cannot be eliminated and should be allowed for if the charge transfer condensers are integrated, or it can be minimised if it is possible to connect very large discrete condensers outside the chip. In any case, for applications in which no average current is absorbed on the load said contribution is null. Rated operation is as follows. During the half-period in which the output 01 is low, i.e. grounded, the nodes NA and NB are at potential VS and VOUT respectively, M1 and M4 are extinguished, M2 and M3 are lit. In this condition the first condenser TC1 charges through the N-channel MOS transistor M2 and the charge transfer condenser TC2 charges the condenser SC through the P-channel MOS transistor M3. During the half-period in which the output 01 is high, i.e. at power potential, the nodes NDA and NDB are at potential VOUT and VS respectively, M1 and M4 are lit, M2 and M3 are extinguished. In this condition the first condenser TC1 charges the condenser SC through the P-channel MOS transistor M1 and the charge transfer condenser TC2 charges through the N-channel MOS transistor M4. In rated operation, assuming the output resistance of the oscillator OSC to be null, output voltage will be: [2] 2 * VS - 2 * RDS_ON * IL - IL * T / C ; where RDS_ON is the series resistance of the MOS transistors assumed to be equal. From a comparison of formulas [1] and [2] the advantage achieved by means of use of the MOS transistors is clear, especially for applications in which in rated operation the term IL becomes null, e.g. when the load to be piloted is an MOS transistor. For correct operation of the circuit it is well to make some remarks. When the node NA goes low, the bulk diode D2 of the N-channel MOS transistor M2 (this applies also to D4 and M4) goes into conduction triggering an NPN parasite transistor which has for emitter the drain diffusion of the N-channel MOS transistor M2, for base the bulk diffusion of the N-channel MOS transistor M2, and for collector the well containing the N-channel MOS transistor M2. If the well of the N-channel MOS transistor M2 is biased at the voltage VOUT the intervention of this parasite transistor would discharge the condenser SC and prevent reaching of rated condition. Hence, if the circuit is integrated in the same chip, it is advisable to place the transistors M1, M2, M3, M4 in separated wells and bias the well of the N-channel MOSes at the same bulk potential, i.e. VS. When the node NA goes high the bulk diode D1 of the P-channel MOS transistor M1 (this also applies for D3 and M3) goes into conduction triggering a parasite PNP transistor which has for emitter the drain diffusion of the P-channel MOS transistor M1, for base the well of the P-channel MOS transistor M1, and for collector the substrate and the insulation. The presence of this parasite transistor would slow reaching of rated condition. Therefore it is advisable to minimise said undesired effect by surrounding the MOSes M1 and M2 with e.g. a deep highly doped type N diffusion. Another important point to be mentioned concerns dimensioning of the four MOSes and the output resistance of the oscillator OSC. The MOS transistors should be constructed allowing first for the RDS_ON because the voltage drop on it is to be subtracted from the output voltage but without overdoing it because reduction of this parameter involves an opposite increase in the cross current lost during each switching which affects conversion efficiency. In addition, in rated operating condition if the transfer condensers TC1 and TC2 are sufficiently large that the charge lost can be considered negligible, the potential at the nodes Na and NB during a rising or falling front will be determined by the resistive divider made up of the RDS_ON of the MOS transistors and the output resistance of the oscillator OSC. Normally even the oscillator OSC has its output stage provided by MOS inverters. Therefore, assuming half the switching threshold of the inverters made up of the pairs of MOSes M1,M2 and M3,M4, for said inverters to be able to switch, the oscillator must have an output resistance smaller than the RDS_ON of the MOSes. It must also be noted that the MOS transistors work in the voltage space between VOUT and VS and must be constructed in such a manner as to hold this potential difference while the well containing them must hold the highest voltage VOUT. FIG. 4 shows a block diagram of a voltage booster in accordance with the present invention also based on an oscillator OSC having two outputs 01 and 02 in phase opposition and at least one pair of charge transfer condensers so that the accumulation condenser SC is loaded during both half-periods of the wave, usually square, generated by the oscillator OSC. Said booster comprises generically N loading sections CS indicates as CS1-CSN. In the circuit of FIG. 4 the voltage at the output OUT is equal to N+1 times the continuous power voltage VS, hence in the case of a single loading section the booster will be a doubler. The generic loading section CS is illustrated in FIG. 5 and is a device with four terminals, i.e. a first side terminal A, a second side terminal B, a power input terminal C, and a charge output terminal D. All the first side terminals A1-AN are connected to the output 01 and all the second side terminals B1-BN are connected to the output 02. In the case of a single loading section CS the terminal D is connected to the output OUT and to the condenser SC and the terminal C to a potential reference, in the case of FIG. 4 the continuous power voltage VS. In the case of N loading sections CS1-CSN these are connected in series by means of the input terminals C1-CN and the output terminals D1-DN and the first output terminal (D1) of the series connection is connected to the output OUT and to the condenser SC and the last input terminal (CN) of the series connection to a potential reference, in the case of FIG. 4 the continuous power voltage VS. Each loading sections CS includes: a first charge transfer condenser TC1 and a second charge transfer condenser TC2 having first terminals connected to the first A and second B side terminals respectively, and two inverters connected together in a loop in such a way as to form a flip-flop having inputs connected to second terminals of the first condenser TC1 and of the second charge transfer condenser TC2 respectively, negative power terminals connected together to the power input terminal C and positive power terminals connected together to the charge output terminal D. The first inverter is made up of the MOS transistors M1 and M2 and the second of the MOS transistors M3 and M4. Again in FIG. 5 the bulk diodes D1,D2,D3,D4 are shown (basically for operation of the circuit), the cathode of the diodes D1 and D3 is connected to the charge output terminal D while the anode of the diodes D2 and D4 is connected to the power input terminal C. In FIG. 4 a terminal of the condenser SC is connected to ground GND. Naturally a different potential reference could be chosen with a consequent change in the potential at the output OUT. Again in FIG. 4 the continuous power voltage VS is supplied at input both to the oscillator OSC and the terminal CN. Again in this case the terminal CN could be connected to a different potential reference, e.g. RIF. The output voltage would then be equal to N times the continuous power voltage VS of the oscillator OSC increased by the reference potential RIF. As already mentioned, there are various electrical circuits which require voltage booster circuits for the environment in which they operate. A first case are the Flash EPROM memory devices. Indeed, these require a relatively low read voltage, e.g. 3 to 5V. but relatively high programming and reading voltages, 12V. Naturally it is rather inconvenient to have, only for these devices, a 12V power source and it is thus convenient to insert a booster in the memory device. A second case are the voltage regulators with low voltage drop between input and output of the type comprising an MOS power transistor as the output regulation element. Such a regulator is shown in FIG. 6. This is a device basically with three terminals, one input terminal VI, an output terminal VO, and a potential reference terminal GND which is usually connected to ground. To the input terminal VI is connected the drain terminal of a P-channel MOS power transistor OM, and to the output terminal VO is connected the source terminal of the P-channel MOS power transistor OM. In parallel with the channel of the P-channel MOS power transistor OM is placed a protection diode PD. To the output terminal VO are also connected regulation means RM whose output is connected to the gate terminal G of the P-channel MOS power transistor OM through a diode D6. To the input terminal VI can also be connected protection means PM against current overloads whose output is again connected to the gate terminal G of the P-channel MOS power transistor OM through another diode D7. Again to the input terminal VI must be connected voltage booster means EM whose output OUT is connected to the gate terminal G of the P-channel MOS power transistor OM through a current generator IG. Said current generator fulfils principally a function of limitation of the current generated by the voltage booster means EM and also permits letting the potential of the gate terminal G vary. The voltage booster means EM serve to have on the gate terminal G a potential greater at least than the threshold voltage at the potential present on the output terminal VO, hence by at least one volt. If the regulator has low voltage drop the potential on the output terminal VO will be greater only by a few tenths of a volt at the potential on the output terminal VO and hence would not be sufficient to pilot the gate terminal G of the P-channel MOS power transistor OM, hence the necessity of inserting a voltage booster.

Claims: Voltage doubler receiving at input a continuous power voltage (VS) and supplying at an output (OUT) a voltage having a value virtually double that of said continuous power voltage (VS) and comprising: a. an oscillator (OSC) powered by said continuous power voltage (VS) and having a first (01) and a second output (02), said second output (02) in phase opposition in relation to the first output (01), b. a charge accumulation condenser (SC) having a first terminal connected to a potential reference (GND) and specifically ground and a second terminal connected to the output (OUT) of the doubler, c. a first charge transfer condenser (TC1) having a first terminal connected to said first output (OUT) of said oscillator (OSC), and d. two inverters (M1, M2, M3, M4) connected together in a loop so as to form a flip-flop having an input connected to a second terminal of said first condenser (TC1), negative power terminals connected together to said continuous power voltage (VS) and positive power terminals connected together to said second terminal of said charge accumulation condenser (SC), and characterised in that it comprises a second charge transfer condenser (TC2) having a first terminal connected to said output (02) and a second terminal connected to another input of said inverters, said first (TC1) and second charge transfer condenser (TC2) allowing charge transfer to and from said accumulation condenser (SC). Doubler in accordance with claim 1 in which said inverters (M1, M2, M3, M4) are provided by means of MOS transistors and are virtually equal and in which the corresponding bulk terminals of said MOS transistors are connected in such a manner as to create a one-way conduction path between said negative terminals and said positive terminals of said inverters. Doubler in accordance with claim 2 in which said inverters (M1, M2, M3, M4) are charge accumulating elements and each of said inverters (M1, M2, M3, M4) drives at least another of said inverters (M1, M2, M3, M4). Voltage doubler receiving at input a continuous power voltage (VS) and supplying at an output (OUT) a voltage having a value virtually double that of said continuous power voltage (VS) and comprising: a. an oscillator (OSC) powered by said continuous power voltage (VS) and having outputs (01, 02) in phase opposition, b. a charge accumulation condenser (SC) having a first terminal connected to a potential reference (GND) and specifically ground and a second terminal connected to the output OUT of the doubler, c. a first charge transfer condenser (TC1) and a second charge transfer condenser (TC2) having first terminals connected to the outputs (01, 02) respectively of said oscillator (OSC), thus allowing charge transfer to and from said accumulation condenser (SC). d. a bridge comprising four diodes (D1, D2, D3, D4) having a positive terminal connected to the second terminal of said charge accumulation condenser (SC), a negative terminal connected to said continuous power voltage (VS) and the remaining two indifferent terminals connected to second terminals of said first (TC1) and said second (TC2) condensers respectively, and e. four transistors (M1, M2, M3, M4) having principal conduction paths connected in parallel to said four diodes (D1, D2, D3, D4) and control terminals connected in such a way as to lower the voltage drop along the bridge branches, at steady state. Doubler in accordance with claim 4 in which said four transistors (M1, M2, M3, M4) are the MOS type and are virtually equal. Doubler in accordance with claim 4 in which said four diodes (D1, D2, D3, D4) are the bulk diodes of said four transistors (M1, M2, M3, M4). Doubler in accordance with claim 6 in which said four transistors (M1, M2, M3, M4) are integrated in the same chip, in separated wells, said wells being biased at the same potential. Doubler in accordance with claim 7 in which at least the wells of the NMOS transistors (M2, M4) are biased at a potential equal to the bulk terminal potential. Doubler in accordance with claim 7 in which at least the PMOS transistors (M1, M3) are surrounded by a deep highly doped type N diffusion. Voltage booster receiving at input a continuous power voltage (VS) and supplying at an output (OUT) a high voltage and of the type comprising: a. an oscillator (OSC) powered by said continuous power voltage (VS) and having outputs (01, 02) in phase opposition, b. a charge accumulation condenser (SC) having a first terminal connected to a first potential reference (GND) and a second terminal connected to the output (OUT) of the booster, and c. at least one charging sections (CS) having each a charge output terminal (D), a power input terminal (C), a first (A) and a second (B) side terminals connected to the outputs (01, 02) respectively of said oscillator (OSC) and said sections (CS1-CSN) being connected in series through the input terminals (C1-CN) and output terminals (D1-DN) and the first output terminal (D1) of the series connection being connected to the second terminal of said charge accumulation condenser (SC) and the last input terminal (CN) of the series connection being connected to a second continuous power voltage (VS), in which each loading section (CS) comprises: d. a first charge transfer condenser (TC1) and a second charge transfer condenser (TC2) having first terminals connected to said first (A) and second (B) side terminals respectively, and e. a bridge of controlled switches (M1, M2, M3, M4) having indifferent terminals connected to second terminals of said first charge transfer condenser (TC1) and said second charge transfer condenser (TC2), negative terminal connected to said power input terminal (C) and positive terminal connected to said charge output terminal (D), and in which the value of said high voltage corresponds virtually to the value of said second potential less the value of said first potential plus the sum of a number of values of said continuous power voltage (VS) equal to the number of charging sections. Booster in accordance with claim 10 in which said bridge comprises two inverters (M1, M2, M3, M4) connected together in a loop so as to form a flip-flop and having inputs connected to second terminals of said first charge transfer condenser (TC1) and second charge transfer condenser (TC2) respectively, negative power terminals connected together to said power input terminal (C) and positive power terminals connected together to said charge output terminal (D). Booster in accordance with claim 11 in which said inverters (M1, M2, M3, M4) are provided by means of MOS transistors. Booster in accordance with claim 12 in which the corresponding bulk terminals of said MOS transistors are connected in such a way as to create a one-way conduction path between said power input terminal (C) and said charge output terminal (D). Booster in accordance with claim 11 in which said inverters (M1, M2, M3, M4) are virtually equal. Booster in accordance with claim 10 in which said first input terminal (CN) is connected to said continuous power voltage (VS). Booster in accordance with claim 10 in which said oscillator (OSC) consists of an oscillator having a single output referred to a potential reference, specifically ground, from an inverting buffer and from a non-inverting buffer having virtually equal delays. Electric circuit and specifically an electrically programmable and deletable non-volatile memory device of the type powerable with low voltage and comprising a voltage booster in accordance with one of claims 6 to 12 for generation of a high internal power voltage. Voltage regulator having a low voltage drop between input (VI) and output (VO) of the type comprising a MOS power transistor (OM) as the output regulation element and a voltage booster means (EM) in accordance with one of claims 10 to 16 having output (OUT) coupled to the control terminal (G) of said power transistor (OM) to hold said transistor in conduction condition with changes in the operating conditions of the regulator.

Inventors: GARIBOLDI ROBERTO, PULVIRENTI FRANCESCO, GARIBOLDI, ROBERTO, PULVIRENTI, FRANCESCO
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H02M3
IPC codes: H02M3