Control arrangements for digital radio receivers

Abstract: In a frequency modulated digital radio transmission system, frequency differences between transmitter and receiver which give rise to DC offsets at the output of the demodulator are countered for any one data transmission by establishing a frequency controlling or DC level controlling signal during a preamble sequence having a known constant DC component, such as the sequence 10101 ------- used for clock or data synchronisation, and retaining that controlling signal substantially unaltered for use during the remainder of that data transmission.

Description: A problem arises in digital FM radio receivers in that demodulated data may be superimposed on a DC level which is dependent on frequency differences between oscillators in the transmitter and receiver. The DC level will also be subject to drift with time and temperature. When a comparator is used to slice the demodulated data signal, which is usually almost sinusoidal for the highest frequency data pattern, considerable pulse stretching will occur as the slicing point on the data moves with DC level. AC coupling can be used with DC restoration but is always less than perfect and introduces a degree of timing jitter on the recovered data, particularly when the demodulated data contains amplitude variations which may be introduced as the data rate approaches the maximum obtainable from the channel bandwidth. In a radio system where a number of transmitters and receivers communicate together on a network using frequency hopping, rapid switches in channel frequency and from transmit to receive are required. A conventional AFC system would be difficult to use in these circumstances as considerable time would be lost waiting for the system to recover after each frequency step or switch to receive function. Any AFC system used with digital modulation cannot respond to the average DC output level as this varies with data content and would produce a variable slicing level. Peak sensing of the data out could be used but this is also subject to variation as the channel limits are approached, as mentioned in the previous paragraph. DC control arrangements are known e.g. from US-A-4 544 894. According to the present invention in a receiver arrangement for a frequency modulated digital data radio transmission system in which each data transmission commences with a predetermined sequence of digital values, there are provided control means comprising means to derive a correction factor for DC offsets pertaining at the output of a demodulator of the receiver arrangement during a said predetermined sequence and means to retain said correction factor substantially unaltered during the remainder of the respective data transmission. The correction factor may be applied to control the tuning of the demodulator of the receiver arrangement or may be applied to circuit means arranged to counter said DC offsets. Said circuit means may comprise a level shift circuit. The means to derive the correction factor may comprise a protocol controller in the receiver arrangement. In a system in which all transmitters and receivers are crystal controlled short term drift would be negligible and it would only be necessary to apply the correction at the commencement of communication between a transmitter/receiver pair, when a balanced code of say 101010 data can be transmitted to obviate problems with amplitude and average DC level at the demodulator output. A control loop may be formed to incorporate a memory such that during the preamble at the beginning of communication between a particular transmitter/receiver pair a frequency correction factor can be derived such as effectively to cancel DC level offset at the demodulator output for the duration of the transmission. The same frequency correction factor could be retained if the direction of communication between the transmitter/receiver pair is reversed. Control arrangements for frequency modulated digital data radio receivers will now be described way of example with reference to the accompanying drawings, of which:- Figures 1 and 2 show respective control arrangements in which a correction factor is applied to control the tuning of a demodulator of a receiver, and Figures 3, 4 and 5 show control arrangements in which a correction factor is applied to counter DC offsets at the output of a demodulator of a receiver. Referring to the drawings, in the control arrangement shown in Figure 1 the output of a demodulator 1 is applied by way of a comparator 2 to an automatic frequency control circuit 3, which is arranged to apply a frequency controlling signal by way of a digital to analogue convertor 4 to "pull" the frequency of a crystal controlled local oscillator 5 to match that of an incoming RF signal applied to a mixer 6. In the arrangement shown in Figure 2 a similar control loop is used to control the capacitance of a varactor diode 7 in a tuned circuit used to produce quadrature reference signals in the demodulator 1. In the arrangements shown in Figure 3 and in Figures 4 and 5 a similar control loop is arranged to add a DC component to each of the outputs of a differential demodulator 1, by means of a level shift circuit 8, to bring these outputs to similar DC levels without affecting the data components. In the arrangement shown in Figure 3 the values of the added DC components are controlled by the output of a digital to analogue convertor 4, whereas in the arrangement shown in Figures 4 and 5 a pair of track and hold circuits 9 are arranged to develop on respective capacitors 10 (Figure 5) potentials corresponding to the average levels on respective differential outputs of a modulator 1. The track and hold circuits 9 are biased into the track mode by means of a control signal from a data and clock recovery circuit 11 over a path 12 until such time as the circuit 11 indicates that a suitable number of pulse edges with correct timing have been received, denoting the recognition of a valid preamble. The control signal on the path 12 then switches the circuits 9 to the hold mode during which the potentials on the capacitors 10 remain substantially unaltered. The potentials on the capacitors 10 are applied by way of respective buffer amplifiers 13 (Figure 5) to differential level shift circuits 8 which effectively remove any DC offset from the signals passed to a data comparator 14. Since these potentials are held at a constant level except during the preamble, the control arrangement is prevented from responding to the variable DC content of the data block.

Claims: A receiver arrangement for a frequency modulated digital data transmission system in which each data transmission commences with a predetermined sequence of digital values, characterised in that said receiver arrangement provides control means comprising means (2,3,11) to derive a correction factor for DC offsets pertaining at the output of a demodulator (1) of the receiver arrangement during said predetermined sequence and means (3,4,9) to retain said correction factor substantially unaltered during the remainder of the respective data transmission. A receiver arrangement in accordance with Claim 1 wherein said correction factor comprises a frequency control voltage, which is arranged to be applied to control the tuning of the demodulator of the receiver arrangement. A receiver arrangement in accordance with Claim 2 wherein the frequency control voltage is applied to control the frequency of operation of a local oscillator (5). A receiver arrangement in accordance with Claim 2 wherein the frequency control voltage is applied to control the tuning (7) of a phase quadrature network of the demodulator. A receiver arrangement in accordance with Claim 1 wherein said correction factor comprises an offset control signal (12) which is arranged to be applied to counter the effect of said DC offsets on a data recovery circuit (11) of said receiver. A receiver arrangement in accordance with Claim 5 wherein said offset control signal (12) is arranged to be applied to a DC level shift circuit (8) interposed between the output of the demodulator (1) and said data recovery circuit (11). A receiver arrangement in accordance with Claim 5 or Claim 6 wherein said demodulator provides differential outputs and said means to derive a correction factor comprises respective track and hold circuit means (9) arranged to derive respective potentials corresponding to the average DC levels of said differential outputs. A receiver arrangement in accordance with Claim 7 wherein said track and hold circuit means (9) are arranged to derive said respective potentials during reception of said predetermined sequence of digit values and to hold said potentials substantially constant during the subsequent reception of data signals.

Inventors: FOBBESTER IAN GODFREY, FOBBESTER, IAN GODFREY
Applicants: MITEL SEMICONDUCTOR LTD, MITEL SEMICONDUCTOR LIMITED
Application year: 1994
Main classification: H03D3
IPC codes: H03J7, H04L7, H04L27, H04B1