Manufacturing process for obtaining bipolar transistors with controlled storage time

Abstract: A manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time comprises the steps of: in a silicon material (1, 2), forming at least one bipolar transistor occupying a first area (A D ) on a first surface of the silicon material (1, 2); covering the first surface of the silicon material (1, 2) with an insulating material layer (5); selectively removing the insulating material layer (5) to open at least one window (6) having a second area (A Pt ) much smaller than the first area (A D ) occupied by the bipolar transistor; implanting into the silicon material (1, 2) a medium dose (D) of platinum ions through said window (6); and diffusing into the silicon material (1, 2) the implanted platinum ions to obtain a uniform distribution of platinum inside the transistor.

Description: The present invention relates to a manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time. In bipolar transistors, the "storage time" is the parameter defining the time necessary for the device to move from the saturation region to the active region, and depends on the biasing conditions and on the minority carrier lifetime in the base and collector regions of the transistor. In several applications, such as lamp ballast circuits, it is necessary to use power bipolar transistors with highly controlled storage time, not to affect the circuit oscillation frequency and the power delivered to the load. In view of such applications, the manufacturers make available different selections of transistors with guaranteed storage time values, with tolerances limited to 20% of the specified value. One way to assure such a fine tuning of the storage time is to prevent the bipolar transistor from being driven into deep saturation, by means of circuital techniques such that described in the European Patent Application No. EP-A-0 630 051. Another way is to make use of techniques for controlling the minority carrier lifetime; in the practice, this means reducing the minority carrier lifetime from about 30 µs to 10-20 µs, depending on the specific application. One known lifetime-control techinique calls for exposing the device to an electron radiation: in this way, silicon atoms in the lattice are displaced from their sites, and deep energy levels are introduced in the silicon energy band gap; such deep energy levels causes a variation of the minority carrier lifetime, which can therefore be controlled. This technique shows some limitations: firstly, electron-hole pairs are created at the interface between the silicon surface and the silicon dioxide layer, reducing the device reliability; secondly, the damage produced in the lattice by the displacement of silicon atoms from their sites is unstable and varies with temperature and time: it is in fact sufficient to submit the device to temperatures in the range of 280-400 °C to re-establish in the lattice the conditions before the exposure to the electron radiation; since during its packaging the device is submitted to a thermal process ("die attach") at temperatures ranging from 300 °C to 350 °C, the precision of the minority carrier lifetime tuning is compromised. Another known lifetime-control technique calls for the introduction of platinum atoms: the tuning of the minority carrier lifetime thus achieved is not affected even if the device is successively submitted to temperatures ranging from 400 °C to 600 °C. The minority carrier lifetime τ is related to the dose of platinum atoms introduced into the silicon by the following equation: (1/τ) - (1/τ 0) = K Pt × D where τ 0 is the minority carrier lifetime before the introduction of platinum atoms, K Pt is a constant for platinum, and D is the dose of platinum atoms introduced. It is therefore necessary to introduce extremely low doses of platinum atoms, ranging from 10 10 to 10 11 atoms/cm 2 , since for doses of the order of 10 12 atoms/cm 2 the minority carrier lifetime falls to values of some microseconds, which are too low for the applications under consideration. Such low doses cannot be statistically reproduced by any known implanting industrial apparatus: the dispersion between different implants would infact be higher than 50%, and would make the technique impossible to be industrialized. The introduction of platinum atoms by means of the deposition technique is even more inadequate to achieve such low doses. EP-A-0488440 describes a process of introduction and diffusion of platinum ions in a slice of silicon, substantially as recited in the preamble of claim 1. However, the process described in this document is not suitable for bipolar transistors, wherein the amount of platinum ions to be introduced must be quite small, in order not to reduce too much the minority carrier lifetime. The technical paper of Coffa et al. "Three-dimensional concentration profiles of hybrid diffusers in crystalline silicon" published in Journal of Applied Physics, vol. 74, No. 1 of 1 July 1993 investigates the mobility of platinum ions in silicon. US-A-5204273 describes a method for the manufacturing of a thyristor with defined lateral resistor, wherein the value of the lateral resistor is adjusted as defined by the width ratio of recesses regularly arranged in a deposition layer and respective ribs remaining between the recesses. The deposition layer can be generated by implantation of boron in the semiconductor body, and the recesses and the ribs are generated by using an implantation mask. The width ratio is approximately equal to 1, and it can be slightly varied in qrder to finely adjust the resistor value. In view of the state of the art described, the object of the present invention is to provide a manufacturing process for obtaining bipolar transistors with controlled storage time by means of the introduction of platinum atoms into silicon, overcoming the abovementioned difficulties. According to the present invention, such object is attained by means of a manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time, as set forth in claim 1. Thanks to the present invention, it is possible to implant platinum ions with implant doses which are easy to control by using existing implanting apparatus; after thermal diffusion, the platinum ions are uniformly distributed in the device, and since the area of implantation is much smaller than the area of the device, the concentration of platinum is equivalent to that which will be obtained if the whole device surface would be implanted with a much lower, impractical dose of platinum ions. The storage time of the device can thus be finely tuned. The features of the present invention will be made more evident by the following detailed description of two practical embodiments, illustrated as non-limiting examples in the annexed drawings, wherein: Figure 1 is a top plan view of a portion of a semiconductor wafer, taken at an intermediate step of a manufacturing process according to the present invention; Figure 2 is a cross-sectional view of the portion of wafer taken along the line II-II of Figure 1; Figure 3 is a top plan view of said portion of wafer, taken at another intermediate step of the manufacturing process; Figure 4 is a cross-sectional view of the portion of wafer taken along the line IV-IV of Figure 3; Figure 5 is a cross-sectional view similar to Figure 4, taken at a third intermediate step of the manufacturing process; Figure 6 is a top plan view similar to that of Figure 3, taken at an intermediate step of a manufacturing process according to another embodiment of the present invention. A manufacturing process according to the invention starts with a silicon wafer heavily doped to form an N+ substrate 1. Over the substrate 1 a lightly doped N- layer 2 is grown, for example epitaxially, with resistivity and thickness determined on the basis of the breakdown voltage desired for the bipolar transistors which are to be fabricated. The N- layer 2 constitutes a collector region of the bipolar transistors. Acceptor-type dopant impurities are then selectively introduced, according to any known technique, into the N- layer 2 (for example by means of ion implantation and diffusion), to form heavily doped P+ regions 3, substantially with square shape, each constituting a base region of a respective bipolar transistor. As shown in Figure 1, the P+ regions 3 are disposed to form a bidimensional array on the wafer surface. Donor-type dopant impurities are then selectively introduced into the P+ regions 3 to form N+ regions 4, each one constituting an emitter region of said respective bipolar transistor; as shown in Figure 1, the N+ regions 4 can for example have a comb-like shape, to increase emitter efficiency. The wafer is then oxidixed, and an oxide layer 5 thus formed is selectively removed from the surface of the wafer to open windows 6 to expose selected areas of the wafer surface. As shown in Figure 3, the windows 6 are located along the sides of the P+ regions 3: each P+ region 3 is therefore surrounded by four windows 6. Platinum ions are then selectively implanted into the wafer surface with an implantation dose D (atoms/cm 2 ), the oxide layer 5 acting as a mask; platinum ions can therefore be introduced into the N- layer 2 only in correspondance of the windows 6. The platinum ions thus introduced are then made to diffuse by heating the wafer to a temperature ranging from 850 °C to 1000 °C; at the end of this step the platinum ions are uniformly distributed in the bulk of the silicon wafer. Each window 6 has an area A Pt /2; since the platinum ions introduced through each window 6 diffuse isotropically into the silicon, they are shared by two adjacent devices: each window 6 contributes therefore for an area A Pt /4 to the area of implantation of platinum ions per device. Since each device is surrounded by four windows 6, the area of implantation of platinum ions per device is globally A Pt . Assuming that the area occupied on the wafer surface by each device is A D , substantially corresponding to the area of the P+ base region 3, after the diffusion the concentration of platinum in each device corresponds to that which will be obtained if an equivalent dose Deq of platinum ions would be implanted into the whole area A D of the device, with Deq being given by: Deq = D × A Pt /A D . By making the window areas A Pt /2 very small, so that A Pt is much lower than A D , it is possible to obtain a value for the equivalent dose Deq of implanted platinum ions which is very low, even if the effective implant dose D is kept in a range of values sufficiently high to allow the use of the existing implanting apparatus, and to be reproducible. If for example the device area is A D = 10 mm 2 and A Pt = 0.01 mm 2 , the factor A Pt /A D is 1/1000, and for an implantation dose D = 10 13 at/cm 2 there is obtained an equivalent implantation dose Deq = 10 10 at/cm 2 . Decreasing the window area, or keeping the same window area for larger devices, lower equivalent implantation doses of platinum can be obtained. In this way it is possible to introduce into the silicon wafer a controlled amount of platinum ions, which is reproducible, and which therefore allows to obtain bipolar transistors with a controlled storage time, with a minority carrier lifetime in the desired range of 10 to 20 µs. The diffusion step of the implanted platinum ions is carried out after all the other thermal steps in the manufacturing process have been performed; it has been experimentally verified that with a temperature of 850-1000 °C, a few hours are sufficient to obtain a uniform distribution of the platinum ions over the whole wafer; since the diffusion steps utilized for the manufacturing of power devices call for high temperature processes of 1100-1200 °C and long times (5-15 hours), the diffusion process of the platinum ions do not alter the junction depths of the layers. After the introduction of platinum, the oxide layer 5 is selectively removed to form contact holes, and a metal layer 7 is deposited over the wafer surface and selectively etched to provide electrical contacts to the P+ base regions 3 and to the N+ emitter regions 4 of the various devices (Figure 5). The oxide layer 5 is also removed along the sides of the devices to facilitate the device cutting by means of mechanical or laser scribing. According to a second embodiment of the present invention, shown in Figure 6, if the device area A D is of the order of 1 cm 2 , the windows 6 in the oxide layer 5 can be opened over the devices, instead that along their sides; this makes it possible to obtain, after implantation and diffusion, a uniform distribution of platinum ions in the silicon wafer, without increasing the temperature and/or the time duration of the platinum diffusion steps. The distribution of windows 6 over each device can be varied, the only requirement being that the overall area A Pt of the device exposed to the implantation of platinum ions is much smaller than the device area A D . In the shown example, four windows 6 per device have been opened, each window 6 having an area A Pt /4. Even if the process according to the invention has been described with reference to the fabrication of controlled storage time NPN bipolar transistors, it is evident to anyone skilled in the art that it can as well be used for the fabrication of controlled storage time PNP transistors, changing the P-type semiconductor regions into N-type, and vice-versa.

Claims: Manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time, comprising the steps of: a) in a silicon material (1, 2), forming at least one bipolar transistor occupying a first area (A D ) on a first surface of the silicon material (1, 2); b) covering the first surface of the silicon material (1, 2) with an insulating material layer (5); c) selectively removing the insulating material layer (5) to open at least one window (6); d) implanting into the silicon material (1, 2) a dose (D) of platinum ions through said window (6); e) diffusing into the silicon material (1, 2) the implanted platinum ions to obtain a uniform distribution of platinum inside the transistor, characterized in that said at least one window (6) has a second area (A Pt ) much smaller than the first area (A D ) occupied by the bipolar transistor, so that the concentration of platinum is equal to a concentration which would be obtained if an equivalent dose (Deq) of platinum ions were implanted through a window having an area substantially equal to the first area (A D ), said equivalent (Deq) dose being lower than said dose (D) by a factor equal to the ratio of said second area (A Pt ) to said first area (A D ). Manufacturing process according to claim 1, characterized in that said dose (D) of platinum ions depends on the desired concentration of platinum inside the transistor after step e) has been performed, and on the ratio between the first area (A D ) of the bipolar transistor and the second area (A Pt ) of said at least one window (6). Manufacturing process according to claim 2, characterized in that said dose (D) of platinum ions and said ratio between the area (A D ) of the bipolar transistor and the area (A Pt ) of said at least one window (6) are such that after the step e) a uniform distribution of platinum ions with a concentration in the range 10 12 -10 13 atoms/cm 3 is obtained. Manufacturing process according to claim 1, characterized in that said at least one bipolar transistor comprise a first plurality of uniformly distributed bipolar transistors, each having a first area (A D ), and said at least one window (6) comprises a second plurality of uniformly distributed windows (6), each having a second area (A Pt /2;A Pt /4), the overall area of the second plurality of windows (6) being much smaller than the overall area of the first plurality of bipolar transistors. Manufacturing process according to claim 4, characterized in that each window (6) of said second plurality is located between two respective adjacent bipolar transistors of said first plurality. Manufacturing process according to claim 5, characterized in that the windows (6) of said second plurality are uniformly distributed over the bipolar transistors of said first plurality.

Inventors: FRISINA FERRUCCIO, FRISINA, FERRUCCIO
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L29