Nonvolatile semiconductor memory device having a status register and test method for the same

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Description: The present invention relates to a nonvolatile semiconductor memory, and a test method for the same. Further, the invention relates to a semiconductor memory having a sense amplifier, and a semiconductor device. More particularly, the invention relates to a semiconductor device and a test method for the same, wherein testing can be conducted easily to check whether the fabricated semiconductor device has a prescribed performance. Semiconductor memories such as DRAM and SRAM are widely used, and flash memory has been attracting attention as an electrically erasable nonvolatile memory. Each memory cell of a flash memory consists of a single transistor. This transistor is called a memory cell transistor. A memory cell transistor of the flash memory has the structure of an n-channel MOS transistor with a floating gate formed beneath its gate. For erasure, a control gate is left open, and a high voltage is applied to a source, which causes a charge to be drawn through the source, leaving almost zero charge on the floating gate. In this situation, when an appropriate voltage is applied to the control gate, the transistor conducts. When a high voltage is applied to the control gate and the drain, avalanche breakdown occurs, and part of electrons that have gained high energy near the drain are captured by the floating gate. This operation is called writing. Once writing is done, the charge remains accumulated on the floating gate, so that the transistor will not conduct even when a voltage is applied to the control gate. Data is defined according to whether the transistor conducts or not. In the flash memory, the writing and erasure of information can be accomplished electrically, as described above. Flash memories require different voltages for different operating modes, read, write, and erasure, for application to various elements, and accordingly, their control operations are complex: Furthermore, a read or erase operation is usually followed by a verify operation to verify the processed data by reading it. Such operations have previously been done by applying prescribed voltages to designated terminals of the flash memory by using a writer or other external equipment. This puts a great deal of load on the writer and other external equipment used for write and erase operations. To simplify such complex control algorithms, the recent flash memory design incorporates automatic circuitry that allows the writing and erasure of flash memory cells to be accomplished just by entering simple control commands from the outside. Such a flash memory design is becoming predominant. In a flash memory equipped with such automatic circuitry, once an external control command is accepted, all processing is automatically done internally until a cell write or erase operation is completed. It is therefore usual to provide a status register facility as a means for allowing external monitoring of the device status. Once the automatic circuitry is activated, it is not possible to know the status of internal circuitry without reading out the status register. After the fabrication of a semiconductor device is completed, various tests are performed to check whether the semiconductor device has the prescribed performance. In the case of a nonvolatile memory such as a flash memory, for example, a test is performed to check whether the status register functions properly. The status register provides an external indication of the status of write and erase operations performed by the operational logic circuit; that is, the bit values in the status register indicate whether the write or erase operation has been completed correctly. Therefore, to verify whether the status register is functioning correctly, the operational logic circuit is actually made to perform various operations to produce various status conditions, and the status register is tested to see whether it reflects the status correctly. In the status register test procedure above, only the operation of the status register is tested. For example, when the operation of the status register for write mode is tested, the test result of normal or failure is set into the status register without performing real write and verify operations. Therefore, the procedure does not guarantee that the status register will function properly when a failure occurs in the memory cell matrix or a sense amplifier/write amplifier. Namely, with the status register test for a flash memory explained above, it is only possible to verify the status register function and part of the whole circuit operation. In the testing of memories, with increasing memory capacity, the test time is increasing by a large extent, which pushes the test costs even higher than before. To reduce the test costs, it is important to be able to identify defects in the shortest possible time, but at the same time, it is also important to combine various tests into a single comprehensive test process to reduce the test time and minimize the increase in test costs. Therefore, in the status register test also, it is desirable that the test be performed in a more comprehensive manner, not limiting the test to the parts mentioned above. The test method currently practiced is not sufficient from this point of view. Among tests unique to a nonvolatile memory such as a flash memory, there is a test to guarantee proper retention of the stored data for long periods of time after power to the memory is removed. Since such a long-period test cannot be performed under actual conditions, the data retention test is usually conducted by an accelerated test called an aging test. In the aging test, after writing is done up to a prescribed level, accelerating stresses are applied to stress the data retention conditions by holding the device at a temperature higher than normal, and after that, the threshold level is detected. As described above, each individual device is subjected to the aging test after it is assembled and sealed in a package. However, since the aging test as described above is performed in the final test step after the device assembly, a sufficiently high temperature cannot be applied to the device assembled in a plastic package, thus requiring a long aging time to guarantee the reliability of data retention, and hence increasing the number of steps. There has been proposed another process different from the above process in which the aging test is performed between a passivation layer growing step and the coating film growing step. In this process, after writing is done up to a prescribed level, accelerating stresses are applied in the aging step where the device is held for one hour at 300°C . Then, the data level is verified. With the aging test described above, while it can guarantee the device reliability since the devices are subjected to aging on the wafer, it still involves a problem in that it increases the number of steps. Furthermore, for a semiconductor memory, a power supply margin on the high-voltage side that can be applied to the memory cell needs to be measured. However, the memory cell current characteristic is such that the gradient decreases with increasing gate voltage; therefore, the sense amplifier of the prior art has the problem that the sense point becomes displaced when the supply voltage is increased, which prevents correct cell comparison. To avoid this problem, an extra circuit has to be added so that the sense amplifier power supply can be separated from the cell power supply, and also, a special test for measuring it has to be added. When measuring the power supply margin for the sense amplifier, the test is performed using a circuit that separates the sense amplifier power supply from the cell gate power supply. Such a test, however, cannot be performed in the usual test process, but a separate test step for that purpose needs to be provided. The problem here is that the extra test in addition to the usual test steps will introduce an extra cost which will be reflected in the final chip cost. Furthermore, for a semiconductor device, the power supply current during operation needs to be measured. Because of the test process employed, the power supply current is measured using a setup with the output pin connected to a load circuit. The measuring conditions for the operating power supply current guaranteed in specifications, etc., require that the current flowing through a load be 0 mA. However, when the measurement is made with the output connected to the load circuit, the correct current value cannot be obtained since the charge/discharge current flowing through the load circuit is also measured. Therefore, when measuring the guaranteed design value, the output pin is disconnected from the measuring circuit. With the output circuit setup described above, the power supply current cannot be accurately measured; therefore, the measurement is made after disconnecting the output pin from the measuring circuit. This introduces a cumbersome step in the test process. The present invention has been made in view of the above enumerated problems, and may provide a nonvolatile semiconductor memory that permits comprehensive testing of the status register function, sense amplifiers, etc., including internal automatic circuitry, and that serves to achieve improvements in test efficiency and test accuracy. According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of word lines and a plurality of bit lines arranged in a grid pattern; a memory cell matrix consisting of electrically erasable nonvolatile memory cells whose gates are connected to said word lines and whose drains are connected to said bit lines, each of said memory cells being formed at one of the intersections between said word lines and said bit lines; a sense amplifier for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell located at the intersection between a selected word line and a selected bit line is conducting or nonconducting; a write/erase timing circuit for automatically performing timing control necessary for writing data into and erasing data from said memory cells; and a status register for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally, said nonvolatile semiconductor memory being characterised by the provision of dummy cells provided outside the address of said memory cell matrix and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier outputs a logic value "1" or "0" depending on the state of the accessed dummy cell; and control means for performing control so that said dummy cells are accessed when said write/erase timing circuit is operated to test the performance of said status register. According to a second aspect of the present invention, there is provided a performance test method for a nonvolatile semiconductor memory comprising: a plurality of word lines and a plurality of bit lines arranged in a grid pattern; a memory cell matrix consisting of electrically erasable nonvolatile memory cells whose gates are connected to said word lines and whose drains are connected to said bit lines, each of said memory cells being formed at one of the intersections between said word lines and said bit lines; a sense amplifier for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell located at the intersection between a selected word line and a selected bit line is conducting or nonconducting; a write/erase timing circuit for automatically performing timing control necessary for writing data into and erasing data from said memory cells; and a status register for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally; characterised in that said method comprises the steps of: providing dummy cells outside the address of said memory cell matrix and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier outputs a logic value "1" or "0" depending on the state of the accessed dummy cell; providing a write failure state or an erasure failure state by attempting to write a logic value "0" to a cell, of said dummy cells, preset to a logic value "1", or by attempting to erase a cell preset to a logic value "0" and confirming that the cell does not change to the logic value "1"; providing a write normal state by attempting to write a logic value "1" to a cell, of said dummy cells, preset to a logic value "l", or by attempting to write a logic value "0" to a cell preset to a logic value "0"; providing an erasure failure state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to a written state; or providing an erasure normal state by attempting to erase a cell, of said dummy cells, preset to a value corresponding to an unwritten state. In a semiconductor memory according to the present invention, testing the status register function does not involve forcibly applying a test signal to part of the internal automatic circuitry, as was practiced in the prior art, but is accomplished by performing an operation to write data "0" into a dummy cell that is preset to data "0" and is not alterable, thus making it appear as if the write operation has been completed successfully. Conversely, if an operation is performed to write data "0" to a dummy cell that is fixed to data "1" and is not alterable, it is possible to make it appear as if a write failure has occurred. Likewise, in an erasure test, if an erase operation is performed on a dummy cell that is fixed to data "1" and is not alterable, it is possible to make it appear as if the erasure has been done successfully. Conversely, if an erase operation is performed on a dummy cell that is fixed to data "0" and is not alterable, it is possible to make it appear as if an erase failure has occurred. Thus, according to the invention, it is possible to check the performance of the entire circuit, including the internal automatic circuitry, for both cell normal and cell failure states. While in the prior art it was only possible to check the status register function and parts of other circuitry, the present invention makes it possible to check the performance of the entire circuit including the internal automatic circuitry, in addition to the status register function check. The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: Figs. 1A through 1C are diagrams showing a memory cell structure of a flash memory; Fig. 2 is a block diagram showing the configuration of a prior art flash memory; Fig. 3 is a flowchart showing a test procedure for a status register according to the prior art; Fig. 4 is a block diagram showing the configuration of an embodiment of the present invention; Fig. 5 is a circuit diagram showing an address buffer according to the embodiment; Fig. 6 is a circuit diagram showing a test dummy cell signal input circuit according to the embodiment; Fig. 7 is a circuit diagram showing a data input buffer according to the embodiment; Fig. 8 is a circuit diagram showing a memory cell matrix according to the embodiment; Fig. 9 is a circuit diagram showing a row decoder according to the embodiment; Fig. 10 is a diagram showing a command register according to the embodiment; Fig. 11 is a circuit diagram partly showing a data comparator register and a data output buffer according to the embodiment; Fig. 12 is a circuit diagram showing the remaining part of the data comparator; Fig. 13 is a diagram showing a timing generating circuit according to the embodiment; Figs. 14 and 15 are circuit diagrams respectively showing individual registers included in a status register; Fig. 16 is a circuit diagram showing a part of the data output buffer according to the embodiment; and Fig. 17 is a flowchart showing a test procedure for a status register according to the embodiment. Before proceeding to a detailed description of the preferred embodiment of the present invention, prior art nonvolatile semiconductor memories will be described, with reference to the accompanying drawings relating thereto, for a clearer understanding of the differences between the prior art and the present invention. An example of the memory cell transistor of the flash memory is shown in Figs. lA through lC: Fig. lA shows a top plan view, Fig. lB shows an A-A' cross section, and Fig. lC shows a B-B' cross section. Reference numeral 9l indicates a p-type silicon (Si) substrate, 92 indicates a floating gate (FG) formed from polysilicon, 93 indicates a control gate (CG) formed from polysilicon capacitively coupled to the FG 92, 94 and 95 indicate n-type regions which form the source and drain, and 96 indicates an oxide film. Fig. 2 is a block diagram showing the configuration of a prior art flash memory. Throughout the drawings, the same reference numerals are used to indicate the same functional elements, while the reference numerals with an alphabetic character suffixed thereto indicate elements having similar, but not the same, functions. The numeral l indicates a command register circuit, 2 indicates a status register circuit, 3 indicates an operational logic circuit, 4 indicates a column address buffer, 5 indicates a row address buffer, 6 indicates a block address buffer, 7 indicates a write/erase switching circuit, 8A indicates a data comparator circuit, 9A indicates a write/erase timing generating circuit, 10 indicates a column decoder, 11A indicates a row decoder, 12 indicates a block decoder, and 13A indicates a write/erase test signal input circuit which, only when a test signal is input to it, forcibly activates the write/erase timing generating circuit 9A while inhibiting the data comparator function of the data comparator circuit 8A. The numeral 14 indicates an input/output buffer, 15 indicates a sense amplifier/write amplifier, 16 indicates a Y-gate, 17A indicates a memory cell matrix, and 18 indicates an erasure source control circuit. As described above, flash memories put a great deal of load on the writer and other external equipment used for write and erase operations. To simplify such complex control algorithms, the recent flash memory design incorporates automatic circuitry that allows the writing and erasure of flash memory cells to be accomplished just by entering simple control commands from the outside. A flash memory equipped with such automatic circuitry usually provides a status register facility as a means for allowing external monitoring of the device status. Once the automatic circuitry is activated, it is not possible to know the status of internal circuitry without reading out the status register. After the fabrication of a semiconductor device is completed, a test is performed to check whether the status register functions properly. The status register provides an external indication of the status of write and erase operations performed by the operational logic circuit; that is, the bit values in the status register indicate whether the write or erase operation has been completed correctly. Therefore, to verify whether the status register is functioning correctly, the operational logic circuit is actually made to perform various operations to produce various status conditions, and the status register is tested to see whether it reflects the status correctly. Fig. 3 is a flowchart showing a prior art status register test procedure for a flash memory. First, in step 501, selection is made as to whether the test is performed with a normal operation mode or in such a manner as to induce a failure, and the write/erase test signal input circuit 13A of Fig. 2 is set accordingly. In response to the selection, data comparison by the data comparator register circuit 8A is inhibited in step 502 so that the result of the normal or fail mode operation can be obtained independently of the data to be compared. In step 503, a command is entered for a write or erase operation whichever is selected, and in step 504, the selected operation is started. The operation cycles through steps 505 and 506 until it is completed. When the operation is completed, the status register value is read out to verify that the value reflects the correct status. The status register test procedure of the prior art is performed in the above manner. In the above procedure, however, it is the data comparator register 8 that causes an operation failure, and the procedure does not guarantee that the status register 2 will function properly when a failure occurs in the memory cell matrix 17A or the sense amplifier/write amplifier 15. The following embodiment of the present invention serves to achieve improvements in test efficiency and test accuracy of the status register. Fig. 4 is a block diagram showing the configuration of a flash memory according to the embodiment of the invention. The configuration shown corresponds to that of the prior art shown in Fig. 2; the same functional elements are indicated by the same reference numerals between the two figures, while corresponding elements having different functions are indicated by the same reference numerals but with an alphabetic suffix "A" in Fig. 2. The numeral 1 indicates a command register circuit, 2 indicates a status register circuit, 3 indicates an operational logic circuit, 4 indicates a column address buffer, 5 indicates a row address buffer, 6 indicates a block address buffer, 7 indicates a write/erase switching circuit, 8 indicates a data comparator circuit, 9 indicates a write/erase timing generating circuit, 10 indicates a column decoder, 11 indicates a row decoder, 12 indicates a block decoder, 14 indicates an input/output buffer, 15 indicates a sense amplifier/write amplifier, 16 indicates a Y-gate, 17 indicates a memory cell matrix, and 18 indicates an erasure source control circuit. The numeral 19 indicates a test dummy cell select signal input circuit, and 20 indicates a test dummy cell block consisting of a dummy cell that is fixed to "0" and is not alterable, and a dummy cell that is fixed to "1" and is not alterable. In this embodiment, although only one dummy cell of each type is provided in the test dummy cell block, a plurality of dummy cells of each type may be provided. By comparing Fig. 2 and Fig. 4, it is apparent that elements comprising the flash memory of the embodiment are almost the same as those of the prior art flash memory. Therefore, only portions relating to the status register test will be described. Further, the status register test is divided into a test for write mode and a test for erase mode. To simplify the explanation, circuits relating only to the test for write mode will be explained. Fig. 5 is a circuit diagram showing address buffers such as the column address buffer 4, the row address buffer 5, and the block address buffer 6. The address buffer consists of individual address buffers, one indicated at 33, the number of address buffers being equal to the number of bits of an address signal. Each bit of the address signal is input to an address signal input terminal such as PAi or PAj, indicated by references 31, 32. The address signal input terminal 32 is a selected one to which a test dummy cell signal input circuit 19 is connected. As shown in Fig. 5, each address buffer includes a NOR gate, five NAND gates, three inverters, and two capacitors. A /PD signal is a chip enable signal, and a FIX-H signal is fixed to "High" during operation. The address buffer 33 outputs an Ai signal which is equivalent to the input address signal, a /Ai which is an inverted signal of Ai, and a /ATDAi which is an inverted address transition detection signal. Fig. 6 shows the test dummy cell select signal input circuit 19 which is connected to the address signal input terminal. The test dummy cell select signal input circuit 19 includes two p-channel transistors TP1 and TP2, two n-channel transistors TN1 and TN2, a depletion type n-channel transistor TD1, and two inverters G9 and G10. In this circuit, transistors of high withstand voltage type are used. When the test dummy cell is selected for the status register testing, a voltage higher than source voltage VCC by 3 to 4V is applied to this terminal 32. By this voltage, p-channel transistors TP1 and TP2 are turned on and TN1 and TN2 are also turned on, so that a TROM SEL which is a dummy cell select signal is set to the "High" state. /TROM SEL is an inverted signal of TROM SEL. Fig. 7 is a circuit diagram showing the data input buffer. The data input buffer consists of individual data input buffers shown in Fig. 7, the number of data input buffers being equal to the number of bits of a data signal. Each bit of the data signal is input to a data signal input/output terminal such as PIOi indicated by references 35. As shown in Fig. 7, the buffer circuit includes a NOR gate, eight NAND gates, and three inverters. WP is a pulse signal which is normally "Low", and changes to "High" for a short period when data is input. In the following, a pulse signal such as WP is called "a positive pulse", and a pulse which is normally "High" and changes to "Low" in a short period is called "a negative pulse". This data input buffer outputs a Din Data i signal equivalent to the input data signal, and a /Din Data i signal which is an inverted signal of Din Data i. A portion consisting of NAND gates G16 through G19 and inverters G20, G21 operates as a latch circuit. The state of this latch circuit is set when a DATA LATCH signal is "High", and the latched data is held while DATA LATCH is "Low". The latch circuit outputs Din Latch Data i and /Din Latch Data i. Fig. 8 is a diagram showing the Y-gate 16, memory cell matrix 17, erasure source control circuit 18, and test dummy cell block in more detail. As shown in Fig. 8, unlike other memory cells, the dummy cells, D 1 and D 2 are conventional n-channel transistors that do not have a floating gate; their gates are connected to a dummy word line DWL, and their sources are connected to a common source line SL; the drain of the dummy cell D1 is connected to a first bit line BL 1 , and the drain of the dummy cell D2 is not connected to a second line BL 2 . The dummy cells D 1 and D 2 are accessed by selecting the dummy word line DWL and the first bit line BL 1 or the second bit line BL 2 . As in the case of the normal memory cells Cij, current flows or does not flow to the common bit line KBL according to whether or not the dummy cell conducts, and the state is sensed by the sense amplifier 151. The dummy cells are thus read out in the same manner as the normal memory cells Cij. As shown in above, the dummy cell D 1 is a conventional n-channel transistor which is turned ON when it is accessed. Therefore, when the dummy cell D 1 is accessed, a current flows from the first bit line BL 1 to ground through the dummy cell D 1 , and the data "1" is always read out. Since drain of the dummy cell D 2 is not connected to the bit line BL 2 , when the dummy cell D 2 is accessed, a current does not flow from the first bit line BL 1 to ground through the dummy cell D 2 , and the data "0" is always read out. In the erasure source control circuit 18, a WRITE signal is "High" during read and write operation, and an ERASE signal is "Low" during erasure operation. Therefore, in accordance with the input signal the n-channel transistor TN13 is turned on for read and write operations, to connect the common source line SL to ground, and the p-channel transistor is turned on for an erase operation, to apply a high voltage to the common source line SL. Fig. 9 is a diagram showing the row decoder 11 in more detail. The row decoder 11 consists of individual decoders, one indicated at 21, the number of decoders being equal to the number of word lines, and a voltage VC is applied to the word line selected by decoding the address signal. As VC, VCC is applied for a read operation, and VPP is applied for a write operation. TN6 indicates one of the AND gates forming the decoder; since /TROM SEL is "Low" when selecting a dummy cell, " Low" signal is applied to this gate to inhibit the selection of the normal memory cells Cij. The numeral 23 indicates a circuit for driving the dummy word line DWL; since TROM SEL is "High" when selecting a dummy cell, "High" signal is input so that the voltage VC is applied to the dummy word line DWL. As a result, the dummy cell is selected, and the normal memory cells are deselected. Fig. 10 shows the command register 1. A write command is input as a predetermined hexadecimal data such as #40 or #10. This data is supplied to the command register through the input data buffer, and the command register 1 outputs a /WRITE START signal which is a negative pulse signal generated when the write operation starts. Fig. 11 shows a part of the data comparator register 8 and a part of the data output buffer. In this circuit, an Exclusive NOR gate G30 corresponds to the data comparator. The data comparator register 8 consists of individual data comparators, one indicated in Fig. 11. Namely, each data bit is respectively judged at the circuit shown in Fig. 11. The portion except the Exclusive NOR gate G30 forms a latch circuit which latches a READ DATA i signal output from the sense amplifier 151. LTHD is a positive pulse signal generated when the memory cells including the dummy cells are read. This latch circuit outputs a READ DATA i signal. READ DATA i is compared with Din Latch Data i which is held in the data input buffer. When these data coincide, DATA MATCH i becomes "High". Fig. 12 shows the remaining portion of the data comparator register 8. All DATA MATCH i signals output from the circuits shown in Fig. 11 are further judged at two NAND gates G31 and G32, and a NOR gate G33 to determine whether or not all of them are "High". Namely, when read data of each bit respectively coincides to latched data which is same as the input data, an output of the NOR gate G33 becomes "High". During normal operation, since TEST, FAIL TEST, and PASS TEST signals are "Low", therefore, an ALL MATCH signal is "High" when read data of each bit respectively coincides to input data. Namely, the ALL MATCH signal represents a test result. As shown in Fig. 12, when the TEST is set to "High", it is possible to set the ALL MATCH to be "High" by inputting "High" signal as the PASS TEST signal, and it is possible to set the ALL MATCH to be "Low" by inputting a "High" signal as the FAIL TEST signal irrespective of the output the NOR gate G33. In a conventional status register test method, the ALL MATCH signal is set "High" or "Low" by setting the PASS TEST and FAIL TEST signals, and a path from this portion to the data output buffer through the status register is checked. Therefore, the prior art test method does not guarantee that the status register 2 will function properly when a failure occurs in the memory cell matrix 17A or the sense amplifier/write amplifier 15. However, in the first embodiment, this is guaranteed. Further, in the first embodiment, the conventional status register test method in which the PASS TEST signal and the FAIL TEST signal are used is also available. Fig. 13 is a diagram showing the write/erase timing generating circuit 9. This circuit 9 receives a /WRITE START signal from the command register 1 and an ALL MATCH signal from the data comparator register 8. When the ALL MATCH changes to "High" or when write operations are repeated for a predetermined number of times, the circuit 9 outputs a /WRITE END signal which is a negative pulse signal. Further, the circuit 9 outputs a WRITE FAIL signal which is a positive pulse signal. The status register 2 consists of individual registers. Figs. 14 and 15 respectively show each one of the individual registers in the status register 2. The status register shown in Fig. 14 receives the WRITE FAIL, and outputs a SR4 signal. The SR4 signal is set to "High" by inputting a /RESET signal which is a negative signal, and its state is held unless a WRITE FAIL signal is input. Namely, the SR4 is "Low" when a write operation is performed without failing, and the SR4 is "High" when a write operation fails. The status register shown in Fig. 15 outputs a busy signal as SR7 which is normally "High", and is "Low" during a write operation. Fig. 16 is a circuit diagram showing the data output buffer. The data output buffer consists of individual data output shown in Fig. 7, the number of data output buffers being equal to the number of bits of data signal. Each bit of data signal is output to a data signal input/output terminal such as a PIOi. This circuit is divided into two portions. One portion includes NAND gates G49 through G52, G56 through G58, and inverters G53 through G55. This portion receives a RDATA i signal output from the circuit shown in Fig. 11 and a SRi DATA signal output from the status register, and is controlled to output the RDATA i or the SRi DATA by inputting a /SRTK signal which is a negative pulse signal. When read data is read out, the /SRTK is set to a "High" state, and RDATA i passes through a NAND gate G56 to be output from a NAND gate G58. When status register data is read out, the /SRTK is set to a "Low" state, and SRi DATA passes through a NAND gate G57 to be output from the NAND gate G58. A portion consisting of an inverter G59, two input NAND gates G60, G61, a p-channel transistor TP6, and an n-channel transistor TN9, is an output circuit. When a Hi-Z signal is "High", either of the p-channel transistor TP6 or the n-channel transistor TN9 turns ON in accordance with output of the NAND gate G58. Namely, data is output to the PIOi. When the Hi-Z is "Low", both of p-channel transistor TP6 and the n-channel transistor TN9 turn OFF, and the output of the PIOi is at a high impedance state. In the above, circuits we've described only relate to the write mode, however, circuits to automatically perform the erase operation are also provided. The following describes a test procedure for testing the performance of the status register circuit 2 in the above embodiment. Fig. 17 is a flowchart showing the test procedure. To initiate the performance test, first a pass mode for normal operation or a fail mode that induces an operation failure is selected in step 101. Then, by applying a prescribed voltage to the terminal 31 of the test dummy cell select signal input circuit 19, the dummy cell select signal is applied to the row decoder 11 which then selects the word line connecting to the dummy cells. Next, in step 102, the column address is changed so as to select a dummy cell that is fixed to data "0" and is not alterable, or a dummy cell that is fixed to data "1" and is not alterable. For example, to test the function of the status register circuit for the write circuitry when a cell write is accomplished correctly, a dummy cell that is fixed to data "0" and is not alterable is selected. In this state, a write command is entered in step 103, and a normal write operation is performed in step 104. Then, the write operation should terminate normally. After the operation is completed through steps 105 and 106, the status register is read out in step 107 to determine whether the status register is functioning properly when the write operation is completed normally. On the other hand, to check the function of the status register circuit in case of the occurrence of a failure, a dummy cell that is fixed to data "1" and is not alterable is selected in step 102. In this state, when a normal write operation is performed, the writing should terminate in a failed state. Based on this, determination can be made as to whether the status register circuit is functioning properly in case of the occurrence of a write failure. Likewise, to test the function of the status register circuit for the erase circuitry, a dummy cell that is fixed to data "1" and is not alterable is selected if it is desired to test the function of the status register circuit when an erasure is done correctly. In this state, when a normal erase operation is performed, the erasure should terminate normally, based on which it can be determined whether the status register circuit is functioning properly when the erase operation is completed normally. On the other hand, to check the function of the status register circuit in case of the occurrence of an erasure failure, a dummy cell that is fixed to data "0" and is not alterable is selected. In this state, when a normal erase operation is performed, the erasure should terminate in a failed state. Based on this, a determination can be made as to whether the status register circuit is functioning properly in case of the occurrence of an erasure failure. Thus, the testing is performed in a comprehensive manner, including the entire write and erase circuitry, to check the performance of the entire circuit including the automatic circuit for both cell normal and failed states. Alternatively, the test may be so configured that the test signal for selecting the dummy cell is input to the column address side; in this state, the row address is changed so as to select a dummy cell that is fixed to data "0" and is not alterable or a dummy cell that is fixed to data "1" and is not alterable. In this configuration also, the same effect as described above can be achieved. Thus, in the above embodiment, it is possible to check the performance of the entire circuit, including the internal automatic circuitry, thereby contributing greatly to improving the reliability.

Claims: A nonvolatile semiconductor memory comprising: a plurality of word lines (WLi) and a plurality of bit lines (BLj) arranged in a grid pattern; a memory cell matrix (17) consisting of electrically erasable nonvolatile memory cells (Cij) whose gates are connected to said word lines (WLi) and whose drains are connected to said bit lines (BLj), each of said memory cells (Cij) being formed at one of the intersections between said word lines (WLi) and said bit lines (BLj); a sense amplifier (15) for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell (Cij) located at the intersection between a selected word line (WLi) and a selected bit line (BLj) is conducting or nonconducting; a write/erase timing circuit (9) for automatically performing timing control necessary for writing data into and erasing data from said memory cells (Cij); and a status register (2) for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally; said nonvolatile semiconductor memory being characterised by the provision of dummy cells (D1, D2, D3,...) provided outside the address of said memory cell matrix (17) and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier (15) outputs a logic value "1" or "0" depending on the state of the accessed dummy cell; and control means (19) for performing control so that said dummy cells (D1, D2, D3, ...) are accessed when said write/erase timing circuit (9) is operated to test the performance of said status register (2). A performance test method for a nonvolatile semiconductor memory comprising: a plurality of word lines (WLi) and a plurality of bit lines (BLj) arranged in a grid pattern; a memory cell matrix (17) consisting of electrically erasable nonvolatile memory cells (Cij) whose gates are connected to said word lines (WLi) and whose drains are connected to said bit lines (BLj), each of said memory cells (Cij) being formed at one of the intersections between said word lines (WLi) and said bit lines (BLj); a sense amplifier (15) for outputting a signal corresponding to a logic value "1" or "0" by detecting the amount of current that varies according to whether the memory cell (Cij) located at the intersection between a selected word line (WLi) and a selected bit line (BLj) is conducting or nonconducting; a write/erase timing circuit (9) for automatically performing timing control necessary for writing data into and erasing data from said memory cells (Cij); and a status register (2) for storing the operating state of said memory at the completion of the operation of said write/erase timing circuit in such a manner that the stored state is accessible externally; characterised in that said method comprises the steps of: providing dummy cells (D1, D2, D3,...) outside the address of said memory cell matrix (17) and consisting of electrically unalterable cells each preset to one of two states so that said sense amplifier (15) outputs a logic value "1" or "0" depending on the state of the accessed dummy cell; providing a write failure state or an erasure failure state by attempting to write a logic value "0" to a cell, of said dummy cells (D1, D2, D3 ...), preset to a logic value "1", or by attempting to erase a cell preset to a logic value "0" and confirming that the cell does not change to the logic value "1"; providing a write normal state by attempting to write a logic value "1" to a cell, of said dummy cells (D1, D2, D3, ...), preset to a logic value "l", or by attempting to write a logic value "0" to a cell preset to a logic value "0"; providing an erasure failure state by attempting to erase a cell, of said dummy cells (D1, D2, D3,...), preset to a value corresponding to a written state; or providing an erasure normal state by attempting to erase a cell, of said dummy cells (D1, D2, D3, ...), preset to a value corresponding to an unwritten state.

Inventors: KASA YASUSHI, KUMAKURA SINSUKE, WATANABE HISAYOSHI, YAMAZAKI HIROKAZU, KASA, YASUSHI, KUMAKURA, SINSUKE, WATANABE, HISAYOSHI, YAMAZAKI, HIROKAZU, KASA, YASUSHI, C/O FUJITSU LIMITED, KUMAKURA, SINSUKE, C/O FUJITSU LIMITED, WATANABE, HISAYOSHI, C/O FUJITSU LIMITED, YAMAZAKI, HIROKAZU, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1994
Main classification: G11C29
IPC codes: G11C29, H01L21, G11C16, G11C17, G11C7, H01L27, G01R31, G11C5