Video signal format compression apparatus

Abstract: A video signal format compression apparatus in accordance with a first exemplary embodiment of the present invention takes out a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A video signal format compression apparatus in accordance with a second exemplary embodiment of the present invention uses a FIFO memory which is unnecessary to generate an address. Therefore, the circuit scale can be made small. A video signal format compression apparatus in accordance with a third exemplary embodiment of the present invention can select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. A video signal format compression apparatus in accordance with a fourth exemplary embodiment of the present invention can change a display position of the picture.

Description: FIELD OF THE INVENTION The present invention relates to a video signal compression apparatus for horizontally compressing a video signal of television receivers, video cassette recorders, video projectors, etc. BACKGROUND OF THE INVENTION Recently, wide screen displays having an aspect ratio of 16:9 shown in FIG. 12(a) are spreading in the Japanese market. When an ordinary video signal having an aspect ratio of 4:3, that is 12:9 is applied to a display apparatus having an aspect ratio of 16:9, the displayed picture is horizontally deformed (elongated). As a result, a true circle, for example, is displayed as an ellipse as shown in FIG. 12(a). Accordingly, order to get a correct picture, it is necessary to compress video signal horizontally as shown in FIG. 12(b). In FIG. 12, picture aspect ratio is 4:3, while the screen aspect ratio is 16:9. A block diagram of a video signal compression apparatus in accordance with the prior a]! is shown in FIG.9 (see e.g. the article 54(3) EPC-publication EP-A-0 582 305). A line memory 31 using an SRAM (static random access memory) stores an input video signal in order from the address 0 and when a read address An is given, outputs data Dn and Dn+1 for the address An and An+1, respectively. An address generator 32 includes a counter 34, a multiplier 35 and an adder 36. The counter 34 counts the number of clock pulses and outputs 0, 1, 2, 3, ...., after being cleared, synchronizing with a horizontal sync signal 103. The multiplier 35 multiplies the output of the counter 34 by a specific value given from the outside. This specific value determines a compression ratio. The adder 36 adds an integer part of the output of the multiplier 35 and the output of the counter 34 and makes a read address An of the line memory 31. An interpolation filter 33 includes a subtracter 37, a multiplier 38 and an adder 39. The subtracter 37 calculate data (Dn+1 - Dn). The multiplier 38 multiplies the data (Dn+1 - Dn) by a decimal part of the output of the multiplier 35. The adder 39 adds the data Dn and the output of the multiplier 38 and outputs the sum. The output of the adder 39 is a compressed video signal as explained below. The performance of a video signal compression apparatus in accordance with the prior art is explained using a time chart shown in FIG.10. (a) The data of the input video signal is stored in the line memory 31 in order from address 0. (b) The multiplier 35 calculates the products of the output 0, 1, 2, 3 ... of the counter 34 and a specific value (1/3 in this case). The calculated result is separated to an integer part and a decimal part. (c) The read address An is made from the sum of the integer part and the output of the counter 34. (d) When the read address An is inputted, the line memory 31 outputs the data Dn and Dn+1. (e) The subtracter 37 calculates data (Dn+1 - Dn). (f) The multiplier 38 multiplies the data (Dn+1 - Dn) by the decimal part separated from the output of the multiplier 35. (g) The adder 39 adds the data Dn and the output of the multiplier 38 and outputs a compressed video signal. FIG.11(a) shows a video signal before compression, that is an input video signal and FIG.11(b) shows a video signal after compression, that is an output signal of the video signal compression apparatus. The axis of abscissa shows time and the axis of ordinate shows signal level. SUMMARY OF THE INVENTION A video signal compression apparatus as claimed in claim 1 in accordance with a first exemplary embodiment of the present invention takes out and uses a specific value written in an ROM (read only memory) at every system clock signal. The specific value representing a predetermined compression ratio can be varied at at every system clock. Therefore, for example only the center part of the image can be horizontally compressed. A video signal compression apparatus as claimed in claim 2 in accordance with a second exemplary embodiment of the present invention uses a FIFO (first in, first out) memory which does not need to generate address. Therefore, the circuit scale can be made small. A video signal compression apparatus as claimed in claim 3 in accordance with a third exemplary embodiment of the present invention can select a mode with a constant compression value or a mode to vary a compressed value at every system clock pulse. Further, the constant compression value can be set from the outside. A video signal compression apparatus as claimed in claim 4 in accordance with a fourth exemplary embodiment of the present invention can vary a display position of the picture. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram of a video signal compression apparatus in accordance with a first exemplary embodiment of the present invention. FIG.2 shows a timing chart of a video signal compression apparatus in accordance with the first exemplary embodiment of the present invention. FIG.3 is a block diagram of a video signal compression apparatus in accordance with a second exemplary embodiment of the present invention. FIG.4 shows a timing chart of a video signal compression apparatus in accordance with the second exemplary embodiment of the present invention. FIG.5 is a block diagram of a video signal compression apparatus in accordance with a third exemplary embodiment of the present invention. FIG.6 illustrates displayed pictures for three different compression ratios of a video signal compression apparatus in accordance with the third exemplary embodiment of the present invention. FIG.7 is a block diagram of a video signal compression apparatus in accordance with a fourth exemplary embodiment of the present invention. FIG.8 shows timing chart of a video signal compression apparatus in accordance with the fourth exemplary embodiment of the present invention. FIG.9 is a block diagram of a video signal compression apparatus in accordance with the prior art. FIG.10 shows a timing chart of a video signal compression apparatus in accordance with the prior art. FIG.11 shows how a video signal is compressed. FIG.12 illustrates pictures before and after the video signal is compressed. DETAILED DESCRIPTION OF THE INVENTION (First exemplary embodiment) A block diagram of a video signal compression apparatus in accordance with a first exemplary embodiment of the present invention is shown in FIG.1. A line memory 11 stores an input signal in order from the address 0 and when a read address An is given, the line memory 11 outputs data Dn for the address An and data Dn+1 for the address An+1. A counter 12 counts the number of system clock pulses after being cleared, synchronizing with a horizontal sync signal 103 and outputs counted data 0, 1, 2, 3 ... . An ROM 13 outputs a specific value (a predetermined compression ratio value) which is previously written, individually corresponding to each counted data of the counter 12. An adder 14 adds an output of a flip-flop 15 and an output of the ROM 13. An integer part in the output of the flip-flop 15 is used for a read address of the line memory 11. A subtracter 16 calculates (Dn+1 - Dn). A multiplier 17 multiplies the data (Dn+1 - Dn) by the decimal part of the output of the flip-flop 15. An adder 18 adds the data Dn and the output of the multiplier 17 and outputs the sum. The output of the adder 18 is a compressed video signal as explained below. The performance of a video signal compression apparatus in accordance with the first exemplary embodiment of the present invention is explained a timing chart shown in FIG.2. (a) The data of the input signal is stored in the line memory 11 in order from the address 0. (b) The counter 12 outputs the counted data 0, 1, 2, 3 ... (c) The Rom 13 outputs the specific value previously written, individually corresponding to each counted data of the counter 12. (d) The output of the flip-flop 15 is an integral value of the specific value outputted from the ROM 13 and is separated to an integer part and a decimal part. (e) The integer part of the output of the flop-flop 15 is used for the read address An. (f) By inputting the read address An, the line memory 11 outputs the data Dn and Dn+1. (g) The subtracter 16 calculates the data (Dn+1 - Dn). (h) The multiplier 17 multiplies the data (Dn+1 - Dn) which is an output of the subtracter 16 by the decimal part separated from the output of the flip-flop 15. (i) The adder 18 adds the data Dn and the output of the multiplier 17 and outputs a compressed video signal. According to the first exemplary embodiment of the present invention, the compression ratio can be varied at every system clock signal. For example, it is possible to compress only the center part of the picture. (Second exemplary embodiment) A block diagram of a video signal compression apparatus in accordance with a second exemplary embodiment of the present invention is shown in FIG. 3. A FIFO memory 21 stores an input video signal in order. A timing generator 22 generates a RE (read enable) pulse to control the FIFO memory 21 and an interpolation coefficient for interpolation. A flip-flop 23 delays the output of the FIFO memory 21 A subtracter 24 subtracts an output of the flip-flop 23 from the output of the FIFO memory 21. A multiplier 25 multiplies the output of the subtracter 24 by the interpolation coefficient generated at the timing generator 22. An adder 26 adds the output of the flip-flop 23 and the output of the multiplier 25 and outputs the sum. The output of the adder 26 is a compressed video signal as explained below. The performance of a video signal compression apparatus in accordance with the second exemplary embodiment of the present invention is explained using a timing chart shown in FIG.4. (a) Data of an input video signal is stored in the FIFO memory 21 in order. (b) A read clock signal 30 and a RE pulse are inputted to the FIFO memory 21. A system clock signal having two times of the write clock frequency is used for a read clock signal. Because only the clock signal which is coincident with the RE pulse is effective, the data is read out repeating a cycle of two time read and one time rest. (c) The data read out is delayed at the flip-flop 23. (d) The subtracter 24 subtracts the output of the flip-flop 23 from the data read out. (e) The multuplier 25 multiplies the output of the subtracter 24 by an interpolation coefficient generated at the timing generator 22. (f) The adder 26 adds the output of the flip-flop 23 and the output of the multuplier 25 and outputs a compressed video signal. (g) The input video signal is compressed into 3/4 and the number of data increases to two times of the original. If unnecessary, they are thinned out. Although a 3/4 compression was explained above, any compresion ratio can be realized by varying the number of cycles of the RE pulse and the interpolation coefficient. According to the second exemplary embodiment of the present invention, because a FIFO memory 21 which an address generation is unnecessary is used, the circuit scale can be made small. (Third exemplary embodiment) A block diagram of a video signal compression apparatus in accordance with a third exemplary embodiment of the present invention is shown in FIG.5. A counter 113 counts the number of clock pulses after being cleared by a horizontal sync signal 102 for writing and outputs a write address. A memory 211 stores an input video signal at the write address generated at the counter 113 and when a read address An which is an integer part of the output of the flip-flop 15 is inputted to the memory 211, the memory 211 outputs data Dn and Dn+1 for the address An and An+1, respectively. A specific value generator 100 counts the number of clock pulses after being cleared by a horizontal sync signal 103 for reading and outputs a specific value previously written, individually corresponding to each counted data at every count. A signal selecting means 106 selects either the specific value generated at the specific value generator 100 or a fixed specific value 104 inputted from the outside according to a selection command 105. An adder 14 adds the output of the flip-flop 15 and the output of the signal selecting means 106. The flip-flop 15 latches the output of the adder 14. The integer part of the output of the flip-flop 15 is used for a read address of the memory 211. A subtracter 16 calculates data (Dn+1 - Dn). A multiplier 17 multiplies the data (Dn+1 - Dn) by the integer part of the output of the flip-flop 15. An adder 18 adds the data Dn and the output of the multiplier 17 and outputs the sum. The output of the adder 18 is a compressed video signal as explained below. Pictures produced by a video signal compression apparatus in accordance with the third exemplary embodiment of the present invention are illustrated in FIG.6. When the input video signal is desired to be outputted as it is, the signal selecting means 106 is set to select a terminal B and a fixed specific value R which the compression ratio is 1 is inputted from the outside to the terminal B. The picture in this case is illustrated in FIG.6(a). When the input video signal is desired to be horizontally compressed to 3/4, the signal selecting means 106 is also set to select the terminal B and a fixed specific value S which the compression ratio is 3/4 is inputted from the outside to the terminal B. The picture in this case is illustrated in FIG.6(b). When the compression ratio is desired to be varied at every clock pulse, the signal selecting means 106 is set to select the terminal A and a specific value T shown in FIG.6(d) is inputted from the specific value generator 100 to the terminal A. The picture in this case is illustrated in FIG.6(c). According to the third exemplary embodiment of the present invention, it is possible to select a mode in which the compression ratio is constant or another mode in which the compression ratio is varied at every system clock pulse. Further, in the mode in which the compression ratio is constant, an arbitrary compression ratio can be set from the outside. (Fourth exemplary embodiment) A block diagram of a video signal compression apparatus in accordance with a fourth exemplary embodiment of the present invention is shown in FIG.7. A counter 113 counts the number of clock pulses after being cleared by a horizontal sync signal 102 for writing data and outputs a write address. A memory 211 stores an input video signal in the write address generated at the counter 113 and when a read address An which is an integer part of the output of the flip-flop 15 is inputted to the memory 211, the memory 211 outputs data Dn and Dn+1 for the address An and An+1, respectively. A counter 112 counts the number of clock pulses after being cleared by a horizontal sync signal 103 for reading data and when the counted data reaches a data value a designated from the outside, the counter 112 outputs a reset signal L to a counter 212 and a second signal selecting means 111. The counter 212 counts the number of clock pulses after being cleared by the reset signal L and outputs the counted data 0, 1, 2, 3 ... to an ROM 13. The ROM 13 outputs a specific value previously written, individually corresponding to each counted data of the counter 212 at every count. A first signal selecting means 106 selects either a specific value generated at the ROM 13 or a fixed specific value 104 inputted from the outside according to a selection command 105. An adder 14 adds an output of the flip-flop 15 and the output of the first signal selecting means 106. A second signal selecting means 111 usually selects an output of the adder 14 but only when the reset signal L is generated, the second signal selecting means 111 selects a read start addressing A inputted from the outside for a short time. The flip-flop 15 latches the output of the second signal selecting means 111. The integer part of the output of the flip-flop 15 is used for a read address of the memory 211. A subtracter 16 calculates data (Dn+1 - Dn). A multiplier 17 multiplies the data (Dn+1 - Dn) by the decimal part of the output of the flip-flop 15. An adder 18 adds the data Dn and the output of the multiplier 17 and outputs the sum. The output of the adder 18 is a compressed video signal, as explained below. The performance of a video signal compression apparatus in accordance with the fourth exemplary embodiment of the present invention is explained using a timing chart shown in FIG. 8. (a) A data value a is inputted to the counter 112 from the outside. (b) A read start addressing A is inputted from the outside. (c) The counter 112 is cleared. (d) The counter 112 outputs a reset signal L after a clock pulses. The counter 212 is cleared by the reset signal L. The second signal selecting means 111 selects the read start addressing A for a short time only when the reset signal L is generated and outputs the read start addressing A to the flip-flop 15. (e) The counter 212 counts the number of clock pulses after being cleared by the reset signal L and outputs the counted data 0, 1, 2, 3 ... to the ROM 13. The ROM 13 outputs the specific value a, b, c, d ... previously written, individually corresponding to each counted data. (f) The flip-flop 15 outputs the address A, A + a, A + a + b .... . In the fourth exemplary embodiment of the present invention, the picture position and the compression position can be selected by the values a and A inputted from the outside.

Claims: A video signal compression apparatus comprising: line memory means (11) for storing an input video signal and outputting data Dn corresponding to a read address An and data Dn+1 corresponding to a read address An+1; counter means (12) for counting the number of system clock pulses; read only memory means (13) for outputting a predetermined compression ratio value, individually corresponding to each count at receiving counted data from said counter means (12); first adder means (14) for adding the output of the read only memory means (13) and the output of flip-flop means (15); said flip-flop means (15) for latching the output of said first adder means (14), wherein an integer part of the output of said flip-flop means (15) is said read address An of said line memory means (11); subtracter means (16) for calculating (Dn+1 - Dn); multiplier means (17) for multiplying the data (Dn+1 - Dn) by a decimal part of the output of said flip-flop means (15); and second adder means (18) for adding the data Dn and the output of said multiplier means (17) and outputting a compressed video signal. A video signal compression apparatus comprising: FIFO memory means (21) for storing an input video signal, said FIFO memory means having a read clock signal (30) input thereto; timing generator means (22) for generating a read enable pulse to control said FIFO memory means (21) and for generating a designated interpolation coefficient; said FIFO memory means being controlled to output said video signal when said read enable pulse coincides with said read clock signal; flip-flop means (23) for latching the output of said FIFO memory means (21); subtracter means (24) for subtracting the output of said flip-flop means (23) from the output of said FIFO memory means (21); multiplier means (25) for multiplying the output of said subtracter means (24) and said designated interpolation coefficient outputted from said timing generator means (22); and adder means (26) for adding the output of said multiplier means (25) and the output of said flip-flop means (23) and outputting a compressed video signal; wherein the video signal compression ratio is varied by varying the number of cycles of said generated read enable pulses and said generated interpolation coefficient; A video signal compression apparatus comprising: memory means (211) for storing an input video signal (101) and outputting data Dn corresponding to a read address An and data Dn+1 corresponding to a read address An+1, when a read address An is inputted; predetermined compression ratio value generator means (100) for counting a number of system clock pulses and outputting a predetermined compression ratio value corresponding to said number of counted system clock pulses; signal selector means (106) for selecting one of said predetermined compression ratio value and another predetermined compression ratio value (104) inputted from the outside according to a selection command (105); first adder means (14) for adding the output of said signal selector means (106) and the output of a flip-flop means (15); said flip-flop means (15) for latching an output of said first adder means (14), wherein the integer part of the output of said flip-flop means (15) is an address An of read address of said memory means (211); subtracter means (16) for calculating data (Dn+1- Dn); multiplier means (17) for multiplying said data (Dn+1 - Dn) by the decimal part of the output of said flip-flop means (16); and second adder means (18) for adding the data Dn and the output of said multiplier means (17) and outputting a compressed video signal. A video signal compression apparatus comprising: memory means (211) for storing an input video signal (101) and outputting data Dn corresponding to the address An and data Dn+1 corresponding to the address An+1, when a read address An is inputted; first counter means (112) for counting the number of system clock pulses after being cleared by a horizontal sync signal for reading (103) and outputting a reset signal (L) to a second counter means (212) and a second signal selector means (111), when the counted data reaches a designated value (a) supplied from the outside; said second counter means (212) for counting the number of system clock pulses after being cleared by said reset signal (L) and outputting the counted data to a read only memory means (13) at every count; read only memory means (13) for outputting a predetermined compression ratio value, individually corresponding to each counted data at every reception of the counted data from said second counter means (212); first signal selector means (106) for selecting either the output of said read only memory means (13) or a another predetermined compression ratio value (104) supplied from the outside according to a selection command (105); first adder means (14) for adding the output of said first signal selector means (106) and the output of a flip-flop means (15); said second signal selector means (111) for usually selecting the output of said first adder means (14) and selecting a read start address command (A) inputted from the outside for a short time only when said reset signal is generated being actuating said selector means (111); said flip-flop means (15) for latching the output of said second signal selector means (111), wherein the integer part of the output of said flip-flop means (15) is the read address An of said memory means (211); subtracter means (16) for calculating data (Dn+1 - Dn); multiplier means (17) for multiplying said data (Dn+1 - Dn) by the decimal part of the output of said flip-flop means (15); and second adder means (18) for adding the data Dn and the output of said multiplier means (17) and outputting a compressed video signal.

Inventors: IZAWA YOSUKE, NIO YUTAKA, OKUMURA NAOJI, SATO TOSHICHIKA, TANI MASAHIRO, IZAWA, YOSUKE, NIO, YUTAKA, OKUMURA, NAOJI, SATO, TOSHICHIKA, TANI, MASAHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H04N5
IPC codes: H04N5