LOOK-UP ENGINE FOR PACKET-BASED NETWORK

Abstract: An arrangement is disclosed for parsing packets in a packet-based data transmission network. The packets include packet headers divided into fields having values representing information pertaining to the packet. The arrangement comprises input receiving fields from the packet headers of incoming packets, a memory for storing information related to possible values of said fields, and a device for retrieving said stored information appropriate to a received field value. The retrieving device comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and a controller for controlling the operation of the memory. The arrangement is capable of performing fast look-up operations at a low cost of implementation.

Description: LOOK-UP ENGINE FOR PACKET-BASED NETWORK This invention relates to the field of data communications, and more particularly to packet-based networks. There are two broad classes of network: circuitbased and packet-based. Conventional telephone networks are circuit based. When a call is established in a circuit-based network, a hard-wired connection is set up between the calling parties and remains in place for the duration of the call. Circuit-based networks are wasteful of available bandwidth and lack flexibility. Packet-based networks overcome many of the disadvantages of circuit-based networks. In a packetbased network, the data are assembled into packets containing one or more address fields which define the context of a packet, such as protocol type and relative positions of other fields embedded in the packet. LAN bridges and routers use the information in the packet to forward it to the destination. In a packet-based network, a packet must be parsed as it flows through the network. Parsing is the process of extracting and analyzing the information, such as source and destination address and net layer protocol, contained in the packets. In known networks, packet parsing is generally performed with a microprocessor, which provides flexibility in handling different packet types and can be upgraded to handle new packet types as they are defined. Content Addressable Memory (CAM) is commonly used for hardware assistance to speed up searches through a list of known addresses. This is a tedious task. CAMs are also relatively expensive and limited in size and availability. General purpose processor architectures are not specifically directed toward the types of operations required in packet parsing and so they tend to be inefficient. To meet performance requirements, a fast but expensive processor based solution can be implemented. In the highest performance systems, hardware solutions are implemented to increase speed, but at the cost of flexibility. An object of the invention is to provide a fast, but inexpensive solution to the problem of packet-parsing in packet-based networks. According to the present invention there is provided an arrangement for parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, said arrangement comprising input means for receiving fields from said packet headers of incoming packets, means for storing information related to possible values of said fields, and means for retrieving said stored information appropriate to a received field value, characterized in that said retrieving means comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and controller means for controlling the operation of said at least one memory. The memory and retrieving means constitute a look-up engine, which is the central resource containing all information necessary for forwarding decisions. In a packetized data transmission conforming to IEEE802 standards, the packets have a MAC (medium access control) header containing information about the destination and source addresses and the net layer protocol. The invention permits packet switching to be achieved in a bridge-router, for example an Ethernet to ATM bridge-router, at a rate of about 178,000 packets per second using 64 byte minimum Ethernet packets. This means that the MAC headers are interpreted once every 5.6 micro seconds. The look-up engine preferably employs table look-ups using nibble indexing on variable portions of the packet, such as MAC and network layer addresses, and bit pattern recognition on fixed portions for network layer protocol determination. Each look-up table is organized into a hexadecimal search tree. Each search tree begins with a 16 word root table. The search key (e.g. MAC address) is divided into nibbles which are used as indices to subsequent tables. The 16 bit entry in the table is concatenated with the next 4 bit nibble to form the 20 bit address of the next 16 word table. The final leaf entries point to the desired information. Bit pattern recognition is achieved by a microcode instruction set. The microcode engine has the ability to compare fields in a packet to preprogrammed constants and perform branches and index increments in a single instruction cycle typically. The microcode engine has complete control over the search procedure, so it can be tailored to specific look-up functions. New microcode is downloaded as new functions are required. The look-up engine can perform up to two tree searches in parallel with microcode execution. Look-up time is quick because the microcode determines the packet's network layer format while the source and destination addresses are being searched in parallel. The results of the source and destination look-ups and the protocol determination arrive at roughly the same time, at which point the next level of decisions is made. The look-up engine also performs protocol filtering between areas. The system allows devices to be grouped arbitrarily into areas on a per protocol basis and defines filtering rules among these areas. The look-up engine keeps track of each station's area for each of its protocols. The source and destination areas are crossindexed in a search tree, which is used to find the filtering rule between the two areas. Separate filtering rules are defined for bridging and network layer forwarding; bridging is normally allowed within an area while network layer forwarding is selectively allowed between areas. The parsing controller typically has a pointer to the current field in the packet being examined. The controller moves this pointer to the next field in the packet after all decisions based on the current field are made. At each decision point on a tree, the current field is compared to a known value or range. If the comparison yields a true condition, the controller moves to the next decision point by moving the current field pointer. Otherwise the field pointer is left alone and controller branches to new code to compare the current field to a different value or range. This process is repeated until a final decision is made. Moving to the next decision point requires several discrete steps in a general purpose processor. Unlike a general purpose processor, which has the disadvantage that it only has a single memory bus for both instruction and data fetches, the Look-up engine controller has separate buses for instruction and data and typically performs one decision per step. Fast decisions are made possible by a special set of instructions which both conditionally move the pointer and conditionally branch to new code in a single step. The comparisons and pointer movements can be byte or word wide, according to the current field's size. The look-up engine implements other optimized instructions which perform bit level logical comparisons and conditional branches within the same cycle as well as other instructions tailored to retrieving data from nibble-indexed data structures. The look-up engine is preferably divided into the following sections: a) one or more nibble tree address look-up engines (ALE) b) one microcode engine Each ALE is used to search for addresses in a tree structure in its own large bank of memory. The result of a search is a pointer to pertinent information about the address. An ALE is assigned to destination addresses (DALE) and source addresses (SALE). The ALEs operate independently of each other. The microcode engine is used to coordinate the search. It invokes the SALE and DALE to search for the source and destination addresses respectively and continues on to parse the remainder of the packet using an application-specific instruction set to determine the protocol. The SALE, DALE and microcode engine can execute in parallel and arrive at their corresponding results at roughly the same time. The microcode engine then uses the SALE and DALE results along with its own to arrive at the forwarding decision. The advantage of using RAM over a CAM is expandability and cost. Increasing RAM is a trivial and inexpensive task compared to increasing CAM size. The advantage of the microcode engine over a general purpose processor is that an ASIC implementation of the function is much less expensive and less complex than a processor-based design with all the overhead (RAM, ROM) associated with it. The invention also related to a method of parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, comprising storing information related to possible values of said fields, receiving fields from said packet headers of incoming packets, and retrieving said stored information appropriate to a received field value, characterized in that said information is stored in a memory organized in a hierarchical tree structure. The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is an example of a MAC layer header of a typical packet; Figure 2 shows the data paths in a typical bridgerouter between Ethernet LAN and ATM networks; Figure 3 is a block diagram of a first embodiment of a look-up engine in accordance with the invention; Figure 4 is a block diagram of a look-up engine controller for the look-up engine shown in Figure 3; Figure 5 is a block diagram of a second embodiment of a look-up engine in accordance with the invention; Figure 6 is a block diagram of a look-up engine controller for the look-up engine shown in Figure 5; Figure 7 is a map of look-up engine Address Look-up engine (ALE) memories; Figure 8 is a diagram illustrating search tree operation in an ALE; ; Figure 9 shows one example of a MAC search tree; Figure 10 shows the effect of the organizationally unique identifier of the MAC addresses on the size of the search tree; Figure 11 shows the source address look-up engine table; Figure 12 shows the destination address look-up table; Figure 13 illustrates the look-up engine addressing modes; Figure 14 shows a station information block; Figure 15 shows a port information block; Figure 16 shows an example of protocol filtering; Figure 17 shows a look-up engine controller Instruction State Machine; Figure 18 shows a typical fast timing diagram; and Figure 19 shows a typical SIB RAM access instruction timing diagram. A typical look-up engine (LUE) in accordance with the invention is designed to be used in a twelve-port wire speed Ethernet to ATM bridge-router capable of switching about 178,000 packets per second using 64 byte minimum Ethernet packets. This packet rate corresponds to a look-up request occurring every 5.6 uses. The LUE is used each time a packet is received off the Ethernet or the ATM network. The type of information that the engine provides depends on the direction of packet flow and the type of packet. The look-up engine provides all the information needed to find the path to each known destination, as well as default information in the case of unknown destinations. Figure 1 shows a typical MAC layer header format for a packet that can be parsed with the aid of the look-up engine in accordance with the invention. The header comprises destination and source address fields 100, 101, a network layer protocol type field 102, and network layer destination and source address fields 103, 104. Figure 1 also illustrates how the header is parsed in accordance with the invention. All fields except 102 are parsed using a tree search. The Net Layer Protocol Type field 102 is parsed by using microcode comparisons in the microcode engine to be described. On a bridge-router, each port is represented by a corresponding bit in a PortSet (Ports 0-11), which is a 16 bit value that has local significance only. The Control Processor and ATM are each assigned a port. The following definitions are special cases of a PortSet: SinglePortSet a PortSet with a single bit set. HostPortSet a SinglePortSet corresponding to the Control Processor MyPortSet a SinglePortSet corresponding to the source port of this packet. NullPortSet a PortSet of no ports. A Connection Identifier (CI), which is a 16 bit value with local significance only, is used to map connections into VPI/VCI values. The following definitions are special cases of CI: Mesh cm a CI corresponding to a path towards the destination endstation's Bridge-router. Null CI a CI connected to nothing. It is returned when the destination is attached to the local Bridge-router or if the connection is not allowed. RAS CM a CI corresponding to a path to the Route Server. ABS¯CI a CI corresponding to a path to the Address/Broadcast Server. MAC layer addresses are globally unique 48 bit values, except in some protocols such as DECNet, where they may not be globally unique. Unicast¯DA a MAC layer destination address of an end-station. Router¯DA a MAC layer destination address of the Route Server. An end station sends packets to the Route Server when it cannot send to the destination directly at the MAC layer. Broadcast¯DA the broadcast MAC layer address (all ones) which is received by all end-stations. It cannot be a source address. Multicast¯DA a multicast MAC layer address (group bit set) which is received by end-stations that recognize that multicast address. Network layer (NL) addresses are network protocol dependent. They are generally divided into Network, Subnet, and Node portions, although not all protocols have all three present. The Network Layer Address Field Sizes (in bits) are summarized in the table below. EMI11.1 <tb> Protocol <SEP> Total <SEP> Slze <SEP> Network <SEP> sublet <SEP> Node <tb> IP <SEP> 32 <SEP> 8/16/24 <SEP> variable <SEP> variable <tb> IPX <SEP> 80 <SEP> n/a <SEP> 32 <SEP> 48 <tb> <SEP> (MAC <SEP> address) <tb> AppleTalk <SEP> 24 <SEP> n/a <SEP> 16 <SEP> 8 <tb> DECNet <SEP> 64 <SEP> 16 <SEP> 38 <SEP> 10 <tb> <SEP> (reserved) <SEP> (32 <SEP> = <tb> <SEP> 'HIORD') <SEP> <tb> <SEP> (6 <SEP> = <SEP> subnet) <SEP> <tb> The look-up engine handles unicast network layer addresses. When the look-up engine is used in a bridge-router providing an interface between an Ethernet and ATM network, packets coming from the Ethernet side are fed into the Look-up Engine. The result of the look-up has the form: Input - > Command, CI, PortSet where Input is derived from the first few bytes of the packet and Command is an opcode to the AXE (Transfer engine). The Quad MAC status word distinguishes between router MAC, broadcast and multicast MACs. Bridging occurs when the destination address is a unicast address other than the Route Server address. Bridging is allowed between two endstations in the same area for a given protocol. Both source and destination MAC addresses must be known before automatic bridging/filtering is performed; otherwise, the packet is sent to the Route Server for: SA (Source Address) validation if the SA has never been seen speaking a given protocol DA (Destination Address) resolution if the DA was not found in the local MAC cache. The Bridge command instructs the AXE (Transfer Engine) to use RFC-1483 bridge encapsulation. BridgeProp command instructs the AXE to use bridge-router encapsulation (include source PortSet in encapsulation) Unknown¯SA - > BridgeProp, Null CI, HostPortSet, Myportset Unknown SA - send to HP for Spanning Tree processing HP will decide whether to forward it to ABS for learning, depending on Spanning Tree state Unicast¯DA - > Bridge, Mesh CI, NullPortSet DA in the same area on a different Bridge-router Unicast¯DA - > Bridge, Null CI, NullPortSet DA not in the same area (reject) Protocol not allowed to bridge-router DA on the same port Unicast¯DA - > Bridge, Null¯CI, SinglePortSet DA in the same area on the same Bridge-router but on a different port Unknown¯DA - > BridgeProp, ABS¯CI, NullPortSet, MyPortSet DA not found in the table - send to ABS for flood processing Broadcast¯DA - > BridgeProp, ABS CI, NullPortSet, MyPortSet Broadcast DA - Send to Control Processor for broadcast processing Multicast¯DA - > BridgeProp, ABS CI, NullPortSet, MyPortSet Multicast DA - Send to ABS for multicast processing Multicast¯DA - > BridgeProp, Null¯CI, HostPortSet, MyPortSet Multicast DA is of interest to HP (eg Spanning Tree) HP will decide whether to forward it to ABS for multicast processing Routing occurs when the destination address is the unicast Route Server address. Filtering rules between areas are explicitly defined per protocol. The per protocol source area is an attribute of the source MAC address and the per protocol destination area is an attribute of the destination NL address. Both source MAC and destination NL addresses must be known before network layer forwarding can occur. The packet will be bridged to the Route Server if any of the following are true: IP options are present Protocol is unknown The packet will be dropped if any of the following are true: Source area is not allowed to send to Destination area for this protocol Source NL address is invalid (eg. any IP broadcast address) Checksum is invalid Time-To-Live field expires Unicast¯NLDA - > Route, Mesh CI, NullPortSet NL node on a different bridge-router Unicast¯NLDA - > Route, Null CI, SinglePortSet NL node on the same bridge-router (could be same port) Unknown¯NLDA - > Bridge, RS CI, NullPortSet unknown NL node - send to Route Server Unknown¯Protocol - > Bridge, RS CI, NullPortSet protocol unknown, or packet with options Figure 2 shows the data paths in a typical bridgerouter. Control processor 16 has control over the formatting of packets it sends and receives. If the control processor 16 wants look-up engine 17 to perform a look-up, it formats the packet in the same way as Quad Mac 15; otherwise it sends it as a raw packet, which does not require a lengthy look-up. The control processor predetermines the destination by providing a CI (Connection Identifier) and an output Portset as part of the data stream. A bit in the Quad MAC status word indicates a raw packet and the look-up engine simply retrieves the CI and Portset as part of the data stream. A bit in the Quad MAC status word indicates a raw packet and the look-up engine simply retrieves the CI and Port set from the data stream and feeds it to the AXE (Transfer Engine) through the result FIFO. The Control processor is responsible for correctly formatting the required encapsulation. As shown in Figure 2, packets coming from the ATM side are fed into the look-up engine. The look-up engine accepts an RFC-1483 encapsulated packet and determines whether to look at a MAC or NL address. The result of the look-up will have the form: Input - > PortSet Filtering is not performed in this direction. It is assumed that the all filtering is done at the ingress side. It is also assumed that the destination endstation is known to be attached to the receiving Bridge-router, so unicast packets with unknown destination addresses are dropped. Flood and broadcast packets are encapsulated in a special format which includes an explicit output PortSet. Unicast¯DA - > SinglePortSet DA on this Bridge-router Unknown¯DA - > NullPortSet DA not in the table (drop) - this situation should not occur. Unicast¯NLDA - > SinglePortSet NLDA on this Bridge-router Unknown¯NLDA - > NullPortSet NLDA not in the table (drop) - this situation should not occur. Broadcast¯DA,PortSet - > PortSet Proprietary Broadcast request received from RS Multicast¯DA,PortSet - > Portset Proprietary Multicast request received from RS Unknown¯DA,PortSet - > PortSet Proprietary Flood request received from RS Turning now to Figure 3, the look-up engine consists of three functional blocks, namely a destination address look-up engine (DALE) 1, a source address look-up engine (SALE) 2, and a look-up engine controller (LEC) 3, which includes a microcode ram 4. DALE 1 includes a destination address look-up controller 5 and DALE RAM 6. SALE 2 includes a source address look-up controller 7 and SALE RAM 8. The input to the look-up engine is through a fast 16-bit wide I/F RAM 9 receiving input from the AXE (Transfer Engine) and re-assembler. The output from the look-up engine is through word-wide FIFOs 11, 12. One embodiment of look-up engine controller (LEC) 3 is shown in more detail in Figure 4. This comprises (Station Information Block) SIB ram 20, interface ram 21, and microcode ram 22. The SIB ram 20 is connected to look-up pointers 23. Interface ram 21 is connected to data register 25 and index pointers 26 connected to ALU (Arithmetic Logic Unit) 27. Microcode ram 22 is connected to instruction register 28. The look-up Engine controller 3 is a microcoded engine tailored for efficient bit pattern comparisons through a packet. It communicates with the Source Address Look-up Engine 2 and the Destination Address Look-up Engine 1, which both act as co-processors to the LEC 3. The look-up engine snoops on the receive and transmit data buses and deposits the header portion of the packet into the I/F RAM 9. The look-up response is sent to the appropriate FIFO 11, 12. Figures 5 show an alternative embodiment of the loop-up engine and controller. In Figure 5, the LEC 3 includes a 64 x 16 I/F (Interface) ram 41 connected to FIFO's 42, 43 (First-in, First-out memories) respectively connected to latches 44, 45 receiving AXE (Transfer Engine) and reassembler input. Referring now to Figure 6, the LEC 3 also contains several registers, which will now be described. Register select instructions are provided for the register banks (XP0-7, LP0-7). Index Pointer register (IP) 50 is a byte index into the I/F RAM 21. Under normal operation, the index pointer register 50 points to the current packet field being examined in the I/F RAM 21 but it can be used whenever random access to the I/F RAM 21 is required. The IP 50 can be modified in one of the following ways: 1) loaded by the LOADIP instruction (eg. to point to the beginning of the packet) 2) incremented by 1 (byte compare) or 2 (word compare) if a branch condition is not met. 3) incremented by 2 by a MOVE (IP)+ type instruction. Data Register 51 contains the 16 bit value read from I/F RAM 21 using the current IP. The DR 51 acts like a one word cache; the LEC keeps its contents valid at all times. Program Counter 52 points to the current microcode instruction. It is incremented by one if a branch condition is true, otherwise the displacement field is added to it. The Lookup Pointers (LPO-7) 23 are 16 bit registers which contain pointers to the SIB RAM 20. The LPs are used to store pointers whenever milestones are reached in a search. One LP will typically point to a source SIB and another will point to a destination SIB. The LP provides the upper 16 bits of the pointer; the lower 4 bits are provided by the microcode word for indexing into a given SIB. The LPs are also used to prime the SALE and DALE with their respective root pointers. X,Y Registers 53, 54 are general purpose registers where logic manipulations can be made (AND, OR, XOR). They are used for setting and clearing bits in certain words in the SIB RAM (eg. Age bit) and to test for certain bits (eg. status bits). The X Register 53 can be selected as Operand A to the Logic Unit while the Y Register can be selected as Operand B. The BYZ and BYNZ instructions conditionally branch on Y=0 and Y < > 0 respectively. The Y Register 54 is the only register source for moves to the result FIFOs. The X Register 53 can be saved to or restored from X' Registers (X'O-X'7) 55. The mnemonic symbol for the currently selected X' register is XP. The S Register 56 is a pipelining stage between SIB RAM 20 and the Logic Unit. It simplifies read access from SIB RAM 20 by relaxing propagation delay requirements from SIB RAM 20 valid to register setup. It provides the added advantage of essentially caching the most recent SIB RAM access for repeated use. It is loaded by the GET Index(LP) instruction. As in Figure 3, the LEC 3 controls the operation of the look-up engine. All look-up requests pass through the LEC 3, which in turn activates the SALE 2 and the DALE 5 as required. The LEC 3 is microcode based, running from a 32-bit wide microcode RAM. The instruction set consists mainly of compare-and-branch instructions, which can be used to find specific bit patterns or to check for valid ranges in packet fields. Special I/O instructions give the LEC random read access to the interface RAM. The LEC has access to 3 memory systems: the interface RAM 9, the SIB RAM 20 and the Microcode RAM 22. The interface RAM 9 is used to feed packet data into the LEC 3. The look-up engine hosts dump packet headers into this RAM through snoop FIFOs 42, 43. This RAM is only accessible through the snooped buses. The SIB RAM 20 is used to hold information for each known end-station. The LEC 3 can arbitrarily retrieve data from this RAM and transfer it to one of the response FIFOs 11, 12 or to internal registers for manipulation and checking. High speed RAM is also used to minimize the data retrieval time. The size of the SIB RAM 20 is dependent on the maximum number of reachable endstations. For a limit of 8,000 end-stations, the SIB RAM size is 256K bytes. This RAM is accessible directly to the Control Processor for updates. The Microcode RAM 22 is dedicated to the LEC 3. It contains the 32 bit microcode instructions. The LEC 3 has read-only access to this high speed RAM normally, but it is mapped directly to the Control Processor's memory space at startup for microcode downloading. Variable fields of a packet, such as addresses, are searched in one of many search trees in the ALEs 1, 2, (Figure 5), which are nibble index machines. Each ALE 1, 2 has its own search tree RAM 6, 8 (Figure 7), which is typically high density but low speed. This RAM is divided into 32 byte blocks which can either be Index Arrays or Information Blocks. The searches in the ALEs 1, 2 are based strictly on the root pointer, the search key and search key length it is given. A look at the look-up engine memory map (Figure 7) as viewed from the ALEs shows how the mechanism works. All search trees in a given ALE 6, 8 reside in the upper half of its memory. The 16-bit root pointer given to the ALE will have the most significant bit set. The search key (eg. MAC address) is divided into nibbles. The first nibble is concatenated with the root pointer to get an index into the root pointer array. The word at this location is retrieved. If the MSB (Most Significant Bit) (P Bit) is set, the next nibble is concatenated with the retrieved word to form the next pointer. If the P Bit is clear, the search is finished. The final result is given to the LEC, which uses it either as a pointer into the SIB RAM, or as data, depending on the context of the search. A zero value is reserved as a null pointer value. Figure 8 illustrates search tree operation. The search key length limits the number of iterations to a known maximum. The control processor manipulating the search tree structure may choose to shorten the search by putting data with a zero P bit at any point in the tree. "Don't Care" fields are also achievable by duplicating appropriate pointers within the same pointer array. Search trees are maintained by the Control Processor, which has direct access to the SALE and DALE RAMs 6, 8. Figure 9 is a diagram illustrating a MAC search tree example. The main purpose of the ALE RAMs 6, 8 is to hold MAC layer addresses. The size of the RAM required for a MAC address tree depends on the statistical distribution of the addresses. The absolute worst case is given by the following formula: EMI21.1 where X is the number of addresses L is the number of nibbles in the address N is the number of pointer arrays The amount of memory required, given 32-byte pointer arrays, is 32N. The number obtained from this formula can be quite huge, especially for MAC addresses, but some rationalizations can be made. In the case of MAC addresses, the first 6 nibbles of the address is the Organizationally Unique Identifier (OUI), which is common to Ethernet cards from the same manufacturer. It can be assumed that a particular system will only have a small number of different OUIs. The formula for MACs then becomes: EMI22.1 where M is the number of different OUIs Xj is the number of stations in OUIj Assuming that the addresses are distributed evenly over all OUIs, EMI22.2 The effect of OUI on Search Tree Size is shown in Figure 10. Similar rationalizations can be made with IP and other network layer protocol addresses. An IP network will not have very many subnets and even fewer network numbers. Although the SALE 2 typically holds locally attached source MAC addresses and the DALE 1 typically holds destination MAC addresses, either ALE 1, 2 is capable of holding any arbitrary search tree. Network layer addresses, intra-area filters, and user-defined MAC protocol types can all be stored in search trees. The decision to put a search tree in either SALE or DALE is implementation dependent; it relies on what searches can be done in parallel for maximum speed. The principal function of the SALE 2 is to keep track of the MAC addresses of all stations that are locally attached to the bridge-router. Typically one station will be attached to a bridge-router port, but connections to traditional hubs, repeaters and bridgerouters are allowed, so more source addresses will be encountered. Using the formula for RAM size above, typical RAM calculations for the source address trees are as follows: Number of OUIs Number of Total Bytes Stations 20 400 65,440 2 500 65,184 20 500 77,984 20 800 116,284 5 1,000 131,552 The number of source stations is limited to some fraction of the total allowable stations. The limit is imposed here because the SALE will most likely hold many of the other search trees (eg. per protocol NL address search trees, intra-area filters). Whenever a new source address is encountered, the SALE 1 will not find it in the MAC source address search tree. The LEC 3 realizes the fact and sends it to the Control Processor. The new source address is inserted into the search tree once validation is received from the Route Server. Whenever a previously learned address is reencountered, the Age entry in the SIB 20 is refreshed by the LEC 3. The control processor clears the Age entry of all source addresses every aging period. The entry is removed when the age limit is exceeded. The source address look-up engine table is shown in Figure 11. The DALE 1 keeps track of all stations that are directly reachable from the bridge-router, including those that are locally attached. The DALE search trees are considerably larger because they contain MAC addresses of up to 8,000 stations. Typical memory sizes for MAC destination address search trees would be: Number of Number of Total Bytes OUIs Stations 10 8,000 856,992 20 8,000 945,824 30 8,000 1,034,464 A station's MAC address will appear in the MAC search tree if the station is reachable through MAC bridging. A station's network layer address will appear in the corresponding network layer search tree if it is reachable through routing. The destination address look-up engine MAC table is shown in Figure 12. IP masking may be required if a particular port is known to have a router attached to it. Masking is achieved by configuring the IP network layer search tree in such a way that the node portion of the address is treated as Don't Care bits and the corresponding pointers point to the same Next Index Array. The SALE and DALE RAMs 8, 6 are divided up into 16 word blocks. These RAMs are accessible only to the corresponding ALE and the Control Processor. These RAMs contain mostly pointer arrays organized in several search trees. The SIB RAM 20 is divided into 16 word blocks which can be treated as records with 16 fields. Each block typically contains information about an endstation. This RAM is accessible only to the LEC and the CP. The LEC 3 uses the lookup pointer (LP) as a base pointer into a SIB 20. The contents of the LP is obtained either from the result of a SALE 2 or DALE 1 search to access end-station information, or from a constant loaded in by the microcode to access miscellaneous information (eg. port information). The LP provides the upper sixteen bits and the microcode word provides the lowest four bits of the SIB RAM address. The lookup Engine addressing scheme is shown in Figure 13. The SIB RAM 20 (Figure 14) generally contains information about the location of an endstation and how to reach it. For example, the PortSet field may keep track of the port that the endstation is attached to (if it is locally attached) and the connection index refers to a VPI/VCI pipe to the endstation (if it is remotely attached). Other fields are freely definable for other things such as protocol filters, source and destination encapsulation types and quality-of-service parameters, as the need arises. A variant of the SIB is the Port Information Block (PIB) (Figure 15). PIBs contain information about a particular port. Certain protocols have attributes attached to the port itself, rather than the endstations. An endstation inherits the characteristics assigned to the port to which it is attached. The definition of the SIB is flexible; the only requirement is that the data be easily digestible by the LUE instruction set. The field type can be a single bit, a nibble, a byte, or a whole word. In Figure 14, the CI (Connection Identifier) field is a reference to an ATM connection to the endstation if it is remotely attached. This field is zero for a locally attached endstation. The PortSet field is used both for determining the destination port of a locally attached endstation, and for determining whether a source endstation has moved. In one Newbridge-router Networks system, a moved endstation must go through a readmission procedure to preserve the integrity of the network. This field is zero for a remotely attached endstation. The MAC Index is a reference to the 6-byte MAC layer address of the endstation. This field is used for network layer forwarded packets, which have the MAC layer encapsulation removed. The MAC layer address is reattached when a packet is re-encapsulated before retransmission out an Ethernet port. The encapsulation flags determine the MAC re-encapsulation format. The Proto Area and Proto Dest Area fields are used for filtering operations. Because the Newbridge-router system essentially removes the traditional physical constraints on a network topology, the area concept logically re-imposes the constraints to allow existing protocols to function properly. Filtering rules defined between areas determine whether two endstations are logically allowed to communicate with each other using a specific protocol. The Proto Area field is a pointer to a filtering rule tree, which is similar in structure to the address trees. The Dest Area field is a search key into the tree. The result of the search is a bitfield in which each protocol is assigned one bit. Communications is allowed if the corresponding bit is set. Figure 16 shows a filtering rule tree. The microcode for the LEC 3 will now be described. The LEC microcode is divided into four main fields as shown in the table below. The usage of each field is dependent on the instruction group. EMI27.1 <tb> 31-29 <SEP> 28-24 <SEP> 1 <SEP> 23-16 <SEP> 1 <SEP> 15-0 <tb> Inst <SEP> Instruction <SEP> Displacement <SEP> Parameter <tb> Group <tb> The instruction group field consists of instructions grouped according to similarity of function. A maximum of eight instruction groups can be defined. The Instruction field definition is dependent on Instruction Group. In branch instructions, the Displacement field is added to the PC if the branch condition is true. This field is used by non-branch instructions for other purposes. The Parameter field is a 16 bit value used for comparison, as an operand, or as an index, dependent on the instruction.= The functions of the groups are set out in the following table. EMI28.1 <tb> Group <SEP> o <SEP> Index <SEP> Pointer/Bank <SEP> Select <tb> <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> manipulate <SEP> the <tb> <SEP> IP <SEP> and <SEP> the <SEP> register <SEP> bank <SEP> select <tb> <SEP> register. <tb> Group <SEP> 1 <SEP> Fast <SEP> Move <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> move <SEP> data <tb> <SEP> between <SEP> I/F <SEP> RAM <SEP> and <SEP> internal <tb> <SEP> registers. <tb> Group <SEP> 2 <SEP> Conditional <SEP> Branch <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> branch <SEP> when <SEP> a <tb> <SEP> given <SEP> condition <SEP> is <SEP> met. <SEP> They <SEP> can <tb> <SEP> optionally <SEP> increment <SEP> the <SEP> IP. <tb> Group <SEP> 3 <SEP> X <SEP> Register <SEP> Branch <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> branch <SEP> on <SEP> an <SEP> X <tb> <SEP> Register <SEP> logic <SEP> comparison. <tb> Group <SEP> 4 <SEP> Not <SEP> Used <tb> Group <SEP> 5 <SEP> Slow <SEP> Move <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> generally <tb> <SEP> involve <SEP> the <SEP> SIB <SEP> RAM <SEP> bus. <SEP> The <tb> <SEP> access <SEP> time <SEP> to <SEP> the <SEP> SIB <SEP> RAM <SEP> is <tb> <SEP> longer <SEP> because <SEP> of <SEP> address <SEP> setup <tb> <SEP> time <SEP> considerations <SEP> and <SEP> because <tb> <SEP> the <SEP> CP <SEP> may <SEP> be <SEP> accessing <SEP> it <SEP> at <SEP> the <tb> <SEP> same <SEP> time. <SEP> Access <SEP> to <SEP> the <SEP> Result <tb> <SEP> FIFOs <SEP> are <SEP> included <SEP> here. <tb> Group <SEP> 6 <SEP> Not <SEP> Used <tb> Group <SEP> 7 <SEP> Misc <SEP> Instructions <tb> <SEP> These <SEP> instructions <SEP> invoke <SEP> special <tb> <SEP> functions. <tb> The following table describes the use of each of the fields. EMI29.1 <tb> Grp <SEP> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> <SEP> 18 <tb> <SEP> 16* <tb> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Oper. <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> or <tb> <SEP> Register <SEP> Select <SEP> (15-4) <tb> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> Dest. <SEP> Size <SEP> LSel <SEP> ASel <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> Register <SEP> Select <SEP> (15-4) <tb> <SEP> or <SEP> Index <SEP> (3-0) <tb> 2 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> Cond. <SEP> Size <SEP> Disp. <SEP> (8) <SEP> Comparand <tb> 3 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> Cond. <SEP> 0 <SEP> 0 <SEP> LSel <SEP> Disp <SEP> (5) <SEP> Comparand <tb> 4 <SEP> 100 <SEP> <tb> 5 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> Dest. <SEP> Size <SEP> LSel <SEP> ASel <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> Register <SEP> Select <SEP> (15-4) <tb> <SEP> or <SEP> Index <SEP> (3-0) <tb> 6 <SEP> 110 <tb> 7 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Size <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> codes <tb> <SEP> when <SEP> LSel <SEP> = <SEP> 110 <tb> Condition 000 - (IP) = Comparand 001 - (IP) < Comparand 010 - (IP) > Comparand 011 - True 100 - Extended Condition = True 101 - Extended Condition = False 110 - Y = 0 111 - Y < > 0 Dest - Destination 000 - currently active FIFO 001 - X Register 010 - Lookup Engine Address RAM 011 - Group 5: S Register otherwise: None 100 - Y Register 101 - Index(LP) (SIB RAM) 110 - XP Register 111 - Lookup Pointer Operation - IP/Register Select operation 00 - Register Select 10 - Load Size - IP increment size 00 - no increment 01 - byte (+1) 10 - word (+2) Displacement (8 bits) 00000001 - next instruction 00000000 - same instruction Displacement (5 bits) 00001 - next instruction 00000 - same instruction LSel - Logic Unit Select 000 - A AND B 001 - A OR B 010 - A AND NOT B 011 - A OR NOT B 100 - A XOR B 101 - Reserved 110 - B 111 - A ASel - Operand A Select 000 - (iP) , (iP)+ Indirect I/F Data 001 - X X Register 010 - S S Register 011 - XP X' Register 100 - XP X' Register 101 110 111 BSel - Operand B Select 00 - Y Y Register 01 - &num; ;Value Immediate Value 11 - Special Function When LSel = 110: 010 - DALE Lookup Result 110 - SALE Lookup Result Immediate Value Word values fill the whole field Byte values must be repeated twice to fill the field When BSel = 11 (Special Functions): Value Function Mnemonic $0000 X rotate left 4 L4(X),R12(X) $1000 X rotate 8 (byte swap) SWAP(X),L8(X),R8(X) $2000 X rotate right 4 R4(X),L12(X) $3000 portset(X) PSET(X) $4000 X rotate left 1 L1(X) $5000 X rotate right 1 R1(X) $6000 flip X FLIP(X) $7000 LUE Version number VER When Value = $3000 (Portset Function): X(11:8) f(15: :0) 0 0000000000000001 1 0000000000000010 2 0000000000000100 3 0000000000001000 4 0000000000010000 5 0000000000100000 6 0000000001000000 7 0000000010000000 8 0000000100000000 9 0000001000000000 10 0000010000000000 11 0000100000000000 12 0001000000000000 13 0010000000000000 14 0100000000000000 15 1000000000000000 FIFO Write Instructions EMI31.1 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> <SEP> 15-0 <SEP> <tb> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> Extra <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> Extra/BSel Oee 01 MOVEF &num; ;Value,Extra Move Immediate Value to FIFO with Extra bits Oee 00 MOVEF Y,Extra Move Y Register to FIFO with Extra bits lee 00 MOVEF Index(LP),Extra Move Indexed Lookup Data to FIFO with Extra bits The FIFO write instructions are used to write data into the currently active result FIFO. The Extra field control bits 16 and 17 in the FIFO data bus. The third instruction in the list is a direct memory access from SIB RAM to the active FIFO. SIB RAM is enabled while the active FIFO is sent a write pulse. Doing so avoids having SIB data propagate through the LUE. Bit 20 differentiates between a DMA and a non-DMA instruction. The X register cannot be used as a MOVEF source because what would normally be the ASel field conflicts with the Extra field. Usage: MOVEF #IPSnap,0 ; Packet is IP over SNAP Interface RAM Data Read Instructions EMI32.1 <tb> 131-29 <SEP> 128-26 <SEP> 125-24 <SEP> 123-21 <SEP> 120-18 <SEP> 117-16 <SEP> 115-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> Dest <SEP> Size <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Unused <tb> Dest/Size 001 00 MOVE (IP),X Move IP indirect to X Register 001 10 MOVE (IP)+,X Move IP indirect autoinc to X Register 100 00 MOVE (IP),Y Move IP indirect to Y Register 100 10 MOVE (IP)+,Y Move <RTI ID=32.15> IP indirect auto inc to Y Register 111 00 MOVE (IP),LP Move IP indirect to LP Register 111 10 MOVE (IP)+,LP Move IP indirect auto inc to LP Register Interface RAM Data Read instructions are used to read data from the Interface RAM 41 into the X, Y or LP Register. The LP used is preselected using the RSEL instruction. Lookup Pointer Instructions EMI32.2 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> Group <SEP> Dest <SEP> O <SEP> O <SEP> LSel <SEP> ASel <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> or <SEP> Reg <SEP> Sel <SEP> (15-4) <tb> <SEP> Extra <SEP> or <SEP> Index <SEP> (3-0) <tb> Group/Dest/LSel/ASel/BSel - Instruction Type 101 101 111 001 00 MOVE X,Index(LP) Move X Register to Indexed Lookup Data 101 101 110 000 00 MOVE Y,Index(LP) Move X Register to Indexed Lookup Data 101 011 000 000 00 GET Index(LP) Load S Register with Indexed Lookup Data 001 111 110 000 00 MOVE Y,LP Move X Register to Lookup Pointer 001 111 110 000 01 MOVE &num; ;Value,LP Move Immediate Value to Lookup Pointer 001 111 111 001 00 MOVE X,LP Move X Register to Lookup Pointer Lookup Pointer instructions are used to load the Lookup Pointers or to store and retrieve values in Lookup RAM. Usage: MOVE Age(LP),X ; Get Age field ; check age ... ; reset age MOVE X,Age(LP) input put it back in Logic Instructions EMI33.1 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> Dest <SEP> 0 <SEP> 0 <SEP> LSel <SEP> ASel <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> or <SEP> Index <SEP> (3-0) <tb> Logic instructions are used to perform logic manipulations on the X and Y Registers. Combinations of the selections above yield the following (useful) instructions: Dest/LSel/ASel/BSel 001 110 000 00 MOVE Y,X Y - > X 100 111 001 00 MOVE X,Y X - > Y 001 111 010 00 MOVE S,X S - > X 100 111 010 00 MOVE S,Y S - > Y 001 110 000 01 MOVE &num;Value,X Immediate Value - > X 100 110 000 01 MOVE &num;Value,Y Immediate Value - > Y 001 000 001 00 AND X,Y,X X AND Y - > X 001 000 010 00 AND S,Y,X S AND Y - > X 001 000 001 01 AND X,&num;Value,X X AND Value - > X 001 000 010 01 AND S,&num;Value,X S AND Value - > X 100 000 001 00 AND X,Y,Y X AND Y - > Y 100 000 010 00 AND S,Y,Y S AND Y - > Y 100 000 001 01 AND X,&num;Value,Y X AND Value - > Y 100 000 010 01 AND S,&num;Value,Y S AND Value - > Y OR, ANDN, ORN and XOR are similar to AND: dst 001 aaa bb OR aaa,bb,dst aaa OR bb - > dst dst 010 aaa bb ANDN aaa,bb,dst aaa OR bb - > dst dst 011 aaa bb ORN aaa,bb,dst aaa OR bb - > dst dst 100 aaa bb XOR aaa,bb,dst aaa OR bb - > dst Conditional Branch Instructions EMI34.1 <tb> 31-29 <SEP> 128-26 <SEP> 25-24 <SEP> 123-16 <SEP> 15-0 <SEP> <tb> 0 <SEP> 1 <SEP> 0 <SEP> Cond. <SEP> Size <SEP> Displacement <SEP> I <SEP> comparand <SEP> <tb> Cond/Size 000 01 ESCNE.b &num;Comparand,Label Escape if Byte Not Equal 000 10 ESCNE.w &num;Comparand,Label Escape if Word Not Equal 001 01 ESCGE.b &num;Comparand,Label Escape if Byte Greater or Equal 001 10 ESCGE.w &num;Comparand,Label Escape if Word Greater or Equal 010 01 ESCLE.b #Comparand,Label Escape if Byte Less or Equal 010 10 ESCLE.w &num;Comparand,Label Escape if Word Less or Equal 110 00 BYZ Label Branch if Y Register is zero 111 00 BYNZ Label Branch if Y Register is not zero Increment Branch instructions are used to compare the current packet field with an immediate value. If the condition is met, the branch is taken; otherwise IP is incremented by the Increment Size. Usage: Labell: check check if SNAP header ESCNE.w #$AAAA,Label2 ; compare to SNAP value ESCNE.w & um;S0003,OtherLabel Label2: X Register Branch Instructions EMI35.1 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-16 <SEP> 15-0 <SEP> <tb> 0 <SEP> 1 <SEP> 1 <SEP> Cond <SEP> 0 <SEP> 0 <SEP> LSel <SEP> Disp <SEP> Value <tb> Cond/LSel 110 100 BXEQ &num;Value,Label Branch if X is equal to value 111 100 BXNE &num;Value,Label Branch if X is not equal to value 110 000 ANDBZ &num;Value,Label Branch if X AND Value is equal to zero 111 000 ANDBNZ &num;Value,Label Branch if X AND Value is not equal to zero 110 010 ANDNBZ &num;Value,Label Branch if X AND NOT Value is equal to zero 111 010 ANDNBNZ &num; ;Value,Label Branch if X AND NOT Value is not equal to zero X Register Branch instructions are derived from the X Register Logic instructions with Operand A always set to the X Register and Operand B always set to the Immediate value. The X Register is not affected by any of these instructions. The displacement field is reduced to 5 bits (+/- 32 instructions) Usage: See Destination Lookup Instruction example SKIP.w ; ignore the next word field Other Branch Instructions EMI36.1 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-16 <SEP> 15-4 <SEP> 3-0 <tb> 0 <SEP> 1 <SEP> 0 <SEP> Cond <SEP> Size <SEP> Disp <SEP> ExtCond <SEP> ExtDisp <tb> Cond/Size/Disp/ExtCond/ExtDisp 100 00 $00 $000 0 DWAIT Wait for DALE 100 00 $00 $800 0 SWAIT Wait for SALE 101 00 $00 $C00 0 FWAIT Wait for Snoop FIFO done 101 00 ddd $400 0 BCSERR ddd Branch on checksum error 011 01 $01 $000 0 SKIP.b Skip Byte (same as IBRA.b +1) 011 10 $01 $000 0 SKIP.w Skip Word (same as IBRA.w +1) 011 01 ddd $000 d IBRA.b Label Increment Byte and Branch Always 011 10 ddd $000 d IBRA.w Label Increment Word and Branch Always 011 00 000 $800 0 SWITCH Switch on X (add X to PC) 011 00 ddd $000 d BRA.u Label Branch Always These instructions are derived from the conditional branch instructions. Wait instructions loop until the extended condition is false. Skip instructions move to the next instruction and increment the IP appropriately. More branch instructions can be defined easily by using Cond=100 or 101 and picking an unused ExtCond pattern. When Cond = 011 (True), the displacement field is extended to 12 bits. The SWITCH instruction adds the least significant nibble of X to the PC. If X(3:0) = 0, 16 is added to the PC. Usage: SKIP.w ; ignore the next word field Index Pointer/Register Select Instructions EMI37.1 <tb> 31-29 <SEP> 128-26 <SEP> 125-24 <SEP> 23-21 <SEP> 20-18 <SEP> 117-16 <SEP> 115-0 <SEP> <tb> Group <SEP> Dest <SEP> Oper <SEP> LSel <SEP> ASel <SEP> BSel <SEP> Immediate <SEP> Value <SEP> (15-0) <tb> <SEP> or <tb> <SEP> Register <SEP> Select <SEP> (15-4) <tb> Group/Dest/Oper/LSel/ASel/BSel 001 110 00 111 000 00 ST X[,XPn,LPn] X - > XP, optionally switch to XPn,LPn 001 001 00 111 100 00 LD X[,XPn,LPn] XP - > X, optionally switch to XPn,LPn 001 011 00 111 000 00 RSEL XPn,LPn switch to XPn,LPn 000 011 10 110 000 01 LOADIP &num; ;Value Load IP immediate 000 011 10 111 001 00 LOADIP X Load IP with X Index Pointer instructions are used to perform manipulations on the index pointer. Transfers from the X registers are not normally used in a lookup function but may be useful for general purpose transfers from interface RAM. The Register Select instruct ion selects a register from each of the register banks. The format of the Bank Select Bits field is: EMI38.1 <tb> 15-12 <SEP> 1 <SEP> 11 <SEP> 1 <SEP> 10-8 <SEP> 7 <SEP> 16-4 <SEP> 3-0 <SEP> <tb> X <SEP> X <SEP> X <SEP> X <SEP> xEn <SEP> XSel <SEP> LPEn <SEP> LPSel <SEP> X <SEP> X <SEP> X <SEP> X <SEP> <tb> The En bits determine whether the corresponding select bits are valid. If En is zero, the corresponding register selection remains unchanged. If En is one, the corresponding select bits are used. This mechanism allows register selections to be made independent of each other. Destination Lookup Instructions EMI38.2 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 115-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> Size <SEP> 1 <SEP> 1 <SEP> 1 <SEP> ASel <SEP> O <SEP> O <SEP> Command/Address <SEP> <tb> Size/ASel 00 001 DLOAD X,Address [,Command] Load X into DALE 00 000 DLOAD (IP),Address [,Command] Load IP indirect into DALE / load Command Reg 10 000 DLOAD (IP)+,Address [,Command] Load IP indirect autoinc into DALE / load Command Reg EMI38.3 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> Dest <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> not <SEP> used <tb> Dest 111 DMOVE LP Move DALE result pointer into Lookup Pointer 001 DMOVE X Move DALE result pointer into X Register 100 DMOVE Y Move DALE result pointer into Y Register The destination lookup instructions set up the DALE and read results from it. The currently selected lookup pointer is used as the root pointer. The DLOAD instruction loads words into the 16 by 16 bit DALE Nibble RAM and loads the Command Register. The DMOVE instruction returns the DALE result. Command Register EMI39.1 <tb> 15 <SEP> 14 <SEP> 13-12 <SEP> 11-4 <SEP> 3-0 <SEP> <tb> Start <SEP> 0 <SEP> Nibble <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Address <tb> <SEP> Offset <tb> The Start bit signals the DALE to start the lookup. The Nibble Offset field points to the first valid nibble in the first word loaded into the Address RAM. The Address field points to the word being written in Nibble RAM. The DMOVE instruction gets the 16 bit DALE result pointer. DMOVE should be preceded by DWAIT, otherwise the result may be invalid. Usage: LOADIP #StartOfPacket ; point to start of packet DLOAD (IP)+,Wordl load load DA word 1 DLOAD (IP)+,Word2 load load DA word 2 DLOAD (IP)+,Word3,Start load load DA word 3 and start lookup ... ; do other stuff DMOVE X get get result BXNE & um;Null,DAFound ; address found in table Source Lookup Instructions EMI39.2 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> Size <SEP> 1 <SEP> 1 <SEP> 1 <SEP> ASel <SEP> O <SEP> 1 <SEP> Command/Address <tb> Size/ASel 00 001 SLOAD X,Address [,Command] Load X into SALE 00 000 SLOAD (IP),Address [,Command] Load IP indirect into SALE / load Command Word 10 000 SLOAD (IP)+,Address [,Command] Load IP indirect auto inc into SALE / load Command Word EMI40.1 <tb> 31-29 <SEP> 28-26 <SEP> 25-24 <SEP> 23-21 <SEP> 20-18 <SEP> 17-16 <SEP> 15-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> Dest <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> immediate <SEP> Value <SEP> (15-0) <tb> Dest 111 SMOVE LP Move SALE result pointer into Lookup Pointer 001 SMOVE X Move SALE result pointer into X Register 100 SMOVE Y Move SALE result pointer into Y Register The destination lookup instructions set up the SALE and read results from it. The currently selected lookup pointer is used as the root pointer. The SLOAD instruction loads words into the 16 by 16 bit SALE Nibble RAM and loads the Command Word. The SMOVE instruction returns the SALE result. Command Word EMI40.2 <tb> 15 <SEP> 14 <SEP> 13-12 <SEP> 11-4 <SEP> 3-0 <tb> Start <SEP> O <SEP> Nibble <SEP> O <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Address <tb> <SEP> Offset <tb> The Start bit signals the SALE to start the lookup. The Nibble Offset field points to the first valid nibble in the first word loaded into the Address RAM. The Address field points to the word being written in Address RAM. The SMOVE instruction gets the 16 bit SALE result pointer. The SMOVE instruction should be preceded by SWAIT, otherwise the result may be invalid. Usage: SLOAD (IP)+,Wordl load load DA word 1 SLOAD (IP)+,Word2 load load DA word 2 SLOAD (IP)+,Word3,Start load DA word 3 and start lookup ... ; do other stuff SWAIT ; wait for SALE to finish SMOVE X ; get result BXNE &num;Null,SAFound ; address found in table Checksum Engine Instructions EMI41.1 <tb> 31-29 <SEP> 28-26 <SEP> 1 <SEP> 25-24 <SEP> 23-21 <SEP> 1 <SEP> 20-18 <SEP> 17-16 <SEP> 1 <SEP> 15-0 <tb> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> Size <SEP> 1 <SEP> 1 <SEP> 1 <SEP> ASel <SEP> 1 <SEP> 0 <SEP> $8000 <tb> Size/ASel 00 001 CLOAD X Load X into Checksum Engine and start 00 000 CLOAD (IP) Load IP indirect into Checksum Engine and start 10 000 CLOAD (IP)+ Load IP indirect auto inc into Checksum Engine and start The CLOAD instruction loads a word count into the checksum engine, clears the checksum and starts the engine. The word currently indexed by IP is subsequently added to the checksum each time the IP crosses a word boundary until the count is exhausted. Miscellaneous Instructions EMI41.2 <tb> 131-29 <SEP> 128-16 <SEP> 115-0 <tb> <SEP> 111 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> Code <SEP> (2-0) <tb> These instructions invoke special functions Code 001 STOP Stop execution until next lookup request The lookup engine operation will now be described in more detail. The instruction State Machine (ISM) is shown in Figure 17. A lookup engine microcode will typically take four clock cycles. At 50 MHz, the instruction cycle takes 80 ns to execute. Instructions that require access to SIB RAM, which require arbitration with the Control Processor, and any future extensions that require more time to execute will require one or more additional cycles to complete. After reset, the 3 LEC is in the idle state. soon as one of the snoop FIFOs 42, 43 is non-empty, the ISM enters the main instruction cycle loop. A microcode instruction cycle is typically divided into four main states. State 3 and State 0 allow the microcode contents to propagate through the LEC. The instruction group is determined in State 1. If a fast instruction is being executed (Groups 0-3), State 2 is entered immediately. Otherwise the appropriate next state is entered according to the Group field. Figure 18 shows a typical fast instruction. By the time State 2 is reached, all signals will have settled. New values for the PC and if necessary, the IP and/or the selected destination, are loaded at the end of this state. State 42 is a dummy state for currently undefined groups. State 52 is a wait state for external accesses to SIB RAM. The ISM exits this state when the SIB RAM has been granted to the LEC long enough for an access to complete. Figure 19 shows a typical SIB RAM access instruction. States 72 and 73 are executed during the STOP instruction. State 73 flushes the snoop FIFOs in case The LEC cycles through States 0 to 3 indefinitely until a STOP instruction is encountered, which brings the LEC back to the idle state. The lookup request mechanism for a MAC layer lookup is as follows: The requestor (eg. the AXE) places information, generally a packet header, into the snoop FIFO. The empty flag of the FIFO kickstarts the LEC. The LEC instructs the DALE to look up the destination address. The LEC instructs the SALE to look up the source address. The LEC looks into the packet to determine the network layer protocol in case it needs to be forwarded. The LEC waits for the SALE and reads the Source Address SIB pointer. The source port is compared against the previously stored portset to see if the source endstation has moved The LEC waits for the DALE and reads the Destination Address SIB pointer. The destination area is compared to the source area to see if the endstations are in the same area The source port is compared against the destination port to see if the endstations are on the same port. Packets are discarded if they serve no other useful purpose (eg. SA and DA on the same port or in different areas, errored packets). Otherwise they are sent to the Control Processor for further processing. Sample Program File: BDG.a Unicast Bridging Case Release 1.1 Functionality BDG¯Start: ;XO = Packet Status Word ;IP = Points to 2nd byte of PSW ;DR = Contains Packet Status Word ;xO, LP0 are default XP, LP MOVE $8000,LP ;Look up Destination MAC DLOAD (IP)+,0 ; Load Dst Addr bits 0-15 DLOAD (IP)+,1 ;Load Dst Addr bits 16-31 ;Load Dst Addr bits 32-47 DLOAD (IP)+,2,$8000 and start lookup MOVE $8000,LP ;Look up Source MAC SLOAD (IP)+,0 ;Load Src Addr bits 0-15 SLOAD (IP)+,1 ;Load Src Addr bits 16-31 ;Load Src Addr bits 32-47 SLOAD (IP)+,2,$8000 ; ;and start lookup determine protocol here ESCGE.w 1500,CheckEnetType ;check if 802.3 format ESCNE.w $AAAA,UnknownType ;check DSAP/SSAP ESCNE.w $0300,SNAPUnknownType ;check CTL field ESCNE.w $0000,SNAPUnknownType ESCNE.w $0800,SNAPUnknownProtocol ;check protocol type field it's IP over SNAP BdgSNAPIP: : CLOAD 5 assume IP header length is 5 ESCNE.w $4500,BdgSNAPIP withopts ;check IP header SKIP.w ;skip length SKIP.w ;skip identification SKIP.w ;skip offset ESCLE.b SO1,BdgSNAPIP TTLExpired ;check TTL SKIP.b ;skip protocol SKIP.w ;skip checksum MOVE (IP)+,X ;read NLSA MOVE R12(X),X ;shift first nibble to bottom SWITCH ;check IP Class BRA.u BdgSNAPIPClassA ;0xxx = Class A address BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassA BRA.u BdgSNAPIPClassB lOx:: : = Class B address BRA.u BdgSNAPIPClassB BRA.u BdgSNAPIPClassB BRA.u BdgSNAPIPClassB BRA.u BdgSNAPIPClassC ;110x = Class C address BRA.u BdgSNAPIPClassC BRA.u BdgSNAPIPClassD ;1110 = Class D address BRA.u BdgSNAPIPClassE ;1111 = Class E address (future) BRA.u BdgSNAPIPClassA ;0xxx = Class A address BdgSNAPIPClassA: OR X,$FF00,X ;check if broadcast BXNE SFFFF,BdgSNAPIP NLSARealign MOVE (IP)+,X ;check lower address word BXEQ $FFFF,BdgSNAPIP¯NLSAInvalid;all ones host address BRA.u BdgSNAPIP¯NLSAValid broadcast SA is not allowed BdgSNAPIP¯NLSARealign: SKIP.w BRA.u BdgSNAPIP¯NLSAValid BdgSNAPIPClassB: : MOVE (IP)+,X ;check lower address word BXNE SFFFF, BdgSNAPIP¯NLSAValiB BRA.u BdgSNAPIP¯NLSAValid BdgSNAPIPClassC: MOVE (IP)+,X ;check lower address byte OR X,$FF00,X ;check if broadcast BXEQ SFFFF,BdgSNAPIP NLSAInvalid. BRA.u BdgSNAPIP¯NLSAValid BdgSNAPIPClassD: SKIP.w BRA.u BdgSNAPIP¯NLSAValid BdgSNAPIP¯NLSAInvalid: SWAIT ;clean up after SALE and DALE DWAIT OR XP,CMD¯DISCARD | CMD¯UNICAST,Y ;Load command Word MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI ; Send CI Index MOVEF PORT¯CP Dest Port is CP MOVEF RSN¯FRC¯MAC¯SRC¯INVALID ; Send Reason STOP BdgSNAPIP NLSAValid: SKIP.w ;skip NLDA SKIP.w BCSERR BDG SNAPIP CSError RSEL LP1 Store source SIB pointer in LP1 SWAIT SMOVE Y ;Y contains SALE result MOVE Y,LP,LP2 ;LP1 points to Source Addr SIB ;Store dest SIB pointer in LP2 BYNZ BDG¯SrcHit BDG¯SrcMiss: : ;**+ Source Cache Miss *** OR XP,CMD¯FWDCP 1 CMD¯UNICAST,Y ;Load command Word ;Default MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI Send CI Index MOVEF PORTCP Dest Port is CP MOVEF RSN FRC MAC SRC MISS Send Reason STOP ;Done!!! BDG¯SNAPIP¯CSError: OR XP,CMD¯DISCARD | CMD¯UNICAST,Y ;Load command Word MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI ; Send CI Index MOVEF PORTCP Dest Port is CP MOVEF RSN¯FRC¯MAC¯CSERR ; Send Reason STOP BDG¯SrcHit: DWAIT DMOVE Y ;Get DALE result MOVE Y,LP,LP1 ;point to source SIB BYNZ BDG¯CheckSrcPort and check source port BDG¯DestMiss: ;*** Destination Cache Miss *** OR XP,CMD¯FWDCP 1 CMD¯UNICAST,Y Load command Word ;Default MAC Ethernet Type default Low priority MOVEF Y, FIRST ;Send Command Word MOVEF NULL¯CI send CI Index MOVEF PORT¯CP Dest Port is CP MOVEF RSN FRC¯MAC DST MISS;Sencl Reason STOP ;Done!!! BDG¯CheckSrcport: GET SIB¯MAC¯PORTSET(LP) Compare portsets in LP = > Src SIB AND S,PSET(X),Y ;Y = src addr bit AND src port bit BYNZ BDG¯CheckDestArea source moved if bits don't match BDG¯SrcMove: : ;** * Source Moved *** OR XP,CMD¯FWDCP | CMD¯UNICAST,Y ;Load command Word Default MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI send CI Index MOVEF PORT¯CP Dest Port is CP MOVEF RSN¯FRC¯SRC¯MOVED Send Reason STOP ;Done!!! BDG¯CheckDestArea: RSEL LP2 ;point to dest SIB GET SIB PROTO¯AREA¯1(LP) ;get IP Dest Area AND S,MASK¯AREA,Y ;Mask off top 4 bits BYNZ BDG¯CheckSrcArea BDG¯DestAreaInvalid: : ;*** Destination Area Invalid *** LD X OR X,CMD¯DISCARD I CMD¯UNICAST,Y ;Load command Word ;Default MAC Ethernet Type ;Default Low priority ;Default Multicast MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI Send CI Index MOVEF PORTCP Dest Port is CP MOVEF RSN¯DRC¯DST¯AREA¯INV send Reason STOP ;Done!!! BDG¯CheckSrcArea: RSEL LPl ;get ready for Source Addr check GET SIB¯PROTO¯AREA¯1(LP) OR S,SIB¯AREA¯PROTO¯ACTIVE,X set PA bit in SIB¯IPAREA MOVE X,SIB PROTO AREA¯1(LP) ;modify AND X,MASK¯AREA, X ;Mask off top 4 bits XOR X,Y,Y,LP2 ;check against Dest Area switch to LP2 (Dest SIB) BYZ BDG¯CheckDestPort BDG-srcAreaInvalid: : ;*** Source Area Invalid *** OR XP,CMD¯DISCARD I CMD UNICAST,Y ;Load command Word Default MAC Ethernet Type Default Low priority ;Default Multicast MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI ;Send CI Index MOVEF PORT¯CP ;Dest Port is CP MOVEF RSN DRC SRC AREA INV;Send Reason STOP ;Done!!! BDG¯CheckDestPort: - ;XO, LP2 are default XP, LP LD X ;restore PSW GET SIB¯MAC¯PORTSET(LP) ; S = dest address portset AND S, PSET(X),Y ;compare against source port portset BYZ BDG¯OK BDG¯SamePort: ;*** Src Port = Dest Port *** OR XP,CMD¯DISCARD I CMD¯UNICAST,Y Load command Word Default MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST Send Command Word MOVEF NULL¯CI ;Send CI Index MOVEF PORT¯NULL Dest Port is NULL MOVEF RSN¯DRC¯DST¯SAME Send Reason STOP ;Done!!! BDG¯OK: : ;*** Bridge-router *** OR XP,CMD¯BRIDGE-ROUTER | CMD¯UNICAST,Y ;Load command Word Default MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST ;Send Command Word MOVEF SIB¯MAC¯CI(LP) ;Send CI Index from dst SIB MOVEF SIB¯MAC¯PORTSET(LP) Dest Port is determined from dst SIB MOVEF SIB¯MAC¯MACINDEX(LP) ;Get MAC Index from dst SIB STOP ;Done!!! The described look-up engine is capable of performing bridge-router and most network layer look-ups in less than 5.6 tjs (1/178,000) with to minimum RAM requirements and cost and maximizes flexibility for future additions/corrections without hardware changes. The intended application of the look-up engine is high performance LAN systems and other packet-based devices. GLOSSARY BRIDGE-ROUTER A LAN bridging-routing device, with 12 ethernet ports and 1 ATM port. ATM Asynchronous Transfer Mode. A cell relay standard. ABS Address/Broadcast Server A component of a Route Server that handles address resolution and broadcast traffic. AXE A Transfer Engine DA Destination Address. The MAC address of the intended destination of a MAC frame. DALE Destination Address Look-up Engine. The LUE component that generally searches through a table of MAC layer destination addresses. CI Connection Identifier. A number internally used to indicate a particular connection. IP Internet Protocol A popular network layer protocol used by the Internet community. IPX Internet Packet Exchange A Novell developed network layer protocol. LEC Look-up Engine Controller. The LUE component that executes microcode. LUE Look-up Engine. MAC Medium Access Control. A term commonly encountered in IEEE 802 standards generally referring to how a particular medium (ie. Ethernet) is used. "MAC address" is commonly used to refer to the globally unique 48 bit address given to all interface cards adhering somewhat to the IEEE 802 standards. RS Route Server. SA Source Address. The MAC address of the originator of a MAC frame. SALE Source Address Look-up Engine. The LUE component that generally searches through a table of MAC layer source addresses. SIB Station Information Block. The data structure in the LUE that holds relevant information about an endstation. CAM Content Addressable Memory. VPI Virtual Path Identifier VCI Virtual Channel Identifier Control Processor The processor in the Bridge-router that handles management functions

Claims: Claims: 1. An arrangement for parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, said arrangement comprising input means for receiving fields from said packet headers of incoming packets, means for storing information related to possible values of said fields, and means for retrieving said stored information appropriate to a received field value, characterized in that said retrieving means comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and controller means for controlling the operation of said at least one memory. 2. An arrangement as claimed in claim 1, characterized in that said controller means compares, at each decision point on the tree structure, the current field with a known value or range, and moves to the next decision point by moving the current field pointer and branching to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition. 3. An arrangement as claimed in claim 1, characterized in that said tree structure is based on nibbles of said field values, and said controller means matches successive nibbles of a field in said memory to locate the related information. 4. An arrangement as claimed in claim 3, characterized in that said controller means concatenates a first nibble of an incoming field value with a root pointer to obtain an index to a root pointer array, retrieves a word at a location identified by said index, concatenates the next nibble with the next word to form the next pointer and so on until said related information is retrieved. 5. An arrangement as claimed in claim 1, characterized in that said memory is a random access memory (RAM). 6. An arrangement as claimed in claim 1, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination addresses. 7. An arrangement as claimed in claim 1, characterized in that said look-up engine further comprises a plurality of said memories operating in parallel, said memories being associated with respective fields of said packet headers. 8. An arrangement as claimed in claim 1, characterized in that each said memory is a random access memory (RAM). 9. An arrangement as claimed in claim 6, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination addresses, and another of said fields comprises a source address and said retrieving means also locates path data associated with the source address in the header of said packet in parallel with the location of the path data associated with the destination address. 10. An arrangement as claimed in claim 7, characterized in that said controller means comprises a main controller controlling overall operation of the look-up engine and memory controllers associated with each said memory. 11. An arrangement as claimed in claim 10, characterized in that said main controller is a microcode engine. 12. An arrangement as claimed in claim 10, characterized in that said microcode engine comprises an interface memory for receiving said incoming packets, a station information block memory for storing information pertaining to endstations, and a microcode memory storing microcode instructions. 13. An arrangement as claimed in claim 11, characterized in that the microcode engine parses the remainder of the packet header using a specific instruction set while said information is retrieved from said memories. 14. An arrangement as claimed in claim 13, characterized in that said microcode engine comprises separate buses for instructions and data. 15. An arrangement as claimed in claim 14, characterized in that said microcode engine further comprises means for implementing optimized instructions that perform bit level logical comparisons and conditional branches within the same cycle and other instructions tailored to retrieving data from nibble-indexed data structures. 16. An arrangement as claimed in claim 15, characterized in that said microcode engine is implemented as an ASIC processor. 17. An arrangement for parsing packets in a packet-based data transmission network, said packets including packet headers including destination and source address fields, said arrangement comprising input means for receiving fields from said packet headers of incoming packets, means for storing information related to possible values of said source and address fields, and means for retrieving said stored information, characterized in that it further comprises respective source and destination address look-up engines, a processor controlling overall operation of said source and destination address look-up engines, each said address look-up engine comprising a memory and associated memory controller, and said address look-up engines and said processor operating in parallel. 18. An arrangement as claimed in claim 17, characterized in that each said memory is based on a hierarchical tree structure. 19. An arrangement as claimed in claim 18, characterized in that said memory controllers compare, at each decision point on the tree structure, the current field with a known value or range, and move to the next decision point by moving the current field pointer and branching to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition. 20. An arrangement as claimed in claim 18 or 19, characterized in that said processor comprises a microcode engine that parses additional fields in said packet header while said address look-up engines retrieve said related information. 21. An arrangement as claimed in claim 18 or 19, characterized in that said microcode engine comprises an interface memory for receiving said incoming packets, a station information block memory for storing information pertaining to endstations, and a microcode memory storing microcode instructions. 22. A method of parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, comprising storing information related to possible values of said fields, receiving fields from said packet headers of incoming packets, and retrieving said stored information appropriate to a received field value, characterized in that said information is stored in a memory organized in a hierarchical tree structure. 23. A method as claimed in claim 22, characterized in that at each decision point on the tree structure, in retrieving said information the current field is compared with a known value or range, the current field pointer is moved and branched to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition. 24. A method as claimed in claim 22, characterized in that said tree structure is based on nibbles of said field values, and successive nibbles of a field are matched to locate the related information. 25. A method as claimed in claim 24, characterized in that a first nibble of an incoming field value is concatenated with a root pointer to obtain an index to a root pointer array, a word at a location identified by said index is retrieved, the next nibble is concatenated with the next word to form the next pointer and so on until said related information is retrieved. 26. A method as claimed in claim 22, characterized in that information related to a plurality of fields is retrieved in parallel. 27. A method as claimed in claim 26, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination address, and another of said fields comprises a source address and said related information comprises the path data associated with said source address. 28. A method as claimed in claim 27, characterized in that the remainder of the packet header is parsed using a specific instruction set while said related information is retrieved.

Inventors: BEHKI NUTAN, BURWELL WAYNE, GOBUYAN JEROME, BEHKI, NUTAN, BURWELL, WAYNE, GOBUYAN, JEROME
Applicants: BEHKI NUTAN, BURWELL WAYNE, GOBUYAN JEROME, NEWBRIDGE NETWORKS CORP, BEHKI, NUTAN, BURWELL, WAYNE, GOBUYAN, JEROME, NEWBRIDGE NETWORKS CORPORATION
Application year: 1994
Main classification: H04L12
IPC codes: G06F13, G06F17, H04L12, H04Q11