Planarization technique for an integrated circuit

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer (1) of spin-on glass is deposited, a layer of low-temperature oxide (3) is deposited before a second layer of spin-on glass (2).

Description: The present invention relates to formation and structures for interlevel dielectrics in integrated circuit fabrication. A high degree of planarization is essential in the fabrication of integrated circuits with multiple levels of interconnect. Application of spin-on glass 1 , followed by global etch-back, is widely used in the industry to achieve the desired level of surface planarity. However, spin-on glass ("SOG") and SOG etch-back technique are inadequate in a variety of situations where topologies with high aspect ratio and/or more topologies are encountered due to lack of planarization and/or SOG cracks. (Spin-on glass deposition is an example of a "sol-gel" process, which has been used in the semiconductor industry for many years. The unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally. e.g., Dauksher et al., "Three 'low Dt' options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process," 139 J.ELECTROCHEM.SOC. 532-6 (1992).) US 5,110,763 discloses the deposition of an organic glass layer over an underlying structure having regions of high and low relief. The regions of high relief are associated with underlying wiring. The organic glass layer is partially removed by overetching so that the areas of high relief of the underlying structure are exposed. The organic glass layer remains as bulks in the areas of low relief. A layer of silicon dioxide is then deposited. A layer of inorganic glass is then deposited. The inorganic glass is etched overall to expose portions of the layer of silicon dioxide. An interlevel dielectric layer is deposited. Vias are etched through the interlevel dielectric, the silicon dioxide layer and the underlying structure to the metal wiring. A metal layer is deposited to make connection to the underlying metal wiring. In most cases, successful planarization of severe topologies is achieved by a single or double SOG deposition+etchback step in the following sequence: a) a layer of dielectric is applied between the underlying surface and SOG. b) application of a layer of SOG and SOG cure; c) application of a second layer of SOG and SOG cure (optional); and d) SOG etchback. However, in extreme topologies, when the volume of SOG is very large, shrinkage of SOG during planarization and post-planarization processing leads to formation of undesirable cracks or voids. US 5,110,763 discloses a planarization process in which recesses in an underlying structure are substantially filled with spin-on glass. The precharacterising portion of the independent claims are based upon the disclosure of this document. According to one aspect of the present invention there is provided a method according to claim 1. According to another aspect of the present invention there is provided an integrated circuit according to claim 14. The proposed method seeks to alleviate the problem of SOG cracking by performing the following operations: a) conventional dielectric deposition is applied (optional); b) application of a layer of SOG and SOG cure (as in prior art); c) deposition of a layer of dielectric (e.g. TEOS/ozone deposition, or simple plasma-enhanced-TEOS, 2 or plasma-enhanced-silane oxide) with or without dopant can be used to adjust for etchback selectivity between SOG and dielectric. ("TEOS", or tetraethoxysilane, is a popular and convenient feedstock for deposition of oxides from the vapor phase.) Thicknesses between 100nm and 500nm (1000Å and 5000Å) can be used; d) application of a second layer of SOG and/or SOG cure; and e) SOG etchback. This process will leave a layer of dielectric between the 1st and 2nd SOG layers in locations where conventional planarization technique are likely to crack or void. This provides enhanced reliability. The thickness of the first SOG layer can be reduced to avoid any undesired effects, such as field inversion of underlying devices or enhanced hot-carrier injection. ( See, e.g., Lifshitz et al., "Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric," 12 IEEE ELECTRON DEVICE LETTERS 140-2 (March 1991).) A positive sloped valley is produced for second dielectric deposition. The step coverage will be enhanced due to this positive slope. The structure provided by these steps has improved resistance to cracking, and improved resistance to other undesirable possible effects of thick spin-on glass layers. The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein: Figures 1A-1C show steps in a conventional process; Figures 2A-2C show steps in a first embodiment of the invention; Figures 3A-3C show steps in a second embodiment of the invention. Figure 4 shows a sample device structure incorporating a planarization layer according to the disclosed innovations. The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. The disclosed process steps can be applied, for example, after fabrication of the first metal layer. Thus, the starting structure would be patterned metallization lines running over an interlevel dielectric which includes contact holes, and also has topographical excursions due to the underlying polysilicon layer(s) and field oxide layer. The maximum topographical excursion will include contributions from all of these. (However, the disclosed innovations can also be applied after fabrication of the second metal layer, before deposition of a third metal layer.) Figures 1A-1C show steps in a conventional process. The starting structure will of course be defined by the previous process steps; but assume, for example, that the recesses have widths of 0.8 µm each, are spaced on a minimum pitch of 1.6 µm, and have a maximum depth of 1 µm. (Of course, these numbers are merely illustrative.) As shown in Figure 1A, a first layer 1 of SOG would be spun on and cured, to a thickness of e.g. 300nm (3000Å) in flat areas. (The thickness is substantially more in recessed areas.) As is well known to those of ordinary skill, the thickness of the SOG is determined by the individual composition and by the spin rate. As seen in Figure 1A, a single deposition of SOG is not enough to fill the recesses. As shown in Figure 1B, a second layer 2 of SOG would then be spun on and cured, to provide an additional thickness of e.g. 300nm (3000Å) in flat areas. A global etchback step is then performed, to remove the SOG from flat areas. The resulting surface contour, as shown in Figure 1C, is susceptible to cracking. Figures 2A-2C show steps in a first embodiment of the invention. Assume that the same recess dimensions are used as in Figures 1A-1C. Again, the specific dimensions and parameters given here are merely illustrative, and do not delimit the invention. A first layer 1 of SOG is deposited as in Figure 1A. That is, for example, a siloxane-based spin-on glass (Such materials may be obtained, for example, from Ohka America™ or Allied Signal™ or other suppliers.) is spun on to a thickness of 200nm (2000Å) over flat areas, and is then cured for 60 minutes at 425°C. A layer 3 of low-temperature oxide is then deposited, to a thickness of 200nm (2000Å). (For example, this may be done by plasma-enhanced deposition of TEOS.) This produces the structure shown in Figure 2B. A second layer 2 of SOG is then be spun on and cured, to provide an additional thickness of e.g. 300nm (3000Å) in flat areas. A global etchback step is then performed, to remove the SOG and TEOS from flat areas. The resulting surface contour, as shown in Figure 2C, provides improved filling of the recessed areas. Moreover, the combination of slightly different materials (SOG and low-temperature oxide) reduces susceptibility to cracking. The drawing of Figure 2C shows exactly 100% etchback Figures 3A-3C show steps in a second embodiment of the invention. This may be particularly advantageous with more extreme topologies. In this embodiment, assume, for example, that the recessed areas have widths of 0.8 µm each, are spaced on a minimum pitch of 1.6 µm, and have a maximum depth of 2 µm. (Of course, these numbers are merely illustrative.) A first layer 1 of SOG is spun on and cured to produce a thickness of 200nm (2000Å) over flat areas, as shown in Figure 3A. A layer 3 of low-temperature oxide is then deposited, to a thickness of 300nm (3000Å). (For example, this may be done by plasma-enhanced deposition of TEOS.) This produces the structure shown in Figure 3B. A second layer 2 of SOG is then be spun on and cured, to provide an additional thickness of e.g. 200nm (2000Å) in flat areas. A global etchback step is then performed, to remove the SOG and TEOS from flat areas. The resulting surface contour, as shown in Figure 3C, provides improved filling of the recessed areas, even under extreme topologies. Moreover, the combination of slightly different materials (SOG and low-temperature oxide) reduces susceptibility to cracking. The drawing of Figure 3C shows exactly 100% etchback In alternative embodiments, it is also possible to deposit a plasma oxide before the first layer of spin-on glass. (This is commonly done to prevent direct contact between the SOG and the underlying metallization.) In this embodiment, 100nm-500nm (1000Å-5000Å) of (for example) TEOS oxide would be deposited before the first layer of SOG. Processing then continues with deposition of an interlevel dielectric, such as PSG, and conventional further processing steps. One particular advantage of the disclosed invention is that it can be very easily implemented (in at least some processes) by a simple transposition of steps (depositing the low-temperature oxide before, rather than after, the second layer of spin-on glass). Figure 4 shows a sample device structure incorporating a planarization layer according to the disclosed innovations. In this example, the partially fabricated device structure included active devices 12 in a substrate 10, including polysilicon lines 14. Field oxide 13 provides lateral separation active devices. Metal lines 18 overlie a first interlevel dielectric 16 (e.g. of BPSG over TEOS), and make contact to active device areas at contact locations 20. (This provides the starting structure on which planarization is performed as described above.) A planarization layer 22 is then deposited, by the techniques described above, to reduce or eliminate the topographical excursions of the structure. An interlevel dielectric 24 overlies the planarization layer 22 (and the rest of the planarized structure), and includes via holes 25 through which a second metal layer 26 contacts the first metal layer 18. The structure shown can be topped by a protective overcoat (not shown) through which holes are etched to expose locations of contact pads in the second metal layer. It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts. The disclosed innovative steps have been described in the context of via formation (e.g. forming connections from second metal to first metal, or third metal to second metal). Due to the accumulated topographical excursions, planarization is especially desirable at these stages. However, the disclosed innovative concepts can also be applied to planarization of lower levels as well. The disclosed innovative concepts can also be applied to other spin-on materials, such as polyimide or polymethylmethacrylate. As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.

Claims: An integrated circuit fabrication method, comprising the steps of: (a) providing a partially fabricated integrated circuit structure having conductive portions on the upper surface thereof and having an uneven topography including high points; (b) applying and curing spin-on glass, to form a first dielectric layer (1); (c) depositing a second dielectric layer under vacuum conditions (3); (d) applying and curing spin-on glass to form a third dielectric layer (2); (e) performing a global etchback step; (f) depositing an interlevel dielectric layer (24); (g) etching holes (25) in said interlevel dielectric layer in predetermined locations; and (h) depositing and patterning a metallization layer (26) to form a desired pattern of connections, including electrical connections through said holes to said conductive portions of the integrated circuit, characterised in that prior to step (e) said third dielectric layer (2) overlies said second dielectric layer (3) which overlies said first dielectric layer (1) and in that said global etchback step removes said third, second and first dielectric layers from the high points of said partially fabricated structure to form a planarized structure comprising the partially fabricated integrated circuit and the remaining portions of the first, second and third dielectric layers. The method of claim 1, wherein said second dielectric layer (3) is a layer of silicon dioxide. The method of claim 1 or 2, wherein said second dielectric layer (3) has a thickness equal to or less than said first dielectric layer (1) and said third dielectric layer (2) has a thickness equal to or greater than said second dielectric layer (3). The method of any one of claims 1 to 3, wherein said deposition step (c) is plasma-enhanced. The method of any one of claims 1 to 3, wherein said deposition step (c) uses TEOS as a source gas. The method of any one of claims 1 to 3, comprising the additional step of applying a passivating dielectric, under vacuum conditions, after said step (a) and before said deposition step (b). The method of any one of claims 1 to 3, wherein said deposition step (b) applies said spin-on glass with a thickness in the range of 100-500nm inclusive. The method of any one of claims 1 to 3, wherein said interlevel dielectric (24) is a doped silicate glass. The method of any one of claims 1 to 3, wherein said deposition step (d) applies said spin-on glass with a thickness in the range of 100-500nm inclusive. The method of any preceding claim, wherein said second dielectric layer (3) is doped. The method of any preceding claim, wherein said second dielectric layer (3) is a low temperature oxide. The method of any preceding claim, wherein said second dielectric layer (3) is deposited from the vapour phase. An integrated circuit comprising: an underlying structure, including therein a substrate, active device structures, isolation structures, and one or more patterned thin-film conductor layers including an uppermost conductor layer, said underlying structure having an uneven topography including recesses and high-points; a planarization structure within the recesses of said underlying structure comprising spin-on glass; an interlevel dielectric layer (24) overlying said planarization structure and said underlying structure and having holes (25) therein; and a thin-film patterned conductor layer overlying said interlevel dielectric layer extending through said holes to selected locations of said uppermost conductor layer, characterised in that said planarizing structure within the recesses of said underlying structure comprises a first dielectric (1) overlaid by a second dielectric (3) overlaid by a third dielectric (2) wherein said first and third dielectrics are spin-on glass, and said planarization structure does not overlie said high-points. An integrated circuit according to claim 13, wherein said second dielectric (3) is silicon dioxide.

Inventors: KALNITSKY ALEX, LIN YIH-SHUNG, KALNITSKY, ALEX, LIN, YIH-SHUNG
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L23