Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform

Abstract: An opto-electronic hybrid integrated circuit of the present invention satisfy a low-loss optical waveguide function, an optical bench function and a high-frequency electrical wiring function. The circuit includes a silicon substrate (1), an optical waveguide part (I) arranged in a recess of the substrate (1), and an optical device mounting part (II) formed on a protrusion (52) of the substrate (1). An optical device (37) is mounted on an optical sub-module (44). This sub-module (44) is placed on the protrusion (52). An electrical wiring part is disposed on another protrusion 35 of the substrate (1).

Description: The present invention relates to an opto-electronic hybrid packaged platform capable of incorporating an optical device or optical sub-module used for optical communication and optical signal processing in addition to optical waveguides and electrical wirings, an optical sub-module which can be equipped on the board, and an opto-electronic hybrid integrated circuit equipped with the optical device or optical sub-module, and to a method for producing the hybrid optical integration platform. With recent advance in optical communication and optical information processing, development of an opto-electronic integration circuit is in demand, in which active devices are incorporated in low-loss optical waveguides and the like to be driven by a high-frequency electrical circuit. To achieve a circuit incorporated with active devices on the optical waveguide and high-frequency driven, three conditions are required for the optoelectronic board, which are (1) a low-loss optical waveguide function, (2) an optical bench function to incorporate an optical device on the same substrate and prevent axis deviation, and (3) a high-frequency electrical wiring function required to drive the optical device. However, a circuit that satisfies the above three conditions has not been obtained with the prior art. As a prior art example, Fig. 1 is a schematic perspective view showing construction called "Silicon optical bench" in which, using a guide groove 2 and positioning reference surfaces 3a, 3b, and 3c formed on a silicon substrate 1, an optical fiber 4 and a semiconductor laser (LD) 5 are integrated on the silicon substrate. In this construction, since the guide groove can be formed with a good precision utilizing good processability of the silicon substrate, integration of the optical fiber 4 with optical devices such as the semiconductor laser (LD) 5 and a photo-detector (PD) can be easily achieved. Further, since the silicon substrate is superior in thermal conductivity, it also functions as a good heat sink for optical devices. Further, the electrical wiring 6 is formed directly on the surface of the silicon substrate 1, or through a very thin oxide film of less than 0.5µm in thickness, but this structure has a problem of considerably deteriorating the high-frequency characteristics of the electrical wiring 6. That is, to form the electrical wiring 6 with superior high-frequency characteristics, the electrical wiring layer must have a sufficient thickness and be formed on an insulator with small dielectric loss. However, the silicon substrate 1 is very thin in thickness, the resistance is not high enough to ensure the high-frequency characteristics, and has a specific resistivity of about 1 k-ohm.cm. Fig. 2 shows high-frequency characteristics of a 0.6 mm long coplanar wiring formed directly on the silicon substrate (T. Suzuki et al.: Microwave Workshop Digest (1993) p95). The axis of ordinates indicates transmission characteristics S 21 of S parameter and the axis of abscissas indicates a frequency (GHz). Loss of the 0.6 mm long wiring is about 0.4 dB (2 GHz) and about 0.8 dB (10 GHz), which are converted to 1 cm as 7 dB (2 GHz) and 13 dB (10 GHz), thus showing a substantial loss. On the other hand, an optical packaged circuit having an optical waveguide function, application of silica-based optical waveguide formed on the silicon substrate is expected. Prior art optical waveguides include (1) a "ridge type optical waveguide" in which the core is protected with a thin over-cladding layer as shown in Figs. 3A and 3B, and (2) an "embedded optical waveguide" in which the core is embedded in a sufficiently thick over-cladding layer as shown in Figs. 3C and 3D. Fig. 4 is a schematic perspective view showing an example of the ridge type optical waveguide which is described in a document. This document is "Hybrid-Integrated 4 × 4 Optical Gate Matrix Switch Using Silica-Based Optical Waveguides and LD Array Chips", IEEE J. Lightwave Technol., vol.10, pp. 383-390, 1992, by Y. Yamada et al. This example shows a hybrid optical integrated circuit including a silica-based optical waveguide 7 formed on the silicon substrate 1 and a semiconductor optical device 8. In this example, a semiconductor laser amplifier represents as SLA. The optical waveguide 7 has a structure of ridge type optical waveguide, in which a core 7a formed on a thick under-cladding layer 7c formed on the silicon substrate 1 is protected with very thin cladding layers 7b and 7c. The SLA 8 is surface packaged in an upside-down construction in which an active layer 8a is facing down in the vicinity of the waveguide end, and a heat sink 9 for heat dissipation is provided on the backside. Since, in such a structure, the core is only covered with very thin cladding layers 7b and 7c, it has problems that (1) the optical waveguide has a large loss, (2) it is liable to be affected by external disturbance, and (3) formation of a directional coupler circuit is difficult. In particular, the directive coupler is an indispensable circuit element to fabricate a high-performance optical circuit, and the impossibility of the formation means that application of the ridge type optical waveguide is limited to a narrow area. Thus, the ridge type optical waveguide does not sufficiently satisfy the optical waveguide function. Further, electrical wiring function is not investigated here. Fig. 5 shows an example of "optical waveguide circuit with terrace" (Yamada, Kawachi, Kobayashi: Japanese Patent Application Laying-open 63-131104 "Hybrid Optical Integrated Circuit") in which an optical waveguide is formed in a recess 1a on a silicon substrate 1 having irregularities and a device is equipped on a protruded part 1b. In Fig. 5, an under-cladding layer 10c of a silica-based optical waveguide 10 is formed in the recess 1a of the silicon substrate 1, and a core layer 10b is formed on top, and finally an embedding cladding layer 10a is formed. The upper surface of the under-cladding layer 10c and the upper surface of the protruded part 1b of the silicon substrate are in line in height, and the protruded part 1b can be used as a height reference surface of the optical device 8. In such a substrate 1, low-loss optical waveguide function and optical bench function are satisfied, but a function to provide high-frequency wirings is not considered quite at all. When an electrical wiring is equipped, it is formed on the protruded part 1b of the silicon substrate 1, which does not satisfy the requirements for high-frequency characteristics. In Fig. 5, the reference numeral 8a indicates an active layer, and 11 indicates a reference surface for device positioning. Fig. 6 is a schematic perspective view showing construction of a hybrid optical integrated circuit disclosed in Japanese Patent Application Laying-open No. 62-242362. This circuit almost comprises a buffer layer 12 provided on a silicon substrate 1, a silica-based optical waveguide 13 provided thereon, a device holding table 14 having the same height from the upper surface of the silicon substrate 1 as the buffer layer 12, a semiconductor laser 15 held in upside-down construction on the holding table 14, and an electrical wiring table 16 having a conductive film 16a electrically connected with a gold wire to the upper electrode of the semiconductor laser 15 and protrudingly provided on the upper surface of the silicon substrate 1. The reference numeral 17 indicates a heat sink. In such a circuit construction, since a difference in height from the upper surface of the buffer layer 12 to the core of the waveguide 13 is set equal to the difference in height from the upper surface of the device holding table 14 to the active layer 15a of the semiconductor laser 15, it has an advantage that optical devices such as a semiconductor laser can be equipped with a very high positioning precision. However, even with this circuit, the optical waveguide 13 is limited to the ridge type, tends to be affected by external disturbance, and cannot provide a low loss optical waveguide function. Fig. 7 is a schematic perspective view showing construction of a hybrid optical integrated circuit disclosed in Japanese Patent Application Publication 5-2748. This circuit mainly comprises an optical waveguide 18 protrudingly disposed with nearly the same height on the silicon substrate, an optical fiber guide 19, an optical device guide 20, an electrical wiring holding table 21, a first conductive film (common electrode) 22 disposed on the silicon substrate 1, a second conductive film 23 disposed on the upper surface of the electrical wiring holding 21 and insulated from the first conductive film 22, an optical fiber 24 disposed along the optical fiber guide 19, and a laser diode 25 as an optical device disposed long the optical device guide 20. The circuit of this construction, since the optical device is equipped directly on the silicon substrate, has an advantage that the silicon substrate can be functioned as a heat sink. However, even with this circuit, the optical waveguide 18 is limited to the ridge type, tends to be affected by external disturbance, and cannot provide a low loss optical waveguide function. Fig. 8 is a schematic cross sectional view showing construction of an optical waveguide device disclosed in Japanese Patent Application Laying-open 5-60952. This device mainly comprises a silicon substrate 1, an optical waveguide formed on the substrate 1, and a semiconductor device 27 equipped in an upside-down construction in a recess of the silicon substrate 1. In the device of this construction, since the optical waveguide 26 is formed on a convex region of the silicon substrate 1, an under-clad of a sufficient thickness cannot be formed. Therefore, it has a large transmission loss, tends to be affected by external disturbance, and does not satisfy a sufficient optical waveguide function. Further, in the above device, since the electrical wiring 28 is provided on the silicon substrate 1, requirements for high-frequency characteristics are not satisfied. As described above, the prior art hybrid optical integration technology does not satisfy the above three requirements. In particular, the high-frequency electrical wiring function has not been considered. Further prior art is known from the "Proceedings of the 43 rd Electronic Components & Technology Conference", 1993, pp. 826-830 (particularly the Figs. 2, 3 and 6 and their corresponding description). Therein, a terrace (sub-carrier), an optical waveguide member (multi-mode optical fiber) and an electrical wiring member (multi-layer ceramic wiring board) which are individually produced is disclosed. Additionally, the electrical connection between the terrace and the electrical wiring member is performed by a wiring-bonding method because the terrace and The electrical wiring member are separate from each other. On the other hand, the parts above are not prepared on a same substrate. In this document, the electrical connection between the terrace and the electrical wiring member is performed by a wiring-bonding method because the terrace and the electrical wiring member are separate from each other. Furthermore, document JP-A-5 067 770 discloses an optical wiring board having a projecting part used as a terrace, an optical waveguide formed on a surface except for the projecting part of the silicon substrate, and a reflecting film functions as an interconnection for power supply, with the film being formed on a slope as an inclined side surface of the terrace. A photoelectronic IC chip is mounted on the terrace of the board. The IC chip has a light emitting device and a photodetector each facing the slope when the IC chip is mounted on the terrace. Besides that, the reflecting film functions only as an electrical wiring part being formed on the slope of the terrace, whereas the electrical wiring parts on the terrace and on the dielectric layer are not electrically connected with the electrical wiring part formed on the slope. The optical waveguide is set lower than the surface of the terrace and not such that the core of the optical waveguide is set higher than the surface of the terrace. Moreover, document JP-A-62 242 362 discloses a terrace, an optical waveguide and an electrical wiring part which are made of the same material. An upper surface of the terrace is set lower than the optical waveguide, and accordingly an optical device for optically connecting with the optical waveguide is able to be mounted on the upper surface of the terrace in a face-down state. Thus, this document discloses only an electrical wiring part formed on a dielectric layer. In addition, there is no structure including a silicon terrace as an optical device mounting part. Further, an electrode formed on the optical device and an electrical wiring part formed on the optical waveguide are electrically connected with a wire-bonding technique. Therefore, again the electrical wiring parts on the terrace and on the dielectric layer are not electrically connected without a wire. Furthermore, document EP-A-0 466 134 discloses a substrate having a terrace as a protrusion which is higher than a surface of the substrate, an optical fiber arranged in a v-shaped groove of the substrate, and an electrical wiring part formed on the surface of the substrate. The surface of the electrical wiring part on the substrate is set lower than an upper surface of the terrace. A core of the optical fiber is set higher than the surface of the terrace, and accordingly an optical device can be mounted on the terrace in a facedown state. In this document, all of the electrical connection including the connection with the optical device is carried out on the plan surface of the substrate. Moreover, the electrical wiring part is not arranged on both of the terrace and on the dielectric layer. In summary, none of the above discussed prior art arrangements satisfies the demands for a high-frequency electrical wiring in an opto-electronic hybrid packaged platform. Hence, it is an object of the present invention to solve the above drawbacks inherent to the known prior art devices, and to provide an opto-electronic hybrid packaged platform which, while satisfying a low-loss optical waveguide function and an optical bench function, exhibits superior high-frequency electrical wiring characteristics. A further object of the present invention is to provide a method for producing a corresponding opto-electronic hybrid packaged platform. A still further object of the present invention is to provide a corresponding opto-electronic hybrid integrated circuit. According to the present invention, the foregoing objects are achieved by the claimed subject matter as set out in the claims 1, 14, and 15, respectively. Favourable refinements of the present invention are defined in respective dependent claims. The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings. Fig. 1 is a schematic perspective view showing construction called "silicon optical bench"; Fig. 2 is a graph illustrating high-frequency characteristics of a 0.6 mm long coplanar wiring formed directly on the silicon substrate; Fig. 3A is a cross-sectional view showing a platform having a structure of ridge type optical waveguide; Fig. 3B is a cross sectional view showing an optical device mounting part of the platform as shown in Fig. 3A; Fig. 3C is a cross sectional view showing a platform having a structure of embedded type optical waveguide; Fig. 3D is a cross sectional view showing an optical device mounting part of the platform as shown in Fig. 3D; Fig. 4 is a schematic perspective view showing a platform having a ridge type optical waveguide; Fig. 5 is a schematic perspective view showing a platform having an embedded type optical waveguide; Fig. 6 is a schematic perspective view showing construction of a hybrid optical integrated circuit disclosed in Japanese Patent Application Laying-open No. 62-242362; Fig. 7 is a schematic perspective view showing construction of a hybrid optical integrated circuit disclosed in Japanese Patent Application Publication 5-2748; Fig. 8 is a schematic perspective view showing an example of a conventional optical semi-conductor device; Fig. 9 is a schematic perspective view showing an opto-electronic hybrid integrated circuit; Fig. 10 is a schematic perspective view showing a second opto-electronic hybrid integrated circuit; Fig. 11 is a cross-sectional view showing an optical device mounting part of the platform according to the invention in the circuit as shown in Fig. 10; Fig. 12 is a cross-sectional view taken on line A-A' of Fig. 10; Fig. 13 is a cross-sectional view taken on line B-B' of Fig. 10; Figs. 14A to 14D are cross-sectional views showing an embodiment of a process for fabricating a platform according to the present invention, respectively; Fig. 14A is a cross-sectional view showing a process for forming a silica-based optical waveguide on a substrate; Fig. 14B is a cross-sectional view showing a step for forming silicon terraces for mounting an optical device and an electrical circuit, respectively; Fig. 14C is a cross-sectional view showing a step for removing a layer of polyimide which is formed on the terraces as shown in Fig. 14B to expose the terraces; Fig. 14D is a cross-sectional view showing a step for forming an electrical wiring part on the polyimide layer; Fig. 15 is a schematic perspective view showing a third embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Figs. 16A to 16E are cross-sectional views showing another embodiment of a process for fabricating a platform according to the present invention, respectively; Fig. 16A is a cross-sectional view showing a step for forming a part corresponding to a silicon terrace on a substrate; Fig. 16B is a cross-sectional view showing a step for forming an under-cladding layer of silica-based optical waveguide in a recess of the substrate; Fig. 16C is a cross-sectional view showing a step for forming a core pattern and an over-cladding layer on the under-cladding layer; Fig. 16D is a cross-sectional view showing a step for removing the core pattern and the over-cladding layer to expose the silicon terrace; Fig. 16E is a cross-sectional view showing a step for forming an electrical wiring part on the under-cladding layer; Fig. 17 is a schematic perspective view showing a fourth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 18 is a cross-sectional view taken on line A-A of Fig. 17; Fig. 19 is a graph illustrating the curvature radius of the substrate and the axis deviation between LD array and an optical waveguide core; Fig. 20 is a schematic perspective view showing an optical device as a single body corresponding to the array optical device as shown in Fig. 18; Fig. 21 is a cross-sectional view taken on line A-A of Fig. 20; Fig. 22 is a cross-sectional side view showing the circuit as shown in Fig. 18; Fig. 23 is a cross-sectional side view showing a circuit whose coplanar wiring part is lowered as compared to Fig. 18; Fig. 24 is a cross-sectional side view showing a circuit whose coplanar wiring part is formed on an under-cladding part, and whose the under-cladding part is thick as compared to Fig. 18; Fig. 25 is a schematic perspective view showing a fifth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 26 is a cross-sectional view taken on line D-D of Fig. 25; Fig. 27 is a schematic perspective view showing a sixth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 28 is a cross-sectional view taken on line C-C of Fig. 27; Fig, 29 is a schematic perspective view showing a seventh embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 30 is a cross-sectional view taken on line E-E of Fig. 29; Fig. 31 is a schematic perspective view showing an eighth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 32 is a cross-sectional view taken on line X-X of Fig. 31; Fig. 33 is a schematic perspective view showing a ninth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 34 is a schematic perspective view showing a eleventh embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 35 is a schematic perspective view showing a twelfth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 36 is a schematic perspective view showing a thirteenth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Fig. 37 is a schematic perspective view showing a fourteenth embodiment of an opto-electronic hybrid integrated circuit according to the present invention; Comparative example Fig. 9 is a schematic perspective view showing a hybrid optical integrated circuit. The reference numeral 1 indicates a substrate, and the present example uses a silicon substrate provided with a protrusion and a recess on the surface. The reference numeral 30 indicates a silicon terrace which functions as an optical device mounting part, utilizing the protruded upper surface of the silicon substrate 1. The reference numeral 31 indicates an optical fiber used as an optical waveguide of the present example, which is held in an optimum position in a V-groove provided in the silicon terrace 30. The reference numeral 52 indicates a thin film electrode for contacting with the surface electrode of the an optical functional device disposed on the silicon terrace 30, which is formed by patterning a 1µm thick Au-Sn solder on a 0.5µm thermal oxide film provided on the silicon terrace 30 surface. This thin film electrode 52 is electrically connected to a surface electrode pattern 51 of the optical functional device disposed on the surface of a dielectric layer 50 formed in a recess of the silicon substrate of the electrical wiring portion. The reference numeral 35 indicates a silicon terrace for electronic circuit. The terrace 35 is surrounded by a dielectric layer 33, and a conductor pattern 51 for electronic circuit is formed on the surface. In the present embodiment, the silicon recess has an 80µm step, the dielectric layer 50 has a thickness of 50µm, and the conductor pattern 51 on the dielectric layer 50 is formed by a 5µm thick Au plating. As a result, a 25µm step is provided between the upper surface of the terrace 35 and the upper surface of the conductor pattern 51. The reference numeral 37 indicates an optical functional device, and the present embodiment uses a semiconductor laser (LD). The device 37 is put on a device mounting part on the silicon terrace 30 in an upside-down configuration with the active layer facing down, thereby achieving positioning in the height direction between the fiber and LD without core adjustment. Positioning in the lateral direction may be made by monitoring the optical coupling efficiency of the optical fiber and the LD, or using a guide structure formed at the substrate side without core adjustment. In this case, the active layer side electrode of the LD 37 contacts the thin film electrode 52 on the silicon terrace 30, and electrically connected with a conductor pattern 38 on the dielectric layer 50. In the thin film electrode 52, the solder is heat melted to fix the LD 37 on the substrate. Since the LD is fixed using the thin film electrode 52 on the silicon terrace 30 as shown above, the silicon terrace 30 can be utilized as a heat sink. At the same time, since electrical wiring except the connection with the optical functional device is provided on the dielectric layer 50 having a sufficient thickness, superior high-frequency characteristics can be obtained. The electronic circuit 38 is disposed on the silicon terrace 35 with the device forming surface facing down. In this case, since the upper surface of the conductor pattern 51 on the dielectric layer 50 is set 25µm lower than the upper surface of the silicon terrace 35, when an about 25µm thick solder bump is used, the surface of the central portion of the electronic circuit can be contacted to the upper surface of the silicon terrace 35 and, at the same time, the electronic circuit electrode can be contacted with the conductor pattern 51 of the dielectric layer 50 without using an electrical wiring. Therefore, in the present embodiment, heat dissipation of the electronic circuit using the silicon terrace 35 is possible, and a high-frequency electrical wiring is achieved not through the silicon substrate 1. As described above, with the optical/electronic hybrid integrated substrate of the present comparative example, the optical bench function of the silicon terrace, that is, optical axis positioning function between the optical functional device and the optical fiber, a heat dissipation function of the optical functional device and the electronic circuit can be achieved, and the high-frequency electrical wiring function can be provided. Embodiment 1 Fig. 10 is a schematic perspective view showing the entire construction of a second embodiment of the optical/electronic hybrid optical integrated circuit of the present invention. Fig. 11 is a schematic cross sectional view in the vicinity of the circuit shown in Fig. 10, Fig. 12 is a cross sectional view taken along surface AA' in Fig. 10, and Fig. 13 is a cross sectional view taken along surface BB' in Fig. 10. As shown in Fig. 10, the packaged substrate of the present embodiment uses the silicon substrate 1 provided with a protrusion and a recess on the surface as in Embodiment 1. In the optical waveguide unit, a silica-based optical waveguide 40 is formed in the recess of the silicon substrate 1. As shown in Fig. 12, the silicon terrace 35 is provided on the optical device mounting part. In the electrical wiring portion, a dielectric layer 50 comprising a polyimide resin is formed in the recess of the silicon substrate, the conductor patterns 51 and 510 are provided on the surface and inside. The silicon terrace 35 for electronic circuit is disposed at the center of the electrical wiring portion. As shown in Fig. 11, there is a 17µm step in the silicon recess in the optical waveguide part on the left side of the silicon terrace 35, and a silica-based optical waveguide 40 comprising an under-clad 41 (20µm thick), a core 42 (6µm × 6µm), an over-clad 43 (15µm thick) is stacked on top. The waveguide structure is referred to as an "embedded type structure", which has superior optical waveguide characteristics since the core pattern is embedded in a clad layer with a sufficient thickness. The silicon terrace 30 has an inclined side surface, and the upper surface and the electrical wiring side surface are provided with a thin film electrode 52 formed by patterning a 1µm thick Au-Sn solder. Distance from the surface of the thin film electrode 52 to the optical waveguide core center is 5µm. This size is equal to the distance from the surface of the mounted LD to the active layer, and positioning in the height direction of the optical waveguide core 42 and the optical functional device can be achieved without adjustment by mounting the optical functional device on the silicon terrace 30 in the upside-down condition with the surface of the active layer facing down. The electrical wiring portion on the right of the silicon terrace includes the dielectric layer 50 comprising a 15µm thick polyimide on the recess of 25µm depth in silicon, the conductor pattern 51 comprising a 5µm thick Au pattern formed on the surface, and the conductor pattern 510 formed inside. The conductor pattern 51 on the dielectric layer 50 electrically contacts the thin film electrodes 52 formed on the upper surface and the side surface of the silicon terrace. In this case, there is a step of about 10µm between the surface of the silicon terrace 35 and the surface of the dielectric layer 50, and such electrical wiring can be achieved between two layers with different heights because the side surface of the silicon terrace is inclined. When the silicon terrace 35 side surface is formed nearly vertical, it is difficult to electrically connect the two layers without using a wire because the electrical wiring is opened by the step between the thin film electrode on the silicon terrace and the conductor pattern on the dielectric layer. In the electrical wiring portion, as shown in Fig. 10, the silicon terrace for electronic circuit is provided at the center, where the electronic circuit is disposed. The electrical wiring connecting the silicon terrace for optical device and the silicon terrace for electronic circuit is formed of a coplanar wiring comprising a central conductor 51a and a ground conductor 51b. Electrical wiring around the electronic circuit is formed of a microstrip wiring comprising the surface conductor pattern 51 and the ground conductor 510 provided in the dielectric material. As shown in Fig. 13, the ground conductor 51b of the coplanar wiring and the ground conductor 510 of the microstrip wiring are connected with a through electrode 520 provided in the dielectric layer. Comparing the coplanar wiring and the microstrip wiring, the former can be easily formed since it is formed of a single layer of electrical wiring, but the wiring density is not high. On the other hand, the latter has a multilayer of electrical wiring and requires a complex fabrication work, but can achieve a high wiring density. Since, in the present embodiment, polyimide is used, which is easy to form a multilayer wiring as a dielectric layer in the electrical wiring portion, formation of the microstrip wiring is possible. By the use of such a packaged substrate structure, integration of the optical functional device and the electronic circuit with a number of connection terminals. The optical functional device 37 mounted on the packaged substrate is a semiconductor laser (LD), which is mounted on a sub-carrier 44, which is formed by processing a heat conductive material such as the silicon substrate. The sub-carrier 44 has a protrusion and a recess formed on the surface, and is fixed so that, after a conductor pattern electrically connected from the protrusion surface to the recess surface, the LD backside contacts on the recess, and the LD backside and the conductor pattern on the sub-carrier are electrically connected. To mount the LD mounted on the carrier on the silicon terrace 30, the active layer side surface of the LD is faced down and contacted with the silicon terrace 30. the LD active layer side electrode and a first thin film electrode 53a directly contact each other, and the LD backside electrode contacts a second thin film electrode 53b on the packaged substrate through the sub-carrier. In this case, since the distance from the thin film electrode surface on the silicon terrace to the waveguide core center and the distance from the LD device to the active layer are in line with each other, positioning in the height direction with the optical waveguide is completed merely by mounting the LD. Positioning within the surface is made by monitoring the coupling effect of the optical waveguide with the LD. The silicon terrace is a reference surface with high precision when mounting the device and, at the same time, functions as a heat sink. The electronic circuit is mounted on the silicon terrace using solder bump with the device surface facing down as in Embodiment 1. In this case, as described above, the height of the dielectric layer of the electrical wiring portion and the conductor pattern surface formed thereon is lower than the upper surface of the silicon terrace. As a result of the structure, it is possible to contact/mount the electronic circuit on the SILICON terrace, and directly contact all electrodes of the electronic directly with the conductor pattern on the dielectric layer not through the electrical wiring on the silicon terrace. Thus, the electronic circuit can be mounted with superior heat dissipation characteristics and high-speed operation. As described above, in the present embodiment, the silicon terrace for electronic circuit is provided in the electrical wiring portion, and the height of the conductor pattern surface around the circuit is set lower than the SILICON terrace. Therefore, in the optical/electronic hybrid integrated circuit of the present embodiment, the electronic circuit electrodes and the conductor pattern on the dielectric layer can be electrically directly connected using solder bump and, at the same time, the electronic circuit can be packaged while maintaining contact with the silicon terrace. Further, since the side surface of the SILICON terrace is inclined, in spite of the step between the upper surface of the SILICON terrace and the conductor pattern on the dielectric layer, the thin film electrode provided on the SILICON terrace for the optical device and the conductor pattern on the dielectric layer can be electrically connected. Therefore, the electrode leads of the optical functional device can be provided on the SILICON terrace to enhance the heat sink effect, and all electrical wirings other than the electrode leads can be formed on the dielectric layer, thereby achieving superior high-frequency characteristics. With the present embodiment, the optical bench function, that is, the optical axis positioning function between the optical functional device and the optical fiber and the heat dissipation function of the optical functional device and the electronic circuit are possible, and the high-frequency electrical wiring function can be provided. The packaged substrate of the present embodiment can be fabricated, for example, in steps shown in Fig. 14A to 14D. First, by a method described later, a recess is formed on the silicon substrate 1, and the silica-based optical waveguide 40 comprising the under-clad layer 41, the core pattern 42, and the over-clad layer 43 is formed (Fig. 14A). Then, the surface of the SILICON substrate 1 is processed to form the silicon terrace 30 for optical device and the silicon terrace 35 for electronic circuit are formed. In this case, on the bottom surface of the silicon recess in the vicinity of the silicon terrace 35 for electronic circuit, the conductor film silicon such as gold or copper is provided as a ground conductor layer (Fig. 14B). On top of it, polyimide is coated and cured as a dielectric material for the electrical wiring portion, unnecessary polyimide is removed by dry etching or the like to expose the silicon terraces 30 and 35. Further, the polyimide layer 50 is etched so that the layer is lower by a predetermined step from the silicon terrace (Fig. 14C). Finally, the conductor pattern 51 is formed on the surface of the dielectric material 50, and the thin film electrode 52 is formed to electrically connect with the conductor pattern 51 on the dielectric layer 50 on the silicon terrace 30 for the optical device. Embodiment 2 Fig. 15 is a schematic perspective view showing construction of a third embodiment of the hybrid optical integrated circuit of the present invention. A major difference of the present embodiment from Embodiment 2 is that the dielectric layer of the electrical wiring portion is formed using the same material as the optical waveguide. That is, the silicon recess is formed by providing a 33µm step from the silicon terrace surface with the optical waveguide and the electrical wiring portion. In the silicon recess corresponding to the optical waveguide, the silica-based optical waveguide 40 having the under-clad 41 (35µm thick), the core 42 (6µm × 6µm), and the over-clad 43 (30µm thick) is formed. On the other hand, on the silicon recess corresponding to the electrical wiring portion, the under-clad layer 41 of the silica-based optical waveguide if formed as the dielectric layer 50. It has a thickness of 25µm, and is 10µm lower than the upper surface of the silicon terrace 10 for the optical device and the silicon terrace 35 for the electronic circuit. Since the height of the conductor pattern upper surface of the electrical wiring portion is set lower then the upper surface of the silicon terrace, important electrical wiring can all be formed on the dielectric layer and connected using solder bump, and the electronic circuit and the silicon terrace can be contacted. Therefore, the packaged substrate has high-frequency electrical characteristics and good device heat dissipation function. The structure of the present embodiment, in which the dielectric material of the electrical wiring portion and the optical waveguide are formed of the same material, has an effect to simplify the substrate formation step. For the effect, the substrate formation process will be described with reference to Figs. 16A to 16E. A first step of the substrate fabrication is to form a step corresponding to the silicon terrace on the substrate (Fig. 16A). In the present embodiment using silicon as the substrate, a desired step can be formed by anisotropic etching using an alkali etching solution such as KOH. By appropriately selecting the crystal orientation of the silicon substrate, the silicon terrace side surface can be formed with an inclination of about 7° as shown. After that, the under-clad layer 41 of the dielectric optical waveguide such as silica-based optical waveguide is formed on the substrate recess, and the surface is flattened by polishing or the like (Fig. 16B). Then, the core pattern 42 and the over-clad layer 43 of the optical waveguide are formed (Fig. 16C). After that, the optical waveguide formed in the region of the electrical wiring including the silicon terrace is removed by etching to expose the silicon terrace. At this time, in the etching step of the silica-based optical waveguide and the polymer waveguide (polyimide optical waveguide, etc.), that is, in reactive ion etching using a mixture of CF 4 and H 2 or O 2 gas as an etchant, the silicon substrate 1 can be used as an etching stop layer. Therefore, when the silicon terraces 30 and 35 are exposed as the etching advances, etching of the surface does not advance. On the other hand, etching of the optical waveguide portion is continued. As a result, the step between the dielectric surface of the electrical wiring portion and the silicon terrace can be formed by a single etching step (Fig. 16D). Finally, the conductor pattern is formed on the dielectric surface of the electrical wiring portion, and the thin film electrodes are formed on the surface and the inclined surface of the silicon terrace to form the packaged substrate of the present embodiment (Fig. 16E). In this case, an anisotropic etching of the silicon substrate is used in the step shown in Fig. 16A, an inclination can be automatically formed on the silicon terrace side surface. Since this method can easily form the inclination of the silicon terrace side surface, even with a step between the silicon terrace and the upper surface of the dielectric layer, the electrical wiring can be formed without open circuit between both. Thus, by forming the dielectric optical waveguide and the dielectric layer of the electrical wiring portion using the same material, the fabrication process can be simplified compared to formation of both parts with different materials. Further, that the silicon terrace side surface is inclined as described above, rather than formed vertically, has an effect to considerably relax difficulty of packaged substrate fabrication. That is, when the silicon terrace side surface is formed nearly vertical, for example, in the packaged substrate in Fig. 9, if there is a step between the silicon terrace for optical device and the upper surface of the dielectric layer 50, it is difficult to electrically connect the thin film electrode 52 on the silicon terrace 30 and the conductor pattern 51a on the dielectric layer 50. Therefore, formation of the upper surface of the silicon terrace and the upper surface of the dielectric layer without a step in the process of Fig. 16D in order to achieve an electrical wiring as shown in Fig. 9 using a silicon terrace having a vertical side surface requires very high control over the etching time and etching rate of the optical waveguide, which makes fabrication of the packaged substrate of this structure extremely difficult. This difficulty is eliminated by inclining the side surface of the silicon terrace as described above. Embodiment 3 Fig. 17 is a schematic perspective view of a fourth embodiment of the hybrid optical integrated circuit of the present invention, and Fig. 18 is a schematic cross sectional view taken along line A-A in Fig. 17. The Figures show an embedded type optical waveguide 60 in which an under-cladding layer 60c, a core 60b, and an over-cladding layer 60a are integrated on the silicon substrate 1. Since the example shown in Fig. 17 is intended to mount a 400µm pitch 4-array optical device, the cores 60b are arranged at 400µm intervals. As shown in Fig. 18, a coplanar line 61 comprising a central conductor 61a of 400µm interval and a ground conductor 61b is formed. A width W of the central conductor 61a, a gap interval S between the central conductor 61a and the ground conductor 61b, and a thickness H of the silica-based waveguide layer between the coplanar line 61 and the silicon substrate 1 are important parameters affecting the high-frequency characteristics of the coplanar line 61. The parameters will be described later with reference to a table. A mounting part 63 of an optical device 62 is formed by etching the over-cladding layer 60a to expose the upper surface of the under-cladding layer 60c, where an electrical wiring layers 63a and 63b are formed. In this case, a 5µm thick Au plated wire is used as the electrical wiring layers 61a, 61b, 63a, and 63b, and the length of the wiring layers 63a and 63b is set to less than 1 mm to reduce the loss. The central conductor 61a of the four coplanar lines 61 is connected by gold ribbon wires 64 to copper, block, and a guide post 65a called ground post, connected to the electrical wiring layer (electrode) 63a on the under-clad 60c, and connected to four electrodes 62c under the optical device 62 through a solder pattern 66 comprising a gold-tin alloy. The ground conductor 61b of the coplanar line 61 is similarly connected to the guide post 65b by a gold ribbon wire 64, connected to the electrical wiring layer (electrode) 63b on the under-clad 60c, and connected to the electrical wiring layer 67a of a silicon sub-carrier 67 through the solder pattern 66. Here, the silicon sub-carrier is formed on the surface with a conductive layer 67a, and held by connecting the electrode 62b on the backside of the optical device 62 to the conductive layer 67a of the recess by gold-tin solder. Therefore, with the optical device 62 mounted on the mounting part 63, it is possible to high-frequency drive with the four arrays by the coplanar line 61. With the optical device 62 mounted on the mounting part 63, four active layers 62a of the optical device 62 are optically coupled with the core 60b of the silica-based optical waveguide at the front side in Fig. 17. In the present embodiment, positions of the electrode 62 and solder pattern 66 of the optical device 62 are shifted to the side from directly beneath the active layer 62a of the optical device 62, thereby preventing stress due to mounting of the optical device from directly acting on the active layer. Here, the S parameter S 21 and axis deviation as an optical bench function will be considered on the main parameters W, S, and H which affect the high-frequency characteristics of the coplanar line. Table 1 shows the relationship between w and s and transmission loss S 21 of the coplanar line, and the silicon substrate 1 has an average resistivity of less than 1 ohm-cm. For parameters W and S, since patterning is made by coating a resist on the substrate having a several tens 1 step such as silica-based optical waveguide, it is difficult to form less than 20µm with good repeatability. Therefore, w and s are more than 20µm. In Table 1, the thickness h of the under-clad 2c is 24µm, and the thickness H of the entire silica-based waveguide is 601, and w is varied from Embodiment I-1 to Embodiment I-5. As a result, the S parameter S 21 is smallest when w and s are smallest, and the loss is the smallest. Since, in Table 1, the thicknesses h and H are not varied, the axis deviation is a constant value of 0.7µm even with 4 arrays. Table 2 utilizes the results of Table 1 so that (w, s) = (20,20)µm where S 21 is smallest, and S parameter and axis deviation are picked up when the thickness h of the under-clad 60c and H are varied. In Reference Examples II-1 and II-7, the prior art structure is applied, and in Reference Examples II-2 to II-6, h and H are varied. As a result, good results are shown in the vicinity of H = 50 to 90. Axis deviation is caused by warping of the substrate due to the thickness of the clad, which leads to an increase in coupling loss. Table 2 will be described in detail. As to the thickness H dependence, in general, loss in the high-frequency must be less than 1.0 dB/cm and, considering wide applications of the hybrid substrate of the present embodiment, it is required to be less than 1.5 dB/cm. From Table 2, to reduce the loss to less than 1.5 dB/cm, the total thickness H of the silica layer must be more than 50 µm. Further, for the hybrid substrate to maintain a good optical bench function, warping of the substrate must be small. In Fig. 18, since the silica-based optical waveguide layer and the silicon substrate 1 differ in thermal expansion coefficient, warping of substrate increases as H increases. When warping of the substrate is increased, the optical waveguide end face and optical device, for example, the active layer of the LD array, causes dislocation, resulting in optical coupling loss and impairing the optical bench function. Since the opto-electronic hybrid packaged substrate is required to be developed to 4 × 4 switches and the like, it is required that, for example, a 4-array LD module or the like is mounted on the substrate to deal with array application of the optical device. As a result, the value in the right column of Table 2 (axis deviation) is required to be decreased. Fig. 19 shows relationship of the thickness H of the silica layer on the silicon substrate, warping of the silicon substrate (curvature radius), and the axis deviation in a 400µm interval 4-array LD module. It can be seen from the Figure that the thickness H must be less than 120µm to reduce the axis deviation to less than 1µm. In summary, in the silica-based optical waveguide in Fig. 18, to satisfy the high-frequency electrical wiring function and the optical bench function for mounting the optical device, H is required to be more than 50µm and less than 120µm. As can be seen from Table 1 and Table 2, the example shown in Fig. 17 is practically and optimally usable as a low-loss optical waveguide, which uses a hybrid optical integrated substrate of under-clad h = 30µm, core diameter = 6 × 6µm, over-clad = 30µm, and total silica layer = 66µm. Further, transmission loss of the optical waveguide shown in Fig. 17 is less than 0.1 dB/cm, and when LD is used as an optical device, good characteristics are obtained in high-speed modulation of 10 GHz for the 4 arrays. Thus, the present embodiment has a low-loss optical waveguide function, an optical bench function with reduced axis deviation, and a high-frequency electrical wiring function with reduced S 21 . Figs. 20 and 21 show the 4-array of Fig. 17 divided into discrete devices. In this case, since it is not an arrayed device but the arrayed device is divided into discrete devices, even when warping of the substrate occurs, no axis deviation occurs, and it has the above three functions even except the condition of the thickness H of less than 120µm. On the contrary, when discrete devices are combined into an array, the condition of thickness H of less than 120µm is added. In the present embodiment, the coplanar line 61 is formed on the surface of the over-clad, but the coplanar line can also be formed in other positions. Fig. 22 shows a side view of Fig. 17, Fig. 23 shows a side view in which the over-clad 60a under the coplanar line 61 is made thin, and Fig. 24 shows a side view in which the entire under-cladding layer 60c is made thicker, and the coplanar like 61 is formed directly on the under-clad 60c. As in the examples shown in Figs. 23 and 24, even when the height of the coplanar wiring layer is set lower than the upper surface of the over-clad of the optical waveguide, it can also be used as a good opto-electronic packaged substrate as well. Embodiment 4 Embodiment 3 was an example using a general-purpose silicon substrate (resistivity: up to 1 ohm-cm). On the other hand, the high-frequency electrical wiring function can be even further improved by increasing the resistivity of the silicon substrate. This enables a thinner silica-based optical waveguide between the coplanar line and the silicon substrate, and construction is possible as shown in Fig. 25 in which the high-frequency line can be placed on a thinner under-clad 2c, thereby expanding the application. First, for the structural parameter of the substrate used in Fig. 25, optimization is made in view of the high-frequency electrical wiring function and the optical bench function by Fig. 26 which has the same structure as the D-D cross sectional view of the high-frequency electrical wiring portion in Fig. 25. In Figs. 25 and 26, the reference numeral 61a indicates a central conductor of the coplanar line, 61b indicates a ground conductor, 61c indicates an under-cladding layer, and 1 is a silicon substrate having a higher resistance than Embodiment 1 shown in Fig. 17. In Fig. 25, 67 is a sub-carrier of silicon, and the optical device 62 is held in the recess. A conductive layer 67a is formed on the surface of the sub-carrier 67, which electrically connects with the backside of the optical device 62. By connecting both legs of the sub-carrier to solder pattern 67b, the coplanar line 61 and the electrode 62b on the backside of the optical device 62 are electrically connected. On the other hand, the electrode 62c on the side of the active layer of the optical device is connected by a solder pattern 67b formed on the central conductor 61a of the coplanar line 61, and the optical device 62 can be operated by the coplanar line. Further, the silicon sub-carrier 67 absorbs heat generated in the optical device, and dissipates the heat to the air or the coplanar line 61. In the present embodiment, the position of the solder pattern 67b connecting to the electrode 62c of the optical device 62 is shifted to the side from directly beneath the active layer 62a of the optical device, thereby preventing a stress associated with mounting of the optical device from acting directly on the active layer. Main parameters affecting the high-frequency characteristics of the coplanar line are thickness h of the silica under-cladding layer between the coplanar line and the silicon substrate, width w of the central conductor 61a of the coplanar line, and gap spacing s between the central conductor 61a and the ground conductor layer 61b of the coplanar line. Relationship between the parameters S and W and S parameter S 21 representing loss of the coplanar line is shown in Table 3, and the S parameter S 21 and axis deviation by the thickness of the under-clad 2c based on s and w of Table 3 are shown in Table 4. The silicon substrate uses one which has an average resistivity of up to 50 ohm-cm. For w and s, since patterning is made by coating a resist on the substrate which has a step of several tens µm such as silica-based optical waveguide and the like, it is difficult to form in less than 20µm with good reproducibility. Further, Figs. 25 and 26 are examples of discrete optical devices, and Table 4 shows axis deviation due to warping of the substrate when a 4-array optical device is mounted in 400µm pitch. First, changes in conductor width w which is a structural parameter of the coplanar line and S parameter S 21 by the gap s are shown in Table 3. As can be seen from Table 3, as results of Embodiments III-1 to III-5, (w, s) = (20, 20)µ gives the smallest loss as in Table 1. Further, as shown in Table 4, with (w, s) = (20, 20)µm, S 21 and axis deviation with changes in the under-clad thickness h are shown. As shown, in order to reduce S 21 to less than 1.5 dB/cm at 10 GHz, h is required to be more than 20 µm. By increasing the resistivity of the silicon substrate, the thickness of the silica layer on the silicon substrate can be reduced to less than Embodiment 1. Further, to reduce the axis deviation between the active layer of the optical device and the core of the optical waveguide, the total thickness H of the silica layer must be less than 120 µm. As described above, in the silica-based optical waveguide of Figs. 25 and 26, it has been found that, to satisfy the high-frequency electrical wiring function and the high precision optical bench function for mounting the optical device, the under-clad thickness h of the silica-based optical waveguide must be more than 20 µm. Further, when an optical device of 4-array or more is mounted in 400 µm pitch, a condition is added that the total thickness H of the silica-based optical waveguide must be less than 120 µm. As can be seen from Table 3 and Table 4, an example using a discrete LD module as an optical device using a substrate in which under-clad h = 30µm, core diameter = 6 × 6µm, over-clad thickness = 30µm, and the entire silica layer of 66µm is shown in Fig. 25, which is considered to be optimum as a low loss silica-based optical waveguide. As described above, the hybrid optical integrated substrate of Embodiment 5 satisfies not only the proven low loss optical waveguide function, but also the high-frequency wiring function for driving the optical device and the high precision optical bench function for ensuring the flatness of the substrate. Further, as compared with Embodiment 1, the present embodiment uses an under-clad of 30 µm thick which has been proven as optical waveguide, and does not use a guide post or the like, thereby simplifying the electrode structure. Therefore, the high-frequency characteristics are improved and the packaging work has been simplified. Transmission loss of the optical waveguide of the hybrid optical integrated circuit was less than 1 dB/cm. Further, when LD is used as an optical device, good characteristics are shown in high-speed modulation at 10 GHz. Embodiment 5 Fig. 27 is a schematic view showing a sixth embodiment of the hybrid optical integrated circuit of the present invention. The present embodiment uses the silicon substrate 1 having protrusion and recess in place of the flat silicon substrate 1 used in Embodiment 4. The under-cladding layer 60c of the silica-based optical waveguide is formed in the recess of the silicon substrate 1, and protrusions 68a and 68b of the silicon substrate are exposed to an optical device mounting part 68 as shown, which can be used as a height reference surface when mounting the optical device 62. The B-B cross section in Fig. 27 is the same in structure as in Fig. 26, wherein the under-cladding layer 60c of thickness h = 30µm which is optimized in Table 3 and Table 4. A C-C cross sectional view in the optical device mounting part 68 is shown in Fig. 28. On the protrusion 68a of the silicon substrate 1, a thin electrode 62c is formed separately from the active layer 62a of the optical device 62, which functions as the height reference surface and an electrode of the optical device 62. The coplanar line uses a 5µm thick gold plating layer on the under-clad, but uses a gold spatter film of less than 1µm in thickness on silicon terraces 68a and 68b. The electrode 62b on the backside of the optical device 62 is held by the silicon sub-carrier, and electrically connected to the electrode 61b on the silicon terrace 68b through the conductive layer 67a on the surface of the silicon sub-carrier 67a and a conductive bonding material 69. Using the silicon substrate having the protrusion, the silicon protrusion 68a can be used as the mounting height reference surface, and positioning of the optical device 62 and the optical waveguide core 62a can be made with even higher precision. Heat generated in the optical device 62 can be dissipated to heat conductive silicon substrate 1 through the sub-carrier 67 and 68b and, since the substrate 1 is closely contacted to a highly heat conductive package 70, heat dissipation of the optical device 62 is remarkably improved. High-frequency characteristics in the coplanar line 14 are also good as in Embodiment 4. Although the high-frequency line is located immediately above the electrode on the silicon terraces 68a and 68b, the distance flowing high-frequency is actually very short, and the loss is very small. The thickness H including the under-clad 60c, the core 60b, and the over-clad 60a uses 66 µm optimized in Table 4, which is a good optical bench with reduced warping. Embodiment 6 Fig. 29 is a schematic perspective view showing a seventh embodiment of the hybrid optical integrated circuit of the present invention. The present embodiment uses an LD 71 as the optical device 62 of Embodiment 6, and further an LD driver 72 for driving the LD is mounted on the same substrate 1. The optical device mounting part 68 is the same in structure as in Fig. 27. The input side coplanar like 61b to the LD driver is the same in structure as the coplanar line 61 in Fig. 27. However, the coplanar line 61a connecting the LD driver 72 and the LD 71 is inserted with a high-frequency chip resistor 73 for impedance matching of the 50-ohm coplanar line with the LD. An E-E cross sectional view of the LD driver 72 is shown in Fig. 30. As shown, the LD driver 72 is placed on a protrusion 74 of the silicon substrate in order to efficiently dissipate heat of the LD driver 72 which has high heat evolution. As in Embodiment 5, heat of the LD is efficiently absorbed by the silicon substrate. By contacting the entire LD module closely with a package of highly heat conductive material, heat can be efficiently dissipated. Connection between the LD driver 72 and the coplanar line 61a and between the LD driver 72 and a DC bias line 61c, as shown in Fig. 30, is made using a guide post 65c and a gold ribbon wire 64 to reduce loss of the high-frequency components to a minimum. Since the silicon protrusion 74 contacts only the bottom surface of the driver, and separates from the coplanar line, the high-frequency characteristics are not deteriorated. Transmission loss of the optical waveguide of the hybrid optical integrated circuit was less than 1 dB/cm. Further, by inputting a 10 GHz modulation signal from a coplanar line input end 75 to the LD driver 72 and adjusting the amplitude and modulation potential by the DC bias line 61c, the LD device showed good modulation characteristics up to 10 GHz. As described above, by utilizing the low-loss optical waveguide function, high-frequency electrical wiring function, and high precision optical bench function of the hybrid optical integrated substrate of the present embodiment, such a high-speed LD module can be achieved on the same substrate of several cm square. Embodiment 7 Fig. 31 is a schematic perspective view showing an eighth embodiment of the hybrid optical integrated substrate of the present invention. The present embodiment has the same construction for the silica-based optical waveguide, the optical device mounting part 13, the coplanar wiring parts 61a and 61b, and the LD driver mounting part 61c. However, the silicon substrate 1 is extended to form a guide groove 77 so that a fiber 76 can be connected on an end face 62d of the silica-based optical waveguide without core adjustment. An X-X cross sectional view of the guide groove 77 is shown in Fig. 32. The guide groove 77 can be easily formed by etching the optical waveguide and the silicon substrate. By the guide groove 77, the optical fiber 76 can be easily connected to the optical waveguide core 62b without core adjustment, thereby even further expanding application of the hybrid optical integrated substrate. Embodiment 8 Fig. 33 is a schematic perspective view showing a ninth embodiment of the hybrid optical integrated circuit of the present invention. In the present embodiment, portions other than the silica-based optical waveguide have the same construction as Embodiment 4, and the silica-based optical waveguide is changed from the embedded type to the ridge type. In association with the change, only the thickness of the over-clad 62a is the same as that of a ridge type optical waveguide 78 and is thus small. As previously described, the ridge type optical waveguide is slightly inferior in characteristics to the embedded type but, for other points, functions as a good packaged substrate for hybrid optical integration. Embodiment 9 A tenth embodiment (not shown) is the same as Embodiment 4 shown in Fig. 20, except for the optical device mounting part 3, in which the optical device mounting part 63 is changed to an optical device mounting part 68 using the silicon terrace as shown in Fig. 27. Compared with Embodiment 4, good characteristics are maintained in terms of the optical waveguide function and the electrical wiring function as in Embodiment 4 and, as described in Embodiment 6, the silicon terrace can also be used as a height reference surface of optical device mounting, and heat dissipation is improved. Embodiment 10 Fig. 34 is a schematic perspective view showing an eleventh embodiment of the hybrid optical integrated circuit of the present invention. The present embodiment is the same in structure as Embodiment 5 shown in Fig. 25 except for the silica-based optical waveguides 60a and 60b, and the embedded type optical waveguides 60a and 60b are changed to ridge type optical waveguides 78a, 78b, and 78c. As previously described, the ridge type optical waveguide is slightly inferior to the embedded type optical waveguide in optical waveguide characteristics, but Embodiment 11 functions as a good packaged substrate for hybrid integration as in Embodiment 5 in terms of the high-frequency electrical wiring function and the optical bench function. Embodiment 11 Fig. 35 is a schematic perspective view showing a twelfth embodiment of the hybrid optical integrated circuit of the present invention. The present embodiment is the same in structure as Embodiment 6 shown in Fig. 27 except for the silica-based optical waveguides 60a and 60b, and the embedded type optical waveguides 60a and 60b are changed to ridge type optical waveguides 78a, 78b, and 78c. As previously described, the ridge type optical waveguide is slightly inferior to the embedded type optical waveguide in optical waveguide characteristics, but Embodiment 12 functions as a good packaged substrate for hybrid integration as in Embodiment 6 in terms of the high-frequency electrical wiring function and the optical bench function. As described above, in the hybrid optical integrated packaged substrate of the above embodiment, the disadvantage of high dielectric loss at high frequencies of the silicon substrate proven as a low loss silica-based optical waveguide substrate is solved by using a silica-based buffer layer with an appropriate thickness and, in view of the high precision optical bench function, the thickness of the silica-based optical waveguide is optimized so that warping of the substrate is reduced to the extent that coupling loss is not increased due to axis deviation relative to the optical waveguide even when an arrayed optical device is mounted. Therefore, an active device can be mounted to the optical waveguide with good precision, and it can used as an opto-electronic packaged substrate or a platform which operates with improved high-frequency characteristics. The high-frequency electrical characteristics are even further improved by enhancing the resistivity of the silicon substrate, and sufficiently good high-frequency characteristics can be maintained even though the thickness of silica layer between the coplanar line and the silicon substrate. Therefore, it is also possible to use the under-cladding layer of about 30µm in thickness which is proven as an optical waveguide, and use a structure where the coplanar line is lower than the core layer, thereby expanding the application. Further, by using the silicon substrate with protrusion and recess, forming the under-cladding layer of the silica-based optical waveguide is formed in the recess, and the protrusion is exposed in the optical device mounting part and used as a height reference surface, thereby providing an even higher precision optical bench function. In this structure, the highly heat conductive silicon substrate can be utilized as a heat dissipation plate for the optical device and its driving IC through the silicon terrace. By forming a fiber guide groove in the silicon substrate, it is possible to connect the fiber to the silica-based optical waveguide without core adjustment. Embodiment 12 Fig. 36 is a schematic cross sectional view showing a thirteenth embodiment of the opto-electronic hybrid optical integrated circuit of the present invention. The reference numeral 1 indicates a silicon substrate having a resistivity of 100 ohm-cm. In the optical waveguide section, a silica-based optical waveguide 2 is formed in the recess provided on the substrate surface. The under clad has a thickness of 30µm, the core is 6µm thick, and the over-clad is 30µm thick. A dielectric layer 50 comprising the same material as the silica-based under-cladding layer is formed in the silicon recess of the electrical wiring part. Thickness of the dielectric layer 50 between the optical device silicon terrace 30 and the electronic circuit terrace 35 is 20µm, and a 5µm thick conductor pattern 51 is formed on top. Thin film electrodes 52 are formed on the upper surface of the optical device silicon terrace 30 and the inclined side surface, and electrically connected to the conductor pattern 51. The optical active device 37 is mounted upside down on the silicon terrace 30 while maintaining electrical connection with the thin film electrode 52. The electronic circuit 38 is mounted on the silicon terrace 30 with the device surface facing down, and fixed with the conductor pattern 51 with a 5 µm high solder bump 53. In the electrical wiring part on the right of the electronic circuit, a second dielectric layer 52c is stacked on the dielectric layer 50 comprising the silica-based optical waveguide under-cladding layer. A multilayered conductor pattern 510 is provided in the second dielectric layer 52c, and a conductor pattern 51b is provided on the surface. In the present embodiment, the dielectric layer of the electric wiring part is the dielectric layer 50 comprising the same material as the silica-based optical waveguide, the second dielectric layer 52c comprising polyimide is provided in part of the dielectric layer, and the multilayered electrical wiring 510 is provided inside. With this construction, the optical device of low wiring density and the electronic circuit are connected with the high-speed coplanar line, and the electronic circuit of high wiring density can be wired using a multilayered microstrip wiring. Further, in the present embodiment, the coplanar wiring area and the microstrip wiring area use the under-clad layer of the optical waveguide for the first dielectric layer. As a result, compared with Embodiment 2 for achieving the same object as the present embodiment, fabrication process of the packaged substrate can be simplified. Embodiment 13 Fig. 37 is a schematic cross sectional view showing a fourteenth embodiment of the hybrid optical integrated circuit of the present invention. The substrate 1 in the present embodiment is a ceramic substrate, and the optical device silicon terrace 30 and the electronic circuit silicon terrace 35 are provided on top. The optical waveguide 40 is a silica-based optical waveguide. The dielectric layer 50 of the electrical wiring part is formed of polyimide. The present embodiment is characterized in that not only the conductor pattern 51 is provided on the surface and inside the dielectric layer 50 of the electrical wiring part, but also an electrical wiring 530 is provided in the ceramic substrate. In the present embodiment, silicon terrace with high thermal conductivity is used for the device mounting part, a silica-based optical waveguide is used as the optical waveguide, in the electrical wiring part, conductor patterns are provided inside and on the surface of the dielectric layer on the substrate, and a conductor pattern is provided also in the ceramic substrate which is easy to provide a multilayered electrical wiring. As a result, the packaged substrate of the present embodiment has a high-performance optical waveguide function, the silicon bench function, and the high-frequency electrical wiring function, and a very high density electrical wiring can be formed. To provide a silicon terrace on a substrate of different material such as ceramic, for example, an anodic bonding technique can be used. In this technique, a thin SiO 2 film is previously formed on the surface of the ceramic substrate and backside of the silicon terrace, and both are heated to join.

Claims: An opto-electronic hybrid packaged platform, comprising: an optical waveguide ( 31; 40, 41-43 ) having a core ( 42 ) and being arranged on an optical waveguide part; an optical device mounting part ( 30; 52; 52a, 52b ); and an electrical wiring part ( 50, 51a, 51b, 35, 53; 50, 51; 510; 53 ) said three parts being provided on a same substrate ( 1 ), wherein said optical device mounting part has a first silicon terrace ( 30 ) for mounting an optical device ( 37; 37, 44 ), said first silicon terrace being provided as a protrusion with reference to the adjacent surfaces of the substrate ( 1 ); said optical waveguide being formed on the substrate with a height so that the bottom of the core ( 42 ) of said optical waveguide is above an upper surface of the first silicon terrace; and said electrical wiring part has a dielectric layer ( 50 ) being formed on a surface of the substrate said surface forming a reference surface, and a conductor pattern ( 51; 51, 510 ) being formed on a surface of said dielectric layer ( 50 ), wherein said first silicon terrace ( 30 ) has a side surface including an inclination angle to the upper surface of said first silicon terrace; at least in the vicinity of said first silicon terrace, with reference to said reference surface, a height of an upper surface of the conductor pattern ( 51 ) formed on said dielectric layer ( 50 ) is set lower than an upper surface of said first silicon terrace ( 30 ), wherein a part of the inclined side surface of said first silicon terrace is exposed, wherein a portion of a thin film electrode ( 52 ) is formed on the exposed part of the inclined side surface of said first silicon terrace, a further portion of said thin film electrode ( 52 ) being disposed on the upper surface of said first silicon terrace and electrically connected to said conductor pattern ( 51 ) formed on the upper surface of said dielectric layer ( 50 ) through said conductor pattern on the inclined side surface of said first silicon terrace. A platform as claimed in claim 1, further comprising an electrical wiring layer ( 510 ) being formed within said dielectric layer ( 50 ) formed on the reference surface of said substrate. A platform as claimed in claim 1, wherein the substrate ( 1 ) is made of silicon material; the optical waveguide part ( 40 ) and the dielectric layer ( 50 ) of the electrical wiring part formed on the reference surface of the silicon substrate includes an optical waveguide made of dielectric material prepared by the steps of forming an under-clad ( 41 ), a core pattern ( 42 ) and an over-clad ( 43 ) on the substrate ( 1 ) in that order and then patterning the dielectric layer of the electrical wiring part, the dielectric layer of the electrical wiring part in the vicinity of the silicon terrace ( 30, 35 ) being constituted by a part of the under-clad ( 41 ) of the dielectric optical waveguide. A platform as claimed in claim 3, wherein said dielectric optical waveguide ( 40 ) is a silica-based optical waveguide. A platform as claimed in claim 3, wherein an additional silicon terrace is arranged in the vicinity of the other end of the optical waveguide, opposite to the optical device mounting part, and a positioning groove ( 77 ) for aligning an optical fiber ( 76 ) is formed on the additional silicon terrace. A platform as claimed in claim 4, further comprising a second dielectric layer ( 520 ) arranged on the under-clad ( 50 ) of the electrical wiring part, an electrical wiring layer ( 51b, 510 ) being formed on or within a surface of the second dielectric layer, wherein the electrical wiring layer of the second dielectric layer is electrically connected with an electrical wiring ( 51 ) formed on or within the surface of the second dielectric layer. A platform as claimed in claim 1, wherein an electrical wiring ( 510 ) is formed on the substrate ( 1 ), and the electrical wiring is electrically connected ( 520 ) with the electrical wiring ( 51, 51b ) arranged on or within the surface of the dielectric layer ( 50 ). A platform as claimed in claim 1, further comprising a second silicon terrace ( 35 ) for mounting an electronic circuit ( 38 ) arranged on the electrical wiring part, wherein, with reference to the reference surface of the substrate, a height of the upper surface of the second silicon terrace ( 35 ) is higher than the upper surface of the dielectric layer ( 50 ) in the vicinity of the second silicon terrace. A platform as claimed in claim 8, further comprising an electrode ( 53 ) for connecting with the electronic circuit arranged on the dielectric layer in the vicinity of the silicon terrace for the electronic circuit. A platform as claimed in claim 3, wherein a dielectric layer ( 60 ) is formed in the electrical wiring part at a position which is remote from said silicon terrace ( 35 ), such that a height of the dielectric layer is substantially flush to a surface of said over-clad ( 60a ) of said optical waveguide. A platform as claimed in claim 3, wherein said dielectric layer ( 50 ) has a thickness of 50 µm or more regardless of an average resistivity of said silicon substrate. A platform as claimed in claim 3, wherein said dielectric layer has a thickness of 20 µm or more and said silicon substrate has an average resistivity of 50 ohm-cm or more. A platform as claimed in claim 4, wherein said silica-based optical waveguide has a total thickness ( H ) of 120 µm or less. A method for producing a packaging platform according to claims 1 to 13, comprising the steps of: forming a protrusion defining a terrace ( 30, 35 ) having a desired shape on a desired position of a substrate ( 1 ) made of silicon material by a wet etching process; forming an under-clad ( 41, 50 ) of a dielectric optical waveguide ( 40 ) and then flattening the upper surface of said under-clad to be flush with the upper surface of the protrusion terrace; forming a core pattern ( 42 ) and an over-clad ( 43 ) in the order on the under-clad ( 41 ); removing all of the over-clad and the core pattern, and a part of the under-clad in an optical device mounting part ( 52; 52a, 52b ) including a desired part of an electrical wiring part ( 35, 50, 51, 53 ) and the area of the silicon terrace ( 30, 35 ) to expose all of the upper surface and a part of an inclined side surface of the silicon terrace and to reduce, the height of the surface of the under-clad ( 50 ) in a desired portion of the electrical wiring part so as to be lower than the upper surface of the silicon terrace ( 30, 35 ) by a desired height; and forming an electrical wiring pattern ( 51, 53 ) in the electrical wiring part to form an electrical wiring pattern ( 51 ) on the under-clad ( 50 ) and simultaneously to form an electrical wiring pattern ( 52 ) on the exposed part of the inclined side surface and the upper surface of the silicon terrace ( 30 ), wherein the electrical wiring pattern ( 51 ) formed on the under-clad ( 50 ) and the electrical wiring pattern ( 52 ) formed on the silicon terrace ( 30 ) are electrically connected. An opto-electronic hybrid integrated circuit, comprising a platform recited in any one of claims 1 to 13. An opto-electronic hybrid integrated circuit as claimed in claim 15, wherein an area of the upper surface of the silicon terrace for mounting an optical device ( 30 ) is equal to or less than an area of the optical device ( 37 ) mounted on the silicon terrace. An opto-electronic hybrid integrated circuit as claimed in claim 15, wherein an optical device ( 37 ) is facedown mounted on the silicon terrace ( 30 ) for mounting the optical device, the optical device being electrically connected and fixed with an electrode pattern ( 52 ) for joining with an optical device by a thin film solder, and wherein an electronic circuit ( 38 ) is mounted on the silicon terrace ( 35 ), the optical device being electrically connected with the electrical wiring ( 51 ) arranged on the dielectric layer ( 50 ) through a thick film conductive material.

Inventors: HASHIMOTO TOSHIKAZU, KATO KUNIHARU, MINO SHINJI, MORIWAKI KAZUYUKI, OGAWA IKUO, SUGITA AKIO, TERUI HIROSHI, YAMADA YASUFUMI, YANAGISAWA MASAHIRO, YOSHINO KAORU, HASHIMOTO, TOSHIKAZU, KATO, KUNIHARU, MINO, SHINJI, MORIWAKI, KAZUYUKI, OGAWA, IKUO, SUGITA, AKIO, TERUI, HIROSHI, YAMADA, YASUFUMI, YANAGISAWA, MASAHIRO, YOSHINO, KAORU
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1994
Main classification: G02B6
IPC codes: G02B6, H01S5