DIFFERENTIAL COMPARATOR WITH ADJUSTABLE THRESHOLD AND TRACKING HYSTERESIS

Abstract: An improved programmable comparator circuit having a pair of differential inputs (VN, VP), that will, through respective identical resistor networks (16, 30, 17, 31), turn on a first current switch (22, 23) for comparing the differential of the inputs to a threshold voltage. The threshold voltage is established by the voltage created when a selected current is drawn through one of said resistor networks, such that a bias current, through one of the transistors forming the first current switch, and through a second current switch (12, 13) establishes a hysteresis current through one of the transistors forming the second current switch. Positive feed back means (28, 29, D1-D4) coupled to the output of said first current switch (22, 23) control the second current switch (12, 13).

Description: DIFFERENTIAL COMPARATOR WITH ADJUSTABLE THRESHOLD AND TRACKING HYSTERESIS FIELD OF THE INVENTION This invention generally relates to differential comparators and more particularly to a differential comparator that will make a decisive comparison of analog differential signals to an arbitrary threshold with an indication of whether the differential input is greater than or less than the threshold. BACKGROUND OF THE INVENTION In analog signal processing, it is often required to be able to determine whether or not a signal exceeds a specified level or threshold. A high gain differential amplifier with no negative feedback can be used as a comparator to achieve this by connecting the positive input to the input signal and the negative input to the desired threshold. In many analog systems, the input signals are made differential for the purpose of rejecting noise that appears on the inputs with respect to a reference potential, e.g., ground. Hence a comparator the can directly handle a differential input signal is desirable. In an analog system, such as a high performance, hard disk drive read channel, the threshold is not fixed but rather changes as the average amplitude of the input signal changes. These changes occur because of temporal and positional variations in the read head, the magnetic medium, and etcetera. Differential signals are used in such a system for the reasons noted above. Hence a different comparator with an adjustable threshold is desirable. Furthermore, the digital logic that is required to process the output of such comparators requires a firm signal at the comparator output. If the comparator output hangs in the middle of two logic levels or if it switches rapidly between the logic levels the digital logic cannot interpret the output. This problem is especially prevalent when the input signal is close to the threshold voltage of the comparator. The industry presently desires a comparator circuit in which all the above describe problems are avoided. Because the presently available comparators lack these desirable features there exists a need for a comparator that can not only directly handle a differential input signal but that has an adjustable threshold. SUMMARY OF THE INVENTION Accordingly, the present invention, provides a differential comparator which is provided with an adjustable threshold and a hysteresis that tracks the threshold as it is adjusted. The present invention is a programmable comparator circuit having a pair of differential inputs coupled through respective identical resistor networks, to turn on an active device in a first current switch. Turning on this device in the current switch permits the comparison of the differential of the inputs to a threshold voltage established by a selected value of current through a respective one of the resistor networks. This establishes a bias current through one of the transistors forming the first current switch, and through a second current switch for turning on the second switch and thus establishing a hysteresis current through one of the transistors forming the second current switch. By providing positive feed back means from the output of said first current switch control of the second current switch is assured. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simple embodiment of the present invention in schematic form. Fig. 2 is the preferred embodiment of the present invention in schematic form. DESCRIPTION QF THE PREFERRED EMBODIMENT Referring to the drawing and especially Fig. 1 , there is shown a simple embodiment of the comparator circuit of the present invention in schematic form. This schematic sets forth the comparator circuit 10 of the invention and includes a hysteresis switch 1 1 comprised of a pair of NPN, bipolar, emitter coupled transistors 12 and 13 whose emitters are coupled to ground 14 through a hysteresis current source 15. The collectors of transistors 12 and 13 are respectively coupled, through respective hysteresis resistors 16 and 17, to respective differential inputs 18 and 19 and their bases are respectively coupled to the outputs 20 and 21 through respective diode pairs Dl, D2 and D3, D4. The circuit 10 further includes a second emitter coupled switch formed of a pair of NPN, bipolar, emitter coupled, main amplifier transistors 22 and 23. The 9042 PCIYUS94/14459 4 emitters of these main amplifier transistors 22 and 23 are coupled to ground 14 through a bias current source 24. The collectors of these amplifier transistors 22 and 23 are respectively coupled to a supply voltage V DD through respective current resistors 26 and 27 and to the bases of respective output NPN, bipolar, drive transistors 28 and 29. The bases of the main amplifier transistors 22 and 23 are respectively connected through respective threshold resistors 30 and 31 to the collectors of the switching transistors 12 and 13. The base of amplifier transistor 23 is further coupled to ground 14 through a threshold current source 33. The output drive transistors 28 and 29 have their collectors coupled to the voltage source V DD and have their emitters respectively coupled to the respective outputs 20 and 21 and thence through the respective diode pairs Dl, D2 and D3, D4 to the bases of the respective switch transistors 12 and 13. The described circuit operates as follows. It will be assumed that varying differential input voltage signals are respectively applied to the inputs 18 and 19. For purposes of this description, it will be assumed that initially the voltage of the signal applied to the input 18 is much higher than the voltage of the signal applied to the input 19. The higher voltage applied to input 18 causes the amplifier transistor 22 to turn on to permit current to flow from the voltage source V DD through the current resistor 26, the transistor 22, and the current source 24 to ground 14. When transistor 22 turns on the voltage applied the base of the drive transistor 28 is lowered. Since transistor 28 operates as an emitter follower, the lowering of its base voltage also lowers the voltage at its emitter and at base of transistor 12 and transistor 12 is held off. Simultaneously, the transistor 23 is held off by the lower input voltage applied to its base from input 19. Because transistor 23 is off the voltage applied to the base of the drive transistor 29 remains high, transistor 13 remains on and current flows from the input 19 through the hysteresis resistor 17, the transistor 13 and the hysteresis current source 15 to ground. It should be noted that the threshold current source 33 continues, under all circuit conditions to draw a constant current from the input 19 through both the hysteresis resistor 17 and the threshold resistor 31. As the applied input voltage signals change, the difference therebetween decreases and, as the voltage difference between the two inputs approaches the total voltage across threshold resistor 31 and hysteresis resistor 17, both of the main amplifier transistors 22 and 23 begin to conduct and the amplifier enters its linear mode. With the main amplifier in its linear mode, the hysteresis switch, comprised of transistors 12 and 13, also enters its linear mode because of the feedback loops between the collectors of the hysteresis switch transistors 12 and 13 and the bases of the respective amplifier transistors 22 and 23 to which each of said collectors is respectively coupled. These feedbacks between transistors 12 and 22 and between transistors 13 and 23 are positive and cause the entire network to switch when the feedback loops reach unity gain. This occurs approximately at the point at which the voltages applied to the bases of the transistors 22 and 23 become equal. When the differential voltages applied to the inputs 18 and 19 continue to change, i.e., input 19 becomes more positive than input 18 plus the total voltage across the threshold resistor 31 and the hysteresis resistor 17, the amplifier transistor 23 turns on more fully and the transistor 22 turns off. Now the current flowing, from V DD through the bias current source 24 to ground 14, switches to flow from V DD through the current resistor 27, the transistor 23, and the source 24 to ground 14. With the turning on of transistor 23 the voltage applied the base of the drive transistor 29 is lowered. Since transistor 29 operates as an emitter follower, the lowering of its base voltage also lowers the voltage at its emitter and at the base of transistor 13 and transistor 13 turns off. With transistor 22 now off the voltage applied to the base of the drive transistor 29 goes high turning on transistor 12 and current now flows from the input 18 through hysteresis resistor 16, transistor 12 and the hysteresis current source 15 to ground. It should be noted that the threshold current source 33 continues, under all circuit conditions to draw a constant current from the source 19 through both the hysteresis resistor 17 and the threshold resistor 31. If the input voltage VP, at input 19, now decreases with respect to the input voltage VN, at input 18, the circuit will eventually return to the initial state previously described. However the threshold voltage at which this occurs is different from that at which the circuit switched from the initial state. This is due to the current I H now flowing through the hysteresis resistor 16 rather than through the hysteresis resistor 17. This causes the base of amplifier transistor 22 to be at a voltage I H R H below the input voltage VN, while the base of amplifier transistor 23 is at I T (R H + R τ ) below the input voltage VP. The switch point from this state also occurs when these base voltages are approximately equal, or where (VP - VN) = I T (R H + R T ) - I H R H . This contrasts with a switch point at (VP - VN) = I T (R H + R T ) + I„R H from the initial state described above. Thus there has been taught a comparator circuit in which a decisive comparison of analog differential signals to an arbitrary threshold level can be made. Also the circuit permits the logical indication of whether the differential input is greater than (logical 1 output) or less than (logical 0 output) the threshold. It can be readily demonstrated that the comparator has switch points at a voltage equal to the current flow I H through in the hysteresis current source 15 and the hysteresis resistor (R„) 16 i.e., I H R H above and below a threshold I T (R H + R τ ) results in a hysteresis width of 2I H R H . This means the hysteresis of the comparator can be set independently of the threshold voltage or can be set to track the threshold voltage by simply choosing the appropriate values of I τ , I H , R τ , and I Analysis of the circuit will readily show that by meeting the following criteria the comparator threshold will be proportional to the externally supplied voltage V JH and the hysteresis will be αV^ where α is desired constant of proportionality between the threshold and the hysteresis. The preferred embodiment of the comparator is shown in Fig. 2. In this Fig. 2, the comparator circuit of the invention includes a hysteresis current switch comprised of a pair of NPN, bipolar, emitter coupled transistors 112 and 113 whose emitters are coupled to ground 114 through a hysteresis current source 115. The collectors of transistors 112 and 113 are respectively coupled through respective hysteresis resistors 116 and 117 to the emitters of a pair of NPN, bipolar, emitter follower transistors 140 and 141. Thus the collector of transistor 112 is connected to the emitter of emitter follower transistor 140 and the collector of auxiliary switch transistor 113 is coupled to the emitter of emitter follower transistor 141. Respective differential inputs 1 18 and 119 are respectively coupled to the bases of these emitter follower transistors 140 and 141. The bases of the switching transistors 112 and 1 13 are respectively coupled to the outputs 120 and 121 through respective diode pairs D7, D8, and D13, D14. An auxiliary emitter coupled current switch is formed of NPN, bipolar transistors 142 and 143, whose bases are coupled in common with the bases of the switching transistors 112 and 113. This auxiliary current switch is also coupled between the emitter follower transistors 140 and 141 and ground 114. More specifically the emitters of the auxiliary transistors 142 and 143 are coupled through a separate current source 115a to ground 114 and their collectors are cross-coupled to the respective emitters of the emitter follower transistors 140 and 141. Thus the collector of transistor 142 is connected to the emitter of emitter follower transistor 141 and the collector of auxiliary switch transistor 143 is coupled to the emitter of emitter follower transistor 140. In a manner similar that shown in Fig. 1 the circuit shown in Fig. 2 further includes a pair of NPN, bipolar, emitter coupled, main amplifier transistors 122 and 123. The emitters of these main amplifier transistors 122 and 123 are coupled to ground 114 through a bias current source 124. The collectors of these amplifier transistors 122 and 123 are respectively coupled to a supply voltage V DD through respective current resistors 126 and 127 and to the bases of respective output drive NPN, bipolar, transistors 128 and 129. The bases of the main amplifier transistors 122 and 123 are respectively connected through respective threshold resistors 130 and 131 to the collectors of the switching transistors 112 and 1 13. The base of amplifier transistor 123 is further coupled to ground 114 through a threshold current source 133. The output drive transistors 128 and 129 have their collectors coupled to the voltage source V DD and have their emitters respectively coupled to the respective outputs 120 and 121 and thence through the respective diode pairs D7, D8 and D13, D14 to the bases of the respective switch transistors 112 and 1 13. The addition of the emitter follower transistors 140 and 141 and the auxiliary current switch formed of transistors 142 and 143 significantly improve the operation of the comparator circuit of the present invention. By buffering the input voltages V P and V N with the emitter follower transistors 140 and 141, the effective load on the circuit driving these points is reduced. Addition of the these devices also results in a level shift of the base to emitter voltage V^ and any base to emitter voltage V f c mismatch between the two follower transistors 140 and 141 manifests itselfas an offset from the threshold voltage. The minimum V ta difference will occur if the currents through the two devices are kept equal. The currents through the emitter follower transistors 140 and 141 can be made to be constant under all operating conditions by selectively setting the bias current levels passing through the second and third current switches i.e., the current switches respectively formed of transistors 124 and 133 and transistors 142 and 143. By cross coupling the collectors of the auxiliary current switch transistors 142 and 143 as above described, the extra hysteresis current I H through the current source 115a is steered by the emitter follower transistor that is driving the main amplifier transistor that is on. This current is selected to assure that when all bias and base currents flowing in the circuit are accounted for, the total current in follower transistors 140 and 141 will be precisely equal. In the actual circuit built the threshold voltage was 80% of the voltage difference between the external threshold voltage and the reference voltage and the actual width of the hysteresis was nominally 20% of the threshold voltage. Although the circuits were shown as being implemented using NPN bipolar transistors it should be noted that PNP bipolar transistors can be substituted with the proper voltage changes. Also field effect transistors (FETs) such as MOSFETSs can also be used but in using such FET devices the circuit speeds and accuracy may be reduced. The described invention thus teaches a fully differential comparator circuit SUBSTITUTE SHEETS 26) that compares a differential input to a predetermined threshold voltage that can be adjusted by changing the voltage on of the differential inputs to the circuit. The comparator of the invention further provides a hysteresis that tracks the threshold by a factor that is less than 1. This completes the description of the preferred embodiment of the invention. Since changes may be made in the above process without departing from the scope of the invention described herein, it is intended that all the matter contained in the above description or shown in the accompanying drawings shall be interpreted in an illustrative and not in a limiting sense. Thus other alternatives and modifications will now become apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.

Claims: What is claimed is: 1. A programmable comparator circuit comprising: a pair of differential inputs, each being coupled, through respective resistor networks, to a first current switch for turning on said first switch, to compare the differential voltage between said inputs to a threshold voltage established by the current through a selected one of said respective resistor networks, and establishing a bias current through one of the transistors forming said first current switch, and through a second current switch for turning on said second switch and establishing a hysteresis current through one of the transistors forming said second current switch; and positive feed back means coupled to the output of said first current switch to control said second current switch. S UBSTm.TESH-ET (B--E -6) 2. A programmable comparator circuit comprising: a pair of resistor networks, each comprising a threshold resistor and an hysteresis resistor; a pair of differential inputs, each being coupled, through respective resistor networks, to a first current switch, comprised of a first pair of transistors, for turning on said switch, to compare the differential voltage between said inputs to a threshold voltage established by the current through a selected one of said respective resistor networks, and establishing a bias current through one of the transistors forming said first current switch, and through a second current switch, comprised of a second pair of transistors, for turning on said switch and establishing a hysteresis current through one of the transistors forming said second current switch; and positive feed back means coupled to the output of said first current switch to control said second current switch to create a predictable hysteresis voltage equal to the voltage drop across the hysteresis resistor in said resistor network. 3. The circuit of claim 1 wherein there is further provided. a third current switch, comprised of a third pair of transistors; said differential inputs being respectively coupled through said third current switch transistors to a current source; and said positive feed back means are cross-coupled to control said transistors of said third current switch. SUBSTITUTESHEET IBULE 26) 4. A programmable comparator circuit comprising: a pair of differential inputs, each being coupled, through respective identical resistor networks, to a first current switch, comprised of a first pair of transistors, for turning on said switch, to compare the differential of said input to a threshold voltage established by a selected one of said input voltages across one of said respective resistor networks, and establishing a bias current through one of the transistors forming said first current switch, and through a second current switch, comprised of a second pair of transistors, for turning on said switch and establishing a hysteresis current through one of the transistors forming said second current switch; and positive feed back means coupled to the output of said first current switch to control said second current switch to create a predicable hysteresis equal to the voltage drop across the other of said resistor networks. SUBSTITUTE SHEET (RULE .3) 5. The circuit of claim 1 wherein there is further provided: a third current switch, comprised of a third pair of transistors; said differential inputs being respectively coupled through said third current switch transistors to ground; and said positive feed back means are cross-coupled to control said transistors of said third current switch. 6. The circuit of claim 1 wherein said transistors are bipolar transistors. 7. The circuit of claim 1 wherein said current switches each comprise a pair of emitter coupled NPN, bipolar transistors. 8. The programmable comparator circuit of claim 4 wherein: said respective identical resistor networks includes first and second resistors; said first current switch is comprised of a first pair of NPN bipolar emitter coupled transistors; said second current switch is comprised of a second pair of NPN bipolar transistors; and said positive feed back means coupled to the output of said first current switch to control said second current switch include said second resistor. 9. The programmable comparator circuit of claim 4 wherein: there is further provided a pair of emitter follower transistors, each of said follower transistors being respectively coupled between the first resistor in each said network and said inputs. 10. The programmable comparator circuit of claim 9 wherein: there is further provided a third current switch use outputs are respectively cross-coupled to a respective junction between each respective emitter follower transistor and said first resistor in each of said networks. 11. The circuit of claim 4 wherein the Hysteresis current is proportional to the threshold current. 12. The programmable comparator circuit of claim 10 wherein the bias current levels of said second and third current switches are set to provide a constant current in said emitter follower transistors S UBSTITUTESHEET (RULE -6) AMENDED CLAIMS [receiv3d by the International Bureau on 27 October 1995 (27. 10.95 ) ; original claim 1 amended ; remaining claims unchanged ( 1 page) ] 1. A programmable comparator circuit comprising: a pair of differential inputs, each being coupled, through respective resistor networks, each comprising two resistors, to a first current switch for turning on said first switch, to compare the differential voltage between said inputs to a threshold voltage established by the current through a selected one of said respective resistor networks, and establishing a bias current through one of the transistors forming said first current switch, and through a second current switch, comprising a pair of transistors, for turning on one of said transistors in said second switch and establishing a hysteresis current through said one of the transistors forming said second current switch; and positive feedback means coupled to both outputs of said first current switch to control said second current switch. Statement Under Article 19(1) Claim 1 is replaced by an amended claim bearing the same number. Copies of substitute page 11 containing revised claim 1 is attached. Claims 2 to 10 remain unchanged. Claim 1 has been amended by adding; in the second paragraph clarifying language. Specifically the words " each comprising two resistors," were added in the second and third lines and the words "comprising a pair of transistors," and the words "one of said transistors in"; were added in the ninth, tenth and eleventh lines of the first paragraph. Claim 1 was further amended by deleting the words " the output " in the first line of the second paragraph and substituting therefore the words " both outputs ". The International Search Report uncovered United States Patent 3,757,137 and deemed it to be of particular relevance because the claimed invention could not be considered novel when this reference is taken alone. The invention taught in the referenced patent USP 3,757,137 is to a reference circuit which relies on the fixed ratio of two resistors R and R', each of which is coupled in series with a respective diode string(Dl, D3, D5) and (D2, D4, D6), to establish a voltage drop. Thus in the cited reference the threshold is invariable and cannot be changed with out physically changing either the resistors R and R' or the number of the diodes in each string. Thus the threshold of the cited circuit is fixed at its time of manufacture. In contradistinction the circuit of the present invention as set forth in claim 1 above is programmable that is: the threshold is set by the values of one of the resistor networks which is fixed at its time of manufacture, times the value of the current I τ , which can be set by analog or digital control signal inputs, thereby permitting the threshold to be variable during normal operation of the circuit. Furthermore, the circuit of the cited reference has only one of its inputs coupled through a single resistor. Again the present invention is distinguishable from the referenced patent for the present claim 1 calls for each of its outputs being coupled to the transistors of the first current switch. Still further, The positive feedback of the cited reference is taken off the output of its second current switch and is used to control the first current switch. Still again the present claim 1 is distinguishable in that it call for the positive feedback to be coupled to the output of the first current switch to control the second current switch. The present invention as set out in claim 1 requires that its differential inputs each be coupled, through respective identical resistor networks, each of which comprise two resistors, to compare the differential voltage between said inputs to a threshold voltage established by the current in a selected one of said respective resistor networks, and establishing a bias current through one of the transistors forming the first current switch, and through a second current switch for turning on the second switch and establishing a hysteresis current through one of the transistors forming said second current switch. This configuration is quite different from that shown, taught or used by the referenced prior art patent. Because the present invention relies on identical resistor networks, i.e., each resistor network comprising resistors Rj, and R τ , in each leg of the current switch and there is a an additional current source I τ coupled to the base of one of the first current switch transistors, the circuit, of the present invention which permits the present invention to be adjustable during normal operation. The circuit shown in the cited reference USP 3,757,137 is not adjustable once manufactured. Furthermore the cited reference is only single ended (i.e., the collector of transistor 22 is coupled to a fixed potential) thus it throws away one half of its potential outputs. Accordingly, the cited reference cannot be considered as taking away the novelty of the claimed invention.

Inventors: BONACCIO ANTHONY R, BONACCIO, ANTHONY, R.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1994
Main classification: H03K3
IPC codes: H03K3, H03K5