Digital recording and reproducing

Abstract: A digital signal magnetic recording and reproducing apparatus comprises a coding portion 10 for convolutionally coding input digital data, a modulating portion 20 for quadrature-amplitude-modulating and phase-shift-keying-modulating the convolutionally coded digital data, a pilot signal mixer 30 for generating a pilot signal and adding it to the modulated signal, a recording controller 40 for forming a magnetized signal suitable for a magnetic recording medium 52 from the modulated signal mixed with the pilot signal, a reproducing controller 60 for outputting a digital signal of which the distortion and deterioration produced in a transmission system are corrected, from the magnetized signal reproduced from the magnetic recording medium 52, a carrier wave restoring portion 70 for generating a clock signal having the carrier signal frequency by detecting a pilot signal from the reproduced magnetized signal, a demodulating portion 80 for demodulating the quadrature-amplitude-modulated signal output from the reproducing controller and a decoding portion 100 for outputting original digital data by Viterbi-decoding convolutionally coded data from the demodulating portion 80. The apparatus increases frequency utilization efficiency by adopting a multiple valued digital modulation method, is effective in recording at high density and is characterized in that the overall signal processing is carried out digitally.

Description: The present invention relates to digital recording and reproducing, and is concerned particularly, although not exclusively, with digital signal magnetic recording and reproducing apparatus which can record and reproduce digital signals at high-density on a bandwidth-restricted channel in a digital video tape recorder or the like. As analog signals and circuits are being progressively replaced by digital signals and circuits, due to the continuing development of the related technology, various kinds of digital recording and reproducing methods have been provided. Although a digital signal magnetic recording and reproducing apparatus, which records and reproduces a digital image signal, is excellent in picture quality and dubbing performance in comparison with an analog magnetic recording and reproducing apparatus, which records and reproduces an analog image signal, the quantity of data to be recorded on a tape may be over ten times as large as that of an analog magnetic recording and reproducing apparatus, in recording the same image signal. In other words, by analog-to-digital conversion, the quantity of the signal data in a digital magnetic recording and reproducing apparatus is increased considerably. Accordingly, when a digital signal is recorded, the tape consumption is increased and it is difficult to record a great number of signals. Therefore, for the purpose of obtaining the same efficiency as that of an analog signal recording, it is necessary to increase recording efficiency by compressing data, modulating binary data to data of multiple-value level, recording the modulated data and improving bit error rate (BER) by increasing signal-to-noise ratio. Because of the difficulty of recording and reproducing direct current components using a recording and modulating method applicable to a conventional digital magnetic recording and reproducing apparatus, base band modulating methods such as a non return to zero inverse modulation (NRZI), partial response(PR) modulation, eight-to-fourteen modulation (EFM), etc. have been employed Such base band modulating methods convert the zero-run length of data rows to be expressed in a binary code and record the concentrated signal frequency to attain a high-density recording. However, the base band modulation method, in which the signal level to be recorded has only two potential values, makes high-density recording difficult because of a low coefficient of utilization of recording frequency bands. Because of increased tape consumption, long-duration recordings are also difficult. Therefore, as a channel coding technology suitable to a high-density recording is required, a modulation method which has been used in the communication field is changed and applied in a form suitable for recording and reproduction, thereby increasing a frequency utilization efficiency and accomplishing improvement of a recording bit rate without an increase in number of recording channels. Accordingly, a code modulation method which is performed by combining multiple value modulations and shows a high coefficient of utilization of frequency bands by an error control coding applicable to a digital data transmission has been proposed. Such a code modulation method which reduces bit error rate without increasing bandwidth has been used greatly in the communication field. Also, to realize a high-density recording, multiple value digital modulation methods such as quadrature amplitude modulation (QAM) and phase shift keying modulation (PSK), etc. used in the communication field have been introduced and, as a result, an increase of utilization efficiency of frequency bands has made high-density recording advantageous. A digital signal magnetic recording and reproducing apparatus, which uses multiple valued QAM modulation and maximum likelihood decoding is disclosed in U.S. Pat. No. 5,095,392. The digital signal magnetic recording and reproducing apparatus of US-A-5,095,392 performs a digital-to-analog conversion from the start, processes the converted signal, converts the processed signal into a multiple value signal at the time of encoding, records the converted multiple value signal, and decodes the signal by a maximum likelihood decoding after demodulating the signal recorded in an analog form and finally performs an analog-to-digital conversion. US-A-4,979,052 (Matsushita) discloses a digital signal magnetic recording and reproducing apparatus which likewise performs a digital-to-analog conversion from the start and applies multi-value QAM and bias records the multi-value QAM signal to improve linearity and signal to noise ratio. US-A-5,119,243 (also Matsushita) further discloses using a carrier frequency and clock frequency having an integer multiple relation where the carrier and clock are reproduced using a phase lock loop PLL and the clock phase is shifted before use in decoding the demodulated signal to prevent degradation of error rate. Also, a clock phase reference signal is periodically inserted in the recording signal to improve accuracy of adjustment of the clock phase. Preferred embodiments of the present invention aim to provide a digital signal magnetic recording and reproducing apparatus, which can improve recording efficiency by applying a multiple valued digital modulation method applicable to the communication field. Another aim is to provide a digital signal magnetic recording and reproducing apparatus, which can record signals in high-density using quadrature amplitude and modulation phase shift keying modulation at the time of magnetically recording and reproducing a digital signal. Still another aim is to provide a digital signal magnetic recording and reproducing apparatus, which processes an overall signal digitally by adopting a multiple value modulation method which possesses a low error rate and a high recording efficiency. A further aim is to provide a digital signal magnetic recording and reproducing apparatus, which reduces a bit error rate by inserting a synchronizing signal to an input digital signal and reconstructing the synchronizing signal efficiently. A still further aim is to provide a digital signal magnetic recording and reproducing apparatus, which modulates data by a carrier wave synchronized with data by generating the carrier wave using a system clock at the time of modulation and by generating a pilot signal for detecting the carrier wave synchronized at the time of demodulation. According to one aspect of the present invention, there is provided a digital signal magnetic recording and reproducing apparatus which modulates a digital image input signal, records the modulated signal on a magnetic medium, reads the signal recorded thereon and demodulates it to the original signal, said apparatus characterised by : coding means for converting an input digital image signal into a multiple valued digital signal; modulating means for digitally quadrature-amplitude-modulating and phase-shift-keying-modulating said multiple valued digital signal according to a carrier signal; pilot signal mixing means for generating a pilot signal and digitally mixing the pilot signal with said modulated signal; recording controlling means for forming a magnetized signal suitable for recording on a magnetic recording medium from the modulated signal mixed with said pilot signal; reproducing controlling means for outputting a digital signal of which the signal distortion and deterioration produced in a transmission system are corrected, from a magnetized signal reproduced from said magnetic recording medium; carrier wave restoring means for generating a clock signal having the carrier signal frequency by detecting a pilot signal from said reproduced magnetized signal; demodulating means for digitally demodulating the modulated signal output from said reproducing controlling means according to the carrier signal restored from said carrier wave restoring means; and decoding means for outputting original digital data by Viterbi-decoding convolutionally coded data from the output of said demodulating means. A digital signal magnetic recording and reproducing apparatus as above may further comprise noise eliminating means for restricting bands and decreasing clock frequencies to improve a signal-to-noise ratio of the output of said demodulating means. Preferably, said modulating means comprises: a first ROM in which a first carrier signal to be expressed in sine components is stored; a second ROM in which a second carrier signal to be expressed in cosine components is stored; a first multiplier for multiplying the first carrier signal output from said first ROM by the in-phase (I) channel data output from said coding means; a second multiplier for multiplying the second carrier signal output from said second ROM by the quadrature-phase (Q) channel data output from said coding means; and a first adder for adding the outputs of said first and second multipliers. Preferably, said modulating means comprises: first and second pulse shaping filters for wave-shaping and band-restricting of the I and Q channel data output from said coding means; a first carrier signal generator having a first ROM wherein a first carrier signal to be expressed in sine components is stored and a second ROM wherein a second carrier signal to be expressed in cosine components is stored; a first balanced-modulator having a first AND gate combination circuit for combining the I channel data output from said coding means with a first carrier signal output from said first ROM, a first adder combination circuit for adding the output of the first AND gate combination circuit and a first latch for temporarily storing the output of the first adder combination circuit; a second balanced-modulator having a second AND gate combination circuit for combining the Q channel data output from said coding means with a second carrier signal output from said second ROM, a second adder combination circuit for adding the output of the second AND gate combination circuit and a second latch for temporarily storing the output of the second adder combination circuit; and a first adder having a third adder combination circuit for adding the outputs of said first and second latches, that is, the modulated signal of the I channel and the modulated signal of the Q channel, and a third latch for temporarily storing the quadrature-amplitude-modulated signal which is the output of said third adder combination circuit. Preferably, said pilot signal mixing means comprises: a pilot signal generator for generating a pilot signal having a frequency equal to a predetermined number of times the frequency of the carrier signal; and a second adder for adding the pilot signal to the modulated data of said modulating means. Preferably, said recording controlling means comprises: a digital-to-analog (D/A) converter for converting the output of said pilot signal mixing means to an analog signal; a recording amplifier for amplifying the output of said D/A converter; a bias signal generator for generating a bias signal; and a third adder for adding the bias signal to the output of said recording amplifier. Preferably, said recording controlling means comprises: a digital-to-analog (D/A) converter for converting the output of said pilot signal mixing means into an analog signal; a bias signal generator for generating a bias signal to use a linear portion of a magnetized characteristic curve considering non-linear characteristics of a magnetic channel; and a third adder for adding the output of said D/A converter to the bias signal of said bias signal generator. Preferably, said reproducing controlling means comprises: a reproducing amplifier for amplifying a magnetized signal reproduced from said magnetic recording medium; a phase shifter for shifting the phase of the output of said reproducing amplifier to compensate a phase shift by the differential characteristics of a magnetic channel at the time of recording; a low-pass filter for filtering the reproduced signal from the output of said phase shifter; an analog-to-digital (A/D) converter for converting the output of said low-pass filter into a digital signal form; and a band-pass equalizer for receiving the output of said A/D converter and correcting signal distortion and deterioration produced in a transmission system. Preferably, said reproducing controlling means comprises: an analog-to-digital (A/D) converter for A/D converting the signal reproduced from said magnetic recording medium; and a reproducing equalizer for correcting both phase and amplitude attenuation of a reproduced signal due to a differential magnetic channel characteristic. Preferably, said carrier wave restoring means comprises: a band-pass filter for detecting a pilot signal from an output of said reproducing controlling means; and a phase locked loop (PLL) for generating a clock signal having a frequency corresponding to that of the carrier signal from the output of said band-pass filter. Preferably, said demodulating means comprises: a third ROM from which a first carrier signal to be expressed in sine components is read in accordance with a clock corresponding to said restored carrier signal; a fourth ROM from which a second carrier signal to be expressed in cosine components is read in accordance with a clock corresponding to said restored carrier signal; a third multiplier for multiplying the modulated signal output from said reproducing controlling means by the first carrier signal output from said third ROM; a fourth multiplier for multiplying the modulated signal output from said reproducing controlling means by the second carrier signal output from said fourth ROM; and a fourth adder for adding the outputs of said third and fourth multipliers. Preferably, said demodulating means comprises: a second carrier signal generator having a third ROM from which a first carrier signal to be expressed in sine components is read in accordance with a clock corresponding to said restored carrier signal and a fourth ROM from which a second carrier signal to be expressed in cosine components is read in accordance with a clock corresponding to said restored carrier signal; a third balanced-modulator having a fourth AND gate combination circuit for combining the modulated signal output from said reproducing controlling means with the first carrier signal output from said third ROM, a fourth adder combination circuit for adding the output of the fourth AND gate combination circuit and a fourth latch for temporarily storing the output of the fourth adder combination circuit; a fourth balanced-modulator having a fifth AND gate combination circuit for combining the modulated signal output from said reproducing controlling means with the second carrier signal output from said fourth ROM, a fifth adder combination circuit for adding the output of the fifth AND gate combination circuit and a fifth latch for temporarily storing the output of the fifth adder combination circuit; and first and second matching filters for restricting the output bands of said third and fourth balanced-modulators. Preferably, said noise eliminating means comprises: first and second decimators for decreasing a clock frequency to improve a signal-to-noise (S/N) ratio of the output of the first and second matching filters; first and second base-band equalizers for compensating the output signals of said first and second decimators; and third and fourth decimators for redecimating the outputs of said first and second base-band equalizers to decrease the clock frequency. Preferably, the digital signal magnetic recording and reproducing apparatus comprises : digital-to-analog (D/A) converting means for converting the modulated signal with which said pilot signal is mixed into an analog signal; bias signal generating means for generating a bias signal having a frequency more than a predetermined number of times the frequency of a carrier signal to be recorded using a linear portion on a magnetizing characteristic curve of a magnetic channel, combining the generated bias signal with the output of said D/A converting means and transmitting the result to said magnetic recording medium; analog-to-digital (A/D) converting means for outputting an analog magnetized signal reproduced from said magnetic recording medium as a digital signal form after correcting the signal distortion and deterioration of the signal, produced in the transmission system; Preferably, the digital signal magnetic recording and reproducing apparatus comprises: synchronizing signal inserting means for inserting a synchronizing signal to input digital data supplied to said coding means and outputting a synchronizing flag signal; synchronizing signal controlling means for controlling the coding of said coding means by receiving said synchronizing flag signal; synchronizing flag detecting means for restoring a synchronizing flag signal from said demodulated signal output by said demodulating means; and said decoding means for outputting original digital data by Viterbi-decoding convolutionally coded data from the output of said demodulating means in accordance with said synchronizing flag signal. Preferably, said coding means comprises: a buffer for temporarily storing part of the bits of data output from said synchronizing signal inserting means; a convolution encoder in which a coding gain and a bit error rate are considered from the data output from said synchronizing signal inserting means; and a mapper which sets the relationship between signal points through said convolution encoder so that a coding gain becomes large at the time of decoding. Preferably, the digital signal magnetic recording and reproducing apparatus, further comprises a selecting means for selectively outputting some of the bits of the signals output from said synchronizing signal inserting means to said mapper and the rest of the bits to said convolution encoder so as to be parallel shifted. Preferably, said mapper maps the synchronizing signal output from said synchronizing signal inserting means at the origin on a signal constellation diagram while said synchronizing flag signal is in "excited" level period. Preferably, said mapper is constituted by ROMs, and in the signal constellation, a parallel shifted portion among signals of said convolution encoder is set-partitioned farthest and a signal shifted in the same state is set-partitioned far. Preferably, said synchronizing signal controlling means comprises: a frequency-divider for frequency-dividing a system clock by a predetermined number and inputting the frequency-divided clock as a clock signal of the mapper; a first delay element for frequency-dividing the output of said frequency-divider again and outputting a clock signal of said selecting means; a second delay element for outputting the clock signal of said convolution encoder by receiving the output of said frequency-divider as its input, and receiving said synchronizing flag signal as an enabling signal; a third delay element for delaying said synchronizing flag signal by one clock portion; and a logic element for logic multiplying said synchronizing flag signal by the output of said third delay element and outputting the result to an enabling terminal of said mapper. Preferably, said synchronizing flag detecting means comprises: comparing means for comparing the I and Q channel data output through said first and second low-pass equalizers with specific synchronization patterned data being predetermined synchronizing flag reference values; detecting means for detecting specific data whereon a synchronizing signal is loaded and an adjacent predetermined number of data thereto from said compared values; and counting means for counting the synchronizing flag signal for the period of the synchronizing flag signal, detecting the starting and ending points of excited states of the synchronizing flag signal and outputting the synchronizing flag signal. Preferably, said decoding means comprises: a branch evaluated value computing circuit for computing the evaluated values for the respective branches of the I and Q channel data demodulated from said first and second low-pass equalizers; an adder/comparator/selector circuit for comparing the branch evaluated values in accordance with respective states on a Trellis diagram indicated in a time scale and selecting the least evaluated value; a state memory for storing the output of said adder/comparator/selector circuit; and a non-trace path memory for decoding information on survival paths according to respective states from said adder/comparator/selector circuit. Preferably, said decoding means is controlled in accordance with the synchronizing flag signal detected from said synchronizing flag detecting means and decodes the original synchronizing data in the manner that the value of said non-trace path memory is not output while the synchronizing flag signal is at an "excited" level. The invention extends to a video recorder and/or player provided with apparatus according to any of the preceding aspects of the invention. Preferred embodiments of the present invention may have the following effects. Frequency bands having a good carrier-to-noise ratio (CNR) in a magnetic recording and reproducing channel can be used by means of a multiple valued level modulation method. Also, a system can be realized easily by performing the modulation by generating a carrier wave signal (also called a carrier signal) synchronized with a system clock and performing the modulation digitally. Recording efficiency can be increased by extending frequency bands up to the permissible extent of CNR and BER of a reproduced signal. Further, the detecting synchronizing data can be easily detected after demodulation, by inserting a synchronizing signal and mapping the value of the synchronizing signal at the origin on a signal constellation diagram in another embodiment of the present invention, and the error rate can be improved by using the detected synchronizing data at the time of decoding. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of one example of an embodiment of a digital signal magnetic recording and reproducing apparatus, according to the present invention; Figure 2 is a view for explaining the concept of a modulator shown in Figure 1; Figures 3A to 3D are operational timing charts of the modulator shown in Figure 2; Figure 4 is a detailed block diagram of the modulator shown in Figure 2; Figure 5 is a detailed circuit diagram of the modulator shown in Figure 4; Figures 6A to 6C are views for explaining a carrier signal of sine components stored in a first ROM shown in Figure 5; Figures 7A to 7C are views for explaining a carrier signal of cosine components stored in a second ROM shown in Figure 5; Figure 8 is a view for explaining the concept of a demodulator shown in Figure 1; Figure 9 is a detailed block diagram of the demodulator shown in Figure 8; Figure 10 is a block diagram of another embodiment of a digital signal magnetic recording and reproducing apparatus, according to the present invention; Figures 11A to 11F are operational timing charts of the digital signal magnetic recording and reproducing apparatus shown in Figure 10; Figure 12 is a view for explaining the frequency characteristics of signals recorded in a magnetic recording medium by means of the apparatus shown in Figure 10; Figure 13 is a detailed circuit diagram of a synchronizing signal controlling means shown in Figure 10; Figures 14A to 14E are operational timing charts of the synchronizing signal controlling means shown in Figure 13; Figure 15 is a detailed circuit diagram of a convolution encoder shown in Figure 10; Figure 16 is a signal constellation diagram of a mapper shown in Figure 10; Figure 17 is a state diagram of the mapper shown in Figure 10; Figure 18 is a configurational diagram of a non-linear mapper shown in Figure 10 at the time of a ROM embodiment; and Figure 19 is a detailed circuit diagram of a synchronizing flag detecting means shown in Figure 10. The digital signal magnetic recording and reproducing apparatus according to the embodiment of Figure 1 comprises: a coding portion 10 having a convolution encoder 11 for convolutionally coding digital input data bits and a signal mapper 12 for parallel processing outputs of the convolution encoder 11 simultaneously by the number of the necessary bits; a modulating portion 20 having first and second pulse shaping filters 21 and 22 for band-restricting the output of the signal mapper 12 and a modulator 23 for modulating the outputs of the first and second pulse shaping filters 21 and 22; a pilot signal mixer 30 having a pilot signal generator 31 for generating a pilot signal and a second adder 32 for adding the pilot signal to the data modulated from the modulator 23; a recording controller 40 having a digital-to-analog (D/A) converter 41 for converting the output of the second adder 32 into an analog signal, a recording amplifier 42 for amplifying the output of the D/A converter 41, a bias signal generator 43 for generating a bias signal and a third adder 44 for adding the bias signal to the output of the recording amplifier 42; a magnetic recording and reproducing portion 50 having a recording head 51 for recording the output of the third adder 44 on a magnetic recording medium 52 as a magnetized signal and a reproducing head 53 for reproducing the magnetized signal recorded on the magnetic recording medium 52; a reproducing controller 60 having a reproducing amplifier 61 for amplifying the signal reproduced by the reproducing head 53, a phase shifter 62 for shifting the phase of the output of the reproducing amplifier 61, a low pass filter 63 for detecting a reproduced signal which is quadrature amplitude-modulated from the output of the phase shifter 62, an analog-to-digital (A/D) converter 64 for converting the output of the low-pass filter 63 into a digital signal form and a band-pass equalizer 65 for equalizing the output of the A/D converter 64; a carrier wave restoring means 70 having a band-pass filter 71 for detecting the pilot signal from the output of the phase shifter 62 and a phase locked loop (PLL) 72 for detecting a clock signal having the same frequency as that of the carrier signal from the outputs of band-pass filter 71; a demodulating portion 80 having a demodulator 81 for demodulating the output of the band-pass equalizer 65 and first and second matching filters 82 and 83 for restricting the output bands of the demodulator 81; a noise eliminator 90 having first and second decimators 91 and 92 for decimating the outputs of the first and second matching filter 82 and 83 for improving a signal-to-noise (S/N) ratio, first and second base-band equalizers 93 and 94 for equalizing the outputs of the first and second decimators 91 and 92 and third and fourth decimators 95 and 96 for redecimating the outputs of the first and second base-band equalizers 93 and 94; and a decoding portion 100 having a synchronizing signal detector 101 for detecting a synchronizing signal from the outputs of the third and fourth decimators 95 and 96 and a decoder 102 for decoding the outputs of the third and fourth decimators 95 and 96 in accordance with the detected synchronizing signal. The operation of the digital signal magnetic recording and reproducing apparatus shown in Figure 1 will now be described. According to Figure 1, the input data bits are output as k bits through the convolution encoder 11, with m bits not coded and n bits coded at a ratio of n/k. A convolution code is a non-block signal, which causes previous data to influence subsequent data and has an excellent capability of correcting burst errors. However, use of the convolution encoder 11 together with a signal mapper 12 is like block coding. Here, conventionally, the coding portion and the modulating portion have been treated separately, but the present embodiment of the invention uses the serially linked convolution encoder and modulator as in Ungerboeck's Trellis Coded Modulation (TCM). The Ungerboeck's channel coding method enhances a coding gain by reducing the detecting error of a Viterbi decoder at the time of coding and by maximizing the Euclidean distance between signals. In other words, to avoid a conventional method of performing coding and modulation separately, as in the Ungerboeck's channel coding method, there is a convolution coding so as to have a maximum Euclidean distance on a phase diagram of a modulated signal by creating a mutually organic relationship between coding and modulation. Therefore, k bits output from the convolution encoder 11 are coded at a maximum Euclidean distance among the codes, thereby minimizing detection error at the time of decoding. If the coded k bits and non-coded m bits are input to the signal mapper 12, they are changed into m+k bits suitable to be modulated, separated into (m+k)/2 and finally input to the in-phase (I) and quadrature-phase (Q) channels of first and second pulse shaping filters 21 and 22, respectively. Here, many more bits than m+k bits can be given by additional bits. The first and second pulse shaping filters 21 and 22 are constituted by low-pass filters and perform band restriction and wave shaping to eliminate inter-symbol interference (ISI). In other words, the signal, quadrature-amplitude-modulated and phase-shift-keying-modulated by the modulator 23, is output as r bits after passing through first and second pulse shaping filters 21 and 22, which are band-restricted within base bands in order to prevent internal modulation. The pilot signal generator 31 generates a pilot signal having a frequency of 2fc which is double the frequency of a carrier wave (fc) for the restoration of a carrier wave and outputs it to a first input terminal of the second adder 32. The second adder 32 adds the pilot signal to the r-bit modulated signal and outputs an s-bit signal. The D/A converter 41 converts the output of the second adder 32 into an analog signal and amplifies it in the recording amplifier 42. The bias signal f B generated in the bias signal generator 43 is recorded in a recording signal band so as to have the following relationship with a maximum frequency f H , as described in equation (1). f B ≥ 3f H The third adder 44 adds the output signal of the recording amplifier 42 to the bias signal to record the added signal on the magnetic recording medium 52 as a magnetized signal by means of recording head 51. The bias signal is a signal for correcting a hysteresis characteristic of the magnetized signal. The demodulating process is processed in the inverse sequence of the above described modulation process. After a modulated signal recorded on the magnetic recording medium 52 is reproduced by reproducing head 53, the reproduced signal is amplified in reproducing amplifier 61. The phase shifter 62 shifts the phase of the signal reproduced from the reproducing amplifier 61 by 90° to compensate the 90° phase shift which is due to the differential characteristic of a magnetic channel at the time of recording. The low-pass filter 63 detects a base band wherein a modulated signal is loaded, from the output of the phase shifter 62. A/D converter 64 converts the output of the low-pass filter 63 into a c-bit digital signal form and inputs it to demodulator 81 through band-pass equalizer 65. The band-pass equalizer 65 corrects the signal distortion and the signal deterioration which are generated in the transmission system. Meanwhile, band-pass filter 71 detects a band wherein a pilot signal is loaded among the signal amplified from the reproducing amplifier 61. The phase locked loop (PLL) 72 detects an r MHz modulation clock signal (a carrier wave) from the output of the band pass filter 71 and inputs it to the demodulator 81. The demodulator 81 receives, as its input, the output of the band-pass equalizer 65 and the output clock of the PLL 72, generates first and second carrier signals and outputs I and Q channel data by balance-modulating the carrier signals. Therefore, the demodulator 81 outputs the demodulated signals of two channels having d bits by forming convolutionally coded data. First and second matching filters 82 and 83 restrict the output bands of the demodulator 81. The matching filters are devices for prohibiting the modulation from being involved in the inter-symbol interference in accordance with the characteristics of first and second pulse shaping filters 21 and 22 at the time of modulation. The inter-symbol interference is generated from a reproduced signal by a frequency characteristic of magnetic recording and reproducing portion 50. Therefore, the convolutionally coded data of the demodulator 81 are band-restricted through first and second matching filters 82 and 83, thereby eliminating noise and improving the S/N ratio. First and second decimators 91 and 92 decimate the outputs of first and second matching filters 82 and 83. Band restriction and clock frequency reduction occurs by first and second matching filters 82 and 83 and first and second decimators 91 and 92, respectively. First and second base band equalizers 93 and 94 equalize two signals of I and Q channels of first and second decimators 91 and 92. Third and fourth decimators 95 and 96 redecimate the outputs of first and second base band equalizers 93 and 94 and output them to synchronizing signal detector 101 and decoder 102. Signal addition and clock frequency reduction occurs by first and second base band equalizers 93 and 94 and third and fourth decimators 95 and 96, respectively. Here, the reason why the decimation is performed twice is to seek system stability by lowering the clock frequency. Synchronizing signal detector 101 detects the synchronizing signal from the outputs of third and fourth decimators 95 and 96 and outputs it to the decoder 102. The decoder 102 decodes the demodulated signal of I and Q channels in accordance with the synchronizing signal. Here, a Viterbi decoder is employed as the decoder. In other words, the decoder 102 performs decoding by selecting the path of which the Hamming distance with the received data series is shortest by a maximum likelihood decoding (MLD). Figure 2 is a view for explaining the concept of the modulator shown in Figure 1. Referring to Figure 2, if data is input separately to I and Q channels, first and second carrier signals (the respective signals having a 90° phase difference) are multiplied by the data and two signals are added, then, a quadrature amplitude- and phase-shift-keying-modulated signal is output. Conventionally, such a signal processing as stated above is processed analogically, but in the present embodiment of the invention, signal processing is performed digitally, thereby improving signal distortion due to noise and environmental conditions. In other words, the modulator 23 shown in Figure 1 is a quadrature amplitude modulator (QAM). The modulator 23 generates a carrier signal in a first carrier frequency generator 24 in accordance with a system clock frequency, as shown in Figure 2. The first carrier signal C 1 (t) which can be expressed in the following equation (2) generates an i-bit signal and outputs it to a first balanced-modulator 25. C 1 (t) = A · SINωc · t The first balanced-modulator 25 balance-modulates a (m+k)/2 bit signal output to I channel from the first pulse shaping filter 21 and a first carrier signal and outputs a p-bit signal to a first input terminal of the first adder 27. Meanwhile, a second carrier signal C 2 (t) having a phase difference of ±90° from that of first carrier signal C 1 (t) = A · SINωc · t, which is generated from the carrier frequency generator 24, can be expressed in the following equation (3) and a second balanced modulator 26 balance-modulates a second carrier signal and a (m+k)/2 bit signal which is output to Q channel from the second pulse shaping filter 22 and outputs a q-bit signal to a second input terminal of the first adder 27. C 2 (t) = A · COSωc · t Assuming that the output of the first adder 27 is S(t), S(t) can be expressed in the following equation (4) and is output to a second input terminal of the second adder 32 as an r-bit signal. S(t) = (m+k)/2 · A · COSωc · t + (m+k)/2 · A · SINωc · t Figure 3A shows a modulating clock used for modulation, Figure 3B shows a parallel input of (m+k)/2 bit of I channel, Figure 3C shows a first carrier signal which is parallel input as i bits and Figure 3D shows quadrature-amplitude-modulated data which are the output of the first adder 27. Although only modulated signals of I channel are taken as examples in Figures 3A to 3D, it should be noted that such modulations are performed in I and Q channels at the same time. Figure 4 is a block diagram of the modulator shown in Figure 2. A characteristic of the modulator according to this embodiment of the invention is that the modulated signal processing steps process digital signals from input to output. The modulator shown in Figure 4 comprises: the first carrier signal generator 24 having a first ROM 241 wherein a first carrier signal which can be expressed in such sine components as the equation (2) is stored and a second ROM 242 wherein a second carrier signal which can be expressed in such cosine components as the equation (3) is stored; the first balanced-modulator 25 having a first AND gate combination circuit 251 for combining the I channel data output from the first pulse shaping filter 22 and a first carrier signal output from the first ROM 241, a first adder combination circuit 252 for adding the output of the first AND gate combination circuit 251 and a first latch 253 for temporarily storing the output of the first adder combination circuit 252; the second balanced-modulator 26 having a second AND gate combination circuit 261 for combining the Q channel data output from the second pulse shaping filter 23 and a second carrier signal output from the second ROM 242, a second adder combination circuit 262 for adding the outputs of the second AND gate combination circuit 261 and a second latch 263 for temporarily storing the output of the second adder combination circuit 262; and the first adder 27 having a third adder combination circuit 271 for adding the outputs of the first and second latches 253 and 263, that is, the p-bit modulated signal of the I channel to the q-bit modulated signal of the Q channel and a third latch 272 for temporarily storing the output of the third adder combination circuit 271, that is, the r-bit quadrature-amplitude-modulated signal. Figure 5 is a detailed circuit diagram of the modulator shown in Figure 4. Referring to Figure 5, a first multiplier 250 corresponds to the first AND gate combination circuit 251 and first adder combination circuit 252 shown in Figure 4 and a second multiplier 260 corresponds to the second AND gate combination circuit 261 and second adder combination circuit 262, first to third latches 253, 263 and 272 are constituted by D flip-flops and a third adder combination circuit 271 corresponds to an adder. Now, the operation of the modulator of Figure 4 will be explained in connection with Figures 5 to 7C. Referring to Figure 4, if the input digital data is separated into I and Q channels respectively, and input to first and second AND gate combination circuits 251 and 261, the digital data (the first carrier signal) of the sine components from first ROM 241 and the I channel data are multiplied in the first AND gate combination circuit 251 and first adder combination circuit 252 and are then latched to first latch 253. The digital data (the second carrier signal) of cosine components from second ROM 242 and the Q channel data are multiplied in second AND gate combination circuit 261 and second adder combination circuit 262 and are then latched to second latch 263. The third adder combination circuit 271 combines the I and Q signals and generates a quadrature-amplitude-modulated signal through the third latch 272. The input data Di and carrier Ci are multiplied to generate an output Mi. Here, a reference letter i denotes integers from numeral 1 through n. Here, composition examples of the carrier frequencies indicating a digital composition method are shown in Figures 6A to 7C. For example, Figure 6A shows the waveform of a carrier of frequency 5.332 MHz. In Figure 6A which illustrates a wavelength of first carrier signal C1(t) having K MHz frequency, the abscissa indicates address numbers 0 to 2 n -1 and the ordinate indicates quantizing levels with respect to amplitudes. If address and amplitude are quantized into 10 bits and 4 bits, respectively, a table as shown in Figure 6B is obtained. Figure 6B explains the relationship between addresses and amplitudes, which is expressed in an equation, y = sin (2 n-2 /90) · m. Here, y indicates an equidistance of amplitudes. Here, if the table is read by a clock of 26 MHz, only about 4.876 data values are read. The relationship is indicated as follows: 26 MHz/5.332 MHz = 4.876 The result is as follows. 1024/4.876 = 210. That is, 1024 addresses are continuously read at an interval of 210 addresses. If such operations are repeated, the same value as that of the initially read address is read again at the 513th operation. Then, the remaining 512 values are discarded and only the repetitive 512 values are taken to form the table using a ROM, which is first ROM 241. Figure 6C indicates such a table formed by the above relationship. As indicated in the table, whenever a clock signal is received, sequentially repetitive signals are read from the actual addresses 0 through 511. Figure 7A illustrates a wavelength of second carrier signal C2(t) having K Mhz frequency, where the abscissa indicates address numbers 0 to 2 n -1 and the ordinate indicates quantizing levels with respect to amplitudes. Figure 7B shows a relationship between address and amplitude and y indicates a given variation of the amplitude as every address is increased by one. As indicated in the table shown in Figure 7C by such a relationship, whenever a clock signal is received, sequentially repetitive signals are read from the actual addresses 0 through 511 and the value stored in the address becomes a second carrier signal of the cosine components, which is stored in second ROM 242. Figure 8 is a drawing for explaining the concept of the demodulator 81 shown in Figure 1, and the operation thereof is performed in the inverse order to that of modulation. Referring to Figure 8, the input modulated signal is input to a first input of third and fourth balanced-modulators 85 and 86. First and second carrier signals which are generated from a second carrier frequency generator 84 by a clock frequency having the input frequency of f c are input to a second input of third and fourth balanced-modulators 85 and 86, respectively. The second carrier signal to be expressed in cosine components input to the fourth balanced-modulator 86 is a signal phase-shifted by 90°, compared with the first carrier signal which can be expressed in sine components. The modulated input signals are balance-modulated in the third and fourth balanced-modulators 85 and 86, respectively, by two carrier signals. Figure 9 is a detailed block diagram of an example of the demodulator shown in Figure 8. Referring to Figure 9, the second carrier frequency generator 84 corresponds to a third ROM 841 wherein a first carrier signal to be expressed in sine components is stored and a fourth ROM 842 wherein a second carrier signal to be expressed in cosine components is stored. The signals stored in these ROMs are the same as those stored in first and second ROMs 241 and 242, as described above in connection with Figures 6A to 7C. The third balanced-modulator 85 corresponds to a fourth AND gate combination circuit 851 for combining the modulated signal output from band-pass equalizer 65 and the first carrier signal output from the third ROM 841, a fourth adder combination circuit 842 for adding the output of the fourth AND gate combination circuit 851 and a fourth latch 853 for temporarily storing the output of the fourth adder combination circuit 852. The fourth AND gate combination circuit 851 and fourth adder combination circuit 852 are constituted by multipliers. The fourth balanced-modulator 86 corresponds to a fifth AND gate combination circuit 861 for combining the modulated signal output from band-pass equalizer 65 and the second carrier signal output from the fourth ROM 842, a fifth adder combination circuit 862 for adding the output of the fifth AND gate combination circuit 861 and a fifth latch 863 for temporarily storing the output of the fifth adder combination circuit 862. The fifth AND gate combination circuit 861 and a fifth adder combination circuit 862 are constituted by multipliers. Figure 10 is a block diagram of the digital signal magnetic recording and reproducing apparatus according to another embodiment of the present invention, which comprises: a synchronizing signal inserter 110 for inserting a synchronizing signal to input digital data; a synchronizing signal controller 120 for synchronizing the overall system; a multiplexer 130 for selectively outputting the output of the synchronizing signal inserter 110 in accordance with a synchronizing flag signal output from the synchronizing signal controller 120; a coding portion 140 having a buffer 141 for temporarily storing a part of the bits which are parallel transferred among data output from the multiplexer 130, a convolution encoder 142 for coding data of the rest of the bits among data output from the multiplexer 130 considering a coding gain and a bit error rate and a mapper 143 for setting the relationship between signal points through the convolution encoder 142 so that a coding gain becomes large at the time of decoding; a modulating portion 150 having first and second pulse shaping filters 151 and 152 for restricting base bandwidths of the I and Q channel data output from the mapper 143 and removing inter-symbol interference and a modulator 153 for generating a carrier wave using a ROM table and for quadrature-amplitude-modulating andphase-shift-keying-modulating the output of two channels of the mapper 143 using the carrier wave; a pilot signal mixer 160 having a pilot signal generator 161 for facilitating demodulation in synchronization with a carrier frequency and a first adder 162 for adding the pilot signal to the modulated data of the modulator 153; a recording controller 170 having a digital-to-analog (D/A) converter 171 for converting the output of the first adder 162 to an analog signal, a bias signal generator 172 for utilizing a linear component of a magnetization characteristic curve considering non-linear characteristics of magnetic channels and a second adder 173 for adding a bias signal of the bias signal generator 172 to the output of the D/A converter 171; a magnetic recording and reproducing portion 180 having a recording head 181 for recording the output of the second adder 173 on a magnetic recording medium 182 as a magnetized signal and a reproducing head 183 for reproducing the magnetized signal recorded on the magnetic recording medium 182; a reproducing controller 190 having an analog-to-digital (A/D) converter 191 for A/D converting a signal reproduced by the reproducing head 183 and a reproducing equalizer 192 for correcting both phase, by the differential characteristics of the magnetic channels for the reproduced signal, and signal amplitude attenuation; a carrier wave restoring portion 200 having a band- pass filter 201 for detecting frequency bands wherein a pilot signal is loaded from the signal reproduced from the reproducing head 183 and a carrier wave reproducer 202 composed of a PLL for detecting a clock signal having the same frequency as that of the carrier signal from the output of the band-pass filter 201; a demodulating portion 210 having a demodulator 211 for demodulating the modulated signal to the I and Q channel data using the reproduced carrier wave and first and second low-pass equalizers 212 and 213 for amplitude- and phase-correcting the output of the demodulator 211; a synchronizing flag signal detector 220 for restoring a synchronizing flag signal from the signal demodulated from the first and second low-pass equalizers 212 and 213; and a Viterbi decoder 230 having a branch evaluated value computing circuit 231 for computing the evaluated amount for the respective branches of the I and Q channel data demodulated from the first and second low pass equalizer 212 and 213, an adder/comparator/selector circuit 232 for comparing the evaluated branch values according to respective states of a Trellis diagram indicated in a time scale and selecting the least value of the evaluated value, a state memory 233 for storing the output of the adder/comparator/selector circuit 232 and a non-trace pass memory 234 for decoding the information on the survival paths in accordance with the respective states. Now, the operation of the digital signal magnetic recording and reproducing apparatus shown in Figure 10 will be explained with reference to Figures 11A to 11F. If such m-bit digital data as shown in Figure 11A is input to synchronizing signal inserter 110, a synchronizing signal is inserted to the digital data in accordance with the system clock shown in Figure 11B and then output as a signal form shown in Figure 11C to be input to multiplexer 130. The signal (Figure 11C) to which a synchronizing signal is added by means of the synchronizing signal inserter 110 is output as n bits through the multiplexer 130. Among the output bits, (n-2) bits are parallel shifted to be input to buffer 141 and the other two bits are input to convolution encoder 142. A synchronizing flag signal output from the synchronizing signal inserter 110, as shown in Figure 11D, is synchronized to the system clock shown in Figure 11B to be input to synchronizing signal controller 120 which is a system synchronization circuit. The synchronizing signal controller 120 outputs a clock signal which is "low" during an interval where a synchronizing signal is loaded and which is "normal" during a valid data interval, to the convolution encoder 142, as shown in Figure 11E. The data output through the multiplexer 130 are input to the mapper 143 through a convolution encoder 142 while the synchronizing flag signal shown in Figure 11F is "low (0)" and the convolution encoder 142 does not operate while the synchronizing flag signal is "high (1)." If the synchronizing flag signal of "high (1)" state is input to the terminal S of the mapper 143, the synchronizing signal is mapped at the origin of a signal constellation diagram. The signals separated into the I and Q channels through the mapper 143 are input to modulator 153 through first and second pulse shaping filters 151 and 152 which do not have inter-symbol interference (ISI) and restrict bands suitably to the bandwidth of the magnetic channels. Here, the structure and operation of the modulator 153 are the same as those of the modulator as already explained in Figures 2 to 7. The signal input to the modulator 153 is balance-modulated with the carrier wave signal synchronized with the system clock (Figure 11B) and the output of the modulator 153 is then added to the pilot signal of which the frequency is double that of a carrier wave, which is generated in the pilot signal generator 161, in first adder 162. The pilot signal generator 161 is a circuit necessary for demodulating the signal by reproducing the pilot signal and synchronizing the reproduced signal through the synchronized carrier wave generator 202 when a signal is demodulated. The carrier wave generator 202 is composed of a phase locked loop (PLL). The modulated signal to which the pilot signal is added, is converted to an analog signal through D/A converter 171, generates the bias signal having the frequency three times more than that of the modulated signal in the bias signal generator 172, and adds it to the modulated signal converted to an analog signal, so as to be output to record the signal on the magnetic recording channel using a linear component on the magnetized characteristic curve of a magnetic channel. The frequency spectrum of the signal recorded on the magnetic recording channel is as shown in Figure 12. Among the signals reproduced through the magnetic recording medium 182, a pilot signal is detected by band-pass filter 201. The carrier wave regenerator 202 reproduces a carrier wave in synchronization with the reproduced signal and so as to be input to the demodulator 211. Also, the signal reproduced through the magnetic channel (the magnetic recording medium) is converted to digital data through the A/D converter 191 and the signal distorted due to the channel is compensated through the reproducing equalizer 192, to be input to the demodulator 211. The reproducing equalizer 192 is composed of a 90° phase correcting circuit by the differential characteristic of a magnetic channel and an amplitude correcting circuit for correcting amplitude attenuation of a signal. The output of the reproducing equalizer 192 is multiplied to the carrier wave reproduced by the carrier wave reproducer 202 to be demodulated in the demodulator 211. The frequency and the phase of the signal are compensated through first and second low-pass equalizers 212 and 213 and then decoded through Viterbi decoder 230. The synchronizing flag signal detector 220 controls the Viterbi decoder 230 by detecting a synchronizing flag signal from the demodulated signal output from first and second low-pass equalizers 212 and 213 and decodes the original data by not letting the value of a non-trace pass memory 234 be output while the synchronizing flag signal is "high (1)". The I and Q data input to the Viterbi decoder 230 is calculated as the evaluated value for the respective branches by the branch evaluated value computing circuit 231 and is transmitted to adder/comparator/selector circuit 232 and status memory 233. The branch evaluated value computing circuit 231 which computes an evaluated value with input data and coded data, computes all the values of the I and Q channels, respectively, squares the respective values, adds the I and Q values having a signal point on a signal constellation diagram and extracts their square roots. Thus all of 32 signal points are computed. The adder/comparator/selector circuit 232 adds the evaluated values of both the branch evaluated value computing circuit 231 and the status memory 233, compares the branch evaluated values in accordance with the respective states on the Trellis diagram indicating the status diagram shown in Figure 16 in a time scale, selects the least of the evaluated values to store it in the state memory 233 again, transfer the information on the survived paths of the respective states to the non-trace path memory 234 to output decoded final data. In other words, the adder/comparator/selector circuit 232 adds a current evaluated value to an existing evaluated value of paths, and selects the least of the evaluated values to extract a path select signal and a newly evaluated value. Figure 13 is a detailed circuit diagram of the synchronizing signal controller shown in Figure 10. In Figure 13, reference numeral 121 denotes a frequency-divider, 122, 125 and 126 are D flip-flops, 123 and 124 are inverters and 127 is an AND gate. The operation of the synchronizing signal controller shown in Figure 13 will be explained with reference to Figures 14A to 14E. Assuming that a system clock is Q Mhz, the system clock is frequency-divided through the frequency-divider 121 by a frequency division ratio of Q/n, the frequency-divided clock signal (shown in Figure 14B) is input to the mapper 143 shown in Figure 10 as a clock signal and at the same time input to the clock terminal CLK of the D flip-flop 122 to be frequency-divided by two, and finally is input as a clock signal of the multiplexer 130 shown in Figure 10. Also, the output of the inverter 123 is input to the input terminal D of the D flip-flop 125 having a latch function and the clock terminal CLK of the D flip-flop 126. The synchronizing flag signal shown in Figure 14A is input to an enabling terminal G of the D flip-flop 125 and also input to the input terminal D of the D flip-flop 126 through the inverter 124. The output (shown in Figure 14C) of the D flip-flop 125 is input as a clock signal of the convolution encoder 142 shown in Figure 10, the inverted output Q of the D flip-flop 126 as shown in Figure 14D is logically multiplied by the synchronizing flag signal shown in Figure 14A, through the AND gate 127, and the output signal shown in Figure 14E is input to the enabling terminal S of the mapper 143 shown in Figure 10. Also, the system clock is input as the address clock of the modulator 153 and the pilot signal generator 161 shown in Figure 10. Meanwhile, while the synchronizing flag signal shown in Figure 14A is "1," the convolution encoder 152 does not operate. While the synchronizing flag signal is "0," 2-bit data input to the convolution encoder 142 are coded to be output as 3 bits. The detailed circuit diagram of the convolution encoder 142 is as shown in Figure 15. In Figure 15, numerals 241 to 245 are D flip-flops, 246 to 248 are exclusive-OR gates (XOR). In the following description related to the example of Figure 15, numerals 241 to 242 now denote D flip- flops. These reference signs do not fall within the terms of the claims. The operation of Figure 15 will be explained with reference to Figures 16 to 18. The clock signal (shown in Figure 14C) output from the D flip-flop 125 is input to the clock terminal CLK of the D flip-flops 241 to 245. The 2-bit data output from the multiplexer 130 are input to the input terminal of the D flip-flops 241 to 245. The output of the D flip-flop 241 is input to the input terminal D of the D flip-flop 242 and a first input terminal of the XOR 247, and the output of the D flip-flop 242 is input to a first input terminal of the XOR 246 and a first input terminal of the XOR 248. The output of the D flip-flop 243 is input to the input terminal D of the D flip-flop 244, a second input terminal of the XOR 246 and a fourth input terminal of the XOR 248 and the output of the D flip-flop 244 is input to the input terminal D of the D flip-flop 245 and a third input terminal of the XOR 247. The output of the D flip-flop 245 is input to a second input terminal of the XOR 247 and a third input terminal of the XOR 248. The output of the XOR 246 becomes the lowest encoded bit, the output of the XOR 247 becomes an upper bit and the output of the XOR 248 becomes the uppermost bit. The logic states of the input and output according to the present state and next state of the convolution encoder shown in Figure 15 are as follows. INPUT PRESENT STATE NEXT STATE OUTPUT 00 000 000 000 01 001 000 000 10 010 000 000 11 011 000 111 00 100 010 001 01 101 010 001 10 110 010 110 11 111 010 000 00 000 001 111 01 001 001 101 10 010 001 010 11 011 001 100 00 100 011 011 01 101 011 110 10 110 011 011 11 111 011 010 00 000 100 101 01 001 100 110 10 010 100 001 11 011 100 010 00 100 110 011 01 101 110 111 10 110 110 010 11 111 110 110 00 000 101 011 01 001 101 100 10 010 101 011 11 011 101 100 00 100 111 100 01 101 111 101 10 110 111 100 11 111 111 001 The convolution encoder 142 is devised so as not to have a catastrophe phenomenon that an error is spread infinitely and that an error rate is reduced at the time of decoding. The n+1 bits output through the convolution encoder 142 are mapped as in the signal constellation shown in Figure 16 to be output through I and Q channels. The origin in Figure 16 is where synchronizing data are mapped. The synchronizing data is mapped at the origin while the synchronizing flag signal input by the synchronizing signal controller 120 not through the convolution encoder 142 is "1," where the synchronizing signal is less affected by an error to facilitate the detection of the synchronizing flag signal from the synchronizing flag signal detector 220. In the signal constellation illustrated in Figure 16, the signals are mapped so that coding gains are increased in the manner that the parallel shifted portions are set-partitioned farthest and the shifted signal in the same state is set partitioned far, among the signals encoded in accordance with the state diagram of Figure 17. The respective sets partitioned into 8 sets are as follows. C 0 = [00000(0), 01101(13), 10111(23), 11011(27)], C 1 = [00001(1), 01010(10), 10110(14), 11000(24)], C 2 = [00101(5), 01001(9), 10011(19), 11100(28)], C 3 = [00100(4), 01000(8), 10010(18), 11111(31)], C 4 = [00011(3), 01100(12), 10110(22), 11010(26)], C 5 = [00110(6), 10000(16), 10100(20), 11101(29)], C 6 = [00010(2), 01011(11), 10000(15), 11001(25)] and C 7 = [00111(7), 10001(17), 10101(21), 11110(30)] Figure 18 shows a structure of the ROM table when the mapper is constructed in an ROM. Figure 19 is a detailed circuit diagram of the synchronizing flag detector shown in Figure 10. In Figure 19, numerals 221 and 222 are first and second comparators, 223 is a shift register, 224 is a counter, 225 is a D flip-flop, A1 to A5 are AND gates, N1 is a NOR gate, OR1 and OR2 are OR gates. Next, the operation of the synchronizing flag detector shown in Figure 19 will be explained. Referring to Figure 19, the I and Q channel data output through the first and second low pass equalizers 212 and 213 shown in Figure 10 are compared with the specific synchronization patterned data by the comparators 221 and 222 and the compared values are logically multiplied in the first AND gate Al to be input to the shift register 223. The synchronization patterned data which are predetermined synchronizing flag reference values, are "0000" since they are mapped at the origin. The value of "1111", "1101" or "1011" of the shift register 223 is detected in the second and third AND gates A2 and A3 and input to the load port LOAD of the counter 224 through the OR gate OR1 and NOR gate NOR 1. If a signal is input to the load port LOAD of the counter 224, the counter 224 counts the number of clock pulse for which synchronizing flag signals are repeated. If the counted values are data corresponding to the points at which the "high" interval of the synchronizing flag signal starts and ends, they are input to the clock of the D flip-flop 225 through the fourth and fifth AND gates A4 and A5 and the second OR gate OR2 and a synchronizing flag signal is output from the D flip-flop 225. The signal counted as often as the frequency of the synchronizing flag signal is negative logic summed with the signal compared by the comparators 221 and 222 through the NOR gate NOR to be loaded to the load port LOAD . The synchronizing flag signal is input to a Viterbi decoder 400. As stated above, the illustrated examples of digital signal magnetic recording and reproducing apparatus increase frequency utilization efficiency by adopting a multiple valued digital modulation method, which is used in the communication field, having a high recording efficiency due to the low error rate of the reproduced data, and improves a recording bit rate without increasing recording channels, thereby enabling high density recording.

Claims: A digital signal magnetic recording and reproducing apparatus which modulates a digital image input signal, records the modulated signal on a magnetic medium (52), reads the signal recorded thereon and demodulates it to the original signal, said apparatus being characterised by : coding means (10, 140) for converting an input digital image signal into a multiple valued digital signal; modulating means (20, 150) for digitally quadrature-amplitude-modulating and phase-shift-keying-modulating said multiple valued digital signal according to a carrier signal; pilot signal mixing means (30, 160) for generating a pilot signal and digitally mixing the pilot signal with said modulated signal; recording controlling means (40, 170) for forming a magnetized signal suitable for recording on a magnetic recording medium (52, 182) from the modulated signal mixed with said pilot signal; reproducing controlling means (60, 190) for outputting a digital signal of which the signal distortion and deterioration produced in a transmission system are corrected, from a magnetized signal reproduced from said magnetic recording medium (52); carrier wave restoring means (70, 200) for generating a clock signal having the carrier signal frequency by detecting a pilot signal from said reproduced magnetized signal; demodulating means (80, 210) for digitally demodulating the modulated signal output from said reproducing controlling means (60) according to the carrier signal restored from said carrier wave restoring means (70, 200); and decoding means (100, 230) for outputting original digital data by Viterbi-decoding convolutionally coded data from the output of said demodulating means (80, 210). A digital signal magnetic recording and reproducing apparatus, as claimed in claim 1, further comprising noise eliminating means (90) for restricting bands and decreasing clock frequencies to improve a signal-to-noise ratio of the output of said demodulating means (80) supplied to said decoding means (100). A digital signal magnetic recording and reproducing apparatus, as claimed in claim 1 or 2, wherein said modulating means (20, 150) comprises: a first ROM (241) in which a first carrier signal to be expressed in sine components is stored; a second ROM (242) in which a second carrier signal to be expressed in cosine components is stored; a first multiplier (25) for multiplying the first carrier signal output from said first ROM (241) by the in-phase (I) channel data output from said coding means (10); a second multiplier (26) for multiplying the second carrier signal output from said second ROM (242) by the quadrature-phase (Q) channel data output from said coding means (10); and a first adder (27) for adding the outputs of said first and second multipliers (25,26). A digital signal magnetic recording and reproducing apparatus, as claimed in claim 1 or 2, wherein said modulating means (20, 150) comprises: first and second pulse shaping filters (21,22,151,152) for wave-shaping and band-restricting of the I and Q channel data output from said coding means (10); a first carrier signal generator (24) having a first ROM (241) wherein a first carrier signal to be expressed in sine components is stored and a second ROM (242) wherein a second carrier signal to be expressed in cosine components is stored; a first balanced-modulator (25) having a first AND gate combination circuit (251) for combining the I channel data output from said coding means (10, 140) with a first carrier signal output from said first ROM (241), a first adder combination circuit (252) for adding the output of the first AND gate combination circuit (251) and a first latch (253) for temporarily storing the output of the first adder combination circuit (252); a second balanced-modulator (26) having a second AND gate combination circuit (261) for combining the Q channel data output from said coding means (10, 140) with a second carrier signal output from said second ROM (242), a second adder combination circuit (262) for adding the output of the second AND gate combination circuit (261) and a second latch (263) for temporarily storing the output of the second adder combination circuit (262); and a first adder (27) having a third adder combination circuit (271) for adding the outputs of said first and second latches (253,263), that is, the modulated signal of the I channel and the modulated signal of the Q channel, and a third latch (272) for temporarily storing the quadrature-amplitude-modulated signal which is the output of said third adder combination circuit (271). A digital signal magnetic recording and reproducing apparatus, as claimed in any of the preceding claims, wherein said pilot signal mixing means (30, 160) comprises: a pilot signal generator (31, 161) for generating a pilot signal having a frequency equal to a predetermined number of times the frequency of the carrier signal; and a second adder (32, 162) for adding the pilot signal to the modulated data of said modulating means (20, 150). A digital signal magnetic recording and reproducing apparatus, as claimed in any of the preceding claims, wherein said recording controlling means (40) comprises: a digital-to-analog (D/A) converter (41) for converting the output of said pilot signal mixing means (30) to an analog signal; a recording amplifier (42) for amplifying the output of said D/A converter (41); a bias signal generator (43) for generating a bias signal; and a third adder (44) for adding the bias signal to the output of said recording amplifier (42). A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 1 to 5, wherein said recording controlling means (170) comprises: a digital-to-analog (D/A) converter (171) for converting the output of said pilot signal mixing means (160) into an analog signal; a bias signal generator (172) for generating a bias signal to use a linear portion of a magnetized characteristic curve considering non-linear characteristics of a magnetic channel; and a third adder (173) for adding the output of said D/A converter to the bias signal of said bias signal generator. A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 1 to 7, wherein said reproducing controlling means (60) comprises: a reproducing amplifier (61) for amplifying a magnetized signal reproduced from said magnetic recording medium (52); a phase shifter (62) for shifting the phase of the output of said reproducing amplifier (61) to compensate a phase shift by the differential characteristics of a magnetic channel at the time of recording; a low-pass filter (63) for filtering the reproduced signal from the output of said phase shifter (62); an analog-to-digital (A/D) converter (64) for converting the output of said low-pass filter (63) into a digital signal form; and a band-pass equalizer (65) for receiving the output of said A/D converter (64) and correcting signal distortion and deterioration produced in a transmission system. A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 1 to 7, wherein said reproducing controlling means (190) comprises: an analog-to-digital (A/D) converter (191) for A/D converting the signal reproduced from said magnetic recording medium (182); and a reproducing equalizer (192) for correcting both phase and amplitude attenuation of a reproduced signal due to a differential magnetic channel characteristic. A digital signal magnetic recording and reproducing apparatus, as claimed in any of the preceding claims, wherein said carrier wave restoring means (70, 200) comprises: a band-pass filter (71, 201) for detecting a pilot signal from an output of said reproducing controlling means (60); and a phase locked loop (PLL) (72, 202) for generating a clock signal having a frequency corresponding to that of the carrier signal from the output of said band-pass filter (71, 201). A digital signal magnetic recording and reproducing apparatus, as claimed in any of the preceding claims, wherein said demodulating means (80, 210) comprises: a third ROM (841) from which a first carrier signal to be expressed in sine components is read in accordance with a clock corresponding to said restored carrier signal; a fourth ROM (842) from which a second carrier signal to be expressed in cosine components is read in accordance with a clock corresponding to said restored carrier signal; a third multiplier (85) for multiplying the modulated signal output from said reproducing controlling means (60, 190) by the first carrier signal output from said third ROM (841); a fourth multiplier (86) for multiplying the modulated signal output from said reproducing controlling means (60, 190) by the second carrier signal output from said fourth ROM (842); and a fourth adder for adding the outputs of said third and fourth multipliers (85,86). A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 1 to 10, wherein said demodulating means (80, 210) comprises: a second carrier signal generator (84) having a third ROM (841) from which a first carrier signal to be expressed in sine components is read in accordance with a clock corresponding to said restored carrier signal and a fourth ROM (842) from which a second carrier signal to be expressed in cosine components is read in accordance with a clock corresponding to said restored carrier signal; a third balanced-modulator (85) having a fourth AND gate combination circuit (851) for combining the modulated signal output from said reproducing controlling means (60, 190) with the first carrier signal output from said third ROM (841), a fourth adder combination circuit (852) for adding the output of the fourth AND gate combination circuit (851) and a fourth latch (853) for temporarily storing the output of the fourth adder combination circuit (852); a fourth balanced-modulator (86) having a fifth AND gate combination circuit (861) for combining the modulated signal output from said reproducing controlling means (60, 190) with the second carrier signal output from said fourth ROM (842), a fifth adder combination circuit (862) for adding the output of the fifth AND gate combination circuit (861) and a fifth latch (863) for temporarily storing the output of the fifth adder combination circuit (862); and first and second matching filters (82,83) for restricting the output bands of said third and fourth balanced-modulators (85,86), or first and second low pass equalisers (212, 213) for correcting the amplitudes and phases of the output bands of said third and fourth balanced-modulators (85,86). A digital signal magnetic recording and reproducing apparatus, as claimed in claims 2 and 12, wherein said noise eliminating means (90) comprises: first and second decimators (91,92) for decreasing a clock frequency to improve a signal-to-noise (S/N) ratio of the output of the first and second matching filters (82,83); first and second base-band equalizers (93,94) for compensating the output signals of said first and second decimators (91,92); and third and fourth decimators (95,96) for redecimating the outputs of said first and second base-band equalizers (93,94) to decrease the clock frequency. A digital signal magnetic recording and reproducing apparatus as claimed in any preceding claim, comprising : digital-to-analog (D/A) converting means (41) for converting the modulated signal with which said pilot signal is mixed into an analog signal; said recording controlling means (40) comprising bias signal generating means for generating a bias signal having a frequency more than a predetermined number of times the frequency of a carrier signal to be recorded using a linear portion on a magnetizing characteristic curve of a magnetic channel, combining the generated bias signal with the output of said D/A converting means and transmitting the result to said magnetic recording medium (52); and said reproducing controlling means (60) comprising analog-to-digital (A/D) converting means (64) for outputting an analog magnetized signal reproduced from said magnetic recording medium (52) as a digital signal form after correcting the signal distortion and deterioration of the signal, produced in the transmission system; A digital signal magnetic recording and reproducing apparatus as claimed in any preceding claim, comprising : synchronizing signal inserting means (110) for inserting a synchronizing signal to said input digital data supplied to said coding means (140) and outputting a synchronizing flag signal; synchronizing signal controlling means (120) for controlling the coding of said coding means (140) by receiving said synchronizing flag signal; synchronizing flag detecting means (220) for restoring a synchronizing flag signal from said demodulated signal output by said demodulating means (210); and said decoding means (230) outputting original digital data by Viterbi-decoding convolutionally coded data from the output of said demodulating means (210) in accordance with said synchronizing flag signal. A digital signal magnetic recording and reproducing apparatus, as claimed in claim 13, wherein said coding means (140) comprises: a buffer (141) for temporarily storing part of the bits of data output from said synchronizing signal inserting means (110); a convolution encoder (142) in which a coding gain and a bit error rate are considered from the data output from said synchronizing signal inserting means (110); and a mapper (143) which sets the relationship between signal points through said convolution encoder (142) so that a coding gain becomes large at the time of decoding. A digital signal magnetic recording and reproducing apparatus, as claimed in claim 16, further comprising a selecting means (130) for selectively outputting some of the bits of the signals output from said synchronizing signal inserting means (110) to said mapper (143) and the rest of the bits to said convolution encoder (142) so as to be parallel shifted. A digital signal magnetic recording and reproducing apparatus, as claimed in claim 16 or 17, wherein said mapper (143) maps the synchronizing signal output from said synchronizing signal inserting means (110) at the origin on a signal constellation diagram while said synchronizing flag signal is in an "excited" level period. A digital signal magnetic recording and reproducing apparatus, as claimed in claim 14, 15 or 16, wherein said mapper (143) is constituted by ROMs, and in the signal constellation, a parallel shifted portion among signals of said convolution encoder (142) is set-partitioned farthest and a signal shifted in the same state is set-partitioned far. A digital signal magnetic recording and reproducing apparatus, as claimed in claim 17, or any of claims 18 or 19 as appendant thereto, wherein said synchronizing signal controlling means (120) comprises: a frequency-divider (121) for frequency-dividing a system clock by a predetermined number and inputting the frequency-divided clock as a clock signal of the mapper (143); a first delay element (122) for frequency-dividing the output of said frequency-divider (121) again and outputting a clock signal of said selecting means (130); a second delay element (125) for outputting the clock signal of said convolution encoder (142) by receiving the output of said frequency-divider (121) as its input, and receiving said synchronizing flag signal as an enabling signal; a third delay element (126) for delaying said synchronizing flag signal by one clock portion; and a logic element (127) for logic multiplying said synchronizing flag signal by the output of said third delay element (126) and outputting the result to an enabling terminal of said mapper (143). A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 15 to 20, wherein said synchronizing flag detecting means (220) comprises: comparing means for comparing the I and Q channel data output through said first and second low-pass equalizers (212,213) with specific synchronization patterned data being predetermined synchronizing flag reference values; detecting means for detecting specific data whereon a synchronizing signal is loaded and an adjacent predetermined number of data thereto from said compared values; and counting means for counting the synchronizing flag signal for the period of the synchronizing flag signal, detecting the starting and ending points of excited states of the synchronizing flag signal and outputting the synchronizing flag signal. A digital signal magnetic recording and reproducing apparatus, as claimed in any of claims 14 to 21, wherein said decoding means (230) comprises : a branch evaluated value computing circuit (231) for computing the evaluated values for the respective branches of the I and Q channel data demodulated from said first and second low-pass equalizers (212,213); an adder/comparator/selector circuit (232) for comparing the branch evaluated values in accordance with respective states on a Trellis diagram indicated in a time scale and selecting the least evaluated value; a state memory (233) for storing the output of said adder/comparator/selector circuit (232); and a non-trace path memory (234) for decoding information on survival paths according to respective states from said adder/comparator/selector circuit (232). A digital signal magnetic recording and reproducing apparatus, as claimed in claim 22, wherein said decoding means (230) is controlled in accordance with the synchronizing flag signal detected from said synchronizing flag detecting means (220) and decodes the original synchronizing data in the manner that the value of said non-trace path memory is not output while the synchronizing flag signal is at an "excited" level. A digital signal recording and reproducing apparatus according to any of the preceding claims, wherein said apparatus comprises a video recorder.

Inventors: CHANG YONG-DEOK, PARK SAM-YONG, CHANG, YONG-DEOK, PARK, SAM-YONG
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1994
Main classification: H04N5
IPC codes: G11B20, H04N5, H04N7, G11B5, H04L27