Burst refresh mode for DRAMs

Abstract: Burst refresh mode circuitry is provided for a memory (100) having cells (112) in rows and columns, sense amplifiers (110) and Latch N/Latch P driver circuitry (124), a RAS buffer (102), refresh counters (106), address buffers (104), row decoders (108), precharge circuitry (120) producing shorting clocks (128), and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry (140) detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit (136) causes the RAS buffer (102) to generate a new internal RAS signal. Burst refresh mode logic (134) has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit (130) interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry (132) is partially disabled.

Description: The present invention concerns a method of refreshing an integrated circuit memory of the kind defined in the preamble of Claim 1 and a memory circuit as defined in the preamble of Claim 11. A method and a memory circuit of the above kinds are known from US-A-4 549 284. According to this prior document a dynamic random access memory (DRAM) has an automatic refresh circuit which consists of a clock generator that generates refresh clock pulses when an access strobe signal is not produced, and an address counter that increments a refresh address by counting the refresh clock pulses. Succeeding refresh cycles may be triggered by an oscillator circuit. DRAMs include memory storage cells that store data on capacitors. Charge or lack of charge on these capacitors is used to represent logic "1" or "O" data states. The capacitors are susceptible to charge leaking off (or on) over periods of time, typically milliseconds, and must therefore be refreshed or restored to their representative data states periodically. DRAMs are constructed of or organized into one or several memory cell arrays or subarrays consisting of rows and columns (which correspond to word lines and bit lines). When a row is selected during an active cycle, all of the cells along that row are sensed and restored. An active cycle is when the memory cells are accessed by word lines to read, write or refresh, for example. Then a precharge cycle is performed, which is not part of an active cycle, to ready the memory array to enter another active cycle. To refresh the entire array, also done during an active cycle, generally only the rows need to be selected. All the capacitors of the memory cells along a row or portion of a row are refreshed when that row is addressed. (That is, all of the columns are operative during refresh.) Row selection can be done by cycling through all the row addresses with a row address strobe signal ("RAS"), or any standard read/write cycle. For example, column address strobe before row address strobe (CAS before RAS or "CBR") cycling provides the row address internally from refresh counters so that each row will be selected and refreshed. The external signal RAS , supplied by a system and provided externally of the memory package, is generally used to control many functions of a DRAM. One of its uses is analogous to a chip select signal as used by other types of chips. If the external signal RAS remains low for a long enough time, all of the active cycle clocks will operate in proper sequence, terminate and then wait for a user command, such as reading or writing new data by toggling CAS , or returning to precharge by bringing RAS high. As illustrated in Figs. 1 (a) - (k), active cycle events of conventional DRAMs are started with the falling edge of an external signal RAS (see Fig. 1(a)). For a refresh active cycle, the falling edge of the external signal RAS triggers an internal signal RAS ' (Figs. 1 (a) and (b)). Internal signal RAS ' is the main control signal of the internal functions of a memory part, and is illustrated as active low. The falling edge of RAS ' triggers an internal address signal ADD, which triggers a precharge clock signal  P and a shorting clock signal  SH (Figs. 1 (b), (c), (e) and (f)). Internal address signal ADD (shown as active high in Fig. 1(c)) allows the address, supplied externally or by internal counters, to be input to memory row decoders of the memory. Precharge clock signal  P is a representation of one or more precharge clocks used to trigger precharge functions of the memory device. As shown in Fig. 1 (e), precharge clock signal  P is active high, that is, when  P is high, the memory circuitry is precharged. Shorting clock signal  SH is used to trigger the shorting of the bit lines during precharge. The bit lines are shorted together to so that small amounts of charge from the memory cells can be sensed when a memory cell is selected. Shorting clock signal  SH is illustrated in Fig. 1(f) as being an active high clock. That is, when  SH is high, the bit lines are shorted. Internal address signal ADD triggers a word line signal WL as shown in Figs. 1 (c) and (d). Essentially, word line signal WL is generated from the decoded address that internal address signal ADD allowed to pass to the row decoder. WL is one of many word lines or rows in a memory cell array (for example a typical 4 meg DRAM can be configured as 1024 rows by 4096 columns). Word line signal WL triggers a sense clock signal  S (Figs. 1 (d) and (g)). Sense clock signal  S represents one or more sense clock signals which are used to enable sense amplifiers of the memory to read corresponding bit lines. As seen in Figs. 1(g)-(i), sense clock signal  S triggers a latch signal LN and a latch signal LP, which have active states that are low and high, respectively. Latch signals LN and LP are sense amplifier driver signals that control the bit line sense amplifiers. When the sense amplifiers latch, each bit line connected thereto is driven either high or low, depending on the voltage of that bit line (or the differential in voltage between the two bit lines). Driving the LP and LN lines high or low serves to latch the logic value present on the bit lines as shown in Fig. 1(h)-(j) which will restore full levels back into the memory cells. Typically, a restore finished signal RF is triggered when latch signal LP reaches a predetermined level. At this point the memory array is ready to enter a precharge cycle. A precharge cycle generally will not start as long as the external signal RAS remains low. When the user or system causes the external signal RAS to go high, if the signal RF is high, then the precharge cycle begins. The precharge cycle will complete itself if the external signal RAS remains high long enough. The right side of Figs. 1 (a)-(k) shows a timing sequence for a precharge cycle for a conventional DRAM. External signal RAS triggers internal signal RAS ' to become inactive. Figs. 1 (a), (b). RAS ' triggers internal address signal ADD to become inactive and precharge clock signal  P to become active, as shown in Figs. 1 (b), (c) and (e). Precharge clock signal  P triggers word line signal WL to become inactive. See Figs. 1 (d) and (e). Figs. 1 (d) and (f) show that word line signal WL triggers the shorting clock signal  SH to become active and sense clock signal  S inactive. Shorting clock signal  SH triggers the latch signals LN and LP to become inactive, and bit line and bit line bar signals BL/ BL to a precharged state, as shown in Figs. 1 (f) and (h)-(j). The precharged state of bit line and bit line bar lines BL/ BL is typically VCC/2 (where VCC is a power supply voltage). Figs. 1 (a)-(k) show one cycle for refreshing and precharging one row address. It is important to note that external signal RAS is controlled by the user or system. After a row is accessed and restored, the user or system must change the state of external signal RAS . When external signal RAS changes, the precharge cycle is triggered. After the precharge cycle is completed, the memory waits until the user or system changes the state of external signal RAS to start yet another active cycle. For conventional DRAMs, a time margin is added when specifying how quicky RAS can cycle or change. That is, minimum high and low times for the external signal RAS are specified for worst case operating conditions. At nominal or typical operating conditions, the time margin is wasted since internally the memory is operating faster. This time could be saved if the memory would, for at least refreshing purposes, automatically enter precharge when the active cycle is completed and then automatically enter the active cycle when precharge is completed. This would tend to minimize the cycle time for any given operating voltage and temperature. Conventional DRAMs are driven or controlled by memory controller devices that are not part of the memory chip. These devices control the functions of the memory, such as read, write and refresh. Memory controller devices are typically quite complex to furnish the refresh operation for a DRAM. In the instance where the memory part uses CAS before RAS refreshing, the memory controller must supply column and row address strobes for each row that is to be refreshed. For a 4 megabit memory array, the memory controller would have to provide 1024 CAS before RAS cycles to refresh the whole memory. In one prior patent to Malik and Celio, U.S. Patent 4,503,525 entitled "Common Circuit For Dynamic Refresh And System Clock Function," a memory is controlled by a RAM controller. That patent seeks to use the dedicated system clock (which is external to both the RAM and the RAM controller) to control the refresh operation of the RAM, in addition to its basic use as a time-of-day counter. It is known also to use counters located on the RAM chip itself for refreshing. For example, Ikuzaki USP 4,549,284 is an example of prior art which does not use self-timing. Rather, it uses timers and fixed delays. The timers are used to enter the active cycles and the precharge cycles. White et al. U.S. Patent 4,494,222 is for a processor with an on-chip refresh address system for dynamic memory. In that refresh system for DRAMs, White uses no self-timing. White uses internal address counters to supply row addresses for refreshing so that external addresses are ignored. In one embodiment, mentioned at column 5, lines 31-44, a counter sequences through 256 possible row addresses, one at a time, but the address in the sequential counter changes each time a refresh clock ΦR' appears. ΦR' is derived by a control circuit from a signal ΦR from an on-chip generator. The bottom passage of column 5 indicates that in a refresh cycle, which is shown in the central part of Figure 6, no addresses are latched in, and the device refreshes "all 256 bits in the selected row." Col. 5, ln. 66. However, White's associated timing diagram of Figure 6 does not show multiple ΦR' signals being generated. It is therefore questionable whether all rows of the memory are refreshed in that embodiment described with respect to Figure 5 of White. With regard to the earlier embodiment of White, which is described at column 3, White notes "the address in the sequential counter changes each time an RF signal appears on a chip input pin 35." Col. 3, lns. 65-67. Consequently, that embodiment must cycle the external control signal RF to refresh sequential rows of memory. There have been some references to self-timing.For example, some DRAMs have a battery back-up mode where a refresh counter is used in the process of addressing rows for refreshing the DRAM, in a low power operation. Such systems are not directed to high speed operations but rather to conserving power. See , for example, Konishi et al. "A 38ns 4Mb DRAM with a Battery Back-up (BBU) Mode," ISSCC 90 pp. 230 et seq. ("The BBU mode is a kind of self refresh mode ... As a result all memory cells are refreshed within 4096 cycles per 256 msec in the BBU mode.") Nagami USP 4,500,974 uses a dummy column to detect when the full restore of the memory cells along one row has occurred. He detects the low level on either side of the column sense amplifier and times the end of the active cycle off of this level. Nagami does not self-time the precharge. He refreshes only one row, then enters the precharge cycle, and waits there. This does not solve the problem at hand. Therefore, it is a general object of the present invention to overcome the above-mentioned drawbacks and reduce complexity. Another object of the present invention is to make semiconductor memories, especially DRAMS, more accessible to typical computer systems by reducing the time required for refresh operations. An object of this invention is to create an operation, which is called a "burst refresh mode" (BRM), in order to refresh the data in a given DRAM in as little time as possible. Whereas many users employ CAS before RAS refreshes to restore the data, another object of the invention is to allow the CAS before RAS cycles to be fewer in number or faster in cycle time, or both, so that the user has less of what the art refers to as "refresh overhead." According to the invention the above objects are achieved by the method of Claim 1 and the memory circuit of Claim 11. This invention provides burst refresh mode ("BRM") circuitry to decrease the amount of time required to refresh a memory array. The invention is applicable to DRAMs, ferroelectric RAMs, and any other semiconductor RAM that can benefit from periodic refresh. A preferred embodiment of the present invention includes an internal address counter, another counter to count how many addresses have been accessed, and detection circuitry used to self-time the cycles of a memory array. The internal address counter is used to provide addresses to the address decoder faster than would be possible by providing the addresses from the external pins. The present invention may also include a variable address circuit to increase the number of addresses accessed during an active cycle, thereby to reduce the number of addresses to be supplied. This further reduces the time needed to refresh the memory device. A novel and important aspect of the operation of such burst refresh mode circuitry is its ability to reduce the amount of time for a memory array refresh without complicating the user or system interface with the memory part. Another important aspect of such circuit is that it reduces the amount of circuitry required by the given (host) computer system memory controller, which will now need to provide fewer functions. The invention also includes a method for operating a burst refresh mode circuit. A method of operating the circuit may comprise combining the steps of: (1) entering or initiating burst refresh mode; (2) self-timing the active cycle; (3) self-timing the activation of the precharge cycle and start of next active cycle; and (4) providing addresses from an internal counter. In its preferred implementation, burst refresh mode circuitry is provided for a DRAM memory having volatile cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refresh in the burst refresh mode. Battery back-tip mode circuitry is partially disabled. The invention, together with its objects and the advantages thereof, may better be understood by reference to the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a timing diagram for conventional refresh and precharge cycles of a DRAM; and Fig. 2 is a block diagram of a preferred embodiment of the present invention; Fig. 3 is a schematic diagram of the preferred embodiment of block 140 (burst refresh mode entry circuit ) of Fig. 2; Fig. 4 is a schematic diagram of the preferred embodiment of block 130 ( SH delay circuit) of Fig. 2; Figs. 5A and 5B are schematic diagrams of the preferred embodiments of blocks 132 and 136 (the auto refresh burst refresh mode circuits) of Fig. 2; Figs. 6A and 6B together show a schematic diagram of the preferred embodiment of block 134 (burst refresh mode logic circuit) of Fig. 2; and Fig. 7 is a set of timing diagrams for refresh and precharge cycles of a DRAM implementing the preferred embodiment of the present invention. The present invention preferably includes a method of and apparatus for entering the burst refresh mode after the memory device is finished with its precharge cycle. There are many ways in which this may be done, and the present invention is not limited to the exemplary methods described infra . A first way to enter the burst refresh mode is to have circuitry responsive to a change in an input pin voltage. For example, if the user or system were to raise the voltage of a given input pin to above the power supply voltage VCC, to 1.5 VCC, illustratively, the circuitry would construe this as an instruction and initiate a burst refresh mode once the last precharge cycle is completed. Another way is to use an extra pin of the memory package to provide a signal to the circuitry that will place the memory device in a burst refresh mode. For instance, the circuitry could receive the pin signal and cause the memory device to enter burst refresh mode once the last precharge cycle is completed. A further way to initiate a burst refresh mode is to send a prescribed sequence of signals through already established package pins. For instance, active write and output enable signals may be provided before a column address strobe before row address strobe ("CBR") signal. Another approach would be to provide an active address bit before a write enable signal. The write enable signal would in turn be provided before a CBR signal. The selection of signalling conditions can be varied within the scope of the present invention. BLOCK DIAGRAM Figure 2 shows a simplified block diagram of relevant portions of a DRAM 100 according to a preferred embodiment of the present invention. Figure 2 may be read in conjunction with timing charts of Figure 7 described infra . Starting at the top left, a RAS buffer 102 receives an input from a RAS pad 103. Buffer 102 develops an internal RAS ' signal, the state of which is a function of at least three things. One is the polarity of the input pad 103. Another factor is whether the system is in self refresh mode (so that the RAS buffer 102 would be controlled with block 136, described infra ), or whether the system is in burst refresh mode (so that it is controlled by a block 132 described infra through auto refresh signals). Buffer circuit 102 provides signal RAS ' to a set of address buffers 104. Associated with address buffers 104 is refresh counter circuitry 106. Refresh counter 106 provides address bits of real addresses that will be refreshed. It transfers those addresses to the address buffers. Signals RAI and its complement RAI are shown on Fig. 2. "RAI" denotes Refresh Address I(th). In a typical 4 meg DRAM, I would index from 0 to 9 to produce ten real addresses. The two signals RAI and RAI are duplicated for each of the addresses. In a 4 meg DRAM, there would be ten such pairs of addresses and refresh counter combinations, which would be indexed 0 through 9. At the trailing edge, for example, of a signal to the address buffers 104, all ten of the refresh counters (illustratively) in a 4 meg DRAM, provide row addresses of the next row that is required to be refreshed. This occurs for rows 1 through 2 10 (1024 rows). Preferably no individual bits are addressed here, just rows. An output of address buffer circuit 104 is a set of internal addresses ADD applied to row decoders 108. The row decoders decode the row from the address information and activate illustratively a single word line by providing an output signal WL to sense amplifier circuitry 110. There are of course numerous sense amplifiers 110 in a large integrated circuit memory, and each such sense amplifier generally is coupled either directly or selectively to memory cells illustrated generally by reference numeral 112. A representative complementary bit line pair BL, BL is shown communicating with sense amplifiers 110. It should be noted that the present invention can be used more fully by incorporating the invention for a DRAM VARIABLE ROW SELECT described in U.S. Patent 5,331,601 based on serial no. 08/013,333 filed on February 4, 1993. This allows the row decoders to access two (or more) rows simultaneously. While the same sense amplifier does not read two different rows at the same time, the architecture of the device can access different arrays at one time. The RAS ' signal from circuit 102 is applied also as an input to a precharge circuit 120. Another input to precharge circuit 120 is the address signal ADD from address buffer circuit 104, which tells circuit 120 that it can exit or terminate precharge for that partition or block of the RAM. Circuit 120 then activates the precharge clock signal  P to unshort the array in the sense amps and to get ready to start sensing. Precharge clock signal  P from circuit 120 is shown in Fig. 2 as an input to sense clock circuitry 122. The word line signal WL is also inputted to circuit 122, which provides a sensing signal  S that is applied as an input to latch P and latch N generator circuits 124. Reference may be had to United States Patent 5,334,890 based on serial no. 07/969,418 filed October 30, 1992 in the name of Kim Hardee for a SENSE AMPLIFIER CLOCK DRIVER and to U.S. serial no. 07/976,312 filed November 12, 1992, also by him, for a SENSE AMPLIFIER WITH LOCAL WRITE DRIVERS , and the corresponding EP publications EP 595050 and EP 597231.The outputs LN (latch n) and LP (latch p) of generator 124 are applied to the sense amplifiers 110, preferably as the power supply thereto. That is, Latch P can be provided to the source-drain path of p-channel FETs in a CMOS sense amplifier and Latch N would correspondingly be provided to the n-channel FETs thereof. Latch P and latch N are activated or turned on through block 124, thereby allowing the sense amplifier(s) 110 to sense and refresh the memory cell(s) 112. Preferably, the signal Latch P is applied to restore circuitry 126 which provides a Restore Finished signal RF. That signal is used to automatically time the end of that restore operation. This circuit preferably works in such a way that when Latch P has gone to a high enough level, then restore circuit block 126 senses that it can fire the RF clock (restore finish clock) and send that information to burst refresh mode logic described infra . Circuit 126 determines that the restore is finished because Latch P is a clock that latches the sense amps, and when the sense amps are latched, then that level is written back into the cells. If that level (of Latch P) is high enough, then one can assume that the restore is finished (for that row). The restore finish signal RF is applied to circuit blocks 132 and 136 in Fig. 3 to tell the system to bring RAS ' high in the precharge. Latch P/Latch N generator circuitry 124 mentioned above receives a signal from shorting clock circuitry 128. The inputs to circuit 128 include the address signal ADD from address buffers 104, the precharge timing signal  P from precharge circuit 120, and the word line signal WL from row decoders 108. Shorting clocks circuit 128 contains the required logic and drivers to turn off "shorting" clock signal  SH if the  P clock goes to its inactive state and the proper address of the particular memory block is valid. Circuit 128 also controls the turning on of  SH by sensing the level of the WL input. "Shorting" clock signal  SH is applied to the generator circuit 124, to sense amplifiers 110, and to a delay circuit 130. Delay circuit 130 produces a delayed shorting signal D  SH that is applied as an input to a circuit 132 which is one of two Auto Refresh Burst Refresh Mode ("ABRM") circuits shown on Fig. 2. The other ABRM circuit is circuit 136. Delay circuit 130 tracks the equilibration of the bit lines and latch clocks. It is noted that at hot operating temperatures or high operating voltages where shorting takes longer, the delay in circuit will also be longer. Therefore, the delay affords adequate time for the precharging of LN and LP lines and the bit line pair. Circuit 132 receives several further inputs including: a signal from burst refresh mode logic 134, the restore finished signal RF from restore circuitry 126, and a battery back-up mode signal BBUM. Circuit 132 provides an auto refresh signal AREF (sometimes referred to as AUTO REF) to circuits 102 and 134. A burst refresh mode bar signal BRMB from logic circuit 134 enables circuit 132 to become active. Circuit 136 receives a RESET signal from RAS buffer 102, a toggle signal TOG, the battery back-up signal BBUM, and the restore finished RF from restore circuit 126, as well as generating the auto refresh signal AREF similar to circuit 132. The BBUM signal will enable circuit 136 to drive AREF and disable circuit 132 from driving AREF. Thus it will be understood that in the illustrated embodiment, both circuits 132 and 136 are capable (separately) of generating auto refresh signal AREF, given the appropriate conditions. Such a signal can be provided in the battery back-up mode (BBU mode) or in burst refresh mode (BRM). As shown in Figs. 5A and 5B, described infra , it is preferred that only one of the two circuits 132 and 136 should be able to generate AREF at any given time. Shown at the bottom of Figure 2 is a burst refresh mode entry circuit 140 receiving a signal CASB from a "CAS buffer bottom" circuit 142 and a signal WEB from a "write buffer bottom" circuit 144. Here, "bottom" refers to the physical bottom of the chip, which is not particularly important for the present invention. Circuit 140 further receives an address signal A0 from an A0 address pad 147. Circuit 142 receives an input from a CAS pad 143. Circuit 144 receives an input from a write enable WE pad 145. Block 142 produces signal CASB, and block 144 produces signal WEB. These are two of four different clocks applied as inputs into the burst refresh mode entry block 140. Buffers 142 and 144 basically convert a TTL level to a CMOS level for internal use. Circuit 140 is used to detect the conditions for entry into the burst refresh mode. While various conditions could be used to signal entry into such a mode of operation, as noted supra , this mode in the preferred embodiment is initiated when the signals at the CAS 143 pad and write enable pad 145 are both low and address bit A0 at pad 147 is high before the RAS pad 103 (voltage) falls low. If that occurs, then burst refresh mode entry circuit 140 brings its output signal BRM INIT to the valid (active) state and the system enters burst refresh mode. This now-active BRM INIT signal is applied to burst refresh mode logic 134. Circuit 134 includes counters to determine how many burst refresh mode cycles occur internally on the chip. By counting the correct number of cycles (rows), the system can determine when the entire memory has been refreshed and can exit burst refresh mode at that time, thereby to await further instructions, or in an alternate embodiment could begin another sequence of refreshing. Circuit 134 also provides signal BRMB to control circuit 132. Circuit 132 is one of the two circuits that produces the actual control signal AREF that is applied to RAS buffer 102. Signal AREF controls the timing for RAS ' to go automatically into active cycles and automatically go into precharge cycles as required. (In this circuit, when RAS ' is high, the system is in precharge or standby, and when RAS ' is low, the system is in the active state.) Circuit 132 has knowledge of whether the system has entered burst refresh mode, as determined by blocks 140 and 134. Circuit 132 also determines whether it needs to change the state of the internal RAS signal , i.e. whether the system needs to go from a precharge cycle to an active cycle or vice versa . Such determination involves using the restore finish signal RF and the output D  SH of circuit 130. It will be recalled that when the restore finish signal RF goes high, this causes or allows block 132 to send a signal to the RAS buffer 102 for the internal RAS signal to go high because one row (or more) has been refreshed and that one active cycle is over. Now the system precharges for the next row selection. Signal RAS ' will go high and the system will go through similar clock logic and wrap back around such that signal D  SH will then tell the system that the precharge cycle is finished and that another active cycle now needs to be started. In this way, the system self-times the precharge cycle. Block 136 is an auto refresh block that already exists on common DRAMs today to control what is called "battery back-up mode." It is adapted for use in the preferred embodiment of this invention, but the invention can be practiced without this particular circuit. This circuit is shown receiving a clock signal TOG (a toggle bit) and a battery back-up mode signal BBUM which come from battery back-up mode logic. Block 136 will be disabled when using the present invention, but in the preferred embodiment, it appeared that the system could conveniently use the same auto refresh clock signal as would be generated from circuit 136. Hence, the key new circuit blocks shown in this Figure 2 are the burst refresh mode entry block 140, burst refresh mode logic block 134, the timing signal delay block 130, and the auto refresh burst refresh block 132. CIRCUIT DIAGRAMS Figure 3 shows the circuitry for the burst refresh mode entry circuit 140. The inputs are on the left: the A0 pad 147, a write enable input 204 (this one is WENPG, which stands for "write enable, no power gating.") The next input 206 is CAS ' middle. RAS ' is the fourth input 208. The output 210 is a burst refresh mode initialize signal BRM INIT. Thus, circuit 140 accepts the four inputs and detects whether or not this write CAS A0 before RAS clock sequence has occurred so it knows whether or not it should send a valid signal out for burst refresh mode BRM INIT. The A0 pad 147 is the lowest level address bit coming from the user, which is a pin on the package. Hence, in the preferred embodiment, circuit 140 is mainly a detector that is arranged to detect the right combination of four particular input signals, as shown on the left side of Figure 3. Figure 4 shows circuit 130 which is the  SH delay block. This receives the shorting clock  SH at input node 220 and generates a delayed signal D  SH at output node 222. In the preferred embodiment, this is done by taking an input and delaying it on the rising edge of  SH to generate a delay such that the falling edge of D  SH will occur later, illustratively about 10 nanoseconds. While a delay can be generated by passing a signal through a succession of inverters, in the preferred embodiment, a constant current source 224 is combined with an RC delay circuit. Fig. 4 shows an MOS capacitor 225 and the resistor 226 within current source 224. Part of circuit 130 functions to detect that the bit lines and the latch lines have started to be shorted together and to allow enough time for that shorting process to reach completion. Hence it is preferred that a circuit such as this be used and that it will track changing conditions. When VCC is very high, the equilibration of the bit lines and latch clocks actually takes longer since the voltage difference before  SH goes high is larger than when VCC is low. This equilibration also takes longer when the circuit operating temperature rises. Circuit 130 provides a longer delay with high VCC and/or with increased operating temperature. Thus, in the preferred embodiment, circuitry is provided to detect the state of  SH and then measure out a delay. Figure 5A shows the new auto refresh generator block 132. When in burst refresh mode, this block 132 generates an auto refresh signal AREF that will control the times for RAS ' to go high and low. Circuit 132 as shown in Fig. 5A receives its input signals BRM at a node 250, D  SH at a node 252, RF at a node 254, and BBUM at a node 256. The output of this circuit is the signal AREF at a node 258. Circuit 132 contains a latch circuit 260. It may be noted that if the system enters battery back-up mode, then the auto-refresh circuitry of circuit block 132 is disconnected and isolated from the circuit. Battery back-up mode is a mode of refreshing the DRAM and it differs from the present invention in at least the respect that battery back-up mode refreshes the memory with minimum power rather than maximum speed. If the system is in neither burst refresh mode nor battery back-up mode, then circuit 132 pulls AREF low. The battery back-up mode signal BBUM at node 256 together with BRM at node 250 and transistors 262-274 disables AREF at output node 258 when not in battery back up mode or burst refresh mode. If the system is in burst refresh mode, then the input voltage at node 250 will be low. This will enable the signal at input node 252 to be seen as an input to this circuit. When that clock goes low, then it sets a latch 260 and drives the AREF signal high. This will cause the RAS ' to enter an active cycle. When the RF input at node 254 fires, then it sets auto-refresh signal AREF low by setting latch 260. In this way, self-timing occurs. If the system is in burst refresh mode, battery back-up signal BBUM will be low. That signal is inverted by transistors 266 and 268 which would turn on transistor 274 to lock AREF low. However, transistors 262 and 264 invert the active low input from node 250 thereby to turn on transistor 272. That grounds the gate electrode of transistor 274 and permits AREF to become active. Fig. 5B shows a preferred embodiment of circuit block 136. As shown in both Fig. 2 and Fig. 5B, this circuit receives the RESET signal from RAS buffer 102, the restore finished signal RF from circuit 126, the toggle input TOG, and the battery back up mode signal BBUM. Circuit 136 can generate an auto-refresh signal AREF at an output node 280 and a DRESET signal that is applied to RAS buffer 102. When the DRAM is in the battery back-up mode, AREF at output node 280 becomes an active signal, and toggles in accordance with inputs TOG and RF. The input signal RESET and the output signal DRESET (delayed reset) are used in exiting from battery back-up mode. It should be noted that circuit 136 does not receive the BRMB signal from circuit block 134 (Figs. 2, 6A, and 6B) and therefore does not produce any AREF output signal when the DRAM enters burst refresh mode. Rather, the AREF signal is produced by circuit 132 shown in Fig. 5A, at output node 258 thereof, as already described. Figs. 6A and 6B show the burst refresh mode logic 134, which provides the signal BRM to input node 250 in Fig. 5A. The burst refresh mode initialize signal BRM INIT from output node 210 in Fig. 3 is applied to input node 300 in Fig. 6. When that input signal is active, it sets a latch 302. Via inverters 304 and 306, this will also drive the burst refresh mode bar signal BRM low so that will tell circuit block 132 (Fig. 2) that the system is actively in burst refresh mode. The signal will also be used to control a bank of counters 310-319. Counters 310-319 are marked as blocks XC0 through XC9 which are symbols representing counter bits. These are used to count how many burst refresh mode cycles have occurred, so that the whole array can be refreshed. Fig. 6B shows eight circuit blocks 320-327 which represent AND gates used to generate toggle inputs T to the counters 310-319. Counter bit C0 is the least significant bit so the T input to counter 310 is shorted to VCC. This will cause c0 to change states with each CNT cycle. C1 is the next bit and will change states on CNT cycles when c0 is high, so c0 is used for its T (toggle) input. AND gate 320 causes t2 to go high when C0 and C1 are both high. This causes C2 to be the next order bit. Gate 322 generates t3 which is valid when C2, C1 and C0 are all high (since t2 is C0 and C1). This logic is continued up to t9 which is generated by AND gate 327, the logical AND of all lower order c bits, c0 to c8. Signal BRM INIT will start the counters 310-319, which will count how many rows are selected by using AUTO REF (see input node 312) as the input so every time that AUTO REF goes high, it will toggle another bit in the counters. Thus, the system does not have a clock driving the counters. Rather it counts the number of auto refresh cycles that have occurred, based on the number of times RF and D  SH change state. Figure 6A also shows that a burst refresh mode finish signal BRMF is generated as an output 330 from the last counter 319. That signal is used to gate a transistor 332. When the last carry bit goes high, then it will change the state of latch 302 and turn it off. It can be seen that when BRMF goes high, transistor 332 turns on to pull a node 334 low. This is inverted by transistors 336 and 338 to drive a node 340 high. That high signal is twice inverted by inverters 304 and 306, thus driving BRM high , i.e. to the inactive state. OPERATION Figs. 7 (a)-(s) illustrate a timing sequence of a refresh and a precharge cycle utilizing the present invention. Signals in Figs. 1 and 7 having the same function are designated the same. Fig. 7(a), (b), (c) and (d) show four externally applied signals WE , CAS , A0 and RAS respectively. When the timing of these four signals is as shown, burst refresh mode initiate signal BRM INIT (Fig. 7e) goes active. The first rising edge of AREF keeps the internal RAS ' low and isolates the RAS pad from internal RAS ' . This allows RAS pad to become a "don't care." Fig. 7(d) shows that external signal RAS is preferably in a "don't care" state once burst refresh mode initiate signal BRM INIT is activated. Burst refresh mode signal BRM INIT triggers signal BRM . When BRM goes low, auto-refresh signal AREF goes high as shown in Figs. 7(f) and (g). Auto-refresh signal AREF is substituted for the external signal RAS (Fig. 1(d)). This is done to remove the external control of internal signal RAS '. Auto-refresh signal AREF triggers internal signal RAS ' to become active, as shown in Figs. 7(g) and (h). Internal signal RAS ' triggers internal address signal ADD to become active which triggers precharge clock signal  P to become inactive, as shown in Figs. 7 (h), (i) and (k). Internal address signal ADD triggers word line signal WL to become active, as shown in Figs. 7 (i) and (j). Word line signal WL triggers sense clock signal  S to become active, as shown in Figs. 7 (f) and (i). Internal address signal ADD triggers shorting clock signal  SH to become inactive, as shown in Figs. 7 (i) and (l). Shorting clock signal  SH triggers delayed shorting signal D SH to become inactive, as shown in Figs. 7 (l) and (r). Sense clock signal  S triggers latch driver signals LN and LP to the active state, as shown in Figs. 7 (n) - (o). Both latch signals LN and LP trigger bit line and bit line bar signal BL/ BL to be active. The LP signal triggers restore finish signal RF to become active, as shown in Figs. 7 (o) and (q). Restore finish signal RF triggers auto-refresh signal AREF to the inactive state, as shown in Figs. 7 (g) and (q). As illustrated in Figs. 7(g) and (h), inactive auto-refresh signal AREF triggers internal signal RAS ' to become inactive. Inactive internal signal RAS ' triggers internal address signal ADD to become inactive and precharge clock signal  P to become active, as shown in Figs. 7(h), (i) and (k). As illustrated in Figs. 7(j) and (k), active precharge clock signal  P triggers the WL inactive. The WL then triggers the sense clock signal  S inactive as shown in Figs. 7(j) and (m). Clock signal  SH triggers the restore finished signal RF inactive as shown in Figs. 7(l) and (q). Inactive word line signal WL also triggers shorting clock signal  SH active as shown in Figs. 7(j) and (l). Active shorting clock signal  SH triggers latch signals LN and LP and bit line and bit line bar signal BL/LB to become inactive, and delayed shorting clock signal D SH to become active, as shown in Figs. 7(l), (n), (o), (p) and (r). Active delayed shorting signal D SH triggers auto-refresh signal AREF active as shown in Figs. 7(g) and (r). The foregoing description explains a burst-refresh mode for a single row. Briefly, when auto-refresh signal AREF changes to an active state, the row address is supplied, preferably by the internal counters 310-319 of Fig. 6A. The row is accessed and the data values on the bit lines are sensed. When the refresh finished signal RF changes to an inactive state, the memory array has left the access mode and is now in the restore mode. When the delayed shorting signal D SH transitions preferably to an active state, the row is through with precharge. Further, the delayed shorting signal D SH self-times the next refresh of another row by triggering the auto-refresh signal AREF, specifically, the trailing edge of D  SH triggers the next rising edge of AREF, as seen in Figs. 7(r) and (g). The first AREF signal was caused by the BRM leading edge. The burst refresh mode cycles are faster than regular access cycles since the address used to select which rows are refreshed comes from refresh counters instead of externally supplied signals. Because of the location of the refresh counters and required logic for external signals, this can save several nanoseconds in each cycle. The self-timed feature of this invention also reduces the time required to complete refresh while in burst refresh mode. This allows the circuit to go as fast as it can while eliminating the need for clock margins required when externally supplying the clocks over temperature and voltage operating ranges. These two items can save roughly 15% off a conventional DRAM refresh cycle. To further increase speed of refreshing during the burst refresh mode of the present invention, a variable select row address circuit may be implemented. An example of such a variable DRAM row select circuit is disclosed in EP publication 609577 which is based on U.S. application serial No. 08/013,333 filed February 4, 1993 entitled DRAM VARIABLE ROW SELECT , now U.S. Patent 5,331,601. The use of such a circuit as disclosed in the above-identified US patent and EPO application effectively increases the speed of the refresh by Increasing the number of addressed rows. Briefly, the circuit is configured so that it can block an address bit and provide an active address signal to an address decoder in place of the blocked address bit. This will cause more rows to be addressed than if that address bit were inactive. Such configuration, as disclosed, would double (or more) the minimum number of rows addressed for each address bit blocked. Hence, the number of rows can be effectively increased for refreshing and therefore the amount of time to refresh would be diminished by, for example, a factor of two. To refresh 4 million bits using this arrangement and technique would require on the order of 100 nanoseconds per row (selecting a row, restoring its data, turning off the row, and precharging the bit lines and latch circuitry) times 512 rows, i.e. 50 microseconds. The typical format DRAM architecture is configured with 1,024 rows. The foregoing calculation assumes that the system would select two at a time, 512 selections occur. This results in a time savings of about 50%. The total time required to refresh a dynamic RAM with this invention can then be 85% of the 50% when adding in all the speed savings in the previous 3 paragraphs, or about 57% faster than conventional refresh cycles. Further, the present invention simplifies the user's circuitry or its operation because a memory controller used with a memory having the present invention will not need to provide the memory with 1,024 CAS before RAS cycles or 1,024 RAS only refresh cycles. Instead, the memory controller can simply initialize the burst refresh mode and wait for the invention to refresh the memory. The associated memory controller does not have to provide address inputs to the memory.

Claims: A method of refreshing an integrated circuit memory (100) comprising the steps of: detecting conditions for entering a burst refresh mode, and if said conditions are detected, then generating an auto-refresh signal (AREF); internally producing an internal address signal (ADD) and refreshing one or more rows of memory cells (112) based on said internal address signal (ADD); and repeating said step of internally producing an internal address signal (ADD) until all of the memory (100) has been refreshed; characterised by the steps of: internally detecting when said refreshing of one or more rows of memory cells (112) is substantially completed; and triggering a new refresh cycle in response to detection of the completion of a preceding refresh cycle; and repeating also said steps of internally detecting and triggering a new refresh cycle until all of the memory (100) has been refreshed. The method of claim 1 wherein said step of repeating includes indexing a count of rows that have been refreshed and terminating said burst refresh mode when all of the rows have been refreshed. The method of claim 2 wherein said step of indexing includes counting the number of times said auto-refresh signal (AREF) is generated. The method of claim 1 employing a variable row select function to select more rows for refreshing than in a normal mode of operation of the memory (100) so that each cycle refreshes more rows than are normally refreshed in normal mode. The method of any prior claim including detecting a set of prescribed conditions on one or more inputs to said memory circuit (100) upon entering a burst refresh mode. The method of claim 5 including detecting said prescribed conditions among an address bit, a column address signal and a write enable signal. The method of any preceding claim including detecting the condition of an electrical signal used during a sensing operation associated with said refreshing, and determining whether said electrical signal has reached a predetermined condition. The method of claim 7 wherein said memory circuit (100) uses a latch signal (LP) to latch sense amplifiers (110) within the memory (100), and wherein said condition is a voltage level of said latch signal (LP). The method of Claim 8 wherein said latch signal (LP) is a latch signal for activating p-channel transistors in sense amplifiers (110) of the memory circuit (100). The method of any preceding claim including counting the number of burst refresh mode cycles so that all of said rows of the memory circuit (100) are refreshed. A memory circuit (100) having a plurality of memory cells (112) arranged in rows and columns, a plurality of sense amplifiers (110) coupled to said columns of memory cells, a sense amplifier driver circuit (124) coupled to said plurality of sense amplifiers, a control signal circuit (102) coupled to receive an externally-applied control signal (/RAS), a refresh counter circuit (106), a plurality of address buffers (104) coupled to said control signal circuit and said refresh counter circuit (106), a row decoder circuit (108) coupled to said address buffers (104) and to said rows of memory cells, and precharge (120) and clock circuitry responsively coupled to said control signal circuit (102) for providing a precharge signal used to precharge the sense amplifiers (110), a burst refresh mode control circuit (134, 140) coupled to receive externally-applied signals and effective for determining whether the memory circuit (100) should enter burst refresh mode; characterised by a detector circuit (126) coupled to said sense amplifier driver circuit (124) to provide a refresh finished (RF) signal indicative that a refresh cycle is substantially completed; a selectively operable burst refresh node circuit (132) responsively coupled to said burst refresh mode control circuit (134, 140), the burst refresh mode circuit (132) being coupled to said control signal circuit (102) and coupled to receive said refresh finished signal (RF) from said detector circuit (126), said burst refresh mode circuit (132) being effective to carry out successive refresh cycles for refreshing rows of memory cells in response to successive ones of said refresh finished signal (RF). The memory circuit of claim 11 wherein said burst refresh mode circuit (132) includes a burst refresh mode logic circuit (134) providing a counting function to determine when all rows of the memory circuit (100) have been refreshed in the burst refresh mode. The memory circuit of claim 11 or 12 further comprising a delay circuit (130) coupled to receive a precharge clock signal produced by said precharge circuit (120) and to provide a delayed timing signal based thereon to said burst refresh mode circuit (132).

Inventors: PARRIS MICHAEL C, PARRIS, MICHAEL C.
Applicants: MOSEL VITELIC INC, MOSEL VITELIC, INC.
Application year: 1994
Main classification: G11C11
IPC codes: G11C11