Emitterfollower circuit and analog to digital converter using such circuit

Abstract: A plurality of comparators are arranged in parallel, and novel constructions are employed for emitter followers or like circuits of input circuits of the comparators or for reference voltage supplying circuits for use for those circuits, thereby to improve the differential linear distortion or some other characteristic and reduce noise without the input capacitance. Further, an ECL circuit for use for signal processing is provided with a power saving function to reduce the power dissipation.

Description: This invention relates to an emitter follower circuit which includes an emitter follower stage, a differentiation circuit and a first current mirror circuit as specified in the precharacterizing part of claim 1. An analog to digital converter of the parallel comparison type called flash analog to digital converter of the construction wherein a number of comparators, which have comparison voltages of different voltage values, equal to the number of bits of a digital signal are arranged for collectively determining the comparison voltages to find out a reference voltage equal to an analog input voltage commonly employs, at an input stage of each of the comparators, an emitter follower circuit which has the characteristics that the input impedance is comparatively high and that it is superior in interference suppressing capability for the preceding and following stages. An example of the construction of an analog to digital converter of the parallel comparison type is shown in FIG. 1. Referring to FIG. 1, a reference voltage generation circuit 1 includes, where a digital signal is constituted from, for example, 8 bits, 256 resistors r 1 to r 256 connected in series, for example, between lines V RT and V RB and generates reference voltages of different voltage values at 255 junctions between adjacent ones of the registers by potential division of the resistors. The reference voltages serve as comparison voltages for 255 comparators COP1, ... of a comparison circuit 2. An analog input voltage V IN is inputted commonly as an object voltage for comparison to the 255 comparators COP1, ... The 255 comparators COP1, ... collectively determine one of the comparison voltages which is equal to the input voltage VIN. The comparison outputs of the comparators COP1, ... are supplied by way of a gate circuit 3 to an encoder 4, by which they are converted into a digital signal D1 to D8 of 8 bits to be outputted. A conventional example of the circuit construction of the comparators of the analog to digital converter of the parallel comparison type described above is shown in FIG. 2. Referring to FIG. 2, an NPN transistor Q1 of an emitter follower to the base of which an analog input voltage V IN is inputted, another NPN transistor Q2 to the base of which a bias voltage V BIAS is inputted and a resistor R1 are connected in series between a GND line and a V EE line to construct an emitter follower stage 11 on the analog input side. A further NPN transistor Q3 of another emitter follower to the base of which a reference voltage V REF is inputted, a still further NPN transistor Q4 to the base of which the bias voltage V BIAS is inputted and another resistor R are connected in series between the GND line and the V EE line to construct an emitter follower stage 12 on the reference voltage input side. Meanwhile, a pair of differential transistors Q5 and Q6 whose emitters are connected common to perform a differential operation, a pair of resistors R3 and R4 connected between the collectors of the differential transistors Q5 and Q6 and the GND line, respectively, and a constant-current transistor Q7 and a resistor R5 connected in series between a common junction between the emitters of the differential transistors Q5 and Q6 and the V EE line construct a differential amplifier 13. In the differential amplifier 13, the analog input voltage V IN is applied by way of the emitter follower stage 11 to the base of the transistor Q5 of the differential transistor pair, and the reference voltage V REF is applied to the other transistor Q6 by way of the emitter follower stage 12. Comparison outputs are thus led out from the collectors of the differential transistors Q5 and Q6. Subsequently, a second related art will be described. An ECL output circuit having such a construction as shown in FIG. 3 is conventionally known as an ECL output circuit which has a power saving function. Referring to FIG. 3, a pair of differential transistors Q11 and Q12 whose emitters are connected common to perform a differential operation, a pair of resistors R11 and R12 connected between the collectors of the differential transistors Q11 and Q12 and a GND terminal 21, and a transistor Q13 and a resistor R13 connected in series between a common junction between the emitters of the differential transistors Q11 and Q12 and a V EE power source terminal 22, respectively, construct a differential amplifier 23. In the differential amplifier 23, the bases of the differential transistors Q11 and Q12 are connected to input terminals 24 and 25, respectively. Upon power saving (PS) operation, a PS signal is supplied to a reference voltage circuit 27 by way of a control terminal 26. The reference voltage circuit 27 applies, when a power saving operation is not to be performed, a predetermined reference voltage to the base of the transistor Q13 to turn the transistor Q13 into an on-state, but when a power saving operation is to be performed, the reference voltage circuit 27 turns the transistor Q13 into an off-state in response to the PS signal. Two outputs of the differential amplifier 23 are supplied to another differential amplifier 30 at the last stage by way of a pair of emitter follower circuits 28 and 29. The emitter follower circuit 28 includes a transistor Q14 whose collector is connected to the GND terminal 21 and whose base receives one of the two outputs of the differential amplifier 23, another transistor Q15 connected in a diode connection with the collector and the base thereof connected common to the emitter of the transistor Q14, and a further transistor Q16 and a resistor R14 connected in series between the emitter of the transistor Q15 and the V EE power source terminal 22. The emitter follower circuit 29 similarly includes a transistor Q17, another transistor Q18 connected in a diode connection, a further transistor Q19 and a resistor R16. A predetermined bias voltage V BIAS is applied from a variable voltage source 31 to the bases of the transistors Q16 and Q19. The differential amplifier 30 includes a pair of differential transistors Q20 and Q21 whose emitters are connected common to perform a differential operation, a resistor R16 connected between the collector of the transistor Q21 and the GND terminal 21, and a transistor Q22 and a resistor R17 connected in series between a common junction between the emitters of the differential transistors Q20 and Q21 and the V EE power source terminal 22. The predetermined bias voltage V BIAS from the variable voltage source 31 is applied also the base of the transistor Q22. The variable voltage source 31 is constructed so as to stop, upon power saving operation, generation of the bias voltage V BIAS in response to a PS signal. Consequently, upon power saving operation, the transistors Q16, Q19 and Q22 are put into an off-state. The collector output of the transistor Q21 is led out from an output terminal 32 by way of an output transistor Q23. In the emitter follower circuit 11 at the analog input stage of the construction described above, since the emitter of the transistor Q1 has a parasitic capacitance C P , there is a problem in that, if the through rate of the input voltage V IN is high, then the base-emitter voltage V BE of the transistor Q1 is varied by a charging or discharging current flowing through the parasitic capacitance C P , which gives rise to distortion in the emitter voltage of the transistor Q1. Meanwhile, in the analog to digital converter of the parallel comparison type, a number of, for example, 255 in the case of 8 bits, comparators of the construction wherein the emitter follower stages 11 and 12 and the differential amplifier 13 are provided in a one by one corresponding relationship are arranged in parallel to the analog input voltage V IN . However, in the comparator of the construction described above, since high currents flow, upon switching of the differential amplifier 13, through the bases of the differential transistors Q5 and Q6 and such current changes have a significant influence on the emitter current of the emitter follower stage 11, the conversion accuracy in analog to digital conversion is deteriorated. In order to reduce the influence of kickback noise from the differential amplifier, the current to flow through the emitter follower stage 11 should be increased. This, however, will give rise to an increase the current consumption. By the way, in an ideal analog to digital converter, an analog input voltage has the width of one LSB (Least Significant bit) for one digital code. In an actual analog to digital converter, the width may be greater or smaller than one LSB. The variation in width appears as a differential linear distortion (DLE). In order to reduce the differential linear distortion in the analog to digital converter of the parallel comparison type of the construction described above, it is required to effectively reduce the difference ΔV BE between the base-emitter voltages V BE of the transistors Q11 and Q13 of the emitter follower stages 11 and 12 constituting the input stages of each comparator. A conventional countermeasure for such effective reduction of the difference ΔV BE between the base-emitter voltages V BE of the transistors Q1 and Q3 of the emitter follower stages 11 and 12 is to increase the size of each of the transistors Q1 and Q3. However, if the transistors Q1 and Q3 of the emitter follower stages 11 and 12 are increased in size, then another problem takes place in that the input capacitance which has a significant influence on the conversion rate upon analog to digital conversion is increased, resulting in deterioration of the conversion accuracy. Besides, since the difference ΔV BE cannot be reduced below a limit provided by a process, there is a limitation in reduction of the differential linear distortion. Further, in the ECL output circuit of the related art of the construction described above, there is a problem in that, when the power saving function operates, the output level of the output transistor Q23 rises to a high level, resulting in increase of the power dissipation at the terminal end of the output. In particular, when the bias voltage V BIAS of the variable voltage source 31 approaches V EE upon power saving operation, the transistor Q22 is turned into an off-state. Consequently, only the base current of the output transistor Q23 flows through the resistor 16 so that the base potential of the transistor Q23 becomes substantially equal to 0 V, and as a result, the output level of the transistor Q23 changes to a high level. Here, if it is assumed that the present circuit terminates, for example, in a V TT power source of -2 V by way of a resistor of 50Ω as indicated by a dotted line in FIG. 3, then when the high level is -0.9 V, since the potential difference between the opposite ends of the resistor of 50Ω is 1.1 V, a current of 22 mA flows through the resistor of 50Ω, but when the low level is -1.8 V, since the potential difference between the opposite ends the resistor of 50Ω is 0.2 V, a current of 4 mA flows through the resistor of 50Ω. Accordingly, between the high level output and the low level output, a power dissipation difference of 36 mW (= 18 mA x 2 V) is produced for each output terminal. Prior art document Patent Abstracts of Japan, Vol. 11, No. 374 (E-562) & JP-A-62 141 820 discloses an input circuit for an A/D converter comprising emitter follower stages which have a current source connected as a load thereto, a reference voltage circuit for generating a plurality of reference voltages, a plurality of comparators for individually comparing an analog input signal with the plurality of reference voltages; and a capacitor connected between the input and output. This capacitor could function as a differentiation circuit for differentiating the input signal. Further, prior art document EP-A-0 293 833 discloses an emitter follower circuit comprising an emitter follower stage which has a variable current source connected as a load thereto and to which an input signal is supplied. A capacitor functions as a differentiation circuit for differentiating the input signal (T1, T2), and a current mirror circuit is paired with the variable current source for supplying a current to the variable current source in response to a differentiation output of the differentiation circuit. It is an object of the present invention to provide an emitter follower circuit which minimizes analog distortion arising from a parasitic capacitance. To solve this object the present invention provides an emitter follower circuit as specified in claim 1. A preferred embodiment of the invention is described in the subclaim. An analog to digital converter can reduce the influence of kickback noise from a differential amplifier without increasing the number of elements or the power dissipation of the circuit. Further, an analog to digital converter can reduce the differential linear distortion without increasing the input capacitance only by adding a simple circuit. An ECL output circuit can reduce the power dissipation upon power saving operation only by adding a circuit. Further objects, details and advantages of the invention will be apparent from the following description when taken in conjunction with the drawings, wherein: Fig. 1 is a block diagram of an analog to digital converter of the parallel comparison type of the related art; FIG. 2 is a circuit diagram of an emitter follower circuit of the related art which is employed for an input circuit or a like circuit; FIG. 3 is a circuit diagram of an ECL circuit of the related art; FIG. 4 is a circuit diagram showing an emitter follower circuit; FIG. 5 is a circuit diagram showing an example of the detailed construction of a control circuit which is an embodiment of the present invention; FIG. 6 is a circuit diagram showing an example of the detailed construction of a control circuit; and FIG. 7 is a circuit diagram showing an example of the detailed construction of another control circuit. In the following, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a circuit diagram showing an emitter follower circuit useful for the understanding of the present invention. Referring to FIG. 4, an NPN transistor Q31 of an emitter follower to whose base an input voltage V IN is inputted, another NPN transistor Q32 which serves as a load to the transistor Q31 and also as a variable current source, and a resistor R21 are connected in series, for example, between a pair of power source lines of a ground GND and a negative power source V EE to construct an emitter follower stage 41. In the emitter follower stage 41, the emitter of the transistor Q31 has a parasitic capacitance C P1 . The input voltage V IN is applied also to a terminal A of a control circuit 42. An input terminal of a differentiation circuit 43 is connected to the terminal A. The differentiation circuit 43 differentiates the input voltage V IN to convert the voltage variation into a current variation. In the control circuit 42, a constant-current source 44, an NPN transistor Q33 connected in a diode connection and a resistor R22 are connected in series between the GND line and the power source V EE line. An output terminal of the differentiation circuit 43 is connected to a junction between the constant-current source 44 and the collector (base) of the transistor Q33. The transistor Q33 connected in a diode connection is connected to the transistor Q32 of the emitter follower stage 41 commonly at the bases of them by way of a terminal B to construct a current mirror circuit. In the emitter follower circuit of the construction described above, if the emitter current of the transistor Q31 of the emitter follower stage 41 is represented by I E1 ; the emitter current of the transistor Q32 by I E2 ; the parasitic capacitance by C P1 ; the coefficient of the differentiation circuit 43 by k; and the current of the constant-current source 44 by I 0 , the following equation stands: I E1 = I E2 + C P1 · (dV IN /dt) = I 0 - k · (dV IN /dt) + C P1 · (dV IN /dt) Here, the constant k of the differentiation circuit 43 is equal to 0 when no current correction is performed, and in this instance, a charging current which increases in proportion to the through rate of the input voltage V IN flows through the transistor Q31 of the emitter follower stage 41. On the other hand, when k = C p1 , I E1 = I 0 , and accordingly, the emitter current I E1 of the transistor Q31 is fixed irrespective of the through rate of the input voltage V IN . Since the emitter current I E1 of the transistor Q31 can be adjusted in response to the through rate of the input voltage V IN by differentiating the input voltage V IN by means of the differentiation circuit 43 to convert the voltage variation into a current variation and controlling the current of the transistor Q32, which is a load to the transistor Q31 of the emitter follower stage 41, in response to the current variation as described above, a portion of the current which flows through the parasitic capacitance C p1 can be corrected with the through rate of the input voltage V IN . As a result, the variation of the base-emitter voltage V BE of the transistor Q31 caused by a charging or discharging current flowing through the parasitic capacitance C p1 can be suppressed, and consequently, an analog distortion which arises from the parasitic capacitance C p1 can be reduced. An embodiment of the present invention will be described subsequently. FIG. 5 is a circuit diagram of an example of the detailed circuit construction of the control circuit 42 in FIG. 4. Referring to FIG. 5, a resistor R33, a PNP transistor Q34 connected in a diode connection and a constant-current source 55 are connected in series between a GND line and a power source V EE line. A capacitor C C1 is connected between a junction point between the transistor Q34 and the constant-current source 55 and a terminal A. Meanwhile, a resistor R34 and a PNP transistor Q35 are connected in series between the GND line and the collector (base) of the NPN transistor Q33. A current mirror circuit is constituted from the transistor Q34 and the transistor Q35. In such circuit construction, since the collector voltage of the transistor Q34 can be considered to be substantially fixed, the current i flowing in from the capacitance C C1 is given by i = C C1 · (dV IN /dt) and where the current of the constant-current source 55 is represented by I 0 , a current I 0-i flows through the transistor Q34. Since the transistor Q34 and the transistor Q35 construct a current mirror circuit, where the emitter current is represented by I E3 , the emitter current I E3 given by I E3 = I 0 -i = I 0 - C C1 · (dV IN /dt) flows into the emitter of the transistor Q33. Here, if the capacitance C C1 is set to C C1 = C p1 , then the emitter current I E1 of the transistor Q31 of the emitter follower stage 41 can be made a constant. By the way, in actual use, it is required in most cases to employ the construction wherein n such emitter follower stages 41 are connected to the single control circuit 42. In this instance, the transistors Q33 and Q35 in the circuit of FIG. 5 should be multiplied by n, and the resistors R32 and R34 should be reduced to l/n. With the construction, there is an effect in that an analog distortion which arises from the parasitic capacitance C P1 in each of the n emitter follower stages 41 can be reduced by the single control circuit 42. Subsequently, a further embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing another example of the detailed circuit construction of the control circuit 42 in FIG. 4. Referring to FIG. 6, a resistor R43, an NPN transistor Q46 and a constant-current source 57 are connected in series between a GND line and a V EE line. A dc voltage E is applied to the base of the transistor Q46. A capacitor C C2 is connected between a junction between the transistor Q46 and the constant-current source 5 and a terminal A. An NPN transistor Q47 and a constant-current source 58 are connected in series between the GND line and the V EE line. The base of the transistor Q47 is connected to the collector of the transistor Q46. Meanwhile, a resistor R44 and an PNP transistor Q45 are connected in series between the GND line and the collector (base) of the transistor Q43. The base of the transistor Q45 is connected to the emitter of the transistor Q47. In such circuit construction described above, since the emitter of the NPN transistor (transistor Q46) is connected to the capacitor C C2 , there is a characteristic in that the parasitic capacitance is lower than an alternative circuit construction wherein the collector and the base of the PNP transistor (transistor Q34) are connected to each other as in the circuit construction of FIG. 5. FIG. 7 is a circuit diagram showing a further example of the detailed circuit construction of the control circuit 2 of FIG. 4. The presence circuit example is provided in order to employ, for the capacitor C C3 , a capacitor having a different capacitance from the parasitic capacitance C p1 and has a circuit construction wherein, in addition to the circuit construction of FIG. 5, a series circuit of a resistor R55 and a PNP transistor Q58 is connected in parallel to a series circuit of a resistor 54 and a PNP transistor Q55 and a constant-current source 60 for a current I 0 is connected in parallel to a series circuit of an NPN transistor Q53 and a resistor R52. In such circuit construction, a current I 0 -i flows through the transistor Q54, and another current I 0 - 2i flows through the transistor Q53. Accordingly, by employing a capacitor having a capacitance of C C3 = C p1 /2 as the capacitor C C3 , analog distortion which arises from the parasitic capacitance C p1 can be corrected. In other words, the capacitance of the capacitor C C3 can be reduced to one half comparing with that of the circuit construction of FIG. 5. The emitter follower circuit according to the present invention which is constructed in such a manner as described hereinabove is employed as a circuit at an input stage of each of comparators of, for example, such an analog to digital converter of the parallel type as shown in FIG. 1. Referring to FIG. 1, a reference voltage generation circuit 1 includes, where a digital signal is constituted from, for example, 8 bits, 256 resistors r1 to r256 connected in series, for example, between lines V RT and V RB and generates reference voltages of different voltage values at 255 junctions between adjacent ones of the registers by potential division of the resistors. The reference voltages serve as comparison voltages for 255 comparators COP1, ... of a comparison circuit 2. An analog input voltage V IN is inputted common as an object voltage for comparison to the 255 comparators COP1, ... The 255 comparators COP1, ... collectively determine one of the comparison voltages which is equal to the input voltage V IN . The comparison outputs of the comparators COP1, ... are supplied by way of a gate circuit 3 to an encoder 4, by which they are converted into a digital signal D1 to D8 of 8 bits to be outputted. With the construction described above, analog distortion of the analog to digital converter of the parallel type which arises from the parasitic capacitance of an emitter follower stage can be improved. It is to be noted that the present invention can be applied not only to an emitter follower at an input stage of a comparator in an analog to digital converter of the parallel type but also similarly to an amplifier or a like circuit which has an emitter follower circuit at an input stage thereof. As described so far, according to the present invention, since an input voltage is differentiated to convert the voltage variation into a current variation and the current to flow through an emitter follower stage is controlled in response to the current variation to adjust the emitter current of a transistor of the emitter follower stage in response to the through rate of the input voltage, the variation of the base-emitter voltage V BE of the transistor at the emitter follower stage caused by a charging or discharging current flowing through a parasitic capacitance can be suppressed, and consequently, analog distortion which arises from the parasitic capacitance can be reduced. Further, since the emitter follower circuit according to the present invention is applied to an emitter follower circuit which is used at an analog input stage of a comparator of an analog to digital converter of the parallel type, analog distortion of the analog to digital converter of the parallel type which arises from the parasitic capacitance at the emitter follower stage can be improved.

Claims: An emitter follower circuit, comprising: an emitter follower stage (41) which has a variable current source (Q32) connected as a load thereto and to which an input signal (V IN ) is supplied; a differentiation circuit (43) for differentiating the input signal (V IN ); and a first current mirror circuit (Q33) paired with said variable current source (Q32) for supplying a current to said variable current source (Q32) in response to a differentiation output of said differentiation circuit (43), characterized in that said differentiation circuit (43) contains an inverting circuit which includes a second current mirror circuit (Q34, Q35) for performing an inversion of the input signal (V IN ). An analog to digital converter of the parallel type, comprising: a reference voltage generation circuit (1) for generating a plurality of reference voltages having different voltage values; a plurality of comparators (2) for individually comparing an input analog signal with the plurality of reference voltages; a plurality of gate circuits (3) to which comparison outputs of said plurality of comparators (2) are supplied individually; and an encoder (4) to which outputs of said gate circuits are supplied; wherein: an analog input stage of each of said comparators (2) is constituted using the emitter follower circuit according to claim 1.

Inventors: GENDAI YUJI, GENDAI, YUJI, GENDAI, YUJI, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: H03F3
IPC codes: H03F3, H03K19, H03M1