Apparatus for synchronizing asynchronous circuits for testing operations

Abstract: An apparatus for synchronizing a plurality of asynchronous circuits during testing operations is provided. The apparatus includes first and second clock inputs, a test mode input, and an output. The apparatus receives a first clock signal from a first clock at the first clock input, and a second clock signal from a second clock at the second clock input. Responsive to the state of a test mode signal at the test mode input, the apparatus generates either the first clock signal or the second clock signal at the output. A first circuit is arranged to be driven by the output of the apparatus, while a second circuit is driven by one of the first or second clocks. Consequently, the first and second circuits are driven by different clocks when the test mode signal is in one state, and driven by the same clock when the test mode signal is in another state. Because the first and second circuits are driven by the same clock during testing operations, the timing of the communications between the circuits is predictable, making it possible to perform certain testing techniques that are not possible when the timing of inter-circuit communication is not predictable.

Description: The present invention relates to an apparatus for synchronizing a plurality of circuits, and more specifically for synchronizing a plurality of asynchronous circuits during testing operations. In many computer systems, not all circuits are driven by the same clock. Computer systems comprising circuits driven by different clocks are referred to herein as asynchronous systems, and intrasystem data transfers between circuits which are driven by different clocks are asynchronous. The asynchronous nature of inter-circuit communications between circuits within a computer system which are driven by different clocks makes accurate testing of such asynchronous systems difficult. Specifically, a testing operation generally comprises the steps of monitoring actual outputs of a tested circuit at predetermined times and comparing those actual outputs of the tested circuit with predetermined correct outputs. The tested circuit is considered faulty if the actual outputs do not substantially match the predetermined correct outputs. For such a testing operation to work, one must be able to predict exactly when a valid (non-faulty) circuit will produce particular outputs. However, the time that an asynchronous system will produce a given output may vary since the timing of data transfers within the system between a circuit driven by one clock and a circuit driven by another clock may vary. The variance in the timing of such data transfers may result from, for example, a variance in testing temperature. A change in testing temperature may affect the transfer timing between different circuits in different ways, depending on the direction and magnitude of the temperature change and the internal characteristics of the circuits involved. Another reason for such variance in timing of data transfers is that such transfers are often effected upon the coincidence of particular timing, or clock, signals in two asynchronous circuits; the required coincidence of two independent clock signals cannot be predicted with sufficient accuracy to sufficiently accurately compare actual outputs with predetermined outputs to reliably test a computer system. That is, if, during testing, the outputs of an asynchronous system are checked at the wrong times, then a valid asynchronous system may fail a testing operation, or a faulty asynchronous system may pass a testing operation. Testing becomes even more difficult when the separately-clocked circuits of an asynchronous system reside on a single integrated circuit chip, since there is generally no convenient way to directly monitor a chip's internal data transfers. Further, certain testing techniques, such as scan-testing and burn-in testing, are rendered difficult and inefficient when the circuit to be tested contains separately-clocked regions. Scan-testing consists of shifting data directly into a specific component of a system configured as an integrated circuit, clocking the circuit to shift data from a first component through a series of other components, and then shifting the data out of the system. The data shifted out is then compared to predicted output data. If the data shifted out does not substantially match the predicted output data, then the integrated circuit is considered faulty. Paths within an integrated circuit which couple the series of components through which data is shifted during scan-testing are called scan paths. When an integrated circuit does not comprise a plurality of separately-clocked circuits, a relatively simple set of instructions can be used to perform data loading and data shifting required by the scan-testing process. However, in asynchronous systems the boundary between separately-clocked components effectively becomes a barrier to scan paths. This is because one cannot reliably predict whether data will be transferred between asynchronous components during any particular clock cycle. Consequently, each respective asynchronous circuit or region, within a tested system must be scan-tested separately. As a result, each asynchronous circuit requires its own set of instructions for loading and shifting data, and such instruction sets are typically more complex than they would be for the loading and testing of data within a synchronous system where respective intrasystem circuits are driven by the same clock. In addition, the testing is less comprehensive in such asynchronous systems where respective asynchronous circuits are scan-tested separately, since each separately-clocked circuit is tested in isolation, rather than being tested in conjunction with other circuits with which a respective tested circuit normally operates. During burn-in testing, a system to be tested is placed in a high-temperature environment and selected signals are applied to the system while the system is clocked. By thus "exercising" the components of the system at a high temperature, any marginal components in the system are forced to fail. Burn-in testing for asynchronous systems is difficult, since a plurality of clock signals must be applied to the tested system to effectively "exercise" the system. In addition, the propagation of signals within even a valid chip is unpredictable, since such signals must cross the asynchronous boundaries between the separately-clocked circuits on components. An attempt has been made to accurately predict the generation of outputs in an asynchronous system by allowing a tester to phase shift or "skew" the signal of one of the clocks in the tested system. The signal of one clock is skewed in order to "tune" the output timing to the timing of the test mechanism which monitors the outputs. The altered timing of the skewed clock signal will alter the timing of the asynchronous data transfers between the circuit driven by the skewed clock signal and the other circuits in the tested system. The altered timing of the asynchronous data transfers will, in turn, alter the timing of the outputs generated by the asynchronous system. Under the assumption that a successful test operation will only result when the output generation is accurately synchronized with output monitoring, the skew of the clock signal is adjusted until the asynchronous system tests valid. This signal-skewing technique has the disadvantage that, even when the tested system is valid, the skewing process is relatively time consuming. Further, if the tested system is faulty, then the tester may waste time trying to skew the clock signal timing to achieve a valid test result when such a result is impossible. Further, the signal-skewing technique does not overcome the problems involved in scan testing or burn-in testing an asynchronous system, as described above. As is evident from the foregoing, it is clearly desirable to provide an apparatus that allows asynchronous systems to be accurately tested without a preliminary clock tuning process. It is further desirable to provide an apparatus that allows asynchronous systems to be accurately tested more quickly than is currently possible using the clock signal skewing process of the prior art. It is further desirable to provide an apparatus that allows asynchronous systems to be accurately scan tested. Finally, it is desirable to provide an apparatus that allows asynchronous systems to be accurately burn-in tested. EP-A-0, 454, 320 discloses a scan path test architecture for testing circuits having multiple system clocks with different frequencies wherein a controller disables the system clocks during a test cycle and a master clock generates a signal frequency signal to each circuit module. According to the present invention there is provided a clock selection circuit, for use in a computer system including a first circuit and a second circuit, a first communication port of the first circuit being connected with a second communication port of the second circuit, the clock selection circuit being for synchronizing said first circuit with said second circuit in response to a test mode signal when said first and second circuits are being tested, said computer system including a first clock generating a first clock signal and a second clock generating a second clock signal, the clock selection circuit comprising: a first clock input operatively connected with said first clock for receiving said first clock signal; a second clock input operatively connected with said second clock for receiving said second clock signal; a test mode input for receiving said test mode signal; and a clock output operatively connected with said first clock input, said second clock input, said test mode input and a clock input of said first circuit but not with said second circuit; the clock selection circuit driving said first circuit with said first clock signal through said clock output when said test mode signal is in a first predetermined state and said first and second circuits are not being tested, and driving said first circuit with said second clock signal through said clock output when said test mode signal is in a second pmdetermhed state and said first and second circuits are being tested, said second circuit being driven by said second clock signal regardless of the state of said test mode signal, any communication between said first circuit and said second circuit through said first and second communication ports being asynchronous when said test mode signal is in said first predetermined state, said first circuit and said second circuit operating synchronously in response to said second clock signal when said test mode signal is in said second predetermined state. In the accompanying drawings, by way of example only: Figure 1 illustrates in block diagram form an asynchronous system employing a representative embodiment of the present invention; Figure 2 illustrates in block diagram form a representative embodiment of the clock selector circuit of Figure 1 in greater detail; and Figure 3 illustrates in block diagram form a representative embodiment of the signal selector unit of Figure 2 in greater detail. Figure 1 illustrates in block diagram form an asynchronous system 10 employing the present invention. System 10 includes a plurality of circuits 12 and 14, a clock selection circuit ("CSC") 16, a plurality of clock signal inputs 26 and 28, and a test mode input 30. Clock signal input 26 is connected with a clock 32, and clock signal input 28 is connected with a clock 34. Circuit 12 may be, for example, a circuit for controlling a peripheral device in a computer system, while clock 32 is a clock signal generator associated with the peripheral device. Similarly, circuit 14 may be a processor device in a computer system, while clock 34 may be a clock signal generator for driving the processor device. In the preferred embodiment of the present invention, circuit 12, circuit 14, and clock selection circuit 16 all reside on a single integrated circuit chip. Test mode input 30 is connected with a test mode selector 36. clock selection circuit 16 includes a first CSC clock input 18, a second CSC clock input 20, a CSC test mode input 22, and a CSC clock output 24. CSC clock input 18 is connected with clock signal input 26, and CSC clock input 20 is connected with clock signal input 28. CSC test mode input 22 is connected with test mode input 30. Circuit 12 includes a circuit-driving clock input 38 and a communications port 40. Circuit 12 is driven by clock pulses applied at circuit-driving clock input 38, which is connected with CSC clock output 24. Circuit 14 includes a circuit-driving clock input 42 and a communication port 44. Circuit 14 is driven by clock pulses applied at circuit-driving clock input 42, which is connected with clock signal input 28. Communication port 40 of circuit 12 is connected with communication port 44 of circuit 14. Test mode selector 36 transmits a test mode signal to clock selection circuit 16 through test mode input 30 and CSC test mode input 22. The state of the test mode signal indicates whether system 10 is currently being tested or is being operationally employed. For example, the test mode signal may be a logical HIGH when system 10 is operationally employed and is being tested, and a logical LOW when system 10 is not being tested. Clock 32 transmits a clock signal through clock signal input 26 and CSC clock input 18 to clock selection circuit 16. Clock 34 transmits a different clock signal through clock signal input 28 to CSC clock input 20 and circuit-driving clock input 42. When the test mode signal at CSC test mode input 22 indicates that system 10 is not being tested, clock selection circuit 16 generates at CSC clock output 24 the clock signal received at CSC clock input 18. Conversely, when the test mode signal at CSC test mode input 22 indicates that system 10 is being tested, clock selection circuit 16 generates at CSC clock output 24 the clock signal received at CSC clock input 20. Thus configured, circuit 14 will be driven by the clock signal from clock 34 regardless of the state of test mode signal generated by test mode selector 36; circuit 12 is driven by the clock signal from clock 32 when the test mode signal indicates that system 10 is not being tested, and by the clock signal from clock 34 when the test mode signal indicates that system 10 is being tested. Consequently, during non-testing operation, circuit 12 is driven by a first clock signal, circuit 14 is driven by a second clock signal, and any communication which occurs between circuit 12 and circuit 14 through communication ports 40 and 44 is asynchronous. During a testing operation, both circuit 12 and circuit 14 are driven by the clock signal generated by clock 34. Since both circuits 12 and 14 are driven by the same clock, communications between circuits 12 and 14 becomes synchronized, or synchronous. As a result, the timing of the data transfers between circuit 12 and circuit 14 becomes predictable. Since the timing of the data transfers between circuits 12 and 14 is predictable, the timing of the outputs of system 10 are predictable. In effect, system 10 is transformed into a synchronous circuit for the purposes of testing, thus avoiding all of the predictability problems discussed above with respect to testing asynchronous systems. Figure 2 illustrates in block diagram form the clock selection circuit 16 of Figure 1 in greater detail. clock selection circuit 16 includes a signal selector unit ("SSU") 50 and an OR gate 52. Signal selector unit 50 has a plurality of SSU clock signal inputs 54 and 58, a plurality of SSU clock signal outputs 60 and 62, and a test signal input 56. SSU clock signal input 54 is connected with CSC clock input 18, and SSU clock signal input 58 is connected with CSC clock input 20. Test signal input 56 is connected with CSC test mode input 22. OR gate 52 has a plurality of inputs 64 and 66, and an output 68. Input 64 is connected with SSU clock signal output 60, and input 66 is connected with SSU clock signal output 62. Output 68 is connected with CSC clock output 24. Thus configured, signal selector unit 50 receives the test mode signal at test input 56, receives the clock signal from clock 32 at SSU clock signal input 54, and receives the clock signal from clock 34 at SSU clock signal input 58. When the test mode signal at test input 56 indicates that system 10 is not being tested, signal selector unit 50 allows the clock signal at SSU clock signal input 54 to pass through to SSU clock signal output 60, and drives SSU clock signal output 62 to a logical LOW. OR gate 52 receives the signal at SSU clock signal output 60 at input 64 and the signal at SSU clock signal output 62 at input 66. Since the signal generated at SSU clock signal output 62 is LOW, the output of OR gate 52 will mirror the signal applied at input 64. Specifically, OR gate 52 will generate, at output 68, a logical HIGH when the clock signal applied at SSU clock signal input 54 is HIGH, and a logical LOW when the clock signal applied at SSU clock signal input 54 is LOW. Consequently, when the test mode signal indicates that system 10 is not being tested, the signal at output 68 mirrors the signal at SSU clock signal input 54. Since the signal at SSU clock signal input 54 is generated by clock 32, and circuit 12 is driven, through circuit-driving clock input 38, by the signal at output 68, the timing of circuit 12 is determined by clock 32. In contrast, the timing of circuit 14 is determined by clock 34, which generates a clock signal to drive circuit 14 through circuit-driving clock input 42. Thus, when the test mode signal indicates that system 10 is not being tested, circuit 12 is being driven by a different clock than circuit 14. Because circuits 12 and 14 are being driven by different clocks, the communication between circuits 12 and 14 is asynchronous. That is, all data sent between circuits 12 and 14 via ports 40 and 44 are sent in sync with one clock, but recieved in sync with another clock. As mentioned above, the asynchronous nature of these communications renders accurate prediction of the receipt of transmitted data, which prediction is essential to perform certain testing techniques, extremely difficult. When the test mode signal indicates that system 10 is being tested, signal selector unit 50 allows the clock signal at SSU clock signal input 58 to pass through to SSU clock signal output 62, and drives SSU clock signal output 60 to a logical LOW. OR gate 52 receives the LOW signal generated at SSU clock signal output 60 at input 64 and the clock signal at SSU clock signal output 62 at input 66. Since the signal generated at SSU clock signal output 60 is LOW, the output of OR gate 52 will mirror the signal applied at input 66. Specifically, OR gate 52 will generate, at output 68, a logical HIGH when the clock signal applied at SSU clock signal input 58 is HIGH, and a logical LOW when the clock signal applied at SSU clock signal input 58 is LOW. Consequently, when the test mode signal indicates that system 10 is being tested, the signal at output 68 mirrors the signal at SSU clock signal input 58. Since the signal at SSU clock signal input 58 is generated by clock 34, and circuit 12 is driven, through circuit-driving clock input 38, by the signal at output 68, the timing of circuit 12 is determined by clock 34. As discussed above, the timing of circuit 14 is also determined by clock 34. Thus, when the test mode signal indicates that system 10 is being tested, circuit 12 is being driven by the same clock as circuit 14. Because circuits 12 and 14 are being driven by same clock, the communication between circuits 12 and 14 is synchronous. That is, all data sent between circuits 12 and 14 via ports 40 and 44 are sent and received in sync with the same clock. As a result, the receipt of data transmitted between circuit 12 and 14 may be accurately predicted, allowing system 10 to be tested using testing techniques that would not otherwise be possible. Figure 3 is a block diagram illustrating the preferred embodiment of signal selector unit 50 of Figure 2 in greater detail. Signal selector unit 50 preferably includes a plurality of AND gates 70 and 72 and an inverter 74. AND gate 70 has a plurality of inputs 76 and 78 and an output 80. Input 76 is connected with SSU clock signal input 58, and input 78 is connected with input 56. Output 80 is connected with SSU clock signal output 62. AND gate 72 includes a plurality of inputs 82 and 84 and an output 88. Input 82 is connected to an output 86 of inverter 74, and input 84 is connected with SSU clock signal input 54. Output 88 is connected with SSU clock signal output 60. Thus configured, when the test mode signal at input 56 is HIGH, the signal at input 78 will be HIGH and the signal at input 82 will be LOW. Because input 82 is LOW, output 88 of AND gate 72 will be LOW, regardless of the signal applied at input 84 through SSU clock signal input 54. On the other hand, because input 78 is HIGH, output 80 of AND gate 70 will mirror the signal at SSU clock signal input 58, as it is applied to input 76. When the test mode signal at input 56 is LOW, the signal at input 82 will be HIGH and the signal at input 78 will be LOW. Because the signal at input 78 is LOW, the output 80 of AND gate 70 is LOW, regardless of the signal applied at input 76 through SSU clock signal input 58. On the other hand, because input 82 is HIGH, output 88 of AND gate 72 will mirror the signal at SSU clock signal input 54, as it is applied to input 84. Consequently, when the test mode signal is LOW, output 88 mirrors the signal at SSU clock signal input 54, and output 80 is LOW. Conversely, when the test mode signal is HIGH, output 80 mirrors the signal at SSU clock signal input 58, and output 88 is LOW. Since the signals at outputs 88 and 80 are sent to OR gate 52, OR gate 52 generates at output 68 the signal at SSU clock signal input 54 when the test mode signal is LOW, and the signal at SSU clock signal input 58 when the test mode signal is HIGH. Further, because the signal at SSU clock signal input 54 and the signal at SSU clock signal input 58 are generated by clocks 32 and 34, respectively, output 68 will generate the clock signal of clock 32 when the test mode signal is LOW, and generate the clock signal of clock 34 when the test mode signal is HIGH. It is to be understood that the detailed drawings and specific examples given describe preferred embodiments of the invention and are for the purpose of illustration, that the apparatus of the invention is not limited to the precise details and conditions disclosed, and that various changes may be made therein without departing from the invention which is defined by the following claims:

Claims: A clock selection circuit (CSC), for use in a computer system including a first circuit (12) and a second circuit (14), a first communication port (40) of the first circuit (12) being connected with a second communication port (44) of the second circuit (14), the clock selection circuit (CSC) being for synchronizing said first circuit (12) with said second circuit (14) in response to a test mode signal (30) when said first and second circuits are being tested, said computer system including a first clock (32) generating a first clock signal (26) and a second clock (34) generating a second clock signal (28), the clock selection circuit (CSC) comprising: a first clock input (18) operatively connected with said first clock (32) for receiving said first clock signal (26); a second clock input (20) operatively connected with said second clock (34) for receiving said second clock signal (28); a test mode input (22) for receiving said test mode signal (30); and a clock output (24) operatively connected with said first clock input (18), said second clock input (20), said test mode input (22) and a clock input (38) of said first circuit (12) but not with said second circuit (14); the clock selection circuit (CSC) driving said first circuit (12) with said first clock signal (26) through said clock output (24) when said test mode signal (30) is in a first predetermined state and said first and second circuits are not being tested, and driving said first circuit (12) with said second clock signal (28) through said clock output (24) when said test mode signal (30) is in a second predetermined state and said first and second circuits are being tested, said second circuit (14) being driven by said second clock signal (28) regardless of the state of said test mode signal (30), any communication between said first circuit (12) and said second circuit (14) through said first and second communication ports (40, 44) being asynchronous when said test mode signal (30) is in said first predetermined state, said first circuit (12) and said second circuit (14) operating synchronously in response to said second clock signal (28) when said test mode signal (30) is in said second predetermined state. A clock selection circuit as recited in claim 1, wherein said clock output (24) is operatively connected with said first clock input (18), said second clock input (20), and said test mode input (22) through logic means (SSU+52), said logic means (SSU+52) being configured to generate at said clock output (24) a signal logically related to signals at said first clock input (18), said second clock input (20), and said test mode input (22). A clock selection circuit as recited in claim 2, wherein said logic means (SSU+52) comprises a signal selector unit (SSU) operatively connected with said first clock input (18), said second clock input (20) and said test mode input (22), said signal selector unit (SSU) having a first signal selector unit output (60) and a second signal selector unit output (62). A clock selection circuit as recited in claim 3, wherein said signal selector unit (SSU) electrically couples said first clock input (18) with said first signal selector unit output (60) and drives said second signal selector unit output (62) LOW when said test mode signal (30) is in said first predetermined state, and said signal selector unit electrically couples said second clock input (20) with said second signal selector unit output (62) and drives said first signal selector unit output (60) LOW when said test mode signal (30) is in said second predetermined state. A clock selection circuit as recited in claim 4, wherein said logic means (SSU+52) further comprises a logic circuit (52) operatively connected with said first signal selector unit output (60), said second signal selector unit output (62) and said clock output (24), for generating at said clock output (24) a signal logically related to signals at said first signal selector unit output (60) and said second signal selector unit output (62). A clock selection circuit as recited in claim 5, wherein said logic circuit (52) comprises an OR gate (52) having a first OR input (64) electrically connected with said first signal selector unit output (60), a second OR input (66) electrically connected with said second signal selector unit output (62), and an OR output (68) electrically connected with said clock output (24). A clock selection circuit as recited in any one of claims 3 to 6, wherein said signal selector unit (SSU) comprises: a first AND gate (72) having a first AND1 input (84), a second AND1 input (82) and an AND1 output (88), said first AND1 input (84) being operatively connected with said first clock input (54), said AND1 output (88) being operatively connected with said first signal selector unit output (60); a second AND gate (70) having a first AND2 input (76), a second AND2 input (78) and an AND2 output (80), said first AND2 input being operatively connected with said second clock input (58) and said second AND2 input (78) being operatively connected with said test mode input (56), said AND2 output (80) being operatively connected with said second signal selector unit output (62); and an inverter (74) having an inverter input and an inverter output (86), said inverter input being operatively connected with said test mode input and said inverter output (86) being operatively connected with said second AND1 input (82). An integrated circuit (10) wherein the clock selection circuit as recited in any one of claims 1 to 7 resides with said first circuit (12) and said second circuit (14) on a single integrated circuit chip. An integrated circuit as recited in claim 8 wherein said first circuit (12) comprises a peripheral device controller and said second circuit (14) comprises a processor.

Inventors: GANAPATHY GOPI, KROMER STEPHEN C, GANAPATHY,GOPI, KROMER, STEPHEN C.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1994
Main classification: G06F11
IPC codes: G01R31, G06F11, G06F1