Reference potential generating circuit utilizing a difference in threshold between a pair of MOS transistors

Abstract: A reference potential generating circuit comprises a first PMOS transistor having its gate and its drain connected in common to a first node and its source connected to Vcc, a second PMOS transistor having its gate and its drain connected in common to a second node and its source connected to Vcc, a resistor connected between the first node and the second node, and a first current source connected between the first node and ground. A third PMOS transistor is connected at its gate to the second node and at its source connected to Vcc, so that a current mirror is constituted of the second and third transistors. A fourth PMOS transistor is connected at its source connected to a drain of the third PMOS transistor. A gate of the fourth PMOS transistor is connected to the first node, and a drain of the fourth PMOS transistor is connected to one end of a second resistor having its other end grounded. A reference potential is generated from the one end of the second resistor.

Description: Background of the Invention Field of the invention The present invention relates to a reference potential generating circuit, and more specifically to a reference potential generating circuit utilizing a difference in threshold between MOS transistors having different threshold voltages. Description of related art Characteristics generally required in reference potential generating circuits is that (1) a reference potential is ceaselessly at a constant independently of a voltage supply voltage, and (2) the reference potential is always at a constant regardless of temperature variation. Referring to Figure 1, there is shown a band-gap reference type reference potential generating circuit which can meet with the above mentioned demands and which have been widely used. The shown circuit is composed of bipolar transistors, and has an advantage in that a generated reference potential has an extremely small variation independently of a temperature variation and of a very large voltage supply voltage ranging from several volts to several tens volts. However, in the case that this reference potential generating circuit is incorporated into a CMOS semiconductor integrated circuit such as a memory, new problems are encountered in that a process for manufacturing the bipolar transistors must be newly added into the manufacturing process for the CMOS integrated circuit, and several hundred microamperes are additionally required for a consumed current of this reference potential generating circuit. Under this circumstance, a reference potential generating circuit composed of COMS transistors as shown in Figure 2 has been proposed and actually used. The shown COMS reference potential generating circuit was proposed by M. Horiguchi, et al in "1990 Symposium on VLSI Circuits", pp75-76. This proposed reference potential generating circuit is configured to generate a reference potential for a step-down voltage supply which is used to internally step down an external voltage supply voltage. In a threshold voltage difference generating circuit 10, a PMOS (P-channel MOS) transistor Q 1 is manufactured to include a channel region having an impurity diffusion concentration which is different from that of a PMOS transistor Q2, so that the PMOS transistor Q 1 has a threshold in absolute value larger than that of the PMOS transistor Q 2 . Each of PMOS transistors Q 1 and Q 2 have its gate and its drain connected to each other, so that the threshold of each transistor appears between a source and the drain. Therefore, a voltage, which is a difference in threshold between the transistors Q 1 and Q 2 , will appear on a node VR, independently of a voltage supply voltage V CC . In addition, since both of the transistors Q 1 and Q 2 are governed by P-type carriers, the temperature coefficient of the threshold of these transistors Q 1 and Q 2 are substantially equal to each other. Accordingly, the voltage appearing on the node VR has less temperature dependency. The node VR is connected to one input of a differential amplifier 12, which has an output connected to a gate of a PMOS transistor Q7, and a voltage on a node VL is divided by a trimming circuit 14 and fed back to the differential amplifier. Therefore, on the node VL there is generated a voltage obtained by multiplying the voltage of the node VR by an integer determined by a dividing ratio of the trimming circuit 14 This trimming circuit 14 includes a plurality of fuses, so that a desired voltage can be generated on the node VL by trimming the fuses in the trimming circuit 14 after completion of diffusion steps in the manufacturing process The voltage on the node VL is used as a reference potential of a step-down voltage supply, and does not almost vary dependently upon a voltage supply voltage variation and a temperature variation. In the conventional CMOS reference potential generating circuit shown in Figure 2, however, since the threshold voltage difference VR is amplified by a feedback type circuit, a sufficient caution in design is required to prevent an oscillating operation. In order to prevent the oscillating operation, it is required to make the capacitance of a compensating capacitor C 1 sufficiently large, and also to make a consumed current of the differential amplifier 12 (a current flowing through an NMOS (N-channel MOS) transistor Q 8 ) sufficiently large, so that the differential amplifier 12 quickly operates. According to study of the inventor, in order to prevent oscillation, it is necessary that the capacitance of a compensating capacitor C 1 is about 100 pF and the consumed current of the differential amplifier 12 is about 10 µA. In addition, considering a consumed current in the threshold voltage difference generating circuit 12 as well as a current flowing through the trimming circuit 14, this reference potential generating circuit requires a total consumed current of at least about 20 µA. Furthermore, the capacitance of 100 pF needs a large area in a mask layout. At present, in addition, most of CMOS memories has a total consumed standby current on the order of a few microamperes to a few tens microamperes. In this case, the consumed current of the reference potential generating circuit becomes a large part of the total consumed current of the integrated circuit. Moreover, there is a restriction that the threshold voltage difference VR is required to be about 1 V or more. In the circuit shown in Figure 2, a voltage on a node D, namely, a drain voltage of the transistor Q 8 , is on the order of (VR-V TN ) (where V TN is a threshold voltage of the NMOS transistor), and therefore, is low. The transistor Q8 operates in a non-saturated region in a current-voltage characteristics, but the threshold voltage difference VR fluctuates in a range of about ±0.1 V because of variation in the manufacturing process. Accordingly, the current flowing through the transistor Q 8 greatly varies due to the fluctuation of the threshold voltage difference VR. Accordingly, it must be designed that the threshold voltage difference VR is about 1 V or more even if the variation is the most severe, in order to ensure the high speed operation for preventing oscillation. On the other hand, in a conventional CMOS process, the threshold value of PMOS transistors is controlled by diffusing P-type impurities such as boron to a channel region of the PMOS transistors. Therefore, a PMOS transistor having its channel region diffused with no impurity for controlling the threshold value, has a threshold larger in absolute value than that of a channel-diffused PMOS transistor. From this principle it can be considered to use, as the transistor Q 1 , a PMOS transistor having its channel region diffused with no impurity for controlling the threshold value, so that the transistor Q 1 can have the threshold different from that of the transistor Q 2 , so as to generate the threshold voltage difference VR. In this case, the threshold of the transistor Q1 is determined by the impurity concentration of a well in which the transistor Q1 is formed. The impurity concentration of the well is controlled by a device isolation of a diffusion layer, and therefore, it does not necessarily follow that the difference in threshold between the transistors Q 1 and Q 2 is about 1 V or more. If the threshold voltage difference is smaller than 1 V, it is necessary to add a process of diffusing N-type impurities to the channel region of the transistor Q 1 in order to enlarge the absolute value of the threshold of the transistor Q 1 . This results in increase of the manufacturing cost. All of the problems of the conventional example shown in Figure 2 can be said to be attributable to the fact that the threshold voltage difference is amplified by the feedback circuit using the differential amplifier circuit. In the prior art, however, it is difficult to amplify the threshold voltage difference by a simple structure circuit other than the feedback circuit using the differential amplifier circuit. Summary of the Invention Accordingly, it is an object of the present invention to provide a reference potential generating circuit which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a reference potential generating circuit capable of generating a reference potential by use of a simple structure circuit other than the feedback circuit using the differential amplifier circuit, even if the threshold voltage difference is less than 1 V. Still another object of the present invention is to provide a reference potential generating circuit which is constituted of a simple structure circuit other than the feedback circuit using the differential amplifier circuit, but which needs no capacitor of a large capacitance and has only a reduced consumed current. The above and other objects of the present invention are achieved in accordance with the present invention by a reference potential generating circuit using MOS transistors having different thresholds and configured to generate a reference potential by amplifying a difference between the thresholds of the MOS transistors, the reference potential generating circuit comprising a first PMOS transistor having its gate and its drain connected in common to a first node and its source connected to a high voltage supply voltage, a second PMOS transistor having its gate and its drain connected in common to a second node and its source connected to a high voltage supply voltage, a resistor connected between the first node and the second node, a first current source connected between the first node and a low voltage supply voltage, a third PMOS transistor having its gate connected to the second node, its drain connected to a third node and its source connected to a high voltage supply voltage, a fourth PMOS transistor having its source connected to the third node, its gate connected to the first node and its drain connected to a fourth node, and a second resistor connected between the fourth node and a low voltage supply voltage, a reference potential being generated from the fourth node. One embodiment of the reference potential generating circuit claimed in Claim 1 further includes a means for adjusting a resistance of the first resistor, and/or means for adjusting a resistance of the second resistor. Furthermore, the second PMOS transistor can include a plurality of second PMOS transistors connected in parallel to each other, sop that at least one of the plurality of second PMOS transistors can be selectively separated so as to adjust a current flowing through the first resistor. Similarly, the third PMOS transistor can include a plurality of third PMOS transistors connected in parallel to each other, so that at least one of the plurality of third PMOS transistors can be selectively separated so as to adjust a current flowing through the fourth PMOS transistor. In addition, the reference potential generating circuit can further include a differential amplifier circuit having an input connected to the fourth node, for buffering and amplifying the reference voltage appearing on the fourth node. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of a conventional reference potential generating circuit; Figure 2 is a circuit diagram of another conventional reference potential generating circuit; Figure 3A is a circuit diagram of a first embodiment of the reference potential generating circuit in accordance with the present invention; Figure 3B is a graph illustrating potential changes on various internal nodes in the circuit shown in Figure 3A; Figure 4 is a circuit diagram of a second embodiment of the reference potential generating circuit in accordance with the present invention; Figure 5A is a circuit diagram of a third embodiment of the reference potential generating circuit in accordance with the present invention; and Figure 5B is a graph illustrating potential changes on various internal nodes in the circuit shown in Figure 5A. Description of the Preferred embodiments Referring to Figure 3A, there is shown a circuit diagram of a first embodiment of the reference potential generating circuit in accordance with the present invention. The reference potential generating circuit shown in Figure 3A includes a PMOS transistor Q 1 having its gate and its drain connected to each other, and its source connected to a high voltage supply voltage V CC , another PMOS transistor having its gate and its drain connected to each other and its source connected to the high voltage supply voltage V CC , and a resistor R 10 connected between the drain of the transistor Q 1 and the drain of the transistor Q 2 . Further, an NMOS transistor Q 5 is connected between a low voltage supply voltage or ground GND and the drain (called a node "A" hereinafter) of the transistor Q 1 connected to the resistor R 10 . A gate of this NMOS transistor Q 5 is connected to the high voltage supply voltage V CC . A PMOS transistor Q 3 is connected at its gate to the gate (called a node "B" hereinafter) of the transistor Q 2 . A source of the transistor Q 3 is connected to the high voltage supply voltage V CC . A PMOS transistor Q 4 is connected at its source to a drain (called a node "C" hereinafter) of the transistor Q 3 . A gate of the transistor Q 4 is connected to the drain of the transistor Q 1 (the node A). Another resistor R 20 is connected between a drain of the transistor Q 4 and the low voltage supply voltage GND. A reference potential VR is extracted from the drain of the transistor Q 4 . Now, operation of this circuit will be described. The PMOS transistor Q 1 has a threshold in absolute value higher or larger than that of the PMOS transistors Q 2 and Q 3 . Since each of the transistors Q 1 and Q 2 has its drain and its gate short-circuited to each other, potentials on the nodes A and B are respectively lower than Vcc by the absolute value of the threshold of the respective transistors Q 1 and Q 2 . Accordingly, a difference ΔVT in threshold between the transistors Q 1 and Q 2 is applied across the resistor R 10 , independently of V CC . Therefore, a current I 1 flowing through the resistor R 10 can be expressed as follows: I 1 = ΔVT /R 10 On the other hand, the transistors Q 2 and Q 3 constitute a current mirror. Therefore, assuming that a transconductance constant of the transistors Q 2 and Q 3 are β 2 and β 3 , respectively, a current I 2 flowing through the transistor Q 3 is expressed as follows: I 2 ≅ (β 3 /β 2 )·I 1 = (β 3 /β 2 )·(1/R 10 )·ΔVT Here, the fact that the current I 2 is approximately equal to the current I 1 multiplied by a ratio in transconductance constant between the transistors Q 2 and Q 3 , is attributable to the fact that a source-drain voltage V DS of the two transistors Q 2 and Q 3 are different. In addition, since a current flowing through the resistor R 20 is equal to the current I 2 , a voltage VR across the resistor R 20 is expressed as follows: VR = I 2 ·R 20 ≅ (β 3 /β 2 )·(R 20 /R 10 )·ΔVT Furthermore, because of the PMOS transistor Q 4 , the potential on the node C is higher than the potential on the node A by the absolute value of a threshold of the transistor Q 4 . Accordingly, the source-drain voltage V DS of the transistor Q 3 is independent of V CC , and therefore, is maintained at a constant value. As a result, the current I2 has no dependency to V CC , and VR is at a constant voltage under the condition of V CC ≥V CCO , as shown in Figure 3B which is a graph illustrating dependency between potentials of various nodes in the circuit shown in Figure 3A and the voltage supply voltage V CC . In the equation (3), the temperature dependency of the transconductance constant and the temperature dependency of the resistance of the resistor are respectively cancelled between a numerator and a denominator. In addition, the threshold difference Δ VT is constant regardless of the temperature variation. Accordingly, the potential of the voltage VR is always maintained at a constant value independently of the temperature variation. Furthermore, as will be seen from the equation (3), the voltage VR is a value obtained by amplifying the threshold difference Δ VT by the ratio between the transconductance constants of the transistors Q 2 and Q 3 and by the ration between the resistances of the resistors R 10 and R 20 . Therefore, even if the threshold difference Δ VT is smaller than 1 V, the shown circuit can operate properly. Accordingly, the step of diffusing the N-type impurities to the channel region of the transistor Q 1 in order to increase the absolute value of the threshold of the transistor Q 1 , is no longer necessary. In addition, since the shown circuit includes no feedback circuit, there is no possibility of oscillation occurring in the circuit. Therefore, about 100 pF of the compensating capacitor C1 which was required in the conventional example shown in Figure 2 is also no longer necessary, and accordingly, a mask layout of the circuit can be made small, and the consumed current can be reduced to the order of a few microamperes. Referring to Figure 4, there is shown a circuit diagram of a second embodiment of the reference potential generating circuit in accordance with the present invention. This second embodiment is characterized in that the first embodiment is added with various means for trimming various parameters after completion of the diffusing process, for the purpose of setting the voltage VR to a desired value. Therefore, in Figure 4, elements similar or corresponding to those shown in Figure 3A are given the same Reference Numerals, and explanation thereof will be omitted. Specifically, a resistor R 11 is additionally connected in series with the resistor R 10 , and in parallel to the additional resistor R 11 is connected a fuse F 1 which can be blown out or cut off if necessary at the time of trimming. Similarly, a resistor R 21 is additionally connected in series with the resistor R 20 , and a fuse F 2 is connected in parallel to the additional resistor R 21 . This fuse F 2 can also be blown out or cut off if necessary at the time of trimming. Furthermore, a PMOS transistor Q A is additionally connected in parallel to the transistor Q 2 in such a manner that a gate and a source of the PMOS transistor Q A are connected to the node B and V CC , respectively, and a drain of the PMOS transistor Q A is connected through a fuse F 4 to the node B. Similarly, a PMOS transistor Q B is additionally connected in parallel to the transistor Q 3 in such a manner that a gate and a source of the PMOS transistor Q B are connected to the node B and V CC , respectively, and a drain of the PMOS transistor Q A is connected through a fuse F 3 to the node C. When the voltage VR is measured after completion of the diffusion process, if the voltage VR is higher than a desired value because of variation of the threshold voltage, the voltage VR can be lowered by cutting off the fuse F 1 , F 3 or F 4 by means of the trimming. On the other hand, if the voltage VR is lower than a desired value because of variation of the threshold voltage, the voltage VR can be elevated by cutting off the fuse F 2 by means of the trimming. In this second embodiment, if a number of resistors R 11 , each connected in parallel to one fuse F 1 , are additionally connected in series with the resistor R 10 , it is possible to finely adjust the voltage VR to a desired value with a reduced error. Now, a third embodiment of the reference potential generating circuit in accordance with the present invention will be described. The circuit shown in Figure 3A is disadvantageous in that, if the voltage supply voltage V CC is smaller than V CCO , the voltage VR becomes lower than the desired value. The reason for this is that the voltage VR can never become higher than the potential on the node C. This is a problem in the case that a permissible range of the voltage supply voltage includes a voltage less than V CCO . In addition, the circuit shown in Figure 3A has another disadvantage that since all of the current flowing through the transistor Q 3 must be flowed through the resistor R 20 , it is not allowable to consume a current from the voltage VR. This may become a defect, dependently upon the type of a circuit which utilizes the reference potential. Referring to Figurer 5A, there is shown a circuit diagram of a third embodiment of the reference potential generating circuit configured to overcome the above mentioned two defects. The circuit shown in Figure 5A includes a threshold voltage difference generating circuit 20 which has the same construction as that of the reference potential generating circuit of the first or second embodiment. A voltage VR generated in the threshold voltage difference generating circuit 20 is connected to a differential amplifier 22 of a feedback type circuit for buffering and amplifying the voltage VR so as to generate a reference voltage VL. The voltage VR is connected to a gate of an input NMOS transistor in one of a pair of branches of the differential amplifier 22, and an output of the same branch is connected to a gate of a PMOS transistor Q 7 having a source connected to V CC . A drain of the transistor Q 7 is connected to an output terminal VL, which is grounded through a compensating capacitor C 1 . The drain of the transistor Q 7 also grounded through a pair of series-connected resistors R 30 and R 31 , which constitute a voltage divider. A connection node of these series-connected resistors R 30 and R 31 is connected to a gate of an input NMOS transistor in the other branch of the differential amplifier 22. Referring to Figure 5B, there is shown a graph illustrating dependency between the voltages VR and VL in the circuit shown in Figure 5A and the voltage supply voltage V CC . In this third embodiment, the voltage VR is set at a value which is within a range of 1 V or more but which is lower than that set in the first embodiment, but a desired reference voltage VL can be obtained by amplifying the voltage VR by an amplification factor determined by a ratio in resistance between the resistors R 30 and R 31 . In the third embodiment, accordingly, even if V CC <V CCO , a desired voltage can be obtained as the reference voltage VL. In addition, even if a circuit utilizing the reference voltage VL consumes a current from the terminal VL, the reference voltage VL can be maintained at a constant value. Since the third embodiment has the circuit construction of the feedback type circuit including the differential amplifier, similarly to the conventional example shown in Figure 2, in order to prevent oscillation, it is necessary that the capacitance of a compensating capacitor C 1 is about 100 pF, and a total consumed current of the reference potential generating circuit reaches at least about 20 µA. However, even if the threshold voltage difference is as small as 1 V or less, the reference voltage can be amplified to a level of not smaller than 1 V, which is sufficient to cause a differential amplifier to operate quickly. On the other hand, the process for diffusing the N-type impurities to the channel region of the PMOS transistor for the purpose of enlarging the absolute value of the threshold of the PMOS transistor, which was required in the conventional circuit, is no longer necessary. In other words, the third embodiment can sufficiently operate with the threshold determined by the N-well impurity concentration. The third embodiment can be easily manufactured with a conventional CMOS manufacturing process, and therefore, the manufacturing cost does not increase. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A reference potential generating circuit using MOS transistors having different thresholds and configured to generate a reference potential by amplifying a difference between the thresholds of the MOS transistors, the reference potential generating circuit comprising a first PMOS transistor having its gate and its drain connected in common to a first node and its source connected to a high voltage supply voltage, a second PMOS transistor having its gate and its drain connected in common to a second node and its source connected to a high voltage supply voltage, a resistor connected between said first node and said second node, a first current source connected between said first node and a low voltage supply voltage, a third PMOS transistor having its gate connected to said second node, its drain connected to a third node and its source connected to a high voltage supply voltage, a fourth PMOS transistor having its source connected to said third node, its gate connected to said first node and its drain connected to a fourth node, and a second resistor connected between said fourth node and a low voltage supply voltage, a reference potential being generated from said fourth node. A reference potential generating circuit claimed in Claim 1 further including a means for adjusting a resistance of said first resistor. A reference potential generating circuit claimed in Claim 1 further including a means for adjusting a resistance of said second resistor. A reference potential generating circuit claimed in Claim 1 wherein said second PMOS transistor includes a plurality of second PMOS transistors connected in parallel to each other, and further including a means for selectively separating at least one of said plurality of second PMOS transistors so as to adjust a current flowing through said first resistor. A reference potential generating circuit claimed in Claim 1 wherein said third PMOS transistor includes a plurality of third PMOS transistors connected in parallel to each other, and further including a means for selectively separating at least one of said plurality of third PMOS transistors so as to adjust a current flowing through said fourth PMOS transistor. A reference potential generating circuit claimed in Claim 1 further including a differential amplifier circuit having an input connected to said fourth node, for buffering and amplifying said reference voltage appearing on said fourth node.

Inventors: TSUKADA SHYUICHI, TSUKADA, SHYUICHI, TSUKADA, SHYUICHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: G05F3
IPC codes: G05F3, H03F3