An apparatus and method for increasing breakdown voltage ruggedness in semiconductor devices

Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current).

Description: The present invention relates to semiconductor power devices that have a wide base transistor therein, and more particularly to an apparatus and method for reducing breakdown voltage sensitivity to temperature and rate of change of voltage (dV/dT) in a semiconductor power device that has a wide base transistor by increasing the current through the base relative to 'the current through the emitter, either by diverting current from the emitter to the base or by injecting current from the collector into the base. More specifically the present invention relates to a method for reducing breakdown voltage dependence on temperature and dV/dT in a four layer semiconductor device according to the preamble of claim 1 as well as to a four layer semiconductor device according to the preamble of claim 5. The structural features of a four layer semiconductor device according to the preamble of claim 4 are for example known from JP4014259 and serve the purpose of the protection of the semiconductor element from excess voltage. The problem underlying the present invention may be more easily understood from the following remarks in conjunction with the enclosed drawings Fig. 1 - 5 depicting the prior art four layer semiconductor devices. Various types of semiconductor power devices include a wide base transistor, such as the MOS controlled thyristor (MCT) 10 illustrated in Figure 1 and the insulated gate bipolar transistor (IGBT) 20 illustrated in Figure 2 (gate turn-on devices and silicon controlled rectifiers are further examples) In such devices, the transistor 12, 22 has a wide voltage carrying layer (the wide base 14, 24) Four layer devices, such as the (MCT) 10, may also include an upper transistor 16 having layers common to those of the lower, wide base transistor 12 (e.g., the wide base 14 is also the collector of the upper transistor 16). A buffer layer 15 may be placed between the lower emitter-base junction J1 and the wide base layer 14 to improve lateral conductivity of leakage currents away from the middle of the device. A circuit diagram equivalent to the P-MCT illustrated in Figure 1 (an MCT with a P-type wide base) is shown in Figure 3. The operation of semiconductor power devices is discussed in Semiconductor Power Devices by S. K. Ghandi, John Wiley & Sons, 1977. Briefly, and with further reference to Figures 1 and 3, an MCT is turned on by the on-FET when a small voltage of one polarity (e,g., -5 volts) is applied to the gate 18. The voltage starts a regenerative action that turns on both the upper and wide base transistors 12, 16 so that the MCT conducts, The MCT is turned off by the off-FET when a small voltage of the opposite polarity (e.g., +7, Volts) is applied to the gate. When the MCT is being turned off, the gate voltage creates an electric field in the channel region 19 beneath the gate; that is, the electric charge on the gate 18 causes the semiconductor type of the channel region 19 beneath the gate to convert to the opposite semiconductor type, effectively snorting the emitter-base junction of the upper transistor 16. The channel is a conductive path around the emitter that turns off the upper transistor 16 and stops MCT conduction (the device is in a blocking condition) When the MCT is in the blocking condition the wide base transistor 14 is not being shorted like the upper transistor and is essentially free to operate if a current, such as a leakage current, is applied thereto. One of the problems associated with the wide base transistors, more so with NPN transistors than PNP transistors, is that they appear to be very fragile when the device is operated at high voltages with low current levels. Specifically, the operation of the transistor with an inductive load may be accompanied by voltage excursions beyond BV CEO . With reference to Figure 4 that illustrates the common emitter characteristics of a semiconductor power device, it may be seen that at extremely low current levels, the breakdown voltage rises to its upper limit of BV CEO . Once this voltage is exceeded, the current through the device increases, accompanied by an increase in current gain. As a result, the device voltage "snaps back" as illustrated by line portion AB. Operation under these conditions leads to device failure caused by lateral electrical instability The extremely low current levels that may cause such failure are associated with temperature induced leakage currents and/or dV/dT induced leakage currents that may be found in semiconductor power devices. The inventors have determined that these induced leakage currents are the reason why semiconductor power devices do not achieve their experimentally determined breakdown voltage under actual operating conditions. For example, a P-MCT with an experimentally determined breakdown voltage of 1460 volts may have an actual breakdown voltage of only about 900 volts. With reference now to Figure 5 (experimental results for a P-MCT under varying temperature and dV/dT conditions), it may be seen that as the temperature of the device increases, the breakdown voltage of the device decreases, Similarly as dV/dT increases at low temperature, the breakdown voltage decreases. By way of explanation, and using the P-MCT as an example, when the P-MCT is in the blocking condition the electric charge on the gate forms an inversion channel 19 that shunts current flowing through the upper transistor 16, bypassing the upper emitter-base junction and preventing the device from latching on. The small cell sizes employed in the fabrication of MCTs ensure that the upper transistor 16 is well shorted even under large dV/dT conditions. In contrast, the wide base transistor 12 of the P-MCT is not shorted, is in an open base state when in the blocking condition, and may have an open base current therein. If it is assumed that the upper transistor of the MCT is completely shunted by the off-FET and does not contribute any back injection, then the open base current equation for the wide base transistor is: where M is the multiplication factor, α. is the current gain, I co is the open emitter leakage current, and C dV/dT is the capacitive current component. Breakdown takes place when I αk gets very large with small increases in voltage. This occurs in the open base situation when the effective multiplication defined below gets large. Effective Multiplication = M (1 - α o * M) The variable M is a function of the doping profile, the applied voltage, and the carrier type initiating the ionization and may be calculated for a specific voltage using known techniques. The current gain, α. is a function of the wide base transistor 12 doping profile, base/collector voltage, transistor type, temperature, and the current level in the wide base transistor 12. The dependence on current level can be significant. If current gain, α., is strongly dependent on current level at low current levels, as it is in the wide base NPN transistors of semiconductor power devices, then the α. M product will change as the current level through the device changes. When the change causes the product to approach the value one, the effective multiplication can become very large, causing current gain, I αk to increase, causing breakdown to occur. As is known, the current level is affected by temperature and dV/dT. Increasing the temperature of a device increases the leakage current through it, and increasing dV/dT in the device increases the capacitive current therein. Thus, increases in temperature and dV/dT cause the current level in the device to increase, thereby decreasing the breakdown voltage of the device. One of the operational problems that this dependence on temperature and dV/dT creates is that the breakdown voltage of the semiconductor power device is neither stable nor predictable. Users of such devices need to know the breakdown voltage of their devices with some certainty so that systems can be designed to achieve specific results. Another operational problem caused by this dependence is that changing breakdown voltage also causes the avalanche current capability of the device to become unstable and unpredictable. Thus, the user of the device in an environment with changing temperature and dV/dT is faced with not only an unpredictable breakdown voltage, but also with a device having an unpredictably reduced capability. The term "ruggedness" is used herein to refer to the ability of a semiconductor power device to withstand temperature and dV/dT changes without inviting these problems. An object of the present invention is to provide a method and system for improving the ruggedness of a semiconductor power device and to provide an apparatus and method in which ruggedness is improved. A further object is to provide an apparatus and method in which ruggedness is improved by injecting a current into the wide base at least as large as the current associated with temperature and dV/dT effects. Another object is to improve lateral conductivity in a buffer layer in a semiconductor power device to reduce the dependence on temperature and dV/dT. These objects are achieved by the independent claims. The dependent claims relate to advantageous embodiments of the present invention. The invention will now be described by way of example, with reference to the accompanying drawings in which; Figure 1 is a partial vertical cross-section illustrating the interior of a P-type MOS controlled thyristor (P-MCT) known in the prior art. Figure 2 is a partial vertical cross-section illustrating the interior of a P-type insulated gate bipolar transistor (P-IGBT) known in the prior art. Figure 3 is a circuit diagram of the P-MCT of Figure 1. Figure 4 is graphical depiction of "snap back" in known wide base transistors of semiconductor power devices. Figure 5 is a chart illustrating the dependence of P-MCT breakdown voltage on temperature and dV/dT in know semiconductor power devices. Figure 6 is a circuit diagram of a P-MCT incorporating an embodiment of the present invention (the emitter short) Figure 7 is a graphical depiction of the improved device common emitter characteristics (solid line A) afforded by the embodiment of Figure 6. Figure 8 is a pictorial representation of a vertical cross-section of an epitaxially grown semiconductor power device illustrating an embodiment of the resistive current path of the present invention. Figure 9 is a pictorial representation of a vertical cross-section of a 'substrate based semiconductor power device illustrating a further embodiment of the resistive current path of the present invention. Figure 10 is a circuit diagram of a P-MCT incorporating a further embodiment of the present invention (the feedback mechanism). Figure 11 is a graphical depiction of the improved device common emitter characteristics (solid line A) afforded by the embodiment of Figure 10. Figure 12 is a pictorial representation of a vertical cross-section of a semiconductor power device illustrating an embodiment of the feedback mechanism of Figure 10. Figure 13 is a pictorial representation of a vertical cross section of a semiconductor power device illustrating a further embodiment of the feedback mechanism of Figure 10. Figure 14 is a graphical depiction of the improved device common emitter characteristics (solid line A) afforded by the embodiment of Figure 13. Figures 15A-C are pictorial representations of alternative embodiments of the resistive layer in partial vertical cross section (Figure 15A) and top plan view (two embodiments, Figures 15B-C) Figures 16A-D are pictorial representations of further embodiments of the present invention illustrating geometric patterns of a resistive layer in top plan view (two embodiments, Figures 16A-B) and partial vertical cross section (two embodiments, Figures 16C-D) Figures 17A-B are pictorial depictions of a resistive reducing grid of an embodiment of the present invention in side view (Figure 17A) and in top plain view (Figure 17B) Referring to the drawings the present invention discloses that breakdown voltage sensitivity to temperature and rate of change of voltage (dV/dT) in a wide base transistor is decreased by increasing the current through the base relative to the current through the emitter by using a resistive current path to (a) divert current from the emitter to the base (an emitter short) or (b) inject current from the collector of the wide base transistor into the base (a feedback mechanism). By so doing, the breakdown voltage is stabilized at a predictable level (a lower level in the feedback mechanism than in the emitter short) that is not substantially affected by temperature and/or dV/dT. In effect, the present invention biases the transistor to a value of base current that is beyond the current gain attributable to temperature and/or dV/dT. By way of example, an acceptable level of base current may be about 1 mA for an N-MCT device and about 2 to 3 mA for a P-MCT. At this level the device's negative resistance is significantly reduced so that the device is more rugged. The emitter-base junction potential is desirably less than that required for any appreciable injection (I.e., a fraction of a diode drop) The location of the resistive current path and the magnitude of the resistance in the path are to be determined based on the specific semiconductor power device. As will be discussed in more detail below, the location of the path is determined, at least in part, by the method of manufacturing the semiconductor power device (i.e.. epitaxially grown or substrate based). It is preferable that the resistance in the current path be rather large, in the megohm range, as it presents an unwanted loss term. The Emitter Short with reference now to Figure 6, the embodiment of the present invention incorporating an emitter short may be seen in a P-MCT circuit. A current path 30 with resistor 32 provides a shunt between the base and the emitter of the wide base transistor 34 that shorts, or partially shorts, the emitter junction without appreciably affecting forward drop or device complexity, and, perhaps more significantly, without appreciably changing the breakdown voltage. When device current levels reach the point where the shunt is no longer effective, the transistor gain is reasonably stable and the breakdown of the wide base transistor is not subject to "snap back" to the BV CEO value. The resistive path reduces the effective gain of the wide base transistor 34 for the small current levels induced by high temperature and/or dV/dT. The result of the addition of the resistive current path is illustrated in Figure 7 in which the common emitter characteristics of the device with the invention are shown in the solid line A and the characteristics without the invention (Figure 4) are shown in the dashed line B. When the semiconductor power device is manufactured using an epitaxial process, such as illustrated in Figure 8, the base of the wide base transistor can be contacted through a terminal B on the upper surface of the device. The resistive current path may be wired to the anode or cathode directly, such as through a circuit 38 or through an externally controlled switching circuit (not shown) . The circuit 38 is desirably direct wire-bonded between a field stop 39 and the backmetal 41 of the device. The total resistance in the resistive current path may be considered to include the lateral sheet resistance in the buffer layer 40 (R-lateral), the effective series resistance between the buffer layer 40 and the terminal B R-series), and the resistance R in the external portion of the resistive current path. In semiconductor power devices manufactured using diffusion and/or implant techniques (such as illustrated in Figure 9), a wide base contact area may be provided so that the direct connection between the wide base contact B and the anode or cathode may be on the same surface of the semiconductor device. Again, the resistance in the resistive current path 42 may be considered to include the lateral sheet resistance in the buffer layer 44, the effective series resistance and the external resistance R in the conductive path 42. Feedback Mechanism with reference now to Figure 10, the embodiment of the present invention that incorporates a feedback mechanism may be seen in a P-MCT circuit. A current path 50 with a resistor 52 connects the base of the wide base transistor 54 to its collector to inject a current into the base. The result of the addition of the resistive current path is illustrated in Figure 11 in which the common emitter characteristics of the device with the invention are shown in the solid line A and the characteristics without the invention (Figure 4) are shown in the dashed line B, and where the current at i 1 ≈ BV CEO /R T , R T being the total resistance in the resistive current path. By way of example, it has been found that the feedback mechanism of the present invention may increase the safe breakdown voltage current level of a P-MCT from about 10 µ A (at 25°C) to more than 6mA, while reducing the breakdown voltage from 1150 volts to 963 volts where R T is about 1 megohm. Since the resistive path must support the full rated blocking voltage of the device, the resistive path is preferably located in the termination area of the device with one end of the resistive path contacting the field stop diffusion region. It also must be recognized that the placement of a resistor above the high voltage termination region can adversely affect breakdown voltage. To prevent this, the resistor may be graded to mirror the subsurface voltage distribution near the breakdown voltage. It is also recognized that the resistive current path can be useful in some cases to increase breakdown voltage by offering another means to control lateral voltage and fields in the termination region. With reference now to Figure 12, the resistive current path of the present invention may be a resistive layer 60 that biases the wide base 62 when placed between a field stop 64 and the collector 72 in the cellular active region 66 of the device. The resistive layer 60 may be a material that can be doped to different resistivities, such as SIPOS or other doped polyresistor material and may be placed on top of a passivation layer 68. The resistive layer 60 may be doped to a suitable level that, when combined with its geometry, would give a resistance that at full blocking voltage would supply a current of anywhere in the range of tens of microamps to tens of miliamps depending on the desired degree of ruggedness of the device. The resistive layer 60 may be used in epitaxially manufactured devices, such as shown in Figure 12, or in substrate based devices (not shown) Further, in MCT's and IGBT's where a lightly doped polysilicon is used for the gate layer, it is advantageous to use the lightly doped polysilicon to serve in the resistive layer 60 to save manufacturing steps. As illustrated in Figure 13, the feedback mechanism may also be implemented using external components, such as an external current path 70 between the field stop 64 (connected to the wide base 62) and the collector 72 of the wide base transistor. The path 70 may include a simple resistor (such as illustrated in Figure 9) or may include a resistor R s and a string of N thin film zener diodes 73 to avoid power loss at voltages less than BV CEO . The common emitter characteristics of a device incorporating this embodiment may seen in Figure 14. The current i 1 at approximately the BV CEO may be adjusted by changing the number N of zener diodes 73 capable of blocking v Z volts, with i 1 being determined from: i 1 ≈ (BV CEO - N  V,) /R S In alternative embodiments of the feedback mechanism, and with reference to Figures 15A-C, 16A-D, the resistive current A path may be shaped or formed so that it is graded to match the subsurface voltage distribution in the termination passivation region at the edge of the device. For example, as is known field rings 76 may be imbedded in the passivation region to reduce the voltage gradient at the lateral edges of a semiconductor device. By using a combination of a resistive layer 60 and surface rings 78 disposed generally adjacent the field rings 76, the voltage gradient across the passivation region may be patterned to achieve a desired shape. The surface rings 78 (which may be formed from metal, polysilicon, or similar material) divide the voltage gradient across the passivation region in proportion to the effective resistance between the surface rings 78. Thus, by grading the voltage across the region, the resistive layer 60 may also stabilize the voltage gradient of the field rings 76 which might otherwise be fairly uncertain due to unknown variations in the passivation layer 68 charge. With continued reference to Figures 15B-C, the resistive layer 60 need not be continuous but may be shaped to achieve the desired voltage gradient and/or to obtain a desired total resistance between the wide base 62 and the collector 72. For example, with reference to Figure 15B, the resistive layer 60 may be in the form of plural squares (or rectangles) 80 in annular arrangement about the cellular active region 66. As is known, the resistance of the rectangles are proportional to length / width * thickness and thus the width of the rectangles 80 between the surface rings 78 may be adjusted to determine the shape of the charge gradient across the passivation region. Similarly with reference to Figure 15C, the resistive layer 60 may be shaped to increase the length of the resistive path (for example, in a saw-tooth pattern 82), thereby increasing the total resistance of the resistive current path The resistance of the resistive layer 60 in the embodiment of Figure 12 can be varied by varying the length and/or width and/or geometric pattern of the layer 60, such as illustrated in Figures 16A-B. The varying patterns of the layer 60 may be coordinated with field rings as in Figure 16C, or other lateral/passivation structures, such as a multiple zone junction termination extension (JTE) 84 illustrated in Figure 16B. With reference now to Figures 17A-B, in an alternative embodiment of the present invention applicable to both the emitter short and feedback mechanism embodiments, further conductive means for carrying current away from the interior portions of the semiconductor power device 90 may be added (one of the emitter short 100 and the feedback mechanism 102 may be used). Use of the further conductive means may be appropriate when the buffer layer 92 of the device is not able to carry away large induced currents from the middle of the device or when the device itself has a large area from which induced currents are to be carried. The conductive means may be a heavily doped P base grid 94 imbedded in or on the buffer layer to carry currents from the center of the device with acceptable resistance. The grid 94 may be patterned into the starting wafer before the epitaxial growth or the epitaxial growth steps may be broken into two to accommodate formation of the grid. The grid may take a variety of patterns, including a cross-hatch pattern, such as illustrated in cross section in Figure 17A and in plan view in Figure 17B. The grid 94 may include a solid portion 96 under the termination region of the device, and smaller overlapping portions 98 under the active region of the device. The grid may be accessible from a surface of the device through diffused regions, by Thermal Gradient Zone Melting aluminum, by placement of grooves in the surface or by conduction through the base as illustrated by the R-series in Figure 17A. The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current).

Claims: A method of reducing breakdown voltage dependence on temperature and dV/dT in a four-layer semiconductor power device having an upper transistor and a lower wide base transistor (34, 54), the wide base transistor (34) having a buffer layer (40, 44, 92) within its base adjacent the emitter, and in which breakdown voltage is effected by induced currents related to the temperature or the dV/dT of the device, the method comprising the steps of: forming a resistive current path (32, 52, 100, 102) connected to the base of said wide base transistor (34, 54) providing a current in said resistive current path that influences the magnitude of current through said semiconductor device; adding to said buffer layer (92) a grid (94) of semiconductor material that has a higher impurity concentration than that of the base of said wide base transistor for improving lateral conduction of the induced currents. wherein a) connecting by a first resistive current path (32, 100) said base of said wide base transistor (34) to a power terminal (A/K) of the wide base transistor, the resistance of said resistive current path including lateral sheet resistance in said buffer layer (40, 44, 92), effective series resistance between either the buffer layer (40) and a field stop terminal (39) connected to the wide base and disposed at the edge of a termination passivation region on a surface of the device or the buffer layer and a wide base contact diffusion region disposed on a lower surface of the device and connected to a further terminal, and a resistance (R) in an external portion of the resistive current path which connects the said field stop terminal or the said further terminal, respectively, to said power terminal of said wide base transistor; providing a current in said first resistive current path (32, 100) that increases the current through the base of the wide base transistor (34) relative to the current through the emitter of the wide base transistor (34) and thus exceeding the induced current attributable to the temperature or the dV/dT of the device, thereby reducing breakdown voltage dependence on temperature and dV/dT; and/or b) forming a second resistive current path (52, 102) between the collector (72) and base of said wide base transistor (54), the resistance of said second resistive current path (52, 102) including lateral sheet resistance in said buffer layer (92), an effective series resistance between the buffer layer (92) as well as a field stop terminal (64) connected to the wide base and disposed at the edge of a termination passivation region (68) at an upper surface of the device, and a resistance (60, R S ) in an external portion of said second resistive current path (52, 102) which connects said field stop terminal (64) to the collector (72) of the wide base transistor (54); providing a current in said second resistive current path (52, 102) which is injected into the base of the wide base transistor (54) and which is at least as large as the induced current attributable to the temperature or the dV/dT of the device, thereby reducing breakdown voltage dependence on temperature and dV/dT; and A method as claimed in claim 1, characterized in that said external portion of said first and second resistive current paths (32, 52, 100, 102) is formed by the step of providing a resistor (60, R S ) connecting said field stop terminal (39, 64) connected to the wide base and disposed at the edge of a termination passivation region (68) of said semiconductor power device to the emitter of said wide base transistor (34, 54) and / or the collector (72) of said wide base transistor (34, 54). A method as claimed in claim 1 or 2, characterized in that the semiconductor power device is a MOS controlled thyristor. A four layer semiconductor power device having an upper transistor and a lower wide base transistor (34, 54), a buffer layer (40, 44, 92) within the wide base transistor (34) adjacent the emitter, a resistive current path (32, 52, 100, 102) connected to the base of said wide base transistor (34, 54) and a breakdown voltage being effected by induced currents related to the temperature or the dV/dT of the device; wherein a grid (94) of semiconductor material that has a higher impurity concentration than that of the base of the wide base transistor is added to the buffer layer (40, 44, 92). a) a first resistive current path (32, 100) connects said base of said wide base transistor (34) to a power terminal (A/K) of the wide base transistor, the resistance of said first resistive current path (32, 100) including lateral sheet resistance in said buffer layer (40, 44, 92), effective series resistance between either the buffer layer (40) and a field stop terminal (39) connected to the wide base and disposed at the edge of a termination passivation region on a surface of the device or the buffer layer (44) and a wide base contact diffusion region disposed on a lower surface of the device and connected to a further terminal, and a resistance (R) in an external portion of the resistive current path which connects the said field stop terminal or the said further terminal, respectively, to said power terminal of said wide base transistor; and/or b) a second resistive current path (52, 102) connects the collector (72) and base of said wide base transistor (54), the resistance of said second resistive current path (52, 102) including lateral sheet resistance in said buffer layer (44, 92), an effective series resistance between the buffer layer (40) and a field stop terminal (64) connected to the wide base and disposed at the edge of a termination passivation region (68) at an upper surface of the device, and a resistance (60, Rs) in an external portion of said second resistive current path (52) which connects said field stop terminal (64) to the collector (72) of the wide base transistor (54); and A device as claimed in claim 4, characterized in that said external portion of said second resistive current path (52, 102) includes a resistive layer (60) connecting said field stop terminal (64) at an edge of a termination passivation region (68) of the device, said field stop (64) being connected to the base of the wide base transistor (54). A device as claimed in claim 4 or 5, characterized in that said resistive layer (60) is shaped substantially to match a surface voltage distribution in the termination passivation region (68). A device as claimed in any one of claims 4 to 6, characterized in that the shape of said resistive layer (60) includes a saw-tooth pattern or a pattern in which layer width varies as a function of distance from the field stop (64).

Inventors: ARTHUR STEPHEN DALEY, NEILSON JOHN MANNING SAVIDGE, TEMPLE VICTOR ALBERT KEITH, WATROUS DONALD LELAND, ARTHUR, STEPHEN DALEY, NEILSON, JOHN MANNING SAVIDGE, TEMPLE, VICTOR ALBERT KEITH, WATROUS, DONALD LELAND
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1994
Main classification: H01L29
IPC codes: H01L29, H01L21