Exposure apparatus, and manufacturing method for devices using same

Abstract: An exposure apparatus includes an exposure device for exposing an exposure area of a substrate (3) through a pattern (21) of a mask (1), wherein the pattern involves writing error; and a correcting device for correcting the writing error of the pattern to correctly overlay the pattern on the exposure region.

Description: The present invention relates to an exposure apparatus and a method of manufacturing devices using the same. The recent progress of the semiconductor device manufacturing and the fine processing related thereto are remarkable. Particularly, photolithography is mainly effected by reduction projection exposure apparatus (stepper) having a resolution of submicrons, and a larger numerical aperture (NA) and further reduction of wavelength of the light for the exposure are developed toward further improvement in the resolution. One-to-one scanning type exposure apparatus using reflection type projection optical system is improved, for example, there are noted a reduction projection optical system incorporating a refraction element such as lens in a projection optical system to combine with reflection element such as mirror, or a scanning type exposure apparatus in which a reduction projection optical system constituted only by refraction elements are used, and both of a mask stage and a wafer stage are moved in a speed ratio corresponding to the reduction. As a factor influencing alignment between a mask pattern and a wafer pattern, there is a deviation of EB writing (electron beam writing) of the mask pattern (original) from design pattern. Conventionally, the deviation has been ignored because the amount of deviation is small. According to one aspect the present invention provides an exposure apparatus comprising: means for exposing an exposure area (22) of a substrate through a pattern of a mask, wherein said pattern deviates in position, size or shape with respect to a design pattern; and means for detecting the deviation of the pattern wherein said exposure means is responsive to said detecting means to effect its exposure operation so as to compensate for the pattern deviation during exposure of the substrate. According to a second aspect the present invention provides an exposure method using a mask (4) having a device pattern deviated in position, size or shape with respect to a design pattern, the method comprising the steps of: detecting the deviation of the device pattern; and exposing a pattern area of a substrate while compensating for the deviation of the device pattern. Embodiments of the present invention will now be described with reference to the accompanying drawings in which: Figure 1 is a schematic view illustrating an apparatus according to an embodiment of the present invention. Figure 2 illustrates scanning exposure in the apparatus of Figure 1. Figure 3 is a flow chart for manufacturing a semiconductor device. Figure 4 shows a wafer process of Figure 3. The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings. Figure 1 shows a scanning exposure apparatus according to an embodiment of the present invention, for manufacturing semiconductor devices or devices such as CCD, liquid crystal panel, magnetic head. A mask 1 having a written pattern is supported in a main assembly on a mask stage 4 driven and controlled in XY direction by control means 103 and laser interferometer (not shown). The mask 1 and the wafer 3 are located at optically conjugate positions through the projection optical system 2. A slit-like exposure beam 6 extending in Y direction from an unshown illumination system is projected on the mask 1, and the pattern of the mask 1 is imaged on a wafer 3 with a scale corresponding to the projection magnification of the projection optical system. For the scanning exposure, both of the mask stage 4 and the wafer stage 5 are moved in X direction at a speed ratio corresponding to the projection magnification of the projection optical system 2 relative to the slit exposure beam 6, so that the relative scanning is effected between the mask 1 and the wafer 3. By this, the entirety of the device pattern 21 of the mask 3 is transferred onto a transfer region (pattern region) 22 of the wafer 3. The projection optical system 2 may be constituted only by refraction elements or by both of reflection elements and refraction element. In this embodiment, the mask 1 is supported on a mask stage 4, and the state of pattern writing of the device pattern on the mask 1 is measured. More particularly, a plurality of mask writing evaluation marks 51 (written together with the device pattern) arranged in XY directions on the mask 1, are observed by a pair of observing microscopes 7. A signal relating to mark 51 position obtained by the microscopes 7 is processed by mark detecting means 101, and the output thereof is transmitted to a processing circuit 102 as position information of the mask writing evaluation mark. The position of the mask stage 4 during the observation is measured by an unshown laser interferometer. The information relating to the position of the stage 4, is transmitted to a processing circuit 102 by drive control means 103, and is stored corresponding to the position information for the mask writing evaluation mark 51. The measurement is repeated for the plurality of mask writing evaluation marks 51, while controlling the position of the mask stage 4 using a laser interferometer (not shown), by which writing state of the mask pattern on the mask 1 is discriminated. The mask writing evaluation marks 51 are written by an electron beam writing device simultaneously with the device pattern 21, and therefore, represent original position of the pattern 21, writing magnification (size) and/or the perpendicularity of the pattern. Therefore, when the writing magnification or the perpendicularity are to be measured, at least three mask writing evaluation marks 51 are required. In this Figure, the mask writing evaluation marks 51 are disposed in the manner of enclosing the device pattern 21. However, they may be disposed in the pattern 21 region. The configuration of the mark is not limited to "cross". The device pattern 21 may be used as the mark. During the exposure operation, a scanning driving method for correcting the detected writing error is instructed to the drive control means 103 from processing circuit 102 storing the writing state (error) of the pattern 21. Using an unshown laser interferometer, the relative position between the mask stage 4 and the wafer stage 5 is controlled to correct the writing error, and therefore, the pattern 21 is transferred onto the transfer region 22 on the wafer with high accuracy. The consideration will be made as to the case in which the pattern 21 is written with perpendicularity error , as shown in Figure 2A, for example. Using an unshown alignment system, the mask 1 and the wafer 3 are aligned, and the pattern 21 and the scanning start side of the transfer region 22 are aligned relative to the slit exposure light 6, as shown in Figure 2B. Subsequently, the processing circuit 102 instructs the drive control means 103 the scanning drive method for correcting the perpendicularity error . More particularly, the mask stage 4 is driven inclinedly by the degree corresponding to the perpendicularity error , relative to the scanning direction (X) of the wafer stage 5. The mask stage 4 and the wafer stage 5 are moved relative to the slit exposure light 6 as shown in Figures 2B - 2D, while controlling the positions using an unshown laser interferometer. As a result, the transfer region 22 is exposed to the pattern 21 with the writing error corrected. Therefore, the patterns 21 and 22 can be overlaid with high precision. The observation microscopes 7 in this embodiment may be used also as alignment optical system for detecting positional deviation between the mask 1 and the wafer 3. When the positional deviation between the mask 1 and the wafer 3 is detected, the position of the mask writing evaluation marks 51 is also detected. At this time, the writing evaluation mark 51 of the mask 1 may be used also as the mask alignment mark, advantageously. The description will be made as to an embodiment of device manufacturing method using the scanning exposure apparatus. Figure 3 is a flow chart of manufacturing semiconductor devices such as IC, or LSI, or devices such as liquid crystal panel or CCD. At step 1, (circuit design), the circuits of the semiconductor device is designed. At step 2, the mask having the designed circuit pattern is manufactured. On the other hand, at step 3, a wafer is manufactured using the proper material such as silicon. Step 4 is called pre-step, in which actual circuit pattern is formed on a wafer through lithographic technique using the prepared mask and wafer. At step 5 (post-step), a semiconductor chip is manufactured from the wafer subjected to the operations of step 4. The step 5 includes assembling steps (dicing, bonding), or packaging step (chip sealing). At step 6, the operation of the semiconductor device manufactured by the step 5 is inspected, and durability test thereof is carried out. In this manner, the semiconductor device is manufactured and delivered at step 7. Figure 4 is a flow chart of detailed wafer processing. At step 11, the surface of the wafer is oxidized. At step 12 (CVD), an insulating film is formed on a surface of the wafer. At step 13 (electrode formation), an electrode is formed on the wafer by evaporation. At step 14 (ion injection), the ion is implemented into the wafer. At step 15 (resist processing), a photosensitive material is applied on the wafer. At step 16 (exposure), the circuit pattern of the mask is projected onto the wafer by the above-described exposure apparatus. At step 17 (development), the exposed wafer is developed. At step 18 (etching), the portion outside the resist image are removed. At step 19 (resist removal), the resist is removed after the etching. By repeating the above-described steps, overlaid circuit patterns are formed on the wafer. According to the manufacturing method of one aspect of the invention, a highly integrated circuit pattern can be formed in the semiconductor devices.

Claims: An exposure apparatus comprising: means for exposing an exposure area (22) of a substrate (3) through a pattern (21) of a mask (4), wherein said pattern deviates in position, size or shape with respect to a design pattern; and means (51,7,101,102) for detecting the deviation of the pattern wherein said exposure means is responsive to said detecting means (51,7,101,102) to effect its exposure operation so as to compensate for the pattern deviation during exposure of the substrate (3). An apparatus according to claim 1, wherein said detecting means (51,7,101,102) includes means for measuring a plurality of portions of a device pattern (21) of the mask (4), the detecting means (51,7,101,102) detecting the pattern deviation on the basis of an output of said measuring means. An apparatus according to claim 1, wherein said detecting means (51,7,101,102) includes measuring means (7,101) for measuring positions of a plurality of marks (51) of the mask (4), the detecting means (51,7,101,102) detecting the pattern deviations on the basis of an output of said measuring means (7,101). An apparatus according to claim 3, wherein the plurality of marks (51) also function as alignment marks for alignment of the mask (4) with the substrate (3). An apparatus according to claim 4, wherein said measuring means comprises an alignment optical system for detecting alignment marks. An apparatus according to any one of claims 1 to 5, wherein said exposure means includes means for scanning the mask (4) and the substrate (3) relative to an exposure beam (6). An apparatus according to claim 6, wherein said scanning means scans the mask (4) and the substrate (3) so as to compensate for the pattern deviation. An apparatus according to claim 7, wherein when the pattern deviation involves perpendicularity error, said scanning means being adapted to scan the mask (4) and the substrate (3) in different directions. An exposure method using a mask (4) having a device pattern (21) deviated in position, size or shape with respect to a design pattern, the method comprising the steps of: detecting the deviation of the device pattern (21); and exposing a pattern area (22) of a substrate (3) while compensating for the deviation of the device pattern (21). A method according to claim 9, wherein the exposing step comprises scanning the mask (4) and the substrate (3) with exposure light whilst relatively moving the mask (4) and substrate (3) so as to compensate for the deviation in the device pattern. A method according to claim 9 or claim 10 wherein the detection step includes measuring a plurality of portions of a device pattern (21) of the mask (4) and detecting the pattern deviation on the basis of the measurement. A method according to claim 9 or claim 10 wherein the detection step includes measuring positions of a plurality of marks (51) on the mask (4), and detecting the pattern deviation on the basis of the measurement. A method according to claim 12 wherein the plurality of marks (51) also function as alignment marks for alignment of the mask (4) with the substrate (3), including the step of aligning the mask (4) and the substrate (3) using the marks (51). A method according to any one of claims 9 to 13 wherein the exposure step includes scanning the mask (4) and the substrate (3) relative to an exposure beam (6). A method as claimed in claim 14 wherein the mask (4) and substrate (3) are scanned so as to compensate for the pattern deviation. A method as claimed in claim 15 wherein the pattern deviation involves perpendicularity error, and the scanning step includes scanning the mask (4) and the substrate (3) in different directions. A method of manufacturing a device comprising the exposure method of any one of claims 9 to 16 and the step of fabricating a device using the exposed substrate (3).

Inventors: JIGYOSHO KOSUGI, MORI,TETSUYA, JIGYOSHO, KOSUGI, C/O CANON K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: G03F7
IPC codes: G03F7, H01L21