Package for parallel subelement semiconductor devices and method

Abstract: A package for semiconductor devices (40) with plural subelements and method of packaging. Semiconductor power devices may include plural subelements (20) to increase device manufacturing yield. Each subelement is separately contacted through the lid (44) of the package by attaching a foil (32,34) to a subelement contact and depending a tab (36,38) from the foil that extends through the lid. Tabs for operative subelements can be connected external to the package, and tabs for inoperative subelements may be left unconnected or covered.

Description: The present invention relates to a method for manufacturing a package of a power semiconductor device, and more particularly to methods of manufacturing packaged semiconductor devices having plural subelements in which inoperative subelements are not connected to operative subelements. Some semiconductor devices, particularly power devices, require a large active area to be able to carry the large currents associated with such devices. As is known, current carrying capability is a function of active area size. However, as the size of the active area increases, the yield rate (i.e., the percentage of the devices manufactured that are operative) decreases. In some high power semiconductor devices, the yield rate may be only a few percent. To increase the likelihood that the semiconductor device will be operative, the active area of the device may be divided into smaller subelements with higher yield rates, each subelement having an active area that may be selectively connected in parallel to other subelement active areas to create an active area of requisite size. While not all subelements will be operative (typically, the yield rate does not reach 100%), the number of subelements can be selected so that, on average, the number of subelements available will meet the device's current rating. By way of example, and with reference to Figure 1, a semiconductor device 10 requiring four units of active area to achieve its current rating may include six subelements 12, each with a yield rate of about 70% and an active area of one unit (the subelement boundaries are indicated by the dashed lines in Figure 1). The likelihood that four or more subelements will be operative is far better than the yield rate for a device with a single active area of four units. The subelements may each include an active area 16 and a gate 18 and may be separated from the edge of the device by a termination region 14. The active areas 16 are desirably separated from each other in the silicon substrate so that inoperative subelements do not interfere with the operation of operative subelements. The distance between active areas may be reduced to save space on the device by reducing the carrier diffusion length between active areas, such as by reducing local carrier lifetimes. The manufacture of semiconductor devices with plural subelements has presented new problems and the present invention is directed, at least in part, to solving some of those problems. For example, electrical contacts are to be made to operative subelements, but should not be made to inoperative subelements; how and when in the manufacturing process are the subelements tested; where the electrical connections should be located among operative subelements; how to make the electrical connections to the operative subelements through the package for the device? An object of the invention is to provide a method of manufacturing a package for a semiconductor device with plural subelements in which operative subelements are electrically connected, while inoperative subelements are not, and to provide a method of manufacturing a package for a semiconductor device with plural subelements in which the electrical connections to operative subelements are made after the device has been packaged and on top of the lid for the package. Another object is to provide a method of manufacturing a package for a semiconductor device with plural subelements in which the active area and the gate for each subelement are contacted separately through the lid of the package for the device, and to provide a method of manufacturing a package for a semiconductor device in which a contact for a subelement gate is bonded to the gate pad without decreasing the size of the active area of the subelement. These problems are solved by the method according to claim 1.The dependent method claims aim at preferred embodiments of the present invention. From EP-A-0 064 231 there is known a semiconductor device showing the following structural features: A semiconductor device having a substrate upon which subelements are formed and wherein each subelement has a gate and a terminal and a contact for each gate and terminal that is to be electrically connected to corresponding contacts of other subelements. Furthermore, from WO-A-9,314,517 and US-A-5,028,987, there is known a semiconductor device which is packaged within the interior of a package; wherein said package comprises a cup like base with a bottom wall and a side wall terminating in an outwardly extending flange; a lid being provided extending laterally outwardly and overlapping the flange; said package comprising a plurality of conductive foils, one for each of the contacts, each foil being attached to its respective one of said contacts in electrically conductive relationship, each foil having a contact pin connected thereto; said lid covering said plurality of subelements and having a plurality of openings, one for each contact pin;said seal being provided for each of said openings; said pins being associated with an operative subelement each being surrounded by a seal in such a manner that electrical contact can be made therewith, and said remaining pins associated with an inoperative subelement are each covered by an appropriate material in such a manner that electrical connections cannot be made thereto. However, it is to be noted that said prior art documents do not at all address the above-mentioned problem related to the low yield when manufacturing power semiconductor devices based on an integral large active area semiconductor element. The invention will now be characterized by way of example, with reference to the accompanying drawings in which Figure 1 is a pictorial representation of a top plan view of a semiconductor device with subelements. Figure 2 is an exploded pictorial representation of an embodiment of the present invention illustrating a single subelement in the interest of clarity. Figure 3 is a vertical cross section of an embodiment of the present invention illustrating a single subelement in the interest of clarity. Figure 4 is a pictorial representation of a packaged device of the present invention illustrating the subelement contacts extending through the lid of the package. With reference to Figure 2, an embodiment of the present invention may be seen as applied to a single subelement 20 having an active area 22 with a contact pad 24, and a gate contact pad 26. Other subelements 20 have been omitted in the interest of clarity, the embodiment illustrated in Figure 2 is applicable to semiconductor devices with a plurality of subelements ( e . g ., devices with twenty-five subelements have been manufactured using the present invention). Further, the depiction of the subelement 20 having a gate and an active area (typically an anode or cathode terminal in power devices, such as MOS gated bipolar devices) is not limiting as the invention is also applicable to other types of semiconductor devices in which operating portions of the device may be divided into subelements. The invention can also be used to contact the opposite terminal in the device. Metal sheets 28 and 30 may be attached to the contact pads 26 and 24, and metal foils 32 and 34 may be attached thereto, with each of the foils 32 and 34 having a tab 36 and 38 depending therefrom and extending away from the surface of the subelement 20. The sheets and foils may be conventional materials, such as copper, nickel and aluminum, and may be attached using conventional techniques, such as bonding, soldering, etc., with bonding being preferred. The sheet 28 attached to the gate contact pad 26 is desirably larger than the pad 26 so that the foil 32 may be attached (thereby completing electrical connection from the tab 36 to pad 26). A contact pad for the gate is needed, but takes up space in the subelement that may be used for active area, and accordingly is desirably as small as possible while having sufficient space for attachment of a contact thereto. The presence of sheet 28 precludes the need to increase gate contact pad size. The sheet 28 may overlie other parts of the subelement, including the active area 22, and may be separated therefrom with appropriate insulation. Further, the tabs 36 and 38 are desirably large enough to allow connection to circuits in which the semiconductor device may operate. With reference now to Figure 3, the semiconductor device 40 with subelement 20 (again only one of the subelements is shown in the interest of clarity) may be packaged in a cup 42 with a lid 44. Tabs 36 and 38 extend through openings 46 in the lid 44 so that they may be connected as appropriate. The cup 42 and lid 44 may be conventional and attached in manners other than that shown. The lid may be a ceramic that is direct bonded copper (DBC) to a metal cup in a hermetic or non-hermetic package, or the lid may be bonded to the cup using diffusion bonding after suitable metalization of the bonding surfaces. The lid also may be a plastic encapsulation material that fills the cup, or the lid may be attached directly to the substrate for the semiconductor device by extending the edge of the substrate to provide a bonding surface, obviating the need for a cup. Seals 48 may be provided as needed to close the openings 46. With reference now to Figure 4, in which a lid 50 for a semiconductor device with six subelements in a cup 52 may be seen, the tabs 36 and 38 of operative subelements may extend above the lid 50 so that they may be contacted as needed, such as depicted by the gate contact circuit 54 and device terminal circuit 56. The tabs of inoperative subelements (two in the example of Figure 4) may be covered or sealed with appropriate material 58 so that they cannot be electrically contacted. The length of tabs of inoperative subelements may be reduced, such as by cutting, so that they do not extend above the surface 60 of the lid 50. Alternatively, the tabs of inoperative elements may extend above the surface 60 and be left unconnected and/or marked to alert the manufacturer or user. In an alternative embodiment of the present invention, the sheets 28 and 30 (illustrated in Figure 2) may be omitted, although the size of the foil 32 and tab 36 must be commensurately reduced if active area size is to be maintained. In another alternative embodiment, the sheet 30 may be omitted and the foil 34 may be attached directly to the contact pad 24. In the method of the present invention, the determination that a subelement is operative is made after providing a lid for covering the subelements and before providing seals which surround contact pins associated with an operative subelement so that electrical contact can be made therewith and covering or sealing the contact pins of inoperative subelements with appropriate material so that electrical connections cannot be made therewith.

Claims: A method of manufacturing a package of a power semiconductor device comprising the following sequence of steps: providing a substrate upon which a plurality of subelements (20) is formed within the interior of a package, said package comprising a cup like base (42) with a bottom wall and a side wall terminating in an outwardly extending flange, with each subelement having a gate (26) and a terminal and a contact for each gate and terminal that is to be electrically connected to corresponding contacts of other subelements; providing a plurality of conductive foils (32, 34), one for each of the contacts, each foil being attached to its respective one of said contacts in electrically conductive relationship, each foil having contact pins (36, 38) connected thereto; providing a lid (44) extending laterally outwardly and overlapping said flange for covering the subelements, said lid having a plurality of openings (46), one for each of said contact pins; determining which subelements (20) are operative and which subelements are inoperative providing seals (48) which surround contact pins (36, 38) associated with an operative subelement (20) so that electrical contact can be made therewith, covering or sealing the contact pins of inoperative subelements with appropriate material (58) so that electrical connections cannot be made therewith, electrically connecting respective contact pins for operative subelements. A method as claimed in claim 1, wherein contact pins (36, 38) associated with an inoperative subelement are shortened so that they do not extend through openings (46) of said lid (44), and said contact pins (36, 38) associated with operative subelements extend through openings (46) of said lid (44). A method as claimed in claim 1 or 2, wherein a plurality of electrically conductive sheets (28, 30) are provided, one for each of the gate contacts (26), said conductive sheets being each substantially larger than their respective gate contacts (26) and being bonded to the gate contacts and to said foils (32, 34). A method as claimed in any one of claims 1 to 3, wherein each of the subelements has plural electrical contact pads that are to be electrically connected to corresponding pads of other subelements with inoperative subelements not being electrically connected, and electrical connections are made among operative subelements (20) contacting the extended portions of contact pins associated with said operative subelements, whereas no electrical connections are made between contact pins that are each associated with a pad for an inoperative subelement. A method as claimed in claim 4, wherein each of said contact pins comprises a foil (32, 34) that is in an electrically conductive relationship with a pad, said foil having a tab depending therefrom, and comprising a plurality of electrically conductive sheets, one for each of the contact pads, that are each bonded to a contact pad and to its respective said foil. A method as claimed in claims 4 or 5, wherein the semiconductor device is a MOS gated power device with at least six subelements, and the contact pads comprise a gate contact (26) and an emitter contact for each subelement (20), and providing a plurality of electrically conductive sheets (28, 30), one for each gate contact (26), that are each substantially larger than their respective gate contacts, and that are bonded to the gate contacts.

Inventors: GLASCOCK HOMER H II, TEMPLE VICTOR A K, WATROUS DONALD L, GLASCOCK, HOMER H., II, TEMPLE, VICTOR A.K., WATROUS, DONALD L.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1994
Main classification: H01L25
IPC codes: H01L23, H01L25