A/D converter having a variable integrator whose time constant can be changed

Abstract: Pulse signals indicating up or down of a time constant are received and counted. When a time-out occurs, a time constant change signal is output. At up counting, when input signal is low, the flip-flop 80 of each bit is forcibly set to 1. Then, an up counter consisting of the high-order two bits (control bits) is provided. A time constant of a variable integrator is changed in response to output of the high-order two bits, so that the time constant can be changed rapidly. On the other hand, if the input signal is high, a 5-bit down counter is provided. Thus, the time constant of the variable integrator can be changed gently.

Description: This invention relates to an A/D converter for use with a delay circuit and more particularly to an A/D converter containing a variable integrator whose time constant is changed. Hitherto, a surround sound of an audio machine has been produced by delaying a reproduced sound for a predetermined time, attenuating, and superposing the resulting sound. Such reproduction modes as a stadium mode and a church mode are available for delaying and superposing reproduced sounds by different techniques. One of the delay circuits used for such purposes is shown in Figure 1. In the circuit, an analog reproduction signal is temporarily converted into digital data by an A/D converter 10 and the digital data is stored in a memory 12. The data read from the memory 12 is converted back into analog data by a D/A converter 14. In the circuit, the write time into and read time out of the memory 12 are varied and the difference therebetween becomes a delay time. Used as the A/D converter 10 is one as shown in Figure 2. The A/D converter 10 comprises an adder 20, a quantizer 22, a variable integrator 24, and a control section 26; an analog output of the variable integrator 24 is fed back into the adder 20 to which an analog signal is input. The quantizer 22 comprises a comparator 22a which outputs high or low in response to input signal voltage and a latch circuit 22b which latches the output of the comparator 22a in response to a predetermined clock for converting an input signal into a 1-bit digital signal. The variable integrator 24 integrates outputs of the quantizer 22 for providing an analog signal corresponding to the input signal. The output of the variable integrator 24 is fed back into the adder 20, which then finds a difference between both the signals; for the input signal with no change, the quantizer 22 outputs high and low, namely, "1" and "0" alternately. On the other hand, the control section 26 changes a time constant in the variable integrator 24 in response to the output state of the quantizer 22. That is, if the output level of the adder 20 is large and the quantizer 22 makes an unbalanced output between "0" and "1," the time constant of the variable integrator 24 is made small; if the output level of the adder 20 is small and the quantizer 22 outputs "0" and "1" keeping a balance therebetween, the time constant of the variable integrator 24 is made large. Under such control, when there is silence, the time constant can be made large to suppress occurrence of high-frequency noise; when the input signal changes, the time constant can be made small to output a high tone sufficiently. In the D/A converter 14, the analog signal is restored in response to the signal read from the memory 12. At that time, the same variable integrator as the A/D converter 10 is used to provide the same analog signal as the input signal. Thus, in the conventional circuit, the time constant of the variable integrator 24 is determined uniquely in response to the detected level. That is, the time constant is changed in the same degree for attack, in which sound becomes large rapidly, and for recovery, in which sound becomes small rapidly. If the signal subjected to such signal processing is reproduced, the listener feels a sense of acoustic disorder. If the time constant is set too large, high frequencies are cut too much in the beginning of attack; if the time constant is set too small, high frequencies are cut rapidly during recovery. In the conventional device, the control width when the time constant is changed is always the same, and if the input signal changes rapidly and largely, it cannot be followed up and slant overload distortion on the waveform of reproduced sound becomes large. JP-A-61050424 discloses an A/D converter with a variable integrator, in which a control signal for the integrator is derived from the input analogue signal via a differentiator. If the slope of the input signal is above (or below) a threshold value, an additional parallel resistor is switched into the integrator feed back. Reference is also made to: IEEE Transaction on Consumer Electronics Vol.35, No.4, November 1989, pages 767-773, "One-Bit A/D D/A Converters IC for Audio Delay", by Tsutomu Ishikawa et al. This article discloses an A/D converter which is generally of the kind discussed above, having a variable integrator in which the response is charged in accordance with the bit stream from the quantiser. Instead of controlling the gain of an amplifier with a fixed integrator, the article proposes a sliding band filter in which the cut-off frequency is shifted. EP-A-0308826 discloses a further example of such an A/D converter with a variable frequency low-pass adaption filter. The control signal for the filter is derived from the quantiser pulse stream via a low-pass filter, a rectifier and a smoothing circuit. The smoothing circuit is described as having a fast attack/slow decay characteristic. It is therefore an object of one embodiment of the invention to provide an A/D converter having a variable integrator capable of preferred following-up both at attack and at recovery. The present invention provides an A/D converter in accordance with the accompanying claims. Thus, the change direction detection means detects the direction in which an input signal change becomes large or small. Control is performed so that a time constant change speed accelerates, upon detection of the direction in which an input signal change becomes large, as compared with the direction in which an input signal change becomes small. That is, when the input signal changes from the state with no change to the large change state, the time constant is changed promptly. In contrast, if the input signal changes from the large change state to the small change state, the time constant is changed gently. Thus, according to a delay circuit using the A/D converter at attack, the time constant can be changed promptly for preventing a high tone from being cut and at recovery, a high tone can be cut gradually to reduce a sense of acoustic disorder. The change direction detection means may comprise: a counter for counting high or low duration of the pulse string signal output by the quantizer for a predetermined time; and decode means responsive to whether or not a value of the counter is a predetermined intermediate level for outputting a high or low signal, whereby a large or small change is detected in response to whether the decode means outputs high or low. The time constant control means comprises: an up/down counter which serves as an up or down counter in response to the direction in which a change becomes large or small, output by the change direction detection means, whereby the number of bits of the up/down counter is changed at up counting and at down counting, thereby providing a different signal depending on the direction in which a change becomes large or small, for changing the time constant with the signal. The up/down counter may have at least one dummy bit and use the dummy bit for counting only either at up counting or at down counting for changing the number of bits. The time constant control means may control so that the time constant change speed accelerates in sequence if the same change direction continues. Thus, a response accelerates gradually at attack and at recovery. Therefore, when the same state continues, a response can be accelerated gradually and a sense of acoustic disorder can be decreased. The time constant control means may comprise: an up/down counter which serves as an up or down counter in response to the direction in which a change becomes large or small, output by the change direction detection means, whereby the number of bits of the up/down counter is changed in sequence both at up counting and at down counting and is increased in sequence at either up counting or down counting and is decreased in sequence at the other counting, thereby providing a signal which varies and changes in response speed in sequence depending on the direction in which a change becomes large or small, for changing the time constant with the signal. The up/down counter may have at least two dummy bits and change the number of dummy bits used for counting at up counting and at down counting in sequence. Embodiments of the present invention will now be described with reference to the drawings, in which: Figure 1 is a block diagram showing the schematic configuration of a delay circuit of the prior art; Figure 2 is a block diagram showing a configuration example of an A/D converter of the prior art; Figure 3 is a block diagram showing the configuration of an entire control section of the prior art; Figure 4 is a block diagram showing the configuration of an LPF and a full-wave rectifier in the control section of one embodiment of the present invention; Figure 5 is a block diagram showing a configuration example of a counter 50 of one embodiment of the present invention; Figure 6 is a block diagram showing another configuration example of a counter 50 of another embodiment of the present invention; Figure 7 is an illustration showing the count state of the counter 50 of one embodiment of the present invention; Figure 8 is a block diagram showing the configuration of one example of a time constant controller of the present invention; Figure 9 is an illustration showing the flip-flop state in the time constant controller of one embodiment of the present invention; Figure 10 is an illustration showing how a time constant changes according to one embodiment of the present invention; Figure 11 is a block diagram showing the configuration of a time constant controller of another embodiment of the present invention; Figure 12 is an illustration showing the flip-flop state in the time constant controller of one embodiment of the present invention; and Figure 13 is an illustration showing how a time constant changes according to one embodiment of the present invention. Referring now to the accompanying drawings, there are shown preferred embodiments of the invention. [Overall configuration of control section] Figure 3 is a block diagram showing the configuration of a control section of an A/D converter according to one embodiment of the invention. As shown in Figure 3, the control section consists of a low-pass filter 30, a full-wave rectifier 32, and an integrator 34, whereby the high-frequency component of an output of the quantizer 22 is removed, then the level is detected. [Configuration of low-pass filter and full-wave rectifier] In the embodiment, the A/D converter is made of a digital circuit. Figure 4 shows the configuration of the portion of the low-pass filter 30 and the full-wave rectifier 32. A pulse string signal output from the quantizer 22 is input through an input terminal 40 to a D input terminal of a D flip-flop 42. A predetermined clock is input to a CL input terminal of the D flip-flop 42. A Q output of the D flip-flop 42 is input to one input terminal of a NAND gate 44. The clock is input via an inverter 46 to the other input terminal of the NAND gate 44. The D flip-flop 42, the NAND gate 44, and the inverter 46 make up an input signal sampling circuit 48. An output of the NAND gate 44 is inverted, then input to a CL input terminal of a counter 50 for counting outputs of the sampling circuit 48. Also, the clock is input to a timer 52, which then counts the clock and when a predetermined time has elapsed, generates an output signal. The output signal of the timer 52 is input to a D input terminal of a D flip-flop 54, and the clock is supplied to a CL input terminal of the D flip-flop 54. Therefore, the output of the timer 52 is held in the D flip-flop 54. A Q output of the D flip-flop 54 is input to one input terminal of a NAND gate 56 and the inverted clock is input to the other input terminal of the NAND gate 56. An output of the NAND gate 56 is supplied to a reset terminal of the counter 50. Therefore, when the timer 52 times out, the counter 50 is reset. The output of the timer 52 is also supplied to a D input terminal of a D flip-flop 58 having a CL input terminal to which the clock is supplied. Thus, the output of the timer 52 is also held in the D flip-flop 58. On the other hand, an output of the counter 50 is supplied to a D input terminal of a D flip-flop 60 and a Q output of the D flip-flop 54 is supplied to a CL input terminal of the D flip-flop 60. Thus, when the timer 52 outputs the time-out output, the output of the counter 50 is latched in the D flip-flop 60. Q outputs of the D flip-flops 58 and 60 are supplied to a time constant controller 62. Next, the operation of the circuit in Figure 4 will be discussed. The pulse string input signal output from the quantizer 22 is applied to the input terminal 40 and is sampled by the sampling circuit 48 in response to the clock signal applied to the CL terminal. The clock signal is a signal having a sufficiently higher frequency than the input signal. On the other hand, the timer 52 counts the clock signal, and when counting a predetermined number of clock signals (when a predetermined time has elapsed), outputs high at a + terminal of an output terminal and low at a - terminal. The D flip-flop 54 outputs a signal which goes high for only one clock after the time-out; the D flip-flop 58 outputs a signal which goes low only for one clock after the time-out. The counter 50 counts output signals from the sampling circuit 48 for the predetermined time set in the timer 52. The D flop-flop 42 in the sampling circuit 48 takes in the input signal on the rising edge of a clock signal. When the clock signal is low and the D flip-flop 42 outputs high, the NAND gate 44 supplies high to the counter 50. Therefore, the count value corresponding to the time during which the input signal is high is set in the counter 50. That is, when the input signal contains a large high portion, the count value of the counter 50 increases; when the input signal contains a large low portion, the count value of the counter 50 decreases. Output of the NAND gate 56 is supplied to the reset terminal of the counter 50. When time-out output of the timer 52, which is high, is taken in the D flip-flop 54 and the clock signal goes low, the NAND gate 56 outputs high. Therefore, when the timer 52 times out, the counter 50 is reset. On the other hand, when the time-out output of the timer 52, which is high, is taken in the D flip-flop 54, the high output is supplied to the CL terminal of the D flip-flop 60, which then takes in output of the counter 50 and outputs it through the Q output terminal. The counter 50 is a 4-bit counter having a decoder to generate an output, for example, as shown in Figure 5. In the example in Figure 5, an exclusive-OR gate 70 having input terminals connected to the Q outputs at the third and fourth bits is provided as the decoder. Figure 6 shows another example of the counter 50, wherein the decoder consists of a first AND gate 72 having input terminals connected to the inverted Q outputs at the second and third bits and the Q output at the fourth bit, a second AND gate 74 having input terminals connected to the Q outputs at the second and third bits and the inverted Q output at the fourth bit, and an exclusive-OR gate 76 to which outputs of the first and second AND gates 72 and 74 are applied. In Figure 5, when only either of the Q outputs at the third and fourth bits is high, the exclusive-OR gate 70 of the counter 50 generates an output high; otherwise, it generates an output low, as shown under Output 1 in Figure 7. Thus, if the input signal applied to the input terminal 40 (output of the quantizer 22) is a signal containing unbalanced components between high and low, a low output is generated; if the signal contains a substantially equal balance therebetween, a high output is generated. Therefore, when the input signal state changes, the counter 50 outputs low. In the example in Figure 6, the counter 50 outputs as shown under Output 2 in Figure 7. Thus, when the counter 50 in Figure 6 is used, the high output range is narrower than that when the counter 50 in Figure 5 is used. The output of the counter 50 held by the D flip-flop 60 is applied to the time constant controller 62 as up or down data. That is, up data for reducing the time constant is supplied to the time constant controller 62 as low; down data for increasing the time constant is supplied as high. On the other hand, the output of the D flip-flop 58 is applied to the time constant controller 62 as a clock. Figure 8 shows a configuration example of the time constant controller 62. The time constant controller 62 forms a 5-bit counter (Q1-Q5). The low-order three bits provide dummy bits whose state is changed to the active or inactive state in response to a control signal. The high-order two bits provide control bits which are always active. An output signal of the time constant controller 62 is used to control the time constant of the variable integrator 24; specifically, it is used to control charging current and discharging current of capacitors. When the D flip-flop 60 outputs low, the function of the dummy bits is killed. At this time, only the control bits of the time constant controller 62 serve to count up. In contrast, when the D flip-flop 60 outputs high, the five bits containing the dummy bits serve to count down. Each bit of the time constant controller 62 has a D flip-flop 80, an exclusive-OR gate 82 connected to a D input terminal of the D flip-flop 80, an exclusive-OR gate 84, and an AND gate 86. A Q output of the D flip-flop 80 is output via the exclusive-OR gate 84 and the AND gate 86. The Q output of the D flip-flop 80 is input to one input terminal of the exclusive-OR gate 82 and an output from the D flip-flop 60 is input to one input terminal of the exclusive-OR gate 84. Other input terminals of the exclusive-OR gate 82 and the AND gate 86 of the least significant bit (LSB) are pulled high to a power supply. Bit output at the preceding stage, namely, output of the AND gate 86 of the preceding bit is input to other input terminals of the exclusive-OR gate 82 and the AND gate 86 of each bit other than the LSB. The output of the D flip-flop 60 is input to a preset terminal (when low is input, "1" is preset) of the D flop-flop 80 of each dummy bit. Thus, when the output of the D flip-flop 60 is low (the time constant is changed to a smaller value), the D flip-flops 80 of the dummy bits are all set high, namely, to "1" and an output of the AND gate 86 of the third dummy bit also goes high. Further, a low signal is supplied to one input terminal of the exclusive-OR gate 84 of each bit. Therefore, in each control bit, high Q output of the flip-flop 80 is transferred as a carry via the AND gate 86 and the exclusive-OR gate 82. In this state, output of the flop-flop 58 is supplied to the flip-flops 80 of the control bits as a clock, thus the control bits serve as a normal 2-bit up counter. On the other hand, when the output of the D flip-flop 60 is high (the time constant is changed to a greater value), preset operation is not performed, thus all the flip-flops 80 perform normal operation. High signal is supplied to one input terminal of the exclusive-OR gate 84 of each bit. Therefore, for all bits, low Q output of the flip-flop 80 is transferred as a carry for setting the D flip-flop 80 low via high output of the exclusive-OR gate 84 and high output of the AND gate 86. In this state, output of the flip-flop 58 is supplied to the flip-flops 80 of the control bits as a clock, thus the control bits serve as a normal 2-bit down counter. The count state is shown in Figure 9. Thus, the time constant change circuit in the embodiment operates as a 2-bit counter at up counting and a 5-bit counter at down counting. Therefore, for example, if sound output becomes large from the silent state (attack), the time constant change circuit operates as a 2-bit up counter and outputs a signal for reducing the time constant upon output of the control bits set to "1" "1." In contrast, if sound output becomes small (recovery), it operates as a 5-bit down counter and outputs a signal for increasing the time constant upon output of the control bits set to "0" "0." Thus, the time constant changes rapidly for attack and gently for recovery, as shown in Figure 10. In Figure 9, under down count, only a part of the down counting is shown and the down count does not reach "0" "0." However, it is easily understood that "11111" is down counted to "00000" by subtracting one at a time. Further, Figure 11 shows another configuration example of the time constant controller including a 4-bit counter (Q1-Q4). In the example, an output of a D flip-flop 60 is input to another D flip-flop 90. Q output of the two D flip-flops 60 and 90 is input via an exclusive-OR gate 92 to another D flip-flop 94. The same clock is input to the D flip-flops 60 and 90. The same clock is inverted and supplied to the D flip-flop 94. If there is a high-to-low or low-to-high transition of the up or down indicating signal, an input signal to the D flip-flop 60 results, outputs of the two D flip-flops 60 and 90 differ and the exclusive-OR gate 92 outputs high, which is then set in the D flip-flop 94. Therefore, the circuit can detect a change in up, down count for time constant control (an output change of the D flip-flop 60). Inverted Q output of the D flip-flop 94 is inverted and supplied to reset terminals of D flip-flops 96 and 98. For this reason, the D flip-flops 96 and 98 are reset when the output state of the D flip-flop 94 changes. On the other hand, the control bits have the same configuration as shown in Figure 8, but two dummy bits rather than three are provided and for each dummy bit, an OR gate 100 is inserted in the output route of an AND gate 86 for transferring a carry. Q output of the D flip-flop 96 is input to another terminal of one OR gate 100 and that of the D flip-flop 98 to another terminal of the other OR gate 100. Therefore, if outputs of the D flip-flops 96 and 98 are high, the OR gates 100 output high regardless of the output state of the AND gate 86. Therefore, the two dummy bits can be deactivated by setting high in the D flip-flops 96 and 98. A D input terminal of the D flip-flop 96 is pulled high and Q output of the D flip-flop 96 is input to a D input terminal of the D flip-flop 98. The same clock signal as the D flip-flop 80 is supplied to clock input terminals of the D flip-flops 96 and 98 via an inverter 102, a NAND gate 104, and an inverter 106. Output of the AND gate 86 of the MSB of the control bit is input to another input terminal of the NAND gate 104. Thus, when a carry out of the MSB of the control bit is high, the NAND gate 104 outputs low and the clock can be supplied to the D flip-flop. Therefore, when a carry is generated out of the MSB of the control bit, the D flip-flops 96 and 98 take in data. When the counter thus functions as an up counter, if the control bits overflow from "1" "1," the D flip-flops 96 and 98 are set in order, whereby the dummy bits are decreased one at a time. Therefore, when up counting is continued by the circuit, the dummy bits are decreased in order. On the other hand, when the counter functions as a down counter, if the control bits overflow from "0" "0," the D flip-flops 96 and 98 are reset in order, whereby the dummy bits are increased one at a time. Therefore, when down counting is continued by the circuit, the dummy bits are increased in order. The counting state is shown in Figure 12. For a time constant change for attack and for recovery, a response accelerates gradually, as shown in Figure 13. Therefore, when the same state continues, a response can be accelerated gradually and a sense of acoustic disorder can be decreased.

Claims: An A/D converter having characteristics that can be changed, comprising: a quantizer (22) for quantizing an input analogue signal for outputting a pulse string signal; a variable integrator (24) for integrating the output of said quantizer (22) with a desired time constant; an adder (20) for adding the input analogue signal and an output of said variable integrator (24) and supplying a result of the addition to said quantizer (22); and time constant control means (26) for controlling the time constant of the variable integrator (24) in response to the output of said quantizer (22) to reduce the time constant when the quantizer output is unbalanced and increase the time constant when the quantizer output is balanced, the rate of change of the time constant being greater for quantizer output changes from balanced to unbalanced indicating an increasing change of input analogue signal, than for changes from unbalanced to balanced indicating a decreasing change of input analogue signal, characterised by change direction detection means for detecting whether the change of input analogue signal is increasing or decreasing, said detection means comprising a counter (50) arranged for determining the duration within a predetermined time for which the pulse string signal from the quantizer (22) is in one of a high state or a low state, and a decoder (70) responsive to the count in said counter having a predetermined value to output a logic signal indicating whether the change of input analogue signal is increasing or decreasing. An A/D converter having characteristics that can be changed, comprising: a quantizer (22) for quantizing an input analogue signal for outputting a pulse string signal; a variable integrator (24) for integrating the output of said quantizer (22) with a desired time constant; an adder (20) for adding the input analogue signal and an output of said variable integrator (24) and supplying a result of the addition to said quantizer (22); and time constant control means (26) for controlling the time constant of the variable integrator (24) in response to the output of said quantizer (22) to reduce the time constant when the quantizer output is unbalanced and increase the time constant when the quantizer output is balanced, the rate of change of the time constant being greater for quantizer output changes from balanced to unbalanced indicating an increasing change of input analogue signal, than for changes from unbalanced to balanced indicating a decreasing change of input analogue signal, characterised by change direction detection means for detecting whether the change of input analogue signal is increasing or decreasing, and in that said time constant control means (26) comprises an up/down counter (80) arranged to count up or down in response to whether the change of input analogue signal is increasing or decreasing as detected by said change direction detection means, the number of bits of the up/down counter (80) being different for up counting and for down counting, whereby an output from the up/down counter (80) is different depending on whether the change of input analogue signal is increasing or decreasing, said up/down counter output changing the time constant of the variable integrator (24) accordingly. An A/D converter as claimed in Claim 1, wherein said time constant control means (26) comprises an up/down counter (80) arranged to count up or down in response to whether the change of input analogue signal is increasing or decreasing as detected by said change direction detection means, the number of bits of the up/down counter (80) being different for up counting and for down counting, whereby an output from the up/down counter (80) is different depending on whether the change of input analogue signal is increasing or decreasing, said up/down counter output changing the time constant of the variable integrator (24) accordingly. The A/D converter as claim in either of Claims 2 or 3 wherein said up/down counter (80) has at least one dummy bit (Q1-Q3) and is arranged to use the dummy bit for counting only either at up counting or at down counting. The A/D converter as claimed in any of Claims 1 to 4 wherein said time constant control means (26) is arranged so that the rate of change of the time constant increases progressively if the same change direction continues. The A/D converter as claimed in any of Claims 2 to 4 wherein the number of bits of said up/down counter (80) is changed progressively both at up counting and at down counting and is increased progressively on either up counting or down counting and is decreased progressively on counting in the opposite direction, whereby the up/down counter provides a signal which varies and changes in response speed progressively depending on the direction of change of the input signal, for changing the time constant of the variable integrator (24) accordingly. The A/D converter as claimed in Claim 6 wherein said up/down counter (80) has at least two dummy bits (Q1-Q2) and is arranged to change progressively the number of dummy bits used for counting at up counting and at down counting.

Inventors: ONAYA MASATO, ONAYA, MASATO
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1994
Main classification: H03M3
IPC codes: G10K15, H03M3