BUS MANAGEMENT SYSTEM

Abstract: A bus management node (11) is provided with a used-channel register REG1 and bus capacity register REG2. Before starting synchronous communication, each node (12) transmits a read instruction to the registers REG1 and REG2 to read their contents so as to check for available channels and bus capacity. When an unused channel exists and a bus capacity remains, the node (12) transmits a write instruction to the registers REG1 and REG2 so that the number of used channels and the capacity of used buses can be respectively stored in the registers REG1 and REG2. Therefore, buses can be managed by a simple method in a system which performs synchronous communication among a plurality of nodes connected to the buses.

Description: This invention relates to a method for bus management in a system for performing synchronous communication by way of plural channels between plural nodes connected to a bus. A preferred implementation of the invention described below comprises a bus management method in a communication system in which AV apparatus, such as a video tape recorder (VTR), a monitor or a tuner, are connected to a bus for exchanging digital video signals or digital audio signals. There has been proposed a communication system in which AV apparatus, such as video tape recorder (VTR), a monitor or a tuner, are connected to a bus for exchanging digital video signals or digital audio signals. Fig. 8 shows an example of such a communication system, which is provided with a root node 21, a leaf node 22, a branch node 23, a leaf node 24 and a leaf node 25. Input/ output ports between the nodes 21 and 22, also referred to as nodes 21-22, hereinafter the same, the nodes 21-23, the nodes 23-24 and the nodes 23-25, are connected by two sets of twisted pair cables. The nodes 21 to 25 are digital VTRs, tuners or personal computers, as discussed above, each having one or more input/ output ports. Each node 21 to 25 has an amplifier and a relay enclosed therein. The communication system shown in Fig.8 is equivalent (see Fig. 9) to a communication system in which the nodes 21 to 25 are connected to a bus 26. The structure shown in Fig.8 is a hierarchical structure in which the nodes 22 and 23 are connected in the lower layer relative to the node 21 and the nodes 24 and 25 are connected in the lower layer relative to the node 23. In other words, the node 21 is a master node for the nodes 22 and 23, while the node 23 is a master node for the nodes 24 and 25. The sequence for determining such hierarchical structure is now explained. If the nodes 21-22, 21-23, 23-24 and 23-25 are connected by cables, the node only one input/ output port of which is connected to an other node notifies the node to which it is connected that the latter node is the master node. In the case of Fig.8, the nodes 24 and 25 notify the node 23 of the fact that the node 23 is the master node, while the node 22 notifies the node 21 of the fact that the node 21 is the master node. The node, plural input/ output nodes of which are connected to other nodes notifies a node other than the node which has notified the firstly-stated node that the firstly-stated node is the master node that such other node is the master node. In the case of Fig.8, the node 23 notifies the node 21 that the node 21 is the master node, while the node 21 notifies the node 23 that the node 23 is the master node. Since in such case the nodes 21, 23 notify each other that the counterpart node is the master node, the node which has made such notification first becomes the master node. Fig.8 shows a case in which the node 21 has become the master node. The sequence of according an address to each node is explained. Basically, the node address is accorded by the master node permitting an address to be accorded to a slave node. If there are plural slave nodes, addresses are accorded in the order of the smaller port numbers to which the slave nodes are connected. In Fig.8, in which the node 22 is connected to a port #1 of the node 21 and the node 23 is connected to a port #2 of the node 22, the node 21 permits an address to be accorded to the node 22. The node 22 accords the address (i) to itself and transmits data indicating that the address (i) has been accorded to itself over a bus 26. The node 21 then permits the node 23 to set its own address. The node 23 permits an address to be accorded to the node 24 connected to its port #1. The node 23 permits an address to be accorded to a node 25 connected to its port #2. The node 23 accords an address (iii) to itself. After having accorded addresses to its slave node 24 and slave node 25, the node 23 accords an address (iv) to itself. After having accorded addresses to its slave node 22 and slave node 23, the node 21 accords an address (v) to itself. With the present communication system, it is possible to carry out synchronous communication or continuous communication at a constant data rate and asynchronous communication for transmitting control commands, for example, non-periodically, that is whenever the necessity arises. With the present communication system, communication is carried out at a communication cycle having a pre-set period, such as 125 µs, as shown in Fig.10. The communication cycle starts with a cycle start packet csp, followed by a period for transmitting a packet for synchronous communication. By affixing channel numbers 1, 2, 3, ...N to the respective packets for synchronous communication, plural synchronous communication cycles may be carried out. For example, if the channel 1 is allocated to the communication from the node 22 to the node 23, communication is carried out by the node 22 transmitting the packet for synchronous communication having the channel number 1 directly after the cycle start packet csp and by the node 23 monitoring the bus 26 and fetching the packet for synchronous communication having the channel number 1. Similarly, the communication from the node 24 to the node 21 can be accorded to the channel 2, while the packet of a channel can be received by plural nodes. If plural synchronous communication cycles are carried out, it is attempted to transmit the packets for synchronous communication over plural channels directly after the cycle start packet cps. In such case, the packet of synchronous communication of a channel is first transmitted by arbitration means (such as CSMA/CD) as determined by the bus 26. The packets of synchronous communication of other channels are then transmitted sequentially. After termination of transmission of the packets of synchronous communication of all of the channels, the time interval until the next cycle start packet csp is employed for asynchronous communication. To the packets for asynchronous communication (packets A and B in Fig.10) are affixed addresses of the transmitting node and the receiving node. The respective nodes fetch the packets having the addresses proper to the nodes affixed thereto. Since the details of the above-described communication system are publicized as "IEEE P1394 Serial Bus Design Statement, they are not explained herein specifically. In order for the above-described communication system to operate correctly, it is necessary for the respective synchronous communication packets to have different channel numbers, while it is necessary for the sum total of the communication time of the synchronous communication packets of the respective channels not to exceed the period of the synchronous communication. To this end, it is necessary to check before the start of synchronous communication of a node that the communication capacity necessary for the communication is available on the bus and to have an un-used channel allocated for the communication if there is any residual communication capacity in the bus. For supervising the communication capacity and the channel number employed for synchronous communication, it is commonplace practice that one of the nodes connected to a bus become a bus management node and to effect required management. In such case, other nodes indicate the communication capacity desired to be employed to the bus management node, using the asynchronous communication packet, and require channels to be allocated to them. The bus management node checks if the communication capacity in use added to the communication capacity newly requested does not exceed the maximum communication capacity of the bus. If the sum is not in excess of the maximum communication capacity of the bus, the bus management node notices the channel number and the effect of permission of synchronous communication. If the sum is in excess of the maximum communication capacity of the bus, the bus management node notices that the channel allocation is not permitted. After termination of the synchronous communication, the management node is notified of the channel number and the channel capacity which will not be in use. Since the bus supervision is in need of complex processing operations, it is commonplace practice with the communication system centered about, e.g., a personal computer to use the personal computer as a bus management node and to perform the processing operations using the software possessed by the personal computer. However, if this method is employed for the communication system between the AV apparatus, such as a digital VTR, tuner or a monitor, it becomes necessary to interconnect an apparatus having powerful data processing functions, such as personal computer, to the bus, in addition to the AV apparatus, thus raising the cost of the communication system. Plural channel, multi-node communication systems employing central control terminals are disclosed in US Patent No. US-A-3,851,104 and European Patent Application Publication No. EP-A-0,444,207. In view of the above problem, it is an object of the present invention to provide a method for realizing facilitated management of a bus in a system for carrying out synchronous communication between plural nodes connected to the bus. According to the invention there is provided a method for bus management in a system for performing synchronous communication by way of plural channels between plural nodes connected to a bus, the method being characterised in that: among the plural nodes, a pre-set node having first storage means for storing the number of channels in use and second storage means for storing the vacant bus capacity is set as a bus management node; and each node, when it wishes to acquire a channel for synchronous communication, reads out the contents of the first and second storage means and, if there is a vacant channel and vacant bus capacity, writes the vacant channel number it will use for synchronous communication in the first storage means and updates the vacant bus capacity, to account for its forthcoming synchronous communication, in the second storage means. Thus, the number of channels in use and the bus capacity may be supervised by the bus management node by simply responding to the readout and update commands to the first and second storage means. Each node may have plural communication clocks of different frequencies. Thus, it is possible for each node to carry out communication by the communication clocks of plural different frequencies so that communication of different speeds can exist from channel to channel. In a preferred method described below, if the bus management node is changed while a node is already engaged in synchronous communication, that node executes a channel acquisition operation with respect to the new bus management node within a pre-set time. In this manner, the node already engaged in the synchronous communication executes the operation of acquiring the channel within a pre-set time, while a node newly starting synchronous communication executes the operation of acquiring the channel after the pre-set time has elapsed. Preferably, of the plural nodes, a node having a maximum address is set as the bus management node. Thus, if a root node is determined, it becomes the bus management node. The invention will now be further described, by way of illustrative example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing a specified constitution of a communication system to which the present invention is applied. Fig.2 shows a practical constitution of a register for channels in use and a bus capacity register of a bus management node constituting the bus capacity register. Fig.3 is a flow chart showing a practical example of the sequence of channel acquisition before starting synchronous communication. Fig.4 is a flow chart for showing a practical example of the sequence of operations for channel restoration after termination of the synchronous communication. Fig.5 is a flow chart showing the sequence of setting the bits of the register for channels in use in order to avoid competition between nodes. Fig.6 is a flow chart showing the sequence of subtracting the value of the bus capacity from the value of the bus capacity register in order to avoid competition between nodes. Fig.7 is a flow chart showing the sequence of adding the value of the bus capacity to the value of the bus capacity register in order to avoid competition between nodes. Fig.8 shows an example of a communication system for synchronous communication between plural nodes connected to the bus. Fig.9 is a block diagram equivalently stating the above communication system. Fig.10 shows an example of data construction on the bus in the above-mentioned communication system. Referring to the drawings, preferred embodiments of the present invention will be explained in detail. Fig.1 illustrates the concept of the present invention and Fig.2 shows examples of the construction of a register for channels in use and the bus capacity register shown in Fig.1. Referring to Fig.1, a bus management node 11 has the register for channels in use REG1 and the bus capacity register REG2. The register for channels in use REG1 has the capacity of e.g., 32 bits, each of the bits (bit 0 to bit 31) representing the state of use of channels 0 to 31 (see Fig. 2a), with 1 indicating a channel in use and 0 indicating a channel not in use. As shown in Fig.2b, the bus capacity register REG2 has the capacity of e.g., 32 bits, thus having a value capable of indicating the residual bus capacity or the sum of the capacities in use. Before starting the synchronous communication, an other node 12 in the communication system transmits a readout command to the register for channels in use REG1 and the bus capacity register REG2 over a twisted pair cable 13, using the asynchronous communication packet, and reads out the contents of the command over a twisted pair cable 14 in order to confirm the number of the channel not in use and the residual capacity of the bus. If there is any channel not in use and there is any residual bus capacity, the other node 12 transmits write commands to the register for channels in use REG1 and the bus capacity register REG2 so that the number of the channel in use and the capacity of the bus in use will be written in the register for channels in use REG1 and the bus capacity register REG2. When starting the synchronous communication, the bus management node 11 issues write and readout commands to the register for channels in use REG1 and the bus capacity register REG2 therein in order to effect processing in a similar manner. If the present invention is applied to, for example, the communication system shown in Fig.8, the register for channels in use REG1 and the bus capacity register REG2 are provided in the respective nodes. The bus management node 11 is the node 21 as a root node. If the register for channels in use REG1 and the bus capacity register REG2 are provided in each of the respective nodes, bus management becomes possible no matter which node become the root node. Any node other than the root node may also be used as a bus management node. Referring to Figs.3 to 7, preferred embodiments of the present invention will be explained in detail. In the flow charts, YES and NO in the decision steps are abbreviated to Y and N, respectively. Fig.3 is a flow chart showing an example of the procedure for channel acquisition before starting the synchronous communication. Referring to Fig.3, the node 12 effecting the synchronous communication transmits to the bus management node 11 a command for reading out the contents of the register for channels in use REG1. The contents of the register for channels in use REG1 thus read out are checked in order to give judgement if there is any bit 0. If there is no 0 bit, there is no vacant channel, so that the processing comes to a close. If there is a bit 0, the node 12 proceeds to step S2. At step S2, the node 12 transmits to the bus management node 11 a write command for setting the bit corresponding to the channel number desired to be employed. The node 12 then proceeds to step S3. At step S3, the node 12 transmits to the bus management node 11 a command for reading out the contents of the bus capacity register REG2, and checks the contents of the bus capacity register REG2 thus read out. The node 12 compares the value of the bus capacity register REG2, that is the residual capacity of the bus, to the value of the capacity to be newly in use. If the value of the bus capacity register REG2 is larger, synchronous communication is possible, so that the node 12 proceeds to step S4. If the value of the capacity to be newly in use is found at step S3 to be larger, synchronous communication cannot be carried out, so that the node 12 proceeds to step S6. At step S4, the node 12 issues to the bus management node 12 a write command for setting a value equal to the value of the bus capacity register REG2 less the value of the capacity to be newly in use as a new value of the bus capacity register REG2. The node 12 then proceeds to step S5. The node 12 starts the synchronous communication at step S5. At step S6, the node 12 transmits a write command for resetting to 0 the bit set to 1 at step S2 to the bus management node 11. Fig.4 is a flow chart showing the sequence of operations of returning the channel after the end of the synchronous communication. In the following description, the description as to transmitting a readout command for reading the contents of the registers REG1 and REG2 and as to transmitting a write command for rewriting the register contents. Referring to Fig.4, if the communication comes to a close at step S11, the node 12 proceeds to step S12, where the bit corresponding to the number of the channel of the register for channels in use REG1 which has ceased to be used is reset to 0. At step S13, the node 12 adds the value of the capacity of the bus which has ceased to be used to the value of the register for channels in use REG1. With the above-described sequence of operations, it is possible for the bus management node 11 to allocate the channels by a simplified operation of responding to the write command and the readout command. However, it may occur that, with such sequence of operations, correct processing cannot be made in the case of competition among plural nodes. The sequence of operations capable of coping with such case is explained by referring to Figs.5 to 7. Fig.5 is a flow chart for setting the bit of the register for channels in use REG1, that is the operations corresponding to the steps S1 and S2 of Fig.3. At step S21, the node 12 reads the value (binary number) of the register for channels in use REG1 and sets the value to a . The node 12 then proceeds to step S22. At step S22, the node 12 judges whether or not there is a bit 0 in a . The foregoing processing is substantially the same as the step S1 of Fig.3. If there is no bit 0 in a , the node 12 terminates the operational sequence of channel acquisition, since there is no vacant channel. If there is a bit 0 in a , the node 12 proceeds to step S23. At step S23, the node 12 sets the value of the register REG1 in which the bit corresponding to the channel desired to be used for synchronous communication is set to 1 to b , before proceeding to step S24. If at step S24 the value of the register for channels in use REG1 is a , the node 12 rewrites the value to b , before proceeding to step S25. That is, the processing at step S24 is the processing provided for evading the competition with other nodes. This step S24 can be implemented by a node desiring to occupy a channel transmitting a command to the bus management node 11 for rewriting the value of the register for channels in use REG1 from a to b . The value of the register for channels in use REG1 being a means that an other node has not rewritten the value of the register for channels in use REG1 since the time the node 12 read at step S21 the value of the register for channels in use REG1 until step S24. Conversely, the value of the register for channels in use REG1 not being a means that an other node has rewritten the value of the register for channels in use REG1. At step S25, the node 12 judges whether or not the rewriting has resulted in success. If the result is YES, that is the rewriting has succeeded, the node 12 terminates the operating sequence. If otherwise, the node 12 returns to step S21. The decision as to the success/ failure may be given based on the notice of the results of writing transmitted from the bus management node 11, or by reading out the value of the register for channels in use REG1 and checking whether or not it has been rewritten to b . Fig.6 is a flow chart showing the operating sequence of subtracting the bus capacity value from the value of the bus capacity register REG2, that is the operating sequence corresponding to the steps S3 and S4. At step S31, the node 12 reads the value of the bus capacity register REG2 and set the value to c . The node 12 then proceeds to step S32 in which the node 12 judges which of c and the capacity value of the bus to be used newly is larger. The above processing is substantially the same as the step S3 shown in Fig.3. If c is smaller than the capacity value of the bus to be used newly, synchronous communication cannot be carried out, so the node 12 resets the value of the register for channels in use REG1 to its original value, as at step S6 shown in Fig.3. If c is larger than the capacity value of the bus to be used newly, synchronous communication can carried out, so the node 12 proceeds to step S33. At step S33, the node 12 subtracts the capacity value of the bus desired to be used from c to give d before proceeding to step S34. If at step S34 the value of the bus capacity register REG2 is c , the node 12 rewrites it to d before proceeding to step S35. That is, the step S34 is the processing for avoiding competition with other nodes. The value of the bus capacity register REG2 being c means that an other node has not rewritten the value of the bus capacity register REG2. Since the time the node 12 has read out at step S31 the value of the bus capacity register REG2 until step S34. Conversely, the value of the bus capacity register REG2 not being c means that another node has rewritten the value of the bus capacity register REG2. At step S35, the node judges whether or not rewriting has succeeded. If the rewriting has succeeded, the node 12 terminates the processing and, if otherwise, the node 12 returns to step S31. Fig.7 is a flow chart showing the operating sequence of adding the bus capacity value to the value of the bus capacity register REG2, that is the operating sequence corresponding to the step S13 of Fig.4. At step S41, the node 12 reads the value of the bus capacity register REG2, and sets it to e before proceeding to step S42. At step S42, the node adds the capacity value of the bus whose end has come to a close to e and sets the sum to f before proceeding to step S43. If at step S43 the value of the bus capacity register REG2 is e , the node 12 rewrites it to f before proceeding to step S44. At step S44, the node 12 judges whether or not the rewriting has succeeded. If the rewriting has succeeded, the node 12 terminates the processing and, if otherwise, the node 12 returns to step S41. Since the meaning of each processing in the sequence of operations is apparent from the explanation given in connection with Figs.5 and 6, the corresponding description is omitted for simplicity. The value to be stored in the bus capacity register REG2 is now explained. In the present embodiment, the bus capacity register REG2 stores the un-used portion of the time period in the time period of synchronous communication cycle of 125 µs that may be used for synchronous communication, as counted based on the basic clocks used for communication. Thus the register REG2 stored time-based values. If, as an example, the basic clock of communication in a bus system of 98.304 Mbps is 49.152 MHz, and 100 µs within the period of 125 µs is to be useable for synchronous communication, with the remaining 25 µs being used for transmission of the cycle start packet csp shown in Fig.10 and for the asynchronous communication packets A and B, the maximum value of the bus capacity corresponds to 4915 basic clocks. Thus the bus capacity register REG2 is initially set to 4915 from which the number of clocks corresponding to the bus capacity value used for each channel allocation to the node 12 is subtracted. For example, when starting the synchronous communication of 10 Mbps, data equal to 1250 bits per synchronous communication cycle is transmitted. The time consumed for transmitting the data is equal to 625 basic clocks for transmitting data per se plus the overhead time consumed for bus arbitration or the like. If the overhead is 1 µs, corresponding to 50 basic clock periods, 675 is to be subtracted from the bus capacity register REG2. If each node in the communication system is capable of communication with the basic clocks of plural different frequencies, for example, 49.152 MHz, 2 x 49.152 MHz or 4 x 49.152 MHz, and plural synchronous communication cycles are carried out at different basic clocks, it suffices to set the value stored in the bus capacity register REG2 so as to be equal to the value counted by a selected one of the plural basic clocks. The operation when the constitution of the communication system has been changed during the synchronous communication has been changed is explained. If, for example, the cable between the nodes 21 and 23 between the nodes 23 and 24 in the communication system shown in Fig.8 is disconnected during the synchronous communication, there is no bus management node in the communication system including the nodes 23 and 24. For avoiding such problem, if a node is disconnected or connected during the synchronous communication, the node with the maximum address in the new construction of the communication system is set as a new bus management node. If the bus management node is determined, the node engaged in synchronous communication executes a channel acquisition sequence with respect to the new bus management node within a pre-set time, while the node newly starting the synchronous communication executes the channel acquisition sequence after lapse of the pre-set time. It is possible for the node already engaged in synchronous communication to start the synchronous communication immediately and to execute the channel acquisition sequence as a parallel operation. By so doing, if the bus management node is changed, channel allocation is made preferentially to the node engaged in synchronous communication before such change in the bus management node. Thus the state which has prevailed before change in the bus management node may be reflected in the registers REG1 and REG2 of the new bus management node. In the above explanation, it is assumed that all nodes in the communication system have the register for channels in use REG1 and the bus capacity register REG2. If this is not the case, the nodes having the register for channels in use REG1 and the bus capacity register REG2 are retrieved beginning from the node having the address (i) and the node found out first is set as the bus management node. Industrial Applicability As discussed above in detail, the subject-matter of claim 1 provides a method for bus management in a system for performing synchronous communication between plural nodes connected to a bus, wherein, among the plural nodes, a pre-set node having first storage means for storing the numbers of channels in use and for storing the vacant bus capacity is set as a bus management node, each node reading out the contents of the first and second storage means when starting the synchronous communication. If there is any vacant channel or any vacant capacity, each node writes the number of the channel and the capacity of the bus started to be used in the first and second storage means, respectively. Since it is possible for the bus management node to manage the channel number and the bus capacity by simply responding to the readout command and the write command to the first storage means and to the second storage means, the method may be implemented by a simplified hardware. The subject-matter of claim 2 provides for an arrangement in which each node has plural communication clocks of different frequencies. Since the communication cycles with different plural frequencies can be caused to co-exist from channel to channel, it becomes possible to cope with data with different transmission rates, such as video data or audio data. The subject-matter of claim 3 provides for an arrangement in which, if the bus management node is changed within the pre-set time during the synchronous communication, the node already engaged in the synchronous communication executes the sequence of channel acquisition within a pre-set time. Consequently, channel allocation may be made preferentially to the node engaged in the synchronous communication before the bus management node is changed. The subject-matter of claim 4 provides for an arrangement in which the node having the maximum address is set to the bus management node, so that the bus management node may be automatically determined when the root node is set. The subject-matter of claim 5 provides for an arrangement in which the bus use state stored in the second storage means has time-based values, so that bus capacity management becomes possible even if the communication cycles with different rates co-exists from channel to channel.

Claims: A method for bus management in a system for performing synchronous communication by way of plural channels (ch1 - chN) between plural nodes (11, 12) connected to a bus, the method being characterised in that : among the plural nodes (11, 12), a pre-set node (11) having first storage means (REG1) for storing the numbers of channels in use and second storage means (REG2) for storing the vacant bus capacity is set as a bus management node; and each node, when it wishes to acquire a channel for synchronous communication, reads out the contents of the first and second storage means (REG1, REG2) and, if there is a vacant channel and vacant bus capacity, writes in use the vacant channel number it will use for synchronous communication in the first storage means (REG1) and updates the vacant bus capacity, to account for its forthcoming synchronous communication, in the second storage means (REG2). A method according to claim 1, wherein each node has plural communication clocks of different frequencies. A method according to claim 1 or claim 2, wherein, if the bus management node is changed while a node is already in synchronous communication, that node in synchronous communication executes a channel acquisition operation with respect to the new bus management node within a pre-set time. A method according to any one of the preceding claims, wherein, among the plural nodes, the node having the maximum address is set as the bus management node. A method according to any one of the preceding claims, wherein the vacant bus capacity stored in the second storage means (REG2) has time-based values. A method according to any one of the preceding claims, wherein: the plural nodes of the system can also perform asynchronous communication via the bus; and each node, when it wishes to acquire a channel for synchronous communication, reads out the contents of the first and second storage means (REG1, REG2) by way of asynchronous communication via the bus.

Inventors: HAYASHI MINOBU, KUBOTA ICHIRO, MATSUNO KATSUMI, SHIMA HISATO, HAYASHI, MINOBU, KUBOTA, ICHIRO, MATSUNO, KATSUMI, SHIMA, HISATO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: H04L12
IPC codes: H04L12