Correlation detector

Abstract: A correlation detector capable of obtaining a more correct and natural correlation value. The correlation detector outputs a correlation value representative of autocorrelation in accordance with a sum (r + ra) of the number r of consecutive autocorrelated data items before one timing and the number ra of consecutive autocorrelated data items after the one timing.

Description: Background of the Invention Field of the Invention The present invention relates to a correlation detector for outputting a degree of autocorrelation of a digital signal obtained by sampling and quantizing an analog signal. A degree of autocorrelation corresponds to the number of consecutive samples each of which has a substantially identical quantized level. Related Background Art A correlation detector for detecting a degree of correlation of an input signal has generally a circuit structure such as shown in Fig. 7. An input signal is sampled by a sampling pulse having a frequency F, and a presence/absence of autocorrelation between data of the input signal at one timing and at a timing immediately before the one timing is detected by an autocorrelation detector circuit 1. (A presence of autocorrelation between two data samples means that two data samples have a substantially identical quantized level, and reversely an absence of autocorrelation between the means that they have different quantized levels). In accordance with the detection results, an autocorrelation counter 2 counts the number r of consecutive autorelated date items (i.e. the number r of consecutive samples having a substantially identical quantized level) before one timing of the input signal. A value D0 corresponding to the output r of the autocorrelation counter 2 is outputted as a correlation value. The operation of the conventional correlation detector shown in Fig. 7 will be described. The autocorrelation detector circuit (SREL) 1 is supplied with an input signal IN sampled at a clock ck such as shown in Fig.6. A presence/absence of autocorrelation between data of the input signal at one timing and at a timing immediately before the one timing is detected, and the detection result is outputted as a correlation presence/absence signal f which is inputted to the autocorrelation counter 2. The length of the H level of the signal f is outputted as the count signal r from the autocorrelation counter 2 which is inputted to an encoder 5. The encoder 5 outputs D0 = 0 for 0 ≤ r ≤ 1, D0 = 1 for 2 ≤ r ≤ 4, and D0 = 2 for 5 ≤ r. There is a one clock delay when D0 is outputted. Therefore, the input signal IN is delayed by one clock to obtain a delayed input signal IND which is compared with the signal D0. At a timing α1 of the signal IND, three consecutive autocorrelated data items are present before the timing α1, and so r = 3 at α1. Five consecutive autocorrelated data items are present before a timing α2, and so r = 5 at α2. The signal r is inputted to the encoder 5 which outputs a value corresponding to the value r . In this case, D0 = 1 at α1, and D0 = 2 at α2. An output D0 of the conventional correlation detector is a value corresponding to the value r which is the number of consecutive autocorrelated data items before one timing of the input signal, and is not the number of consecutive autocorrelated data items after one timing of the input signal. Therefore, a correlation value obtained by the conventional correlation detector is not natural from the viewpoint of senses. SUMMARY OF THE INVENTION It is an object of the present invention to provide a correlation detector capable of obtaining a more correct and natural correlation value. This object is achieved by the invention as defined in claim 1. Thus according to the present invention solving the above problem, there is provided a correlation detector for outputting a correlation detector outputs a correlation value representative of autocorrelation in accordance with a sum (r + ra) of the number r of consecutive autocorrelated data items before one timing and the number ra of consecutive autocorrelated data items after the one timing. According to an embodiment of the present invention, there is provided a correlation detector including: an autocorrelation detector circuit for receiving an input signal sampled by a sampling pulse having a frequency F and outputting a signal representative of a presence/absence of autocorrelation between data of the input signal at one timing and data at a timing immediately before the one timing; an autocorrelation counter receiving an output of the autocorrelation detector circuit and counting and outputting the number r of consecutive autocorrelated data items before the one timing; an encoder for receiving an output of the autocorrelation counter and outputting a value D0 determined in correspondence with the number r ; n comparators for receiving an output of the autocorrelation counter, comparing the number r with predetermined values r1, r2,..., rn, and outputting signals e1, e2,..., en indicating timings when the number r becomes equal to the values r1, r2,..., rn; n time counters for receiving the outputs of the n comparators and outputting signals c1, c2,..., cn representative of the count period starting in response to the signals e1, e2,..., en and terminating after predetermined periods of T1, T2,..., Tn; a memory read/write controller for receiving the outputs of the n time counters and outputting a write gate signal NW causing a period t0 to be always a write period, causing periods t1, t2, ..., tn to be a write period only when the signals e1, e2,... en are generated, and causing a period t(n + 1) to be always a read period, the periods t0, t1, t2,..., tn, t(n + 1) being obtained by dividing a 1/F period into (n + 2) periods or more; a memory data controller for receiving an output of the encoder, outputting the value during the period t0, and outputting predetermined values D1, D2,..., Dn during the periods t1, t2,..., tn; an address counter for counting a clock having the frequency F and outputting a count Ac; a memory address controller for receiving an output of the address counter and outputting values Ac + A0, Ac + A1, Ac + A2,..., Ac + An, and Ac + A(n + 1) obtained by adding the count Ac to predetermined values A0, A1, A2,..., An, and A(n + 1); a memory whose read/write is controlled by the outputs of the memory read/write controller, the memory data controller, and the memory address controller; and a sampler for sampling and outputting an output of the memory during the memory read period. The correlation detector of this embodiment outputs a correlation value representative of autocorrelation in accordance with a sum (r + ra) of the number r of consecutive autocorrelated data items before one timing and the number ra of consecutive autocorrelated data items after the one timing. For example, referring to Fig.6, eight consecutive autocorrelated data items are present during the period α, and the periods α1 and α2 belong to the same group. According to the present invention, a degree of autocorrelation is less natural from the viewpoint of senses if it is determined basing upon the number f of consecutive autocorrelated data items before one timing, than if it is determined basing upon the number r = ra of consecutive autocorrelated data items before and after the one timing. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a block diagram showing the structure of a correlation detector according to an embodiment of the present invention. Fig.2 is a timing chart explaining the operation of the correlation detector shown in Fig.1. Fig.3 is a timing chart explaining the operation of the correlation detector shown in Fig.1. Fig.4 is a block diagram showing the structure of a modification of a correlation detector according to the invention. Fig.5 is a timing chart explaining the operation of the correlation detector shown in Fig.4. Fig.6 is a timing chart explaining the operation of a conventional correlation detector. Fig.7 is a block diagram showing the structure of a conventional correlation for detecting a degree of correlation of an input signal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the accompanying drawings. Fig.1 is a block diagram showing the structure of a correlation detector according to an embodiment of the present invention. The operation of the correlation detector shown in Fig.1 will be described with reference to the timing charts shown in Figs.2 and 3. In the following description, it is assumed N = 2. An address counter 6 is supplied with a clock ck having a frequency F, and outputs a count Ac. An autocorrelation detector circuit 1 is supplied with an input signal IN sampled at a clock ck such as shown in Fig.6, and outputs a signal f representative of a presence/absence of autocorrelation between data of the input signal at one timing and at a timing immediately before the one timing. This signal f is inputted to an autocorrelation counter 2 which counts the H level length of the signal f and outputs a count r . The count r of the autocorrelation counter 2 is supplied to a comparator (COMP) 3A which outputs an L level signal e1 only when the count r is r = r1 (= 2). The signal el is inputted to a time counter 4A which outputs an H level signal c1 only during a T1 ( = 2/F) period starting from the rising edge of the signal e1. The signal r is also supplied to a comparator 3B which outputs an L level signal e2 only when the count r is r = r2 (= 5). The signal e2 is inputted to a time counter 4B which outputs an H level signal c2 only during a T2 ( = 5/F) period starting from the rising edge of the signal e2. The output signals c1 and c2 of the time counters 4A and 4B are inputted to a memory read/write control circuit 7. While the signal c1 takes the H level, the period t1 during a 1/F period takes the L level, and while the signal c2 takes the H level, the period t2 during the 1/F period takes the L level. The period t0 during the 1/F period always takes the L level irrespective of the level of the signals c1 and c2. As a result, a signal NW is outputted from the memory read/write circuit 7. A portion p of the signal NW is shown enlarged in Fig.3. As indicated at NWL in Fig.3, the periods t0 and t2 take the L level. The output r of the autocorrelation counter 2 is also supplied to an encoder 5 which outputs a signal D0 = 0 for 0 ≤ r ≤ 1, D0 = 1 for 2 ≤ r ≤ 4, and D0 = 2 for 5 ≤ r. The signal D0 is supplied to a memory data controller 8 which outputs one of "0, 1, 2" (D0) during the period to in the 1/F period, outputs always "1" (D1) during the period t1 in the 1/F period irrespective of the value of D0, and outputs always "2" (D2) during the period t2 in the 1/F period irrespective of the value of D0. As a result, an output D of the memory data controller 8 becomes as shown in Fig.2. The portion p of the signal D is shown enlarged in Fig.3 at DL. It can be seen from Fig.3 that "2" (D0) is outputted during the period t0, "1" (D1) is outputted during the period t1, and "2" (D2) is outputted during the period t2. An output Ac of the address counter 6 is supplied to a memory address controller 9 which outputs a signal A = "Ac - 1" (Ac + A0) during the t0 period in the 1/F period, A = "Ac - 4" (Ac + A1) during the t1 period in the 1/F period, A = "Ac - 7" (Ac + A2) during the t2 period in the 1/F period, and A = "Ac - 10" (Ac + A3) during the t3 period in the 1/F period. The portion p of the signal A is shown in Fig.3 at AL. Since Ac = 14, "13" (Ac + A0) is outputted during the period t0, "10" (Ac + A1) is outputted during the period t1, "7" (Ac + A2) is outputted during the period t2, and "4" (Ac + A3) is outputted during the period t3. The outputs of the memory read/write controller 7, memory data controller 8, and memory address controller are supplied to a memory 10 to control the memory read/write. An output of the correlation detector can be obtained by sampling an output of the memory 10 during the memory read period t3. If there are r consecutive autocorrelated data items before one timing of an input signal and ra consecutive autocorrelated data items after the timing, the correlation detector performs the above-described operation and outputs a value of r + ra. The reason why the correlation detector outputs this value will be given below. The correspondence between the output Ac of the address counter and the input signal IN is assumed to be that shown in Fig.3. Assuming that the memory address is Am = Ac, the correspondence between the memory address Am and the memory data Dm becomes as shown in Fig.3. Fig.3 also shows the correspondence between the memory address Am and memory data Dm' when the output D0 of the encoder 5 is written in the memory during the period to in the 1/F period. This correspondence is similar to a conventional correlation detector. As understood from a comparison between the memory data Dm and memory data Dm' shown in Fig.3, the memory data is necessarily Dm = "1" at the memory addresses Am = "2" and "3". Similarly, the memory data is necessarily Dm = "2" at the memory addresses Am = "6", "7", "8", "9", and "10". In order to compensate for such discrepancy, according to the present invention, data in the memory is rewritten by using the periods t1 and t2 in the 1/F period. During the periods at Ac = 6 and 7, in response to the output c1 of the time counter 4A, memory data Dm = "1" is written in the memory at the memory addresses Am = "2" and "3" during the period t1 in the 1/F period. During the periods at Ac = 10 and 11, Dm = "1" is written in the memory at the memory addresses "6" and "7". Similarly, during the periods at Ac = "13", "14", "15", "16", and "17", in response to the output c2 of the time counter 4B, Dm = "2" is written in the memory at the memory addresses Am = "6", "7", "8", "9", and "10" during the period t2 in the 1/F period. In reading the memory data Dm, the memory address Am is moved back more than a maximum value (in this case, "7" addresses) of moving back the memory address Am for the data rewrite. In this embodiment, the memory address Am is moved back by "10" addresses for reading the memory data Dm. Memory data at an address moved back to "10" addresses is not rewritten again. Therefore, the correspondence between Am and Dm becomes as shown in Fig.3, and a value corresponding-to an expected correlation value can be read. As described above, the output r of the autocorrelation counter is compared with the predetermined values r1 (= 2) and r2 (= 5) by the two comparators which output signals e1 and e2 indicating timings when the output r becomes equal to the values r1 and r2. The output signals e1 and e2 of the two comparators are supplied to the two time counters which output signals c1 and c2 representative of the count period starting in response to the signals e1 and e2 and terminating after the predetermined periods of T1 (= 2/F) and T2 (= 5/F). The memory addresses are moved back by preset addresses A1 (-4) and A2 (-7) during the periods indicated by the signal c1 and c2, preset data D1 ( = 1) is written in the memory for the signal c1, and preset data D2 ( = 2) is written in the memory for the signal c2. In this manner, a correlation value corresponding to a value of r + ra can be obtained if there are r consecutive autocorrelated data items before one timing of an input signal and ra consecutive autocorrelated data items after the timing. Fig.4 is a block diagram showing the structure of a modification of a correlation detector according to the invention. This modification is a quantization error eliminator which is constituted by a correlation detector (REL) 100 having the structure shown in Fig.1, low-pass filters (LPF) 101 to 103, and a selector (SEL) 104. The operation of the quantization error eliminator will be described with reference to the timing chart of Fig.5. An input signal A is supplied to the correlation detector 100 which outputs a correlation value as a signal B. This signal B is delayed by a predetermined time Td for compensating for the delay time Td of the filter, and outputted as a signal C. The input signal A is also supplied to the three low-pass filters 101 to 103 and filtered. The low-pass filter 101 is a through-filter having no cut-off frequency, the low-pass filter 102 has a cut-off frequency of 10 kHz, and the low-pass filter 103 has a cut-off frequency of 1 kHz. The outputs D, E, and F of the low-pass filters 101 to 103 are supplied to the selector 104 and selectively outputted therefrom in response to the output signal C of the correlation detector 100. As indicated at G in Fig.5, the output signal of the selector 100 shows that it has been subjected to filtering to the extent corresponding to the length of a flat portion. Specifically, since it is considered that the longer the flat portion, the greater the quantization distortion, a through-output of the filter 101 is selected if the correlation value is "0", an output of the filter 102 is selected if the correlation value is "1", and an output of the filter 103 is selected if the correlation value is "2". As described above, in the correlation detector of the invention, the output r of the autocorrelation counter is compared with predetermined values r1, r2, ..., rn by n comparators which output signals e1, e2,..., en indicating timings when the output r becomes equal to the values r1, r2,..., rn. The output signals e1, e2,..., en of the n comparators are supplied to n time counters which output signals c1, c2,..., cn representative of the count period starting in response to said signals e1, e2,..., en and terminating after predetermined periods of T1, T2,..., Tn. The memory addresses are moved back by preset addresses A1, A2,..., An during the periods indicated by the signal c1, c2,..., cn, preset data D1, D2,..., Dn are written in the memory for the signals c1, c2,..., cn. In this manner, a correlation value corresponding to a value of r + ra can be obtained if there are r consecutive autocorrelated data items before one timing of an input signal and ra consecutive autocorrelated data items after the timing. As described above, the correlation detector of this invention can obtain a more natural and precise correlation value.

Claims: An apparatus for processing a digital signal obtained by sampling and quantizing an analog signal at a predetermined sampling period, said apparatus comprising: a first comparator means (1) for comparing a quantized level at one sample point with a quantized level at a sample point immediately before said one sample point; a counter means (2) responsive to the output (f) of said first comparator means for counting the number of consecutive samples having a quantized level which is substantially identical with the quantized level at said one sample point, before said one sample point; an encoder means (5) for outputting a predetermined data value corresponding to a count value (r) outputted from said counter means; a memory means (10) for receiving a read/write control signal (NW), a data signal (D) and an address signal (A) to perform a read or write operation for data; a memory read/write control means (3A-3N, 4A-4N, 7) responsive to the output (r) of said counter means for selectively generating said read control signal or write control signal (NW); a memory data control means (8) responsive to the output (D0) of said encoder means for selectively generating a predetermined data value; and a memory address control means (6, 9) for selectively generating a predetermined address; whereby a data value corresponding to a sum (r+ra) of the number r of consecutive samples having a substantially identical quantized level before said one sample point and the number ra of consecutive samples having said substantially identical quantized level after said one sample point is read out from said memory means. The apparatus according to claim 1, wherein said memory read/write control means comprises a plurality of second comparator means (3A-3N) responsive to the output (r) of said counter means (2) for outputting a plurality of first timing signals (e1) and a plurality of time counters (4A-4N) responsive to the outputs of said second comparator means for outputting a plurality of second timing signals (C1), and said memory address control means comprises an address counter means (6) for incrementing its count value by one unit at said sampling period. The apparatus according to claim 2, wherein said encoder means (5) outputs a data value D0 determined in correspondence with the count value r outputted from said counter means (2); said plurality of second comparator means (3A-3N) compare the counter value r outputted from said counter means (2) with predetermined values r1, r2, r3,..., rn, to output signals e1, e2, e3, ..., en, indicating timings when said count value r becomes equal to said predetermined values r1, r2, re,..., rn; said plurality of time counters (4A-4N) output signals C1, C2, C3,..., Cn, representative of the count period starting in response to said signals e1, e2, e3,..., en, and terminating after predetermined periods T1, T2, T3,..., Tn, said predetermined periods being determined in correspondence with said signals e1, e2, e3,..., en, respectively; said memory read/write control means (7) outputs a write gate signal NW causing a sub period to to be always a write period, causing sub periods t1, t2, t3, ..., tn, to be a write period only when said signals C1, C2, C3,..., Cn, are generated, respectively, and causing a sub period t(n+1) to be always a read period where said sub periods t0, t1, t2, t3, ..., t(n) and t(n+1) are obtained by dividing said sampling period 1/F into (n+2) periods or more; said memory data control means (8) outputs said data value D0 during said sub period to and predetermined data values D1, D2, D3,..., Dn, during said sub periods t1, t2, t3, ..., tn, respectively; said memory address counter means (6) outputs a count value Ac obtained by counting clocks of frequency F; and said memory address control means (9) outputs during said sub period t0, t1, t2, t3,..., tn and t(n+1) the values Ac+A0, Ac+A1, Ac+A2, ..., and Ac+A(n+1), respectively obtained by adding said count value Ac to said predetermined values A0, A1, A2,..., An and A(n+1).

Inventors: IWATA TOSHIO, IWATA, TOSHIO
Applicants: KENWOOD CORP, KABUSHIKI KAISHA KENWOOD
Application year: 1994
Main classification: G06F17
IPC codes: G10L11, G06F17