Transistor gate formation

Abstract: A method for forming transistors having sublithographic features, for example, gates, is disclosed. A patterned hardmask (formed, for example from PETEOS) is created overlying oxide and polysilicon layers. The dimensions of the hardmask are reduced by isotropic etching. The reduced-dimension hardmask is used with an anisotropic etching process to define a reduced-dimension feature such as a gate.

Description: Technical Field This invention relates to methods of semiconductor integrated circuit formation. Background of the Invention As the use of integrated circuits becomes more pervasive, the geometries of individual circuits continue to shrink. Generally speaking, the lithographic process, which involves patterning a photoresist material and subsequently anisotropically etching underlying layers, determines the size of the smallest features which can be created in an integrated circuit. However, designers have continually sought techniques which will produce features or openings which have dimensions that are less than what may be achieved by conventional lithography. One of the most fundamental features of a MOSFET (metal oxide semiconductor field effect transistor) is the gate. Generally speaking, circuits with smaller gates operate more quickly, and contain more transistors. The prior art documents DE-A-3 915 650 and EP-A-0 394 597 disclose different techniques to pattern a layer in order to form the gate of a transistor, wherein the size of a mask is reduced by isotropic etching to under the limit of resolution of the exposure apparatus. Summary of the Invention The present invention addresses the above-mentioned concerns, and is defined by the appended claim. Brief Description of the Drawings FIGS. 1-4 are cross-sectional views of an illustrative embodiment of the present invention. Detailed Description In the following description it will be referred to thicknesses expressed in Angströms (Å). One Angström equals 0.1 nm. In FIG. 1 reference numeral 11 denotes a substrate of silicon, doped silicon, epitaxial silicon, or a layer of epitaxial silicon upon doped silicon, etc. In general, the term substrate refers to a material or body upon which a variety of layers may be formed. Reference numeral 13 denotes a dielectric layer, typically silicon dioxide or, possibly, silicon oxynitride. Typically, layer 13 is formed upon substrate 11 (after the field oxide has been formed) by thermal oxidation. The thickness of layer 13 may be typically between 50Å and 500Å. Layer 15 is a layer of conductive polysilicon (which may or may not be doped at this juncture). The thickness of layer 15 is typically between 500Å and 5000Å. Layer 15 may be typically formed by chemical vapor deposition. Layer 17 is a layer of tungsten silicide. The thickness of layer 17 is between 500Å and 5000Å. Layer 17 may be formed by a variety of means including sputtering or chemical vapor deposition. Layer 19 is a dielectric used as a hardmask in a hardmask etching process. Layer 19 is formed from plasma-enhanced TEOS. If layers 13, 15 and 17 have thicknesses within the ranges mentioned previously, the thickness of layer 19 is desirably between 1000Å and 3000Å. Feature 21 is a patterned photoresist. The length L of feature 21 may be assumed to be the smallest dimension achievable by lithography. Turning to FIG. 2, patterned photoresist has been utilized in connection with an anisotropic etching process, typically involving CF 4 and O 2 to form raised feature 23 from layer 19. Photoresist 21 is then removed. In FIG. 3, raised feature 23 is subjected to an isotropic process producing a smaller raised feature 25. For example, if raised feature 25 has a length, L , equal to 0.5 µm and a height equal to 0.25 µm (i.e., the thickness of layer 19), it may be subjected to a wet etching process using 100:1 HF for a period of time between 2 minutes and 5 minutes. The wet etching process is isotropic and may be expected to shrink the height of feature 21 by an amount between 0.02 µm and 0.05 µm because both the left and right sides of feature 21 are attacked by the isotropic process. Consequently, the length L of feature 25 is reduced by approximately twice the amount that the height of feature 21 is reduced. Mathematically, L = M + 2 Δ where Δ equals the quantity of isotropic material removal. Feature 25, which has been reduced by the isotropic etching process to a length substantially smaller than what is achievable lithographically, is now used as a hardmask for the subsequent anisotropic etching of at least layers 17, 15. It is important to keep in mind, when choosing the initial thickness of layer 19 in FIG. 1, that hardmask feature 25 must still have sufficient height after the isotropic etching of FIG. 3, to withstand the rigors of the subsequent anisotropic etching process which will attack layers 17 and 15. Turning to FIG. 4, feature 25, having length M substantially smaller than what is lithographically achievable, is utilized as a hardmask in the anisotropic etching of layers 17, 15 and 13. Typically, the anisotropic etching may be performed by HBr and Cl 2 . Layers 17, 15 and 13 ultimately comprise gate stack 27. Subsequent semiconductor integrated circuit processing may commence at this point, including definition of source and drain regions by, for example, ion implantation, deposition of a dielectric layer, contact window opening to source/drain, etc.

Claims: A method of forming an integrated circuit having at least one transistor with a gate comprising: forming a layer of dielectric (13) upon a silicon substrate (11); forming a layer of polysilicon (15) upon said layer of thermal oxide; forming a layer of tungsten silicide (17) upon said layer of polysilicon; forming a layer of dielectric from plasma-enhanced TEOS (19) upon said layer of tungsten silicide; forming a patterned resist (21) over said layer of dielectric; patterning said dielectric (19) using said patterned resist (21) as a mask to form a raised topographic feature (23) having at least one dimension (L); removing said resist; isotropically etching said patterned dielectric (23), thereby reducing said dimension; using said isotropically etched patterned dielectric (25) as a mask, anisotropically etching at least said tungsten silicide layer, and said polysilicon layer to form a gate stack (27).

Inventors: LEE KUO-HUA, YU CHEN-HUA DOUGLAS, LEE, KUO-HUA, YU, CHEN-HUA DOUGLAS
Applicants: AT & T CORP, AT&T CORP.
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L29