Novel TiSi2/TiN clad interconnect technology

Abstract: A TiSi₂/TiN clad LI strap process and structure are disclosed which combine the advantages of both TiSi₂ and TiN LI processes. According to the invention, the retention of a thin TiN layer (12) between the local interconnect (e.g. TiSi₂ 14) and contacts (e.g. TiSi₂ 16) provides a diffusion barrier against counterdoping and relaxes the thermal budget for subsequent processing.

Description: BACKGROUND OF THE INVENTION The use of local interconnect (LI) for connecting poly gates and emitters to diffusion areas and for connecting N + and P + across field oxide regions allow an increased packing density for submicron VLSI circuits and a reduction in parasitic junction capacitance. See Titanium Nitride Local Interconnect Technology for VLSI by T. Tang, C.C. Wei, R.A. Haken, T.C. Holloway, L.R. Hite and T.G.W. Blake, IEEE Trans. Electron Devices, Vol. ED-34, 3 (1987) p. 682. TiN has been used as an LI. However, TiN is very difficult to etch without damaging a silicide layer on a substrate. Both TiN and TiSi 2 LI structures have been developed which are compatible with a self-aligned silicide, or salicide, process. See HPSAC-Silicided Amorphous Silicon Contact and Interconnect for VLSI by D.C. Chen, S. Wong, P.V. Voorde, P. Merchant, T.R. Cass, J. Amano, and K.Y. Chiu, IEDM Tech. Dig., (1984) p. 118 and New Device Interconnect Scheme for Submicron VLSI by S. Wong, D. Chen, P. Merchant, T. Cass, J. Amano, and K.Y. Chiu, IEEE Trans. Electron Devices, Vol. ED-34, 3 (1987) p. 587. The original process for TiSi 2 LI begins with deposition of an amorphous silicon layer onto titanium. The Si layer is photographically defined and etched. Annealing in N 2 causes the remaining Si to react with the underlying Ti to form TiSi 2 , while exposed Ti regions react with the ambient N 2 to form TiN. The TiN is then selectively removed with an H 2 SO 4 + H 2 O 2 solution. In the original process, both contacts and LI are formed simultaneously. Because a high selectively to Ti as between Ti and Si can be achieved by dry etching in a fluorine-based chemistry, this process has an etch advantage over the standard TiN LI process, which exhibits less selectively to the salicided substrate. However, there are two major disadvantages of this process: namely, thermal diffusion of substrate Si into the overlying titanium layer can lead to pitting of the substrate, and counterdoping between P + and N + regions may occur through the LI strap during both silicide formation and subsequent high temperature processing since phosphorous diffuses rapidly in TiSi 2 . The method according to the present invention was developed to overcome these problems. EP-A-0 517 368 discloses a method of forming a local interconnect (LI) for integrated circuits and a LI structure formed as a result of said method, with said method comprising depositing a refractory metal layer such as titanium over the integrated circuit including silicon, depositing a barrier layer such as titanium nitride over the refractory metal layer, depositing a refractory metal silicide layer such as tantalum silicide over said barrier layer and, finally, providing a photoresist layer over said integrated circuit, patterning and developing said photoresist layer. The metal layer will be partially or totally consumed to form a silicide in the source/drain region during subsequent steps. The barrier layer is said to prevent dopant interdiffusion between the connected active areas while the refractory metal silicide layer protects the barrier layer from oxidizing and provides low resistance for increased device performance. SUMMARY OF THE INVENTION The present invention provides a process for forming a local interconnect comprising the features as claimed in claim 1. A local interconnect (LI) technology forming a clad TiSi 2 TiN structure has been developed for submicrometer VLSI devices. TiSi 2 interconnect straps are formed by reaction of a silicon-on-titanium bilayer. A thin TiN layer between the silicide strap and previously salicided regions provides an effective diffusion barrier against counterdoping and substrate silicon outdiffusion. The excellent dry etch selectivity between Si and Ti simplifies the LI patterning process. The LI structure offers improved electrical performance over the standard TiN LI because of its lower electrical resistance. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 4 illustrate cross-sectional drawings of the in-process formation of the local interconnect according to the invention. Figure 5 illustrates a SEM cross-section of a TiSi 2 /TiN clad LI. DETAILED DESCRIPTION OF THE INVENTION The invention provides a novel TiSi 2 /TiN clad local interconnect technology which employs a double Ti deposition sequence. With reference to figure 1 which illustrates a cross-section drawing of the in-process formation of the local interconnect, a diffusion region 4 is formed in silicon substrate 2. A thin oxide is grown over substrate 2 and polysilicon is deposited overall. The polysilicon is patterned and etched along with the oxide to form gate oxide 6 and poly gate 8 as shown. Next, sidewall oxide 10 for the gates are formed by depositing a thick oxide region overall and anisotropically etching the oxide away to leave sidewall filaments. Ti is then deposited overall. Like the original TiSi 2 LI process, an anneal is performed in ambient N 2 which leads to silicidation of the silicon and titanium at the silicon/titanium interfaces and leads to a first barrier metal region or layer of TiN being formed at the surface of the exposed Ti. With reference to figure 2 which illustrates a cross-sectional view of the in-process formation of the local interconnect, a second layer of titanium is deposited overall followed by the deposition of an amorphous silicon layer (α-Si), resulting in a Si-Ti bilayer. The amorphous silicon layer is then patterned and dry etched using a fluorine-based chemistry. With reference to figure 3 which illustrates a cross-sectional view of local interconnect undergoing further processing, annealing the structure undergoing processing in N 2 leads to silicidation of the Si/Ti regions while the exposed Ti forms TiN. The resulting interconnect strap geometry results in a thin TiN barrier layer 12 under a conducting TiSi 2 strap 14. With reference to figure 4 which illustrates a cross-sectional view of the in-process formation of the local interconnect, the unprotected region of TiN are subsequently removed by a wet strip. As shown in the SEM picture of a cross-section of the TiSi 2 /TiN clad LI of figure 5, no undercutting of the TiN layer is observed after the wet strip process. In fact, as shown in both figures 4 and 5, the TiN layer extends slightly beyond the overlying TiSi 2 layer. While the exact mechanism for this phenomenon has not been identified, it is believed to result from impurity diffusion from the Si/Ti bilayer into the underlying TiN film during silicidation. The diffusion of impurities may chemically modify the TiN layer such that it resists dissolution during the TiN wet strip process. The excellent adhesion between the upper level TiSi 2 and the TiN layer may also provide enhanced resistance to undercutting. Following the wet strip process, a high temperature anneal is performed to reduce the TiSi 2 and TiN sheet resistivities. In the original TiSi 2 LI process, the Si/Ti reaction occurs on both Si and SiO 2 substrates; since Ti will react more with Si than with SiO 2 . it is difficult to optimize the Si/Ti ratio. In the invention's TiSi 2 /TiN process, the Ti reaction with the substrate is prevented by the TiN barrier layer, thus Si/Ti ratio is determined by the thickness of Si and Ti within the bilayer. Prior art TiN LI's are fabricated from a TiN layer formed during salicidation. A two step wet/dry process is used to pattern the TiN LI. Although this process does not require any deposition steps other that the first Ti layer, the dry etching of TiN has poor selectivity to the substrate. In the invention's TiSi 2 /TiN process, not only is the excellent dry etch selectivity of the original TiSi 2 process retained, but there is minimal loss of substrate from the wet etch. Because the salicided contacts are not degraded during the wet etch process, excellent contact resistance results can be achieved. The clad TiSi 2 layer can be regarded as an electrically conductive hard mask for the wet TiN strip process. A comparison of typical parametric data for both TiSi 2 /TiN clad LI and TiN LI is shown in table 1. Fifty test structures were subjected to measurement and average values are indicated in table 1. Note that throughout table 1, the standard deviation (sig., short for sigma) of each set of fifty measurements is indicated within parentheses. As shown in table 1, 3000 Ll's were constructed (referred to as an LI chain) and the ohms per strap were measured for both the TiN LI strap and the TiSi 2 /TiN LI strap formed by the invention. Significantly lower resistances were measured for the Lis formed by the present invention regardless of whether these straps were constructed over N + doped diffusions (N + chain), P+ doped diffusions (P+ chain) or over two poly regions (PLY chain). LI serving as resistors can be distinguished generally by their relatively long length in comparison with non-resistor LIs. Ohms per square measurements are indicated in table 1 for LI resistors measuring 150 µm by 0.8 µm and for LI resistors measuring 150 µm by 1.2 µm. Note that a topography resistor can be constructed according to the invention by placing an LI resistor strap over a composite comprising poly moat, sidewall oxide and the like. Measurements for LI topography resistors measuring 150 µm by 0.8 µm are indicated in table 1. PARAMETRIC COMPARISON OF TiN AND TiSi 2 /TiN LI Parameter TiN LI (sig.) TiSi 2 /TiN LI Units 3000 LI-N + Chain 107.8 (8.6) 25.5 (1.7) ohm/strap 3000 LI-P + Chain 84.0 (6.3) 21.4 (1.3) ohm/strap 3000 LI-PLY Chain 126.6 (12.0) 39.8 (3.1) ohm/strap 150µm x 0.8µm Li Resistor 17.9 (1.6) 2.2 (0.2) ohm/square 150µm x 1.2µm Li Resistor 14.5 (1.1) 1.8 (0.1) ohm/square 150µm x 0.8µm LI topo Resistor 32.6 (4.2 10.5 (0.9) ohm/square The invention's TiSi 2 /TiN clad process combines the advantages of both the TiSi 2 and the TiN LI processes. The large dry etch selectivity between Si and Ti for the TiSi 2 process is retained. The retention of a thin TiN layer between the interconnect and the contacts provides a diffusion barrier against counterdoping of phosphorous, which relaxes the thermal budget (thermal budget being a function of temperature multiplied by time) for subsequent processing (i.e., the invention allows higher temperature processing over longer times). The clad TiSi 2 layer can be regarded as an electrically conductive hard mask for a wet TiN strip process. Improved electrical characteristics result from the intrinsically lower resistivity of TiSi 2 as compared to TiN.

Claims: A process for forming a local interconnect interconnecting source/drain (4) and gate (8) regions comprising: depositing a first titanium layer over a semiconductor body having a plurality of source/drain regions and a plurality of gate regions and including silicon, the first titanium layer contacting said source/drain and gate region; annealing the structure thus formed by the foregoing process step in N 2 so as to form a plurality of titanium silicide regions (3,5) distinct from each other at the contacted surfaces of said plurality of source/drain regions and said plurality of gate regions and to form a titanium nitride barrier layer overlying and connecting said titanium silicide regions; depositing a second titanium layer on said titanium nitride barrier layer; depositing silicon on said second titanium layer deposited on said titanium nitride barrier layer; patterning and etching said silicon, leaving said silicon only where said local interconnect is desired; annealing the structure thus formed by the foregoing process steps in N 2 so as to convert said second titanium layer under said silicon to a titanium silicide layer (14) and convert said second titanium layer elsewhere to a titanium nitride (12); and substantially wet etching away exposed regions of said titanium nitride barrier layer and said titanium nitride (12) but not said titanium silicide layer (14), wherein a portion of said titanium nitride barrier layer that extends beyond said titanium silicide layer (14) remains, and wherein the titanium silicide region at the contacted surfaces of said plurality of source/drain regions and the titanium silicide region at the contacted surfaces of said plurality of gate regions extend beyond the remaining portions of said titanium nitride barrier layer.

Inventors: JENG SHIN-PUU, JENG,SHIN-PUU
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1994
Main classification: H01L23
IPC codes: H01L23, H01L27, H01L21