Television circuit utilizing color burst signal

Abstract: A television circuit (1⊘) according to the invention includes a multiplier (12), and a voltage signal (V1) is outputted from an LPF (22) in accordance with the presence or absence of a color burst signal which is to be inputted to the multiplier (12). A rectangular-wave signal (Va) is obtained on the basis of the voltage signal (V1) through a peak holding circuit (24) and a sampling/holding circuit (42). A rectangular-wave signal (Vc) is obtained by averaging the rectangular-wave signal (Va) and a rectangular-wave signal (Vb) which is obtained by delaying the signal (Va) by a 1H delay circuit (44) by an adder (46) and a 1/2 multiplication circuit (48). On the basis of the rectangular-wave signal (Vc), a voltage signal (V3) is produced by an LPF (52) having a relatively small time constant, which is compared with a reference voltage (Vref) by a level-comparator (54), whereby a signal is outputted. The signal is used as a color killer signal for a color killer circuit, for example.

Description: BACKGROUND OF THE INVENTION Field of the invention The present invention relates to a television circuit utilizing a color burst signal. More specifically, the present invention relates to a television circuit which utilizes a color burst signal and is used in a color killer circuit, an ACC circuit, an APC circuit, and a color reproducing circuit or a television receiver which is provided with the circuits therein. Description of the prior art With referring to Figure 2⊘, in a conventional color killer circuit 1, a color burst signal and a sub-carrier signal are inputted to a multiplier 2, whereby an output according to the presence or absence of the color burst signal is applied to an LPF 3, and thus, a voltage signal V1 as shown in Figure 21(A) is outputted for each horizontal line from the LPF 3. In addition, although such a voltage signal V1 has a time width, in Figure 21(A), the same is illustrated as a line to simplify the illustration. This is also applied to Figure 6(A) and Figure 14(A). A peak hold signal V2 shown in Figure 21(B) is outputted from a peak holding circuit 4 to which the voltage signal V1 is applied, and a voltage signal V3 as shown in Figure 21(C) is outputted from an LPF 5, whereby a color killer signal as shown in Figure 21(D) can be outputted from a level-comparator 6. That is, in receiving a color television signal, the color killer signal of the high level is outputted, thereby not to perform a color killer operation, and in receiving a monochrome television signal, the color killer signal of the low level is outputted, thereby to perform the color killer operation. In such a conventional color killer circuit 1, if a time constant of the LPF 5 is made small, there occurs an erroneous operation as follows: In a case where the voltage signal V1 is largely affected by a noise as shown in a period X in Figure 21(A), the voltage signal V3 is also largely affected by the noise, and therefore, there occurs a period (a) (Figure 21(C)) during which the voltage signal V3 becomes smaller than a reference voltage Vref in spite of a color television signal. Therefore, due to the influence of the noise, the color killer signal of the low level is outputted as shown in Figure 21(D), and the color killer operation is erroneously performed. On the other hand, if the time constant of the LPF 5 is made be large, since the peak hold signal V2 is more smoothed, and therefore, the voltage signal V3 is not made be small to a level that is lower than the reference voltage Vref; however, in a case where the television signal being received is changed from a color television signal to a monochrome television signal or vice versa, it takes a long time to switch the color killer signal, and therefore, there was a problem that it is impossible to rapidly respond to the change of the television signal. IEEE Transactions on Broadcasting, Vol. 38, No. 1, March 1992, New York, pages 19-26, Douglas W. Irwin et al.: "Hybrid Clamping in NTSC Digital Video Equipment" discloses an apparatus which forms the average of two samples of the burst signal from adjacent lines. The signals are normally antiphase, and their average thus is representative of the clamping level. In the presence of phase errors, the average is sent as an error voltage to the clamper. SUMMARY OF THE INVENTION Therefore, a principal object of the present invention is to provide a television circuit utilizing color burst signal capable of operating with no erroneous operation. Another object of the present invention is to provide a television receiver including a color killer circuit capable of rapidly responding to the change of the television signal, with no erroneous operation. Another object of the present invention is to provide a television receiver including an ACC circuit capable of performing a gain adjustment properly. Another object of the present invention is to provide a television receiver including an APC circuit capable of performing a phase adjustment properly. A television receiver according to the invention is defined in appended claim 1. In accordance with the present invention, since the, first voltage signal is averaged by the averaging means, it is possible to obtain a television circuit which is not affected by a noise, and thus is resistant to a noise. For example, if the circuit is utilized for a color killer circuit, the color killer circuit is resistant to a noise and with no erroneous operation, and the color killer circuit can rapidly respond to the change of the television signal between the color television signal and the monochrome television signal. Furthermore, even if there is a noise, the ACC circuit can adjust again properly, and the APC circuit can adjust a phase properly. Furthermore, the performance of a color reproducing circuit or a television receiver which is constructed by using such the color killer circuit, ACC circuit, APC circuit and etc. can be obtained. The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a color killer circuit according to one embodiment of the present invention; Figure 2 is a circuit diagram showing one example of a multiplier in Figure 1 embodiment; Figure 3 is a wave-form chart showing an operation of the multiplier shown in Figure 2; Figure 4 is a circuit diagram showing one example of a peak holding circuit; Figure 5 is a circuit diagram showing one example of a 1/2 multiplication circuit; Figure 6 is a wave-form chart showing an operation of Figure 1 embodiment; Figure 7 is a block diagram showing a color killer circuit according to another embodiment of the present invention; Figure 8 is a circuit diagram showing a circuit for performing a weighted mean, being used in Figure 7 embodiment; Figure 9 is a block diagram showing on example of a 1H delay circuit; Figure 1⊘ is a wave-form chart showing an operation of the 1H delay circuit; Figure 11 is a block diagram showing an ACC circuit according to another embodiment of the present invention; Figure 12 is a circuit diagram showing a full-wave rectifying circuit used in Figure 11 embodiment; Figure 13 is a wave-form chart showing operations of the full-wave rectifying circuit and an LPF; Figure 14 is a wave-form chart showing an operation of Figure 11 ACC circuit in a case where a signal which is applied to the same includes a noise; Figure 15 is a wave-form chart showing an operation of a prior art ACC circuit in a case where a signal which is applied to the same includes a noise; Figure 16 is a block diagram showing an APC circuit according to another embodiment of the present invention; Figure 17 is a circuit diagram showing one example of a 9⊘° phase-shifter used in Figure 16 embodiment; Figure 18 is a block diagram showing one example of a television receiver including the present invention; Figure 19 is a wave-form chart showing an operation of a transformer used in Figure 18 embodiment; Figure 2⊘ is a block diagram showing a color killer circuit of a prior art; and Figure 21 is a wave-form chart showing an operation of Figure 2⊘ prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figure 1, a color killer circuit 1⊘ of this embodiment shown includes a multiplier 12 to which a color burst signal and a sub-carrier signal f sc . In receiving a color television signal, the color burst signal is applied to the multiplier 12; however, in receiving a monochrome television signal, no color burst signal is applied to the multiplier 12. The color burst signal and the sub-carrier signal f sc are applied to the multiplier 12 in a manner that the both become in-phase or anti-phase, and an output from the multiplier 12 becomes to have a positive level in a case where the two inputs are anti-phase, or a negative level in a case of the two inputs are in-phase (see Figure 3). In the embodiment shown, the phases of the color burst signal and the sub-carrier signal which are to be inputted to the multiplier 12 in receiving the color television signal are locked in a manner that the both become to be anti-phase. Therefore, in receiving a color television signal, the output from the multiplier 12 becomes a positive level. The multiplier 12 and an LPF 22 are constructed as shown in Figure 2, and operate as shown in Figure 3. The multiplier 12 is enabled in response to a fact that a burst gate pulse (BGP) is applied to a transistor Q1 during a burst gate period, and in the burst gate period, the sub-carrier signal f sc in Figure 3(A) is inputted to input ends 14 and 16 shown in Figure 2, and a color burst signal as shown in Figure 3(B) is inputted to input ends 18 and 2⊘. In a case where the both signals are in-phase as shown in a period (1) of Figure 3, transistors Q2 and Q6 are turned-on during a positive period of the sub-carrier signal f sc , and transistors Q4 and Q7 are turned-on during a negative period thereof. Therefore, a voltage at an output end A pulsates toward a negative direction at every half period as shown in Figure 3(C), and a voltage at an output end B becomes zero as shown in Figure 3(D). Accordingly, a current I1 (i.e., I4) flowing in a transistor Q8 pulsates toward a positive direction as shown in Figure 3(E), and a current I2 flowing in a transistor Q9 becomes zero as shown in Figure 3(F). Therefore, a current I3 (= I2 - I4) flowing in the LPF 22 from the multiplier 12 pulsates toward a negative direction as shown in Figure 3(G). The current I3 is smoothed or integrated by the LPF 22 which includes a resistor R and a capacitor C, and therefore, the LPF 22 outputs a negative voltage signal V1 as shown in Figure 3(H) at a timing that the both signals are in-phase. In a case the both signals are anti-phase as shown in a period (2) of Figure 3, transistors Q5 and Q7 are turned-on during a positive period of the sub-carrier signal f sc , and transistors Q3 and Q6 are turned-on during a negative period of the sub-carrier signal. Therefore, a voltage at the output end A becomes zero as shown in Figure 3(C), and a voltage at the output end B pulsates toward a negative direction at every half period as shown in Figure 3(D). Accordingly, the current I1 (i.e., I4) flowing in the transistor Q8 becomes zero as shown in Figure 3(E), and the current flowing in the transistor Q9 pulsates toward a positive direction as shown in Figure 3(F). Therefore, the current I3 flowing into the LPF 22 from the multiplier 12 pulsates toward a positive direction as shown in Figure 3(G). The current I3 is smoothed or integrated by the LPF 22, and therefore, the LPF 22 outputs a positive voltage signal V1 as shown in Figure 3(H) at a timing that the both signals are anti-phase. In a case where the sub-carrier signal is delayed in phase with respect to the color burst signal by 9⊘ degrees as shown in a period (3) of Figure 3, the transistors Q2 and Q6 are turned-on in a front half of a front half period of the sub-carrier signal as shown in Figure 3(A), and the transistors Q4 and Q7 are turned-on in a rear half of the front half period of the sub-carrier signal. Therefore, a voltage at the output end A becomes a negative voltage in only the front halves of the respective half periods as shown in Figure 3(C), and a voltage at the output end B appears as a negative voltage in the rear halves of the respective half periods as shown in Figure 3(D). Accordingly, the current I1 (I4) flowing in the transistor Q8 flows toward a positive direction only the front halves of the respective half periods as shown in Figure 3(E), and the current I2 flowing in the transistor Q9 flows toward a positive direction in only the rear halves of the respective half periods as shown in Figure 3(F). Therefore, the current I3 flowing in the LPF 22 from the multiplier 12 becomes a sine-wave approximately as shown in Figure 3(G). Accordingly, the LPF 22 outputs a voltage signal V1 having a level of V R (V) approximately at a timing that the sub-carrier signal f sc is delayed in phase by 9⊘ degrees with respect to the color burst signal. In a case of a period (4) of Figure 3, the sub-carrier signal is inputted to the input ends 14 and 16 as shown in Figure 3(A); however, since no color burst signal is inputted to the input ends 18 and 2⊘, that is, a voltage at the input ends 18 and 2⊘ becomes zero as shown in Figure 3(B) voltages at output ends A and B becomes zero, respectively, as shown in Figure 3(C) and Figure 3(D). Therefore, as shown in Figure 3(E), Figure 3(F) and Figure 3(G), the currents I1 (I4), I2 and I3 also become zero. Therefore, the LPF 22 outputs a voltage signal of V R (V) as shown in Figure 3(H). Then, a case where the both signals are anti-phase as shown in the period (2) of Figure 3 corresponds to a state where a color television signal is received, and a case of the period (4) of Figure 3 corresponds to a state where a monochrome television signal is received. Therefore, the LPF 22 outputs a positive voltage signal V1 in receiving the color television signal, and a voltage signal V1 of zero in receiving the monochrome television signal. Thus, the voltage signal V1 outputted from the LPF 22 becomes to be different in accordance with a time that the color television signal is received or that the monochrome television signal is received. Then, the voltage signal V1 is applied to a peak holding circuit 24 which is constructed as shown in Figure 4. The peak holding circuit 24 shown in Figure 4 includes a differential pair 26 composed of transistors Q11 and Q12. Emitters of the transistors Q11 and Q12 are commonly connected to the ground via a constant current source 28 of a current 2I. The voltage signal V1 is inputted to a base of the transistor Q11 from an input terminal 3⊘, and a base of the transistor Q12 is connected to the ground through a series connection of a diode 32 and a constant current source 34 of a current I. Furthermore, a collector of a transistor Q3 is connected to the collector of the transistor Q11, and a base of a transistor Q14 is connected to a base of the transistor Q13, and the collector and the base of the transistor Q13 are connected to each other. That is, the transistors Q13 and Q14 constitute a current mirror circuit 36. A diode 38 is connected between a collector of the transistor Q14 and the base of the transistor Q12, and a base of a transistor Q15 is connected to the collector of the transistor Q14 and to an emitter of the transistor Q15, an emitter of a transistor Q16 having a collector which is connected to the ground is connected through a series connection of resistors R1 and R2. Furthermore, a base of the transistor Q16 is connected to a cathode of the diode 32, and a capacitor C1 having one end which is connected to the ground is connected to a connection point of the resistors R1 and R2, and a voltage at other end of the capacitor C1 is outputted as a peak hold signal V2 from an output terminal 4⊘. In addition, the emitters of the transistors Q13 and Q14 and the collectors of the transistors Q12 and Q15 are connected to a power source voltage Vcc, respectively. In the peak holding circuit 24 thus constructed, when the voltage signal V1 is inputted to the input terminal 3⊘, an output of the differential pair 26 is withdrawn via the transistors Q13, Q14 and Q15 and the resistor R1, whereby the capacitor C1 is charged by a charging current I1. Then, if it becomes a state where no voltage signal V1 is inputted to the input terminal 3⊘, the capacitor C1 is discharged, and therefore, a discharging current I2 flows. If a charging time constant τ 1 = R1·C1 is small and a discharging time constant τ 2 = R2·C1 is sufficiently larger than the charging time constant τ 1 , the voltage difference or potential difference of the capacitor C1 is outputted as the peak hold signal V2 from the output terminal 4⊘. The peak hold signal V2 from the peak holding circuit 24 is applied to a sampling/holding circuit 42 which samples and holds the peak hold signal V2 at a timing of a trailing edge, for example, of a burst gate pulse which is applied for each horizontal line. The sampling/holding circuit 42 thus holds a sampled value during one horizontal line period (1H) so as to produce a rectangular-wave signal Va. The rectangular-wave signal Va is applied to a 1H delay circuit 44 and an adder 46. The rectangular-wave signal Va becomes a rectangular-wave signal Vb by delaying by one horizontal line period (1H) by the 1H decay circuit 44 so as to be applied to the adder 46. The adder 46 applies a rectangular-wave signal (Va + Vb) obtained by adding the rectangular-wave signals Va and Vb to a 1/2 multiplication circuit 48. The 1/2 multiplication circuit 48 includes resistors R3 and R4 as shown in Figure 5, for example, and the rectangular-wave signal (Va + Vb) inputted from an input terminal 5⊘ is divided by the resistors R3 and R4, and therefore, a rectangular-wave signal Vc obtained by the 1/2 multiplication circuit 48. In addition, R3 = R4 . Furthermore, the rectangular-wave signal Vc is represented by the following equation (1). Vc = (1/2)·(Va + Vb) Thus, by performing an averaging of the rectangular-wave signals Va and Vb of adjacent horizontal lines through a simple mean method, the rectangular-wave signal Vc is obtained, and the same is applied to an LPF 52. A time constant of the LPF 52 is set to be relatively small. A voltage signal V3 which is obtained by smoothing the rectangular-wave signal Vc by the LPF 52 is inputted to a (+) input of a level-comparator 54, and a reference voltage Vref is applied to a (-) input of the level-comparator 54. Therefore, the level-comparator 54 outputs a color killer signal of the high level or the low level according to comparison of the voltage signal V3 and the reference voltage Vref. Thus, the television signal which is being received is determined according to whether or not the color burst signal is applied to the multiplier 12. Then, in receiving a color television signal, the color burst signal is applied to the multiplier 12, and therefore, the voltage signal V3 becomes larger than the reference voltage Vref (V3 > Vref), and therefore, the color killer signal of the high level is outputted from the level comparator 54, so that no color killer operation is performed. On the other hand, in receiving the monochrome television signal, no color burst signal is applied to the multiplier 12, and therefore, the voltage signal V3 becomes smaller than the reference voltage Vref (V3 < Vref), and therefore, the color killer signal of the low level is outputted from the level-comparator 54, so that a color killer operation is performed. That is, an operation of a bandpass amplifier 144 (Figure 18) can be controlled. In the following, an operation of the color killer circuit 1⊘ will be described with reference to Figure 6. Figure 6 shows a case where a color television signal includes a noise. In addition, in order to make the comparison with the prior art easily, the voltage signal V1 shown in Figure 6(A) is illustrated to be equal to the voltage signal V1 of the prior art shown in Figure 21(A). First, when the color burst signal and the sub-carrier signal f sc are inputted to the multiplier 12, the voltage signal V1 shown in Figure 6(A) is outputted from the LPF 22 on the basis of the output of the multiplier 12. Then, the peak hold signal V2 shown in Figure 6(B) is outputted from the peak holding circuit 24. The sampling/holding circuit 42 samples and holds the peak hold signal V2 at the timing of the trailing edge, for example, of the burst gate pulse which is applied for each horizontal line, and therefore, the rectangular-wave signal Va shown in Figure 6(C) is generated by the sampling/holding circuit 42. The rectangular-wave signal Vb is obtained by the 1H delay circuit 44, and the rectangular-waves Va and Vb are added to each other by the adder 46, and thereafter, the rectangular-wave signal Vc shown in Figure 6(E) is produced by the 1/2 multiplication circuit 48. The rectangular-wave signal Vc is smoothed by the LPF 52, and therefore, the voltage signal V3 shown in Figure 6(F) is obtained to be applied to the level-comparator 54. Since the rectangular-wave signal Vc is obtained by averaging the rectangular-wave signals Va and Vb, a sudden change in the rectangular-wave signal Va due to a noise can be absorbed, and therefore, the voltage signal V3 is not affected by the noise. In the level-comparator 54, the voltage signal V3 and the reference voltage Vref are compared with each other. As seen from Figure 6(F), even if a noise is included in the color television signal, the color killer signal of the high level can be normally outputted from the level-comparator 54, and therefore, no color killer operation is performed. More specifically, in the prior art, if there is the period X in which the influence due to the noise is large, the color killer signal of the low level is erroneously outputted from the level-comparator 6, and therefore, a color killer operation is erroneously performed. However, in accordance with the color killer circuit 1⊘ of this embodiment shown, even if there is the period X (shown in Figure 6(A)) in which the influence due to the noise is large, the voltage signal V3 does not become smaller than the reference voltage Vref, and therefore, the color killer signal of the high level is continuously outputted from the level-comparator 54, and therefore, the color killer operation can be prevented from being erroneously performed. Furthermore, since it is possible to set the time constant of the LPF 52 to be relatively small, even if the television signal being received is changed from the color television signal to the monochrome television signal or vice versa, it is possible to rapidly change the level of the color killer signal from the color killer circuit 1⊘, and therefore, it is possible to rapidly respond to the change of the television signal which is being received. According to the embodiment shown, since the peak hold signal V2 is sampled and held and averaged, even if the time constant of the LPF 52 which is the smoothing means is set to be relatively small, the voltage signal V3 from the LPF 52 is hardly effected by the influence due to the noise, and therefore, it is possible to obtain a color killer circuit which is resistant to a noise. At the same time, since the time constant of the LPF 52 may be set to be relatively small, it is possible to rapidly respond to the change of the television signal between the color television signal and the monochrome television signal. With reference to Figure 7, in a color killer circuit 1⊘ of another embodiment according to the present invention, the rectangular-wave signal from the sampling/holding circuit 42 is subjected to a weighted mean method, and an averaged output is applied to the LPF 52. Therefore, instead of the 1H delay circuit 44, the adder 46 and the 1/2 multiplication circuit 48 of the color killer circuit 1⊘ shown in Figure 1, a 1H delay circuit 44, a (1 - K) multiplication circuit 56, an adder 58 and a K multiplication circuit 6⊘ are utilized in this embodiment shown. Circuits for constituting the (1-K) multiplication circuit 56, the adder 58 and the K multiplication circuit 6⊘ are constructed as shown in Figure 8. A circuit shown in Figure 8 includes a differential pair 62 composed of transistors Q21 and Q22 and a differential pair 64 composed of transistors Q23 and Q24. Bases of the transistors Q22 and Q23 are connected to each other, and a dc voltage 66 is applied to a connection point thereof. The rectangular-wave signal Va from the sampling/holding circuit 42 is applied to an input end 68 which is connected to the base of the transistor Q21, and the rectangular-wave signal Vb from the 1H delay circuit 44 is applied to an input end 7⊘ which is connected to the base of the transistor Q24. Then, emitters of the transistors Q21 and Q22 are connected to each other via a resistor R5, and emitters of the transistors Q23 and Q24 are connected to each other through a resistor R6, and emitters of the transistors Q21, Q22, Q23 and Q24 are connected to the ground through constant current sources 72, 74, 76 and 78, respectively. Furthermore, collectors of the transistors Q22 and Q23 are connected to each other, and from a connection point thereof, a rectangular-wave signal Vc which is obtained by averaging the rectangular-wave signals Va and Vb through a waited mean method can be withdrawn. In addition, collectors of the transistors Q21-Q24 are commonly connected to the power source voltage Vcc via a resistor R7. In the circuit constructed in the above described manner, on the assumption that R7/R5 = 1 - K , and R7/R6 = K , the rectangular-wave signal Vc can be represented by the following equation (2). Vc = (R7/R5)Va + (R7/R6)Vb = (1-K)Va + KVb As shown by the above described equation (2), the rectangular-wave signal Vc which is obtained by averaging the rectangular-wave signals Va and Vb by a weighted mean method can be obtained. Thus, by averaging the rectangular-wave signals of many horizontal lines through a weighted mean method, it is possible to further reduce the influence of noise. In addition, the 1H delay circuit 44 utilized in the above described embodiments may be constructed by a CCD element, but preferably constructed as shown in Figure 9. The 1H delay circuit 44 shown in Figure 9 includes two sampling/holding circuits 8⊘ and 82, and a multiplexer 84 which selects any one of the sampling/holding circuits 8⊘ and 82. A control pulse CNT3 which has a rectangular-wave form and is obtained by 1/2 frequency dividing the burst gate pulse by a frequency divider 86 is applied to the multiplexer 84, whereby a selection operation of the multiplexer 84 can be controlled. Furthermore, to the sampling/holding circuits 8⊘ and 82, control pulses CNT1 and CNT2 which are in synchronization with the burst gate pulse, respectively are applied at every two horizontal lines. An operation of the 1H delay circuit 44 will be described with reference to Figure 1⊘. A rectangular-wave signal e 1 is applied to the sampling/holding circuits 8⊘ and 82, respectively from an input end 88. The control pulses CNT1 and CNT2 shown in Figure 1⊘(F) and Figure 1⊘(G) are respectively applied to the sampling/holding circuits 8⊘ and 82 which respectively output rectangular-wave signals e 2 and e 3 shown in Figure 1⊘(B) and Figure 1⊘(C) in response to the control pulses CNT1 and CNT2. Then, the control pulse CNT3 shown in Figure 1⊘(H) is applied to the multiplexer 84. The selection operation of the multiplexer 84 is controlled by the control pulse CNT3, so that the multiplexer 84 selects the rectangular-wave signals e 3 and e 2 at every two horizontal lines, and therefore, a rectangular-wave signal e 4 shown in Figure 1⊘(D) is outputted from an output end 9⊘. It will be understood through the comparison of the rectangular-wave signals e 1 and e 4 shown in Figure 1⊘(A) and Figure 1⊘(D) that the rectangular-wave signal e 4 is delayed by one horizontal line period (1H) with respect to the rectangular-wave signal e 1 . Next, an ACC circuit 1⊘⊘ of a preferred embodiment of the present invention is shown in Figure 11. The ACC circuit 1⊘⊘ is a circuit for adjusting a gain of an AGC amplifier 1⊘2 in response to an amplitude of a color burst signal from the AGC amplifier 1⊘2 which is included in the bandpass amplifier 144 (Figure 8). In addition, in the AGC amplifier 1⊘2, the larger gain adjustment signal V9, the higher gain. To the AGC amplifier 1⊘2, a color signal which includes a carrier color signal and the color burst signal is applied, and the AGC circuit 1⊘⊘ includes a full-wave rectifying circuit 1⊘4 for full-wave rectifying the color burst signal. The full-wave rectifying circuit 1⊘4 is constructed as shown in Figure 12, for example. The full-wave rectifying circuit 1⊘4 includes a differential pair 1⊘6 composed of transistors Q31 and Q32. Emitters of the transistors Q31 and Q32 are connected to each other through resistors R13 and R14, and connected to the ground through a constant current source 1⊘8. The color burst signal from an input terminal 11⊘ is applied to a base of the transistor Q31, and a direct current power source voltage V B is applied to a base of the transistor Q32. Collectors of the transistors Q31 and Q32 are connected to a power source voltage Vcc through resistors R11 and R12, respectively. Furthermore, collector outputs of the transistors Q31 and Q32 are connected to bases of transistors Q33 and Q34, respectively. Collectors of the transistors Q33 and Q34 are connected to the power source voltage Vcc, and emitters of the transistors Q33 and Q34 are connected to each other, and an emitter output therefrom is applied to an LPF 23 which includes a resistor R and a capacitor C, for example, as a rectified voltage signal V4. Then, a voltage signal V5 is obtained. In addition, the emitters of the transistors Q33 and Q34 are connected to the ground through a constant current source 112. In the color burst period, the full-wave rectifying circuit 1⊘4 operates as shown in Figure 13. When the color burst signal shown in Figure 13(A) is applied to the transistor Q31 from the input terminal 11⊘, an output according to a voltage differences between the color burst signal and the direct current voltage V B are outputted from the output ends C and D as shown in Figure 13(B) and Figure 13(C). That is, a positive voltage is outputted at the output end C during a positive period of the color burst signal, and a positive voltage is outputted at the output end D during a negative period of the color burst signal. Then, the output from the output end C is applied to the LPF 23 via the transistor Q34, and the output of the output end D is applied to the LPF 23 via the transistor Q33. Therefore, the rectified voltage signal V4 shown in Figure 13(D) is inputted to the LPF 23. In addition, the rectified voltage signal V4 is changed in accordance with a level or amplitude of the color burst signal. Then, the rectified voltage signal V4 is smoothed or integrated by the LPF 23, and therefore, the voltage signal V5 having a level according to the level of the burst color signal and being shown in Figure 13(E) is outputted to the sampling/holding circuit 42. As similar to the case of the color killer circuit 1⊘, the sampling/holding circuit 42 samples the voltage signal V5 shown in Figure 14(A) at a timing of the trailing edge of the burst gate pulse which is applied for each horizontal line, and holds a sampled value during one horizontal line period (1H) to produce a rectangular-wave signal V6 shown in Figure 14(B). The rectangular-wave signal V6 is applied to the 1H delay circuit 44 and the adder 46. The rectangular-wave signal V6 becomes a rectangular-wave signal V7 through the 1H delay circuit 44, which is applied to the adder 46. The adder 46 applies a rectangular-wave signal (V6 + V7) obtained by adding the rectangular-wave signals V6 and V7 to the 1/2 multiplication circuit 48. The 1/2 multiplication circuit 48 is constructed as shown in Figure 5, for example, and therefore, a rectangular-wave signal V8 through the 1/2 multiplication circuit 48 can be obtained. The rectangular-wave signal V8 is applied to the (-) input of the level-comparator 54 so as to be compared with the reference voltage Vref which is applied to the (+) input of the level-comparator 54. The level-comparator 54 outputs a signal of the high level or the low level through the comparison of the rectangular-wave signal V8 and the reference voltage Vref which determines an ACC level. More specifically, if the rectangular-wave signal V8 is larger than the reference voltage Vref, the level-comparator 54 outputs a signal of the low level, and therefore, the gain adjustment voltage signal V9 from an LPF 114 becomes small, and therefore, a gain of the AGC amplifier 1⊘2 becomes small. On the other hand, if the rectangular-wave signal V8 is smaller than the reference voltage Vref, the level-comparator 54 outputs a signal of the high level, and therefore, the gain adjustment signal V9 from the LPF 114 becomes larger and the gain of the AGC amplifier 1⊘2 becomes higher. In the ACC circuit 1⊘⊘ having the above described structure, by applying the rectangular-wave signal V8 which is obtained by averaging the rectangular-wave signals V6 and V7 to the level-comparator 54, the gain adjustment signal V9 from the LPF 114 becomes as shown in Figure 14(E). As seen from Figure 14(E), if there is a noise as shown in Figure 14(A), the gain adjustment signal V9 is hardly varied with respect to a control voltage level which is originally to be set for the AGC amplifier 1⊘2. On the other hand, ACC circuit of the prior art is constructed by deleting the 1H delay circuit 44, the adder 46 and the 1/2 multiplication circuit 48 from the ACC circuit 1⊘⊘ shown in Figure 11. Therefore, in the prior art ACC circuit, the rectangular-wave signal V6 from the sampling/holding circuit 46 is directly applied to the (-) input of the level-comparator 54 as shown in Figure 15(A), the gain adjustment signal V9 from the LPF 114 is largely affected by the noise as shown in Figure 15(B). As seen through the comparison of Figure 14(E) and Figure 15(B), in the ACC circuit 1⊘⊘ of this embodiment shown in Figure 11, even if a large noise is applied, the variation of the gain adjustment signal V9 becomes smaller than that of the prior art, and therefore, the influence of the noise can be reduced. That is, in the ACC circuit 1⊘⊘, even if a receiving condition is bad as such that an electric field is weak or that a noise is erroneously determined as the color burst signal, the gain of the AGC amplifier 1⊘2 can be stably adjusted, and therefore, it is possible to prevent an erroneous operation. Next, an APC circuit 12⊘ of a preferred embodiment of the present invention is shown in Figure 16. The APC circuit 12⊘ is a circuit for adjusting a frequency phase of an oscillation signal outputted from an oscillator 122 which is a VXO (voltage-controlled crystal oscillator), for example. The APC circuit 12⊘ includes a 9⊘° phase-shifter 124. The 9⊘° phase-shifter 124 delays the oscillation signal from the oscillator 122 by 9⊘ degrees so as to apply the same to the multiplier 12. The 9⊘° phase-shifter 124 is constructed as shown in Figure 17, for example. In the 9⊘° phase-shifter 124 shown in Figure 17, an input end 126a is connected to a base of a transistor Q42 of transistors Q41 and Q42 which are connected to each other in a differential manner, via a resistor R21. An input end 126b is connected to a (+) terminal of a constant voltage source 128 having a (-) terminal which is connected to the ground, and the input end 126b is further connected to a base of a transistor Q44 of transistors Q43 and Q44 which are connected to each other in a differential manner, via a resistor R22, and further to a base of the transistor Q41 via a resistor R23. Emitters of the transistors Q41 and Q42 are commonly connected to the ground via a series circuit of a transistor Q48 and a resistor R24. A collector of the transistor Q41 is directly connected to a voltage source Vcc, and a collector of the transistor Q42 is connected to the voltage source Vcc via a series circuit of a transistor Q46 and a resistor R25. A connection point of the collector of the transistor Q42 and a collector of the transistor Q46 is connected to a base of the transistor Q45 and a collector of the transistor Q43. A base of the transistor Q46 is connected to a base and a collector of a transistor Q47, and an emitter of the transistor Q47 is connected to the voltage source Vcc via a resistor R26. These transistors Q46 and Q47 constitute a current mirror circuit. The collector of the transistor Q47 is connected to the ground via a series circuit of a transistor Q5⊘ and a resistor R27. The collector of the transistor Q45 is directly connected to the voltage source Vcc and an emitter thereof is connected to the ground through a series circuit of a transistor Q49 and a resistor R28. The base of the transistor Q42 is connected to the base of the transistor Q43 via a series circuit of a capacitor C3 and a resistor R29. A connection point of the capacitor C3 and the resistor R29 is connected to an output end 126c. An output end 126d is connected to the ground. A capacitor C4 is inserted between the base of the transistor Q43 and the base of the transistor Q44, and emitters thereof are commonly connected to the ground through a series circuit of a transistor Q51 and a resistor R3⊘. Bases of the transistors Q48, Q49, Q5⊘ and Q51 are commonly connected to a (+) terminal of a constant voltage source 13⊘ having a (-) terminal which is connected to the ground. That is, the 9⊘° phase-shifter 124 includes an alternating current negative feed-back amplifier 132 including the transistors Q41, Q42, Q45, Q46, Q47, Q48, Q49 and Q5⊘, and the resistor R21, the capacitor C3 and etc. which constitute a high-pass filter, and surrounded by a one-dotted line in Figure 17, and further having a direct current negative feed-back circuit 134 including the resistors R29 and R22 and the capacitor C4 which constitute a low-pass filter, and the transistors Q43 and Q44, and etc., and surrounded by a two-dotted line in Figure 17, the negative feed-back circuit 134 feeding a direct current voltage back to the negative feed-back amplifier 132. In addition, the transistors Q48, Q49, Q5⊘ and Q51 constitute a constant current source, and the resistors R24, R27 and R3⊘ have the same resistance value. Therefore, collector currents of the transistors Q48, Q5⊘ and Q51 are equal to each other, and therefore, if a current value of the collector current is 2Io, the collector current of the transistor Q46 becomes 2Io if the resistance values of the resistors R25 and R26 are the same resistance value because the transistors Q46 and Q47 constitute a current mirror circuit. Next, an operation in an alternating current of the 9⊘° phase-shifter 124 will be described. The base of the transistor Q41 is connected to the ground in an alternating current. The transistor Q46 functions as a load for withdrawing an output of the differential transistors Q41 and Q42 in a form of a current, and an alternating current load becomes a very large value, and therefore, an open loop gain A is sufficiently large. If the collector current of the transistor Q42 is changed, the base current of the transistor Q45 is also changed, whereby the output is withdrawn as a voltage by an emitter-follower of the transistor Q45. The output voltage e o outputted from the emitter-follower of the transistor Q45 is supplied to the high-pass filter composed of the capacitor C3 and the resistor R21. Therefore, the base voltage of the transistor Q42 is given by the following equation (3). ei = 1 jω C3·R21+1 + e ⊘ jω C3·R21 jω C3·R21+1 Then, the base voltage of the transistor Q41 is connected to the ground in an alternating current, the relationship between the input voltage e i and the output voltage e o is given by the following equation (4). e ⊘ = {⊘ - [e i 1 jω C3·R21+1 + e ⊘ jω C3·R21 jω C3·R21+1 ]}A Then, since the open loop gain A is sufficiently large, the equation (4) can be modified as the following equation (5), and therefore, it will be understood that a phase-shifting amount becomes 9⊘ degrees. -e i = e o [ 1 A + jωC3·R21] -e i ≒ e o jωC3 + R21 Next, an operation in a direct current will be described. The negative feeding-back in an alternating current is performed in the negative feed-back amplifier 132, but no direct current component is fed-back due to the capacitor C3. Therefore, the emitter voltage of the transistor Q45 becomes unstable, and therefore, the negative feed-back amplifier 132 does not operate. However, only a direct current component of the voltage outputted from the emitter-follower of the transistor Q45 is supplied to the low-pass filter of the resistors R29 and R22 and the capacitor C4, and to the base of the transistor Q43 of the transistors Q43 and Q44 which are connected to each other in a differential manner. A constant voltage is supplied to the base of the transistor Q44 from the constant voltage source 128, and therefore, if the base currents of the transistors Q43 and Q44 and a voltage drop due to the resistors R29 and R22 are ignored, a current division ratio of the collector current 2Io of the transistor Q51 is changed according to a difference of the both base voltages, and therefore, the collector current of the transistor Q43 is changed. A direct current voltage at the bases of the transistor Q41 and Q42 is kept at a voltage of the constant voltage source 128, and therefore, if the base current of the transistors Q41 and Q42 and a voltage drop due to the resistors R21 and R23 are ignored, the collector currents respectively flowing through the transistors Q41 and Q42 becomes Io which is a half of the collector current 2Io of the transistor Q48. Furthermore, since the collector current of the transistor Q46 becomes 2Io, if the base current of the transistor Q45 is small and can be ignored, the collector current of the transistor Q43 becomes Io that is obtained by subtracting the collector current of the transistor Q42 from the collector current of the transistor Q46. Then, a condition that the collector current of the transistor Q43 of the transistors Q43 and Q44 which are connected to each other in a differential manner becomes Io is that the base voltages of the transistors Q43 and Q44 must be equal to each other because the collector current of the transistor Q51 is 2Io, and therefore, since the direct current voltage of the emitter of the transistor Q45 is fixed at the voltage of the constant voltage source 128, and accordingly, the negative feedback amplifier 132 can normally operate with an operating point of the voltage. The oscillation signal from the oscillator 122 is delayed by 9⊘ degrees by such the 9⊘° phase-shifter 124 to be inputted to the multiplier 12 which performs a phase-comparison, and therefore, a delayed oscillation signal is compared in phase with the color burst signal. The multiplier 12 and the LPF 22 are constructed as shown in Figure 2, for example, and therefore, a voltage signal V1 is outputted from the LPF 22 in accordance with a phase difference between the both signals. More specifically, if the oscillation signal from the 9⊘° phase-shifter 124 which is inputted to the input ends 14 and 16 is delayed in phase by 9⊘ degrees with respect to the color burst signal which is inputted to the input ends 18 and 2⊘, a state shown in the period (3) of Figure 3 is obtained, and a state of the period (1) of Figure 3 is obtained in a case where the both signals are in-phase, and a state of the period (2) of Figure 3 is obtained in a case where the both signals are anti-phase. As similar to Figure 1 embodiment, the rectangular-wave signal Va is outputted from the sampling/holding circuit 42, which is added to the rectangular-wave signal Vb from the 1H delay circuit 44 by the adder 46, and thereafter, an added signal(Va + Vb) is made be 1/2 by the 1/2 multiplication circuit 48, so that the averaged rectangular-wave signal Vc is obtained. The rectangular-wave signal Vc is smoothed by an LPF 136 to be applied to the oscillator 122 as a phase adjustment signal V1⊘ by which a frequency and phase of the oscillation signal from the oscillator 122 can be controlled. Therefore, the APC circuit 12⊘ is locked such that the oscillation signal through the 9⊘° phase-shifter 124 becomes to have a delay phase of 9⊘ degrees with respect to the color burst signal. At that time, the oscillation signal and the color burst signal becomes to be in-phase. If the APC circuit 12⊘ is unlocked, the phase relationship of the both signals which are inputted to the multiplier 12 is changed within a range of ± 9⊘ degrees at a center of the phase relationship at a time that the APC circuit 12⊘ is locked. Then, the oscillation signal which is in synchronisation with the color burst signal is outputted from the APC circuit 12⊘. According to the APC circuit 12⊘, even if a receiving condition is bad, it is possible to stably adjust a phase of the oscillation signal from the oscillator 122. A television receiver 14⊘ which includes a the present invention is shown in Figure 18. In addition, in the following, the television receiver 14⊘ of the NTSC system will be described; however, it is needless to say that the present invention is applicable an arbitrary television system such as the PAL system, SECAM system and etc. The television receiver 14⊘ including the color reproducing circuit includes a transformer 142 which is a bandpass transformer of 3.58 MHz ± ⊘.5 MHz. Therefore, a signal of a frequency band of 3-4 MHz included in a composite video signal shown in Figure 19(A), that is, the carrier color signal and the color burst signal are outputted at a secondary side of the transformer 142. A direct current component included in the signal outputted from the transformer 142 is removed through a capacitor C5, becoming a wave-form as shown in Figure 19(B). The signal is separated into the carrier color signal and the color burst signal by the bandpass amplifier 144, and the color burst signal is amplified by a burst amplifier 146 to be applied to the color killer circuit 1⊘, the ACC circuit 1⊘⊘ and the APC circuit 12⊘. The color killer circuit 1⊘ controls an operation of the bandpass amplifier 144 in accordance with the presence or the absence of the color burst signal. That is, in a case where there is no color burst signal, the operation of the bandpass amplifier 144 is stopped because the monochrome television signal is received. On the other hand, in a case where there is the color burst signal, the bandpass amplifier 144 is operated because the color television signal is received. Furthermore, the ACC circuit 1⊘⊘ adjusts a gain of the bandpass amplifier 144 in accordance with an amplitude of the color burst signal. That is, if the amplitude of the color burst signal is large, the gain of the bandpass amplifier 144 is made be small, and if the amplitude of the color burst signal is small, the gain is made be large. Furthermore, the carrier color signal is applied to a color demodulation circuit 148 from the bandpass amplifier 144, and therefore, original color difference signals (R-Y, B-Y, and G-Y) can be withdrawn from the carrier color signal. At that time, it becomes necessary to obtain a carrier wave signal having a phase which is the same as that of the sub-carrier signal of 3.58 MHz and utilized for producing the carrier color signal at a transmitter side. Therefore, an oscillator 15⊘ outputs an oscillation signal of the 3.58 MHz. Then, a phase of the oscillation signal of the oscillator 15⊘ is made be coincident with the phase of the color burst signal of the 3.58 MHz by the APC circuit 12⊘. In addition, the oscillation signal from the oscillator 15⊘ is directly applied to the color demodulation circuit 148 and the oscillation signal is further applied to the color demodulation circuit 148 through a phase-shifter 152, and therefore, the color different signals (R-Y, B-Y, and G-Y) are withdrawn from the color demodulation circuit 148. It is to be noted that the circuits shown in Figure 1, Figure 11 and Figure 16 are utilized for the color killer circuit 1⊘, the ACC circuit 1⊘⊘ and the APC circuit 12⊘. By utilizing such circuits, it is possible to obtain the color reproducing circuit or the television receiver which is resistant to a noise. An averaging circuit which is shown in Figure 7 and includes the (1-K) multiplication circuit 56, the adder 58, the K multiplication circuit 6⊘ and the 1H delay circuit 44 may be utilized in the ACC circuit 1⊘⊘ shown in Figure 11 and the APC circuit 12⊘ shown in Figure 16. Furthermore, as the 1H delay circuit 44 of the ACC circuit 1⊘⊘ and/or the APC circuit 12⊘, a circuit shown in Figure 9 can be utilized. Moreover, it is needless to say that such the ACC circuit 1⊘⊘ and/or the APC circuit 12⊘ and the color killer circuit 1⊘ shown in Figure 7 may be utilized for the television receiver 14⊘ shown in Figure 18. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A television receiver which includes a color killer circuit (10), said color killer circuit comprising: first voltage outputting means (12, 22, 24, 42) for outputting a voltage (Va) related to the phase of a color burst signal; first delay means (44) for delaying said voltage by one horizontal line (1-H) period to output a delayed signal (Vb); first averaging means (46, 48; 56, 58, 60) which calculates an average of said voltage and said delayed signal and outputs a mean signal (Vc); and color killer signal outputting means (52, 54) for outputting a color killer signal in response to said mean signal. A television receiver according to claim 1, wherein said first averaging means includes a means (46, 48) for calculating non-weighted average to output said mean signal. A television receiver according to claim 1, wherein said first averaging means includes means (56, 58, 60) for calculating a weighted average to output said mean signal. A television receiver according to one of claims 1 to 3, wherein said first voltage outputting means outputs a rectangular-wave signal as said voltage signal. A television receiver according to claim 4, wherein said first voltage outputting means includes first means (12) which outputs a phase difference signal by comparing the phase of the color burst signal and the phase of the sub-carrier signal, first smoothing means (22) for smoothing the phase difference signal outputted from said first means to output a smoothed signal (V1), peak holding means (24) for holding a peak of said smoothed signal to output a peak-hold signal (V2), and first sampling/holding means (42) for sampling/holding said peak-hold signal in response to the burst gate pulse to output a rectangular-wave signal as said voltage (Va). A television receiver according to one of claims 1 - 5, wherein said color killer signal outputting means includes a second smoothing means (52) which receives said mean signal and outputs a smoothed signal (V3), and a voltage comparator (54) which compares said smoothed signal with a reference voltage (Vref) and outputs said color killer signal. A television receiver according to one of claims 1 - 6, further comprising an ACC (Automatic Chrominance Control) circuit (100) which controls a gain of an AGC amplifier (102) in accordance with an amplitude of the color burst signal, said ACC circuit including: second voltage outputting means (104, 23, 42) for outputting a voltage (V6) related to the amplitude of said color burst signal; second delay means (44) for delaying said voltage by one horizontal line (1-H) period to output a delayed signal (V7); second averaging means (46, 48) which calculates an average of said voltage and said delayed signal and outputs a mean signal (V8); and gain control signal outputting means (54, 114) for applying a gain control signal (V9) to said AGC amplifier in response to said mean signal. A television receiver according to claim 7, wherein said second voltage signal outputting means outputs a rectangular-wave signal as said voltage. A television receiver according to claim 8, wherein said second voltage signal outputting means includes second means (104) which outputs an amplitude signal (V4) by rectifying the color burst signal, third smoothing means (23) for smoothing the amplitude signal outputted from said second means to output a smoothed signal (V5), and second sampling/holding means (42) for sampling/holding said smoothed signal in response to the burst gate pulse to output a rectangular wave signal as said voltage (V6). A television receiver according to one of claims 7 - 9, wherein said gain control signal outputting means includes voltage comparator (54) which compares said mean signal (V8) with a reference voltage (Vref) and outputs a voltage-compared signal, and a fourth smoothing means (114) which receives said voltage-compared signal and outputs said gain control signal. A television receiver according to one of claims 1 - 10, further comprising an APC (Automatic Phase Control) circuit (120) which controls an oscillation phase of an oscillator (122) in accordance with a phase of the color burst signal, said APC circuit including: third voltage outputting means (124, 12, 22, 42) for outputting a voltage (Va) related to the phase of said color burst signal; third delay means (44) for delaying said voltage by one horizontal line (1-H) period to output a delayed signal (Vb); third averaging means (46, 48) which evaluates an average of said voltage and said delayed signal and outputs a mean signal (Vc); and oscillator control signal outputting means (136) for applying an oscillator control signal (V10) to said oscillator in response to said mean signal (Vc). A television receiver according to claim 11, wherein said third voltage signal outputting means outputs a rectangular-wave signal as said voltage. A television receiver according to claim 12, wherein said third voltage signal outputting means includes third means (124, 12) which outputs a phase difference signal by comparing the oscillation phase and the phase of the color burst signal, fourth smoothing means (22) for smoothing the phase difference signal outputted from said third means to output a smoothed signal (V1), and third sampling/holding means (42) for sampling/holding said smoothed signal in response to the burst gate pulse to output a rectangular-wave signal as said voltage (Va). A television receiver according to one of claims 11 - 13, wherein said oscillator control signal outputting means includes a fifth smoothing means (136) which receives said mean signal (Vc) and outputs said oscillator control signal (V10).

Inventors: HONDA FUMIAKI, HOSOYA NOBUKAZU, HONDA, FUMIAKI, HOSOYA, NOBUKAZU
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1994
Main classification: H04N9
IPC codes: H04N11, H04N9