Capacitance multiplier for the internal frequency compensation of switching regulator integrated circuits

Abstract: A monolithic switching regulator includes an operational amplifier which is provided with a small frequency compensation capacitor, which determines the amplifiers unity gain frequency. The non-inverting input is driven at a frequency that is below its unity gain frequency and presents a capacitance having a value of the order of nanofarads, which value would ordinarily require an excessive chip area if fabricated as an actual capacitor.

Description: This invention relates to switching voltage regulators constituted as integrated circuits. A capacitance multiplier circuit is known from EP-A-0,139,230 (Villinger) in which an operational amplifier connected as a voltage follower also has a complex impedance connected in series with the input. The overall capacitance of the circuit is much greater than the value of the capacitor used in the complex impedance. It is an object of the invention to incorporate the frequency compensation components of a switching regulator within the integrated circuit. It is a further or alternative object of the invention to create a virtual compensation capacitor in an integrated circuit in which a capacitance multiplier produces a large effective capacitance which can serve as a switching regulator frequency compensation element. The invention provides a capacitance multiplying circuit for use on an integrated circuit chip for providing a relatively large on-chip capacitance useful in loop frequency compensation functions, said circuit comprising an operational amplifier having inverting and non-inverting inputs, a single ended output and an open-loop unity gain at a particular frequency; a resistive connection between the inverting and non-inverting inputs; means for coupling the output of the operational amplifier to its inverting input; and means for driving the non-inverting input at a frequency that is below the said particular frequency whereby a relatively large equivalent shunt capacitance is present at the said non-inverting input. In a preferred embodiment, a switching regulator is operated at a relatively high switching frequency and incorporates an error amplifier that requires a relatively large compensation capacitor. An operational amplifier has its output connected to its inverting input and includes a first resistor connected across its input terminals. A second resistor couples the non-inverting input of the operational amplifier to the regulator's error amplifier output. The non-inverting input presents an equivalent capacitance inversely proportional to the value of the first resistor multiplied by unity gain frequency of the operational amplifier. This produces a substantial capacitance as an on-chip component and the second resistor provides a series resistor loop compensation component. The equivalent capacitor and the second resistor in series represent the frequency compensating element of the whole switching regulator. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram of one example of a known voltage boosting switching voltage regulator. Figure 2 is an equivalent circuit representation of the circuit of the invention. Figure 3 is a block diagram showing how the circuit of the invention is associated with a switching regulator amplifier. Figure 4 is a schematic diagram of the circuit of the invention. DESCRIPTION OF THE INVENTION Integrated circuit (IC) switching voltage regulators are popular because of their high performance, versatility and economy. The LM1577 is typical of such voltage regulators. It is designed to operate with a five-volt input and to switch at about 52 kHz. It has an adjustment capability which permits the user to control the output voltage. Figure 1 shows an application of the LM1577 which produces a 12 volt output at up to 800 milliamps. The circuit functions to maintain the 12 volt output independent of load and input voltage fluctuations. With reference to Figure 1, box 10 represents an LM1577. The numbers inside the box represent the pin numbers of a five-pin TO-220 IC package. A +5 volt input is applied to terminal 11 (pin 5) with ground return at terminal 12 (pin 3). A relatively low value (0.1 µf) capacitor 13 is connected to the input power line to provide input smoothing. An inductor 14, which has a typical value of about 100 micro-henries, is coupled between IC pins 5 and 4. A Schottky power diode 15 is coupled between inductor 14 and output terminal 16 at which the regulated output voltage will appear. A large-value filter capacitor (several hundred microfarads) 19 is coupled between output terminal 16 and ground. Resistors 17 and 18 act as a voltage divider across the regulated output at terminal 16 to produce a feedback signal that is applied to IC pin 2. Resistor 21 and capacitor 20 are coupled between IC pin 1 and ground to provide frequency compensation for the regulator. In operation, a switch within the regulator periodically switches pin 4 to ground. When the switch is closed the current flowing in inductor 14 will ramp up. When the switch opens the switch current will fall to zero and the inductor will generate an inductive voltage in a polarity that adds to the potential at terminal 11. Rectifier 15 will pass the inductive voltage to charge capacitor 19 to a level above that of terminal 5. The boosted voltage on capacitor 19 will be a function of the average voltage at pin 4. Therefore, the charge on capacitor 19 will be a function of the regulator's duty cycle. When the potential across capacitor 19 exceeds a value, which produces about 1.3 volts at pin 2, the regulator switch's pulse width is reduced. When resistor 18 is 2 kilohms and resistor 17 is 17.4 kilohms, a 12 volt output will be maintained at terminal 16. Thus, the feedback to pin 2 will control the switching pulse width, thereby regulating the output voltage even though the input voltage or the load connected to the regulator vary. Capacitor 20 is relatively large in terms of IC components. It will typically have a value of the order of nanofarads and must therefore be an off-chip component. It would be desirable to incorporate the regulator loop compensation elements in these and analogous circumstances entirely within the integrated circuit chip. Figure 2 illustrates by way of example a basic circuit conforming to the invention. Operational amplifier 22 has its output coupled back to its inverting input and a resistor 23 is connected between the inverting and non-inverting inputs. When such a circuit is driven at terminal 24 by a signal at a frequency that is operating on the -20 db per decade open loop gain slope, the operational amplifier presents an equivalent capacitance 20' at its non-inverting input. The capacitor 20' is shown in dashed outline because it is an effective capacitance, not an actual element. Capacitor 20' will have a value: C 20' = 0.159/(R 23 x F 0 ) where F 0 is the frequency at which open-loop unity gain occurs. Thus, the circuit of Figure 2 can easily simulate a capacitor having a value on the order of several nanofarads. Such a value would otherwise involve inordinate chip area if fabricated as an on-chip capacitance. Figure 3 shows how the circuit of Figure 2 is applied as part of the loop compensation in a switching regulator error amplifier 26. Error amplifier 26 represents the high gain transconductance amplifier which is part of a switching regulator such as element 10 of Figure 1. This amplifier is the circuit element that compares the feedback on pin 2 with an internal reference and drives the circuits that control the switch duty cycle. It is to be understood that amplifier 26 has an output at terminal 27 that can be frequency compensated, either by a discrete resistor and capacitor, or by the invention of utilizing an IC resistor and a relatively large equivalent capacitance. As described above, capacitance 20' is presented at terminal 24. This creates the nanofarad-sized capacitor 20 of Figure 1. Resistor 21 then completes the loop compensation circuit on the output of error amplifier 26. Since the circuit of the invention can be realized, using small area IC components, it is feasible to form the circuit of Figure 3 as an entirely on-chip structure. This removes the requirement of off-chip compensation components. Figure 4 is a schematic diagram showing how the amplifier 22, of Figure 3, can be implemented for an IC chip. This circuit constitutes the preferred embodiment of the invention. The heart of the circuit is a pair of PNP transistors 29 and 30 which respectively form the non-inverting and inverting inputs of the amplifier 22. NPN transistors 31 and 32 respectively form the input and output transistors of a conventional current mirror load for the differential input stage. The single ended output of the input stage appears at the collector of transistor 32 which is directly connected to the base of common emitter transistor amplifier 33. Transistor 35 acts an emitter follower isolating buffer which couples the collector of transistor 33 to the base of emitter follower output transistor 36. This isolation ensures very high voltage gain in transistor 33. The operational amplifier's own small frequency compensation capacitor 34 is connected between the base and collector of transistor 33. This capacitor is needed to ensure the amplifier's unity gain stability. Its typical value is about 20 pf. Resistors 37 and 38 act in series as the emitter load for output transistor 36. These resistors form a voltage divider so that node 39 forms the output of amplifier 22. This node is directly connected to the inverting input so that 100% negative feedback is present as shown in the block diagrams of Figures 2 and 3. Transistor 40 forms a plural output current source. Its emitter is returned to the +V CC rail by resistor 41. The base of transistor 40 is returned to a V BIAS terminal 42 which is operated at a potential that produces the desired current outputs. Transistor 40 is shown as a four collector device which is typically a lateral PNP transistor having four equal quadrant collectors. Typically, the value of V BIAS is selected to produce one microampere in each of the collectors. Thus, transistor 35 receives two microamperes, transistor 33 receives one microampere and the differential input stage operates at a tail current of one microampere. Example The circuit of Figure 4 was constructed in the form of monolithic silicon, planar and PN junction isolated integrated circuit components. The following values were employed: COMPONENT VALUE Resistor 21 7.5k ohms Resistor 23 300 ohms Resistor 37 6.2k ohms Resistor 38 22k ohms Capacitor 34 20pf The circuit was operated from a 2.5 volt supply and node 27 was at 0.8 volt. The V BIAS was set for one microampere in each of the transistor 40 collectors. The operational amplifier had an open-loop unity gain frequency of 100 kHz. When driven at 1 kHz, node 24 displayed an equivalent shunt capacitance 20' of about 5.3 nf. This, in combination with resistor 19, can provide an effective loop frequency compensation for IC switching regulators. The entire circuit dissipated less than 0.1 microwatt at a supply potential of 2.5 volts.

Claims: A capacitance multiplying circuit for use on an integrated circuit chip for providing a relatively large on-chip capacitance useful in loop frequency compensation functions, said circuit comprising: an operational amplifier (22) having inverting and non-inverting inputs, a single ended output and an open-loop unity gain at a particular frequency; a resistive connection (23) between the inverting and non-inverting inputs; means for coupling the output of the operational amplifier to its inverting input; and means for driving the non-inverting input (24) at a frequency that is below the said particular frequency (F 0 ) whereby a relatively large equivalent shunt capacitance is present at the said non-inverting input. A circuit according to claim 1 wherein the operational amplifier includes a small internal frequency compensation capacitor which determines said particular frequency. A circuit according to claim 2 wherein the said equivalent shunt capacitance is proportional to the reciprocal of said the resistance value of the said connection multiplied by said particular frequency. A circuit according to claim 2 wherein an input resistor (21) is coupled to said non-inverting input. A circuit according to any foregoing claim wherein the said output is directly connected to the inverting input.

Inventors: YAMATAKE MINEO, YAMATAKE, MINEO
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1994
Main classification: H03H11
IPC codes: H02M3, H03H11