Intelligent power device

Abstract: A semiconductor substrate (1) comprises a P-type silicon substrate (2) and an N-type epitaxial silicon layer (3) formed on the substrate (2). The N-type epitaxial silicon layer (3) is isolatedly separated into first and second N-type island regions (5, 6) by means of a P-type silicon region (4) which extends from the major surface (8) of the layer (3) to the substrate (2). A power-related element (7) is formed in the first N-type region (5). The current path (A) of the power-related element (7) extends in the first N-type island region (5) and in the substrate (2), i.e., reaches a deep portion of the substrate (1) from the major surface (8). The logic-related element (9) is formed in the second N-type island region (6). The current path (B) of the element (9) extends only in the second N-type island region (6), i.e., reaches a shallow portion of the substrate (1) from the major surface (8). A carrier-recombination-center layer (10) is formed in a deep portion of the substrate (1), and overlaps the current path (A) of the power-related element (7). The layer (10) does not influence the current path (B) of the logic-related element (9) which extends only in a shallow portion of the substrate (1).

Description: This invention relates to a semiconductor integrated circuit device in which elements having different switching speeds are integrated in a single chip. A discrete semiconductor device for high power, such as a power MOS transistor or an IGBT, employs a technique for controlling the life time of carriers so as to increase the switching speed. This technique is generally called "life time control". Specifically, the life time control is to form a multiplicity of recombination centers of carriers in a substrate by diffusing heavy metal into the substrate, thereby increasing the rate of extinction of excessive minority carriers and hence the switching speed of the device. A technique for controlling the life time of carriers are described, for example, in B. J. Baliga et al. IEEE Trans. Electron Devices, vol. ED-24, No. 6 pp. 685 (1977). Since this technique enables the recombination centers of carriers to be formed substantially uniform in the substrate, all elements can have short carrier life time. Although the life time control technique can increase the switching speed, it inevitably reduces the current capacity. This is because the rate of extinction of majority carriers is increased as a result of the forming of the recombination centers of carriers in the substrate. Further, damage (crystal defect) due to life time control reduces the current amplification factor of the device, or changes the threshold voltage of the device. Since, as described above, there is a trade-off relationship between the increase of switching speed and the security of current capacity, it is difficult for the conventional life time control technique to reconcile them. In the field of semiconductor integrated circuit devices, there is a tendency to try to integrate, in a single chip, an element for high power and an element constituting a circuit for driving or controlling the element for high power. Such an integrated circuit device is called an "IPD (Intelligent Power Device)", which is described, for example, in R. S. Wrathall et al. IEEE Power Electronics Specialists Conference, pp. 229-233 (1985) and Y. Ohata et al. IEEE Custom Integraed Circuit Conference, pp. 443-446 (1987). In the semiconductor integrated circuit device of this type, each chip has both an element for increasing the switching speed, i.e., a power-related element (or power system element), and an element from which the influence of the life time control should be prevented (i.e., an element whose current amplification factor and threshold voltage should be accurately adjusted), i.e., a logic-related element (or logic system element). FR-A-2 320 636 discloses semiconductor circuit devices using a carrier-recombination layer to decrease the gain of a parasitic transistor, and other semiconductor circuit devices having a irst semiconductor layer and a second semiconductor layer which are different in the type of conductivity; and a carrier-recombination layer formed in the second semiconductor layer. Even when assuming that those devices are allow an increase of the operation speed of the semiconductor device formed in the second semiconductor layer, they do not secure the current capacity of another device adjacent to the device of the second semiconductor layer. JP-A-1 010 658 shows a semiconductor device having first and second semiconductor layers different in the type of conductivity, and a carrier-recombination layer in the first semiconductor layer. In said device the carrier-recombination layer is formed to decrease the gain of a parasitic transistor, and the current path of the main element is not formed therein. Thus, this device intends to prevent the latch-up of a CMOS device, without improving the operation speed of the main element. Moreover, said document discloses a semiconductor element having a vertical structure, without including first and second semiconductor layers different in the conductivity type in the main portion of the semiconductor element. FR-A-2 138 275 teaches providing in a semiconductor device an isolation of elements using an isolation region, without disclosing a carrier-recombination layer. It is an object of the invention to provide a semiconductor integrated circuit device in which both a demand for an increase in the operational speed of an element, preferably in the increase of the switching speed of a power-related element, and a demand for reducing the influence of the life time control on another element, preferably of a logic-related element, are satisfied. This object is attained by a semiconductor integrated circuit device according to claim 1. Further improvements of the invention are specified in the sub-claims to claim 1. For attending the object of the invention, preferably there might be provided a semiconductor integrated circuit device comprising a semiconductor substrate, a first element formed in the semiconductor substrate and having a first current path in a deep portion of the semiconductor substrate, a second element formed in the semiconductor substrate separated from the first element and having a second current path in a shallow portion of the semiconductor substrate, and a carrier-recombination-center layer formed in a deep portion of the semiconductor substrate. As described above, the first element (power-related element) having its current path in a deep region and the second element (logic-related element) having its current path in a shallow region are employed in a single semiconductor substrate, and the carrier-recombination-center layer is formed in a deep region. This structure can satisfy a demand for an increase in the switching speed of the first element. Further, since the second element has its current path in a shallow region, current is prevented from flowing in the carrier-recombination-center layer, and hence a demand for reducing the influence of the life time control on the second element can be satisfied. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic cross sectional view, showing a semiconductor integrated circuit device according to a first embodiment of the invention; FIG. 2A is a cross sectional view, showing a double-diffusion MOSFET as an example of a preferred power-related element employed in the device of FIG. 1; FIG. 2B is a cross sectional view, showing a lateral IGBT as another example of the preferred power-related element employed in the device of FIG. 1; FIG. 2C is a cross sectional view, showing a diode as a further example of the preferred power-related element employed in the device of FIG. 1; FIG. 3A is a cross sectional view, showing a vertical NPN bipolar transistor as an example of a preferred logic-related element employed in the device of FIG. 1; FIG. 3B is a cross sectional view, showing a lateral NPN bipolar transistor as another example of the preferred logic-related element employed in the device of FIG. 1; FIG. 3C is a cross sectional view, showing a P-channel MOSFET as a further example of the preferred logic-related element employed in the device of FIG. 1; FIG. 3D is a cross sectional view, showing a N-channel MOSFET as a furthermore example of the preferred logic-related element employed in the device of FIG. 1; FIG. 4 is a cross sectional view, showing a specific example of the semiconductor integrated circuit device of FIG. 1; FIG. 5 is a schematic cross sectional view, showing a semiconductor integrated circuit device according to a second embodiment of the invention; FIG. 6 is a cross sectional view, showing a specific example of the semiconductor integrated circuit device of FIG. 5; FIG. 7 is a cross sectional view, showing another specific example of the semiconductor integrated circuit device of FIG. 5; and FIG. 8 is a cross sectional view, showing a further specific example of the semiconductor integrated circuit device of FIG. 5. FIG. 1 is a schematic cross sectional view, showing a semiconductor integrated circuit device according to a first embodiment of the invention. Specifically, FIG. 1 shows an IPD (Intelligent Power Device) in which an element for increasing the switching speed and another element for reducing the influence of the life time control are required to effectively operate at the same time. The IPD comprises two kind of elements incorporated in a single chip -- a first element (hereinafter referred to as a "power-related element") which is selected from the group of a power MOS transistor, an IGBT, a diode, etc., produced by discrete semiconductor devices in the prior art; a second element (hereinafter referred to as a "logic-related element") which forms a circuit for driving or controlling the first-mentioned element and is selected from the group of a MOSFET, a bipolar transistor, etc. In the IPD, in order to save power, the power-related element is required to perform switching at high speed. At the same time, in order to constitute a driving or control circuit, the logic-related element is required to have sufficient drivability or current capacity. As is shown in FIG. 1, a semiconductor substrate 1 includes a P-type silicon substrate 2, an N-type epitaxial silicon layer 3 formed on the substrate 2, and a P-type silicon region 4 extending from the major surface 8 of the N-type epitaxial silicon layer 3 to the substrate 2 and isolating N-type island regions 5 and 6 from each other. The N-type island region 5 has a power-related element 7 formed therein. The current path A of the power-related element 7 extends from within the region 5 into the substrate 2. As viewed from the major surface 8, the current path A reaches a deep portion of the substrate 1. Further, the N-type island region 6 has a logic-related element 9 formed therein. The current path B of the element 9 extends only in the N-type island region 6. In other words, the path B extends only in a shallow portion of the substrate 1, as viewed from the major surface 8. A carrier-recombination-center layer 10 is formed in a deep portion of the substrate 1, in which only the current path A of the power-related element 7 extends. In other words, the carrier-recombination-center layer 10 overlaps the current path A of the power-related element 7 and does not overlap the current B of the logic-related element 9. The layer 10 cannot be formed in such a position by metal diffusion or electron beam radiation, since these methods inevitably form carrier recombination centers in the overall substrate 1. To avoid this, the present invention employs a method for injecting relatively heavy particles (such as protons or helium nucleus) into the substrate 1. This method enables heavy particles to stop in a portion of the substrate 1 with a desired depth in accordance with the injecting energy. In the case of using protons, for example, they stop in a portion with a depth of about 45 µm from the surface of the substrate 1 if the injecting energy is 2 MeV. Further, in the case of using helium nucleus, they stop in a portion with a depth of about 40 µm from the surface of the substrate 1 if the injecting energy is 6 MeV. Crystal defects form in the vicinity of a region in which the heavy particles stop, and become recombination centers of carriers. Such crystal defects form a layer in the substrate 1 (in the substrate 2 in FIG. 1). This layer corresponds to the carrier-recombination-center layer 10. It is known that in the above-described method for injecting heavy particles, it is relatively difficult to form crystal defects in a region in which the particles pass. Accordingly, crystal defects can be formed in the substrate 2 by injecting heavy particles from the major surface 8 into the substrate 1. However, it is desirable to inject heavy particles from the reverse side 11 of the substrate 1 in order to avoid influence on the logic-related element 9. Specific examples of preferable power-related element 7 and logic-related element 9 will now be explained. FIGS. 2A - 2C show examples of the power-related element 7 employed in the device of FIG. 1. FIG. 2A is a cross sectional view of a lateral double-diffusion MOSFET (power MOS transistor), FIG. 2B is a cross sectional view of a lateral insulated-gate bipolar transistor (lateral IGBT), and FIG. 2C is a cross sectional view of a diode. Further, FIGS. 3A - 3D show examples of the logic-related element 9 employed in the device of FIG. 1. FIG. 3A is a cross sectional view of a vertical NPN bipolar transistor, FIG. 3B is a cross sectional view of a lateral PNP bipolar transistor, FIG. 3C is a cross sectional view of a P-channel MOSFET, and FIG. 3D is a cross sectional view of an N-channel MOSFET. First, the power MOS transistor as an example of the power-related element 7 will be explained. As is shown in FIG. 2A, a deep P + -type impurity diffusion layer 21 of high density which reaches the P-type silicon substrate 2 and a P + -type impurity diffusion layer 22 which contacts the layer 21 are formed in the N-type epitaxial silicon layer 3. An N + -type impurity diffusion layer 23 of high density, which serves as the source of the power MOS transistor, is formed in the layer 22. A gate insulating film is formed on the P + -type impurity diffusion layer 22 located between the N + -type impurity diffusion layer 23 and the N-type epitaxial silicon layer 3. A gate electrode (Gp) is formed on the gate insulating film. Moreover, a deep N + -type impurity diffusion layer 25 of high density which reaches the P-type silicon substrate 2 is formed in the N-type epitaxial silicon layer 3, separated from the diffusion layers 21, 22 and 23. An N + -type contact diffusion layer 26 of a density higher than the diffusion layer 25 is formed in the layer 25. An insulating film 27 such as a silicon oxide film (SiO 2 ) is formed on the N-type epitaxial silicon layer 3. A first contact hole is formed in the portion of the insulating film 27, which ranges from a portion of the diffusion layer 21 to a portion of the diffusion layer 23. An electrode wire 28 for a source (Sp) is electrically connected to the diffusion layers 21, 22 and 23 through the first contact hole. A second contact hole is formed in the portion of the insulating film 27 which is located on the contact diffusion layer 26. An electrode wire 29 for a drain (D P ) is electrically connected to the contact diffusion layer 26 through the second contact hole. The operation of the power MOS transistor constructed as above will now be explained. Where the power MOS transistor is in the On-state, the drain (D P ) is at high potential and the source (Sp) is at low potential. In this state, a potential of the gate electrode (G P ) is higher than the source potential, and a channel is formed in the P + -type impurity diffusion layer 22 located under the gate electrode (Gp). Accordingly, electrons e flow from the source (Sp) to the drain (D P ) via the channel. On the other hand, immediately after the power MOS transistor is switched from the On-state to the Off-state, a diode having its anode connected to the source (Sp) and its cathode connected to the drain (D P ) is turned on, since a feedback current flows, in particular, in the case of using an induction load such as a motor. In other words, current flows from the P + -type impurity diffusion layer 21 to the N + -type impurity diffusion layer 26 through the P-type silicon substrate 2 and the N + -type impurity diffusion layer 25. This diode is called a "recovery diode (FRD)". In the power MOS transistor, the FRD has a parasitic diode structure in which the P-type silicon substrate 2 and the P + -type impurity diffusion layers 21 and 22 serve as an anode, while the N + -type impurity diffusion layer 25 serves as a cathode. In the FRD of the parasitic diode structure shown in FIG. 2A, holes h serve as majority carriers. Electrons e as minority carriers flow from the N + -type impurity diffusion layer 25, etc. to the P-type silicon substrate 2. While the injected minority carriers (electrons e) exist, the diode is kept on. However, as is shown in FIG. 1, since the recombination center layer 10 is formed in the P-type silicon substrate 2 which serves as the current path of the FRD of the parasitic diode structure, the rate of extinction of the minority carriers (electrons e) is increased. As a result, the operational speed of the FRD is increased. In accordance with the increase in the operational speed of the FRD, the FRD can instantly be shifted from the On-state to the Off-state, thereby increasing the switching speed. At this time, as is shown in FIG. 1, the logic-related element 9 formed in the same substrate 1 as the power-related element 7 has its influence of the life time control should be prevented from being reduced, since the current path B does not extend in the recombination center layer 10. A lateral IGBT as another example of the power-related element 7 will be explained. As is shown in FIG. 2B, an N-type epitaxial silicon layer 3 has therein a deep and high density P + -type impurity diffusion layer 31 which reaches the P-type silicon substrate 2, and a P + -type impurity diffusion layer 32 which contacts the layer 31. A high density N + -type impurity diffusion layer 33 which functions as the source of the lateral IGBT is formed in the P + -type diffusion layer 32. A gate insulating film is formed on that portion of the layer 32 which is located between the N + -type impurity diffusion layer 33 and the N-type epitaxial silicon layer 3, and a gate electrode (G I ) is formed on the gate insulating film. A deep and high density N + -type diffusion layer 35 which reaches the P-type silicon substrate 2 is formed in the N-type epitaxial silicon layer 3, separated from the diffusion layers 31, 32 and 33. A high density N + -type impurity diffusion layer 36 which serves as the collector of the lateral IGBT is formed in the N + -type impurity diffusion layer 35. Further, an insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the N-type epitaxial silicon layer 3. A first contact hole is formed in that portion of the insulating film 27 which extends on part of the diffusion layers 31, 32 and 33. An emitter (E I ) electrode wire 38 is electrically connected to the diffusion layers 31, 32 and 33 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which extends on the N + -type diffusion layer 36. A collector (C I ) electrode wire 39 is electrically connected to the diffusion layer 36 through the second contact hole. The operation of the lateral IGBT constructed as above will be explained. Where the collector (C I ) is at high potential and the emitter (E I ) is at low potential, when a potential of the gate (G I ) is higher than the source, a channel is formed in that portion of the P + -type impurity diffusion layer 32 which is located under the gate (G I ). As a result, electrons e flow mainly toward the P + -type diffusion layer 35 through the channel. On the other hand, holes are injected into an N + -type impurity diffusion layer 35 on the side of the collector, since the collector side has a PN junction biased in a forward direction. A series of these phenomena causes the layer 35 to have a highly-injected state, thereby reducing the forward saturation voltage of the IGBT. The holes injected from the collector flow into the P + -type impurity diffusion layer 31 through the P-type silicon substrate 2. In the case of the IGBT shown in FIG. 2B, the holes h serve as majority carriers in the P + -type impurity diffusion layer 31. As in the above-described FRD of the parasitic diode structure, injection of electrons e as the minority carriers from the N + -type impurity diffusion layer 35, etc. to the P-type silicon substrate 2 occurs. The minority carriers (electrons e) reduce the operational speed of the IGBT. However, since in the IGBT, too, the carrier-recombination-center layer 10 is formed in the P-type silicon substrate 2 as shown in FIG. 1, the extinction rate of the minority carriers (electrons e) is increased and the operation speed of the IGBT is accordingly increased. In the IGBT, the influence of the life time control of the logic-related element, which is formed in the same substrate 1 as the IGBT (i.e., the power-related element 7), is prevented from being reduced, as in the power MOS transistor. A diode as a further example of the power-related element 7 will be explained. As is shown in FIG 2C, a deep and high density P + -type impurity diffusion layer 41 is formed in the N-type epitaxial silicon layer 3 such that it reaches the P-type silicon substrate 2. Further, a deep and high density N + -type impurity diffusion layer 45 is formed in the N-type epitaxial silicon layer 3 such that it reaches the P-type silicon substrate 2 and is separated from the diffusion layer 41. An insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the N-type epitaxial silicon layer 3. A first contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 41. An anode (A D ) electrode wire 48 is electrically connected to the diffusion layer 41 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 45. A cathode (K D ) electrode wire 49 is electrically connected to the diffusion layer 45 through the second contact hole. The operation of the above-described diode will be explained. Where the anode (A D ) is at a high potential and the cathode (K D ) is at a low potential, the P-type epitaxial silicon layer 2, the P + -type impurity diffusion layer 41 and the N + -type impurity diffusion layer 45 are biased in potential in a forward direction, with the result that current flows through the diffusion layer 41, the substrate 2 and the diffusion layer 45 in this order. In the diode shown in FIG. 2C, holes h function as majority carriers, and electrons e as minority carriers flow from the N + -type impurity diffusion layer 45, etc. to the P-type silicon substrate 2, as in the case of the FRD of the parasitic diode structure. These minority carriers (electrons e) may reduce the operation speed of the diode, if there is no carrier-recombination-center layer 10. In other words, in this case, too, the provision of the P-type silicon substrate 2 increases the extinction rate of the minority carriers (electrons e), thereby increasing the operation speed of the diode. It is a matter of course that the current capacity of the logic-related element 9, which is formed in the same substrate 1 as the power-related element 7, is prevented from reducing, as in the case of the power MOS transistor. The diode of FIG. 2C may be formed in the same substrate 1 as the lateral IGBT of FIG. 2B, and used as a recovery diode (FRD) for the IGBT. This is because the lateral IGBT cannot have a FRD of a parasitic diode structure as employed in the power MOS transistor. In the case of using the diode of FIG. 2C as a FRD, the cathode (K D ) is connected to the collector (C I ) of the IGBT of FIG. 2C by means of a wire layer, and the emitter (E I ) is connected to the anode (A D ) by means of another wire layer. Connecting the FRD to the lateral IGBT as described above can not only increase the operational speed of the device, but also increase the speed of switching from the On-state to the Off-state. Moreover, in this case, too, the influence of the life time control of the logic-related element 9, which is formed in the same substrate 1 as the power-related element 7, is prevented from reducing. The structure of the logic-related element 9 shown in FIG. 1 will be explained. First, a vertical NPN bipolar transistor as an example of the logic-related element 9 will be explained. As is shown in FIG. 3A, a high density N + -type embedded diffusion layer 51 is formed in a boundary region between the P-type silicon substrate 2 and the N-type epitaxial silicon layer 3. A P-type impurity diffusion layer 52 which serves as the base (B VB ) of the bipolar transistor is formed in the N-type epitaxial silicon layer 3. An N + -type impurity diffusion layer 53 which serves as the emitter (E VB ) of the bipolar transistor is formed in the P-type impurity diffusion layer 52. Further, a deep and high density N + -type contact diffusion layer 54 is formed in the N-type epitaxial silicon layer 3, separated from the diffusion layer 52. An insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the N-type epitaxial silicon layer 3. A first contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 53. An emitter (E VB ) electrode wire 56 is electrically connected to the diffusion layer 53 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 52. A base (B VB ) electrode wire 57 is electrically connected to the diffusion layer 52 through the second contact hole. A third contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 54. A collector (C VB ) electrode wire 58 is electrically connected to the diffusion layer 54 through the third contact hole. The operation of the above-described vertical bipolar transistor will be explained. Where the collector (C VB ) is at a high potential and the emitter (E VB ) is at a low potential, current is supplied to the base (B VB ), i.e., holes h are supplied to the P-type impurity diffusion layer 52. Specifically, a bias current is supplied such that a forward current path is formed between the emitter (E VB ) and the base (B VB ). As a result, electrons e flow through the N + -type impurity diffusion layer 53, the P-type impurity diffusion layer 52 and the N + -type embedded diffusion layer 51 in this order. In other words, current flows through the diffusion layer 54, the embedded diffusion layer 51, the diffusion layer 52 and the diffusion layer 53 in this order. Since in the vertical bipolar transistor shown in FIG. 3A, current flows through the N-type epitaxial silicon layer 3 without passing the P-type silicon substrate 2, the h FE (current amplification factor) is prevented from being reduced by the carrier-recombination-center layer 10. A lateral PNP bipolar transistor as another example of the logic-related element 9 will be explained. As is shown in FIG. 3B, a high density N + -type embedded diffusion layer 61 is formed in a boundary region between the P-type silicon substrate 2 and the N-type epitaxial silicon layer 3. A P-type impurity diffusion layer 62 which serves as the emitter (E LB ) of the bipolar transistor is formed in the N-type epitaxial silicon layer 3. Further, a P-type impurity diffusion layer 63 which serves as the collector (C LB ) of the bipolar transistor is formed in the silicon layer 3, separated from the diffusion layer 62 and surrounding the same. Moreover, a deep and high density N + -type contact diffusion layer 64 is formed in the silicon layer 3, separated from the diffusion layers 62 and 63. An insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the silicon layer 3. A first contact hole (which is, for example, annular) is formed in that portion of the insulating film 27 which is located on the diffusion layer 63. A collector (C LB ) electrode wire 66 is electrically connected to the diffusion layer 63 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 62. An emitter (E LB ) electrode wire 67 is electrically connected to the diffusion layer 62 through the second contact hole. A third contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 64. A base (B LB ) electrode wire 68 is electrically connected to the diffusion layer 64 through the third contact hole. The operation of the lateral type bipolar transistor constructed as above will be explained. Where the emitter (E LB ) is at a high potential and the collector (C LB ) is at a low potential, current is let to flow out of the base (B LB ), i.e., electrons e are supplied to the N + -type impurity diffusion layer 64. Specifically, a bias current is supplied such that a backward current path is formed between the emitter (E LB ) and the base (B LB ). As a result, holes h flow through the P + -type impurity diffusion layer 62, the N-type epitaxial silicon layer 3 and the P + -type embedded diffusion layer 63 in this order. In other words, current flows through the diffusion layer 62, the silicon layer 3 and the diffusion layer 63 in this order. Since in the lateral bipolar transistor shown in FIG. 3B, current flows through the N-type epitaxial silicon layer 3 without passing the P-type silicon substrate 2, as in the vertical bipolar transistor of FIG. 3A, the h FE (current amplification factor) is prevented from being reduced by the carrier-recombination-center layer 10. A P-channel MOSFET as a further example of the logic-related element 9 will be explained. As is shown in FIG. 3C, a P-type impurity diffusion layer 71 which serves as the source (S PM ) of the MOSFET is formed in the N-type epitaxial silicon layer 3. A P-type impurity diffusion layer 72 which serves as the drain (D PM ) of the MOSFET is formed in the N-type epitaxial silicon layer 3, separated from the diffusion layer 71. A gate insulating film is formed on the N-type epitaxial silicon layer 3 between the diffusion layers 71 and 72, and a gate electrode (G PM ) is formed on the gate insulating film. An insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the silicon layer 3. A first contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 71. A source (S PM ) electrode wire 74 is electrically connected to the diffusion layer 71 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 72. A drain (D PM ) electrode wire 75 is electrically connected to the diffusion layer 72 through the second contact hole. The operation of the MOSFET constructed as above will be explained. Where the source (S PM ) is at a high potential and the drain (D PM ) is at a low potential, a low potential is supplied to the gate (G PM ), a channel is formed in the N-type epitaxial silicon layer 3 under the gate, and holes h flow from the diffusion layer 71 to the diffusion layer 72. As described above, current flows through the N-type epitaxial silicon layer 3 without passing the P-type silicon substrate 2, as in the case of the bipolar transistors, and hence the V th (threshold voltage) is prevented from being shifted by the carrier-recombination-center layer 10. An N-channel MOSFET as a furthermore example of the logic-related element 9 will be explained. As is shown in FIG. 3D, a P-type well region 81 is formed in the N-type epitaxial silicon layer 3. An N-type impurity diffusion layer 82 which serves as the source (SNM) of the MOSFET is formed in the P-type well region 81. An N-type diffusion layer 83 which serves as the drain (D NM ) of the MOSFET is formed in the silicon layer 3, separated from the diffusion layer 82. A gate insulating film is formed on that portion of the P-type well region 81 which is located between the diffusion layers 82 and 83, and a gate electrode (G NM ) is formed on the gate insulating film. An insulating film 27 such as a silicon oxide (SiO 2 ) film is formed on the silicon layer 3. A first contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 82. A source (SNM) electrode wire 85 is electrically connected to the diffusion layer 82 through the first contact hole. A second contact hole is formed in that portion of the insulating film 27 which is located on the diffusion layer 83. A drain (D NM ) electrode wire 86 is electrically connected to the diffusion layer 83 through the second contact hole. The operation of the N-channel MOSFET constructed as above will be explained. Where the drain (D NM ) is at a high potential and the source (S NM ) is at a low potential, a high potential is supplied to the gate (G NM ), a channel is formed in the P-type well region 81 under the gate (G NM ), and electrons e flow from the diffusion layer 82 to the diffusion layer 83. Thus, current flows through the N-type epitaxial silicon layer 3 without passing the P-type silicon substrate 2, as in the case of the bipolar transistors, and hence the V th (threshold voltage) is prevented from being shifted by the carrier-recombination-center layer 10. FIG. 4 is a cross sectional view, more specifically showing the semiconductor integrated circuit device of FIG. 1. In the device of FIG. 4, a diode is used as the power-related element 7, and a vertical NPN bipolar transistor is used as the logic-related element 9. The P-type silicon region 4 which separates the power-related element 9 from the logic-related element 7 is a diffusion layer formed by diffusing a P-type impurity from the major surface 8 of the substrate 1, i.e., the surface of the N-type epitaxial silicon layer 3. Since in the above structure, the carrier-recombination-center layer 10 overlaps the current path of a diode as the power-related element 7, the diode can operate at high speed. On the other hand, since the current path of the vertical NPN transistor as the logic-related element 9 is located in a shallow portion of the N-type epitaxial silicon layer 3, it is not adversely affected by the carrier-recombination-center layer 10, thereby reducing the influence of the life time control. In the semiconductor integrated circuit device according to the first embodiment, the power-related element 7 shown in FIG. 1 is selected from the elements having current paths formed in deep portions of the substrate as shown in FIGS. 2A - 2C, respectively; and the logic-related 9 is selected from the elements having current paths formed in shallow portions of the substrate as shown in FIGS. 3A - 3D, respectively. In any combination of the power-related element 7 and the logic-related element 9, provision of the carrier-recombination-center layer 10 in a deep portion of a substrate can satisfy both the demand that the power-related element 7 be operated at high speed, and the demand that the logic-related element 9 have a sufficient current capacity. FIG. 5 is a cross sectional view, showing a semiconductor integrated circuit device according to a second embodiment of the invention. As described above, in the first embodiment, the P-type silicon region 4 is formed in the N-type epitaxial silicon layer 3 such that it reaches the P-type silicon substrate 2, thereby separating only the silicon layer 3 into two portions by PN junction. On the other hand, in the second embodiment, a laminated structure of a P-type silicon layer 102 and an N-type silicon layer 103 is isolatedly separated into two portions by a dielectric region 12. The P-type silicon layer 102 corresponds to the P-type silicon substrate 2 of FIG. 1, and therefore has the carrier-recombination-center layer 10 formed therein. Further, the N-type silicon layer 103 corresponds to the N-type epitaxial silicon layer 3 of FIG. 1. As described above, isolating the power-related element 7 from the logic-related element 9, together with the P-type silicon layer 102 having the carrier-recombination-center layer 10 formed therein, increases the degree of insulation between the elements 7 and 9 as compared with the first embodiment. FIG. 6 is a cross sectional view, showing a specific example of the semiconductor integrated circuit device of FIG. 5. In this case, a power MOS transistor is used as the power-related element 7 and a vertical NPN bipolar transistor is used as the logic-related element 9. Further, a complete dielectric isolation substrate is used in the FIG. 6 device. This substrate type is called an "EPIC" (Epitaxial Passivated Integrated Circuit: a registered trademark of US Motoroller Corporation) type. Specifically, this device includes a supporting polysilicon substrate 101 having an isolating projection of a tapered cross section. The isolating projection of the substrate 101 isolates regions, each of which has a laminated structure portion consisting of a P-type silicon layer 102 and an N-type silicon layer 103. Silicon oxide films (SiO 2 ) 104 which correspond to the dielectric region 12 in FIG. 5 are formed on surface portions of the supporting polysilicon substrate 101. FIG. 7 is a cross sectional view, showing another specific example of the semiconductor integrated circuit device of FIG. 5. In this case, too, a power MOS transistor is used as the power-related element 7 and a vertical NPN bipolar transistor is used as the logic-related element 9. Further, a dielectric isolation lamination substrate is used in the FIG. 7 device. This substrate type is called an "SDB" (Silicon wafer Direct Bonding) type, in which two silicon substrate are bonded to each other by means of a silicon oxide film. Specifically, first, a first silicon substrate 151 is coated with a silicon oxide film (SiO 2 ) 152 by thermally oxidizing the surface of the substrate 151 or depositing thereon a silicon dioxide. Then, a second P-type silicon substrate 2 is adhered to the oxide film 152, and an N-type epitaxial silicon layer 3 is formed on the silicon substrate 2. Thereafter, a trench is formed such that it extends through the silicon layer 3 and the silicon substrate 2 and reaches the oxide film 152. When isotropic etching such as a CDE has been used, a trench with a cross section as shown in FIG. 7 is obtained. In other words, the trench thus obtained has a wide opening and a narrow bottom. Actually, a plurality of such trenches are formed in a grid pattern (not shown), thereby defining island regions each of which has a laminated structure of the silicon substrate 2 and the silicon layer 3. Thereafter, silicon oxide films (SiO 2 ) 153 are formed, by thermal oxidation or by the deposition of a silicon dioxide, on those side portions of the silicon substrate 2 and the silicon layer 3 which are exposed in the trench. Subsequently, the trench is filled with a polysilicon layer 154. In this case, the silicon oxide films 152 and 153 correspond to the dielectric region 12 of FIG. 12. As explained above, a dielectric isolation type substrate can be used. FIG. 8 is a cross sectional view, showing a further example of the semiconductor integrated circuit device of FIG. 5. In this case, too, a power MOS transistor is used as the power-related element 7 and a vertical NPN bipolar transistor is used as the logic-related element 9. In the FIG. 8 device, the power-related element 7 (the power MOS transistor) is isolated from the logic-related element 9 (the vertical NPN bipolar transistor) by means of a trench formed by anisotropic etching such as RIE. The trench formed by anisotropic etching has a cross section as shown in FIG. 8, i.e., the trench has an opening and a bottom whose sizes are substantially equal to each other. The other basic structure of the FIG. 8 device is similar to that of FIG. 7. Therefore, like element is denoted by like reference numeral, and no detailed explanation will be given of. Even where element isolation is performed by the use of a trench as shown in FIG. 8, substantially the same advantage as that of the FIG. 7 device can be obtained. In the above-described second embodiment, the carrier-recombination-center layer 10 can be formed by the following method, as well as by injecting heavy particles: In this method, crystal defects are beforehand formed in at least one of the P-type silicon substrate 2 and the P-type silicon layer 102. To form crystal defects, for example, a high density impurity layer is formed by injecting ions of high density. In this case, however, the impurity layer can be formed only in a shallow portion of the substrate as compared with the case of injecting heavy particles. To form such an impurity layer in the structure of FIG. 6, the impurity layer is formed in a bottom portion of the island region along the silicon oxide film 104. Further, in the cases of FIGS. 7 and 8, the impurity layer is formed in a bottom portion of the substrate 2 along the oxide film 152. As explained above, in the case of forming a high density impurity layer by injecting ions of high density, the power-related element 7 is formed at a location at which its current path extends in the high density impurity layer, while the logic-related element 9 is formed at a location at which its current path does not extend in the high density impurity layer. This structure can simultaneously satisfy both a demand for an increase in the switching speed of the power-related element 7 and a demand for reducing the influence of the life time control on the logic-related element 9. Although in the second embodiment, a power MOS transistor is used as the power-related element 7 and a vertical NPN bipolar transistor is used as the logic-related element 9, the elements 7 and 9 may be identical to those employed in the first embodiment. In other words, the element 7 may be selected from the elements having current paths formed in deep portions of the substrate as shown in FIGS. 2A - 2C, respectively; and the element 9 may be selected from the elements having current paths formed in shallow portions of the substrate as shown in FIGS. 3A - 3D, respectively. In any combination of the power-related element 7 and the logic-related element 9, provision of the carrier-recombination-center layer 10 in a deep portion of the substrate can provide a semiconductor integrated circuit device wherein both an element of high switching speed and an element which the influence of the life time control should be prevented are formed in a single chip. Although, for example, an IPD is used as an example of a semiconductor integrated circuit device in the first and second embodiments, it is a matter of course that the invention is also applicable to another type semiconductor integrated circuit device, only if the device is demanded to have an element of high operation speed and an element which the influence of the life time control should be prevented.

Claims: A semiconductor integrated circuit device comprising: a semiconductor substrate (1); a fast switching lateral first device (7), formed in the semiconductor substrate and having a first current path (A) in a first portion of the semiconductor substrate (1); a second device (9) provided to drive or control said first device (7) and formed in the semiconductor substrate (1) so as to be separated from said first device (7) and having a second current path (B) in a second portion of the semiconductor substrate (1), said second portion being shallower than said first portion; and a carrier recombination-center layer (10) formed in said first portion of said semiconductor substrate (1); wherein said semiconductor substrate (1) including a first semiconductor layer (2) of a first conductivity type, a second semiconductor layer (3) of a second conductivity type formed on said first semiconductor layer (2), and an isolating region (4; 12; 154) for providing in said second semiconductor layer (3) a first island region (5) and a second island region (6) electrically isolated and separated from each other; said first device (7) having said first current path (A) extending in said first island region (5) and said first semiconductor layer (2); said second device (9) having said second current path (B) extending in said second island region (6); and said carrier recombination-center layer (10) being formed in said first semiconductor layer (2) wherein said first current path (A) extends laterally through said carrier recombination layer (10). The semiconductor integrated circuit device according to claim 1, wherein said isolating region (4) is a first-conductivity type semiconductor region which extends from a major surface (8) of said semiconductor layer (3) to said first semiconductor layer (2). The semiconductor integrated circuit device according to claim 1, wherein said isolating region (12) is a dielectric region which extends from a major surface (8) of said semiconductor layer (3) to said first semiconductor layer (2). The semiconductor integrated circuit device according to claim 1, wherein said semiconductor substrate (1) further includes a third semiconductor layer (151) formed on a back surface of said first semiconductor layer (2), said back surface being opposite to a front surface on which said second semiconductor layer (3) is formed, with an insulating film (152) interposed between said first layer (2) and said third layer (151); and said isolating region (154) is an insulating layer which extends from a major surface (8) of said second semiconductor layer (3) to said insulating film (152). The semiconductor integrated circuit device according to any of the preceding claims, wherein said carrier-recombination center (10) is further formed in said first semiconductor layer (2) in said second portion of the semiconductor substrate (1). The semiconductor integrated circuit device according to any of the preceding claims, wherein said carrier-recombination center (10) is a crystal defect layer. The semiconductor integrated circuit device according to any of the preceding claims, wherein said first element (7) is a power-related element, and said second element (9) is a logic-related element. The semiconductor integrated circuit device according to claim 7, wherein said first element (7) as a power-related element is selected from a group consisting of a lateral double-diffusion MOSFET, a lateral insulated-gate bipolar transistor and a diode. The semiconductor integrated circuit device according to claim 7, wherein said second element (9) as a logic-related element is selected from a group consisting of a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, a P-channel MOSFET and an N-channel MOSFET.

Inventors: ENDO KOICHI, ENDO, KOICHI, ENDO, KOICHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L27
IPC codes: H01L27, H01L21