Data storage apparatus having memory area having predetermined logic type

Abstract: A data memory (12) of an IC card is divided into a plurality of areas, a logic type used when data is written in each area is set, and the logical AND between the written data and stored data in the memory (12) is calculated by an AND logic circuit (111) and written in the memory (12). In read access, output data can be directly obtained from the memory (12).

Description: The present invention relates to a data storage apparatus provided in an electronic apparatus such as an IC card incorporating an IC chip having a nonvolatile memory and a control element such as a CPU for controlling the nonvolatile memory, which apparatus serves to write/read data in a plurality of areas having a predetermined type and divisionally set in the memory. In recent years, as a portable data storage medium, an IC card incorporating an IC chip having a nonvolatile data memory and a control element such as CPU for controlling the nonvolatile memory has received a great deal of attraction. In an IC card of this type, an incorporated data memory is divided into a plurality of areas, and data processed in a predetermined application are stored in the areas, respectively. As a method of accessing these areas, a method of writing or reading binary data can be considered. JP-A-62 60081 describes a system to enable a microprocessor for an IC card to perform data processing invariably with the same logic by providing a means which converts the logic of data to be transmitted to a terminal and data sent from the terminal in the card body. Data sent from the IC card to the terminal is supplied from the MPU to the OR gate of a logic converting circuit. Data sent from the terminal, on the other hand, is supplied from a serial interface to the OR gate of the logic converting circuit. Further data for logic conversion is supplied from the MPU to both OR gates. Consequently, the control data is set to `0' to supply the data to the interface or MPU without changing the logic. When the control data is set to `1', on the other hand, the logic of the data is inverted and the data is supplied to the interface or MPU. Therefore, the data processing is carried out with the same logic at any time. JP-A-2 144 644 describes a system to shorten check time by writing optional data generated by a data generating means and data obtained by inverting the bits of the optional data in the whole space of a memory part and discriminating whether a memory part is normal or not based upon respective results of 1 st and 2 nd check means for checking whether writing is normally executed or not. Optional data (a character) is inputted from outside and written in the memory part to verify it. Data obtained by inverting the bit of the optional data is inputted from outside and written in the memory part to verify it. When the data is not normally written as the checked result, a control element outputs status meaning memory abnormality to terminal equipment. Although 256 writing/verifying operations are required for checking one byte in an ordinary method, the memory part can be checked by two writing/verifying operations in this method. Consequently, the check time can be shortened and load for the number of times of guarantee of the memory part can be reduced. An IC card having a structure mentioned as above is known in Japanese Patent Application (KOKAI) Publication No. 4-40587 corresponding to U.S. Patent Application Serial No. 07/710.025. In this IC card, a user's area of a memory allocated to a user is divided into a plurality of sub-areas to each of which is written with a prescribed initial code such as "FF" or "00", so that the reliability of the user's area written with the initial code "FF" or "00", however, cannot be performed in the same data writing method. In the case of the initial code "FF", the data writing should be done using the AND logic, while in the case of the initial code "00", the data writing should be performed using the OR logic, so as to perform the data writing correctly. Accordingly, when an IC card is processed in an IC card processing apparatus, the IC card should have a memory written with a prescribed initial logic condition, AND logic condition for example. In this case, if an IC card having a memory having a different logic condition, OR logic condition, is inserted into the IC card processing apparatus, this card cannot be processed therein. Moreover, in the case of an IC card provided as a multi-purpose card to be suited for a plurality of user's system should be stored in each user's area when the IC card is issued. However, when different initial logic conditions are set in the memory areas provided for the plurality of user's system, it is necessary to change the logic condition of data to be written in the different user's area of the memory, thereby lowering the processing speed for issuing the IC card. It is an object of the present invention to provide a data storage apparatus capable of considerably increasing the processing speed of a process for dividing a memory into a plurality of areas. According to an aspect of the present invention, there is provided a data storage apparatus, having a memory having a predetermined logic type and divided into a plurality of areas, for writing/reading data in/from the divided areas, comprising: write logic type setting means for selectively setting one of a plurality of write logic types for each divided area of the memory, the write logic type being used when data is written in the areas; first writing means for directly writing received write data in the areas second writing means for inverting and writing the received data in the areas; first reading means for directly reading and outputting the data form the areas; second reading means for inverting, reading, and outputting the data from the areas and selecting means for selecting said first writing means and said first reading means when the write logic type of the areas set by said write logic type setting means coincides with a logic type of said memory, and for selecting said second writing means and said second reading means when the logic of the areas does not coincide with the logic type of said memory. According to another aspect of the present invention, there is also provided a method for storing data using a memory divided into a plurality of areas, for writing/reading data in/from the divided areas, comprising: selectively setting one of a plurality of logic types for each divided area of the memory, the logic type being used when data is written in the same areas; writing received write data in the areas; inverting and writing the received data in the areas; directly reading and outputting the date from the areas inverting, reading, outputting the data from the areas; selecting one of a first and second writing means based on the logic type set by said logic type setting means at a data writing time; and selecting one of a first and second reading means on the basis of the logic type set by said logic type setting means at a data reading time. According to the present invention, when areas having different logic types are set in the same memory, the initial states of the areas need not be set according to the logic types. Therefore, the processing speed of a process for dividing a memory into a plurality of areas considerably increases. This invention can be more fully understood from the detailed description when taken in conjunction with the accompanying drawings, in which: FIG.1 is a block diagram showing the arrangement of a card handling apparatus to which an IC card according to an embodiment of the present invention is applied; FIG. 2 is a block diagram showing the arrangement of the IC card; FIG. 3 is a memory map showing the arrangement of a data memory; FIG. 4 is a view showing the arrangement of a directory set in the data memory; FIG. 5 is a view showing the format of an area set in the data memory; FIG. 6 is a view showing the format of a data read command; FIG. 7 is a view showing the format of a data write command; FIG. 8 is a view showing the format of a data erase command; FIG. 9 is a view showing the format of area attribute information; FIG. 10 is a view showing a data storage area; FIG. 11 is a view showing a state obtained after data are written in the area; FIG. 12 is a view showing a state obtained after data are erased from the data storage area; FIG. 13 is a view for explaining access control to an area of AND logic; FIG. 14 is a view for explaining access control to an area of OR logic; FIG. 15 is a flow chart for explaining an initial operation of the IC card; FIG. 16 is a flow chart for explaining an operation performed by the data read command; FIG. 17 is a flow chart for explaining an operation performed by the data write command; FIG. 18 is a flow chart for explaining the operation performed by the data write command; and FIG. 19 is a flow chart for explaining an operation performed by the data erase command. An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the arrangement of a card processing device 10 which is used as a terminal device for, e.g., a banking system or shopping system, and to which an IC card serving as a portable electronic device according to this embodiment is applied. That is, an IC card 1 can be connected to a control unit 3 constituted by a CPU through a card reader/writer 2. A keyboard 4, a CRT display 5, a printer 6, and a floppy disk 7 are connected to the control unit 3, thereby constituting the device 10. FIG. 2 shows the arrangement of the IC card 1. The IC card 1 is constituted by a CPU 11 serving as a control unit, a programmable nonvolatile data memory 12, a working memory 13, a program memory 14, a contact unit 15 for obtaining electrical contact with the card reader/writer 2 of the processing device 10. Of these constituent elements, the elements (the CPU 11, the data memory 12, the working memory 13, and the program memory 14) surrounded by a dashed line in FIG. 2 are constituted by one IC chip and mounted in the IC card main body. Note that the elements surrounded by the dotted line may be constituted by a plurality of IC chips. The data memory 12 is used to store various data, and is constituted by, e.g., an EEPROM. The working memory 13 is a memory, e.g., a RAM for temporarily holding process data used when the CPU 11 performs data processing. The program memory 14 is constituted by, e.g., a mask ROM, and stores a program for the CPU 11 or the like. The data memory 12, as shown in FIG. 3, is divided into a control area 120, a directory area 121, an empty area 122, and an area group 123. These areas are managed by the directory 121. The directory area 121, as shown in FIG. 4, is constituted by areas for storing a set of pieces of area defining information each constituted by an area number 21, a top address 22, a size 23, an attribute 24, and a check code 25 of each area. For example, the top address 22 of area [01] is address aaa, and the size 23 of area [01] is Sa bytes. FIG. 5 shows the format of each directory area. As shown in FIG. 5, each area is constituted by a single word or a plurality of words each constituted by a data storage area and a BCC (block check character) storage area. At this time, when the size of a given area is calculated, and the size is 2 to 256 bytes, the given area is constituted by one word. When the size is larger than 256 bytes, the given area is constituted by one 256-byte word and a word having remaining bytes (including one BCC byte). When the size is less than 256, for example, an area having a size of 65 bytes is recognized as an area in which one 65-byte word (a 64-byte data storage area and a 1-byte BCC storage area) is present. When the size is 550 bytes, an area is constituted by total three words, i.e., two 256-byte words (a 255-byte data storage area and a 1-byte BCC storage area) and a 38-byte word (a 37-byte data storage area and a 1-byte BCC storage area). As shown in FIG. 5, an address in each area uses a relative address value such that the top address of the area is set to be '0000'. As shown in FIG. 5, the address is numbered except for a BCC storage area (for this reason, an application area can be accessed regardless of the presence of the BCC storage area). Therefore, the final address of the area is calculated by the following equation. final address = (upper byte of Sn) * 255 + (lower byte) The following three types of access commands are known for each area. The first access command is a command for reading data from an area, and, as shown in FIG. 6, is constituted by a function code representing a read command, an area number to be accessed, information representing the top address of a range to be accessed, and information for setting the number of bytes of data to be read. The second access command is a command for writing data in an area, and, as shown in FIG. 7, is constituted by a function code representing a write command, an area number to be accessed, information representing the top address of a range to be accessed, the number of bytes of data to be written, and the data to be written. The third access command is a command for erasing data from the area, and as shown in FIG. 8, is constituted by a function code representing an erase command, an area number to be accessed, information representing the top address of a range to be accessed, and the number of bytes of data to be erased. Attribute information having a format shown in FIG. 9 is set in each area. As shown in FIG. 9, the following modes, i.e., attributes are defined in units of areas by the upper significant bits "1" and "2". The remaining 6 bits are dummy bits fixed to "0". (1) AND Logic Type The logical AND between stored data and given data is calculated using "AND logic". The logical AND is written in an area (corresponding to an overwrite operation when the initial state of a bit is set to be "1") (2) OR Logic Type The logical OR between the stored data and the given data is calculated using "OR logic". The logical OR is written in an area (corresponding to an overwrite operation when the initial state of a bit is set to be "0"). (3) OTW Type Only when the stored data is set in an initial state, given data is written in an area. (4) REWRITE Type The stored data is rewritten with the given data. Write control to the modes described above will be described below with reference to FIG. 10. FIG. 10 shows a state wherein data is written in an area starting from relative address $0110 to relative address $02AF (the remaining area is set in an empty state) in an area in which a data storage area has 2,687 bytes (area size: 2,698 bytes) as the total number of bytes. Note that although the data in the remaining area set in the empty state is output in response to the data read command, at this time, the values of areas are different from each other depending on the attributes of the areas to be accessed. (a) area of AND logic: '00' (b) area of OR logic: 'FF' In this state, as shown in FIG. 11, an operation of writing 144-byte data starting from address $0280 is considered. This operation is changed depending on the attributes of areas. When an area of AND logic is used, the logical AND between stored data stored at addresses between address $0280 and address $030F and input data is calculated using AND logic, and the calculation result is written in the area. When an area of OR logic is used, the logical OR between the stored data and the input data is calculated using OR logic, and the calculation result is written in the area. When an area of OTW logic is used, and the stored data is written in an area to be written, a data write command is rejected. In addition, when a REWRITE type area is used, the input data is written (rewritten) independently of the stored data. Erase control to each mode will be described below with reference to FIG. 12. In the state shown in FIG. 10, an operation of erasing data at addresses between address $0180 and address $020F is considered. In this case, when the top address is designated as address $0180 by the data erase command described above, and the number of bytes of data to be erased is designated as '90' Hex (i.e., 144 bytes), the following result is obtained. As described above, "AND logic" or "OR logic" write access is determined by the attribute of each area. However, in a memory supported by an IC card, an initial state is generally set to be 'FF' or '00'. For this reason, in the former, basically, an area of "AND logic" type is obtained; in the latter, an area of "OR logic" type is obtained. At this time, when an area defined by the "OR logic" is to be set in a memory having an initial state of 'FF', all data in this area must be initialized to be '00' in an initial state. For this reason, areas having different attributes can be realized in a memory having a single attribute. As shown in FIG. 13, in an area of AND logic in the memory 12 of AND logic set at "FF", in write access, the logical AND between input data and the stored data from the data memory 12 is calculated by an AND logic circuit 111, and the calculation result is written in the data memory 12, thereby obtaining the area of AND attribute in the memory 12. In addition, in read access, the data from the memory 12 is directly output. While, as shown in FIG. 14, in an area of OR logic in the memory of AND logic set at "FF", in write access, the logical AND between a resultant value obtained by inverting input data by a bit inverter 112 (for example, the data can be inverted by calculating the exclusive-OR between the input data and '00' data) and the stored data from the memory 12 is calculated by the AND logic circuit 111, and the calculation result is written in the memory 12, thereby obtaining the area of OR logic in the memory 12. In addition, in read access, a resultant value obtained by inverting the data in the memory 12 by an inverter 113 is output. In FIGS. 13 and 14, areas set in the memory 12 of AND logic are exemplified. As shown in FIG. 2, the circuitry connected between the CPU 11 and the data memory 12 is provided to be used commonly for the circuits shown in FIGS. 13 and 14. When the circuitry of FIG. 2 is used as the circuit of FIG. 13, the AND logic circuit 111 is selected by the CPU in the logic circuit 115 and the switch 116 is switched to the contact 116a. While, in the case of FIG. 14, the switch 116 is switched to the contact 116b to select the bit inverter 112 which is also used as the bit inverter 113 when the operation mode is switched to the read access operation to invert the output of the memory 12. On the other hand, when the attribute of the memory 12 is OR logic, and data is to be written in an area of AND logic set in the memory 12, as in the case of FIG. 14, the switch contact 116b and OR logic circuit 114 in the logic circuit 115 are selected by the CPU 11 and the data is inverted in the bit inverter 112 , the logical OR between the inverted data and the stored data read from the memory 12 is calculated using the OR logic circuit 114 in place of the AND logic circuit 111, and the calculation result is written in the area of the memory 12. In addition, in read access, the contents of the memory area are inverted by the bit inverter 112 used as the bit inverter 113 as shown in FIG. 14 and output as in FIG. 14. When an area of OR logic in the memory 12 of OR logic attribute is used, the switch contact 116a is selected and the data is not inverted in write access of the data, the logical OR between the stored data and the input data is calculated using the OR logic circuit 114 in place of the AND logic circuit 111 in FIG. 13, and the calculation result is written in this area. In addition, in read access, the contents of the area are directly output without being inverted. An operation of the IC card 1 will be described below with reference to FIG. 15. When the IC card 1 is inserted into the terminal device 10, the IC card 1 receives a source voltage and a reset signal from the terminal device 10 through the contact unit 15 and is electrically activated. In this state, the IC card 1 is set in a command wait state in step ST1. At this time, the IC card 1 continuously waits for a command. When the command from the terminal device 10 is input to the IC card 1, the flow advances to step ST2 to extract an area number from the command and to check whether the corresponding area number is present in the directory 121. If the area number is not present in the directory 121, the flow advances from step ST3 to step ST4 to output an abnormal code representing no corresponding area, and returns to step ST1 to set the command wait state. If the area number is present in the directory 121, the flow advances to step ST5 to perform a process in each command routine corresponding to a function code of the input command and to output the processing result, and the flow returns to step ST1 to set the command wait state. An operation of a data read command will be described below with reference to FIG. 16. As shown in FIG. 16, it is checked in step ST11 whether the top read address in the command is set within a designated area. At this time, the lower limit of the range of address values is '0000' and the upper limit of the range is the final address of the corresponding area. In this check operation, when the designated top address falls outside the designated range, designated address abnormal code data is output in step ST12, and the flow returns to step ST1 to set the command wait state. When the address value is set within the range, it is checked in step ST13 whether data corresponding to the number of bytes of data to be read is present in the corresponding area. For this purpose, it is checked whether a value obtained by adding the number of bytes of the data to the designated address and subtracting "1" from it is equal to or smaller than the final address of the corresponding area. If the value is larger than the final address, the flow advances to step ST14 to output address over abnormal code data, and returns to step ST1 to set the command wait state. If NO in step ST13, the flow advances to step ST15 to check the attribute of the corresponding area and to check whether the attribute is "OR logic". If NO in step ST15, the flow advances to step ST16 to read data corresponding to the designated number of bytes starting from a designated address and to directly output it. If YES in step ST15, the read data is inverted and output in step ST17. These processes are continuously performed until final data is detected in steps ST18 and ST19. When the final data is detected, validity of the read data is checked using a BCC accompanying a word having data to be read in step ST20. If the read data is normal, the read data is output together with normal end code data in step ST21, and the flow returns to step ST1 to set the command wait state. If abnormal data is detected using the ECC, the read data is finally output together with abnormal data denoting code data in step ST22, and the flow returns to step ST1 to set the command wait state. A data write operation will be described with reference to FIGS. 17 and 18. As shown in FIG. 17, it is checked in step ST31 whether the top write address in a command is set within a designated area. At this time, the lower limit of the range of address values is '0000', and the upper limit of the range is the final address of the corresponding area. In this check operation, when the designated top address falls outside the range, the flow advances to step ST32 to output designated address abnormal code data, and returns to step ST1 to set the command wait state. When the address value is set within the range, it is checked in step ST33 whether an address is over, i.e., whether a write area corresponding to the number of bytes of data to be written is present in the corresponding area. For this purpose, it is checked whether a value obtained by adding the number of bytes of data to be written to the designated address and subtracting "1" from it is equal to or smaller than the final address of the corresponding area. If the value is larger than the final address, the flow advances to step ST34 to output address over abnormal code data, and returns to step ST1 to set the command wait state. If the write area corresponding to the number of bytes of the data to be written is present in the corresponding area, it is checked in step ST35 whether the attribute of the area is an "OTW" type. If NO in step ST35, the operation shifts to the write operation from step ST38. If YES in step ST35, it is checked in step ST36 whether 'FF' representing that all areas to be written are empty areas is set. If NO in step ST36, abnormal code data denoting not empty is output in step ST37, and the flow returns to step ST1 to set the command wait state. If YES in step ST37, a write operation from step ST38 is started. In the write operation, an area attribute is referred to in step ST38 to check whether the area attribute is "OR logic". If YES in step ST38, the flow advances to step ST39 in FIG. 18. The AND (logical AND) between data generated by inverting the stored data as shown in FIG. 14 and the stored data of the area to be written is calculated, and the calculation result is written in the memory 12. If NO in step ST38, it is checked in step ST40 whether the attribute represents a rewritable area. If YES in step ST40, data corresponding to the designated number of bytes starting from a designated address is written. If NO in step ST40, as shown in FIG. 13, in step ST42, the logical AND between data corresponding to the designated number of bytes starting from the designated address and the stored data of the area to be written is calculated, and the calculation result is written. It is checked in steps ST43, ST44, and ST45 whether the data rewrite operations in steps ST39, ST41, and ST42 are ended up to the designated final byte. If YES in steps ST43, ST44, and ST45, the flow advances to step ST46 to use the read-after-write check to check whether the data can be normally written. If NO in step ST46, the flow advances to step ST47 to output abnormal write code data, and returns to step ST1 to set the command wait state. On the other hand, when a write operation is normally ended up to the designated final byte, the BCC of a word having data to be written is calculated and written at a predetermined position in step ST48. It is checked in step ST49 whether a write operation is normally performed. If YES in step ST49, normal data write end code data is finally output in step ST50, and the flow returns to step ST1 to set the command wait state. If NO in step ST49, abnormal write code data is finally output in step ST47, and the flow returns to step ST1 to set the command wait state. A data erase operation will be described below with reference to FIG. 19. As shown in FIG. 19, it is checked in step ST60 whether the top erase address in a command is set within a designated area. At this time, the lower limit of the range of address values is '0000' and the upper limit of the range is the final address of the corresponding area. In this check operation, when the designated top address falls outside the range, designated address abnormal code data is output in step ST61, and the flow returns to step ST1 to set the command wait state. When the top address is set within the range, it is checked in step ST62 whether an address is over, i.e., whether an erase area corresponding to the number of bytes of data to be erased is present in the corresponding area. For this purpose, it is checked whether a value obtained by adding the number of bytes of data to be erased to the designated address and subtracting "1" from it is equal to or smaller than the final address of the corresponding area. If the value is larger than the final address, the flow advances to step ST63 to output address over abnormal code data, and returns to step ST1 to set the command wait state. If NO in step ST62, 'FF' data corresponding to the number of designated bytes starting from a designated address is written in step ST64. This operation is continuously performed up to a designated final byte. When the final address is confirmed in step ST65, whether data is normally written is checked by the read-after-write check in step ST66. If NO in step ST66, abnormal write code data is output in step ST67, and the flow returns to step ST1 to set the command wait state. When the write operation of the 'FF' data is normally ended up to the designated final byte, the flow advances to step ST68 to calculate the BCC of a word having data to be written and write it at a predetermined position. When this write operation is normally performed, this is detected in step ST69, and the flow advances to step ST70 to finally output normal end code data and returns to step ST1 to set the command wait state. If NO in step ST69, abnormal write code data is finally output in step ST67, and the flow returns to step ST1 to set the command wait state. In the operation described above, the memory 12 of AND logic incorporated in the IC card has been exemplified. However, when a memory of OR logic is used, the present invention can be achieved by the following method. That is, when it is checked in step ST15 in the flow chart of FIG. 16 whether the area attribute is OR logic, the OR logic is replaced with AND logic. In the flow chart of FIG. 17, the present invention can be achieved by the following method. That is, when it is to be checked in step ST38 whether the area attribute is OR logic, the OR logic is replaced with AND logic. When it is to be checked in step ST36 whether all the data in the write area are set to be 'FF', the 'FF' is replaced with '00'. In the flow chart in FIG. 19, the present invention can be achieved by the following method. That is, when a process for writing 'FF' data in step ST64 is replaced with a process for writing '00'. Note that in FIGS. 16 and 19, after data to be written are completely written, whether this write operation is normally performed is checked by the read-after-write check. However, this check operation may be performed each time data corresponding to the specific number of bytes is written. In addition, the timing of calculation of the BCC and the timing of the write operation of the BCC can be changed. For example, the BCC may be calculated and written each time a data write operation in a word is ended. In FIGS. 17 and 18, although the BCC is checked after all data are read, the timing of checking the BCC can be changed. For example, the BCC may be checked when data in a word is read. In FIGS. 17 and 18, in write access, the logical AND or OR between stored data and input data is rewritten in place of the stored data. However, for example, when the memory element itself has an overwrite function using AND or OR logic, the calculation between the stored data and the input data may not be performed, and an overwrite operation may be performed using the function of the corresponding memory element. In this embodiment, although any one of AND logic and OR logic is selected depending on an attribute assigned to each area, for example, two types of function codes may be set for each of the commands shown in FIGS. 7 and 8, and these function codes may be used as AND and OR commands, respectively. In the embodiment, although the IC card has been exemplified as a device for performing data management, the shape of the device housing is not limited to a card-like shape. The shape can be changed into rod- or block-like shape. The present invention can be applied to not only a portable electronic device but also another electronic device. The arrangement contents of the device can be variously changed without departing from the scope of the present invention as defined in the appended claims. The IC card exemplified in this embodiment uses the contact unit to perform transmission/reception of data with an external device. However, a method in which the IC card can perform transmission/reception of data using light, an electric field, a magnetic field, or the like without being in contact with the external device may be used. As has been described above, according to the present invention, when areas having different logic types are set in a single logic memory, different initial states need not be set according to the different logic types. Therefore, there can be provided a storage data management apparatus capable of largely increasing the processing speed of a process for dividing a memory into a plurality of areas.

Claims: A data storage apparatus, having a memory (12) having a predetermined logic type and divided into a plurality of areas, for writing/reading data in/from the divided areas, characterized by: write logic type setting means (115) for selectively setting one of a plurality of write logic types for each divided area of the memory, the write logic type being used when data is written in the areas; first writing means (11) for directly writing received write data in the areas; second writing means (11,112) for inverting and writing the received data in the areas; first reading means (116a) for directly reading and outputting the data from the areas; second reading means (116b) for inverting, reading, and outputting the data from the areas; and selecting means (11) for selecting said first writing means and said first reading means when the write logic type of the areas set by said write logic type setting means coincides with a logic type of said memory, and for selecting said second writing means and said second reading means when the logic of the areas does not coincide with the logic type of said memory. A data storage apparatus according to claim 1, further comprising: a first read means (11) for reading out the data from said memory; a second read means (11) for reading out the data from said memory (12) with a logic state thereof being inverted; and means (11) for selecting one of said first and second read means based on the data stored in said storing means. A data storage apparatus according to claim 1, wherein said memory (12) is divided into a plurality of areas, and said storing means (121) stores data for determining a type of logic operations used for writing the data corresponding to said areas. A data storage apparatus according to claim 3, wherein said data for determining the type of logic operations represents whether the data is to be written into said memory (12) with an AND logic or the data is to be written into said memory (12) with an OR logic, and said selecting means (11) selects said first writing means when an initial logic state of said memory and the type of the logic operation is identical, and selects said second writing means when the initial logic state of said memory and the type of the logic operation is different. A data storage apparatus according to claim 4, wherein said selecting means (11) selects said first read means when the initial logic state of said memory and the type of the logic operation is identical, and selects said second read means when the initial logic state of said memory and the type of the logic operation is different. A method for storing data using a memory (12) divided into a plurality of areas, for writing/reading data in/from the divided areas, characterized by: selectively setting one of a plurality of logic types for each divided area of the memory (12), the logic type being used when data is written in the areas; writing received write data in the areas; inverting and writing the received data in the areas; directly reading and outputting the data from the areas; inverting, reading, outputting the data from the areas; selecting one of a first and second writing means based on the logic type set by said logic type setting means at a data writing time; and selecting one of a first and second reading means on the basis of the logic type set by said logic type setting means at a data reading time. A method according to claim 6, further comprising the steps of: discriminating the logic types set for the areas by said logic type setting step; performing predetermined logic calculation for the data in accordance with the logic type discriminated by said discriminating step; performing predetermined logic calculation for the data read by said reading step in accordance with the logic type discriminated by said discriminating step; and wherein said writing step includes a step of writing data logically calculated by said first logic calculating step in said memory. A method according to claim 7, wherein said first logic calculation step includes a step of calculating logical AND between the data and storage data stored in said memory. A method according to claim 7, wherein said first logic calculating step includes a step of inverting the data, and a step of calculating logical AND between the data inverted by said inverting step and storage data stored in said memory, and said second calculating step includes a step of inverting and outputting data stored in said memory. A data storage apparatus according to claim 1, further comprising: discriminating means (11) for discriminating the logic types set for the areas by said logic type setting means; first logic calculating means (115) for performing predetermined logic calculation for the data in accordance with the set logic type of said memory and the logic type of the areas discriminated by said discriminating means; writing means (11) for writing the data logically calculated by said first logic calculating means in the areas; reading means (11) for reading the data written in the areas; and second logic calculating means (115) for performing predetermined logic calculation for the data read by said reading means in accordance with the set logic type of said memory and the logic type of the areas discriminated by said discriminating means. An apparatus according to claim 10, wherein said first logic calculating means includes an AND circuit (111) for calculating logical AND between the data and storage data stored in said memory. An apparatus according to claim 10, wherein said first logic calculating means includes inverting means (112) for inverting the data and an AND circuit for calculating logical AND between the data inverted by said inverting means and storage data stored in said memory, and said second calculating means includes means (113) for inverting and outputting data stored in said memory.

Inventors: IIJIMA YASUO, IIJIMA, YASUO, IIJIMA, YASUO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: G07F7
IPC codes: G06K19, G07F7, G06F12