Method of forming resistors for integrated circuits by using trenches

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer (50), a first conductive layer (70) of high resistivity and a second conductive layer (80) of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

Description: FIELD OF THE INVENTION This invention relates to resistors for integrated circuits and a method of forming resistors. BACKGROUND OF THE INVENTION Multi-valued linear resistors are required for applications in integrated circuits, including for example, for static random access memory (SRAM) circuits, monolithic filters, and fusible links for programmable read only memories or redundant circuits. In a known method of providing a linear resistor for a MOS, Bipolar, or Bipolar CMOS (BiCMOS) silicon integrated circuit, a layer of polysilicon is deposited over a thick layer of dielectric, for example a field oxide provided on a silicon substrate. The polysilicon layer is patterned to define a resistor structure and then selectively doped by ion implantation. Typically, the polysilicon resistor structure comprises heavily doped end regions forming contact electrodes, and a resistive region extending between the contact regions which is doped sufficiently to provide a desired resistance value. The latter method of fabricating resistors is applicable to forming either n- or p- type ohmic resistors, particularly low and medium valued resistors for applications in MOS and bipolar digital and analog ICs, which are typically formed. Resistors in the low to medium resistance value ranges (i.e. 10-1000 ohm/sq) are linear over a wide voltage range. High value (gigaohm) leakage current resistors, used for example in applications for high density static random access memories (SRAMS), are more difficult to fabricate reproducibly, because undoped or lightly doped polysilicon is required to obtain high resistivities. The latter is more susceptible to process induced damage and defects, which degrade quality, create leakage and lead to poor reliability. More significantly, for a process to provide multi valued linear resistors on an integrated circuit, the resistive portion of each resistor of a different value requires a separate implantation step, with a different dopant dose, to provide a different doping level. Thus multiple photoengraving steps are required, and the number of masks depends on the number of different values of resistors required. SUMMARY OF THE INVENTION The present invention seeks to provide a method of forming resistor structures for integrated circuits and a resistor structure which avoids the above mentioned problems, and with particular application to providing multi-valued linear resistors by a process with a reduced number of photoengraving steps. According to one aspect of the present invention, there is provided a method of forming a resistive element for an integrated circuit. The method comprising: forming a steep sided trench (42) in a major surface of a semiconductor substrate (32) of an integrated circuit, the trench having first and second end contact regions (44) of a first lateral dimension and a narrower portion (46) extending therebetween; providing a conformal dielectric layer (50) over sidewalls and a bottom of the trench, the dielectric layer lining the trench and leaving a cavity (60) within the trench; providing a conformal first conductive layer (70) of a high resistivity material overlying the dielectric layer and of sufficient thickness to partially fill the end contact regions and at least partially fill the narrower portion of the trench; providing a second conductive layer (80) of a low resistivity material filling the contact regions and any unfilled part of the narrower portion of the trench; planarising the resulting structure by selectively removing those portions of the dielectric layer and the first and second conductive layers extending above the surface of the substrate; and annealing the structure for a sufficient time and at a temperature sufficient to cause interdiffusion of elements of the second conductive layer of low resistivity material with elements of the first conductive layer of high resistivity material, the first and second conductive layers thereby combining to form within the trench a conductive layer of mixed composition having a low resistivity in said end contact regions and a high resistivity region in the narrower portion of the trench extending therebetween. Thus a trench isolated resistively conductive element is provided by a method in which a single photoengraving step is required to define the trench. Conformal layers of first and second conductive layers with different resistivities are deposited within the trench. The conductive layers are self-aligned within the trench, so that larger amounts of the second conductive layer are required to fill wider portions of the trench with the lower resistivity material. Consequently after annealing to inter-diffuse elements of the two conductive layers, a conductive element is provided in which the resistivity may be controlled by shape of the trench. For example, the first conductive layer of a high resistivity material and the second conductive layer of lower resistivity material may comprise an undoped or lightly doped semiconductor and a relatively heavily doped semiconductor respectively. Advantageously, for example, semiconductor layers of polysilicon are provided by a known method of chemical vapour deposition. The first layer of polysilicon comprises undoped or very lightly doped polysilicon to provide a high resistivity layer. Then the second conductive layer is provided comprising heavily doped polysilicon, deposited by CVD with in situ doping. The semiconductor layers extending above the substrate surface are removed before annealing, leaving trenches of different widths filled with different amounts of doped and undoped polysilicon. Annealing is carried out in a suitable ambient, at a temperature and for a time sufficient to diffuse dopant from the heavily doped polysilicon layer into the underlying undoped or lightly doped polysilicon layer, while avoiding diffusion into and counterdoping of the surrounding structures, i.e. the underlying dielectric or substrate. Since the first layer of undoped polysilicon is conformal in the trench, the amount of heavily doped polysilicon required to fill the trench depends on the width of the trench, the wider contact regions requiring a larger amount of heavily doped polysilicon, and the narrow portion requiring a lesser amount, or none, of the heavily doped polysilicon. Thus a larger amount of dopant from the layer of heavily doped polysilicon is incorporated in the wider portion of the trench, and after annealing forms heavily doped conductive electrodes. The narrower trench region between the contact electrodes is filled by a relatively small amount of heavily doped polysilicon, incorporating a lesser amount of dopant, so that after annealing the conductive layer in the narrower trench region is relatively lightly doped, and a relatively high resistivity conductor is provided in the narrower portion of the trench between the conductive contact regions. Thus a trench isolated layer of polysilicon is provided in which the resistivity is inversely proportional to the width of the trench. To form a lower value resistor the narrower region of the trench is provided with a relatively large lateral dimension, and a greater amount of doped polysilicon is required to fill the trench. To form a higher value resistor required, the narrower portion may be sufficiently narrow to be filled by the first polysilicon layer only which may be undoped, or lightly doped. Thus, after removal of the polysilicon layers extending above the substrate surface, no heavily doped polysilicon is available to diffuse into this region. Thus, dopant from the heavily doped second polysilicon layer is diffused only into the end contact regions. According to another aspect of the present invention there is provided an integrated circuit including a plurality of multivalued resistors comprising: a substrate (32) for an integrated circuit having a planar surface having defined therein a plurality of trenches (42), each said trench having steep side walls and a bottom and comprising first and second end contact regions (44) of a specific lateral dimension and a portion (46) therebetween having a narrower lateral dimension, the plurality of trenches being provided with different narrower lateral dimensions; a conformal dielectric layer (50) extending over the side walls and bottom of each trench, and a conductive layer (70, 80) overlying the conformal dielectric layer and filling each trench; the conductive layer and the dielectric layer having planarised surfaces substantially coplanar with the substrate surface, the planarised surface area of the conductive layer in the end contact regions of each trench being sufficiently large for formation thereon of an electrical contact; the conductive layer comprising a doped semiconductor material, the dopant concentration being proportional to the lateral dimensions of that trench whereby each trench comprises a conductive layer of mixed composition having a low resistivity in said end contact regions and a high resistivity region in the narrower portion of the trench extending therebetween. Thus, a series of multi-valued resistors may be formed simultaneously in the same circuit, with the same process steps, by defining a series of trenches of different lateral dimensions. As a result of self-alignment of the deposited layers within the trench and subsequent doping of the contact regions and resistive regions by diffusion, the amount of dopant is controlled by the width of the trench. Consequently, the resistance value of a resistor is dependent on width of the narrower portion of the trench. Thus the resistance values are determined in the design layout stage. A single photoengraving step is required only for defining areas for etching the trenches of different widths for each value of resistance. Conductive contact regions are provided by more heavily doped, wider regions of the trench and the requirement for an additional masking step for an implant to define electrically conductive contact electrodes is avoided. The resulting resistive element is protected on by the dielectric layer forming the trench isolation and shielded by the substrate forming the sidewalls and bottom of the trench. A layer of dielectric may be formed during the anneal step or subsequently deposited overall to complete isolation of the resistive element on 4 sides, i.e. top bottom and sidewalls. Since the resistors are formed in the early stages of processing of an integrated circuit, another conductive layer may be provided over the resistive region after providing dielectric isolation over the conductive element, to provide a resistor shield on the top of the resistive portion. The resistor shield comprises for example a conductive layer of polysilicon which may also forming emitter or gate structures of transistors of the integrated circuit. The shield protects lightly doped resistive regions from process induced damage and traps which may create leakage paths or surface inversion, and degrade performance of high value resistors. If required for high resistivity gigaohm resistors, a potential may be applied on the shield in use of the structure, to improve reliability. Thus multivalued resistors for an integrated circuit are provided by resistive trench isolated regions including a resistively conductive layer having the resistivity determined by trench geometry. Thus, there is provided a method of forming a resistively conductive element for an integrated circuit, a method of forming multi-valued resistors for an integrated circuit, an integrated circuit including a plurality of multi-valued resistors, and an integrated circuit including a plurality of resistively conductive elements, in which the above mentioned problems are avoided or reduced. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, in which:- Figures 1A and 1B shows schematic diagrams of a conventional known type of prior art resistor structure for an integrated circuit: Figure 1a shows a cross-sectional view in the direction of arrow IB in Figure 1, through part of a semiconductor substrate wafer and Figure 1B shows a plan view of the surface of the resistor structure; Figure 2 shows a schematic plan view of part of an integrated circuit at an early stage of a process for forming resistor structures for an integrated circuit according to a first embodiment of the present invention; Figures 2A , Figure 2B and Figure 2C respectively show cross sectional views along arrows IIA, IIB and IIC in Figure 2; Figure 3 shows a plan view of the structure of Figure 2 at a later stage of a method of providing resistor structures according to the first embodiment; Figures 3A, Figure 3B and Figure 3C respectively show cross sectional views along arrows IIIA, IIIB and IIIC of Figure 3; Figure 4 to 7 show plan views of the structure at successive steps in the method of providing resistor structures according to the first embodiment; and Figures 4A to 4A, 4B to 7B and 4C to 7C show corresponding cross sectional views along corresponding arrows shown in Figures 4 to 7; and Figure 8 shows a cross sectional view through part of an integrated circuit comprising a resistor structure according to a second embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT In a method of providing a conventional known type of resistor structure 10 for an integrated circuit (IC) as shown schematically in Figure 1A and Figure 1B, a substrate for an integrated circuit is provided, in the form of a silicon wafer 12 part of which is shown in Figure 1A, on which is formed a layer 14 of a conventional dielectric isolation material, typically a field oxide comprising silicon dioxide. A layer 16 of polysilicon is deposited overall and patterned to define a resistor structure. The polysilicon layer is then p- or n- doped by ion implantation to provide a resistive portion 18 having a resistance in a desired range, and end regions 20 of the resistor structure are more heavily doped, if necessary, to provide conductive contact electrodes. Conductive terminals (not shown) are provided by a conventional metallization process. Thus two implants are required to selectively dope the end contact regions and the resistive portion respectively with different amounts of dopant. Resistors having different resistance values on the same substrate each require a different implant dose, and hence separate photoengraving and masking steps are required for each different implant. In a method of providing resistor structures according to a first embodiment of the present invention, a substrate for an integrated circuit is provided in the form of a P type, <100> semiconductor silicon wafer 32, as shown in Figures 2, 2A,2B and 2C, including a masking layer 34 provided on the planar substrate surface 36. The masking layer 34 may comprise for example, a single silicon oxide layer or preferably a composite multilayer structure as shown in Figure 2A. The composite masking layer 34 may be provided by a thin oxide layer 37, and a coating of a relatively hard masking layer 38, for example silicon nitride, which is deposited to serve as a chemical - mechanical polish stop layer, as will be described below. Then, a layer of another masking material 39, for example silicon dioxide, is grown or deposited thereon to serve as a trench etch mask. The masking layers 37, 38 and 39 are photoengraved, i.e. photo-lithographically patterned and etched, to expose regions 40 of the substrate surface for defining trenches. The exposed area 40 of the substrate surface 36 is etched by an anisotropic etching process known in the industry, to a predetermined depth to form a deep, steep-sided trench (Figure 3). In plan view, the trenches 42 (Figure 3) are elongated, and each have end regions 44 which are relatively wide and a narrower intermediate portion 46 extending between the end regions 44. As will be explained below, trenches for forming resistors of different values vary in the lateral dimension, i.e. width, of the narrower portion 46. The width of the narrower portion of trench is predetermined and is inversely proportional to the desired resistance value. After a conventional post trench-etch clean, e.g. in HF solution, a dielectric isolation layer 50, for example silicon dioxide, is provided overall. The dielectric isolation layer 50 thereby conformally lines sidewalls 52 and a bottom 54 of each trench, and leaves a cavity 60 within the trench (Figures 4,4A to 4C). The oxide layer 50 may be provided by a conventional method of thermal oxidation, deposition of oxide, or a composite process with a thermal oxidation step before or after deposition of an oxide layer. As an example, in a 0.8µm BiCMOS process, the oxide layer would typically be 0.5µm thick. A first conductive layer of a high resistivity material, 70, for example, of a layer of an undoped or lightly doped semiconductor, i.e. polysilcon, is deposited conformally overall by a LPCVD (low pressure CVD) method known in the industry (Figure 5). The layer of polysilicon is conformal and thickness of the polysilicon layer 70 is selected so that it only partially fills the end portions 44 of the trench 42 and leaves a cavity 74 which is filled by subsequently deposited layers.(Figure 5B). The narrowest trench region (Figure 5A) is completely filled by the first layer of semiconductor material. On the other hand, part 72 of the narrower portion 46 of the larger trench, shown in Figure 5C, also remains partially unfilled by the first polysilicon layer. Subsequently, a second conductive layer 80 having a lower resistivity is deposited conformally overall (Figures, 5, 5A to C). The second conductive layer comprises a heavily doped semiconductor, for example a layer of polysilicon 80 which is heavily phosphorus or boron doped, as is typically used in the industry. The doped polysilicon layer 80 is, for example, formed by a conventional method of polysilicon CVD with in situ doping. A conformal polysilicon layer 80 typically leaves a depression 82 near the centre of the trench 70, and the contour of this depression is dependent on the deposition thickness and trench width. However, the thickness of the second layer is sufficient (in this example about 350nm) that it completely fills the remaining cavity in the trench 70 above the substrate surface. Thus, the wider contact regions 44 of the trench are filled by the dielectric layer 50 and polysilicon layers 70 and 80. Each of these layers also extend over the planar surface of the masking layer 34 on the surface of the substrate 32 around the trench 42. The narrower portion 46 of the trench is filled by the first dielectric layer, the first polysilicon layer and a lesser amount or none of the second polysilicon layer (Figures 5A, 5B, 5C) depending on the width of the narrower portion. Parts of the dielectric layer, and the first and second semiconductor layers, and masking layer 39 which extend above the substrate surface are selectively removed, i.e. etched back, to leave trenches filled to a level coplanar with layer 38 of chemical mechanical polish resistant material formed on the substrate surface. The resulting structure comprises dielectric isolated trenches having end contact regions filled by an undoped first polysilicon layer and a doped second polysilicon layer, and a narrower region of each trench between the end contact regions filled by the undoped first polysilicon layer, and an amount of the doped second polysilicon layer which is dependent on the width of the narrower region of the trench. The narrowest trenches may be completely filled with the first layer of polysilicon only. Etching back is preferably performed by chemical mechanical polishing process to provide a fully planarized surface, the layer of silicon nitride layer 37 providing a suitable, relatively hard polish stop layer on the substrate surface. After selectivly removing the layers extending above the etch stop layer 37 on the silicon substrate surface, the structure is annealed. Annealing is carried out a temperature and for a time sufficient, and in a suitable ambient, to diffuse dopant from the doped polysilicon layer into the underlying undoped polysilicon layer only, to avoid counterdoping of the surrounding substrate. For example, annealing is carried out in an oxygen ambient at 850°C to 1000°C, which forms a SiO 2 layer on the exposed polysilicon and prevents outdiffusion of dopant. During annealing dopant diffuses from the heavily doped polysilicon layer into the first polysilicon layer thereby forms a conductive layer 90a, 90c, 92 (Figures 7, 7A, 7B, 7C). The conductive layer within each trench comprises polysilicon in which the doping in the wider end contact regions 92 is greater than the doping of the narrower portion (90a, 90c) of the trench extending in between. The width of the contact regions is sufficiently large that the amount of dopant incorporated in the end region provides a heavily doped, low resistivity contact electrode region (92). The narrower portion is of a sufficient width to incorporate a lesser amount of dopant, providing a resistive portion of the structure with a required resistance value (Figs 7A, 7C). The amount of dopant incorporated in the trench is proportional to the lateral dimension (width) of the trench There is no heavily doped polysilicon in the narrowest trench regions 90a Fig.7,7A. Thus there is no dopant available to diffuse during annealling. The resistivity of the undoped or lightly doped first polysilicon layer filling the narrow region determines the resistance of this region, thereby forming a high value resistor. Wider trench regions 90c, and the end contact regions 92, contain more of the second layer of doped polysilicon, and thus more dopant is available to diffuse, during annealling, into the underlying undoped or lightly doped first polysilicon layer. Diffusion of dopant from the more heavily doped polysilicon layer into the underlying polysilicon layer thus forms a region with a resistivity related to the width of the trench, to provide a lower value resistor. After annealing, a layer of dielectric, e.g. silicon dioxide may be provided over the polysilicon layer by a conventional method, i.e. either by thermal oxidation, or by deposition. Then, contacts are provided by conventional metallization steps, for example by a standard CMOS multilevel metal process. Thus the process allows for simultaneously forming a plurality of resistors of different values, using only one mask level to define a plurality of trenches of different lateral dimensions. The requirement for multiple photoengraving and implantation steps to form multi-valued resistors on an integrated circuit is completely avoided. Since each layer filling the trench is conformal, and thus, in effect, self-aligned within the trench, the structure and electrical characteristics of each resistor structure is dependent upon the geometry of the trench. The process uses a unconventional circuit design approach in which the resistivity value of a resistor is defined by the trench dimensions. Additional photo-lithographic steps are not required to define the contact electrode, and consequently a single planarization step only is required after filling the trench with a plurality of conductive and dielectric layers. The number of mask levels used for complex analog BiCMOS process can be reduced. Furthermore, the process allows for formation of resistive elements, or local interconnect conductors, at the initial stages of processing, while retaining substrate wafer planarity. Coplanar contacts are provided to both electrodes without topography related photoengraving problems. The resistor structure is naturally shielded on the sides and bottom of the trench by the substrate forming the trench sidewalls and bottom the trench. Extraneous effects due to charges along the top, sides or bottom of a conventional resistor structure formed by a known method are reduced or avoided. In a method of forming a resistively conductive element for an integrated circuit according to a second embodiment of the present invention, as shown in figure 8, steep-sided trenches are provided in the substrate 132, as described in the first embodiment, having wider contact regions and a relatively narrow portion extending in between. The trench is lined with a layer of dielectric 150. Conformal layers of a first conductive layer and a second conductive layer comprising undoped and doped polysilicon respectively are provided within the trench. After planarizing and annealing similarly as described in the first embodiment there is provided a conductive layer 190 having a resistive portion in the narrow portion of the trench having heavily doped contact regions 192. Subsequently, an dielectric layer 194, e.g. oxide, is grown or deposited on the polysilicon layer 190, followed by another layer of polysilicon 196, for example a deposited layer of about 0.35µm thick polysilicon. The latter may, for example, be a polysilicon layer which forms gate or emitter structures of transistors of the integrated circuit. The polysilicon cap 196 acts as a resistor shield for all subsequent oxide and metal deposition, silicidation, and etch steps, all of which include exposure to the resistor structure to a plasma ambient. A conventional three level metal interconnect is used to complete the structure and provides contacts 198 to the resistor contact regions and the polysilicon shield. Thus, the resistor is not only shielded by the susbtrate on the sides and bottom of the trench, a further polysilicon shield layer is provided on top of the resistive region. The shielded resistor structure is particularly applicable for providing high value resistors (gigaohm). The incorporation of shields early in the processing protects sensitive undoped or lightly doped polysilicon devices from damage, e.g. plasma radiation induced damage during etching, which lead to poor reproducibility or reliability in high value resistances. devices. Furthermore, in use of the resistor, the top polysilicon shield may function as a gate to which a potential may be provided for controlling induced charges which may otherwise tend to cause leakage paths in high value resistors. In other modifications of the embodiments of the invention, the dielectric layer of silicon dioxide is formed compositely by thermal oxidation following deposition. Alternatively, other known insulating materials are used instead of CVD silicon dioxide, for example, a layer of silicon nitride or silicon oxynitride formed by a known method of oxidation, thermal oxidation or an ONO (oxide-nitride-oxide composite) process, or a metal oxide such as tantalum pentoxide. The chemical-mechanical polish stop layer alterna - tively comprises other hard polish resistant materials, for example, silicon carbide. Since the polish stop material must be more polish resistant than the conductive or insula - ting layers, silicon carbide may be advantageous to improve polish selectivity. In the embodiment described above, the trench etch masking layer 39 is preferably removed during the chemical mechanical polishing step along with the overlying dielectric layer 50 which may comprise the same material, and the conductive layers extending above polish stop layer 38 on the substrate surface. Other conventional etch back methods for planar - ization, for example, reactive ion etching may be used. However, planarization by chemical-mechanical polishing is particularly advantageous in providing a fully planarized surface topography. In particular, coplanar contacts to two or more electrodes can then be made readily, thus simplifying subsequent process steps and reducing topography related photoengraving and etch problems in defining conductive interconnect structures, particulary for deep submicron (i.e.< 0.5µm) technology. It will be apparent from the embodiments described that other trench isolated resistively conductive elements may be provided within the scope of the invention by modifying or varying the process steps of the embodiments. Other ohmic circuit elements formed according to the method of the embodiment and having a controlled low resistivity include buried local interconnects conductors and DC conductive rails. A maskless process for forming buried isolated polysilicon fuses, for example, adapated from the first embodiment described above includes providing a highly resistive element of undoped or lightly doped polysilicon, and subsequently, after the step of etching back the structure level with the substrate surface surface, a thin conductive layer, e.g. of titanium silicide, is provided on the surface of highly resistive polysilicon in the narrow region of the trench. Incorporation of a resistively conductive structure in an integrated circuit is primarily at the design level rather than at the processing level. Additional layers or special layers are not required. Various IC device structures may be incorporated at an early stage of processing, without altering the baseline process technology. Thus complex analog BiCMOS circuits may be fabricated with a reduced number of mask levels and process steps, thus reducing processing costs.

Claims: A method of forming a resistive element for an integrated circuit. The method comprising: forming a steep sided trench (42) in a major surface of a semiconductor substrate (32) of an integrated circuit, the trench having first and second end contact regions (44) of a first lateral dimension and a narrower portion (46) extending therebetween; providing a conformal dielectric layer (50) over the sidewalls and bottom of the trench, the dielectric layer (50) lining the trench and leaving a cavity (60) within the trench; providing a conformal first conductive layer (70) of a high resistivity material overlying the dielectric layer (50) and of sufficient thickness to partially fill the end contact regions (44) and at least partially fill the narrower portion (46) of the trench; providing a second conductive layer (80) of a low resistivity material filling the end contact regions and any unfilled part (72) of the narrower portion of the trench; planarising the resulting structure by selectively removing those portions of the dielectric layer and the first (70) and second (80) conductive layers extending above the surface of the substrate; and annealing the structure for a sufficient time and at a temperature sufficient to cause interdiffusion of elements of the second conductive layer (80) of low resistivity material with elements of the first conductive layer (70) of high resistivity material, the first and second conductive layers thereby combining to form within the trench a conductive layer of mixed composition having a low resistivity in said end contact regions and a high resistivity region in the narrower portion of the trench extending therebetween. A method as claimed in claim 1, characterised in that the selective removal of the dielectric layer and the first and second conductive layers extending above the surface of the substrate comprises chemical mechanical polishing. A method as claimed in claim 1 or 2, characterised in that providing the first conductive layer of high resistivity material comprises providing a layer of semiconductor material; in that providing the second conductive layer of low resistivity material comprises providing a layer of heavily doped semiconductor material; and in that the step of annealing causes interdiffusion of dopant from the heavily doped low resistivity semiconductor material into the high resistivity semiconductor material, thereby forming low resistivity end contact regions comprising heavily doped semiconductor material and a high resistivity region within the narrower portion of the trench comprising less heavily doped semiconductor material. A method as claimed in claim 3, characterised in that providing the first conductive layer comprises chemical vapour deposition of polysilicon, and that providing the second conductive layer comprises chemical vapour deposition of in situ doped polysilicon. A method as claimed in claim 3 or 4, characterised in that the substrate is provided having a planar surface comprising a chemical-mechanical polish resistant layer. A method as claimed in any one of claims 1 to 5, characterised in that a plurality of multivalued resistors are provided by forming a plurality of steep sided trenches, the narrow portion of each said trench having a predetermined lateral dimension dependent on the required resistance value of the resistor to be formed therein, the resistivity value of the region within the narrow portion of each trench being inversely proportional to the predetermined lateral dimension of the narrow portion of that trench. A method as claimed in claim 6, characterised in that said step of planarizing the resulting structure provides contact areas to each said low resistivity end contact region and by a further step of providing electrical contacts thereto. An integrated circuit including a plurality of multivalued resistors comprising: a substrate (32) for an integrated circuit having a planar surface having defined therein a plurality of trenches (42), each said trench having steep side walls and a bottom and comprising first and second end contact regions (44) of a specific lateral dimension and a portion (46) therebetween having a narrower lateral dimension, the plurality of trenches being provided with different narrower lateral dimensions; a conformal dielectric layer (50) extending over the side walls and bottom of each trench, and a conductive layer (90a, 90c, 92) overlying the conformal dielectric layer and filling each trench; the conductive layer and the dielectric layer having planarised surfaces substantially coplanar with the substrate surface, the planarised surface area of the conductive layer in the end contact regions of each trench being sufficiently large for formation thereon of an electrical contact; the conductive layer comprising a doped semiconductor material, the dopant concentration being proportional to the lateral dimensions of that trench whereby each trench comprises a conductive layer (92) of mixed composition having a low resistivity in said end contact regions and a high resistivity region (90a, 90c) in the narrower portion of the trench extending therebetween. An integrated circuit as claimed in claim 8, characterised in that the conductive layer comprises a doped semiconductor material, and that the concentration of dopant within the conductive layer in the narrower portion of each trench is proportional to the lateral dimension of the narrower portion of that trench. An integrated circuit as claimed in claim 8, characterised in that the conductive layer comprises doped polysilicon comprising first and second conformal layers of polysilicon, there being an interface between the first and second conformal layers of polysilicon. An integrated circuit as claimed in claim 9 or 10, characterised in that the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride and silicon oxynitride.

Inventors: BOYD JOHN M, ELLUL JOSEPH P, TAY SING P, BOYD, JOHN M., ELLUL, JOSEPH P., TAY, SING P.
Applicants: NORTEL NETWORKS LTD, NORTEL NETWORKS LIMITED
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L27