AC/DC converter using a non-latch type switching device

Abstract: An AC/DC converter includes a rectifying circuit (D1), a main switching device constituted by an N-channel IGBT (QM1) or an N-channel FET (QM2), a control circuit (17), a booster circuit (18), and a series power supply circuit (11). The rectifying circuit (D1) rectifies a half wave of an input AC voltage (AC IN ). One end of the current path of the main switching device (QM1 or QM2) is supplied with a half-wave rectifying output from the rectifying circuit (D1). The control circuit (17) turns on the main switching device (QM1 or QM2) when a voltage between the gate and the other end of the main switching device (QM1 or QM2) exceeds a first level, and turns off the main switching device (QM1 or QM2) when the voltage exceeds a second level which is higher than the first level. The booster circuit (18) boosts the voltage between the gate and the other end of the main switching device (QM1 or QM2) to a level which is higher than the second level when the voltage exceeds the first level. The series power supply circuit (11) has an input terminal to which the other end of the current path of the main switching device (QM1 or QM2) is connected, and outputs a DC voltage (V OUT ).

Description: The present invention relates to an AC/DC converter for rectifying a commercial AC power supply voltage or converting a commercial AC power supply voltage to a stable DC voltage and, in particular, to an AC/DC converter for use in a transformerless power supply of the industrial-consumer field. Document EP-A-0 327 174 A1 describes a circuit arrangement for deriving a direct voltage from an alternating voltage, particularly the mains alterning voltage, said circuit arrangement comprising: a switching transistor whose main current path is connected via a rectifier diode between the input and the output and whose control electrode is controlled by a thyristor. Further, the gate electrode of the thyristor is connected via a diac to a time-determining circuit comprising a series arrangement of a resistor and a capacitor, whilst a diode is arranged across the capacitor in such a way that this diode conducts during the periods when the rectifier diode is blocked. Document EP-A-0 500 113 A2 relates to a power-supply unit. In an electric appliance including an electronic circuit, step-down of the commercial power source voltage is carried out by taking electric power in a predetermined region of a phase-angel from the commercial power source only with an electronic circuit without use of a transformer. HV-2405E of HARRIS is placed on the market as an AC/DC converter for use in a transformerless power supply. Its detailed specifications and circuit arrangement are shown in File Number 2487 of the brochure of HV-2405E. The AC/DC converter of HV-2405E includes a double-gate thyristor serving as a main switching device. A commercial AC power supply voltage (hereinafter referred to as AC power supply voltage) is applied to the double-gate thyristor. When the AC power supply voltage exceeds a predetermined value of about 3 V F , the thyristor is turned on, and this turn-on state is maintained during a period of time corresponding to a positive sinusoidal half wave of the AC power supply voltage. During a period of time corresponding to a negative sinusoidal half wave thereof, the current flowing through the thyristor is smaller than a holding current, and the thyristor is turned off, thereby maintaining this turn-off state. Since, however, the thyristor serving as a main switching device of the AC/DC converter is of a latch type, there is a possibility that the AC/DC converter cannot be regulated if a current flowing through a load is increased suddenly at a frequency which is higher than a commercial frequency. More specifically, since the thyristor can be turned on only once during the period of time corresponding to the positive sinusoidal half wave, if the load varies (becomes great) immediately after the thyristor is turned off, an output voltage of the AC/DC converter will be decreased, even though it is backed up by electric charges of a capacitor. The decrease in the output voltage prevents the AC/DC converter from being regulated. It is accordingly an object of the present invention to provide an AC/DC converter which is resistible to a sudden increase in current flowing through a load to be driven. The above object is attained by providing an AC/DC converter as set out in independent claim 1. In the AC/DC converter of the invention the main switching device can be turned on at the rise and fall of the sinusoidal half wave of an AC voltage using both the control circuit and booster circuit, since the main switching device is constituted by a non-latch type N-channel FET or N-channel IGBT. Even though a large amount of current suddenly flows through a load to be driven, the output voltage can be prevented from being dropped, as compared with a conventional AC/DC converter using a latch-type device as a main switching device. Therefore, the AC/DC converter of the present invention is considerably resistible to a sudden increase in the current flowing through the load to be driven. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram showing an AC/DC converter according to a first embodiment of the present invention; FIG. 2 is a view of a waveform for explaining an operation of the AC/DC converter of FIG. 1 which is in a steady state; FIG. 3A is a view showing a waveform for explaining a usable portion of AC voltage of the AC/DC converter of FIG. 1; FIG. 3B is a view showing a waveform for explaining a usable portion of AC voltage of a conventional AC/DC converter; FIG. 4 is a circuit diagram showing an AC/DC converter according to a second embodiment of the present invention; FIG. 5 is a circuit diagram showing an AC/DC converter according to a third embodiment of the present invention; FIG. 6 is a circuit diagram showing an AC/DC converter according to a fourth embodiment of the present invention; FIG. 7 is a circuit diagram showing an AC/DC converter according to a fifth embodiment of the present invention; FIG. 8 is a circuit diagram showing an AC/DC converter according to a sixth embodiment of the present invention; FIG. 9 is a circuit diagram showing an AC/DC converter according to a seventh embodiment of the present invention; and FIG. 10 is a circuit diagram showing an AC/DC converter according to an eighth embodiment of the present invention. FIG. 1 shows an AC/DC converter according to a first embodiment of the present invention. The AC/DC converter includes resistors R6 to R11, diodes D1 to D4, NPN bipolar transistors Q9 and Q10, Zener diodes DZ2 to DZ5, an N-channel IGBT QM1 serving as a main switching device, a capacitor CB, and a series power supply circuit 11. The diode D1 is used to rectify a half wave of an AC voltage. The anode of the diode D1 is connected to a first power supply terminal 12 and the cathode thereof is connected to one end of each of the resistors R6 and R7 and to the collector of the IGBT QM1. The cathode-to-anode paths of the Zener diodes DZ2 and DZ3 and the resistor R8 are connected in series between the other end of the resistor R6 and a second power supply terminal 13. The anode-to-cathode path of the diode D3 is connected between the other end of the resistor R7 and the gate of the IGBT QM1. The resistor R9 is connected between the gate of the IGBT QM1 and an inhibit terminal 14 to protect the gate. The cathode-to-anode paths of the Zener diodes DZ4 and DZ5, the collector-to-emitter path of the transistor Q9, and the resistor R10 are connected in series between the gate of the IGBT QM1 and the second power supply terminal 13. The base of the transistor Q9 is connected to a connecting point of the Zener diode DZ3 and resistor R8, and the emitter thereof is connected to the base of the transistor Q10. The resistors R6 to R8 and R10, diode D3, Zener diodes DZ2 to DZ5, and transistor Q9 constitute a control circuit 17 for turning on/turning off the IGBT QM1. The collector of the transistor Q10 is connected to that of the transistor Q9, and the emitter thereof is connected to the second power supply terminal 13. A capacitor CB is connected between the collector of the transistor Q10 and the gate of the IGBT QM1. The resistor R11 and the anode-to-cathode path of the diode D4 are connected in parallel between the collector of the transistor Q10 and a capacitor connecting terminal 16. The transistor Q10, capacitor CB, resistor R11, and diode D4 constitute a booster circuit 18 for boosting a gate-to-emitter voltage of the IGBT QM1. The anode of the diode D2 is connected to the emitter of the IGBT QM1, and the cathode thereof is connected to the connecting terminal 16. The input terminal of the series power supply circuit 11 is connected to the terminal 16, and the second power supply terminal 13 and output terminal 15 are connected to the circuit 11. An AC power supply AC IN and a resistor R1 are externally connected in series between the first and second power supply terminals 12 and 13. The resistor R1 is used to restrict the peak of the main current. Further, a capacitor C1 is externally connected between the terminals 12 and 13, a capacitor C2 is externally connected between the terminals 14 and 13, and a capacitor C3 is connected between the terminals 16 and 13. The capacitor C3 serves to smooth the input voltage of the series power supply circuit 11. When the IGBT QM1 is turned on, the capacitor C3 is charged and bootstraps the gate of the IGBT QM1 through the capacitor CB. The diode D2 is formed to prevent a current from flowing reversely from the capacitor C3 toward the control circuit 17. A load R L (which is shown equivalently as a resistor R L in FIG. 1) is connected between the output terminal 15 and second power supply terminal 13. An operation of the AC/DC converter having the above circuit arrangement, will now be described. In the initial state where an AC power supply voltage is applied to the AC/DC converter, if both the interelectrode voltages of the capacitors CB and C3 are 0V, a current flows from the resistor R1 to the capacitor C3 through the diode D1, resistor R7, diode D3, capacitor CB, and resistor R11 in this order, thereby charging the capacitor C3. Assume that the capacitance of the capacitor CB is represented by C B and that of the capacitor C3 is represented by C 3 . Under the condition of C B << C 3 , if the voltage of the capacitor CB increases greatly and the gate-to-emitter voltage of the IGBT QM1 exceeds a threshold voltage (V th ), the IGBT QM1 is turned on to charge the capacitor C3 quickly. However, the interelectrode voltage of the capacitor CB is clamped by the sum of Zener voltages of the Zener diodes DZ4 and DZ5, and this clamped voltage corresponds to the maximum charging voltage. The steady state of the AC/DC converter will now be described, with reference to the waveform shown in FIG. 2. For easy understanding of a bootstrap operation, the steady state during a period of time T/2 from the turn-off of the IGBT QM1 until the end of the positive sinusoidal half wave, will be described. When the cathode voltage V D1K of the diode D1 exceeds a value expressed by the following equation (1), the IGBT QM1 is turned off. V D1K = 2 * (r 6 /r 8 + 1) * V BE9 + V DZ2 + V DZ3 where r 6 and r 8 are resistances of the resistors R6 and R8, V BE9 is a base-to-emitter voltage of the transistor Q9, and V DZ2 and V DZ3 are Zener voltages of the Zener diodes DZ2 and DZ3, respectively. More specifically, if the above equation is satisfied, the transistors Q9 and Q10 are turned on, the gate voltage of the IGBT QM1 is dropped, the emitter voltage thereof is fixed to a low value, and the gate-to-emitter voltage thereof is lowered. Thus, the IGBT QM1 is completely turned off. V DZ4 + V DZ5 << 2 * (r 6 /r 8 + 1 ) * V BE9 + V DZ2 + DZ3 where V DZ4 and V DZ5 are Zener voltages of the Zener diodes DZ4 and DZ5. When the above relationship (2) is satisfied, the IGBT QM1 cannot be completely turned off since the collector of the transistor Q10 is connected as shown in FIG. 1. This can be understood from the fact that the IGBT QM1 operates as an emitter follower since the gate potential is lowered when the IGBT QM1 is turned off. However, no problems arise if the resistance of the resistor R11 is set to a proper value. Then the drain current ID is given by the following equation (3) if the resistance of the resistor R11 is represented by r 11 . ID = (V DZ4 + V DZ5 - V th - V D2 )/r 11 If V DZ4 = V DZ5 = 6V , r 11 = 10 KΩ , and V th = 2V , the drain current ID is in the order of mA, and a power loss can be almost disregarded. FIG. 2 is a view of a waveform for explaining an operation of the AC/DC converter of FIG. 1 which is in a steady state. During a period of time corresponding to the positive sinusoidal half wave during which the IGBT QM1 is turned off, the capacitor CB maintains an interelectrode voltage of V DZ4 + V DZ5 and is preparing for turning on the IGBT QM1 during the next period of time. If, at the beginning of the next positive sinusoidal half wave, the gate of the IGBT QM1 is bootstrapped and the cathode voltage V D1K of the diode D1 exceeds a predetermined value of V C3-1 (V D1K ≧ V FD2 + V C3 = a condition for causing the diode D2 to be biased forwardly) , the collector current of the IGBT QM1 starts to flow. FIG. 3A shows a usable portion of AC voltage of the AC/DC converter of FIG. 1, and FIG. 3B shows a usable portion of AC voltage of a conventional AC/DC converter. The main switching device is turned on in the hatched areas of FIGS. 3A and 3B. In the first embodiment of the present invention, since the IGBT QM1, which is a non-latch type switching device is employed as the main switching device, it can be turned on at two positions of the positive sinusoidal half wave, and the load current capacity can be increased accordingly. Therefore, according to the present invention, the level of output voltage V OUT can be prevented from decreasing even if the current flowing through the load R L is increased rapidly, and the capacitance of the capacity C3 necessary for obtaining the same current can be reduced. FIGS. 4 and 5 are circuit diagrams showing AC/DC converters according to the second and third embodiment of the present invention, respectively. These converters are so arranged that the IGBT QM1 of FIG. 1 is completely turned off. The circuit arrangement of FIG. 4 is the same as that of FIG. 1, except that the collector of the transistor Q10 is connected to the gate of the IGBT QM1. In the circuit of FIG. 5, a resistor R14 and a PNP bipolar transistor Q12 are added to the circuit of FIG. 1. One end of the resistor R14 is connected to the collector of the transistor Q10. The emitter of the transistor Q12 is connected to the gate of the IGBT QM1, the collector thereof is connected to the cathode of the diode D2, and the base thereof is connected to the other end of the resistor R14. The above circuit arrangements shown in FIGS. 4 and 5 allow the IGBT QM1 to be completely turned off and also allows the drain current ID (explained above in relation to the circuit of FIG. 1) to be decreased to a low value of leak current or the like. FIG. 6 is a circuit diagram showing an AC/DC converter according to a fourth embodiment of the present invention, in which the output voltage V OUT is fed back to the cathode side of the diode D1. More specifically, the base of the PNP bipolar transistor Q11 is connected to the output terminal 15, and the collector thereof is connected to both the base of the transistor Q10 and one end of the resistor R10. Furthermore, the anode of the diode D5 is connected to that of the Zener diode DZ2, and a resistor R12 is connected between the cathode of the diode D5 and the base of the transistor Q11. The emitter of the transistor Q11 is connected to a connecting point of the diode D5 and resistor R12. Except for the above, the circuit arrangement of FIG. 6 is the same as that of FIG. 1. In FIG. 6, the same elements as those in FIG. 1 are denoted by the same reference numerals, and their detailed descriptions are omitted. According to the circuit arrangement of FIG. 6, if the following equation (4) is satisfied, the IGBT QM1 is turned on. V D1K ≦ V OUT + (1 + r 6 /r 12 ) * V BE11 + V DZ2 + V D5 where r 12 is the resistance of the resistor R12, V BE11 is the base-to-emitter voltage of the transistor Q11, and V D5 is the forward voltage of the diode D5. When the output voltage V OUT changes, a voltage V C3-2 (= a voltage between terminals of the capacitor C3) for causing the IGBT QM1 to be turned off as expressed by the above equation (4), changes accordingly. It is thus unnecessary to preset the voltage V C3-2 . In other words, in the circuit arrangements shown in FIGS. 1, 4 and 5, the number of series-connected Zener diodes (DZ2, DZ3) and the ratio of the resistance of resistor R6 to that of resistor R8 have to be adjusted in accordance with the line-up (level) of the output voltage V OUT , and the voltage V C3-2 also has to be set using an AL master slice approach or the like. However, this adjustment or setting is not required in the circuit arrangement shown in FIG. 6. FIG. 7 is a circuit diagram showing an AC/DC converter according to a fifth embodiment of the present invention, which is so arranged that the IGBT QM1 shown in FIG. 6 can be completely turned off. The circuit of FIG. 7 is the same as that of FIG. 6, except that the collector of the transistor Q10 is connected to the gate of the IGBT QM1. Like the circuit arrangements of the second and third embodiments, the circuit arrangement of FIG. 7 allows the IGBT QM1 to be completely turned off and also allows the drain current ID to be decreased to a low value of leak current or the like. FIG. 8 is a circuit diagram showing an AC/DC converter according to a sixth embodiment of the present invention. In this converter, an N-channel FET (MOSFET) QM2 is used as a main switching device, and the constitutions of the control circuit 17 and booster circuit 18 are different from those in the above-described embodiments. More specifically, in the circuit arrangement shown in FIG. 8, the anode of the diode D1 for rectifying a half wave of an AC voltage is connected to the first power supply terminal 12, and the cathode thereof is connected to one end of each of the resistors R6 and R7 and to the drain of the MOSFET QM2. A resistor R13 of high resistance is connected between the anode and cathode of the diode D1 and in parallel to the diode D1. The anode-to-cathode paths of the diode D6 and Zener diodes DZ2 and DZ3, and the resistor R8 are connected in series between the other end of the resistor R6 and the power supply terminal 13. The anode-to-cathode path of the diode D3 is connected between the other end of the resistor R7 and the gate of the MOSFET QM2. The resistor R9 is connected between the gate of the MOSFET QM2 and the inhibit terminal 14 to protect the gate of the MOSFET QM2. The collector-to-emitter path of the transistor Q9 is connected between the gate of the MOSFET QM2 and the power supply terminal 13, and the base of the transistor Q9 is connected to the connecting point of the Zener diode DZ3 and resistor R8. The resistors R6 to R8, diodes D3 and D6, Zener diodes DZ2 and DZ3, and transistor Q9 constitute a control circuit 17 serving to turn on/turn off the MOSFET QM2. The anode-to-cathode path of the diode D7 is connected between the emitter and collector of the transistor Q9. The anode-to-cathode path of each of the Zener diodes DZ5 and DZ4 are connected between the source and gate of the MOSFET QM2. In FIG. 8, DSD indicates a parasitic diode of the MOSFET QM2, and Cgd denotes a parasitic capacitance between the gate and drain of the MOSFET QM2. The diode D7, Zener diodes DZ4 and DZ5, parasitic diode DSD, and parasitic capacitance Cgd constitute a booster circuit 18. The anode of the diode D2 is connected to the source of the MOSFET QM2, and the cathode thereof is connected to the capacitor connecting terminal 16. The input terminal of the series power supply circuit 11 is connected to the terminal 16, and the power supply terminal 13 and output terminal 15 are connected to the circuit 11. The AC power supply AC IN and resistor R1 are externally connected in series between the power supply terminals 12 and 13, as in the first to fifth embodiments. A capacitor C2 is externally connected between the terminals 13 and 14, while a capacitor C3 is externally connected between the terminals 13 and 16. Further, a resistor R L is connected between the terminals 13 and 15. In the foregoing circuit arrangement shown in FIG. 8, if the input AC voltage V IN has a value expressed by the following equation (5) during a period of time from the turn-on of the MOSFET QM2 until the end of the positive sinusoidal half wave, the current flows through the diode D1, resistor R6, diode D6, Zener diodes DZ2 and DZ3, and resistor R8. The transistor Q9 is thus turned on, and the gate potential of the MOSFET QM2 is lowered to a GND level and turned off. V IN = (1 + r 6 /r 8 )* V BE9 + V D6 + V DZ2 + V DZ3 + V D1 If the input AC voltage V IN becomes negative, the current flows through the diode D7, Zener diodes DZ4 and DZ5, parasitic diode DSD, and resistor R13. At the same time, electric charges for rendering the gate and drain of the MOSFET QM2 positive and negative, respectively, are stored in the parasitic capacitance Cgd, and their voltage amounts to a value of V DZ4 + V DZ5 . This voltage is sufficient for turning on the MOSFET QM2 and is maintained during a period of time of the negative input AC voltage. The AC voltage gradually increases from 0V, and the capacitor C3 starts to be charged when the diode D2 is biased forwardly. Moreover, if the AC voltage increases and exceeds the voltage level given by the above equation (5), the MOSFET QM2 is turned off. This operation is repeated. The resistor R7 and diode D3 apply the initial trigger to the MOSFET QM2, and the diode D6 prevents the base-to-emitter path of the transistor Q9 from being biased reversely. The diode D3 prevents the charges stored in the gate of the MOSFET QM2 from flowing to the drain thereof or the resistor R13 through the resistor R7. As described above, in the circuit shown in FIG. 8, the parasitic capacitance Cgd of the MOSFET QM2 is actively utilized. FIG. 9 is a circuit diagram showing an AC/DC converter according to a seventh embodiment of the present invention. The circuit of FIG. 9 differs from that of FIG. 8 in a loop for charging the parasitic capacitance Cgd. More specifically, in FIG. 9, the base of the transistor Q9 is connected to a connecting point of the Zener diode DZ3 and resistor R8, the emitter thereof is connected to the power supply terminal 13, and the collector thereof is connected to one end of the resistor R14. The base of the transistor Q12 is connected to the other end of the resistor R14, the emitter thereof is connected to the gate of the MOSFET QM2, and the collector thereof is connected to the capacitor connecting terminal 16. The anode of the diode D7 is connected to the collector of the transistor Q12, and the cathode thereof is connected to the emitter of the transistor Q12. The resistor R13 of high resistance is connected between the cathode of the diode D1 and the power supply terminal 13. Except for the above, the circuit arrangement of FIG. 9 is the same as that of FIG. 8. In the circuit arrangement shown in FIG. 9, if the AC power supply voltage AC IN has a value expressed by the above equation (5) during a period of time from the turn-on of the MOSFET QM2 until the end of the positive sinusoidal half wave, the current flows through the diode D1, resistor R6, diode D6, Zener diodes DZ2 and DZ3, and resistor R8. The transistors Q9 and Q12 are therefore turned on, and the gate potential of the MOSFET QM2 is lowered to a GND level, thus turning off the MOSFET QM2. If the AC power supply voltage AC IN becomes negative, the current is generated from the capacitor C3 serving as a power source and flows through the diode D7, Zener diodes DZ4 and DZ5, parasitic diode DSD, and resistor R13 of high resistance. At the same time, electric charges for rendering the gate and drain of the MOSFET QM2 positive and negative, respectively, are stored in the parasitic capacitance Cgd, and their voltage amounts to a value of V DZ4 + V DZ5 . This voltage is sufficient for turning on the MOSFET QM2. Except for the above, the circuit of FIG. 9 is basically the same as that of FIG. 6, and creates substantially the same advantage. FIG. 10 is a circuit diagram showing an AC/DC converter according to an eighth embodiment of the present invention. The circuit of FIG. 10 differs from that of FIG. 8 in that the output voltage V OUT is fed back to the cathode side of the diode D1. More specifically, in FIG. 10, the Zener diode DZ3 of FIG. 8 is replaced with a PNP bipolar transistor Q11 and a resistor R12. The emitter of the transistor Q11 is connected to the anode of the Zener diode DZ2, the collector thereof is connected to one end of the resistor R8 and the base of the transistor Q9, and the base thereof is connected to the output terminal 15. The resistor R12 is connected between the base and emitter of the transistor Q11. In the circuit arrangement shown in FIG. 10, the input voltage V IN for causing the MOSFET QM2 to be turned off, is given by the following equation (6). V IN = V OUT + (1 + r 6 /r 12 ) * V BE11 + V D6 + V DZ2 According to the circuit arrangement shown in FIG. 10, the voltage for causing the MOSFET QM2 to be turned off, need not be preset in order to change the output voltage, since it varies with the output voltage. The circuit of FIG. 10 is the same as that of the sixth embodiment (FIG. 8) in basic operation, except for the above, and produces the same advantage obtained.

Claims: An AC/DC converter for converting an AC voltage to a DC voltage and driving a load, comprising: rectifying means (D1) for rectifying a half-wave of an input AC voltage, a main switching device having a unidirectional current path, one end of which is supplied with a half-wave rectifying output of said rectifying means (D1), a series power supply circuit (11) for receiving an output from the other end of the current path of said main switching device, and outputting a DC voltage (V OUT ), control means (17) for turning on said main switching device when a voltage between a gate of said main switching device and the other end of the current path exceeds a first level, and for turning off said main switching device when a voltage between the gate of said switching means and the other end of the current path exceeds a second level which is hither than the first level; characterized in that said main switching device includes either an N-channel IGBT (OM1) or an N-channel FET (QM2), and a booster means (18) is further provided comprising capacitor means (CB, Ggd) connected between the gate of said main switching device and the other end of said current path and comprising switching means for charging the capacitor means; said capacitor means bootstraps the gate voltage of said main switching device when said main switching device is in an on-state. The AC/DC converter according to claim 1, characterized by further comprising feedback means for feeding the DC voltage (V OUT ) output from said series power supply circuit (11) back to a control termnal of said rectifying means (D1, R 13) to vary the second level in accordance with a level of the DC voltage (V OUT ). The AC/DC converter according to claim 1, characterized in that said rectifying means includes a diode (D19 whose anode is connected to a first power supply terminal (12) and whose cathode is connected to the one end of the current path of said N-channel IGBT (QM1). The AC/DC converter according to claim 1, characterized by further comprising a diode (D2) whose anode is connected to the other end of the current path of said N-channel IGBT (QM1) and whose cathode is connected to an input terminal of said series power supply circuit (11). The AC/DC converter according to claim 1, wherein said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying means (D1); a first Zener diode (DZ2) whose cathode is connected to other end of said first resistor (R6); a second Zener diode (DZ3) whose cathode is connected to an anode of said first Zener diode (DZ2); a second resistor (R8) connected between an anode of said second Zener diode (DZ3) and a second power supply terminal (13); a third resistor (R7) one end of which is connected to the output terminal of said rectifying means (D1); a first diode (D3) whose anode is connected to other end of said third resistor (R7) and whose cathode is connected to the gate of said N-channel IGBT (QM1); a third Zener diode (DZ4) whose cathode is connected to the gate of said N-channel IGBT (QM1); a fourth Zener diode (DZ5) whose cathode is connected to an anode of said third Zener diode (DZ4); a first transistor (Q9) having a current path one end of which is connected to an anode of said fourth Zener diode (DZ5), and having a control terminal connected to the anode of said second Zener diode (DZ3); and a fourth resistor (R10) connected between the other end of the current path of said first transistor (Q9) and said second power supply terminal (13). The AC/DC converter according to claim 5, characterized in that said booster means (18) includes: a capacitor (CB) having one electrode connected to the gate of said N-channel IGBT (QM1) and other electrode connected to the anode of said fourth Zener diode (DZ5); a second transistor (Q10) having a current path one end of which is connected to the anode of said fourth Zener diode (DZ5) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to the other end of the current path of said first transistor (Q9); a fifth resistor (R11) one end of which is connected to the one end of the current path of said second transistor (Q10) and other end of which is connected to an input terminal of said series power supply circuit (11); and a second diode (D4) whose anode is connected to the one end of the current path of said second transistor (Q10) and whose cathode is connected to the input terminal of said series power supply circuit (11). The AC/DC converter according to claim 5, wherein said booster means (18) includes: a capacitor (CB) having one electrode connected to the gate of said N-channel IGBT (QM1) and other electrode connected to the anode of said fourth Zener diode (DZ5); a second transistor (Q10) having a current path one end of which is connected to the gate of said N-channel IGBT (QM1) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to the other end of the current path of said first transistor (Q9); a fifth resistor (R11) one end of which is connected to the one end of the current path of said first transistor (Q9) and other end of which is connected to an input terminal of said series power supply circuit (11); and a second diode (D4) whose anode is connected to the one end of the current path of said first transistor (Q9) and whose cathode is connected to the input terminal of said series power supply circuit (11). The AC/DC converter according to claim 5, characterized in that said booster means (18) includes: a capacitor (CB) having one electrode connected to the gate of said N-channel IGBT (QM1) and other electrode connected to the anode of said fourth Zener diode (DZ5); a second transistor (Q12) having a current path one end of which is connected to the gate of said N-channel IGBT (QM1) and other end of which is connected to an input terminal of said series power supply circuit (11), and having a control terminal connected to the other electrode of said capacitor (CB), a polarity of said second transistor (Q12) being opposite to a polarity of said first transistor (Q9); a fifth resistor (R14) one end of which is connected to the control terminal of said second transistor (Q12); a third transistor (Q10) having a current path one end of which is connected to other end of said fifth resistor (R14) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to other end of the current path of said first transistor (Q9), a polarity of said third transistor (Q10) being equal to a polarity of said first transistor (Q9); a sixth resistor (R11) one end of which is connected to the other electrode of said capacitor (CB) and other end of which is connected to the input terminal of said series power supply circuit (11); and a second diode (D4) whose anode is connected to the other end of said capacitor (CB) and whose cathode is connected to the input terminal of said series power supply circuit (11). The AC/DC converter according to claim 1, characterized in that said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying means (D1); a first Zener diode (DZ2) whose cathode is connected to other end of said first resistor (R6); a first diode (D5) whose anode is connected to an anode of said first Zener diode (DZ2); a first transistor (Q11) of a first polarity having a current path one end of which is connected to a cathode of said first diode (D5) and having a control terminal connected to an output terminal (15); a second resistor (R12) connected between the one end of the current path of said first transistor (Q11) and the control terminal; a third resistor (13) connected between other end of the current path of said first transistor (Q11) and a second power supply terminal (13); a fourth resistor (R7) one end of which is connected to the output terminal of said rectifying means (D1); a second diode (D3) whose anode is connected to other end of said fourth resistor (R7) and whose cathode is connected to a gate of said N-channel IGBT (QM1); a second Zener diode (DZ4) whose cathode is connected to the gate of said N-channel IGBT (QM1); a third Zener diode (DZ5) whose cathode is connected to an anode of said second Zener diode (DZ4); and a second transistor (Q12) of a second polarity having a current path one end of which is connected to an anode of said third Zener diode (DZ5) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to the other end of the current path of said first transistor (Q11), and said booster means (18) includes: a capacitor (CB) one electrode of which is connected to the gate of said N-channel IGBT (QM1) and other electrode of which is connected to the anode of said third Zener diode (DZ5); a fifth resistor (R11) one end of which is connected to the one end of the current path of said second transistor (Q10) and other end of which is connected to the input terminal of said series power supply circuit (11); and a third diode (D4) whose anode is connected to the one end of the current path of said second transistor (Q10) and whose cathode is connected to the input terminal of said series power supply circuit (11). The AC/DC converter according to claim 1, characterized in that said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying means (D1); a first Zener diode (DZ2) whose cathode is connected to other end of said first resistor (R6); a first diode (D5) whose anode is connected to an anode of said first Zener diode (DZ2); a first transistor (Q11) of a first polarity having a current path one end of which is connected to a cathode of said first diode (D5) and having a control terminal connected to an output terminal (15); a second resistor (R12) connected between the one end of the current path of said first transistor (Q11) and the control terminal; a third resistor (R13) connected between other end of the current path of said first transistor (Q11) and a second power supply terminal (13); a fourth resistor (R7) one end of which is connected to the output terminal of said rectifying means; a second diode (D3) whose anode is connected to other end of said fourth resistor (R7) and whose cathode is connected to the gate of said N-channel IGBT (QM1); a second Zener diode (DZ4) whose cathode is connected to the gate of said N-channel IGBT (QM1); a third Zener diode (DZ5) whose cathode is connected to an anode of said second Zener diode (DZ4); and a second transistor (Q9) of a second polarity having a current path one end of which is connected to the gate of said N-channel IGBT (QM1) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to the other end of the current path of said first transistor (Q11), and said booster means (18) includes: a capacitor (CB) one electrode of which is connected to the gate of said N-channel IGBT (QM1) and other electrode of which is connected to the anode of said third Zener diode (DZ5); a fifth resistor (R11) one end of which is connected to the anode of said third Zener diode (DZ5) and other end of which is connected to the input terminal of said series power supply circuit (11); and a third diode (D4) whose anode is connected to the anode of said third Zener diode (DZ5) and whose cathode is connected to the input terminal of said series power supply circuit (11). The AC/DC converter according to claim 1, characterized in that said rectifying means includes a diode (D1) whose anode is connected to a first power supply terminal (12) and whose cathode is connected to the one end of the current path of said N-channel FET (QM29, and a resistor (R13) connected between the anode of said diode (D1) an the cathode thereof. The AC/DC converter according to claim 1, wherein said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying menas (D1, R13); a first diode (D6) whose anode is connected to other end of said first resistor (R6); a first Zener diode (DZ2) whose cathode is connected to a cathode of said first diode (D6); a second Zener diode (DZ3) whose cathode is connected to an anode of said second Zener diode (DZ3); a second resistor (R8) connected between an anode of said second Zener diode (DZ3) and a second power supply terminal (13); a third resistor (R7) one end of which is connected to the output terminal of said rectifying means (D1, R13); a second diode (D3) whose anode is connected to other end of said third resistor (R7) and whose cathode is connected to the gate of said N-channel FET (QM2); and a transistor (Q9) having a current path one end of which is connected to the gate of said N-channel FET (QM2) and other end of which is connected to said second power supply terminal (13), and having a control terminal connected to the anode of said second Zener diode (DZ3), and said booster means (18) includes: a third diode (D7) whose cathode is connected to the one end of the current path of said transistor (Q9) and whose anode is connected to the other end of the current path of said transistor (Q9); a third Zener diode (DZ4) whose cathode is connected to the one end of the current path of said transistor (Q9); a fourth Zener diode (DZ5) whose cathode is connected to an anode of said third Zener diode (DZ4) and whose anode is connected to the other end of the current path of said N-channel FET (QM2); a parasitic diode (DSD) of said N-channel FET (QM2); and a parasitic capacitance (Cgd) formed between the gate of said N-channel FET (QM2) and the one end of the current path of said N-channel FET (QM2). The AC/DC converter according to claim 1, characterized in that said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying means (D1, R13); a first diode (D6) whose anode is connected to other end of said first resistor (R6); a first Zener diode (DZ2) whose cathode is connected to a cathode of said first diode (D6); a first transistor (Q11) of a first polarity having a current path one end of which is connected to an anode of said first Zener diode (DZ2) and having a control terminal connected to an output terminal (15); a second resistor (R12) connected between the one end of the current path of said first transistor (Q11) and the control terminal thereof; a third resistor (R8) connected between other end of the current path of said first transistor (Q11) and a second power supply terminal (13); a fourth resistor (R7) one end of which is connected to the output terminal of said rectifying means (D1, R13); a second diode (D3) whose anode is connected to other end of said fourth resistor (R7) and whose cathode is connected to the gate of said N-channel FET (QM2); and a second transistor (Q9) of a second polarity having a current path one end of which is connected to the gate of said N-channel FET (QM2) and other end of which is connected to the second power supply terminal (13), and having a control terminal connected to the other end of the current path of said first transistor (Q11), and said booster means (18) includes: a third diode (D7) whose cathode is connected to the one end of the current path of said second transistor (Q9) and whose anode is connected to the other end of the current path of said second transistor (Q9); a third Zener diode (DZ4) whose cathode is connected to the one end of the current path of said second transistor (Q9) ; a fourth Zener diode (DZS) whose cathode is connected to an anode of said third Zener diode (DZ4) and whose anode is connected to the other end of the current path of said N-channel FET (QM2); a parasitic diode (DSD) of said N-channel FET (QM2); and a parasitic capacitance (Cgd) formed between the gate of said N-channel FET (QM2) and the one end of the current path of said N-channel FET (QM2). The AC/DC converter according to claim 1, characterized in that said rectifying means includes a diode (D1) whose anode is connected to a first power supply terminal (12) and whose cathode is connected to the one end of the current path of said N-channel FET (QM2). The AC/DC converter according to claim 14, characterized in that said control means (17) includes: a first resistor (R6) one end of which is connected to an output terminal of said rectifying means (D1); a first diode (D6) whose anode is connected to other end of said first resistor (R6); a first Zener diode (DZ2) whose cathode is connected to a cathode of said first diode (D6); a second Zener diode (DZ3) whose cathode is connected to an anode of said first Zener diode (DZ2); a second resistor (R8) connected between an anode of said second Zener diode (DZ3) and a second power supply terminal (13); a third resistor (R7) one end of which is connected to the output terminal of said rectifying means (D1); a second diode (D3) whose anode is connected to other end of said third resistor (R7) and whose cathode is connected to the gate of said N-channel FET (QM2); and a first transistor (Q9) having a current path one end of which is connected to the second power supply terminal (13) and having a control terminal connected to the anode of said second Zener diode (DZ3); and a fourth resistor (R13) one end of which is connected to the output terminal of said rectifying means (D1) and other end of which is connected to the second power supply terminal (13), and said booster means (18) includes: a second transistor (Q12) having a current path one end of which is connected to the gate of said N-channel FET (QM2) and other end of which is connected to an input terminal of said series power supply circuit (11); a fifth resistor (R14) connected between a control terminal of said second transistor (Q12) and other end of the current path of said first transistor (Q9); a third diode (D7) whose cathode is connected to the one end of the current path of said second transistor (Q12) and whose anode is connected to the other end of the current path of said second transistor (Q12); a third Zener diode (DZ4) whose cathode is connected to the one end of the current path of said second transistor (Q12); a fourth Zener diode (DZ5) whose cathode is connected to an anode of said third Zener diode (DZ4) and whose anode is connected to the other end of the current path of said N-channel FET (QM2); a parasitic diode (DSD) of said N-channel FET (QM2); and a parasitic capacitance (Cgd) formed between the gate of said N-channel FET (QM2) and the one end of the current path of said N-channel FET (QM2).

Inventors: TSUNETSUGU YUKIO, TSUNETSUGU, YUKIO, TSUNETSUGU, YUKIO, C/O INTELL.PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H02M7
IPC codes: H02M7, H03K17, G05F1