Address generation circuit of two-dimensional coding table for Huffman code

Abstract: Circuit for generating the address in a look-up table used for converting two values x and y, corresponding respectively to two events A and B, into one variable length code. Each combination (x,y) corresponds to one address in the table. An escape code instead of a codeword from the table is used if x+log₂(y)>P or if y+log₂(x)>P (codes with low occurence probability). The circuit comprises: coincidence detectors (1a-1g) which detects if at least one of the input x or y takes a value between x and S (S is the biggest integer satisfying S+log₂(S)<P ); large and small comparators (2a-2g) which determine if x+log₂(y)≦P or if y+log₂(x)≦P ; an escape signal generation section (3) which outputs an escape signal according to the output of the coincidence detectors and of the large and small comparators; an address generation section (5) which generates an address in the table depending on x and y; a priority control section (4); and a multiplexer (6); Use: entropy coding of two-dimensional datas like television picture or wind direction/wind velocity.

Description: BACKGROUNDS OF THE INVENTION FIELD OF THE INVENTION This invention relates to an address generating circuit of two-dimensional coding table, and particularly to an address generating circuit of two-dimensional coding table where coded words are distributed in certain ranges of two events. DESCRIPTION OF THE RELATED ART For coding of time series signals having deviated generating frequency, unequal length codes which give a short code to a signal having a high occurrence frequency and a long code to a signal having a low occurrence frequency are used to allow compression coding. This coding is called an entropy coding (Huffman code is one type of the entropy coding). The entropy coding has been applied in various fields such as coding of voice signals and image signals. In variable length coding and variable length decoding, average code length can be minimized by coding to a bit length corresponding to a log (2 is the base) with respect to a reciprocal number of the appearance frequency of each code. In particular, when data occurrence probability is heavily deviated in making transmission or accumulation of data in a large amount, the entropy coding is effective for data compression. For example, in case of recording daily wind direction for past 100 years, to record data about a district having frequent north wind, it is advantageous to compress data when the wind directions and the coded words are corresponded as 1=north, 01=northeast, 001=south, 0001=west, etc. And in recording data about a district having frequent west wind, data is advantageously compressed by assigning a short code to west. Similarly, in case of recording daily wind velocity for past 100 years, it is possible to assign, for example, 1=10 m/sec, 01=30 m/sec, 001=5 m/sec, 0001=20 m/sec, etc. in an order of from high to low of data occurrence probability. In the above coding example, one-dimensional parameters such as wind direction and wind velocity were coded. Further, coding having two parameters (two-dimensional coding) can also be considered. For example, to record both the wind direction and wind velocity, with the wind direction and wind velocity as parameters, a short code is assigned in the order of from high to low of occurrence probability. In this case, the codes are assigned as 1=north wind 10 m/sec, 01=south wind 30 m/sec, 10=southeast wind 10 m/sec, 001=west wind 10 m/sec, etc. Generally, for the entropy coding, the assignment of the entropy codes becomes complex as the assembly of codes is larger. In particular, in the two-dimensional coding, the assembly of codes becomes a direct product of an assembly of two codes. To apply to this case, an escape code may be used for codes having sufficiently low occurrence probability. The escape code takes a form having values of two codes (binary fixed length code) coupled with escape identification section as the entropy code. This escape code being defined, the entropy code is assigned to a combination of high occurrence probability, and the escape code is assigned to a combination of sufficiently low occurrence probability, so that the size of a coding table for fixing the corresponding relation between data and codes can be made small. An example of the escape code in recording the aforementioned wind direction and wind velocity will be described. For example, the wind direction is coded using 4-bit codes as 0000=north, 0001=south, 0010=east, 0011=west, 0100=northeast, 0101=northwest, m/sec, 000001=20 m/sec, 000010=30 m/sec, 000011=40 m/sec, ..... for every 10 m/sec. And, these to codes are coupled into 10-bit codes indicating the wind direction by high order 4 bits and the wind velocity by low order 6 bits. Thus, a state with low occurrence possibility can be coded. The coding table determining the corresponding relation between recorded data and codes is generally structured by assigning respective coded words to an address on memory. Therefore, to refer to a coded word corresponding to a certain data, the assigned address has to be determined. Particularly, in the two-dimensional coding table, an address in that coding table has to be calculated from the values of two events. A conventional address generating circuit to generate the address of such a two-dimensional coding table is as follows. A first address generating circuit is a circuit to read from a coding table a coded word corresponding to the values of two events according to a program which is software. This address generating circuit has a CPU for processing a program and an instruction memory to store the program as essential components. In this address generating circuit, an address is generated as follows. First, an appropriate address is assigned on memory to every coded words corresponding to data. The program detects the values of two events and outputs an address corresponding to their parameters. For example, when recording the aforementioned wind direction and wind velocity, among the two events, the wind direction is determined to be event A and the wind velocity as event B, and an address of a coded word for north wind 10 m/sec is to be read. In this case, when event A=0001, event B=000001, and an address having a coded word stored in the coded word table is determined to be 0010 address, it is programed to read the adress 0010 by a condition judgment of (A=0001) and (B=000001). Using the circuit thus programed, condition is judged from the values of events A and B with respect to every coded word to generate an address of the coding table. A second address generating circuit is a circuit to output an address of the coding table using hardware means such as a comparator or detector in which the values of two events are entered. Specifically, this is a process to generate an address of the coded word through hardware by preparing a dedicated decoder. A third address generating circuit is a circuit having a coding table having the values themselves of two events corresponded to a coded word as an address. This address generating circuit has the value of event A as a high order of the address and the value of event B as a low order of the address, and the values of A and B are coupled to generate an address of the coding table. Such an address generating circuit does not need the addition of a dedicated hardware, and an address can be generated simply. But, the aforementioned conventional address generating circuits of two-dimensional coding table have the following drawbacks. The first address generating circuit according to a program successively compares the values of two events to output an address and requires a time for comparison operation treatment. Therefore, it cannot be used for a high-speed processing such as a real time image processing. And, it also needs a system for address generation such as a CPU and an instruction memory for storing program. Thus, the construction is complicated. The second address generating circuit for generating an address through hardware needs a dedicated hardware for detecting an address of the coding table corresponding to the values of two events, so that the circuit becomes large when the circuit is desired to correspond to a large volume of coded words exceeding 100 words. The third address generating circuit with the coding table having the values of two events as an address has the drawback that a memory capacity which is required by a memory for storing a coding table becomes large. "A Signal Processing Image Communication", vol. 5, no. 1/2, Feb. 1993, pages 39-58, A. Puri et al., deals with "adaptive frame/field motion compensated video coding". The development of the second phase of the Motion Pictures Experts Group (MPEG-2) is outlined, and several techniques used therein are explained, such as motion estimation and compensation, DCT and quantization, the adaptions of a quantizer and a rate control, variable word length coding, and details of the encoder and decoder used for the scheme of coding. SUMMARY OF THE INVENTION An object of this invention is to provide an address generating circuit of two-dimensional coding table which operates fast, does not become large even when corresponding to a large volume of coded words, and does not need a large capacity for a memory to store a coding table. The address generating circuit of two-dimensional coding table for accomplishing the above object of this invention is defined in independent claims 1 and 6. The dependent claims define particular embodiments of the invention. The address generating circuit of two-dimensional coding table according to this invention may further comprise a priority control means which selects and outputs either one of the coincidence detection signal on the x or the coincidence detection signal on the y when both the value x of the event A and the value y of the event B fall under the integral numbers in the range of 1 to S according to the detected result of the coincidence detection means. Other objects, features and effects of this invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing the structure of the address generating circuit of two-dimensional coding table according to a first embodiment of this invention. Fig. 2 is a state diagram showing the distributed condition of coded words of the two-dimensional coding table which is subjected to the treatment according to the embodiment of Fig. 1. Fig. 3 is a chart showing the data format of the outputted address signals of the embodiment of Fig. 1. Fig. 4 is a circuit diagram showing the structure of the address generating circuit of two-dimensional coding table according to a second embodiment of this invention. Fig. 5 is a state diagram showing the distributed condition of coded words of the two-dimensional coding table which is subjected to the treatment according to the embodiment of Fig. 4. Fig. 6 is a chart showing the data format of the outputted address signals of the embodiment of Fig. 4. DESCRIPTION OF THE PREFERRED EMBODIMENT Preferable embodiments of this invention will be described in detail with reference to the attached drawings. Fig. 1 is a circuit diagram showing the structure of the address generating circuit of two-dimensional coding table according to a first embodiment of this invention. Fig. 2 is a state diagram showing the distributed condition of coded words of the two-dimensional coding table which is subjected to the address generating circuit of Fig. 1. The address generating circuit of this embodiment is intended for a two-dimensional coding table which determines the value of event A as x and the value of event B as y (x and y are positive integral numbers) for two events A and B, corresponds respective coded word to a combination of x and y consisting of x which satisfies x + log 2 y ≦ P with respect to each integral number of from 1 through S (S is the maximum value among integral numbers meeting S + log 2 S < P, and P is a positive integral number) and y which satisfies y + log 2 x ≦ P with respect to each integral number of from 1 through S, and stores the applicable coded word in an address which is disposed to correspond to each combination of x and y. In other words, when the distributed condition of coded words corresponding to combinations of x and y is illustrated on an x-y plane with two axes x and y crossing at right angles, as shown in Fig. 2, the two events A and B which become a combination of x and y are subjected so that the distributed condition of coded words becomes linearly symmetrical with respect to the straight lines of x=y. This embodiment relates to an address generating circuit when P=6 and S=3 in the aforementioned formula S + log 2 S < P. Referring to the distributed condition of coded words shown in Fig. 2, it is seen that the value x of event A determines the number of bits in an effective range of the value y of event B, and the value y of event B determines the number of bits in an effective range of the value x of event A. For example, when x=2, the coded words are distributed in the range of y which is represented by 4 bits, and when x=3, the coded words are distributed in the range of y which is represented by 3 bits. Similarly, when y=1, the coded words are distributed in the range of x which is represented by 5 bits, when y=2, the coded words are distributed in the range of x which is represented by 4 bits, and when y=3, the coded words are distributed in the range of x which is represented by 3 bits. This is generally an area satisfying x + log 2 y ≦ P when x=1 to 3 and y + log 2 x ≦ P (where P=6) when y=1 to 3. Areas other than this area are for escape codes. Taking this deviated distributed condition of coded words into consideration, an address is assigned to coded words. Among values x and y of events A and B, values x=3 and y=3 are the maximum values among integral numbers satisfying S+log 2 S < P where P=6. The distributed condition of coded words described above is summarized as follows. When x=1, y is 1 to 32, resulting in 32 words. When x=2, y is 1 to 16, resulting in 16 words. When x=3, y is 1 to 8, resulting in 8 words. When y=1, x is 1 to 32, resulting in 32 words. When y=2, x is 1 to 16, resulting in 16 words. When y=3, x is 1 to 8, resulting in 8 words. To indicate the addresses corresponding to all coded words in such a distributed condition with respect to the combinations of x and y in the aforementioned ranges, 1 + log 2 32 bits are required for x=1 to 3, and 1 + log 2 32 bits are required for y=1 to 3, so that 2 + log 2 32 bits, or P + 1 = 7, are required for all x and y. This embodiment shown in Fig. 1 comprises a plurality of coincidence detectors 1a to 1f which receive as input values x and y of events A and B and detect whether the input values coincide with integral numbers 1 to 3, large and small comparators 2a to 2c which detect whether the inputted y satisfies x + log 2 y ≦ 6 for each integral number of from 1 to 3 of x, large and small comparators 2d to 2f which detect whether the inputted x satisfies y + log 2 x ≦ 6 for each integral number of from 1 to 3 of y, an escape signal generation section 3 which outputs an escape signal according to the output of the coincidence detectors la to 1f and the large and small comparators 2a to 2f, an address generation section 5 which generates and outputs an address signal from values x and y and an identification address ADi for identifying that x and y are which of integral numbers of 1 to 3, a priority control section 4 which inputs the output from the coincidence detectors la to 1f, determines a signal which is outputted with precedence and outputs it, a multiplexer 6 which selects and outputs an address signal in accordance with the output from the priority control section 4, and an output stop circuit 7 which stops the supply of a two-dimensional coding table of the output signal from the multiplexer 6 according to the escape signal. The coincidence detectors la to 1f consist of the coincidence detectors la to lc for inputting x and the coincidence detectors 1d to 1f for inputting y. And, they detect whether the inputted x and y coincide with integral numbers 1 to 3, the coincidence detectors 1a and 1d output a coincidence detection signal which becomes an active level when y is 1, the coincidence detectors 1b and 1e output a coincidence detection signal which becomes an active level when y is 2, and the coincidence detectors 1c and 1f output a coincidence detection signal which becomes an active level when y is 3. The large and small comparators 2a to 2c inspect whether the inputted y satisfies x + log 2 y ≦ 6 with respect to x, the large and small comparator 2a outputs a compared result signal which becomes an active level when x = 1 and y ≦ 32, the large and small comparator 2b outputs a compared result signal which becomes an active level when x = 2 and y ≦ 16, and the large and small comparator 2c outputs a compared result signal which becomes an active level when x = 3 and y ≦ 8. The large and small comparators 2d to 2f inspect whether the inputted x satisfies y + log 2 x ≦ 6 with respect to y, the large and small comparator 2d outputs a compared result signal which becomes an active level when y = 1 and x ≦ 32, the large and small comparator 2e outputs a compared result signal which becomes an active level when y = 2 and x ≦ 16, and the large and small comparator 2f outputs a compared result signal which becomes an active level when y = 3 and x ≦ 8. The escape signal generation section 3 has AND type logic gates G31 to G36 and NOR type logic gate G37. The logic gates G31 to G36 input one detection signal from the coincidence detectors 1a to 1f and a compared result signal from the large and small comparators 2a to 2f, and the logic gate G37 inputs an output signal from the logic gates G31 to G36. And, when there is no combination at an active level among combinations of coincidence detection signals and compared result signals corresponding thereto, escape signal ES at an active level is outputted. Thus, when x is 1, 2 or 3 and y does not satisfy x + log 2 y ≦ 6, and y is 1, 2 or 3 and x does not satisfy y + log 2 x ≦ 6, a coded word corresponding to a combination of x and y containing the above x and y is processed as an escape code. The address generation section 5 has an identification address generating circuit 51 which generates an identification address ADi for identifying that x and y are which of integral numbers of 1 to 3, couples each identification address ADi of y with a certain bit at lower order of the inputted x to output respectively as an address signal AD of 7 bits. The identification address ADi consists of the most significant bit indicating a difference between x side and y side (for example, x side is indicated by 1 and y side by 0) and 1 to 3 bits (for example, 1=1, 2=01, 3=001, etc.) indicating 1, 2, 3 succeeding thereto. And, since it is sufficient if a certain bit at lower order of y and x corresponding to the identification address ADi can identify 32 words when x and y are 1, 16 words when x and y are 2, and 8 words when x and y are 3, respective bits at lower order of y and x forming the address signal AD become 5 bits, 4 bits, and 3 bits. Fig. 3 shows the data format of the address AD thus generated. The priority control section 4 has NOR type logic gate G41 and AND type logic gates G42 to G44. The logic gate G41 inputs a coincidence detection signal from the coincidence detectors 1d to 1f, and the logic gates G42 to G44 input the coincidence detection signals from the coincidence detectors 1a to 1c and the output from the logic gate G41. And, when both the coincidence detection signals on x side and the coincidence detection signals on y side include signals at an active level, the coincidence detection signal on y side is masked, and the coincidence detection signal on x side only is outputted with precedence. In other cases, both the coincidence detection signal on x side and the coincidence detection signal on y side are outputted as they are. Thus, even when there are signals at an active level in both the coincidence detection signals on x side and the coincidence detection signals on y side, a possibility that one address signal AD cannot be surely selected can be avoided. The multiplexer 6 selects and outputs the address signal AD containing an identification address ADi corresponding to the applicable x or y among the address signal AD which is outputted from the address generation section 5, according to the coincidence detection signal at an active level of the coincidence detectors 1a to 1f. As described above, in this embodiment, since the coincidence detectors, large and small comparators and others are sufficient by being provided in numbers corresponding to the maximum number of integral number S satisfying S + log 2 S < P , the circuit scale can be made small. And, the memory capacity of the memory for the two-dimensional coding table is also sufficient in the numbers for addresses corresponding to P+1 bit. Further, since processing is directly made through hardware, high-speed processing in real time is possible. Fig. 4 is a circuit diagram showing the structure of the address generating circuit of two-dimensional coding table according to a second embodiment of this invention. Fig. 5 is a state diagram showing the distributed condition of coded words of the two-dimensional coding table which is subjected to the address generating circuit of Fig. 4. The address generating circuit of this embodiment is intended for a two-dimensional coding table which determines the value of event A as x and the value of event B as y (x and y are positive integral numbers) for two events A and B, corresponds respective coded word to a combination of x and y consisting of x which satisfies x + log 2 y ≦ P with respect to each integral number of from 1 through S (S is the maximum value among integral numbers satisfying 2 (P-S) - 1 ≦ Q - log 2 S, and P and Q are positive integral numbers) and y which satisfies y + log 2 x ≦ Q with respect to each integral number of from 1 through R (R is the maximum value among integral numbers satisfying 2 (Q-R) - 1 ≧ P - log 2 R), and stores the applicable coded word in an address which is disposed to correspond to each combination of x and y. In other words, when the distributed condition of coded words corresponding to combinations of x and y is illustrated on an x-y plane with two axes x and y crossing at right angles, as shown in Fig. 5, the two events A and B which become a combination of x and y are subjected so that the distributed condition of coded words does not become linearly symmetrical with respect to the straight lines of x=y. This embodiment relates to an address generating circuit when P=6, Q=5, R=2 and S=4 in the aforementioned formulas 2 (P-S) - 1 ≧ Q - log 2 S and 2 (Q-R) -1 ≧ P - log 2 R. Referring to the distributed condition of coded words shown in Fig. 5, when x=1, the coded words are distributed in the range of y which is represented by 5 bits, when x=2, the coded words are distributed in the range of y which is represented by 4 bits, when x=3, the coded words are distributed in the range of y which is represented by 3 bits, and when x=4, the coded words are distributed in the range of y which is represented by 2 bits. Similarly, when y=1, the coded words are distributed in the range of x which is represented by 4 bits, and when y=2, the coded words are distributed in the range of x which is represented by 3 bits. This is generally an area satisfying x + log 2 y ≦ 6 when x=1 to 4 and y + log 2 x ≦ 5 when y=1 to 2. Among values x of event A, value x=4 is the maximum values among integral numbers satisfying 2 (6-S) - 1 ≧ 5 - log 2 S. And Among values y of event B, value y=2 is the maximum values among integral numbers satisfying 2 (5-R) - 1 ≧ 6 - log 2 R. Areas other than the above that become areas of the escape code are the same with that of the first embodiment shown in Fig. 1 and Fig. 2. The distributed condition of coded words described above is summarized as follows. When x=1, y is 1 to 32, resulting in 32 words. When x=2, y is 1 to 16, resulting in 16 words. When x=3, y is 1 to 8, resulting in 8 words. When x=4, x is 1 to 4, resulting in 4 words. When y=1, x is 1 to 32, resulting in 32 words. When y=2, x is 1 to 16, resulting in 16 words. To indicate the addresses corresponding to all coded words in such a distributed condition with respect to the combinations of x and y in the aforementioned ranges, a larger value of P or Q, or P+1=7 bits are required in the above example. This embodiment shown in Fig. 1 comprises a plurality of coincidence detectors la to le and 1g which input values x and y of events A and B and detect whether the inputted values x coincide with integral numbers 1 to 4 and the inputted values y coincide with integral numbers 1 to 2, large and small comparators 2a to 2c and 2g which detect whether the inputted y satisfies x + log 2 y ≦ 6 for each integral number of from 1 to 4 of x, large and small comparators 2e to 2f which detect whether the inputted x satisfies y + log 2 x ≦ 6 for each integral number of from 1 to 2 of y, an escape signal generation section 3 which outputs an escape signal according to the output of the coincidence detectors la to le and 1g and the large and small comparators 2a to 2c and 2e to 2g, an address generation section 5 which generates and outputs an address signal from values x and y and an identification address ADi for identifying that x and y are which of integral numbers of 1 to 3, a priority control section 4 which inputs the output from the coincidence detectors la to 1f, determines a signal which is outputted with precedence and outputs it, a multiplexer 6 which selects and outputs an address signal in accordance with the output from the priority control section 4, and an output stop circuit 7 which stops the supply of a two-dimensional coding table of the output signal from the multiplexer 6 according to the escape signal. This embodiment is slightly different from the first embodiment in the circuit structure, the contents of the address signal AD and others. But such differences are not essential, and the basic operation and effects are same with the first embodiment. More specifically, the coincidence detectors, large and small comparators and others are sufficient in the number corresponding to the number added with the maximum number of integral number S satisfying 2 (P-S) - 1 ≧ Q - log 2 S and the maximum number of integral number R satisfying 2 (Q-R) - 1 ≧ P - log 2 R, so that the circuit scale can be made small. And, the memory capacity of the memory for the two-dimensional coding table is also sufficient in the numbers for addresses corresponding to a larger number of P or Q+1 bits. Further, since processing is directly made through hardware, high-speed processing in real time is possible. As described above with reference to the preferable embodiments, this invention is provided with needed and sufficient number of coincidence detectors and comparators derived according to the contributed state of codes and a means for generating an address signal with needed and sufficient address numbers similarly derived, and has the structure to select the address signal according to the output signal of the above coincidence detectors and to generate the escape signal according to the output signal of the above coincidence detectors and comparators, so that it has an effect that the memory capacity of the two-dimensional coding table and the circuit scale can be made small. This invention also has an effect of making a high-speed recessing in real time since the processing can be directly made through hardware. Obviously, various modifications can be made to the above embodiments.

Claims: An address generating circuit of a two-dimensional coding table using entropy coding for compression and an escape code as a binary fixed length code so that the entropy code is assigned to a combination of high occurrence probability and the escape code is assigned to a combination of low occurrence probability so that the size of the two-dimensional coding table can be made small, said circuit comprising: a two-dimensional coding table which determines the value of event A as x and the value of event B as y (x and y are positive integral numbers), wherein the value x of event A determines the number of bits in an effective range of the value y of event B, and wherein the value y of event B determines the number of bits in an effective range of the value x of event A, said table corresponding a respective coded word to a combination of x and y consisting of x which satisfies x + log 2 y ≤ P with respect to each integral number of x from 1 to S (S is the maximum value among integral numbers meeting S + log 2 S < P, and P is a positive integral number) and y which satisfies y + log 2 x < P with respect to each integral number of y from 1 through S, and stores the coded word in an address which is disposed to correspond to each combination of x and y, so that P + 1 bits are required for all combinations of x and y, a coincidence detection means (1a - 1f) which inputs the values x and y of the events A and B and detects whether these values coincide with one of the integral numbers in the range of 1 to S, a first comparing means (2a - 2c) which detects whether the inputted value y of the event B satisfies x + log 2 y ≤ P with respect to the value y of the event B for values of x in the range of 1 to S, a second comparing means (2d -2f) which detects whether the inputted value x of the event A satisfies y + log 2 x ≤ P with respect to the value x of the event A for values of y in the range of 1 to S, an escape signal generating means (3) which outputs an escape signal as an escape code and supplies it to the two-dimensional coding table when the value x of the event A or the value y of the event B does not fall under the integral number of said range according to the detected result of the coincidence detection means, and when the value y of the event B does not satisfy x + log 2 y ≤ P or the value x of the event A does not satisfy y + log 2 x ≤ P according to the detected result of the first and second comparing means, an address generation means (5) which generates and outputs an address signal from the values of said x and y and an identification address (ADi) for identifying which of the integral numbers within said range 1 to S the values of x and y are, when at least one of the value x of the event A or the value y of the event B falls under the integral number of said range of 1 to S according to the detected result of the coincidence detection means, and a selection means (6) which selects and outputs the address signal according to the output of the address generation means and supplies it to the two-dimensional coding table. An address generating circuit of two-dimensional coding table according to Claim 1 which further comprises a priority control means (4) which selects and outputs either one of the coincidence detection signal on the x or the coincidence detection signal on the y when both the value x of the event A and the value y of the event B fall under the integral numbers in the range of 1 to S according to the detected result of the coincidence detection means (1a-1f). An address generating circuit of two-dimensional coding table according to Claim 2, wherein the coincidence detection means (1a-1f) has S numbers of coincidence detectors (1a-1c) for inputting the value x of the event A and S numbers of coincidence detectors (1d-1f) for inputting the value y of the event B, said coincidence detectors outputting a coincidence detection signal which becomes an active level when the inputted value x of the event A or the value y of the event B agrees with the integral numbers of the range of said assigned 1 to S, the first comparing means (2a-2c) has S numbers of comparators for inputting the value y of the event B, said comparators outputting a comparison result signal which becomes an active level when the inputted value y of the event B satisfies x + log 2 y ≦ P with respect to the value y of the event B for values of x in the range of 1 to S, the second comparing means (2d-2f) has S numbers of comparators for inputting the value x of the event A, said comparators outputting a comparison result signal which becomes an active level when the inputted value x of the event A satisfies y + log 2 x ≦ P with respect to the value x of the event A for values of y in the range of 1 to S, the escape signal generating means (3) consists of a plurality of logic gates (G31-G37), inputs one detection signal from the coincidence detectors and the comparison result signal from the first and second comparators, and outputs an escape signal which is an active level when no set of signals at an active level is among the combination of the coincidence detection signals and the comparison result signals respectively corresponding thereto, the address generation means (5) has an identification address generating circuit (51) for generating the identification address, couples each identification address of the value x of the event A with the inputted value y of the event B, and couples each identification address of the value y of the event B with a certain bit at lower order of the inputted value x of the event A to output an address signal of (P+1) bits, the priority control means (4) consists of a plurality of logic gates (G41-G44), inputs the coincidence detection signal from the coincidence comparators, outputs the coincidence detection signal on the x with precedence when both the coincidence detection signal on the value x of the event A and the coincidence detection signal on the value y of the event B have a signal at an active level, and outputs both the coincidence detection signal on the x and the coincidence detection signal on the y in other cases, and the selection means (6) selects and outputs the address signal containing the identification address corresponding to the applicable value x of the event A or the value y of the event B among the address signals outputted from the address generation section according to the coincidence detection signal at an active level of the coincidence detectors. An address generating circuit of two-dimensional coding table according to Claim 2 which further comprises an output stop circuit (7) which stops the supply of the output signal of the selection means (6) to the two-dimensional coding table upon receipt of the escape signal outputted from the escape signal generating means (3). An address generating circuit of a two-dimensional coding table according to claim 3 or 4, wherein said selection means (6) which selects and outputs the address signal, and supplies it to the two-dimensional coding table. An address generating circuit of a two-dimensional coding table using entropy coding for compression and an escape code as a binary fixed length code so that the entropy code is assigned to a combination of high occurrence probability and the escape code is assigned to a combination of low occurrence probability so that the size of the two-dimensional coding table can be made small, said circuit comprising: a two-dimensional coding table which determines the value of event A as x and the value of event B as y (x and y are positive integral numbers), wherein the value x of event A determines the number of bits in an effective range of the value y of event B, and wherein the value y of event B determines the number of bits in an effective range of the value x of event A, said table corresponding a respective coded word to a combination of x and y consisting of x which satisfies x + log 2 y ≤ P with respect to each integral number of x from 1 to S (S is the maximum value among integral numbers meeting 2 (P - S) - 1 ≤ Q - log 2 S, and P and Q are positive integral numbers) and y which satisfies y + log 2 x ≤ Q with respect to each integral number of y from 1 through R (R is the maximum value among integral numbers satisfying 2 (Q - R) - 1 ≥ P - log 2 R, and stores the coded word in an address which is disposed to correspond to each combination of x and y, so that P + 1 or Q +1 bits are required for all combinations of x and y, in case of either P or Q being the larger one of both values, a coincidence detection means (1a - 1f) which inputs the values x and y of the events A and B and detects whether the value of the event A conincides with one of the integral numbers in the range of 1 to S, and whether the value y of the event B coincides with one of the integral numbers in the range of 1 to R, a first comparing means (2a - 2c) which detects whether the inputted value y of the event B satisfies x + log 2 y ≤ P with respect to the value y of the event B for values of x in the range of 1 to S, a second comparing means (2e -2f) which detects whether the inputted value x of the event A satisfies y + log 2 x ≤ P with respect to the value x of the event A for values of y in the range of 1 to R, an escape signal generating means (3) which outputs an escape signal as an escape code and supplies it to the two-dimensional coding table when the value x of the event A or the value y of the event B does not fall under the integral number of said ranges according to the detected result of the coincidence detection means, and when the value y of the event B does not satisfy x + log 2 y ≤ P or the value x of the event A does not satisfy y + log 2 x ≤ P according to the detected result of the first and second comparing means, an address generation means (5) which generates and outputs an address signal from the values of said x and y and an identification address (ADi) for identifying which of the integral numbers within said range 1 to S or said range 1 to R the values of x and y respectively are, when at least one of the value x of the event A or the value y of the event B falls under the integral number of said range of 1 to S or said range 1 to R, respectively, according to the detected result of the coincidence detection means, and a selection means (6) which selects and outputs the address signal according to the output of the address generation means and supplies it to the two-dimensional coding table. An address generating circuit of two-dimensional coding table according to Claim 6 which further comprises a priority control means (4) which selects and outputs either one of the coincidence detection signal on the x or the coincidence detection signal on the y when the value x of the event A falls under the integral numbers in the range of 1 to S and the value y of the event B falls under the integral numbers in the range of 1 to R according to the detected result of the coincidence detection means (1a-1e, 1g). An address generating circuit of two-dimensional coding table according to Claim 7, wherein the coincidence detection means (1a-1c, 1g) has S numbers of coincidence detectors for inputting the value x of the event A and R numbers of coincidence detectors for inputting the value y of the event B, said coincidence detectors outputting a coincidence detection signal which becomes an active level when the inputted x agrees with the integral numbers of the range of said assigned 1 to S and when the inputted y agrees with the integral numbers of the range of said assigned 1 to R, the first comparing means (2a-2g) has S numbers of comparators for inputting the value y of the event B, said comparators outputting a comparison result signal which becomes an active level when the inputted value y of the event B satisfies x + log 2 y ≦ P with respect to the value y of the event B for values of x in the range of 1 to S, the second comparing means (2a-2c, 2g) has R numbers of comparators for inputting the value x of the event A, said comparators outputting a comparison result signal which becomes an active level when the inputted value x of the event A satisfies y + log 2 x ≦ P with respect to the value x of the event A for values of y in the range of 1 to R, the escape signal generating means (3) consists of a plurality of logic gates (G31-G37), inputs one detection signal from the coincidence detectors and the comparison result signal from the first and second comparators, and outputs an escape signal which is an active level when no set of signal at an active level is among the combination of the coincidence detection signal and the comparison result signals respectively corresponding thereto, the address generation means (5) has an identification address generating circuit (51) for generating the identification address, couples each identification address of the value x of the event A with the inputted value y of the event B, and couples each identification address of the value y of the event B with a certain bit at lower order of the inputted value x of the event A to output as an address signal of (larger value of P or Q+1) bits, the priority control means (4) consists of a plurality of logic gates (G41-G47), inputs the coincidence detection signal from the coincidence comparators, outputs the coincidence detection signal on the value x of the event A with precedence when both the coincidence detection signal on the value x of the event A and the coincidence detection signal on the value y of the event B have a signal at an active level, and outputs both the coincidence detection signal on the x and the coincidence detection signal on the y in other cases, and the selection means (6) selects and outputs the address signal containing the identification address corresponding to the applicable value x of the event A or the value y of the event B among the address signals outputted from the address generation section according to the coincidence detection signal at an active level of the coincidence detectors. An address generating circuit of two-dimensional coding table according to Claim 7 which further comprises an output stop circuit (7) which stops the supply of the output signal of the selection means (6) to the two-dimensional coding table upon receipt of the escape signal outputted from the escape signal generating means (3).

Inventors: ISHIDA HIDEO, OOI YASUSHI, ISHIDA, HIDEO, OOI, YASUSHI, ISHIDA, HIDEO, C/O NEC CORPORATION, OOI, YASUSHI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03M7
IPC codes: H04N7, H03M7