Latch controlled output driver

Abstract: An output driver includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. This prevents both of the transistors from turning on simultaneously.

Description: The present invention relates to the field of microelectronics and in particular to digital circuits. Still more particularly, the present invention relates to output drivers in digital circuits. In a digital circuit system, a common path is often used to share and transfer data between various circuits and devices in the system. A small set of shared lines, a bus, may be used to provide the common path. In the designing of digital circuit systems, some devices may have an insufficient amount of maximum output current to drive all of the lines connected to the devices. As a result, a current amplifier, called a driver or a buffer, is used to provide the needed currents. Latches are often used to control output drivers in digital circuit systems. The state of these latches is often critical during the power up phase of a digital circuit system. For example, in an output driver circuit having a pull up and pull down transistor and having two latches controlling the pull up and pull down transistors, forming the output driver, the individual latches may power up in states that turn on both transistors at the same time. Such a condition is known as a "crowbar" condition. Frequently, parts that have differential data bussed all the way to the output can see such effects. In some cases, a power-up reset circuit is used to force the state of the latches to some preset state to avoid a crowbar condition. Such a solution is not always sufficient. For example, sometimes the state of the differential buses may not be differentiated, leading to a crowbar condition during non-power-up conditions. Also, a glitch in device operation or external conditions such as a power supply may cause non-differentiation during a non-power-up condition. In other cases, during testing of the device, a defective memory cell may be accessed, rendering the differential buses non-differentiated and creating a crowbar condition at the outputs. In such a situation, the bad memory cell may be replaced by redundant memory cells, but the testing of the bad memory cell may have fused the power supplies or in some other way rendered the device unusable. Therefore, it would be desirable to have an apparatus to prevent a crowbar condition from occurring in a output driver controlled by two or more latches. JP-A-02 243015 discloses a circuit for controlling a pull-up transistor and a pull-down transistor. First and second latches are provided at the control terminals of the pull- up and pull- down output transistors, respectively. A crowbar condition at the output is avoided by forming a period where the pull- up and pull- down transistors both are turned off. According to the present invention there is provided a control circuit for controlling a pull-up transistor as a first output transistor and a pull-down transistor as a second output transistor in a driver circuit comprising: first and second latches, each latch having an output and an input, the first latch having an output for connection to a gate of the first output transistor, and the second latch having an output for connection to a gate of the second output transistor; a first gate having an output and an input, wherein the output of the first gate is connected to said input of the first latch and the input of the first gate is connected to a first input point; a second gate having an output and an input, wherein the output of the second gate is connected to said input of the second latch and the input of the second gate is connected to a second input point; a first transistor having a source connected to an upper power supply voltage, a drain connected to said input of the first latch circuit; and a gate connected to said input of the second latch circuit; and a second transistor having a source connected to the upper power supply voltage, a drain connected to said input of the second latch circuit, and a gate connected to said input of the first latch circuit. An output driver according to an embodiment of the present invention includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. The control transistors prevent both of the pull-up and pull-down transistors from turning on simultaneously. The latch controlled output driver circuit additionally contains a first pass gate having an output connected to the input of the first latch circuit; a second pass gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figure 1 is a block diagram of a memory unit in which a preferred embodiment of the present invention may be implemented; and Figure 2 is a schematic diagram of a latch controlled output driver. Referring now to Figure 1 , a block diagram of a memory array 100 is illustrated in which a preferred embodiment of the present invention may be implemented. Memory array 100 (also just called a "memory") is subdivided into eight memory groups: 0-7 . Each memory group contains a memory block 102a , a memory block 102b , and an input/output (I/O) block 104a . I/O block 104a is interposed between the two memory blocks 102a and 102b . Data bus latch block 106 is connected to the I/O blocks 104a of memory groups 0-7 via a data array 108 . Data bus circuit block 106 also has an output array 109 . Data bus latch block 106 includes latch controlled output drivers. Referring to Figure 2, a schematic diagram of a latch controlled output driver 90 is depicted. Latch controlled output driver circuit 90 includes an output driver 92 and latches 94 and 96 . Latch controlled output driver circuit 90 is constructed from pass gates G1 and G2 , transistors P1, P2, T1 , and T2 ; and inverters I1-I5 . Transistors P1 and P2 are p-channel metal-oxide field effect transistors (MOSFETs) while transistors T1 and T2 are n-channel MOSFETs. The circuit is powered by connecting the sources of transistor P1 and P2 to power supply voltage Vcc and the drain of transistor T1 to power supply voltage VCC and by connecting the source of transistor T2 to power supply voltage VSS . Typically, power supply voltage VCC is at a higher voltage than power supply voltage VSS . Output driver 92 includes transistors T1 and T2 and has an output node at point 102 . Transistor T1 is a pull-up transistor and transistor T2 is a pull-down transistor in the output driver portion of this circuit. The gate of transistor T1 is controlled by a signal from input point GDT passing through pass gate G1 and inverters I2 and I3 of latch 94 . Similarly, the gate of transistor T2 is controlled by a signal from input point GDC passing through pass gate G2 and through inverters I4 and I5 of latch 96 . Pass gates G1 and G2 are controlled by a clock signal, CLK, applied to point 104 and a complement clock signal, /CLK . The /CLK signal is generated by passing the CLK signal through inverter I1 . Typically, input points GDT and GDC are connected to buses that are precharged high between clock cycles generated by the CLK signal. Afterward, one of the input points, GDT or GDC , selectively goes low when data is read. The latch portion of the circuit latches 94 and 96 , include pass gates G1 and G2 and the cross-coupled inverters I2-I5 . Latch 94 contains inverters I2 and I3 and pass gate G1 ; latch 96 includes inverters I4 and I5 and pass gate G2 . Pass gates G1 and G2 pass data to latches 94 and 96 , respectively. Although the depicted embodiment shows only two latches connected to the output driver, additional latches may be connected to the output driver and selected using a multiplexing circuit in accordance with a preferred embodiment of the present invention. Other variations to the latches and inverters may be made by those of ordinary skill in the art. For example, inverter I3 in latch 94 and inverter I5 in latch 96 may be replaced with NAND gates instead with the other input being from point DC for the NAND gate replacing inverter I3 and from point DT for the NAND gate inverter I5 . The depicted embodiment shows the use of pass gates for gating or sending information to the latches. Other types of gates or devices known to those skilled in the art for gating or providing an interface circuit for controlling data reaching the latches may be used according to the present invention. Transistors P1 and P2 are employed to ensure that a crowbar condition does not occur in the output driver portion of the circuit in Figure 2. These devices prevent points DT and DC from both going low at the same time, during power up while the pass gates are not conductive or during anomalous operations. Transistors P1 and P2 should be sized to overcome the feedback from inverters I3 and I5 . In addition, transistors P1 and P2 may be sized to still exceed the trip point of the inverters driving the output driver transistors T1 and T2 if points DT and DC are being pulled low through pass gates G1 and G2 at the same time by sizing transistors P1 and P2 relative to the pass gate transistors. Consequently, the use of power-up reset control circuits may be avoided, as well as anomalous operation of the outputs or severe stressing of the device when locating bad memory cells in a memory that may occur during testing of the memory cells. The present invention may be implemented in all integrated circuits requiring output drivers controlled by latches. Such integrated circuits include, for example, memory such as DRAMS, SRAMs, and PROMs. By eliminating the need for a power up control circuit to set the latches, the present invention may reduce the amount of space needed to produce memories and other circuits requiring latch controlled output drivers. Although the present invention is depicted using MOS technology, other types of technology and transistors may used in accordance with a preferred embodiment of the present invention.

Claims: A control circuit for controlling a pull-up transistor as a first output transistor and a pull-down transistor as a second output transistor in a driver circuit comprising: first and second latches (12,13; 14,15), each latch having an output and an input, the first latch having an output for connection to a gate of the first output transistor (T1), and the second latch having an output for connection to a gate of the second output transistor (T2); a first gate (G1) having an output and an input, wherein the output of the first gate is connected to said input of the first latch and the input of the first gate is connected to a first input point (GDT) ; a second gate (G2) having an output and an input, wherein the output of the second gate is connected to said input of the second latch and the input of the second gate is connected to a second input point (GDC); a first transistor (P1) having a source connected to an upper power supply voltage, a drain connected to said input of the first latch circuit; and a gate connected to said input of the second latch circuit; and a second transistor (P2) having a source connected to the upper power supply voltage, a drain connected to said input of the second latch circuit, and a gate connected to said input of the first latch circuit. A latch controlled output driver circuit comprising: the control circuit of claim 1 in combination with said pull-up transistor (T1) and said pull-down transistor (T2). The latch controlled output driver circuit of claim 2, wherein the pull-up transistor and the pull-down transistor are n-channel MOSFETs. The circuit of any preceding claim, wherein the first input point (GDT) is connected to a true data line and the second input point (GDC) is connected to a complement data line. A memory circuit comprising: a plurality of memory groups (0-7) having a plurality of outputs; and a data bus circuit (106) having a plurality of inputs connected to the plurality of outputs, the data bus circuit having a latch controlled output driver circuit as claimed in claims 2 or 3. The memory circuit of claim 5, wherein the first input point (GDT) is connected to a true data line and the second input point (GDC) is connected to a complement data line. The circuit of any preceding claim, wherein the gates are controlled by a clock signal. The circuit of any preceding claim, wherein the first latch circuit includes a first inverter (12) and a second inverter (13), the input of the first latch circuit being connected to an input of the first inverter and an output of the second inverter and the output of the first latch circuit being connected to the output of the first inverter and the input of the second inverter and wherein the second latch circuit includes a third inverter (14) and a fourth inverter (15), the input of the second latch circuit being connected to the input of the third inverter and the output of the fourth inverter and the output of the second latch circuit being connected to the output of the third inverter and the input of the fourth inverter. The circuit of claim 8 wherein; said first transistor (P1) is sized to overcome the feedback from the second inverter (13) of said first latch and said second transistor (P2) is sized to overcome the feedback from the fourth inverter (15) of said second latch. The circuit of any of claims 1 to 8, wherein the first latch circuit comprises a first inverter, a second inverter, a third inverter, and a fourth inverter connected in series, wherein the input of the first latch circuit is connected to an input of the first inverter and an output of the fourth inverter and the output of the first latch circuit being connected to an output of the second inverter and an input of the third inverter. The control circuit of any preceding claim, wherein the first and second transistors are p-channel transistors. The circuit of any preceding claim, wherein the sources of the first and second transistors are connected to a positive upper power supply voltage. The circuit of any preceding claim, wherein the first and second gates are pass gates. The circuit of claim 13 wherein, said first and second transistors (P1;P2) are sized relative to the transistors of said first and second gates (Gl; G2) respectively to overcome the outputs of said first and second gates.

Inventors: MCCLURE DAVID CHARLES, MCCLURE, DAVID CHARLES
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1994
Main classification: H03K19
IPC codes: G11C11, H03K19, G11C16, G11C17