SYSTEM FOR ALLOCATING TASKS BETWEEN TWO ACTUATORS SERVICING THE SAME MAGNETIC DISK MEDIA IN A SINGLE DISK DRIVE

Abstract: A task assigning system within a dual actuator disk drive system wherein each task has a cylinder address comprising a plurality of registers, each register having a unique address and a plurality of fields for storing a task including the cylinder address associated with the tasks, a queue RAM (14) comprising a header register, the header register having a plurality of fields, an insertion means for inserting and ordering the registers into the queue RAM (14) when a task is first stored into the register, a first means (28) for assigning tasks stored in the queue RAM (14) to a first actuator (63) of the dual actuators in the sequence of increasing value of the cylinder addresses of tasks stored in the registers in the queue RAM (14) and a second means (30) for assigning tasks stored in the queue RAM (14) to a second actuator (61) of the dual actuators (63, 61) in the sequence of decreasing values of the cylinder addresses of the tasks stored in the registers in the queue RAM (14).

Description: SYSTEM FOR ALLOCATING TASKS BETWEEN TWO ACTUATORS SERVICING THE SAME •MAGNETIC DISK MEDIA IN A SINGLE DISK DRIVE A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any one of the patent documents or the patent disclosure as it appears in the United States Patent & Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. CROSS-REFERENCE TO RELATED APPLICATIONS DISK DRIVE SYSTEM USING MULTIPLE EMBEDDED QUADRATURE SERVO FIELDS, Serial No. 07/386,504, filed July 27, 1989, assigned to the assignee of the present application; ADAPTIVE READ EQUALIZER WITH SHUTOFF MODE FOR DISK DRIVES, Serial No. 07/559,899, filed July 30, 1990, assigned to the assignee of the present application; DISK DRIVE SYSTEM EMPLOYING ADAPTIVE READ/WRITE CHANNEL CONTROLS AND METHOD OF USING SAME, Serial No. 07/420,371, filed October 12, 1989, assigned to the assignee of the present application; HIGH PERFORMANCE DISK DRIVE ARCHITECTURE, Serial No. 07/612,427, filed November 9, 1990, assigned to the assignee of the present application; MULTIPLE ACTUATOR DISK DRIVE, Serial No. 07/614,853, filed November 9, 1990, assigned to the assignee of the present application; and SYSTEM FOR DYNAMICALLY ALLOCATING MEMORY REGISTERS FOR FORMING PSEUDO QUEUES, Serial No. 08/007,199, filed January 21, 1993, assigned to the assignee of the present application. Each of these related applications is hereby incorporated by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention is generally related to hard disk drives and disk drive electronic control systems. In particular, the present invention relates to a system for allocating tasks between two actuators serving the same magnetic media within the disk drive system. Description of the Related Art All disk drives have the common problem of the delay associated with the mechanical latency incurred while the read/write transducer is moved to the correct track on the surface of the disc. One solution for reducing the mechanical latency is the employment of two or more actuators for placing transducers over desired tracks on the disk surface. Two actuators interacting with the same magnetic media allows two different functions to be performed at the same time on the same magnetic media thereby increasing the efficiency of the system. Data management routines have been used to select which actuator should be assigned a specific task so as to minimize the amount of travel the actuator assigned has to travel to start the next task assigned to that actuator. One such data management method is to provide a task queue in which the tasks are placed in the order in which they are received by the disk drive controller. The tasks are then assigned on a first in first out basis to the first actuator to become available for assignment. Another approach is to assign the task within the queue that would require the least amount of travel of the available actuator thereby minimizing the latency time to place the actuator's transducer over the proper track to perform the designated task. The first method, while insuring the priority of the sequence of tasks assigned to the disk drive, still suffers from latency of large movements of the actuator from task to task. The second process, while minimizing the latency time for placing the actuator for the next task may result in a given task not being serviced for a long period of time. The problem of the mechanical latency of the movement of the actuators to the desired track is interrelated with the system's overall efficiency to provide service to a specific task. SUMMARY OF THE INVENTION It is an object of the invention to provide a system which has a low mechanical latency time associated with the positioning of a transducer over a desired track and the ordering of tasks to yield the maximum overall efficiency of the disk drive system. It is another object of the invention to provide a system that allocates tasks to a first actuator as it moves from the outer diameter to the inner diameter of the usable surface of the disk and task to a second actuator as it moves from the inner diameter to the outer diameter of the usable surface of the disk. The present invention assigns tasks to CHANNEL A having actuator A or to CHANNEL B having actuator B. CHANNEL A and CHANNEL B are completely independent of each other and have their own read/write circuitry, track following systems, error correction systems, data buffer and sequencer and control microprocessors. A queue is maintained within the memory for the main microprocessor of the disk drive system for storing information as to each task that is received by the disk drive system. Each register within the queue has a field which indicates the cylinder address associated with the task associated with that register, a "next" field which indicates the address of the register within the queue that has the next highest cylinder address for a task within the queue, a "previous" field which indicates the address of the register within the queue that has the next lowest cylinder address for a task within the queue and a "taken" field indicating whether or not the task is presently being processed. When a task is completed, the register associated with the task will indicate the next task to be assigned to the actuator. If the actuator employed was the actuator moving from the outer diameter to the inner diameter of the disk, then the actuator will be directed to the register indicated in the "next" field. Conversely, if the actuator employed was the actuator moving from the inner diameter to the outer diameter, then the actuator will be directed to the register indicated in the "previous" field. When the actuator moving from the outer diameter to the inner diameter has completed the last task that it can process before reaching the inner diameter, the actuator will be directed to the next task to be processed which is closest to the outer diameter. In similar fashion, when the actuator travelling from the inner diameter to the outer diameter has completed the last task capable that it can process before reaching the outer diameter, the actuator will be directed to the next task to be processed which is closest to the inner diameter. In that actuator A will move orderly across the surface of the disk from the outer diameter to the inner diameter while actuator B will orderly move across the disk from the inner diameter to the outer diameter, it can be realized that all tasks, placed within the queue prior to the actuators starting to transversa the disk surface, will have been serviced when both actuator A and actuator B have made one complete pass across the surface of the disk. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with respect to the particular embodiments thereof and reference will be made to the drawings, in which: FIGURE 1 is a logic diagram of a dual disk drive actuator system embodying the invention. FIGURE 2 is a diagram of a queue register illustrating various fields within the queue. FIGURE 3A through 3H is a series of examples illustrating the system in progress. FIGURE 4 is a flow chart of the routine for inserting a new task into the queue. FIGURE 5 is a flow chart of the routing for removing a completed task from the queue. FIGURE 6 is a flow chart of the routine for assigning the next task for CHANNEL "A". FIGURE 7 is a flow chart of the routine for assigning the next task for CHANNEL "B". DESCRIPTION OF THE PREFERRED EMBODIMENTS The dual disk drive actuator system which embodies the invention is show in Figure 1. The host processor (not shown) is connected via a BUS (not shown) to host interface controller 11 via line 10. Line 10, while shown as a single line, may in fact be comprised of a plurality of lines for communicating with the BUS system as required by the specific BUS system used. Micro¬ processor 12 controls the operation of the overall system. Microprocessor 12, ROM 13, RAM 14, host interface controller 11, buffer sequencer A 28 and buffer sequencer B 30 are interconnected by BUS 15. Microprocessor 12 controls the high level functions of the disk drive system and the receiving and sending of data and commands through host interface controller 11 to and from the host processor. Microprocessor 12 also assigns tasks and provides commands to two independent Channels, CHANNEL A and CHANNEL B. CHANNEL A is comprised of a memory buffer 27 which is controlled by a buffer sequencer 28. Data is transmitted under controller buffer sequencer 28 via line 26 to and from the memory buffer 27 to the host interface controller 11 and to and from disk 65 via read/write circuitry 53. The address for receiving and/or sending data from buffer memory 27 is provided on line 31 by buffer sequencer 28. Buffer sequencer 28 is connected via lines 20 to BUS 15 to form a communication path between microprocessor 12 and CHANNEL A. The buffer sequencer is further connected via lines 32 to BUS 41 to the microprocessor 43 for controlling the operation of CHANNEL A. Microprocessor 51 is connected via lines 43 to BUS 41 to communicate with its associated ROM 37 via lines 39 and the actuator controller 52 via lines 45. Read/write circuitry 53 records and retrieves data via transducer 64 from disk 65. The data path from the disk is transducer 64 to read/write circuitry 53 to buffer sequencer 28 to memory buffer 27. Actuator controller 52 is connected to read/write circuit 53 for obtaining servo information, sector marks and track information from the data recovered by read/write circuitry 53. Actuator controller 52 controls actuator 63 via control lines 57. Microprocessor 12 assigns specific tasks to CHANNEL A by sending the task via BUS 15, buffer sequencer 28 to microprocessor 51. Microprocessor 51 will control the performance of the assigned task of retrieving or recording the data stored in memory buffer 27 to or from disk 65. Microprocessor 51 controls the track seek operation, the track following operation and the recording and recovery of data on the magnetic surface of disk 65. CHANNEL B is identical in structure to CHANNEL A having memory buffer 29, buffer sequencer 30, microprocessor 54 with its associated ROM 38, actuator control 55, read/write circuitry 56, actuator 61 and transducer 62. As can be seen, both memory buffers 27 and 29 are interconnected to host interface controller 11 as are buffer sequencers 28 and 30. Microprocessor 12 in conjunction with buffer sequencers 28 and 30 controls the transfer of data between memory buffers 27 and 29, host interface 11 and the host processor. A queue, of a plurality of registers, is physically embodied within RAM 14. Microprocessor 12 receives tasks from various processors via lines 10 through host interface controller 11. One of the functions of microprocessor 12 is to control the allocations of the tasks between CHANNEL A and CHANNEL B. For each task received by microprocessor 12, a register is assigned within the queue. Figure 2 illustrates a register within the queue for controlling the assignment of tasks to CHANNEL A and to CHANNEL B. Referring to Figure 2, the register 100 has a plurality of fields, four of which are specifically shown and used within the invention. The "previous" field 102 contains the address of the queue register that has the next lowest cylinder address when compared to the register's own cylinder address. The "next" field 103 contains the register address of the queue register that has the next highest cylinder address when compared to the register's own cylinder address. The "taken" field 104 is marked as taken once the task associated with the register has been assigned to a specific channel for processing and is not cleared until the task has been successfully completed. To this end, even though the actual transfer of data to or from disk 65 has been completed to or from the memory buffer of the assigned channel, the "taken" flag will not be removed until the data transfer has been indicated as successful. For example, if CHANNEL A was given a task to recover data from the disk, the task will be completed when the last byte of the requested data is stored in memory buffer 27. CHANNEL A is available to accept a new assignment and move the actuator to the new track location. Microprocessor 12 will then transfer the data from the memory buffer via host interface controller to the requesting host processor. Not until the host processor indicates that it has successfully received the data transmitted from the disk drive system will the "taken" flag be reset freeing the system to mark the register as empty. By this method, the integrity of the data on the disk is maintained until the task requesting the data has been concluded. The "register address" field 101 is arbitrary and is shown in this embodiment for ease in describing the procedures for allocating tasks to the two channels. Microprocessor 12 maintains an empty queue to indicate which registers in the queue are empty and thus available for a new assigned task. The empty queue may take on many different forms. It can be a bit map of the registers of the queue where each bit corresponds to a specific register and indicates whether that register is being used within the queue or is empty and available for a new assignment. Another method would be to list the addresses of the registers in the queue and maintain an associated field indicating whether the register for that address is presently being used. A third method would be to keep a sequential list of the addresses of registers that are not in use. A register's address being in the empty queue is, in and of itself, an indication that the register is available for an assignment of a task. The procedure for maintaining such a list of empty registers by any of the foregoing procedures is well within the skill of an ordinary practitioner familiar with writing programs in microcode. Figure 4 sets forth the routine for the insertion of a new task into the queue. This occurs when the microprocessor 12 receives a new task to be performed by the system. Microprocessor 12 is capable of storing a plurality of tasks and allocates those tasks to be processed via CHANNEL A or CHANNEL B. When a task is received by microprocessor 12, the task will include the identification of the source of the task, the number of blocks of data to be transferred and an unique identification address of where the data should be written to or read from by the disk drive. The identification address is translated by the disk drive into unique cylinder, head and sector addresses for the new task which are stored in the task register assigned to the new task. The system will assign each new task to the task register in the empty queue which has the lowest task register address. Although Figure 1 only shows one disk, it should be understood that there can be a plurality of stacked disks with interleaving actuator arm assemblies with corresponding transducers for communicating with both sides of each disk. Each of the two actuators therefor can be comprised of a plurality of actuator arms where each arm carries a transducer for addressing a specific magnetic surface of one of the disks. The recording technique used for recording data on the disk is to record the data in consecutive tracks on the disk. This is a departure from the recording scheme from where the data is recorded in cylinders, that is first on track one on side one of disk one, then on track one of side two of disk one, then track one on side one of disk two, and then on track one of side two of disk two, etc, until the data is recorded. Here the data is not recorded through cylinders but rather across the surface of a single magnetic disk. It is possible that a data block may start on the surface of one disk and then overflow to the surface of another disk. There is a plurality of task registers, each having a distinct address, which are inserted into and removed from a queue. The queue is made up of a header register which defines that structure of the queue and links the task registers inserted into the queue. The header register has a unique address h and contains two fields, a "previous" field containing the address of the task register having the highest address in the queue or the header address h if the queue is empty and a "next" field containing the address of the task register having the lowest address in the queue or the header address h if the queue is empty. Referring to Figure 4, the routine is there shown for inserting a new task into the queue. The routine will first go to the header register, step 200, and determine if the address stored in "next" field is the header address, step 201 . If it is the header address then the routine will branch and enter step 204 as option (A) . If it is not the header address then the routine will go to the register, hereinafter referred to as the present register, whose address is stored in the "next" field of the register being tested, step 202, and perform the test of step 203. This test compares the cylinder address stored in the cylinder address field of the present register with the cylinder address associated with the task to be stored. If the task's cylinder address is equal to or less than the cylinder address stored in the present register, the routine will branch and enter step 204 as option (B) . If the task's cylinder address is greater than the cylinder address stored in the present register, the routine will branch back to step 201 and test the "next" field of the present register for the header address. If the "next" field of the present register contain the header address, the routine will branch and enter step 204 as option (A) . This condition means that the task has the highest cylinder address of all tasks stored in the queue and will be stored in a task register having the highest address in the queue. If the "next" field of the present register does not have the header address stored therein, the routine will go to the register whose address does appear in the "next" field of the present register, step 203, and that newly addressed register becomes the present register in the routine. The routine loops on steps 203, 201 and 202 until the routine exits the loop from either step 201 as option (A) or step 203 as option (B) . Step 206 will store the new task into the task register, hereinafter referred to as the selected register, in the empty queue that has the lowest task register address. If step 204 was entered as option (A) then option (A) choices will be followed in step 205, 206, 208 and 209. Step 205 makes the "previous" field of the selected register equal to the "previous" field of the header register. Step 206 makes the "next" field of the selected register equal to the address of the header register. Step 207 will make the "next" field of the present register equal to the address of the selected register. Step 208 will make the "previous" field of the header register equal to the address of the selected register. The selected register's address is then removed from the empty register queue since the selected register has now effectively been reinserted actively into the queue of tasks. If step 204 was entered as option (B) then option (B) choices will be followed in step 205, 206, 208 and 209. Step 205 makes the "previous" field of the selected register equal to the register address contained in the "previous" field of the present register. Step 206 makes the "next" field of the selected register equal to the address of the present register. Step 207 will make the "next" field of the register indicated in the "previous" field of the present register equal to the address of the selected register. Step 208 will make the "previous" field of the present register equal to the address of the selected register. The selected register's address is then removed from the empty register queue since the selected register has now effectively been reinserted actively into the queue of tasks. Figure 5 is the routine for removing a completed task from the queue. This condition will exist when a task has been successfully completed such that the task may be safely removed from the queue. This condition is recognized by the microprocessor 12 in step 300. Step 301 makes the "next" field of the register indicated in the "previous" field of the completed register equal to the "next" field of the completed register. Step 302 makes the "previous" field of the register indicated in the "next" field of the completed register equal to the "previous" field of the completed register. Step 303 sets the "taken" fields of the completed register to zero. Finally, the address of the completed register will be entered in the empty queue as being a task register which can be assigned a new task. Figure 6 is the routine for assigning the next task for CHANNEL A. As previously described, step 400 will determine if the last byte of the current task for the register being serviced by CHANNEL A has been completed. Since the actuator may now be moved to the location for the next task, microprocessor 12 must determine what the next task for CHANNEL A will be. Step 401 checks the "next" field of the current register to determine if the "next" field is equal to the queue address of the header register and if so step 402 which causes the processor to interrogate the register indicated in the "next" field of the header by step 403. If the "next" field in the current register is not the queue address for the header, then the routine proceeds directly to step 403. Step 403 tests the "taken" field of the register whose address is indicated in the "next" field of the current register. If the "taken" field indicates that the register is taken, step 404 will cause the system to interrogate the register indicated in the "next" field of this taken register by branching to step 401. When the conditions of 401 and 403 are properly met, step 405, the current register, not being the header register or a taken register, will be marked as taken and step 406 will assign the task associated with that register to CHANNEL A for processing. CHANNEL A will therefor begin to move the actuator to the cylinder address of the register marked taken and whose task has been assigned to CHANNEL A. Figure 7 is the routine for assigning the next task for CHANNEL B and comprises steps 500, 501, 502, 503, 504, 505 and 506. The routine for CHANNEL B is exactly the same for the routine for CHANNEL A except that the assigned task of the register that has been marked as taken by step 505 will be assigned to CHANNEL B for processing by step 506. The invention will be further described by means of the examples shown in Figure 3A through Figure 3H. In this example, there are seven task registers having addresses 1 through 7 and a header register having address h. It should be understood that any number of task registers can be used and this will depend on how many tasks the designer of the system wishes micro¬ processor 12 to store in the queue for processing. Figure 3A shows the queue being empty and the header register's "previous" and "next" fields both being equal to the header address h. Task registers 1 through 7 are empty and their addresses are listed in the empty queue as being available for insertion into the queue. The queue at this time is comprised only of the header register. Assume that task 1 is received by processor 12 and has a cylinder address of 56. The routine of Figure 4 will perform steps 200, 201, 204, 205A, 206A, 207A and 208A in that order to store task 1 in register 1 and place register 1 in the queue. When the routine is completed the queue will contain the header register and register 1. At step 201 the routine will branch to step 204 as option (A) since the "next" field of the header contained the header address h. Step 204 will have task 1 stored into register 1 since the lowest task register address in the empty queue was the address of register l. Register 1 is the selected register in the routine for the following steps. Step 205A makes the "previous" field of register 1 equal to the address in the "previous" field of the header which is the header address h. Step 206A makes the "next" field of register 1 equal to the header address h. Step 207A makes the "next" field of the header register equal to 1, the address of register 1. Step 208A makes the "previous" field of the header register equal to 1, the address of register 1. The system will then assign task 1 to CHANNEL A by default and will set a 1 into the "taken" field of register 1. Figure 3B shows the state of all registers after the routine has been completed. Next assume that task 2 having cylinder address 102 is received by microprocessor 12. the routine of Figure 4 will perform steps 200, 201, 202, 203, 201, 204, 205A, 206A, 207A and 208A in that order. The routine will go to register 1 by steps 200, 201 and 202 since the "next" field of the header register contained the address for register 1. Step 203 determines that the cylinder address of task 3 is greater than the cylinder address stored in register 1 and goes to step 201. Step 201 determines that the "next" field of register 1 is equal to the header address and therefor branches to step 204 as option (A) . Step 204 will have task 2 stored into register 2 since the lowest address contained in the empty queue is that of register 2. At this time the present register is register 1 and the selected register is register 2. Step 205A makes the "previous" field of register 2 equal to the address in the "previous" field of the header which is 1. Step 206A makes the "next" field of register 2 equal to the header address h. Step 207A makes the "next" field of register 1 equal to 2, the address of register 2. Step 208A makes the "previous" field of the header register equal to 2, the address of register 2. The system will then assign task 2 to CHANNEL B by default and will set a 1 into the "taken" field of register 2. Figure 3C shows the state of all registers after the routine has been completed. The queue now contains the header register, register 1 and register 2 ordered in that order. Next assume that task 3 having cylinder address 76 is received by microprocessor 12. The routine of Figure 4 will perform steps 200, 201, 202, 203, 201, 202, 203, 204, 205B, 206B, 207B and 208B in that order. The routine will go to register 1 since steps 200, 201 and 202 are directed by the address in the "next" field of the header register. The routine will then go to register 2 since its address is stored in the "next" field of register 1 as the result of the test of steps 203 and 201 were both negative. The test of step 203 determines that the cylinder address of task 3 is less than the cylinder address stored in register 2 and branches to step 204 as option (B) . Step 204 will have task 3 stored into register 3 since the lowest task register's address stored in the empty queue is that of register 3. At this time the present register is register 2 and the selected register is register 3. Step 205B makes the "previous" field of register 3 equal to the address in the "previous" field of register 2 which is equal to 1. Step 206B makes the "next" field of register 3 equal to the address of register 2. Step 207B makes the "next" field of register 1 equal to 3, the address of register 3. Step 208A makes the "previous" field of the register 2 equal to 3, the address of register 3. The queue now contains the header register, register 1, register 3 and register 2, in that order. Effectively register 3 has been inserted into the queue between register 1 and register 2 and the queue has been ordered in accordance with the cylinder addresses stored within each of the registers in the queue. Figure 3D show the status of all registers after the routine of Figure 4 has been completed. Next assume that task 4 using cylinder 66 is received by microprocessor 12. The routine for Figure 4 will perform the steps of 200, 201, 202, 203, 201, 202, 202, 204, 205B, 206B, 207B and 208B in that order. The routine will go to register 1 since steps 200, 201 and 202 are directed by the address in the "next" field of the header register. The routine will then go to register 3 since its address is stored in the "next" field of register 1 as the result of the test of steps 203 and 201 were both negative. The test of step 203 determines that the cylinder address of task 4 is less than the cylinder address stored in register 3 and branches to step 204 as option (B) . Step 204 will have task 4 stored into register 4 since the lowest task register's address stored in the empty queue is that of register 4. At this time the present register is register 3 and the selected register is register 4. Step 205B makes the "previous" field of register 4 equal to the address in the "previous" field of register 3 which is equal to 1. Step 206B makes the "next" field of register 4 equal to 3, the address of register 3. Step 207B makes the "next" field of register 1 equal to 4, the address of register 3. Step 208A makes the "previous" field of the register 3 equal to 4, the address of register 4. The queue now contains the header register, register 1, register 4, register 3 and register 2 in that order. Effectively, register 4 has been inserted into the queue between register 1 and register 3 and the queue has been ordered in accordance with the cylinder addresses stored within each of the registers in the queue. Figure 3E show the status of all registers after the routine of Figure 4 has been completed. Assume that the task 5 using cylinder 120 is now received by microprocessor 12. Further, the last byte of task 1 associated with register 1 has been sensed. Before an assignment of a task to a channel can be made, all new tasks received by the microprocessor 12 that have not been inserted into the queue must be inserted into the queue. Therefor task 5 dealing with cylinder 120 will first be inserted into the queue before any further action of reassignment of the next task to CHANNEL A will be done. The routine of Figure 4 performs the steps of 200, 201, 202, 203, 201, 202, 203, 201, 202, 203, 201, 202, 203, 201, 204, 205A, 206A, 207A and 208A in that order. In this process the routine will loop three times before finally exiting the loop at step 201. Step 204 will have task 5 stored into register 5 since that is the lowest register address stored in the empty queue. At this time the present register is register 2 and the selected register is register 5. Step 205A makes the "previous" field of register 5 equal to the address in the "previous" field of the header which is 2. Step 206A makes the "next" field of register 5 equal to the header address h. Step 207A makes the "next" field of register 2 equal to 5, the address of register 5. Step 208A makes the "previous" field of the header register equal to 5, the address of register 5. The queue now contains the header register, register 1, register 4, register 3 , register 2 and register 5 in that order. Effectively, register 5 has been inserted into the queue between register 2 and the header register h and the queue has been ordered in accordance with the cylinder addresses stored within each of the registers in the queue. Figure 3F show the status of all registers after the routine of Figure 4 has been completed. Now that task 5 has been inserted into the queue, the process can now address the reassignment of CHANNEL A. Referring to Figure 6, in step 400 the system will have sensed that the last byte of task 1 assigned to register 1 has been completed. At this time the contents of the registers in the queue are shown in Figure 3F. The "next" field of register 1 points to register 4 and therefor step 403 is performed. Since register 4's "taken" field, as shown in Figure 3E, indicates that the task assigned to register 4 is not being processed, task 4 is assigned to CHANNEL A and the "taken" field of register 4 is changed to a 1 to mark register 4 as taken. It should be noted that three registers are indicated as taken within the queue even though only two tasks are actually being serviced by the actuators. This is because register l's task, although the data transfer requiring the use of the actuator has been completed, the total task has not been completed by the disk drive system. CHANNEL A will now be given the information regarding task 4 such that it can begin moving the actuator to cylinder 66 in contemplation of performing that task. Assume that task 1 has now been successfully completed such that it may be removed from the queue. The routine set forth in Figure 5 is therefor implemented. Steps 301 will make the "next" field of the header register equal to 4, the address stored in the "next" field of completed register 1. Step 302 will make the "previous" field of register 4 equal to h, the address stored in the "previous" field of completed register 1. The "taken" field of register 1 is set to 0. The address of register 1 is also listed in the empty queue as being available for a new task. The queue now contains the header register, register 4, register 3, register 2 and register 5 in that order. Effectively, register 1 has been removed from the queue and the registers in the queue are still ordered by the cylinder addresses stored in the queue registers. Figure 3G shows the status of all registers after the routine of Figure 5 has been completed. Assume that task 6 using cylinder 103 is next received by microprocessor 12 and that the last byte associated with task 2 has been sensed. Once again the new task will be inserted into the queue before any reassignment of task can take place. The routine of Figure 4 will perform the steps of 200, 201, 202, 203, 201, 202, 203, 201, 202, 203, 201, 202, 203, 204, 205B, 206B, 207B and 208B in that order. The routine has looped three times and on the fourth pass exited the loop at step 203 and branched to step 204 as option (B) . Step 204 will have task 6 stored in register 1 since the lowest register address in the empty queue is that of register 1. At this time the present register is register 5 and the selected register is register 1. Step 205B makes the "previous" field of register 1 equal to the address in the "previous" field of register 5 which is equal to 2. Step 206B makes the "next" field of register 1 equal to 5, the address of register 5. Step 207B makes the "next" field of register 2 equal to 1, the address of register 1. Step 208A makes the "previous" field of the register 5 equal to 1, the address of register 1. The queue now contains the header register, register 4, register 3, register 2, register 1 and register 5 in that order. Effectively, register l has been inserted into the queue between register 2 and register 5 and the queue has been ordered in accordance with the cylinder addresses stored within each of the registers in the queue. Figure 3H shows the status of all registers after the routine of Figure 4 has been completed. Referring to Figure 7, in step 500 the system will sense that the last byte of task 2, which was assigned to CHANNEL B, has been completed. Assignment of tasks to CHANNEL B is controlled by the "previous" fields of the registers in the queue. The "previous" field of register 2 points to register 3. Since register 3's "taken" field is 0, task 3 will be assigned to CHANNEL B for processing. Register 3's "taken" field will be set to a 1 indicating that the task associated with register 3 is being processed. It should be noted that the next task for CHANNEL B was directed to register 3 with a cylinder address of 76 even though register 1 had a cylinder address of 103 which was only one cylinder away from the cylinder address of 102 for the completed register 2. This is because the system follows an orderly process by which CHANNEL B will always be assigned to the register having the next lowest cylinder address. The routines set forth in Figures 4, 5, 6 and 7 are controlled by microcode stored within RAM 14 and executed by microprocessor 12. The invention as described heretofore uses known digital software implementation and the microprogram was assembled using Motorola 68C11 Assembler, Series 5.0. , which is provided in Appendix A. The program of Appendix A carries out the functions of the routines of the flow charts as shown in Figures 4, 5, 6 and 7 and performs the steps for allocating the task to CHANNEL A or B in accordance with the rules heretofore set forth. It should be understood that the method can be embodied in other microprograms using other programming languages or can be store in a read-only memory within a computer system. It is also possible for the queue to be a physical queue comprised of separate hardware registers whose contents can be read by microprocessor 12. The function of microprocessor 12 can be designed for implementation by a hardware state machine dedicated to perform the functions necessary to carry out the routines described herein. While the invention has been particularly shown and described with reference to the preferred embodiment therefor, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention. Given the above disclosure of general concepts and specific embodiments, the scope of the protection sought is defined by the following claims. APPENDIX A Conner Peripherals , Inc . 1992 13283 13284 1328S 13286 13287 13288 13289 13290 13291 13292 13293 13294 13295 13296 13297 13298 13299 13300 13301 13302 13303 13304 13305 ΛA9A QTOEHPTY 13306 J3307 AA9A SEI ,Don t allow Interrupts while we 13308 . are adiustlng pointers 13309 .remove this CQE Iro current queue 13310 AA9B tOX <S PRV.Y .point X to previous entry 13311 AA9E EDO <S~NXT,Y , get next ol removed queue 13312 AAA1 STD <S~NXT,X . store in neit ol previous entry 13313 13314 AAA3 tDX <S_NXT.Y , point X to next entry 13315 AAA6 tOD <S~PRV Y , get previous ol removed queue 13316 AAA9 STD ( S^PRV.X , store in previous ol next entry 13317 13318 .insert new CQE into empty queue 13319 AAAB cε π C8 IDX IV EMPTY .Get queue header 13320 AAAE EE oo tDX <S~PRV,X , point to last CQE in queue 13321 AABO IA IF 02 STY <S " NXT, X , point neit pointer to new CQE 13322 AAB3 CD £F 00 STX <S~PRV. Y , point prev pointer ol new CQE to last entry 13323 13324 AAB6 CE 11 tDX #V EMPTY . Get queue header 13325 AAB9 1A EF STY <S~PRV, X , point previous to new CQE 13326 AABC CD EF STX ( S ' MXT.Y , point next ol new CQE to header 13327 13328 AABF OE CLI , Interrupts OKAY now 13329 13330 AACO 39 RTS .Return to post status and sense 13331 13332 13333 13334 13335 13336 13337 13338 13339 13340 13341 13342 13343 13344 13345 13346 13347 13348 13349 13350 13351 13352 13353 AAC1 QT02CHAN 13354 13355 AAC1 OF SEI .Don t allow interrupts while we 13356 , are adjust ing pointers 13357 remove this CQE Irom current queue point X to previous entry get next of removed queue store in next of previous entry point X to next entry get previous of removed queue store in previous of next entry ;G«t queue header point to last CQE in queue point next pointer to new CQE point prev pointer of new CQE to last retry tDX IV 2CHAN Get queue header STY <S"PRV,X point previous to new CQE STX <S~NXT,Y point next of new CQE to header C l ; Interrupts OKAY now RTS ; Return to post status and sense NAME: QTOSTAT PURPOSE: Move the CQE (Cooraand Queue Entry) to the status queue THEORY: Y points to the CQE to be moved. Since it is possible for the host to be connected to the process to give status, QTOSTAT checks for this condition and places tbe queue at the bead if tbe host is alreaoy connected. EXIT: NONE AUTHOR: Steve Cornaby DATE: 8 Aug 1990 HISTORY: QTOSTAT. ;Don't allow interrupts while we ; ■ " ■ "•TEST**"" ; are adjusting pointers rent queue ; oint X to previous entry ; get next ol removed queue ; store in next ol previous entry ; point X to next entry ; get previous ol removed queue ; store in previous ol next entry ;Get queue header ;Sιι if we are currently connected ; request at head, If not, it tail ; point to last CQE In queue QTOS05: ; point next pointer to new CQE ; point prev pointer of new CQE to last entry :Get queue haader ; point previous to new CQE : point next of new CQE to header d e 13508 EXIT: 13509 NONE 1' ' 1 13s._ AUTHOR: Steve Cornaby 13513 DATE: 8 Aug 1990 13514 HISTORY: 13515 13516 13517 13518 AB3D QT01CHAN: 13519 13520 AB3D OF SEI ;Don't allow intsrrupts while we 13521 ; are adjusting pointers 13522 AB3E 18 ED 09 STD <S EXCTADD.Y ;S(orι continuing execution address 13523 13524 ; remove this CQE from current queue 13525 AB41 tDX <S PRV.Y ; oint X to previous entry 13526 AB44 LDO <S~NXT,Y ; get next ol removed queue 13527 AB 7 STD <S~NXT,X : store In next of previous entry 13528 13529 AB49 point X to next entry 13530 AB4C get previous of removed queue 13531 AB4F store In previous of next entry 13532 13533 ; insert new CQE into 1 channel queue 13534 AB51 X IV 1CHAN ;Git queue header 13535 AB54 point to last CQE in queue 13536 AB56 point next pointer to new CQE 13537 AB59 point prev pointer of new CQE to last entry 13538 13539 AB5C tDX IV 1CKAN Get queue header 13540 ABSF STY <S " PRV.X point previous to new CQE 13541 AB62 STX <S " NXT,Y point next of new CQE to header 13542 13543 13544 AB65 OE C l , * Interrupts OKAY now 13545 AB66 39 RTS ; eturn to post status and sense 1 13... 13549 NAME: QTO10R0 13550 13551 PURPOSE: Move the CQE (Command Queue Entry) to the Ichannel queue 13552 and order it. 13553 13554 13555 THEORY: 13556 Y points to the CQE to be moved. 13557 D contains execution address when execution continues. 13558 The Ichannel queue is traversed and the destination address 13559 compared against that of the new command. When traversal 13560 Is complete, X will be pointing to the CQE before which the 13561 current CQE Is to be placed. 13562 13563 13564 EXIT: 13565 NONE 13566 13567 13568 AUTHOR: Steve Cornaby 13569 DATE: 8 Aug 1990 13570 HISTORY: 13571 13572 13S73 13574 AB67 QT010RD: 13575 13576 AB67 OF SEI -Don't allow interrupts while we 13577 ; are adjusting pointers 13578 13579 ;*' Set up continue address 13580 13581 AB68 18 ED 09 STD <S_EXCTADD,Y ;Store continuing execution address \V "> " Remove this CQE from current queue tDX <S PRV. point X to previous entry too -S~NXT, get next of removed queue STD <S~NXT, store In next of previous entry tDX <S NXT, point X to next entry tDD <S " PRV, get previous of removed queue STD <S " PRV. store in previous of next entry CLI 'Allow interrupts now Check to see If lchan queue empty ;Get Ichannel queue pointer ; Point to first entry , end iI queue empty 'Branch if not empty :Stt non-sequential flag ORD05. Command with which we arc comparing may be directed If so, It doesn't count for tbe compare. Continue with the next CQE BRSET <S_QSTAT,X,SB_0RCTD,ORD50 ;βranct if directed coimiand 0R010. Command not directed. Compare destination cylinder of new CQE against destination cylinder of lchan CQE. Branch to insert if new less than lchan. too <S DCYL.X Get destination of lchan CQE CPD <S~DCYl,Y subtract destination cylinder new CQE BIS ORD15 branch if NEW command fits before or is on same cylinder as ICHAN coimiand tDAA Set non-sequential command BRA ORD100 New command is greater than lchan CQE command. Check to see if it Ichannel command is Iinked to tbe next command. 0RD15: BRCLR <S_CSTAT,X,SB_C KED.ORD20 ;Branch if command not linked LDX <S~NXT,X ~ ;Get nut command to check it out CPX IV ' ICHAN ;Check if at end BNE 0R015 : branch if not LDAA 01 'AccA l» 0 means non-sequential BRA OR0100 , Insert at end if we are 0RD20. Check II command can be coalesced. First priority is to check If it Is tbe same type of command Get op code check if matches candidate CQE Oiflerint op codes. ;Get 1st L6A past old command ; compare against first LBA of new command ;βranch il not sequential : High byte 'Branch if not sequential Command was sequential Chick if coim-and is still II so, link It to tbe following command. SEI 'Disable interrupts until lchan ; queue is updated tDAA 101 ;Use AccA as a flag IDAB <S DSXSTAT.X ;Get disk status BNE " ORD35 ; Nol executing If status already posted BSET <S CSTAT,X, SB CtNKED ;Set linked bit in old CQE BSET <S " CSTAT,Y,SB~BINKED ; and backward linked bit in new CQE ;** Check to see If command we are linking to Is currently active BRCtR <S_CSTAT,X, SB_CDATIN,OR035 ; Not executing If data not in buffar BRSET <S_QSTAT.X, SB_BCHAN,0RD30 ;Branch If executing on channel ;" Setup linked CQE with same attributes as currently executing CQE ; Set attributes for channel A BCtR <S_QSIAT,Y,SB_BCHAN Not B channel IDD 10 ;Get channel A offset STD <S CHANOFF.Y ; store in CQE channel offset BRA ORD35 ORD30: ;Set attributes for channel B BSET <S QSTAT,Y, SB CHAN Not B channel LDD I0020h ,°Get channel B offset STD <S_CHANOFF.Y *, store in CQE channel offset ORD35: tOX <S NXT.X :Point to following CQE >o new CQE ; will be inserted after old CQE BRA ORD1O0 ; Brancb to insert CQE ; ■ * new CQE is greater than or equal to Icban CQE. Move to the next ; lchan CQE and try again. 0RD50: ;Poi t to next entry ; Insert before end of lchan queue ; if pointing to last entry ; else branch lor another compare ORD100: Insert new CQE before Ichannel CQE destination ; Insert new CQE into 1 channel queue PSHX -Preserve CQE before which we will ; insert new CQE 10X <S PRV.X point to last CQE in queue STY <S " NXT,X point next pointer to new CQE STX <S " PRV,Y point prev pointer of new CQE to last entry PUtX ;Point at CQE STY <S PRV,X point previous to new CQE TX <S " NXT,Y point next of new CQE to header CU 'Allow interrupts TSTA ; et zero flag RTS ;Return to post status and sense NAME: CCHAN PURPOSE: Check If there are more entries In tbe Ichannel queue. Since channel commands can be directed, check tbe status byta to see which channel we art currtntiy servicing, and check for other diracted coi iands to that channel. If there are no directed commands for the channel, select the first CQE in tbe Ichannel queue and place It in tbe appropriate channel header. Then, clear tbe executing bit such that the kernel will start the new process. 13733 THEORY 13734 Y points to the currently executing CQE 13735 13736 The Ichannel queue is checked to see If II is empty If 13737 it Is empty then tbe address field of the currently 13738 exacuting channel is set to zero If tbe Ichannel queue 13739 is not empty, but there are no CQEs directed to tbe 13740 currently executing CQE, and no non-directed CQEs, the 13741 address field of the currently executing channel is again 13742 set to zero 13743 13744 The routine will search all Ichannel entries for directed 13745 commands, which are exβcutad first This occurs because 13746 diracted commands can be steps in the error recovery 13747 sequence, and tbe command may be partially complete In 13748 addition, read and write buffer commands are diractad 13749 commands 13750 13751 This routine Is also the location of more complex algoritblms 13752 lor CQE selection Since they are as yet undefined, the 13753 routine simply selects tbe first entry 13754 13755 •NOTE 1 13756 This routine can be called only after the current operation 13757 has bun removed Irom the Ichannel queue by calling QTOSTAT, 13758 etc 13759 13760 13761 EXIT 13762 NONE 13763 13764 13765 AUTHOR Steve Cornaby 13766 DATE 8 Sep 1990 13767 HISTORY 13768 13769 13770 AC07 CCHAN 13771 ,"* Since we mil be looking for directed commands, tbe 13772 routine splits to a checker for cbanA and cbanB 13773 [01] if TWOACT 13774 AC07 18 IE OB 80 33 BRSET <S_QSTAT Y SBJCHAN CCH19 .Branch if channel B Is ending 13775 [00] βndif 13776 ACOC CD EE 02 tDX <S NXT Y .Point to CQE after current CQE 13777 ACOF 20 02 BRA CCH02 13778 AC11 CCHOO 13779 ," ChanA Is ending Git next CQE, (il any) 13780 13781 AC11 EE 02 tDX <S_NXT X .Point to next CQE 13782 AC13 CCH02 13783 AC13 8C 11 00 CPX IV lChAN make sure il isn't header 13784 AC16 26 02 BNE CCH05 , branch to end i f it isn t 13785 13786 Wi are pointing to header We must skip tbe header and 13787 point to toe next CQE We are done when we are pointing 13788 to the CQE currently pointed to by ACHAN 13789 13790 AC18 EE 02 .Skip header and point to next CQE 13791 AC1A CCH05 13792 ."•"TEST 13793 13794 ACIA BC 11 61 ; check 11 we are done 13795 ACID 26 05 , Branch i f we are not 13796 AC1F CE 00 00 There are no other commands pending 13797 AC22 20 16 , so clear channel and end 13798 AC24 CCH10 13799 , •" We are pointing to next valid CQE 13800 ," Make sure it is not already being executed on a channel 13801 AC24 IE OB 02 E9 BRSET <S QSTAT.X.SB CHANtNK, CCHOO , branch il already linked 13802 AC28 IE OC 02 E5 BRSET <S~CSTAT, , SB~BtNKED, CCHOO , or if backward coalesced 13803 13804 AC2C IF OB 40 04 BRCtR <S QSTAT.X.SB DRCTD, CCH15 .Branch If not a directed coiπnand 13805 AC30 IE OB 20 DD BRSET <S~QSTAT,X. SB ' DIRB CCHOO .Branch if directed to other channel 13806 , " Command " directed fo tbls channel Point to it and end 13807 AC34 CCH15 Clear channel b bit and set channel Iinked bit CCHI8 Update ACHAN " • "TEST* * "" We arc finishing an operation on B channel Point to CQE l-tmediatcly after current CQE If TWOACT CCH19 LDX <S NXT.Y :Point to next CQE BRA CCH22 CCH20 ;* • ChanA Is ending Get next CQE, (if any) tDX <S_NXT,X .Point to next CQE CCH22 CPX IV ICHAN make sure it isn't header BNE CCH2S , branch to end If It isn't ;" We arc pointing to header We must skip tbe header and , point to tbe next CQE Wi are done when we are pointing to tbe CQE currently pointed to by BCHAN tDX <S_NXT.X .Skip header and point to next CQE CCH25 CPX V BCHAN , check it we are done BNE ~ CCH30 , Branch if we are not tDX lOOOOh , Then are no other command* pending BRA CCH38 so clear channel and end CCH30 ," We are pointing to next valid CQE ;" Make sure it is not already being executed on a channel BRSET <S QSTAT.X.SB CHANLNK,CCH20 , branch il already linked BRSET <S~CSTAT,X.SB ' BLNKED,CCH20 , or If backward coalesced BRCtR <S QSTAT.X.SB ORCTO,CCH35.Branch if not a directed command BRCtR <S " QSTAT.X,SB " 0IRB,CCH20.Branch if directed to other channel ," Coπnan " directed To this channel Point to it and end CCH35 BSET <S_QSTAT.X, B_BCHA»'SB_CHANLNK .Set channel and channel linked bits CCH38 STX V BCHAN .Update BCHAN endlf CCH1O0 SEI ,Turn off interrupts until done ,'* Clear out all antries from CNT queui that match the CQE just completed AccY points to CQE we are just finishing ,Sec what head is pointing at , Initialize AccD to zero .Point back oni entry on initialization CCHU5 . ook at valid entry . check if at tail ; branch to end it checked all entries , Check if CQE matches that just written , branch if no match toad with zeroes if matches to invalidate toop to look again CCH120 CLI .Allow interrupts again 13883 13884 AC87 39 RTS and return 13885 13886 13887 NAME: SCHAN 13888 13889 PURPOSE: A non-directed command has lust been placid in the Ichannel 13890 queue. The current status of tbe channels Is unknown. Scan 13891 tba channels to see If they are currently busy. If either Is 13892 not busy, copy the CQE pointer Into the channel command 13893 register. The kernal will detect an un-started command 13894 and start the channel command. 13895 13896 13897 THEORY: 13898 Y points to the CQE just moved to the Ichannel queue. 13899 13900 Channel A is checked to see if it is empty. The channel 13901 pointer will be zero If It is empty. If it is not empty, 13902 Channel B Is checked. If eitaer channel Is empty, the 13903 content] of Y will be written to il. The channel in 13904 process Is 0 as It Is a new command. The kernal samples 13905 for a channel pointer l-> 0 and a Channel in process » 0 13906 to know If It should begin a new command. 13907 13908 13909 EXIT: 13910 NONE 13911 13912 13913 AUTHOR: Steve Cornaby 13914 DATE: 11 Sep 1990 13915 HISTORY: 13916 13917 13918 AC88 HAN: 13919 ACS8 ;No interrupts while we mess with queue 13920 13921 13922 13923 AC89 Check i f channel A free 13924 ACSC branch if not 13925 AC8E Channel is free, tell kernal to start 13926 AC92 CQE Is now linked to a Channel 13927 ACS6 crancb to continue 13928 AC98 13929 AC98 Chick if channel A free 13930 AC9B branch if not 13931 AC9D Channel is free, tell kernal to start 13932 ACA1 CQE is now linked to a Channel 13933 13934 Chick if channel A free 13935 branch i f not 13936 Chinnel is free, tell kernal to start 13937 CQE is now linked to a Channel 13938 13939 [00] 13940 ACA5 13941 13942 ACA5 OE ; Interrupts are okay now 13943 13944 ACA6 39 13945 13946 13947 13948 NAME: FREEZQ 13949 13950 PURPOSE: 13951 An error condition occurred n tbe process. Freeze the Q 13952 so that no further operation: will occur on the channel 13953 until tbe host has a chance to do e command. Normally, tbe 13954 command would be a request sinse command, but if the host 13955 instead chooses to do another command. Queue processing will 13956 proceed normally. 13957

Claims: CLAIMS What is claimed is: 1. A task assigning system within a dual actuator disk drive system wherein each task has a cylinder address comprising: storage means for storing a plurality of tasks; a first means for assigning tasks stored in said storage means to a first actuator of said dual actuators in the sequence of increasing value of said cylinder addresses of said stored tasks; and a second means for assigning tasks stored in said storage means to a second actuator of said dual actuators in the sequence of decreasing value of said cylinder addresses of said stored tasks. 2. A task assigning system within a dual actuator disk drive system wherein each task has a cylinder address comprising: a plurality of registers, each said register having a unique address and a plurality of fields for storing a task including said cylinder address associated with said tasks; a queue comprising a header register, said header register having a plurality of fields; an insertion means for inserting and ordering said registers into said queue when a task is first stored into said register; a first means for assigning tasks stored in said queue to a first actuator of said dual actuators in the sequence of increasing value of said cylinder addresses of tasks stored in said registers in said queue; and a second means for assigning tasks stored in said queue to a second actuator of said dual actuators in the sequence of decreasing value of said cylinder addresses of said tasks stored in said registers in said queue. 3. The task assigning system of Claim 2 further comprising: a third means for storing a task in said register that is not inserted in said queue and has the lowest said register address. 4. The task assigning system of Claim 2 further comprising: a fourth means for identifying said addresses for said registers that are not inserted in said queue. 5. The task assigning system of Claim 4 further comprising: a third means for storing a task in said register that has the lowest address identified by said fourth means. 6. The task assigning system of Claim 2 wherein each of said registers includes a "next" field and a "previous" field where said "next" field is the address for said register in said queue having the next highest value for said cylinder address of a task and said "previous" field is the address for said register in said queue having the next lowest cylinder address of a task. 7. The task assigning system of Claim 6 further comprising: a third means for storing a task in said register that is not inserted in said queue and has the lowest said register address. 8. The task assigning system of Claim 6 further comprising: a fourth means for identifying said addresses for said registers that are not inserted in said queue. 9. The task assigning system of Claim 7 further comprising: a third means for storing a task in said register that has the lowest address identified by said fourth means. 10. The task assigning system of Claim 6 wherein said insertion means orders said register addresses stored in said "next" field and said "previous" field in said registers in said queue whenever a said register is inserted or removed from said queue. 11. The task assigning system of Claim 10 further comprising: a third means for storing a task in said register that is not inserted in said queue and has the lowest said register address. 12. The task assigning system of Claim 10 further comprising: a fourth means for identifying said addresses for said registers that are not inserted in said queue. 13. The task assigning system of Claim 12 further comprising: a third means for storing a task in said register that has the lowest address identified by said fourth means. 14. The task assigning system of Claim 11 wherein: said first means assigns to said first actuator, upon completion of a task by said first actuator, said stored task associated with said register address stored in said "next" field of said register storing said task just completed by said first actuator; and said second means assigns to said second actuator, upon completion of a task by said second actuator, said stored task associated with said register address stored in said "previous" field of said register that is associated with said task just completed by said second actuator. 15. The task assignment system of Claim 6 wherein each of said registers further includes a "taken" field where said "taken" field indicates whether or not a said stored task associated with a said register is being processed by said dual actuator disk drive system. 16. The task assigning system of Claim 6 wherein: said first means will assign, upon completion of a task by said first actuator, to said first actuator said stored task associated with said queue register whose "taken" field indicates that said stored task is not being processed and which has the next highest said cylinder address above said cylinder address for said queue register associated with said completed task; and said second means will assign, upon completion of a task by said second actuator, to said second actuator said stored task associated with said queue register whose "taken" field indicates that said stored task is not being processed and which has the next lowest said cylinder address below said cylinder address for said queue register associated with said completed task. 17. The task assigning system of Claim 16 wherein said insertion means orders said register addresses stored in said "next" field and said "previous" field in said registers in said queue whenever a said register is inserted or removed from said queue. 18. The task assigning system of Claim 16 further comprising: a third means for storing a task in said register that is not inserted in said queue and has the lowest said register address. 19. The task assigning system of Claim 16 further comprising: a fourth means for identifying said addresses for said registers that are not inserted in said queue. 20. The task assigning system of Claim 19 further comprising: a third means for storing a task in said register that has the lowest address identified by said fourth means. 21. The method of assigning tasks in a dual actuator disk drive system wherein each task has a cylinder address, the disk drive system includes a plurality of task registers for storing tasks, a queue comprising a header register, an insertion means for inserting the task registers into the queue when a task is first stored in the task register, where the header register and each task register has a unique address, a "next" field having the address of the task register in the queue having the next highest cylinder address above the cylinder address of the task stored in the register, a "previous" field having the address of the register in the queue having the next lowest the cylinder address below the cylinder address of the task stored within the queue, the task registers also having a "taken" field to indicate whether or not the stored task associated with the register is being processed by the disk drive system and a "cylinder address" field for storing the cylinder address associated with the stored task; and a second means for identifying the address for the task registers that are not inserted in the queue, said method comprising a routine for storing a task into a task register and inserting the task into the queue having the steps of: a) going to the header register; b) branching to step d and following the path of option A if the "next" field is equal to the header register address go; b) going to the present task register whose address is in the "next" field of the register being tested by step b; c) branching to step b if the cylinder address of the task stored in the present task register is less than the cylinder address of the task to be inserted, otherwise go to step d and follow the path of option B; d) storing the task into the selected task register having the lowest address identified in the second means; e) setting the "next" field of the selected task register if option A to the address of the header register or if option B to the address of the present register; f) setting the "previous" field of the selected task register to the address in the "previous" field if option A of the header register or if option B of the present task register; g) if option A setting the "next" field of the present, task register to the address of the selected task register or if option B setting the "next" field of the task register whose address is in the "previous" field of the present task register to the address of the selected task register; and h) if option A setting the "previous" field of the header register to the address of the selected task register or if option B setting the "previous" field of the present task register to the address of the selected task register; and i) end the routine. 22. The method of Claim 21 further comprising the routine for removing the task register for a completed task from the queue, said routine having the steps of: a) setting the "next" field of the task register whose address is in the "previous" field of the completed task register to the address in the "next" field of the completed task register; b) setting the "previous" field of the task register whose address is in the "next" field of the completed task register to the address of the "previous" field of the completed task register; c) setting the "taken" field of the completed task register to zero; d) identifying the address of the completed task register in the second means; and e) end the routine. 23. The method of Claim 21 further comprising the routine for assigning a new task to CHANNEL A for the first actuator of the dual actuators of the disk drive system when the last byte of data has been transferred by the first actuator for the current register storing the task assigned to CHANNEL A, the routine comprising the steps of: a) going to the current register; b) going to the present task register whose address is in the "next" field of the task register being tested or to the present task register whose address is in the "next" field of the header register if the "next" field of the register being tested is the address of the header register; c) branching to step b if the "taken" field of the present register indicates that the present register is taken, otherwise setting the "taken" field of the present register to taken and assigning the task stored in the present task register to CHANNEL A for processing; and d) end the routine. 24. The method of Claim 21 further comprising the routine for assigning a new task to CHANNEL B for the second actuator of the dual actuators of the disk drive system when the last byte of data has been transferred by the second actuator for the current register storing the task assigned to CHANNEL B, the routine comprising the steps of: a) going to the current register; b) going to the present task register whose address is in the "previous" field of the task register being tested or to the present task register whose address is in the "previous" field of the header register if the "previous" field of the register being tested is the address of the header register; c) branching to step b if the "taken" field of the present register indicates that the present register is taken, otherwise setting the "taken" field of the present register to taken and assigning the task stored in the present task register to CHANNEL A for processing; and d) end the routine.

Inventors: CORNABY STEPHEN R, CORNABY, STEPHEN, R.
Applicants: CONNER PERIPHERALS INC, CONNER PERIPHERALS, INC.
Application year: 1994
Main classification: G11B5
IPC codes: G06F3, G11B5, G11B19, G11B21