DECIMATION FILTER

Abstract: The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages (22, 23, 25, 27) and a decimation stage. The decimation filter structure of the invention comprises additional branches (28, 29, 30, 31) for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter.

Description: Decimation filter The present invention relates to a decimation filter comprising a cascade arrangement of the following elements in the given order: M : digital first order integration stages having a clock rate F B and a delay of one clock cycle, M 2 digital second order integration stages having a clock rate F 2 and a delay of two clock cycles, a decimation stage for decreasing the sampling frequency of the output signal from the last integ¬ ration stage by a predetermined decimation ratio K, M digital derivation stages having a clock rate F 8 /K, each comprising a delay element stage for delaying the input signal for one clock cycle and a subtractor element stage for subtracting the input signal from the output signal of the delay element, wherein M=M 1 +2M 2 . A decimation filter is a digital filter where- with the sampling frequency of a signal is decreased (decimated) by a number K (normally an integer) which is called the decimation ratio. A decimation filter is typically used in connection with an oversampling A/D or D/A converter (e.g. sigma-delta converter) to decrease the output sampling frequency of the con¬ verter. Decimation can in principle be performed in one stage comprising a low-pass filter and a unit taking every K:th sample from the output of the low- pass filter, K being the decimation ratio. The fil¬ tering response of the low-pass filter must be such that the information carried by the output signal of the filter fits into the band according to the new sampling frequency. A problem attendant the decimation carried out in one stage will be that a low-pass filter having a very steep and narrow-band frequency response is needed. This problem has traditionally been overcome by performing the filtering and decimation in several stages, so that the product of the decimation ratios K 1 , K 2 ,...K n of the different decimation stages is the requisite decimation ratio K stated above. Thus the requirements on the characteristics of the low-pass filters required in the individual stages are relieved and their number of order is decreased so that the overall number of order in the low-pass filters of the different stages is only a fraction of that of a cor¬ responding single-stage implementation. This is parti¬ cularly the case when the decimation ratio M is high, e.g. > 50. The computationally efficient first stage for multistage decimators is provided by a transfer func¬ tion -K ΛM H( z) = 2 ~p 1 -z 1 - Z - 1 where 2 "p is a scaling constant. It can be used as a first stage with decimation factor K in cases where the overall decimation factor D can be realized in the product D = K , where K and L are integers. The design and structure of such a filter have been described for instance in the article E.B. Hogenauer, "An economical class of digital filters for decimation and interpolation", in IEEE Trans. Acoust. Speech Signal Processing, pp. 155-162, vol. ASSP-29, April 1981. One known decimator structure satisfying the transfer function according to equation 1 is shown in Figure 1. The decimator requires only 2M adders and 2M delay elements and no multiplying oper¬ ations. Furthermore, Figure 1 shows a scaling element 12 and a decimation block 13 forwarding only every K:th sample. It should be noted that if l's or 2's com¬ plement arithmetic (or modulo arithmetic in general) and the worst-case scaling are used, the output values of a filter H(z) implemented as shown in Figure 1 are correct even though internal overflows were to occur in the feedback loops realizing the term 1/(1 - z "1 ) . Furthermore, under the above conditions the effect of temporary miscalculations vanishes from the output in finite time and initial resetting is not necessarily needed. The scaling constant 2 ~p has to satisfy the condition 2- p ≤(l/K) M . The integer M for the prior art filter struc¬ ture has to be selected in such a way that H(z) provides the required attenuation in the frequency bands [F ε /2(2r/K - l/D),F s /2(2r/K+l/D)], r=l, 2, ... , [K/2] which alias into the frequency band [0,F B /2( 1/D)] of the overall decimator. Herein F s is the input sampling fre¬ quency. The prior art structure shown in Figure 1 is attended by the disadvantage that the zeros produced by the transfer function thereof are located at fre¬ quencies F s /K,2*F ε /K,3*F s /K, ... , (K-l)*F ε /K, and the in- teger M can only increase their number, i.e. the number of order of the filter. This results in that the number of structural elements in the prior art filter stage is unnecessarily high for the required attenuation at fre¬ quencies [F ε /2(2r/K-l/D),F ε /2(2r/K+l/D)] . A high number of structural elements increases the number of addi¬ tions and delays required in the implementation. How¬ ever, the major disadvantage is the increase of the gain of the filter when the number of order increases, and thus the number of additional bits required in the structure increases. The required number of additional bits is the smallest integer which is higher than log 2 κ\ The object of the present invention is a fil¬ ter structure in which the number of structural ele- ments can be considerably reduced in comparison with prior art structures having the same attenuations at frequencies [F s (2(2r/K-l/D) , F ε /2(2r/K+l/D)] . In the structure according to the invention, the necessary attenuation can be achieved with lower-order structures than was previously possible, on account of the better location of the attenuation zeros. This is achieved with the decimation filter set forth in the preamble, which in accordance with the invention is characterized in that the decimation fil- ter further comprises 2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to the 1 -stage integrator and the output of the derivation stage of the i:th sec¬ ond stage subsequent to the decimation block in the main branch a signal processing branch (realizes the (i+K * i) clock cycle delay at sampling frequency F B and the coefficient) is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F ε of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F ε /K, and a scaling element having a scaling factor c where i = The present invention also relates to another decimation filter as set forth in the preamble, which is characterized in that the decimation filter com¬ prises 2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to M 1 and the output of the main branch a signal processing branch is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F B of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a pre¬ determined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F s /K, a ( 1 +2(M 2 -i))-stage derivation block, and a scaling element having a scaling factor α x where i = The decimation filter structure according to the invention comprises additional branches for shift¬ ing the location of the attenuation zeros of the deci- mation filter and thereby reducing the order M and the number of structural elements M of the required filter. As an example, let us consider a case with D = 64 when a 120-dB attenuation is desired. With designs according to the invention, for K = 16 the aliased terms are attenuated more than 120 dB by using M. = 2 and M 2 = 2. The scaling factors a l f a 2 of the branches can be quan¬ tized to be integers which may in some cases be sel¬ ected from powers of two. Where the decimation filter of the invention is realized as an integrated circuit, the use of these additional branch coefficients in- creases the silicon area occupation in the configura¬ tion of the integrated circuit only by 10% compared to the prior art configuration having six terms (M=6). Without additional branches, eight terms (M=8) would be required to provide the desired attenuation in the prior art solution. Such a prior art filter would fur¬ ther require a higher internal wordlength (8 bits more, i.e. more than 30% in excess of that of the exemplified pre-filter stage of the sigma-delta modulator which has six terms), and the number of delay elements and adders would be higher. In an integrated circuit design, the estimated saving in silicon area occupation achieved with the invention over the corresponding known solu¬ tion is about 30% for the case where these filters are used as first filter stages in the decimation of a one- bit data stream from a sigma-delta modulator. The structure now disclosed has the further advantage of lower amplitude distortion within the passband, thus facilitating error correction. Furthermore, in several implementations the calculation accuracy of the prior art structure becomes too high, and thus either the speed of the circuit configurations or the clock signals in the system preclude the use of the prior art structure. In the following the invention will be set forth in greater detail by means of illustrating em¬ bodiments with reference to the accompanying drawing, in which Figure 1 is a block diagram illustrating a prior art decimation filter, Figure 2 is a block diagram illustrating a decimation filter according to the invention, Figure 3 is a block diagram illustrating another decimation filter according to the invention, and Figures 4 and 5 show frequency responses of a prior art filter and a filter according to the inven¬ tion. Reference will now be made to Figure 2, illus- trating a decimation filter stage according to the invention. This decimation filter stage decreases the sampling frequency F ε of a signal applied to the input IN, said signal preferably being a one-bit data stream from a sigma-delta modulator, so that the sampling fre- quency of the data stream at the output OUT of the filter is F ε /K. Factor K is called the decimation ratio. At the input of the filter, a scaling element 21 having a scaling factor 2 "p is first provided. Subsequent to the scaling element 21, an integration block E(z) M ι com- prising in series configuration M : integration stages E(z) as shown in Figure 2A is connected in series. In Figure 2A, the integration stage E(z) com¬ prises a series connection of adder 200 and delay means 201. The input signal of the integration stage is applied to one input of the adder 201, and the output signal of the delay means 201, which at the same time provides the output signal of the entire integration stage, is fed back to the second input of the adder 200. The added signal obtained at the output of the adder 200 is applied to the delay means 201. In Figure 2, subsequent to the integration block E(z) ι, a series connection of M2 second order integration blocks E(z) 2 is provided. Each of these blocks comprises in series configuration two integ- ration stages as shown in Figure 2A. After the last integration stage E(z) 2 , denoted by reference 23 M , a decimation block 24 is connected which forwards every K:th sample from the output of the integration stage 23 κ . After the decimation block 24, M 2 second order derivation blocks F(z) 2 , denoted with references 25 1 25 2 ,...25 M respectively, are connected in series. Each second order derivation block F(z) 2 comprises in a series connection a pair of derivation stages F(z) shown in Figure 2B. After the second order derivation stage F(z) 2 , a series connection of adders 26^ 26 2 ,...26 M is provided ahead of the next second order block. These adders add the outputs of the blocks together with the signal from the corresponding branch prior to application to the next block. After the last derivation stage 25 M and adder 26 M , a derivation block F(z) M ι, comprising in series configuration Ml derivation stages as shown in Figure 2B, is connected in series. The derivation stage F(z) of Figure 2B com¬ prises a series connection of delay means 202 and sub- tractor 203. The input signal is applied to adder 203 both directly and via delay means 202 having a delay of one clock cycle, and the differential signal is applied to the output of the stage. The decimation filter further comprises M2 signal processing branches in such a way that between the input of the i:th second order integrator after the Mi-stage integrator and the output of the i:th second order derivation stage F(z) 2 after the decimation block 24 of the main branch a signal processing branch is con- nected which comprises, in series configuration, a first delay element 28 having a delay of i clock cycles at sampling frequency F B of the output signal, a deci¬ mation stage 29, corresponding to decimation stage 24, for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element 30 having a delay of i clock cycles at sampling frequency F s /K, and a scaling element 31 having a scaling factor α A where i = 1,2,3, ... ,M 2 . Thus for example from the input of integration stage 23 M -1, there is an outgoing feedforward signal process- ing branch comprising a delay means 28 2 having a delay z "2 of two clock cycles at clock rate Fs, a decimation stage 29, a delay means 30 2 having a delay z "2 of two clock cycles at clock rate F s /K, and a scaling element 31 2 having a scaling factor A 2 . The output of each scaling element 31 1 ,31 2 , ...31 M is coupled to the second input of the corresponding adder 26 x ,26 2 , ...26 M . The overall transfer function of the filter of Figure 2 is Another alternative filter structure for real¬ izing the above transfer function is shown in Figure 3. In Figure 3, blocks and elements that are the same as in Figure 2 have been denoted with the same references and symbols. As in Figure 2, also in Figure 3 the arrangement comprises - starting from the input IN and in the following sequence - a series connection of a scaling element 21, an Ml-stage integration block 22, M2 second order integration blocks 23 1 ...23 M and a decimation block 24. After the decimation stage 24, a derivation block 25' is connected comprising in a series connection M2 derivation blocks F(z) as shown in Figure 2B, a derivation block 27 comprising in a series connection Ml derivation stages F(z), and an adder 33. The decimation filter of Figure 3 further com¬ prises M2 signal processing branches in such a way that between the input of the i:th second stage integrator 23 after M. and the adder 33 in the output of the main branch a signal processing branch is connected which comprises, in a series connection, a first delay ele¬ ment 28 having a delay of i clock cycles at sampling frequency F ε of the output signal, a decimation stage 29, corresponding to decimation stage 24, for decreas- ing the sampling frequency of the output signal of the first delay element by a predetermined decimation ratio K, a second delay element 30 having a delay of i clock cycles at sampling frequency F ε /K, an ( M. + 2(M 2 -i))- stage derivation block 32, and a scaling element 31 having a scaling factor a where i = 1,2,3, ...,M 2 . Thus for example from the input of the second order integ¬ rator 23 M -1, there is an outgoing feedforward signal processing branch comprising a delay means 28 2 having a delay of two clock cycles at clock rate Fs, a deci- mation stage 29, a delay means 30 2 having a delay of two clock cycles at clock rate F ε /K, a derivation block 32 2 comprising (M-4) derivation stages F(z), and a scaling element 31 2 having a scaling factor A 2 . The filter structure of Figure 2 can be used when the scaling factors . can be quantized to be integers. The filter structure of Figure 3 can also be used with decimal factors ( fractions) o t . Let us next consider an exemplary case with D = 64 when a 120-dB attenuation is desired. For a decimation ratio K = 16, the aliased terms at the desired frequency bands are attenuated more than 120 dB by using M. = 2 and M 2 = 2. In this case, the scaling factors a x and a 2 can be quantized to be integers, so as to provide altogether six integration and derivation blocks (the branches are of the feedforward type) . The frequency response obtained with the filter of the invention is shown by a solid line A in Figure 4. The corresponding prior art filter requires eight terms, and its response is shown by a dashed line B in Figure 4. When the decimation ratio K is increased to K = 32, the prior art filter structure requires thirteen terms, whereas the proposed branched filter structure only requires eight terms. In Figure 5, the solid line A and dashed line B represent the filter responses of the filter of the invention and the prior art filter, respectively. The circuit is generally executed on silicon using parallel arithmetic in the integrator part and serial arithmetic in the derivation blocks. The parallel part takes up about 3/4 of the area, owing mainly to the arithmetic (parallel adders). The proportion of the delay in the parallel part is about 15%. The integration in the decimation circuit is per¬ formed between the derivation blocks by control and a parallel/series register which is very uncomplicated. The area of the serial derivation part is mostly taken up by the delays, since the arithmetic (the adder is only one-bit adder, yet the delay of one sample is equal in parallel and series configurations) is one-bit arithmetic. In the structure now disclosed, the delays (delay elements) ahead of the decimation as well as the actual decimation can be realized by means of a paral¬ lel/series register and control. Only the additional delays after decimation have to be realized; mathe- matically all delays are present in accordance with the block diagrams. This affords considerable saving in silicon area occupation. The scaling factors can be realized with an accuracy of a few bits. The figures and the description relating to them are only intended to illustrate the present inven¬ tion. The decimation filter of the invention can vary in its details within the scope and spirit of the appended claims.

Claims: Claims : 1. A decimation filter comprising a cascade arrangement of the following elements in the given order: M. digital first order integration stages having a clock rate F s and a delay of one clock cycle, M 2 digital second order integration stages having a clock rate F 2 and a delay of two clock cycles, a decimation stage for decreasing the sampling frequency of the output signal from the last integ¬ ration stage by a predetermined decimation ratio K, M digital derivation stages having a clock rate F B /K, each comprising a delay element stage for delaying the input signal for one clock cycle and a subtractor element stage for subtracting the input signal from the output signal of the delay element, wherein M=M 1 +2M 2 , c h a r a c t e r i z e d in that the deci- mation filter further comprises M 2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to the M 1 -stage integrator and the output of the derivation stage of the i:th second stage subsequent to the decimation block in the main branch a signal processing branch is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F ε of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F s /K, and a scaling element having a scaling factor c^ where i = 1,2,3, ...,M 2 . 2. A decimation filter as claimed in claim 1, c h a r a c t e r i z e d in that at the input of the decimation filter, a scaling element is provided for scaling the input signal by a factor 2 "p . 3. A decimation filter as claimed in claim 1 or 2, c h a r a c t e r i z e d in that M 1 =M 2 =2. 4. A decimation filter as claimed in claim 3, c h a r a c t e r i z e d in that the scaling factors a M are integers. 5. A decimation filter comprising a cascade arrangement of the following elements in the given order: x digital first order integration stages having a clock rate F ε and a delay of one clock cycle, M 2 digital second order integration stages having a clock rate F 2 and a delay of two clock cycles, a decimation stage for decreasing the sampling frequency of the output signal from the last integ¬ ration stage by a predetermined decimation ratio K, M digital derivation stages having a clock rate F s /K, each comprising a delay element stage for delaying the input signal for one clock cycle and a subtractor element stage for subtracting the input signal from the output signal of the delay element, wherein M=M 1 +2M 2 , c h a r a c t e r i z e d in that the deci- mation filter further comprises M 2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to M x and the output of the main branch a signal processing branch is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F ε of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F ε /K, a (M 1 +2(M 2 -i))-stage derivation block, and a scaling element having a scal¬ ing factor c^ where i = 1,2,3, ...,M 2 . 6. A decimation filter as claimed in claim 5, c h a r a c t e r i z e d in that at the input of the decimation filter, a scaling element is provided for scaling the input signal by a factor 2" p . 7. A decimation filter as claimed in claim 5 or 6, c h a r a c t e r i z e d in that M : =M 2 =2. 8. A decimation filter as claimed in claim 7, c h a r a c t e r i z e d in that the scaling factors are realized with an accuracy of only a few bits.

Inventors: EEROLA VILLE, HUSU TIMO, INGALSUO SEPPO, PAJARRE EERO, RITONIEMI TAPANI, SARAMAEKI TAPIO, EEROLA, VILLE, HUSU, TIMO, INGALSUO, SEPPO, PAJARRE, EERO, RITONIEMI, TAPANI, SARAMAEKI, TAPIO
Applicants: EEROLA VILLE, HUSU TIMO, INGALSUO SEPPO, PAJARRE EERO, RITONIEMI TAPANI, SARAMAEKI TAPIO, EEROLA, VILLE, HUSU, TIMO, INGALSUO, SEPPO, PAJARRE, EERO, RITONIEMI, TAPANI, SARAMAEKI, TAPIO
Application year: 1994
Main classification: H03H17
IPC codes: H03H17