Photoelectric conversion device

Abstract: The present invention is intended to provide a photoelectric conversion device provided with a plurality of groups comprising a plurality of adjacent photoelectric conversion elements, wherein the plurality of groups are respectively provided with a detection circuit for detecting a peak signal of each group.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion device to be used in image sensors employed e.g. in copying machines, facsimile machines, video cameras and video recorders, optical sensors represented by AE Auto Exposure sensors and AF (Auto Focus) sensors of cameras and sensors for detecting positions of objects, more specifically, a photoelectric conversion device suited to detect a light such as a micro spot light. Related Background Art Figs. 1A to 1C respectively show an example of a known photoelectric conversion device (sensor) and Fig. 1A shows a 2-dimensional sensor which has 16 sensor cells, as photoelectric conversion elements, in total, including four sensor cells per line and four sensor cells per row. In this sensor, each of the lines is selected in sequence from the above in the drawing by a vertical shift register VSR and four discrete signals are outputted by the horizontal shift register HSR in time series sequence to the output terminal OUT. Signals of these sensor cells are output in sequence in combinations of line scanning and row scanning. In an actual sensor, the number of sensor cells amounts to 100 to 100,000 and therefore the effect of reducing the read time and the scan time from one cell is obviously limited. On the other hand, those signals from the sensor cells are visible image signals in most cases. In the case of such visible image, bright signals may be concentrated only at an extremely small area in one frame as the flame of a match in darkness and the remaining area may be occupied by dark signals. Even in such case, the signals of all cells of the known sensor have been outputted in time series sequence and accumulated in an external random access memory, then required image signal processing has been carried out. On the other hand, in case of the AE sensor (photo sensor for automatic exposure control), the size of the cell is expanded to reduce the number of separate parts and a configuration for ensuring short scanning time is used. Fig. 1B shows a sensor as described above and each cell (SS 11 ... SS 22 ) has a larger light receiving area than the cell shown in Fig. 1A and the number of divisions is 4. The sensor shown in Fig. 1B, however, cannot discriminate uniform irradiation of weak light onto the whole light receiving surface of the cell (ma 1 in Fig. 1C) from irradiation of strong light only at a part of the light receiving surface of the cell (ma 2 in Fig. 1C) and therefore it is difficult to apply this sensor to detection of a spot of light on a small area. As described above, the sensor has required a long processing time or has malfunctioned in detection of a light (ma 2) shown in Fig. 1C. For example, Fig. 2 is a plan view of a pixel of a known bipolar sensor. In Fig. 2, 51 is an emitter (serving as the main electrode area where signals based on accumulated carriers are outputted), 52 is an output line formed with Al or the like, 53 is a contact hole for connecting the emitter 51 and the output line 52, 54 is a base (serving as the control electrode area) where an optical charge is accumulated, 55 is a drive line formed with poly-Si or the like for sensor operation of the pixels, 56 is a capacitor C OX formed between the base 54 and the drive line 55, and 57 is a gate of a MOS transistor which is formed with the bases of an adjacent pixels as a source and a drain, and comprises part of the drive line 55. 58 is a thick oxidized film for separation between pixels. Fig. 3 is a sectional view as Fig. 2 is sectioned along line XX' and Fig. 4 is a sectional view as Fig. 2 is sectioned along line YY'. In Figs. 3 and 4, 59 is a thin oxidized film, 60 is a high density n+ layer provided to separate pixel signals in the YY' direction, 61 is an n - epitaxial layer, 62 is a collector (serving as the main electrode area), and 63 is an inter-layer insulation film for separating wires 52 and 55. In addition, Fig. 5 is an equivalent circuit diagram of an area sensor which is formed with the above-described pixels arranged in 2-dimensional format. In Fig. 5, S is a pixel of the sensor (equivalently comprising a bipolar transistor 31, a capacitor C ox 4 and a PMOS transistor 5), 1 is a vertical output line to be connected to the emitter of the pixel S, 6 is a MOS transistor for resetting the vertical output line 1, 7 is a terminal for applying pulses to the gate of the MOS transistor 6, 8 is a horizontal drive line, 9 is a buffer MOS transistor for receiving the output of the vertical shift register and passing a sensor drive pulse, 10 is a terminal for applying the sensor drive pulse, 11 is a wire connected to the drains of PMOS transistors at the right and left ends of the pixel array, 12 is an emitter-follower circuit part for setting a source potential of the PMOS transistor 5 to refresh the pixel S, 13 is a PMOS transistor for setting the base potential of the emitter-follower 12, 14 is a power supply terminal connected to the drain terminal of the PMOS transistor 13, 15 is a terminal for applying pulses to the gate of the PMOS transistor 13, 18 is an accumulation capacitor for accumulating output signal from the pixel S, 19 is a MOS transistor for transferring output signals to the accumulation capacitor 18, 20 is a terminal for applying pulses to the gate of the MOS transistor 19 for transfer, 21 is a horizontal output line, 22 is a MOS transistor for receiving an output of a horizontal shift register and transferring output signals to the horizontal output line 21, 50 is a MOS transistor for resetting the horizontal output line 21, 23 is a terminal for applying pulses to the gate of the MOS transistor 50, and 24 is an amplifier. A 2-dimensional solid image pickup apparatus shown in Fig. 5 is such that all pixels are reset at once, and can be used in a still video camera and the like. The operation of this image pickup apparatus is briefly described below. First a low-level pulse is applied to the terminal 15 to set the PMOS transistor to ON and the output of the emitter-follower circuit part to a positive potential. The output terminal of this emitter-follower circuit part 12 is connected to the source of the PMOS transistor for the pixel S and, if the source potential is sufficiently high enough to turn on the PMOS transistor 5 as compared with the gate potential, holes are injected into the base of the bipolar transistor 31 for pixels (referred to as the "first reset" up to this point). Then the transistor 6 is set to ON and the vertical output line 1 is set to the GND level by applying a high-level pulse to the terminal 7. Next a forward bias is formed between the base and the emitter of the bipolar transistor 31 by driving the vertical shift register in the above state and applying a reset pulse for the pixels to the terminal 10 to reset in sequence the pixels of each line and set the base of the bipolar transistor 31 for all pixels to a fixed potential and then to the reverse bias (referred to as the "second reset" up to this point). After accumulation of photo carriers, a low-level pulse is applied to the terminal 7 to set the MOS transistor 6 to OFF, a read pulse is applied from the terminal 10 to each line selected according to the output of the vertical shift register, a forward bias is formed between the base and the emitter of the bipolar transistor 31, and the signal output of pixels for each line is accumulated in the accumulation capacitor 18 through the MOS transistor 19. The signal output accumulated in the accumulation capacitor 18 is transferred to the horizontal output line 21 through the transfer MOS transistor 22 selected by the horizontal shift register and output through the amplifier 24. In this case, the accumulation time (Ts) of the sensor is a time from the end of the second reset to application of the read pulse to the terminal 10. In the case of a 1-dimensional linear sensor, the maximum value of the signals from each sensor cell (peak signal) is detected and the accumulation time is controlled according to this maximum value. In the case of a 2-dimensional area sensor, it is difficult to detect the peak signal because of the properties of the circuit and therefore it is also difficult to obtain an appropriate signal level for the whole image. For detecting the position of the pixel which presents the maximum output on the light receiving surface, there has been a problem that pixel information (or all pixel outputs) should be used and therefore the signal processing time would be long and a memory would be required. EP-A-0226338 discloses a line sensor in which each photoelectric conversion cell has a double-emitter photoelectric bipolar transistor. The first emitter of each cell is used to provide a signal for read out from the sensor. All of the second emitters are connected together so as to provide a signal which represents the peak signal of all of the cells. This peak signal is provided to an amplification regulating circuit which controls the gain of an amplifier in the output circuit for the sensor. It is stated that the concept may also be applied to an area sensor having cells disposed two-dimensionally. EP-A-0522732 relates to a system in which the minimum peak value and the maximum peak value are both continuously obtained from the cells of a line sensor during the photo-accumulation period, and the contrast range (the difference between the maximum peak and the minimum peak) is continuously monitored. It is proposed that, where two sensor columns are formed on one chip, there is the possibility that the two columns may have different numbers of cells and may also have different stray capacitances, and therefore separate minimum and maximum peak values are taken from each sensor column and the contrast range for each sensor column is monitored separately, with the contrast range monitoring circuit including means for compensating for the effects of the different numbers of cells and the different stray capacitances between the two sensor columns. EP-A-0444938 discloses a photoelectric sensor in which several (for example eight) separate line sensors are all formed on one chip, with some of the line sensors extending at right angles to the others. A maximum peak value and a minimum peak value is provided from each line sensor. EP-A-0577391 (published on 5 January 1994, before the filing date of the present application but after the claimed priority dates) discloses a solid state image pickup apparatus having photoelectric conversion pixels arranged in a two-dimensional array. Arrangements are disclosed for outputting the peak signal of each row and the peak signal of each column, whereby both the row and the column of the most strongly irradiated pixel can be known. Summary of the Invention According to the present invention there is provided a photoelectric conversion device as set out in claim 1 and image processing apparatus as set out in claim 9. Optional features are set out in the remaining claims. Embodiments of the present invention may provide a photoelectric conversion device capable of solving the above-described technical problems, detecting various types of lights and improving the processing speed, by providing the photoelectric conversion device with a plurality of groups each of which comprises a plurality of adjacent photoelectric conversion elements and means for outputting a peak signal of each of the above plurality of groups. In other words, an embodiment of the present invention enables real-time signal processing by dividing a sensor array comprising a plurality of cells into a plurality of groups (blocks) and detecting the peak signal of each group. The photoelectric conversion elements may be transistors each having a control region, on which charge carriers are accumulated, and one or more main regions from which the photoelectric conversion output is provided in response to applying a potential to the control region for forward biassing the control region with respect to the main region. The potential may be applied on drive lines which are capacitively coupled to the control regions. Other embodiments and optional features of the present invention will be known from the following description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A - 1C are diagrams for illustrating known photoelectric conversion devices; Fig. 2 is a plan view of a known pixel using a bipolar transistor; Fig. 3 is a sectional view along line XX' in Fig. 2; Fig. 4 is a sectional view along line YY' in Fig. 2; Fig. 5 is an equivalent circuit diagram of an area sensor comprising a 2-dimensional array of pixels shown in Fig. 2; Fig. 6 is a schematic circuit diagram of a photoelectric conversion device embodying a mode of the present invention; Fig. 7 is a schematic circuit diagram of a photoelectric conversion device according to a first embodiment of the present invention; Fig. 8 is a timing chart for illustrating the operation of the photoelectric conversion device according to the first embodiment; Fig. 9 is a schematic circuit diagram of the photoelectric conversion device according to the second embodiment of the present invention; Fig. 10 is a timing chart for illustrating the operation of the photoelectric conversion device according to the second embodiment; Fig. 11 is a schematic circuit diagram of the photoelectric conversion device according to the third embodiment of the present invention; Fig. 12 is a schematic circuit diagram of the photoelectric conversion device according to the fourth embodiment of the present invention; Fig. 13 is a schematic circuit diagram of the photoelectric conversion device according to the fifth embodiment of the present invention; and Fig. 14 is a schematic circuit diagram of the photoelectric conversion device according to the sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 6 is a schematic circuit diagram showing an embodiment according to the present invention with sensor cells Sij (i=1, 2, 3, 4; j=1, 2, 3, 4). The sensor cells are divided into four blocks each having four adjacent cells and in each block the cells are connected to a common signal output line, which is in turn connected to one or the other of two horizontal shift registers (HSR1 and HSR2). A block is selected by the vertical shift register VSR and the horizontal shift register, and a peak signal is output to the terminal out1 or out2. The horizontal shift registers can be, of course, assembled into a single unit with one output terminal, or the peak signals from four blocks can be output in parallel from four output terminals. Sensor cells to be used for the present embodiment are required such that the signal of a cell which receives the largest amount of light is generated on the output line when the output line is commonly connected to several cells, and a photo transistor which stores photo carriers in the control electrode area such as the base or the gate is preferably used. The sensor cells are provided in an area sensor mode in which the cells are arranged in a 2-dimensional array. The size of the light receiving surface of each cell and the number of cells in each block are appropriately selected and designed in accordance with an application of the sensor. In addition, sensor cells are housed in a single chip as a semiconductor integrated circuit. Signals output from this sensor chip are processed as image signals in various ways by external circuits. The first embodiment of the present invention is described, referring to Fig. 7. Bij (i, j = 1, 4) is a bipolar transistor of a photo sensor cell, Pij (i, j = 1, 4) is a P type MOS switch provided between the base areas of the above-described bipolar transistor, Mij (i, j = 1, 4) is a MOS switch; M 1 j (j 1 - 4) is a MOS switch for resetting the sensor output line, M 2 j (j = 1 - 4) is a switch for transferring signals from the output line to the capacitor, M 3 j (j = 1 - 4) is a switch for resetting the potential of the signal readout capacitor Cj (j = 1 - 4), M 4 j (j = 1 - 4) is a switch for selectively supplying output signals to the output line Y1 according to clock signals  1 ,  2 ,  3 and  4 from the shift register, and M 5 is a switch for resetting the output line 1. Y2 is a shift register and Y3 is an output amplifier. A method for operating this sensor is described below, referring to the timing chart shown in Fig. 8. The vertical output line VLi (i = 1 - 4) is reset to V VC voltage and the readout capacitor Cj (j = 1 - 4) is reset to V CR voltage by applying a high level pulse  VC to the N type MOS switch M 1 j (j = 1 - 4) and a high level pulse  CR to the N type MOS switch M 3 j (j = 1 - 4). Next the pulse  BR of the P type MOS gate is set to a low level to set the P type MOS switch Pij (i,j=1-4) to ON and the base potential of the bipolar transistor of Bij (i,j = 1 - 4) is set to V BR . In this case, a voltage of V BR should be set to be approximately at least 1V higher than V VC . When the pulse  VC is set again to a high level after the pulse  BR to the P type MOS gate has been set to a high level and the P type MOS switch has been set to OFF, and the vertical line level is set to V VC , the bipolar transistor is set to the forward bias and the base potential is converged to the constant potential determined by the emitter potential V VC . As shown in Fig. 7, the emitters of B 11 , B 12 , B 21 and B 22 are commonly connected to the vertical line VL 1 and therefore the bases of the above four bipolar transistors are reset by the potential of the vertical line VL 1 . A similar procedure is executed with respect to bipolar transistors of B 13 , B 14 , B 23 and B 24 blocks, bipolar transistors of B 31 , B 32 , B 41 and B 42 blocks, and bipolar transistors of B 33 , B 34 , B 43 and B 44 . When the pulse  vc is set to a low level, the vertical lines VL 1 - VL 4 come to a floating state and the accumulation period (Y4 in Fig. 8) of an optical signal of each cell starts. The pulse  T is set to a high level to transfer signals to the signal readout capacitor Cj (j = 1 - 4). In this case, the potential V CR for resetting the readout capacitor should be set to be lower than the vertical line reset potential V VC . If the voltage and related factors are set in advance as described above, the potential of the vertical line becomes lower than that in the preceding period when the N type MOS switch M 2 j (j = 1 - 4) is set to ON by the  T pulse, and the bipolar transistor Bij (ij = 1 - 4) is set to the forward bias. In this case, the base-emitter bias is largest in each block for the bipolar transistor of the cell which has the largest optical signal level among the cells of the block. and the emitter potential has a value corresponding to the peak optical signal in that block. When the  T pulse is set to a low level, a peak signal from B 11 , B 12 , B 21 and B 22 is read out to the capacitor C 1 , a peak signal from B 31 , B 32 , B 41 , and B 42 is read out to the capacitor C 2 , a peak signal from B 13 , B 14 , B 23 and B 24 is read out to the capacitor C 3 , and a peak signal from B 33 , B 34 , B 43 and B 44 is read out to the capacitor C 4 . According to scanning pulses  1 ,  2 ,  3 and  4 from the shift register Y2, signals accumulated in the capacitors are output through the amplifier Y3 and the output line Y1. Since 2-dimensional information is compressed to a peak signal of a block area and is serially read out, all sensors are usable as means for determining the presence of an image at a high speed in a wide area, for example, to check whether light from an object has been detected on the sensors. Specifically, when a user looks through a camera, a microscope or the like, light from an LED (which is flickering with externally applied, pulses) shines at and reflects from an eye of the user. If this reflected light is detected by the sensor according to the present embodiment, the reflected LED light is quickly detected with high accuracy and the presence of the user can be determined. Accordingly, it is clearly known that the device can now be started. As another application, the sensor according to the present embodiment is useful in detecting the opening and closing of the eyes of an automobile driver. Light from an external LED is shone at the eyes of a driver according to the above method and the reflected light is received by the sensor of the invention. Though a high intensity signal can be detected if the light is reflected from an eye with a normal cornea, the intensity of the reflected light lowers when a driver is sleepy and the time of closed eyelids increases. When the sensor output is lower than the average intensity of the reflected light, a sleepiness preventing apparatus including a buzzer and a seat shaker can be operated to give a warning to the driver. The peak signal information of the blocks is useful to detect product labels on factory lines. In addition, it is be also possible with the following structure to distinguish the peak signal of each block from the ambient light. A capacitor is connected to each peak output portion in series and signal accumulation is performed under the ambient light to clamp the accumulated signal at its level. Subsequently, accumulation is performed under signal light to detect change of a peak output. A comparator determines whether the detected change exceeds a predetermined level. A second embodiment of the invention is described, referring to Fig. 9 showing an equivalent circuit diagram and Fig. 10 showing the timing chart. The same components as those in the embodiment 1 are given the same reference symbols and numerals and the descriptions of these components are omitted. The second embodiment differs from the first embodiment in that each sensor cell is provided with a base potential control capacitor Cij (ij = 1 - 4) for carrying out a reversely biased accumulating operation. Such construction as described above eliminates a switch for resetting a capacitor for readout operation. The operation is described below. Pulses  VC and  T are set to a high level and the vertical lines VL1 - VL4 and the capacitor Ci (i = 1 - 4) are set to V VC . The  BR pulse is changed over from an intermediate level to a low level to set the P type MOS to ON and the base potential is reset to the V BR . After resetting, the pulse is reset to the intermediate level. The V BR level can be selected so that the bipolar transistor is set at OFF in this state. Then, after the  VC pulse is set to the high level to set the vertical lines VL1 - VL4 to the V VC level, the  BR pulse is changed over from the intermediate level to the high level. Thus the base potential of each bipolar transistor is increased by the amount given below through the capacitor Cij (ij = 1 - 4). C ij C B + C ij ( high level BR -  middle level BR ) The reset voltages V VC and V BR of the bipolar transistor can be set at a forward bias value at which current flows in this case. As in the first embodiment, the emitters of bipolar transistors B 11 , B 12 , B 21 and B 22 of one block are connected to a common line VL1 and therefore the emitter current flows in this line and the base potential is reset to correspond to the emitter potential. This is the same with the blocks of other bipolar transistors. After the emitter current has flowed, the  BR pulse is reset to the intermediate level and simultaneously the  VC pulse of the reset MOS Mij is set to a low level to start accumulation of signals. Sensor cells are separated by a P type MOS Pij (ij = 1 - 4). If the  BR pulse and the  T pulse are set to a high level after completion of the accumulation, the peak signals of blocks are read out to capacitors C 1 - C 4 . Subsequent readout is the same as in the first embodiment. The third embodiment is described below, referring to Fig. 11. The same components as those in the embodiment 1 are given the same reference symbols and numerals and the descriptions of these components are omitted. In this embodiment, the wiring has been improved to ensure a symmetry with the vertical lines VL1 - VL4 of the first embodiment. The vertical line VL1 is extended to the blocks of bipolar transistors B31, B32, B41 and B42 to be symmetrical to the vertical line VL2 and the vertical line VL3 is extended to the blocks of bipolar transistors B33, B34, B43 and B44 to be symmetrical to the vertical line VL4. With this arrangement, the parasitic capacitances of the vertical lines are made similar, so that the readout gains of all blocks are made similar and therefore deviations among the blocks are reduced. The fourth embodiment is described, referring to Fig. 12. The fourth embodiment differs from the first to third embodiments in that the outputs of all peak output detection blocks BL1 - BL4 are not read out in one direction but are read in parallel in upper and lower directions and therefore the readout speed is improved. 72 and 73 are respectively a shift register, 74, 75, 80 and 80' are readout circuits for reading out the signals of blocks BL1, BL2, BL3 and BL4, 76, 77, 78 and 79 are vertical output lines of the blocks, and 70 and 71 are horizontal output lines. The fifth embodiment is described, referring to Fig. 13. In this embodiment, the number of blocks is increased by using two types of vertical output lines, for example, a first Al wire and a second Al wire. Output lines 81 for BL11, output lines 83 for BL12, output lines 85 for BL21 and output lines 87 for BL22 are used respectively and, for example, the Al1 wire is used for these output lines, while output lines 82 for BL31, output lines 84 for BL32, output lines 86 for BL41 and output lines 88 for BL42 are used respectively and the Al2 wire is used for these output lines. The signals from these output lines are read out in parallel into the readout circuits 90 - 97, scanned in the shift register 98 and output to the output line 99. The number of divided blocks can be increased by combining the embodiments as described above. The sixth embodiment is described, referring to Fig. 14. The sixth embodiment is intended to implement reading out of ordinary pixel data in addition to the peak signal of a desired block area of the sensor. 100 denotes a vertical shift register for driving the drive line for reading the bits. This embodiment employs a configuration in which the bipolar sensor B' ij (i,j = 1 - 4) is provided with two emitters, one of which is provided exclusively for reading the pixel signals and the other of which is provided for detecting the peak signals, the peak signal output being connected to the gate of a MOS amplifier. The MOS amplifier comprises MOS switches M 7 i (i = 1 - 4) and a switch M 75 and the peak outputs of the blocks are entered into the gates of MOS switches M 7 i (i = 1 - 4). Reset switches M 8 j (j = 1 - 4) and a reset pulse  RS-EM are provided to reset the vertical lines for detecting the peak signals. With this configuration, the added-up peak output of all rows is outputted from the amplifier 106. Addition in this case is not ordinary linear addition and is addition of square roots of the outputs. However, there is no problem in an application where the linearity is not demanded in the peak outputs. Though the peak values of all rows are added in this embodiment, it is easy to implement separation of the peak value output into blocks for output. The data accumulated in each pixel is output by the device operation described with respect to the first embodiment or Fig. 5. In this embodiment, a plurality of spots of light are shone onto the sensor part and the peak signals are used to count up the number of spots of light. Pixel outputs can be used to check the relative positions of the spots of light and the image processing can be executed at a high speed. The embodiment as described above can provide a photoelectric conversion device capable of detecting even extremely small spots of light and processing signals at a high speed. In the first to sixth embodiments the photoelectric conversion elements are bipolar transistors and, if the present invention specifies a non-destructive sensor, such transistors with other constructions can be used as the sensor. In each of the embodiments described above there is also a control means (not shown in the drawings) which generates the control signals and other voltages with timings as required for operation of the illustrated circuits.

Claims: A photoelectric conversion device comprising a two-dimensional array of photoelectric conversion elements (B), characterised in that: the array comprises a plurality of groups arranged two-dimensionally in the array, each group comprising a plurality of adjacent photoelectric conversion elements, and each group is connected to peak signal output means (BR,72,73,74,75,80,80' ,90-98) for outputting from the group a peak signal representing the maximum or the minimum of the photoelectric conversion outputs from the elements in the group. A device according to claim 1 in which the peak signal output means comprises a plurality of capacitors (C1 to C4) for storing the said peak signals. A device according to claim 1 or claim 2 in which the peak signal output means comprises a common output line (Y1,99) on which the peak signal of each group is output in turn. A device according to claim 1 or claim 2 in which the peak signal output means comprises a plurality of output lines (70,71) on which the peak signals of respective groups are output in parallel. A device according to any one of the preceding claims comprising pixel signal output means connected to the photoelectric conversion elements for outputting pixel signals representing the respective photoelectric conversion outputs of the respective elements. A device according to claim 5 in which the pixel signal output means comprises a pixel signal output line, on which the pixel signals are output in turn, which is separate from any output line or lines on which the peak signals are output. A device according to any one of the preceding claims in which the photoelectric conversion elements comprise bipolar transistors the bases of which accumulate photogenerated charge carriers and the emitters of which provide the photoelectric conversion outputs. A device according to claim 5 or claim 6 in which the photoelectric conversion elements comprise bipolar transistors having first and second emitters, the bases of the transistors accumulating photogenerated charge carriers and both the first and second emitters providing the photoelectric conversion outputs. An image processing apparatus comprising: a photoelectric conversion device according to any one of claims 1 to 8; and an image processing means arranged outside said photoelectric conversion device, for performing an image processing of a signal from said photoelectric conversion device.

Inventors: MIYAWAKI MAMORU, SHINOHARA MAHITO, UENO ISAMU, MIYAWAKI, MAMORU, SHINOHARA, MAHITO, UENO, ISAMU, MIYAWAKI, MAMORU, C/O CANON K.K., SHINOHARA, MAHITO, C/O CANON K.K., UENO, ISAMU, C/O CANON K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: H04N3
IPC codes: H04N3