Non-volatile memory device

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate (FG/8) is controlled, or, a channel of a transistor (4) is buried by an ion implantation, the threshold value at no charges accumulated is set between the respective thresholds corresponding to data "0" and data "1" states, to reduce the disturbances of a drain and a gate when reading.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable nonvolatile memory, for example, a flash EEPROM or other semiconductor nonvolatile memory device, and a method of manufacturing the same. 2. Description of the Related Art Figure 1 is a circuit diagram showing an example of a memory cell array of a NAND type flash EEPROM and showing the bias conditions at the time of a reading operation. In Fig. 1, BL N-1 , BL N , and BL N+1 denote bit lines, V SS denotes a source line, WL 1 to WL 8 denote word lines, SG 1 to SG 2 denote selection gate lines, ST1 N-1 , ST1 N , ST1 N+1 , ST2 N-1 , ST2 N , and ST2 N+1 denote selection gates, MT1 N-1 to MT8 N-1 , MT1 N to MT8 N , and MT1 N+1 to MT8 N+1 denote memory cell transistors, CG S denotes control gates of the memory cells, and FG S denote floating gates of the memory cells. In the memory cell array, one end of each of the bit lines BL N-1 , BL N , and BL N+1 is connected to a common source line V SS . Between the source line V ss and each of the other ends of the bit lines BL N-1 , BL N , and BL N+1 are connected the selection gates ST1 N-1 , ST1 N , and ST1 N+1 and ST2 N-1 , ST2 N , and ST2 N+1 , respectively. Further, between the selection gates ST1 N-1 and ST2 N-1 , between the selection gates ST1 N and ST2 N , and between the selection gates ST1 N+1 and ST2 N+1 are connected eight series-connected memory cell transistors MT1 N-1 to MT8 N-1 , MT1 N to MT8 N , and MT1 N+1 to MT8 N+1 , respectively. The gates of the selection gates ST1 N-1 , ST1 N , and ST1 N+1 are connected to a common selection gate line SG 1 , while the gates of the selection gates ST2 N-1 , ST2 N , and ST2 N+1 are connected to a common selection gate line SG 2 . The control gates CG of the memory cell transistors MT1 N-1 , MT1 N , and MT1 N+1 are connected to a common word line WL 1 . Similarly, the control gates CG of the memory cell transistors MT2 N-1 , MT2 N , and MT2 N+1 are connected to a common word line WL 2 , the control gates CG of the memory cell transistors MT3 N-1 , MT3N, and MT3 N+1 are connected to a common word line WL 3 , the control gates CG of the memory cell transistors MT4 N-1 , MT4 N , and MT4 N+1 are connected to a common word line WL 4 , the control gates CG of the memory cell transistors MT5 N-1 , MT5 N , and MT5 N+1 are connected to a common word line WL 5 , the control gates CG of the memory cell transistors MT6 N-1 , MT6 N , and MT6 N+1 are connected to a common word line WL 6 , the control gates CG of the memory cell transistors MT7 N-1 , MT7 N , and MT7 N+1 are connected to a common word line WL 7 , and the control gates CG of the memory cell transistors MT8 N-1 , MT8 N , and MT8 N+1 are connected to a common word line WL 8 . In such a configuration, when reading out data, for example, as shown in Fig. 1, when an N-th bit line BL N is selected and the word line WL 4 is selected, the selection gates SG 1 and SG 2 , the selected word line WL 4 , the nonselected word lines WL 1 to WL 3 and WL 5 to WL 8 , the selected bit line BL N , and the nonselected bit lines BL N-1 and BL N+1 are biased to the levels as shown in Fig. 1 and Fig. 2. Namely, the selection gates SG 1 and SG 2 are set to 5V, the selected word line WL 4 to 0V, the nonselected word lines WL 1 to WL 3 and WL 5 to WL 8 to 5V, the selected bit line BL N to 3V, and the nonselected bit lines BL N-1 and BL N+1 to 0V In a memory cell of an NAND type flash EEPROM, the threshold voltages V th0 and V th1 at the time when the data is "0" and "1" are usually as follows: The threshold voltage V th0 at the time of the data "0" when there is no charge present in the floating gate FG is about 1 to 2V. On the other hand, the threshold voltage V th1 at the time of the data "1" when there is a positive charge present in the floating gate FG is about -2 to -3V. Here, at the time of reading data, since a memory cell of the data "1" has a positive charge (state where electrons are withdrawn) in the floating gate FG in this way, the potential of the floating gate FG shifts to the positive side by 3 to 5V corresponding to the amount of the difference of the threshold voltage ΔV th at the time of the data "0". This will be explained below using equations. In the case of a read operation of an NAND type flash EEPROM, the potential V FG of the floating gate at a cell where the source-drain potential has fallen below 1V whether a memory cell of a nonselected bit line or a memory cell of a selected bit line, is expressed by the following equation: V FG = α·V WL +α(V THINIT -V TH ) Where is a coupling ratio (0.6 to 0.7), V WL is the word line voltage, V THINIT is the threshold voltage when there is no charge in the floating gate FG, that is, at the time of erasure by ultraviolet light, and V TH is the threshold voltage of the memory cell. Usually, in an NAND type flash EEPROM, the threshold voltage V THINIT at the time of erasure by ultraviolet light is the data "0" state or about 1 to 2V. A memory cell of the data "1" has a positive charge in the floating gate FG, so the threshold voltage V TH is set to -2V to -3V. However, a floating gate of a memory cell of the data "1" on a nonselected word line is supplied with not only the word line potential of the first term of equation (1) mentioned above, but also a positive voltage due to the second term, so a strong electric field is applied to the so-called tunnel oxide film. Accordingly, by continuing the read operation for a long period, in some cases electrons are implanted into the floating gate by the Fowler-Nordheim (FN) tunnelling effect and a memory cell of the data "1" is changed to the data "0", that is, there is the problem of occurrence of a so-called reading gate disturbance. GB-A-2 226 184 discloses a memory device in which erase operations of individual memory cells do not disturb the programmed states of adjacent cells. The memory cells each consist of a floating gate transistor whose floating gate overlaps the drain region by a significant amount. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor nonvolatile memory device which can prevent the occurrence of reading gate disturbances at the time of reading data. To achieve the above object, the present invention provides a NAND type semiconductor non-volatile memory device a memory cell floating gate field-effect transistor, said memory cell floating gate field-effect transistor having respective threshold values when at "0" and "1" states, wherein the channel of said memory cell floating gate transistor has a buried channel structure comprised of a first conductivity type channel portion in which a second conductivity type impurity is provided, such that the threshold value V THINIT of said memory cell floating gate field-effect transistor when the latter is at a state where no charge is stored in its floating gate is such that -1V < V THINIT ≤ OV. According to the present invention, when the threshold value of the data "0" where no charge is present in the charge storage portion is about 1 to 2V and the threshold voltage of the data "1" where a positive charge is present in the charge storage portion is about -2 to -3V, the threshold voltage V THINIT in the state with no charge in the charge storage portion is set to be such that -1V < V THINIT ≤ OV, between the data "0" and "1", by using a buried channel structure in which the channel of the memory cell transistor is made a first conductivity type (for example, P type) channel and is implanted with a second conductivity type (for example N type) impurity. In this way, by setting the threshold voltage at the time of the state of erasure by ultraviolet light to be within the aforementioned range, the amount of the positive charge at the data "1" state is greatly reduced. As a result, there is no longer a strong electric field applied to the tunnel oxide film and the reading gate disturbance at the time of reading of data is greatly mitigated. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become clearer from the following description of preferred embodiments with reference to the accompanying drawings, in which : Fig. 1 is a circuit diagram showing an example of a memory cell array of an NAND type flash EEPROM and a view showing the bias conditions at the time of reading, as a related art; Fig. 2 is a view of the bias conditions at the time of reading of a memory cell array of the NAND type flash EEPROM of Fig. 1; Fig. 3 is a cross-sectional view of a first embodiment of a flash EEPROM according to the present invention; and Figs. 4A to 4I are explanatory views of the process of production of a flash EEPROM according to Fig. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments the present invention will be described with reference to the accompanying drawings. Figure 3 is a cross-sectional view of a first embodiment as an NAND type flash EEPROM according to the present invention. The figure shows a memory cell structure connected to the N-th bit line BL N in the memory array of Figs. 4A to 4I. In Fig. 3, 1 represents a silicon substrate, 2 represents a P-type well, 3 represents a tunnel oxide film, 4 represents a buried channel structure, 5 represents a diffusion layer, 6 represents a bit diffusion layer, 7 represents a source diffusion layer, 8 represents a floating gate polycrystalline silicon layer, 9 represents an intermediate insulating film, 10 represents a control gate polycrystalline silicon layer, 11 represents a layer insulating film, 12 represents a bit line contact hole, and 13 represents an aluminum (Al) bit line. In this flash EEPROM, an N-type impurity, for example, phosphorus or arsenic, is ion implanted at the P-type channel formation region of the memory cell transistors to form a low concentration N-type layer, that is, the buried channel layer 4, and lower the threshold voltage V THINIT of the state with no charge present in the floating gate FG from the conventional 1 to 2V to set it to satisfy -1V < V THINIT ≤ OV. The conventional threshold voltage V th0 at the time of the data "0" where no charge is present in the floating gate FG of a memory cell is 1 to 2V. On the other hand, the threshold voltage V th1 at the time of the data "1" where a positive charge is present in the floating gate FG is -2 to -3V. In this memory cell, the threshold voltage V THINIT in the state with no charge present in the floating gate is set, as shown below, between the threshold voltage V th0 of the time of the data "0" where no charge is present in the floating gate FG and the threshold voltage V th1 at the time of the data "1" where a positive charge is present in the floating gate FG : V th1 <V THINIT <V th0 In this way, by setting within the aforementioned range the threshold voltage V THINIT at the time of the state of erasure by ultraviolet light to a depletion state (negative) from 0V, the amount of the positive charge at the state of the data "1" is greatly reduced. As a result, the second term [α(V THINIT -V TH )] in equation (1) mentioned above becomes much smaller and the reading gate disturbance at the time of reading data is greatly mitigated. Next, an explanation will be made of the method of production of an NAND type flash EEPROM according to the present embodiment with reference to Figs. 4A to 4I. First, as shown in Fig. 4A, a P-type well diffusion layer 2 of the memory portion is formed on the silicon substrate 1, then a tunnel oxide film 3 of a thickness of 10 to 11 nm or so is formed by the thermal oxidation method etc. Next, as shown in Fig. 4B, a resist pattern RGT is formed at the channel formation portions of the memory cell transistors and phosphorus + (P + ) ions (or arsenic + (As + ) ions) are implanted by for example 50 keV to 10 12 to 5 x 10 12 cm2 to form low concentration N-type layers, that is, buried channel layers 4, at the channel portions of the memory cell transistors. Next, the resist pattern is removed, then, as shown in Fig. 4C, a floating gate polycrystalline silicon layer 8 for forming the floating gates FG is formed on the tunnel oxide film 3 using polycrystalline silicon by for example the CVD method. The thickness of this floating gate polycrystalline silicon layer 8 is not particularly limited, but for example may be set to 100 to 200 nm . Next, the floating gate polycrystalline silicon layer 8 is etched by a pattern corresponding to the memory cell formation regions to remove the portions of the floating gate polycrystalline silicon layer 8 at regions where the selection gate transistors ST and ST2 are to be formed. Next, as shown in Fig. 4D the intermediate insulating film 9 is deposited on top. The intermediate insulating film 9 is not particularly limited, but for example use may be made of an ONO film (SiO 2 /SiN/SiO 2 film). The ONO film is formed for example as follows : First, the surface of the floating gate polycrystalline silicon layer 8 is heat oxidized to form an oxide film of not more than about 14 nm. On this heat oxidized film is formed a silicon nitride film of not more than about 11 nm by e.g. the CVD method. This surface is heat oxidized to form an oxide film of not more than about 2 nm. By this processing, it is possible to form a three-layer structure ONO film. This ONO film is low in leakage current and superior in film thickness control. The thickness of the ONO film is not more than 22 nm or so converted to a silicon oxide film. Next, as shown in Fig. 4E, just the portions of the intermediate insulating film 9 in the regions where the selection gate transistors ST1 and ST2 are to be formed are selectively removed, then a control gate polycrystalline silicon layer 10 for forming the control gates CG of the memory cell transistors and the gate electrodes of the selection gate transistors is formed on the tunnel oxide film 3 and intermediate insulating film 9 using polycrystalline silicon and for example the CVD method. The thickness of this control gate polycrystalline silicon layer 10 is not particularly limited, but for example is set to not more than 200 nm. Next, as shown in Fig. 4F, the control gate polycrystalline silicon layer 10, the intermediate insulating film 9, and the floating gate polycrystalline silicon layer 8 are successively etched to obtain the portions of the control gate polycrystalline silicon layer 10, the intermediate insulating film 9, and the floating gate polycrystalline silicon layer 8 for each of the memory cells MT1 to MT8. Further, at the same time, the gates of the selection gate transistors ST1 and ST2 are formed. Next, as shown in Fig. 4G, use is made of the resist film (not shown) at the time of etching for N-type ion implantation on the surface of the P-type well 2 in a self-alignment manner with the memory cell transistors MT to MT8 and the selection gate transistors ST1 and ST2 and thereby form the impurity diffusion layers 5, 6, and 7. Next, as shown in Fig. 4H, a layer insulating film 11 is deposited by e.g. the CVD method on the memory cell transistors MT1 to MT8 and the selection gate transistors ST1 and ST2. The layer insulating film 11 is comprised of for example a silicon oxide layer, silicon nitride layer, PSG layer, BPSG layer. The thickness of the layer insulating film 11 is not particularly limited, but for example may be 200 to 300 nm. Next, as shown in Fig. 4I, the bit line contact holes 12 are formed in the layer insulating film 11 by etching or other means, then a conductive layer comprised of aluminum (Al) is deposited by e.g. sputtering so as to enter into the contact holes 12. Next, the conductive layer is etched to form the aluminum bit lines 13. After this, an overcoat layer is formed, pad electrodes are formed, and other final processes performed to complete an NAND type flash EEPROM of the circuit configuration shown in Fig. 3. Note that in this embodiment, the bit lines 13 were comprised of aluminum, but of course they may also be comprised of other metals or other conductive materials. As explained above, according to the present invention, in an NAND type flash EEPROM, an N-type impurity is implanted in a P-type channel portion to form a so-called buried channel structure and reduce the threshold voltage in the state of zero charge present in a floating gate, that is, the threshold voltage V THINIT at the time of the state of erasure by ultraviolet light, from the usual 1 to 2V to be such that -1V < V THINIT ≤ OV, so the amount of the positive charge in the state of the data "1" can be greatly reduced and the reading gate disturbance at the time of reading data can be mitigated. Note that the present invention is not limited to the above embodiment and may be modified in various ways within the scope of the invention as defined by the appended claims. As explained above, according to the present invention, it is possible to prevent the occurrence of reading gate disturbances at the time of reading data.

Claims: A NAND type semiconductor non-volatile memory device comprising a memory cell floating gate field-effect transistor, said memory cell floating gate field-effect transistor having respective threshold values when at "0" and "1" states, wherein the channel of said memory cell floating gate transistor has a buried channel structure (4) comprised of a first conductivity type channel portion in which a second conductivity type impurity is provided, characterized in that the threshold value V THINIT of said memory cell floating gate field-effect transistor when the latter is at a state where no charge is stored in its floating gate (8) is such that -1V < V THINIT ≤ OV.

Inventors: ARASE KENSHIRO, MAARI KOICHI, ARASE, KENSHIRO, MAARI, KOICHI, ARASE, KENSHIRO, C/O SONY CORPORATION, MAARI, KOICHI, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: H01L27
IPC codes: G11C16, H01L21, H01L27