PIPELINED ANALOG-TO-DIGITAL CONVERTER WITH CURVEFIT DIGITAL CORRECTION

Abstract: An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying +/-Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured. In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, par example, capacitor value voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit stages, and using these voltage coefficients to further adjust the digital output word, providing an even more accurate digital representation of the analog input signal being mesured.

Description: PIPELINED ANALOG-TO-DIGITAL CONVERTER WITH CURVEFΓΓ DIGITAL CORRECTION Background of the Invention This invention pertains to analog-to-digital converters, and more specifically to pipelined analog-to- digital converters which, m accordance with the teachings of this invention, uuhze digital correction features Description of Pπor Art The typical N-bit pipelined analog-to-digital converter (ADC) consists of N 1-bit stages which, as shown in Figure 1, each clude a comparator 11, summing element 12, and gain element 13 The analog input signal Vm to stage 10 is multiplied by 2 by gain element 13. A reference voltage Vref is either added to or subtracted from 2*Vιn by summing element 12, depending upon the digital input signal Dm to stage 10. The resultant residual voltage Vres = 2 Vin± Vref ( 1 ) is applied the next stage. The polarity of residual voltage Vres is detected by comparator 11, whose output signal Dout serves as the digital input signal Din of the next stage Cascading N similar stages 10- 1 through 10-N results in an N-bit Analog-to-Digital converter, as shown in Figure 2, where the residual voltages of each stage are defined by equations (2), (3) and (4) Also shown in Figure 2 is a "zeroth" stage 10-0, providing an N+l bit ADC, which is the sign of the input voltage Vm In the example of Figure 2, stage 10-0 includes a one-times multiplier (for example, just a wired connection), and a comparator The residual voltages for subsequent stages are based on the preceding stages Vreε x = 2 ( Vin± Vref ) ( 2 ) Vres 2 = 2 { Vres^ ± Vr ef ) ( 3 ) Vres N = 2 ( V es N _ ± → ) ( 4 ) Ideally, the transfer function of each stage is given by Equaϋon 1 (for an input voltage of Vin), and is shown in graphical form in Figure 3, having two segments defined by equations (5) and (6) Vres = 2 { Vm + Vr ef ) ( 5 ) Vres = 2 { Vin - Vr ef ) ( 6 ) However, capacitor mismatch errors, charge injection, operauonal amplifier offset voltages, parasitic capacitance, and finite operational ampbfier gain result in vaπations in the single stage transfer function, as graphically depicted in Figures 4a-4d with a solid line, as differentiated from the ideal transfer funcϋon shown as the shaded l e. Figure 4a shows the ideal transfer function and the actual transfer function for a stage in which the gain factor of gam element 13 (Figure 1) is less than 2 as caused, for example, by capacitor mismatch; Figure 4b shows the ideal and actual transfer funcuons for a stage in which the gam is greater than 2 as caused, for example, by capacitor mismatch; Figure 4c shows the ideal and actual transfer function for a stage in which reference mismatch errors cause vertical shift; and Figure 4d shows the ideal and actual transfer functions of a stage in which charge injection in the comparator feedback switch causes a comparator offset Naturally, vaπous ones of these transfer function errors are combined in an actual device The gam error of a pipelined stage is due to capacitor mismatches (typically 0.10% for double-layer polycrystalline silicon capacitors). As the ratio vanes due to capacitor mismatch, the gain vanes, as shown in Figures 4a and 4b. Ga element 13 includes an operational amplifier which inherently has finite gain and offset errors The residual voltage (Vres) is the combinauon of 2*Vιn and ±Vref. Vanauons in the capacitor matching lead to a vertical shift the transfer function, as shown in Figure 4c Vres = 2 Vin± Vref+ ( 7 ) where α is a constant error in reference voltage Vref Ideally, the digital input signal Din is given by Din = 0, for Vin< 0 (8) Din = 1 , Vin> 0 (9) However, charge miecuon in comparator 1 1 causes a variation in the compaπson point, resulung in a hoπzontal shift in the transfer function, as shown in Figure 4d The combinauon of all these error mechanisms applied to a pipelined ADC lunits the resolution of the ADC Furthermore, redundancy must be added to me converter to account for overrange errors in which the transfer function exceeds ±Vref (see Figures 4b and 4c) This is done by using a gain less than 2 for each stage Therefore, a 16-bit Pipelined ADC with 0.1 % capacitor matching, lOmV of charge injecuon, lOmV of operational amplifier offset, a finite operational amplifier gam of 10,000, and an intra-stage gain of 1 97 results in a 1200 LSB linearity error, as depicted in Figure 5 Figure 5 is a graph having ADC code values (i.e., digital output words) on its X-axis, and the error, as measured in a muluple of the least significant bit value, displayed on its Y-axis As shown in Figure 5, for the cπteπa established for this example, a maximum error of approximately 1200 LSB is the undesirable result Charge injecuon, gam, and reference errors can be removed by using known techniques, such as self- calibrauon techniques, trimming capacitor values and reference values, and the use of dummy devices to minimize charge injecuon The majority of lineanty errors is due to the use of a 1 97 gam factor rather than the ideal gam factor of 2 It is known to remove these errors by calculaung three coefficients per stage, K Q , KJ , and K 2 (see Figure 6), and applymg them to the raw output data Once these coefficients K Q , KJ and K 2 are known for each stage, the lineanty error can be corrected, as described in 1993 IEEE Internauonal Solid-State Circuits Conference, Session 4, Paper WP 4.2 Figure 7 shows the progression of lineanty correcuon starting with calibraung LSB stage 10-N (i.e. stage 10-16 for an ADC where N=16), and progressmg towards the cahbrauon of successively more significant bit stages to the most significant bit stage 10-1 The resulting lineanty has a large fullscale and offset error. Thus, even by uUhzmg known techniques for minimizing the effects of charge injecuon, gain errors, and reference voltage errors, as well as the more complex pnor art technique of calculaung three digital coefficients per stage for applicauon to die raw, uncahbrated output data as correction factors, a significant error remains in analog-to-digital converters Accordingly, there remains the need to provide further accuracy in analog-to-digital conversions Summary A novel analog to digital converter system is taught in which raw ADC data is received and digitally manipulated in one or more ways in order to increase the accuracy of the resultant digital output word represenung the analog input voltage being measured In one embodiment, the digital manipulauon of this invenuon is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correcuon is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance In accordance with one embodiment of this invenuon, offset error and full scale error are determined by applying ±Vref as an input signal to the ADC These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital represen tion of the analog input voltage being measured In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, for example, the error due to capacitor voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit suges, and using these voluge coefficients to further ad|ust the digital output word, providing an even more accurate digital represenution of the analog input signal being measured Brief Description of the Drawings Figure 1 is a diagram depicung a typical pπor art 1-bit analog to digital converter stage; Figure 2 is a diagram of a typical pπor art N+l bit analog to digital converter; Figure 3 is a graph of the uansfer funcuon of an ideal analog to digital converter stage of Figure 1 , Figures 4a-4d are graphs depicung nonideal Uansfer funcuons due to vaπous inaccuracies in implemenung the analog to digital converter stage of Figure 1; Figure 5 is a graph depicung ADC code values verses error for a typical pnor art analog to digital converter; Figure 6 is a graph of a Uansfer funcuon for selected input voltages applied to an analog to digital converter to establish coefficients K Q , KJ, and K 2 , in accordance with a pπor art eπor correction technique; Figure 7 is a set of graphs depicting improving lineanty with increasing number of stages calibrated, Figure 8a depicts a uansfer funcuon of an analog to digital converter stage having gain error and residual voltage error, Figure 8b depicts a uansfer funcuon of an analog to digital converter stage showing hneranty error, Figure 9 is a block diagram depicung an analog to digital converter and circuitry for applying ±Vref to its input for calibrauon in accordance with this invenuon; Figure 10a is a graph depicting lineanty error after calibrating out single stage gain and charge injection errors; Figure 1 Ob is a block diagram depicung an analog to digital converter together with digital correction stages, in accordance with this invenuon; Figure 1 1 is a graph depicung die resulung lineanty error for an exemplary analog to digital converter including digital correcuon in accordance with this invenuon; Figure 12 is a block diagram depicung cahbrauon of a first MSB stage, once subsequent LSB stages have been calibrated; Figure 13 is a block diagram depicung an analog to digital converter including digital correction features as taught by the present invenuon; and Figure 14 is a graph depicung die improvement in analog to digital converter accuracy as a result of die second order cahbrauon feature of the present invention Detailed Descπpuon One important characteπsuc of a pipelined ADC is the attenuauon of error with respect to stage number. For example, me first (i.e. most significant bit) suge contnbutes 100% of its mismatches to die final linearity However, the second stage is isolated from die input by a ga of 2, leading to a 50% conUibution to the overall system errors Sunilarly, the third stage errors are reduced to 25% and die forth to 12 5% and so on Based on this feature of pipelined ADCs, in accordance with this exemplary embodiment of die present invention, curvefit calibration is only applied to die first four stages (i.e the most significant suiges 10- 1 through 10-4 of the exemplary ADC circuit of Figure 2), which results in an error of less than 1 LSB Naturally, it will be appreciated bv those of ordinary skill in die art in light of the teachings of this invenuon that the curvefit calibrauon taught bv dns invenuon can be applied to any number of stages m a pipelined ADC, depending on die desired amount of accuracy A second charactensuc of a pipelined ADC is the inherent analog "multimeter" contained within the pipe. For the moment, consider a 16-bit ADC (having stages 10-0 through 10-16), in which stage 10-1 is non-ideal widi a constant gam error and an associated residual voltage error as shown in Figure 8a, while all remaining stages (stages 10-2 through 10-16) are ideal. A lineanty sweep of an ADC under these condiuons, as shown in Figure 12, results m lineanty errors whose signature matches die signature of the non-ideal stage 10-1, as depicted m the graph of Figure 8b. This inherent feature of pipelined ADCs allows calibration of a given stage once stages for less significant bits have been calibrated. Cahbrauon of stages 10-6 ώrough 10-16 using pπor techniques, such as explained above, leads to large ga and offset errors. For interstage ga of 1.97, the gam error is in excess of 20,000 LSB (see Figure 7). By way of example, me integral non-lineaπty is calculated using a 16-bit pipelined ADC with lOppm/volt second order capacitor voltage coefficient. As is known, by using a differenual signal path, first order capacitor voltage coefficient is cancelled Figure 10a shows the lineanty error after calibrating out the single- stage gam and charge injecuon errors This is the resulting lineanty of pπor art ADC circuits after the calculauon of KQ, KJ and K 2 for stages 10-6 through 10-16 pnor to the curve- fit calibrauon of the present invenuon. Applying -t-Vref and -Vref as the input signal Vm to the pipelined ADC as shown in Figure 9, the ADC offset and ADC gain errors are determined. Digital correcuon terms are generated by applying -t-Vref to the ADC to measure tJhe ADC fullscale error and by applying -Vref to measure die ADC offset error The first correcuon term, gain, given by • _ fullscale error-offset error .... 2 N allows adjustment of the slope of the lineanty, for example by using a muluplier. Note that the denominator in equation (10) is equal to 65536 (2 ), the number of possible output codes from die ADC when the ADC contains 16 stages, by way of example The second correcuon term, offset, allows for adjustment of die offset of the lineanty, for example by using an adder For each normal conversion cycle, the raw digital output Dout(raw) is modified using gain and offset correcuon factors, as shown by Equauons 1 1 and 12 Dout. = Dout {raw) -of fset (11) and, following dns step, Dout {g/o corrected) = Dout. - Dout-_ x gain (12) where Dout(g/o corrected) is a digital output word including correcuon for gain and offset enors Once die offset and gain are calibrated, die linearity error is, for an exemplary 16 bit ADC, on the order of 2LSB ( 14 bits accurate), as shown in Figure 1 1. Figure 10b is a block diagram of a suucture m accordance widi die teachings of dns invention suitable for implemenung die correction factors exemplified by equauons ( 1 1 ) and ( 12) Figure 9 depicts how MSB stage 10- 1 is calibrated in accordance with die teachings of dns invention for removing me "system gam" and "svstem offset" errors Measurement of Second Order Coefficient Assuming stages 10-2 through 10-N were previously calibrated, for example by using techniques known in the pnor art as well as the offset and gam calibrauon of dns invenuon as descnbed above, diey may be used to measure die lineanty of die first stage, stage 10-1 and die ADC gain error and ADC offset error. A capacitor voltage coefficient error on die first stage results in a hyperbolic type ansfer funcuon in the lmeaπty plot. This hyperbola has its vertices at ±Vref/2, which, for a typical ADC operaung widi a Vcc of 5 volts, and thus using a Vref of 5 volts, this hyperbola has its veruces at approximately plus and minus 2.5 volts, as shown in Figure 11. Ideally, (no voltage coefficient) die digital output words are equal to: Dou t = 163 84 for Vin = -2 . 5 v ( 13 ) Dou t = 49152 for Vin = +2 . 5 v ( 14 ) However, when an inherent and undesirable error of, for example, a lOppm of capacitors second order voltage coefficient in the first stage 10-1, Dout is changed: Dou t = 16384 + E, for Vin = ~ Vref ( 15 ) Dout = 49152 - E, for Vin = + Vref ( 16 ) where E j and E 2 are digital values representing the error inuoduced by the lOppm voltage coefficient in the first stage for Vm = -Vref/2 and Vin = +Vref/2, respecuvely. By applying exactiy ±Vref/2 to die put of the first stage 10-1 after cahbrauon of stages 10-2 through 10-N (see Figure 12), me values of E j and E 2 are determined As an example, for a capacitor voltage coefficient of lOppm, tins results in E x = 2 . 1 LSB ( 17 ) E 2 = 2 . 1 LSB ( 18 ) Once E j and E 2 have been determined, generated coefficients allow die adjustment of the gain/offset corrected digital output word to provide die final digital output word Dout(fιnal), as depicted in Figure 13 The second order correcuon coefficients are defined as: SEC. = ^ ( 19 ) { ou tpu t : - Vref/ 2 ) 2 E ? SEC 2 = - ( 20 ) { ou tpu t : + Vref/2 -sign bi t) 2 where output:-Vref/2 is equal to the digital output word for an ideal situauon (i.e. widiout any enor) when the ADC receives an input voltage of -Vref/2. In die example where N=16 and Vref=5 volts, this value output:-Vref/2 is equal to 16384. Sundarly, outρut:+Vref72-sιgn bit is equal to the digital output word for an ideal situauon when die ADC receives an input voltage of +Vref/2, minus die digital value of die sign bit. In die example in which N=16 and Vref=5 volts, output:+ Vref/2 is equal to 49152 and the digital value of die sign bit is equal to 32768, and dius the value of output:+ Vref/2 - sign bit is equal to 16384. This results in the following operauons on the gain offset corrected version of Dout (Dout(g/o corrected) from the operauon of equauons (1 1) and (12), for example by die exemplary circuitry of Figure 10b) to provide a final value Dout(fιnal): if sign bi t=± , then Dout { final ) = (21) Dout { g/ o corrected) + { SEC 2 ) { Dout { g/ o corrected) -49152) 2 i f sign bi t=0 , then ,„. Dou t { final ) = Λ Dou t { g/ o corrected) + { SEC. ) {Dou t { g/ o corrected) -16384) 2 Figure 14 is a graph depicung a first curve Dout(g/o correcuon) showing a rather significant second order voltage coefficient exisung after gain and offset cahbrauon as taught by die present invenuon, but pnor to second order cahbrauon. The second curve Dout(final) of Figure 14 shows die much improved second order voltage coefficient resulung from second order calibrauon m accordance widi die teachings of dns invenuon. Second order calibrauon, widi linear gam and offset calibrauon, improves the total unadjusted error to 1/4 LSB accuracy with no offset or fullscale error Thus in accordance widi the teachings of dns invenuon several digital correction techniques are taught for improving the accuracy of pipelined analog to digital converters, by determining die nature of die inherent inaccuracies of die analog to digital converter and manipulaung the raw digital result from the ADC to provide a digitally conected highly accurate output word While the examples given above show digiud correction being performed using dedicated digital adders and multipliers, it will be appreciated by those of ordinary skill in the art m light of die teachings of dns invenuon that other types of digital manipulauon, such as widi microprocessors or table look up features, can be used widiout departing from the spirit of dns invenuon All publications and patent applications mentioned in tiiis specification are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The invention now being fully described, it will be apparent to one of ordinary skill in die art that many changes and modifications can be made diereto without departing from the spirit or scope of the appended claims.

Claims: WHAT IS CLAIMED IS 1. An analog to digital converter system compπsing- an analog to digital converter circuit for receiving an analog input signal and providing a raw digital output word representing said analog mput signal; and digital circuiuy for receiving said raw digital output word and providing a final digital output word representative of said analog mput signal, said digital circuiuy modifying said raw digital output word to adjust for errors in die gam and inherent offsets of said analog to digital converter cucuit. 2. An analog to digital converter system as in claim 1 which further compnses a cucuit to apply a first reference voltage as said analog input signal to obtam a digital output word indicauve of said offset errors and a second reference voltage as said analog input signal to obtam a digital output word indicative of said gam errors. 3. An analog to digital converter system as in claim 2 wherein said second reference voltage is die same magnitude and opposite sign as said first reference voltage. 4. An analog to digital converter system as in claim 2 wherein said digital cucuitry comprises a summer for adjusung said raw digital output word to correct for said offset enors 5. An analog to digital converter system as in claim 2 wherein said digital cucuitry compnses a multiplier for adjusung said raw digital output word to correct for said gam enors 6. An analog to digital converter system as in claim 2 wherein said digital circuiuy compnses a processor for adjusting said raw digital output word to correct for said offset errors 7. An analog to digital converter system as in claim 2 wherein said digital circuitry compnses a procesor for adjusting said raw digital output word to correct for said ga errors. 8 An analog to digital converter system as m claim 1 which further compnses circuitry for calibrating one or more LSB stages of said analog to digital converter cucuit pnor to determining said ga and offset errors 9. An analog to digital converter system as in claim 2 wherein said analog to digital converter circuit uses reference voltages of ±Vref, and said first and second reference voltages are ±Vref 10 An analog to digital converter system as in claim 2 which further compnses circuitry for applying tinrd and fourth reference voltages as said analog input signal to obtain digital words indicauve of second order errors 1 1 An analog to digital converter system as in claim 10 wherein said fourth reference voltage is the same magnitude and opposite sign as said third reference voltage 12 An analog to digital converter system as in claim 10 wherein said digital cucuiuy comprises a summer tor adjusung said raw digital output word to correct for said second order errors 13 An analog to digital converter svstem as in claim 10 wherein said digital circuiuy comprises a processor for ad)ustιng said raw digital output word to correct for said second order errors 14. An analog to digital converter system as in claim 10 wherein said analog to digital converter circuit uses reference voltages of ±Vref, and said third and fourth reference voltages are ±Vref/2. 15. A method for calibrating an analog to digital converter system comprising the steps of: calibrating a plurality of LSB stages; applying a first reference signal to said analog to digital converter to obtain a first digital output word indicative of die offset error of one or more uncalibrated MSB stages; and applying a second reference signal to said analog to digital converter to obtain a second digital output word indicative of the gain error of said one or more uncalibrated MSB stages. 16. A method as in claim 15 wherein said analog to digital converter system used as reference voltages ±Vref, and said first an second reference signals are ±Vref. 17. A method as in claim 15 which further comprises e steps of: applying tiήrd and fourth reference voltages to said analog to digital converter system to determine a second order error coefficient- 18. A method as in claim 17 wherein said diird and fourth voltages are equal to ±Vref/2. 19. A method for operating an analog to digital converter system comprising the steps of: calibrating a plurality of LSB stages; applying a first reference signal to said analog to digital converter to obtain a first digital output word indicative of die offset error of one or more uncahbrated MSB stages; applying a second reference signal to said analog to digital converter to obtain a second digital output word indicative of die gain error of said one or more uncalibrated MSB stages; and applying an unknown analog input signal to said analog to digital converter to obtain a raw digital output word indicative of said analog input signal; modifying said raw digital output word utilizing said first digital output word in order to provide a final digital output word which more accurately represents said analog input signal. 20. A metiiod as in claim 19 wherein said analog to digital converter system used as reference voltages ±Vref, and said first an second reference signals are ±Vref. 21. A method as in claim 19 which further comprises the steps of: applying third and fourth reference voltages to said analog to digital converter system to determine a second order error coefficient. 22. A method as in claim 21 wherein said third and fourth voltages are equal to ±Vref/2. 23. A metiiod as in claim 17 which further comprises a step of modifying said raw digital output word in response to said second order error coefficient to provide said final digital output word.

Inventors: CHIN SING W, MAYES MICHAEL K, CHIN, SING, W., MAYES, MICHAEL, K.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1994
Main classification: H03M1
IPC codes: H03M1