Video signal processing apparatus and its method

Abstract: In shuffling used as efficient coding method of input digital video signal, input digital television signals of different standards are judged in an input judging circuit, the judged information is sent out into a memory write control circuit and a memory read control circuit, the memory write control circuit determines the offset value of the vertical address according to the judgement signal, and writes the input signal at a position corresponding to the screen of the determined shuffling region of the shuffling range corresponding to each signal in the shuffling memory, or writes the block out of the shuffling range into the shuffling memory according to the specified control method in the vacant region of the shuffling range, and the memory read control circuit changes over the offset value of the vertical address to be read out from the memory and the address control according to the judgement information.

Description: FIELD OF THE INVENTION The present invention relates to a video signal processing apparatus for shuffling used as means of efficient coding of digital video signal, and its method, and more particularly to a video signal processing apparatus capable of shuffling more effectively, while decreasing the hardware capacity. when sharing with television signals of plural different standards. and its method. BACKGROUND OF THE INVENTION Shuffling is known as one of the means of efficient coding for recording existing television signals. In this technique, the block arrangement composed of input digital video signals is divided into plural regions, a specific number of blocks are obtained from specific positions of each region to form video segments, and while sequentially shifting the specific positions in each region, video segments are formed progressively.. Accordingly, the data correlation within video segment is weakened, and fluctuations of data length of digital video signals within video segment in each video segment can be prevented at the time of coding process. What matters when applying shuffling in high definition television signal (HDTV) is sharing of the shuffling circuit of a large hardware complexity by digital television signals of different standards. At the present, there are three standards of HDTV as specified by the number of scanning lines and field frequency, that is, 1125 lines/60 Hz (hereinafter called 1125 system), 1050 lines/60 Hz (1050 system), and 1250/50 Hz (1250 system). Between 1050 system and 1250 system, the number of horizontal active pixels per line is the same, and the circuit can be shared by varying the offset value in the vertical direction. In 1125 system, however, since the numbers of horizontal and vertical active pixels are both different from the other standards, and there is no matching at all. and hence sharing of circuit is extremely difficult. A video signal processing apparatus according to the preamble of claims 1 and 4 is described in EP-A-0 469 861. SUMMARY OF THE INVENTION It is hence a primary object of the invention to present a video signal processing apparatus capable of sharing a shuffling circuit of a large circuit complexity between television signals of different standards, decreasing the additional hardware capacity, and shuffling effectively, by adding a circuit of a small complexity, and its method. To achieve the above object, the invention provides video signal processing apparatus comprising: means for determining the television system format of an input video signal, said input video signal being arranged in blocks; a memory region, a plurality of overlapping shuffling regions of said memory region each corresponding to a television system for storing the input video signal, said plurality of shuffling regions having a common horizontal length and having vertical lengths determined by the corresponding television system; said input video signal comprising an input signal region having horizontal and vertical lengths determined corresponding to the television systems respectively; control means arranged to control the storing in said memory region and reading out from said memory region of the input video signal; said control means being arranged to store the input video signal in the corresponding shuffling region of the memory, said control means being further arranged to shuffle the stored input video signal in units of one block on reading out the stored input video signal from the shuffling region in the memory; characterised in that for at least one of said television systems, said input signal region and said corresponding shuffling region have different dimensions and for said at least one case, a main portion of said input signal region is defined comprising the area of overlap of said input signal region and said memory region, the data from said overlapping region of said input signal being always written into said overlapping area of said memory region in substantially the same configuration independently of the determined television system format, the remainder of said input signal region not in said main portion is written to the remainder of the shuffling region. The invention also provides a method for processing a video signal comprising the steps of determining the television system format of an input video signal, said input video signal being arranged in blocks; defining a plurality of overlapping shuffling regions in a memory region each corresponding to a television system for storing the input video signal, said plurality of shuffling regions having a common horizontal length and having vertical lengths determined by the corresponding television system; said input video signal comprising an input signal region having horizontal and vertical lengths determined corresponding to the television systems respectively; storing the input video signal in the corresponding shuffling region of the memory, shuffling the stored input video signal in units of one block on reading the input video signal out of the shuffling region; characterised in that for at least one of said television systems, said input signal region and said corresponding shuffling region have different dimensions and for said at least one case, a main portion of said input signal region is defined comprising the area of overlap of said input signal region and said memory region the data from said overlapping region of said input signal always being written into said overlapping area of said memory region in substantially the same configuration independently of the determined television system format, the remainder of said input signal region not in said main portion is written to the remainder of the shuffling region. In this constitution, when the control means writes an input signal into a memory, the image of the input signal and the region of the shuffling memory are matched at an offset position of a specified value, and the pixel in the shuffling memory region is written into a position corresponding to the screen of the shuffling memory, while the pixel out of the shuffling memory region is written into a vacant region of the shuffling range of the shuffling memory in a basic unit of the region of an integer multiple (including a multiple of 1) of blocks. Thus, the control means of memory writing and reading is provided with means for achieving correspondence of the region of shuffling memory depending on the input television signal, so that the memory reading control circuit of a large circuit complexity and the shuffling memory can be shared effectively between plural television systems, and therefore if television signals of different systems are entered, shuffling can be effected in a small circuit complexity. Moreover, the vacant region when shuffling is decreased, which makes it possible to suppress fluctuations of the quantity between the video segments in which data in empty region is entered and other video segments. BRIEF DESCRIPTION OF THE INVENTION Fig. 1 is a block diagram of a video signal processing apparatus in an embodiment of the invention. Fig. 2 (a) is a conceptual diagram showing arrangements of macro blocks of 1125 system in a first embodiment of the invention. Fig. 2 (b) is a conceptual diagram showing arrangements of macro blocks when data shown in Fig. 2 (a) is written into a memory. Fig. 3 (a) is a conceptual diagram showing a first macro block arrangement subjected to conversion in Fig. 2 (a). Fig. 3 (b) is a conceptual diagram showing a converted macro block arrangement of Fig. 3 (a). Fig. 3 (c) is a conceptual diagram showing a second macro block arrangement subjected to conversion in Fig. 2 (a). Fig. 3 (d) is a conceptual diagram showing a converted macro block arrangement of Fig. 3 (c). Fig. 4 (a) is a conceptual diagram showing arrangements of macro blocks of 1125 system in a second embodiment of the invention. Fig. 4 (b) is a conceptual diagram showing arrangements of macro blocks when data shown in Fig. 3 (a) is written into memory. EMBODIMENTS OF THE INVENTION In Fig. 1, an example of sharing a circuit between 1050 system and 1125 system is explained. First, a digital video signal entered from an input terminal 1 is issued to an input judging circuit 2. In a first embodiment, it is supposed that a digital video signal sampling a luminance signal at sampling frequency 40.5 MHz and a color difference signal at sampling frequency 13.5 MHz is supplied. In the input judging circuit 2, it is judged whether the input digital video signal is of 1125 system or of 1050 system, and the judged signal is sent into a memory write control circuit 5 as a signal 4, and into a memory read control signal 7 as a signal 6, and the digital video signal is issued into a memory 3 for making input and output by receiving a control signal from outside. The memory write control circuit 5 and memory read control circuit 7 are collectively called control means. The memory write control is described below. In the memory control circuit 5 in which the judgement information of the input judging circuit 2 is fed as the signal 4, when the judgement information indicates the 1050 system, the input signal is written into a position corresponding to the screen , in a shuffling memory region specified in the shuffling range corresponding to the individual signals in the memory 3. When the judgement information indicates the 1125 system, by the specified control as mentioned below, the signal is written into the same shuffling memory region as in the 1050 system. At this time of writing, the digital video signal is converted into a macro block unit which is the minimum unit of shuffling. This macro block is composed without dividing the discrete cosine transform block (DCT block) which is the minimum video segment of luminance signal and color difference signal, being constituted of a DCT block of a plurality of luminance signals corresponding to the same positions on the screen, and at least one color difference signal each. Accordingly, one macro block in the embodiment is composed of a total of eight DCT blocks, comprising six DCT blocks of luminance signal consisting of three DCT blocks in the horizontal direction and two DCT blocks in the vertical direction, and two DCT blocks of color difference signal consisting of one R-Y signal (C R ) which is one of the color difference signals positioned in the same range as the six luminance signals on the screen, and other color difference signal B-Y (C B ). That is, one macro block is generally composed of n DCT blocks of one kind of color difference signal, n DCT blocks of another kind of color difference signal in the same image range, and, ordinarily, plural DCT blocks of m luminance signals in the same image range as the DCT blocks of the color difference signals. In correspondence of the macro block constitution with the input signal, the macro block constitution of one frame each consists of 42 macro blocks in the horizontal direction and 64 macro blocks in the vertical direction in 1125 system, and 45 macro blocks in the horizontal direction and 60 blocks in the vertical direction in 1050 system. Fig. 2 shows the mode of conversion of input signal as the writing is actually controlled in 1125 system. Fig. 2 (a) shows arrangements of macro blocks of input signals, and Fig. 2 (b) shows arrangements of macro blocks when written into the memory by controlling the input signal. Regions A, B, C. D, E in Fig. 2 (a) are offset by the portion of two macro blocks in the vertical direction, and written into (60 vertical macro blocks, 9 horizontal blocks) × 4 + (60 vertical macro blocks, 6 horizontal macro blocks). The remaining upper and lower regions (2 vertical macro blocks, 42 horizontal macro blocks) each are divided into twenty regions of No. 1 to No. 20 of (1 vertical macro block, 9 horizontal macro blocks), or (1 vertical macro block, 9 horizontal macro blocks) as shown in Fig. 2 (a). These twenty regions are converted into (3 vertical macro blocks, 3 horizontal blocks) in the numerical sequence as shown in Fig. 3 (b) when there are nine horizontal macro blocks as shown in Fig. 3 (a), or into (2 vertical macro blocks, 3 horizontal macro blocks) in the numerical sequence as shown in Fig. 3 (d) when there are six horizontal macro blocks as shown in Fig. 3 (c), while dummy data, such as gray level, is fed into the remaining three macro blocks in shaded area. Numerals in Fig. 3 denote the sequence of macro blocks in the regions from No. 1 to No. 20. Thus converted (3 vertical macro blocks, 3 horizontal macro blocks) are written in the numerical sequence shown in Fig. 2 (a), at the numerical positions at the right side of regions A, B, C, D in which (60 vertical macro blocks, 9 horizontal macro blocks) are written, and E in which (60 vertical macro blocks, 6 horizontal blocks) are written, as shown in Fig. 2 (b). The read control from memory is described below. In Fig. 1, in the memory read control circuit 7 in which the judgement signal of the input judging circuit is fed as signal 6, one macro block at respective position is read out from five regions composed of (60 vertical macro blocks, 9 horizontal macro blocks) shown in Fig. 2 (b), and five macro blocks are read out and shuffled, and video segments are formed and issued. The digital video signals being read out from the memory 3, shuffled, and converted into video segments are issued sequentially from an output terminal 8. The signals coming out of the output terminal 8 are subjected to processing such as compression and error correction in video segment, and finally recorded in a magnetic tape 9. In this embodiment, only two macro blocks are offset in the vertical direction, but it may be also possible to dispose, without offsetting, four macro blocks in the vertical direction not included in the 60 macro blocks in the vertical direction, at the right side of the region E, and the sequence of arrangement of macro blocks is not limited to the illustrated example, but may be specified as desired. Explained next is a case of sharing with the 1250 system. At this time, in the input judging circuit 2, the digital video signal entered from the input terminal 1 is judged to be of 1125 system, 1050 system or 1250 system, and the judged information is sent into the memory write control circuit 5 as signal 4 and into the memory read control signal 7 as signal 6, and the digital video signal is sent out into the memory 3 for making input and output by receiving a control signal from outside. The input macro block configuration of 1250 system consists of 45 horizontal macro blocks and 72 vertical macro blocks, and therefore a memory region for accepting the 1250 system must be prepared. The memory write control in this case is described below. In the memory write control circuit 5 in which the judgement information of the input judging circuit 2 is fed as signal 4, when the judgement information indicates the 1050 system or 1250 system, the input signal is written in a range corresponding to the screen, in the determined shuffling memory region of the shuffling range corresponding to each signal in the memory 3, that is, in the shuffling memory region of 60 vertical macro blocks in the 1050 system or in 72 vertical macro blocks in the 1250 system. When the judgement information indicates the 1125 system, by the same control as above, the signal is written into the shuffling memory region of 60 vertical macro blocks same as in the 1050 system. As a result, the macro block arrangement in the memory consists of (60 vertical macro blocks, 45 horizontal macro blocks) in the 1050 system and 1125 system, and (72 vertical macro blocks, 45 horizontal macro blocks) in the 1250 system. In this example, the reading control from the memory is described below. In the memory read control circuit 7 in which the judgement information of the input judging circuit is fed as signal 6, the reading control is changed between the 1050 system or 1125 system, and the 1250 system. In the former two systems, the number of macro blocks in the horizontal direction is same, and only the number of macro blocks in the vertical direction is different, and the problem can be solved only by changing the offset value of the reading address in the vertical direction and the address control. That is, one macro block at a specified position is read out from five regions composed of (60 vertical macro blocks, 9 horizontal macro blocks) shown in Fig. 2 (b) in the memory 3 in the case of 1050 system and 1125 system, or from five regions composed of (72 vertical macro blocks, 9 horizontal macro blocks) in the case of 1250 system, and five macro blocks are read out and shuffled, and video segments are formed and issued. Processing after being read out from the memory 3 is same as above. The digital video signals shuffled and converted into video segments are sequentially sent out from the output terminal 8. The processing after the output terminal 8 is same as above. Hence, the circuit may be easily shared with the 1250 system. If there is a memory for the 1250 system, the signal of the 1125 system can be written into the memory 3 without changing as mentioned above. In this case, same as in the case of 1250 system, it is enough to change the offset value of the reading address in the vertical direction of the memory read control circuit 7 and the address control, but the data-free region (3 horizontal macro blocks × 64 vertical blocks) is also included in the video segment, and the difference of the data length of the digital video signal in the video segment increases, and the effect obtained by shuffling decreases. Besides, the effect of shuffling may be also maintained by completely changing the reading control from the memory. At this time, however, the operation of the memory read control circuit 7 is completely free from matching with the other two systems, and the circuit complexity increases. A second embodiment is explained by reference to Fig. 1, in which the sampling frequency of input digital video signal is 54 MHz for luminance signal, and 27 MHz for color difference signal. In the input judging circuit 2, it is judged whether the input digital video signal is of 1125 system or of 1050 system, and the judged information is issued to the memory write control circuit 5 as signal 4, and to the memory read control circuit 7 as signal 6, and the digital video signal is sent to the memory 3 for making input and output by receiving a control signal from outside. At this time of writing, the digital video signal is converted in the macro block unit which is the minimum unit for shuffling, same as in the first embodiment. The macro block is composed without dividing the DCT block which is the minimum video segment of luminance signal and color difference signal, and consists of a plurality of DCT blocks of luminance signals and color difference signals corresponding to the same positions on the screen. Hence, one macro block in this embodiment is composed of a total of six DCT blocks, consisting of luminance signal of four DCT blocks comprising two DCT blocks in the horizontal direction and two DCT blocks in the vertical direction, and two DCT blocks of color difference signal comprising one C R and one C B at the same positions as the luminance signals on the screen. Comparing the macro block constitution with the input signals, the macro block constitution of each frame comprises 84 horizontal macro blocks and 64 vertical macro blocks in the 1125 system, and 90 horizontal macro blocks and 60 vertical macro blocks in 1050 system. Fig. 4 shows the mode of conversion of input signal by actual control of writing to 1125 system, by using a shuffling memory corresponding to 1050 system. More specifically, Fig. 4 (a) shows macro block arrangements of input signals, and Fig. 4 (b) relates to macro block arrangements when written into the memory by controlling the input signals. Regions A, B, C, D and E in Fig. 4 (a) are offset in the vertical direction by the portion of two macro blocks, and written into five regions of (60 vertical macro blocks, 18 horizontal macro blocks) × 4 + (60 vertical macro blocks, 12 horizontal macro blocks) as shown in Fig. 4 (b). The remaining upper and lower regions of 2 vertical macro blocks and 84 horizontal macro blocks each are divided into 28 regions of two vertical macro blocks and six horizontal macro blocks as shown in Fig. 4 (a). These 28 regions are written in the positions corresponding to the numbers at the right side of the regions A, B, C, D and E thus written, as shown in Fig. 4 (b), in the numerical sequence in the diagram without changing the constitution of the macro blocks in the region. The reading control from the memory is explained next. In the memory read control circuit 6 in which the judgement information of the input judging circuit 2 is fed as signal 6, one macro block at specified position each is read out from five regions composed of 60 vertical macro blocks and 18 horizontal macro blocks shown in Fig. 4 (b), and five macro blocks are read out and shuffled, and video segments are formed and issued from the memory 3. The digital video signals being read out from the memory 3, shuffled and converted in video segments are sequentially sent out from the output terminal 8. The signal coming out of the output terminal 8 is processed by compression, color correction, etc. in video segment unit, and is finally recorded in a magnetic tape 9. In this embodiment, too, two macro blocks are offset in the vertical direction, but, without offsetting, it is also possible to dispose the four vertical macro blocks not contained in the 60 vertical macro blocks at the right side of block E, or the configuration of the macro blocks may be freely determined without being limited to the illustrated example. In this embodiment, sharing with 1250 system is explained. At this time, in the input judging circuit 2, it is judged whether the digital video signal entered from the input terminal 1 is of 1125 system, 1050 system or 1250 system, and the judged information is sent out to the memory write control circuit 5 as signal 4, to the memory read control circuit 7 as signal 6, and the digital video signal is issued to the memory 3 for making input and output by receiving a control signal from outside. The input macro block of 1250 system consists of 90 horizontal macro blocks and 72 vertical macro blocks. The writing control of the memory is described below. In the memory write control signal 5 in which the judgement information of the input judging circuit 2 is fed as signal 4. when the judgement information indicates the 1050 system or 1250 system, the input signal is written into a position corresponding to the screen, in the determined shuffling memory region of the shuffling range corresponding to each signal in the memory 3. When the judgement information indicates the 1125 system, by the same control as above, the signal is written in the same shuffling memory region as in the 1050 system. As a result, the macro block arrangement in the memory consists of (60 vertical macro blocks, 90 horizontal macro blocks) in 1050 system and 1125 system, and (72 vertical macro blocks, 90 horizontal macro blocks) in 1250 system. Explained next is the read control from the memory. In the memory read control circuit 7 in which the judgement information of the input judging circuit 2 is fed as signal 6, the read control is changed between the 1050 system or 1125 system, and the 1250 system. In the former two systems, the number of macro blocks in the horizontal direction is same, and only the number of macro blocks in the vertical direction is different, and therefore it is enough to alter the offset value of the address of reading in the vertical direction and the address control. That is, one macro block at a specific position is read out each from five regions composed of (60 vertical macro blocks, 18 horizontal macro blocks) shown in Fig. 4 (b) in the memory 3 in the case of 1050 system and 1125 system, and from five regions of (72 vertical macro blocks, 18 horizontal macro blocks) in the case of 1250 system, and five macro blocks are read out and shuffled, and video segments are formed and issued. The processing after being read out from the memory 3 is same as above. The digital video signals being shuffled and converted in the video segment are sequentially issued from the output terminal 8. The processing after the output terminal 8 is same as in the case of the first embodiment. Hence, even when sharing with the 1250 system, the circuit can be easily used commonly. Where the memory for 1250 system is provided, the signal of 1125 system can be written into the memory 3 without changing as mentioned above. In this case, same as in the case of 1250 system, it is enough to change the offset value of the reading address in the vertical direction of the memory read control circuit 7 and the address control, but since the data-free region (6 horizontal macro blocks × 64 vertical macro blocks) is also included in the video segment, and the shuffling effect decreases due to the same reason as in the first embodiment. Besides, by completely changing the read control from the memory, it is also possible to maintain the shuffling effect. However, in such a case, the operation of the memory read control circuit 6 has not conformity with the other two signals systems at all, and the circuit complexity increases. Thus, the invention is capable of processing regardless of the sampling frequency of the input signal. Besides, the manner of selecting the macro blocks to be converted, the writing position of the macro blocks to be converted, the data to be used as dummy data, and the manner of selecting the macro blocks for inserting the dummy data are all free and arbitrary.

Claims: Video signal processing apparatus comprising: means for determining the television system format of an input video signal, said input video signal being arranged in blocks; a memory region, a plurality of overlapping shuffling regions of said memory region each corresponding to a television system for storing the input video signal, said plurality of shuffling regions having a common horizontal length and having vertical lengths determined by the corresponding television system; said input video signal comprising an input signal region having horizontal and vertical lengths determined corresponding to the television systems respectively; control means arranged to control the storing in said memory region and reading out from said memory region of the input video signal; said control means being arranged to store the input video signal in the corresponding shuffling region of the memory, said control means being further arranged to shuffle the stored input video signal in units of one block on reading out the stored input video signal from the shuffling region in the memory; characterised in that for at least one of said television systems, said input signal region and said corresponding shuffling region have different dimensions and for said at least one case, a main portion of said input signal region is defined comprising the area of overlap of said input signal region and said memory region, the data from said overlapping region of said input signal always being written into said overlapping area of said memory region in substantially the same configuration independently of the determined television system format, the remainder of said input signal region not in said main portion is written to the remainder of the shuffling region. Video signal processing apparatus according to Claim 1, wherein the control means is arranged to shuffle and read out the stored input video signal in the shuffling region in units of macro blocks composed of a plurality of DCT (discrete cosine transform) blocks. The video signal processing apparatus of either of claims 1 and 2, wherein dummy data is stored to a portion in the remainder of the memory region in which none of said input video signal is stored. A method for processing a video signal comprising the steps of determining the television system format of an input video signal, said input video signal being arranged in blocks; defining a plurality of overlapping shuffling regions in a memory region each corresponding to a television system for storing the input video signal, said plurality of shuffling regions having a common horizontal length and having vertical lengths determined by the corresponding television system; said input video signal comprising an input signal region having horizontal and vertical lengths determined corresponding to the television systems respectively; storing the input video signal in the corresponding shuffling region of the memory, shuffling the stored input video signal in units of one block on reading the input video signal out of the shuffling region; characterised in that for at least one of said television systems, said input signal region and said corresponding shuffling region have different dimensions and for said at least one case, a main portion of said input signal region is defined comprising the area of overlap of said input signal region and said memory region the data from said overlapping region of said input signal always being written into said overlapping area of said memory region in substantially the same configuration independently of the determined television system format, the remainder of said input signal region not in said main portion is written to the remainder of the shuffling region. A method ofprocessing a video signal according to claim 4, wherein the step of shuffling the stored input video signal on reading the input video signal out of the shuffling region is effected in units of macro blocks composed of a plurality of DCT (discrete cosine transform) blocks. A method for processing a video signal according to either of claims 4 or 5 further comprising the step of storing dummy data in the remainder of the memory region in which none of said input video signal is stored.

Inventors: AWAMOTO SIGERU, FUJIWARA YUJI, MATSUDA TOYOHIKO, NISHINO SHOUICHI, AWAMOTO, SIGERU, FUJIWARA, YUJI, MATSUDA, TOYOHIKO, NISHINO, SHOUICHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H04N9
IPC codes: H04N5, H04N7, H04N9, H04N11