ADDRESS GENERATOR FOR SOLID STATE DISK DRIVE

Abstract: An address generator (26) for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number (50) to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Description: ADDRESS GENERATOR FOR SOLID STATE DISK DRIVE FIELD OF THE INVENTION This invention relates to address generators and more specifically to an address generator for a "solid state disk" which is a random access memory device which appears to a host computer system to be a disk drive. Description of the Prior Art The well known SCSI interface is ideal for high performance solid state disks. Unlike ESDI or SMD interfaces, the SCSI interface presents the peripheral with the number of the desired logical block to be accessed. Solid State Disks (SSDs) , based on contiguous random access (semiconductor) memory chips, can access the proper information based on the specified logical block. An example of an SSD (which however is not block-length oriented) is disclosed in U.S. Patent No. 5,070,474. Referring to the system diagram in Figure 1, the SCSI host computer 10 presents the SSD 12 with a command to read or write along with the desired logical block and the number of blocks to be written or read on SCSI bus 14. The SSD controller 16 must interpret this command received from SCSI interface 18 and set the DRAM memory array 22 (DRAM chips) to the appropriate starting address via address generator 26. This is analogous to the seek time in a rotating (physical) disk drive. The controller 16 then reads or writes the proper number of blocks to the memory array 22 on address bus 24. (Block-length oriented SSDs are known in the art.) Address generator 26 operates in response to signal AGEN from controller 16. SSD 12 also conventionally includes DMA (direct memory address) controller 30 and error correction circuitry 32 connected by various busses as shown. Also included is a backup interface 34 and backup physical disk 38. A difficulty arises due to the variable length of the logical blocks. Consider a typical host computer system 10 based on a logical block length of 512 bytes per block. Block zero begins at an address of zero, block one begins 512 bytes later, block two at 1024 bytes and so on. Should a second system be based upon a block size of 256 bytes per block these addresses would change. In this case block zero would still begin at byte zero, but block one would occur at byte 256, block two at byte 512 and so on. The method for locating the desired starting address is: Starting Address = Desired Logical Block x Logical Block Length While the method is simple, the magnitude of the variables causes difficulty. The SCSI read/write extended commands specify the desired logical block as a 32 bit variable. The logical block length is as large as 16 bits in a typical computer system. Normally this multiplication is performed in software in a microprocessor or microcontroller 16 using multiply functions or various shifting techniques. Such operations on variables of this magnitude can require many machine cycles on small (reasonably priced) microcontrollers. This results in long seek times which are undesirable in a solid state disk. Microcontrollers allowing 32 bit operations are expensive, difficult to embed and otherwise unnecessary for a typical SCSI peripheral. SUMMARY OF THE INVENTION The present invention in one embodiment includes a dedicated logic circuit for determining the desired starting address of an SSD operation (read or write) . The circuit is a multiplier circuit which, as data block numbers are received by the multiplier, multiplies the data block number by a block size value to quickly generate the address. The block size value is (in one embodiment) programmed once, at power up of the SSD, with the appropriate value for the desired block size. (Alternatively the block size value is dynamically alterable after power up) . The access time is in the submicrosecond range for any typical block size. In a typical SCSI application where a physical (not solid state) disk drive is used, the speed limit of the system is fairly low due to the relatively slow access time of a physical disk drive. The same is true for the relatively slow access time for tape drives and other types of rotating magnetic memory. Thus in these cases, there is no need for a higher speed address generator than that provided in the prior art software address generation calculation, and so use of a dedicated multiplier logic circuit in a physical disk drive address generator would not appear generally to be useful. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a solid state disk drive system diagram. Fig. 2 is a typical computer peripheral interface bus command packet. Fig. 3 is a block diagram of an address generator in accordance with the invention. Fig. 4 is a schematic diagram of an address generator in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION A SCSI peripheral is a block oriented device. Read or write operations specify a starting logical block, and the number of blocks to be written or read. The logical block size is selected by the host computer using a mode select command. The SCSI peripheral stores the logical block size in a non-volatile location. This logical block size remains valid until a subsequent mode select command modifies the block size again. During the initial power up phase, a SCSI SSD retrieves the appropriate size value for logical blocks. The correct logical block size multiplication factor is then programmed into the address generation circuit in accordance with the invention. Normal operation begins when the host computer system issues a read or write command to the SSD. The SCSI interface logic receives the command and checks the validity of the command packet. An example of a SCSI valid command packet is shown in Figure 2. Bytes 02 to 05 specify the logical block at which the read operation is to begin. When the command has been determined valid, the SCSI interface logic 18 signals the microprocessor 16 in the SSD that a valid command packet is present in the buffer of the SCSI interface logic 18. The microprocessor 16 then reads the command packet from the SCSI interface 18 buffer. If the command is determined to require reading or writing data, then the microprocessor 16 transfers the starting logical block information directly to the address generation circuit 26. Figure 3 shows in a block diagram an address generation circuit 26 in accordance with the present invention. The block number (which in this example is a 32 bit value) is received over an input bus 50 from a SCSI port (not shown) . In one version bus 50 instead of being a 32 bit bus is an 8 bit bus, data on which is provided sequentially in four 8 bit bytes. The block number is then received into a 32 bit set of latches 54. In response to a clock signal CLK, the latches 54 transmit their data to a shift register 58 having 32 bits. Separately, at power up of the address generation circuit 26, a block size value is provided on an 8 bit bus 62 as an input data signal to a registered counter 66 which is an 8 bit device. (In this case the input data signal is an 8 bit multiplication factor, not the actual block size, but derived therefrom as described below.) The registered counter 66 has a "load" terminal which responds to the AGEN* (address generation) signal transmitted from microprocessor 16 of Figure 1. Upon receipt of the AGEN* signal, the registered counter 66 transmits the block size data value held in its register to a NAND gate 70. The second input to NAND gate 70 is a DCLK signal which is the system MEMORY clock signal. Thus, NAND gate 70 triggers the shift register 58 to engage in shifts a number of times equal to the data value held in the registered counter 66, when signal AGEN* is received. The output of the registered counter 66 also is a clock signal to the 32 bit counter block 74 as shown via flip-flop 78. The values held in shift register 58 are transferred to the counter 74 which then transmits them out as a address on an address bus 24 to the random access memory array 22 of Figure 1. Figure 3 is a detailed schematic of one embodiment of address generator 26. Latches U37, U38, U39 and U40 store the start logical block information received on lines EXT DB [0,...,8] as clocked in by signals on lines E [2,...,5]. (Hence the start logical block number can be up to 32 bits = 8 bits x 4.) Immediately after, the microprocessor 16 (not shown) negates signal AGEN* input to inverter U114B and then flip-flop U41A to begin the address generation cycle. The address generation circuit includes also cascaded 4 bit shift registers U18, U19, U20, U21, U22, U23 and U24 which provide the basis for a 28 bit "hardware" (dedicated logic) multiplier circuit. In this schematic the exemplary associated SSD is of 2 gigabytes storage capacity using 4 MB DRAM chips in the memory array. The memory array is 16 modules each containing 128 megabytes, thus 2 gigabytes total. Thus a 28 bit address bus is adequate; however, as DRAM chip density increases, the maximum memory array capacity and hence address bus may grow, e.g. to 32 bits. One address generator is provided for each module. The address data from the latches U37,...,U40 is loaded into the shift register string U18,...,U24. Then every clock signal supplied to the shift registers U18,...,U24 on their CLK terminals multiplies the address data by two. Thus for large block sizes the shift register-multiplier U18,...,U24 will be clocked proportionally more times than for small block sizes. The number of shift register clock signals is controlled by registered counter U44, which conventionally consists of an 8 bit register connected to a presettable 8 bit counter. The register is programmed on power up of the SSD with the appropriate multiplication factor on bus EXT DB [0,...,8] for E=5. Signal lines E0 thru E15 are enables for various components in the microprocessor 16 external memory map. The microprocessor 16 can read and/or write these locations across the system address bus (SAB) . When signal AGEN* is set low by the microprocessor 16 of the SSD, the contents of the register part of U44 are loaded into the counter part of U44 because the CLOAD line (connected to the output terminal of flip-flop U41A) has gone low. This causes "ripple carry" to go high on the output terminal RCO of counter U44, and this signal propagates via flip-flop U42A through to the NAND gate U25B. This allows signal DCLK (provided to the second input terminal of NAND gate U25B) through NAND gate 25B, to clock the shift register string U18,...,U24. Each DCLK signal thus multiplies the address data by two. The clock signal DCLK is e.g. a 16MHZ clock source; thus each multiplication by two is accomplished in 62.5 nanoseconds. This multiplication process continues until the internal counter of counter U44 "rolls over" and sets its output signal ripple carry RCO low. This low signal propagates through flip-flop U42A and stops the clock signal to the shift register-multiplier U18,...,U24. Finally this low signal propagates through flip-flop U42B and loads the multiplied address data (i.e., the start address) into the counter string consisting of counters U6, U7, U8, U9, U10 and Ull by clocking each of these counters. The 24 bit output signal of counters U6,...,U11 are provided to the memory array as the starting address for reading or writing this particular logical block. (Only 24 address bits are needed in this particular embodiment.) Output buffers Ul, U2, U3 in turn drive resistor blocks RP1, RP2, RP3 which drive address lines ALO,..., AL10, AHO,..., AH10 and BSO, BS1. Buffers Ul, U2, and U3 are required to drive the address lines on as many as 16 memory modules. Counter U5 drives demultiplexer U15. The outputs of demultiplexer U15 are the module select lines that select any one of the 16 memory modules. OR gates U45A and U45B are part of the address decoding for location E7 of the microprocessor 16 external memory map. Reading location E7 allows the microprocessor 16 to determine which memory module is currently selected. This is accomplished through external buffer U25. Writing to location E7 increments counter U5. This selects the next memory module. Input buffer U43 increases the drive capacity of the CMOS microcontroller 16. Counter U36 and comparator U17 are part of a circuit that controls the switch from one memory module to the next. When a module switch is requested, the microprocessor 16 reads the current module number. If the module is not the last, then microprocessor 16 increments counter U5. If it is the last module, then the command is terminated with an overrange error condition. Signal lines WR and RD carry the strobe signals from the microprocessor 16 that respectively read and write data to various other components. SCRUB is a signal line that allows the memory array 22 to correct memory errors during the refresh cycles. Lines DATA/REF ADR (data refresh address) and RFRQ (refresh request) carry signals that enable the address generator to support 4 MB DRAM chips in DRAM memory array 22. Counter U122 counts the signals on line RFRQ and then supplies the count to multiplexer U92, the selection signal for which is supplied on line DATA/REF ADR; when the signal on DATA/REF ADR is low, refreshing is taking place. The multiplication factor (logical block size value) is adjusted due to the nature of the registered counter U44 used in this circuit. As previously mentioned, the registered counter U44 is an 8 bit device. This implies a count range from 0 to 255 with terminal carry at count 255. Each clock signal of the shift register is a multiply by two, so that one clock =2x, two clocks =4x, three clocks =8x etc. The correct preset value for the register part of register-counter U44 is therefore 255 minus the desired number of clocks. Naively, it would seem that the desired multiplication factor would be directly the logical block size. Under these conditions, because 512 equals 2 9 , the correct value for the register would be 255-9 = 246. This is correct if the memory array produces an output that is only one byte wide. However solid state disks can be implemented with a memory array that is considerably wider if single byte resolution is not necessary. An exemplary solid state disk has a memory bus that is eight bytes wide. Eight equals 2 3 , and therefore the correct block size value factor for this system would be 255-9+3=249, assuming a 512 byte logical block. This is implemented by a lookup table in the microprocessor 16. The multiplier is the required number of clocks to be presented to the shift register, i.e., the multiplication factor. The circuit stops the multiplication process at rollover, thus the "register value" = 255 - multiplier. The "register value" is the actual value supplied to registered counter U44. Logical Block Size Multiplier Register Value 256 5 250 512 6 249 1024 7 248 2048 8 247 4096 9 246 A computer program resident in microprocessor 16 in the SSD is shown in the following appendix; relevant portions of the program that control address generation are at line 390 and following showing the registered counter 390 being programmed; line 878 and following showing a real routine with AGEN at line 960; and at line 1031 and following showing a write routine with AGEN at line 1100. The program is in the 8051 assembly code language. This computer program is copyrighted; the copyright owner gives permission for facsimile reproduction of this material, but reserves all other copyright rights. It is to be understood that the present invention, in addition to being compatible with the SCSI interface, is also compatible with other computer bus peripheral interfaces such as IPI or DSSI or similar interfaces that are block specific. More generally, the present invention is applicable to any interface for computer systems which address memory using a logical block number and a block size, and in particular where the block size is of varying (programmable) length. The above description is illustrative and not limiting; further modifications will be apparent in light of this disclosure and are intended to be covered by the appended claims. APPENDIX 4 ALLPUBLIC 5 RBCO, 1 ,2,3) 6 7 8 ******************** 9 EXTERNAL SYMBOLS 10 ******************** 11 12 EXTERN XLAT, INQ DAT, PAGE_0, BLK DES 13 EXTERN PAGE 1, PAGE 2, PAGE_3, PAGE 4 14 EXTERN PAGE~38, CAPJJAT, RD DAT, ZER0_BLK 15 EXTERN SIFT7 UA_SNS DAT, VIR E2, INSERB 16 EXTERN BACKUP, MSG HDL, RD SW, STICKER 17 EXTERN PB CLR, LEDS, PB SET, IRQ1, IRQO 18 EXTERN EN~INT1, GRN LED~ON,GRN LED OFF 19 EXTERN DEAL_W PBS, NOT RDY SNS7 URT PRO_SNS 20 EXTERN DAT ERR SNS, COPY MODE, REC ERR SNS 21 EXTERN READ EXT, WRITE EXT, COPY FRE2,~NO SNS 22 EXTERN EN_PBI, RLY CLOSE, DIAGS,~FILL RAM- 23 EXTERN SHOWR, SAV_LED OFF, RES LED OFF 24 EXTERN SSAV, SRES, INHD, PRNT_ACC ~ 25 ******************************************************* 26 MISCELLANEOUS EQUATES 27 ******************************************************* 28 =0002 29 CHEC COND ; ARIOUS =0018 30 RSVD~ ;STATUS =0008 31 BUSY ;CODES =0010 32 ISTAT 33 =0020 34 LBAO •LOW ORDER ADDRESS =0030 35 LBA1 =0040 36 LBA2 =0050 37 LBA3 •HIGH ORDER ADDRESS =0060 38 REGISTER COUNTER =0060 39 MUL 40 -******************************************************************** 41 MICROPROCESSOR PORT ASSIGNMENTS 42 .******************************************************************** 43 =0090# 44 DDBEA =0091# 45 RDGATE =0092* 46 WRGATE =0093# 47 DREQA =0094# 48 AGEN =0095# 49 DREQB =0096# 50 DDBEB =0097# 51 OVFL 52 =00A7# 53 E2 =00A6# 54 SRAM =00B4# 55 WR PRT 56 57 58 .A******************************************************************* 59 ; BIT SIZE RAM ASSIGNMENTS 60 •A******************************************************************* CSIBITS,CLASS=BIT,START=OOH,ABSOLUTE 10 CSIBITS BIT 0000 (0001) ;ILLEGAL REQUEST 15 0001 (0001) ;WRITE PROTECTED 0002 (0001) •ONLINE FLAG 0003 (0001) ■ SET WHEN UNIT ATTENTION EXISTS 0004 (0001) /GENERAL PROBLEM FLAG 0005 (0001) • SET WHEN RESERVED 20 0006 (0001) • SET FOR LINKED COMMAND 0007 (0001) ;SET FOR LINK W/FLAG 0008 (0001) ;SELECTED U/ATN 0009 (0001) ;USED TO BYPASS AGEN OOOA (0001) ;SET WHEN 128 BLOCKS LEFT 25 OOOB (0001) • MESSAGE INTERLOCK OOOC (0001) ■ SET WHEN BACKUP DRIVE IS READY OOOD (0001) • SET UHEN BACKUP IS THROUGH OOOE (0001) ;SET FOR RESTORE, FOR SAVE OOOF (0001) ;SET WHEN A PUSH BUTTON INTERRUPT 30 0010 (0001) ■ SET TO SEND CDB TO CRT 0011 (0001) -SET WHEN READ IS FROM RAM 0012 (0001) ■ SET WHEN IN DIAGNOSTIC MODE 0013 (0001) ■ SET FOR SCSI RESET 0014 (0001) ;DRIVE OPERATION IN PROGRESS 35 SCSIDATA,CLASS=DATA,START=30H,ABSOLUTE SCSIDATA 40 .******************************************************************** 92 BYTE SIZE RAM ASSIGNMENTS 93 94 .A******************************************************************* 45 95 96 0030 (0001) 97 FIFO SIZE 0031 (0001) 98 MSG SIZE 0032 (0001) 99 BUS _ ID_1 50 0033 (0001) 100 STATUS 0034 (0001) 101 RESVR 102 103 .A******************************************************************* 55 ' 104 ;THE FLAGS BYTE CONTAINS SEVERAL BIT LEVEL FLAGS 105 ;THEY ARE; 0 UNIT ATTENTION 106 ; 1 WRITE PROTECT 107 ; 2 RESERVED 108 ; 3 SYNCHRONOUS NEGOTIATION 60 109 ; 4 OFFLINE • WAS DB ABSOLUTE 163 164 SEG SCSICODE 165 166 167 ******************************************************* 10 168 POWER ON RESET VECTOR 169 170 171 =0000' 172 ORG RESET 15 173 0000020016' 174 JMP HARD NIT 175 ****************************************************** 176 EXTERNAL INTERRUPT 0 VECTOR 177 ****************************************************** 20 =0003' 178 ORG EXTIO 0003020000 179 JMP IRQO 180 181 182 ******************************************************* 25 183 EXTERNAL INTERRUPT 1 VECTOR 184 ******************************************************* 185 186 187 188 189 190 191 192 HARD INIT: • DIFFERENIATE FROM SCSI RST 193 ;CLEAR HARD RESET ONLY 194 .-SELECT REGISTER 195 • BANK NUMBER ZERO 196 • THESE TWO LINES ADDED 197 ■ FOR DEAD BUS DISK ACTION 198 199 200 201 202 203 • for 512 204 ;PROGRAM MULTIPLIER 205 •DETERMINE CARD COUNT 206 ;CHECK FOR POWER FAILURE 207 208 NHD -ALLOW DIAGNOSTICS 209 210 DO INHD: ;TEMPORARY NAIL 211 INΪT: 212 213 214 215 0049 D2 90 216 ;DDBE* 004B D2 91 217 ;READ GATE * 004D D2 92 218 ;WRITE GATE * 004 F D2 96 219 0051 D2 90 220 10 0053 C2 12 221 ;NECESSARY FOR SCSI ERROR 222 223 *************************************************************** 224 CLEAR SCRUBBING BIT 225 *************************************************************** 15 0055 7950 226 MOV R1,#LBA3 0057 E4 227 CLR A 0058 F3 228 MOVX S)R1,A 229 230 *************************************************************** 20 231 CLEAR SCSI CHIPS 232 *************************************************************** 233 0059 120000 234 BUI: CALL INSERB -CLEAR INTERRUPT FROM 005C 30 B3# FA' 235 JNB P3.3.BUI ;BACKUP PORT 25 236 237 *************************************************************** 238 CHECK TO SEE IF MAIN BUS IS HUNG 239 *************************************************************** 005F 7F OA 240 30 0061 120419' 241 STI: 006420 B2# 47' 242 0067 DF F8' 243 244 245 **************************** 35 246 ARRIVAL HERE MEANS BUS IS 247 PROBABLY HUNG 248 **************************** 249 00697908 250 40 006B 7440 251 ;DISABLE SCSI RESETS 006D F3 252 006E 120419' 253 ;CLEAR ONE LAST TIME 254 255 .**************************** 45 256 • NOW CHECK POWER FAIL FLAGS 257 .**************************** 258 0071 E5 53 259 MOV A.PFL FLG ;GET FLAGS 0073 B4 AA 2D' 260 CJNE A,#OAAH,RESTR ;CHECK IF FATAL OUTAGE 50 261 262 **************************** 263 THE SWITCH MONITOR ROUTINE 264 WATCHES FOR POWER OUT SIGNAL 265 AND CLEARING OF SCSI BUSS 55 266 **************************** 0076 C2 OF 267 SW MON: CLR PBI ;CLEAR FLAG 0078 120000 268 CALL PB CLR -FIRST CLEAR PB REGISTER 10 IW LOOP: 15 20 25 30 RESTR: 35 40 BUS UP: 45 50 55 60 OODD C207 322 CLR FLAG /AND FLAG BITS 00DF C2 11 323 CLR DATA READ /READ CONSTANTS 324 .********************************************************************* 325 ; THE FOLLOWING CODE SETS UP THE UNIT ATTENTION SENSE DATA 10 326 * ********************************************************************* 327 328 329 /MOV R7,#22 /LENGTH FOR SENSE DATA(S) 15 00E1 900000 330 MOV DPTR,#UA SNS DAT/POINT AT TABLE 331 /MOV R0,#SNS~DAT~ 332 ,-MSD: CLR A 333 zMOVC A,3A+DPTR 334 /MOV 3R0.A 20 335 /INC RO 336 /INC DPTR 337 /DJNZ R7.MSD 338 339 25 .********************************************************************* 340 THE NEXT STEP IS TO READ THE 1ST BYTE OF 341 THE E2PROM. IF THIS IS NOT ONE OR TWO, THE 342 DEFAULT MODE AND INQUIRY DATA WILL BE COPY 343 TO THE E2PROM 30 344 * ********************************************************************* 345 00E4904000 346 MOV DPTR,#4000H /LOCATION 0 FOR E2 347 35 00E7 E4 348 CLR A 00E8 EO 349 MOVX A,3DPTR /READ FIRST BYTE 350 351 352 40 353 00E9 B4 02 06' 354 CJNE A,#02,NT1 /COMPARE TO ONE 355 356 * ********************************************************************* 45 ' 357 / IF THE E2 PROM HAS VALID DATA, THEN IT WILL BE 358 / USED AS MODE SELECT DATA 359 * ********************************************************************* 360 50 OOEC 120000 361 CALL COPY FRE2 OOEF 0200F5' 362 JMP PGM CFG2 /DO NOT USE EPROM DATA 363 364 365 55 366 367 * ******************************************************************** 368 A ROUTINE IS ADDED AT THIS POINT TO COPY 369 DEFAULT MODE SELECT DATA TO THE E2 PROM 60 370 371 372 CURRENT MODE DATA IS COPIED FROM ROM TO RAM 373 374 65 * ******************************************************************** 375 00F2 120000 376 NT1: CALL COPY MODE 377 378 * ******************************************************************** 10 ' 379 / THE CONFIGURATION 2 REGISTER WILL BE PROGRAMMED 380 ; TO ENABLE THE HIGHEST ORDER TRANSFER COUNT ADDRESS 381 * ******************************************************************** 382 15 0 000FF55 7799 OOBB 3 38833 PGM CFG2: MOV R1,#0BH /CONFGURATION 2 00F77440 384 MOV A,#40H /SET BIT 6 00F9 F3 385 MOVX 3R1,A /PROGRAMM 386 387 20 OOFA 388 RD MDATA: 389 390 * ******************************************************************** 391 MODE SELECT DATA IS READ, AND THE NECESSARY 25 392 FLAGS SET. THE HARDWARE MULTIPLIER IS PROGRAMMED 393 AT THIS POINT. ALSO THE DMA TRANSFER SIZE WILL 394 BE PROGRAMMED HERE. SIZE = 1 SECTOR 395 MULTIPLIER CONSTANTS 396 248 = 1024 30 397 249 = 512 252 = 64 398 250 = 256 253 = 32 399 251 = 128 254 = 16 400 255 = 8 401 THE BLOCK SIZE IS STORED IN THE LAST TWO BYTES 35 402 OF THE BLOCK DESCRIPTER. THIS IS STORED IN EEPROM 403 AND CAN BE ALTERED UITH A MODE SELECT COMMAND. 404 * ******************************************************************** OOFA 7875 405 MOV R0,#PG_0+10 /POINT AT BLOCK SIZE MSB 40 OOFC E2 406 MOVX A,3R0 /READ TO ACCUMULATOR OOFD 60 16' 407 JZ LESS_THAN_256 /BRANCH IF <256 408 OOFF 7535" F8 409 MORE THAN 256: MOV CONSTANT,#248 /ASSUME 1024 0102 B4 04 03' 410 CJNE A,#04,TRY 512 /TEST FOR 1024 45 0105 02013B' 411 JMP PROGRAM_COUNTER /BRANCH IF EQUAL 412 010805 35 413 TRY 512: INC CONSTANT /BUMP CONSTANT 010A B40203' 414 CJNE A,#02,MUST BE_256/TEST FOR 512 010D 02013B' 415 JMP PROGRAM_COUNTER /BRANCH IF EQUAL 50 416 01100535 417 MUST BE 256: INC CONSTANT 011202013B' 418 JMP PROGRAM COUNTER 419 420 55 421 0115 7876 422 LESS THAN 256: MOV R0,#PG 0+11 /POINT AT BLOCK SIZE LSB 0117 E6 423 MOV A,3R0 " /READ TO ACCUMULATOR 011875 35" FB 424 MOV CONSTANT,#251 /ASSUME BLOCK SIZE=128 011B B48003' 425 CJNE A,#128,TRY_64 /TEST FOR 128 60 011E 02013B' 426 JMP PROGRAM COUNTER /BRANCH IF EQUAL 427 /BUMP MULTIPLIER /TEST FOR 64 TER /BRANCH IF EQUAL /BUMP MULTIPLIER 10 /TEST FOR 32 TER /BRANCH IF EQUAL /BUMP MULTIPLIER E 8 /PROGRAM FOR 8 15 TER /BRANCH IF EQUAL 20 /RETRIEVE CONSTANT _COUNTER /POINT AT COUNTER /PROGRAM VALUE IN A 25 450 ZERO ALL TRANSFER COUNTERS 451 TUO FOR 53C90 30 452 THREE FOR FAST201 453 * ********************************************************************* 01407900 454 MOV R1,#00H 0142 E4 455 CLR A 35 0143 F3 456 MOVX 3R1.A /TRANSFER COUNT LSB 457 01447901 458 MOV R1,#01H 01467402 459 MOV A,#02 0148 F3 460 MOVX 3R1.A /TRANSFER COUNT MID 40 461 014979 OE 462 MOV R1,#0EH /TRANSFER COUNT MSB 014B 7400 463 MOV A,#00 014D F3 464 MOVX 3R1.A 465 45 466 * ******************************************************************** 467 AT THIS POINT, THE CONFIG SWITCH IS READ TO DETERMINE 468 THE NUMBER OF CARDS PRESENT 469 50 * ******************************************************************** 470 /CALL RD SU 471 472 * ******************************************************************** 55 473 THE OPTION SELECT SWITCH IS READ AT THIS POINT 474 THE CONFIG #1 REGISTER IS PROGRAMMED FROM THIS DATA 475 THIS IS INTERNAL REGISTER #08 476 * ********************************************************************* 60 014E 477 RD OSS: 014E 78 FO 478 " MOV R0,#0F0H /CONFIG SWITCH 0150 E2 479 MOVX A.3R0 /READ SUITCH 0151 CO EO 480 PUSH ACC 0153 C210 481 /ASSUME NO CRT 015530 E3# 02' 482 /ACC.3=0 MEANS NO CRT 0158 D2 10 483 ;ACC.3=1 MEANS YES CRT 015A 54 07 484 NO CRT: /SAVE LAST THREE BITS 485 ,-SLOU CABLE BIT 10 015C 7808 486 /CONFIG #1 015E F2 487 /PROGRAM 53C90 015F DO E0 488 /TEMPORARY LOOP 489 490 * *********************************** 15 491 /SIZING ROUTINE FOR RAM CARDS 492 /AUTO SIZER ADDED FOR SGI 493 /CONVERTED TO SUBROUTINE 494 /LOCATED THIS MODULE 495 * *********************************** 20 496 /ASSUME NO CARDS 497 /REZERO UNIT 498 CARD LOOP: /SET TOTAL BLOCKS 499 /BUMP ONE FOR 32M OR 4 FOR 4MEG 25 500 /AND RESTORE 501 /NAIL AT 7 CARDS 502 /CLICK TO NEXT CARD 503 /SETTLE 504 /POINT AT SWITCH 30 505 /AND READ TO ACC 506 /LOOP IF CARD IS PRESENT 507 CALL RTZ /OTHERWISE RTZ 508 35 509 * ************************************ 510 ■ THIS ROUTINE SETS UP THE GEOMETRY 511 /TO BE PLACED IN THE MODE TABLE 512 /THIS ASSUMES THAT THE VALUE OF 513 /CARDS HAS BEEN SET DURING HARD INIT 40 514 * ************************************ 0161 E5 62 515 MOV A,CARDS /TOTAL CARDS 516 /SETB C /PREPARE TO MOVE CARRY INTO BIT 1 517 ,-RLC A /MULTIPLY AND ADD ONE 518 ;RL A 45 519 /ADD A,#01 520 0163 F570 521 MOV PG_0+5,A /SET TOTAL BLOCKS 522 523 ************************************* 50 524 ADD ROUTINE FOR MODE PARAMETER UPDATE 525 ************************************* 0165 E5 62 526 MOV A,CARDS 016778 A6 527 MOV R0,#PG 4+3 /POINT AT CYLINDER MSB 01697F 06 528 MOV R7,#06~ /SET FOR SHIFTING 55 016B 23 529 SHFT: RL A 016C DF FD' 530 DJNZ R7.SHFT 016E CO EO 531 PUSH ACC /SAVE JUMBLED MESS 0170 54 3F 532 ANL A,#00111111B /CHOP OFF REMMINENTS 0172 F6 533 MOV 3R0.A /AND SAVE IN PAGE 4 0173 DO EO 534 0175443F 535 017708 536 0178 F6 537 538 10 539 540 ********************************************************************* 541 / THE CLOCK CONVERSION FACTOR IS PROGRMMED TO A 542 / HARD WIRED VALUE BASE ON OSCILLATOR FREQ 15 543 ********************************************************************* 544 01797809 545 CLK CVR: MOV R0,#09H 017B 7405 546 MOV A,#05 /04 15-20MHZ 05 20-25MHZ 20 0170 F2 547 MOVX 3R0,A ;035-40MHZ 548 549 * ********************************************************************* 550 THE CONFIGURATION 3 REGISTER IS PROGRAMMED TO 25 551 ALLOW OPERATION WITH THE 40 MHZ OSCILLATOR 552 BITO = FAST CLOCK BIT1 = FAST SCSI 553 ********************************************************************* 554 30 017E 78 OC 555 CFG3: MOV R0,#0CH /POINT AT CONFIG 3 01807400 556 MOV A,#OO0O0O0OB /SET FAST CLOCK BIT NOT!! 0182 F2 557 MOVX 3R0,A /AND PROGRAM 558 559 35 * ********************************************************************* 560 AFTER THE FIRST DATA TRANSFER COMMAND 561 SYNCHRONOUS OFFSET PERIOD WILL BE SET 562 FOR OPENERS, ASYNCHRONOUS 563 40 ********************************************************************* 564 018374 00 565 MOV A,#00 0185 7807 566 MOV R0,#07H /SYNCHRONOUS OFFSET REGISTER 0187 F2 567 MOVX 3R0.A /ZERO SPECIFIES ASYNCHRONOUS 45 018875 54" 00 568 MOV SYNC OST,#00 /ADDED FOR 10 MBYTES/SEC 569 * ********************************************************************* 570 / TEMPORARY BRANCH TO THE DIAGNOSTIC ROUTINES 571 ; THAT ARE LOCATED IN MODULE SEVEN 50 572 * ********************************************************************* 573 574 /CALL DIAGS 575 55 576 * ********************************************************************* 577 / SET PUSH BUTTON LEDS AND ENABLE PB INTERRUPT 578 * ********************************************************************* 60 579 580 581 018B 74 FE 582 018D F5 65 583 65 018F 120000 584 585 586 * ********************************************************************* 587 BASED ON EN CRT FLAG, DECIDE WHETHER OR NOT TO 588 PLACE UNIT ONLINE, OR TRY DIAGNOSTICS 589 .********************************************************************* 019220 13# 08' 590 JB SC_RST,NO_DIAGS /AUTOMATICALLY PASS 10 DIAGNOSTICS 019530 10# 05' 591 0198 120000 592 /YES 019B C2 13 593 019D 120000 594 NO DIAGS: /ENABLE HARDWARE 15 01A0 120000 595 /ENABLE PUSH BUTTONS 01A3 120000 596 01A6 E5 53 597 /CHECK FOR POWER OUTAGE 01A8 B4 AA 1C 598 /LOAD RAM IF NECESSARY 01AB C2 OF 599 /CLEAR INTERRUPT FLAG 20 01AD 120000 600 ,-RENABLE PUSH BUTTONS 601 * ********************************************************************* 602 /IF A FATAL POWER OUTAGE HAS OCURRED, THE RAM ARRAY MUST BE WRITTEN 25 603 /WITH A KNOWN PATTERN. TYPICALLY THIS IS ALL ZEROS. 604 605 * ********************************************************************* 606 30 607 01B00201E5' 608 01B3 120000 609 LD RAM: /LIGHT BUSY LIGHT 01B6 120000 610 01B9 120000 611 NO LOAD: /OTHERWISE TURN OFF 35 BUSY LIGHT 612 01BC 79 AO 613 INT AT ERROR REGISTER 01BE E3 614 /DUMMY CLEAR 615 40 01BF 120000 616 /ENABLE PUSH BUTTONS 01C2 C2 OF 617 R PUSHBUTTON INTERRUPT 01C40201E5' 618 THEN ENABLE SELECTION 619 01C77803 620 DO RES: AIN PORT MUST BE ENABLED 45 01C97444 621 /SO THAT THE BUSY STATUS 01CB F2 622 /CAN BE RETURNED DURING SELECTION 01CC 75 53" AA 623 /ALLOWS RESET TO STOP SCSI RESTORE 50 01CF 120000 624 DISK TST: /LIGHT BUSY 01D2 D2 OE 625 01D4 120000 626 01D7 120000 627 /BUSY OFF 628 /ADDED FOR TEST 55 629 /ADDED FOR TEST 630 /ADDED FOR TEST 631 /ADDED FOR TEST 01DA 75 53" AA 632 /SET POWER FLAG WHEN RESTORED 60 01DD 12 0000 633 ;RENABLE PUSH BUTTONS 01E0 C2 OF 634 /CLEAR INTERRUPT FLAG 01E20201EE' 635 /BYPASS ENSEL AS THIS UAS DONE ALREADY 636 65 * ***************************************************************************** 637 /AT THIS POINT, THE DEVICE IS NOU ENABLED FOR SELECTION. THIS WILL BE A 638 /COMMON RETURN POINT AT THE END OF ANY COMMAND. 639 70 * ***************************************************************************** 10 15 20 25 30 35 40 * ************************************************************************ * 676 /THE PROGRAM WILL WAIT AT THIS POINT FOR SELECTION 677 45 /PBI UILL BE SET IF A /PUSH BUTTON HAS BEEN PRESSED EAD CONFIGURATION REGISTER 50 O THAT SCSI RESET CAN BE ISABLED DURING DISK OPERATION /SERVICE INTERRUPT /REREAD CONFIG REGISTER 55 60 5 693 694 * ************************************************************************ 695 /AT THIS POINT THE DEVICE HAS LIKELY BEEN SELECTED 696 /SIMPLE SELECTION WILL PROCEDE THRU TO THE 'SIFTING' PHASE. 10 697 /ALL OTHERS WILL BE REFERRED TO THE EXCEPTIONAL SERVICE REQUIRED tESR] 698 /THIS ROUTINE WILL MANAGE MESSAGE, ANY VARIOUS ERROR RECOVERY PHASES 699 -jc .************************************************************************ 700 701 702 02287805 703 ENS: 20 022A E2 704 705 706 707 708 25 * ************************************************************************ 709 / SEQUENCE STEP SHOULD BE MONITORED HERE 710 * ************************************************************************ 711 30 712 022B 20 E7# 3C 713 022E 20 E0# 51 ' 714 0231 20 E4# 05' 715 35 023420 E1# 4B' 716 ATTENTION 717 718 02370141 719 40 720 721 * ************************************************************************* 722 /THE ASP HAS DETECTED AN ATTENTION FROM THE INITIATOR 723 /THIS ROUTINE WILL RECIEVE THE MESSAGE AND TAKE APPROPRIATE 45 ACTION 50 55 60 65 5 746 * ************************************************************************ 0256 120456' 747 NO SCR: CALL GET CMD /PHASE CHANGE TO INDICATE 748 " /END OF MESSAGE PHASE 749 1 Q .************************************************************************ 750 / ADJUST FOR THE SELECTION ID AND MESSAGE BYTE 751 * ************************************************************************ 02597807 752 15 025B E2 753 025C 54 1F 754 755 756 /FLAGS REGISTER 757 20 025E FF 758 MOV R7,A /SET ADJUSTED LOOP COUNT 025F 2402 759 ADD A,#02 0261 F530 760 MOV FIFO SIZE,A 02637802 761 MOV R0,#02 /POINT AT FIFO 0265 793D 762 MOV R1,#CMD CODE /ADJUSTMENT 25 763 764 0267020290' 765 JMP RD PKT /PICKUP WHERE WE LEFT OFF 766 * ************************************************************************* 30 ' 767 /SOMEWHERE ON THE SCSI BUS AN INTERRUPT HAS BEEN GENERATED. PRESENTLY 768 /WE WAIT ONE SECOND AND THEN REENABLE SELECTION. WHILE THIS WORKS 769 /REASONABLY NOU, IT MAY NOT BE THE PROPER RESPONSE. 35 770 * ************************************************************************* 026A D2 13 026C 20 B2# 03' 026F 120419' 40 0272 20 14# 02' 0275 0141 776 027720 B2# 05' 777 NOINI: 45 027A 120419' 778 027D 80 F8' 779 027F 22 780 RST COM: 781 * ************************************************************************* 50 782 THE ATTENTION BIT IS SET INDICATING THAT THE INITIATOR HAS A MESSAGE 783 UAITING FOR THE CONTROLLER. THE MESSAGE PHASE UILL FOLLOU. THIS MAY 784 BE IDENTIFY, FOLLOWED BY A NORMAL COMMAND. 55 785 * ************************************************************************* 786 787 0280 D208 788 NO DLY: SETB SWATN /RETRIEVE MESSAGE 60 789 790 * ************************************************************************** 791 /AT THIS POINT THE ASP HAS BEEN SELECTED, AND IT IS TIME TO READ THE FIFO 65 792 * ************************************************************************** 793 02827807 794 STFWRD: MOV R0,#07H /FIRST READ THE 0284 E2 795 MOVX A.3R0 /NUMBER OF BYTES 70 0285 54 1F 796 ANL A,#1FH /FROM THE FIFO FLAGS REG. 0287 F530 797 MOV FIFO SIZE,A /ONLY 5 LSBS ARE VALID 798 10 15 20 25 30 35 40 45 50 55 60 * ************************************************************************* 02C2 90 0000 852 UR PRO ERR: 02C5 75 33" 02 853 02C8 12 04FA' 854 02CB 21 E5 855 856 10 02CD F7 857 SAV BYT: 02CE 09 858 02CF DF BF' 859 860 861 15 862 * ********************************************************************* 863 /THE FOLLOUING ROUTINE CHECKS THE LINK AND FLAG BITS 864 /THESE UILL NEED TO BE DEALT WITH LATER 865 20 * ********************************************************************* 866 02D1 70 03 ' 867 02D3 02 0000 868 02D6 13 869 EXEP: 25 02D7 92 06 870 02D9 13 871 02DA 92 07 872 02DC 02 0000 873 874 30 875 ***** 876 877 ***** 35 02DF 40 883 884 885 886 887 45 888 889 890 891 892 50 893 894 895 896 897 55 898 899 900 901 902 60 903 904 * ************************************************************************ 935 THE FOLLOWING CODE CHECKS THE FLAGS BYTE 936 BIT 0 = UNIT ATTENTION 40 937 * ************************************************************************ 938 0311 E536 MOV A,FLAGS 45 031360 1E' JZ DO_RD /PASS THRU IF NO FLAGS 0315 20 E0# 06' JB ACC.0,UAT /CHECK UNIT ATTENTION 031820 E4# OD' JB ACC.4,NOT_RDY /AND TEST READY FLAGS 031B 020333' JMP DO RD /(LATER TEST RESERVED) 031E 90 0000 MOV DPTR,#UA SNS DAT ,-POINT AT UNIT 50 ATTENTION 0321 C2 EO 946 CLR ACC.O ,-CLEAR FLAGS 0323 F536 947 MOV FLAGS,A zRESTORE FLAGS BYTE 032502032B' 948 JMP SCC /SEND CHECK CONDITION 0328900000 949 NOT RDY: MOV DPTR,#NOT_RDY SNS ;POINT AT ERROR 55 032B 75 33" 02 950 see? MOV STATUS,#02 ~ /SET CHECK CONDITION 032E 1204FA' 951 CALL CHK CND 0331 21E5 952 JMP EN SEL /ISSUE ERROR 953 * ************************************************************************ 60 954 ; ROUTINE FOR DEALING WITH STATUS FLAGS 955 * ************************************************************************ 0333 956 DO RD: /MOV R1,#00H 957 ~ /CLR A 958 /MOVX 3R1.A 959 0333 C294 960 CLR AGEN /MOVE HERE TEMPORARY 0335 7903 961 DO RD AGN: MOV R1,#03H /COMMAND REGISTER 033774 A2 962 MOV A,#0A2H /ISSUE SEND DMA COMMAND 10 0339 F3 963 MOVX 3R1,A 964 965 966 /CLR AGEN /PERFORM ADDRESS 033A C291 967 CLR RDGATE /GENERATION 15 033C D294 968 SETB AGEN /CYCLE 969 033E C290 970 CLR DDBEA /TURN DMA LOOSE 0340 120000 971 CALL GRN LED ON /LIGHT BUSY LIGHT 03437970 972 MOV R1,#70H " ;R1 SET FOR CARD BUMP 20 973 974 * ************************************************************************ 975 THE FC INTERRUPT MUST ALSO POLL THE 976 OVERFLOW FLAG. THE PROCESSOR WILL THEN 25 977 DECIDE IF THE CARDS SHOULD BE INCREMENTED 978 OR THE OVERRANGE ERROR SENT TO THE HOST 979 * ************************************************************************ 30 35 40 45 998 RD OK: 999 1000 50 1001 1002 1003 1004 1005 RD CMPLT: 55 1006 1007 1008 1009 JZ RD NO ERR /ZERO = NO ERROR 1010 10 15 20 25 30 35 40 45 50 * ****************************************************************************** 1055 ; THE FOLLOUING FIVE BYTES ARE 55 1056 ; NOT NEEDED FOR 256 BYTE TRANSFERS 1057 * ****************************************************************************** 03A85007' 1058 JNC LST_BYT /SPECIAL CONSIDERATION TO THE 03AA C2 OA 1059 CLR OTE 128 SECTOR CASE 60 03AC 79 OE 1060 MOV R1,#0EH TRANSFER COUNTER MSB 03AE 7401 1061 MOV A,#01 SET TO 128 SECTORS 03B0 F3 1062 MOVX 3R1.A 1063 03B1 E2 1064 LST_BYT: MOVX A.3R0 /GET LAST BYTE 03B2 60 06' 1065 JZ NO_FLG_LNK / I F NOT ZERO, THEN DO FLAGS 1066 1067 10 ' 1068 / ROUTINE FOR DEALING WITH FLAGS [SCSI] 1069 * ************************************************************************ 03B413 1070 RRC A 03B59206 1071 MOV LINK.C 15 03B713 1072 RRC A 03B89207 1073 MOV FLAG.C 1074 1075 * ************************************************************************ 20 ' 1076 ; THE FOLLOWING CODE CHECKS THE FLAGS BYTE 1077 * ************************************************************************ 25 30 35 40 45 50 55 60 03F97904 1117 03FB E3 1118 /READ STATUS BYTE 03FC 09 1119 03FD E3 1120 /READ INTERRUPT BYTE 03FE 20 E3# 0E' 1121 /BRANCH IF NOT FC 10 0401 020414' 1122 /ERROR ROUTINE 1123 0404300A# 08' 1124 WR_OK: INISHED IF OTE NOT SET 0407 C2 OA 1125 04097901 1126 / TRANSFER COUNT MSB 15 040B E4 1127 040C F3 1128 /SET FOR 128 SECTORS 040D 80 CF' 1129 1130 040F 12051D' 1131 WR CMPLT: 20 041221E5 1132 /TEMPORARY 1133 0414 12051D' 1134 WR EXEP: /TEMPORARY 041721E5 1135 1136 25 1137 1138 1139 1140 *************************************************************************** 30 1141 /THIS ROUTINE SERVICES THE INTERRUPT GENERATED BY THE 53C90 1142 /STATUS AND INTERRUPT REGISTERS MAY BE DISPLAYED 1143 *************************************************************************** 1144 35 /DISABLES SERIAL PORT 40 /SAVE 45 50 /CLEAR REMENENTS 55 60 10 15 20 25 30 1197 35 * ************************************************************************ 1198 FROM THIS POINT, THE PACKET MEMORY CAN 1199 BE EXAMINED. IF FLAGS BIT 3 IS SET, THEN 1200 THE INITIATOR STARTED THIS EXCHANGE AND 1201 UE OUE HIM A RESPONSE. IF FLAGS BIT 3 40 1202 IS CLEAR, THEN UE STARTED THIS EXCHANGE 1203 * ************************************************************************* 1204 1205 45 1206 043F 22 1207 RET 1208 0440784D 1209 NOT EXT MSG: MOV R0,#MSG PKT 0442 7C 01 1210 " MOV R4,#01 " 50 0444 1205AA' 1211 CALL TUBE 044722 1212 RET 1213 1214 * *************************************************************************** 55 1215 THIS ROUTINE READS A SINGLE MESSAGE BYTE 1216 THE MESSAGE BYTE IS RETURNED IN A 1217 THE INT REG UILL BE VAILD FOR THE COMMAND 1218 R1 AND A ARE DAMAGED. 1219 £ Q * *************************************************************************** 04487903 1220 GET MSG: MOV R1,#03H /COMMAND REGISTER 044A 7428 1221 ~ MOV A,#28H /GET MESSAGE 044C F3 1222 MOVX 3R1.A /COMMAND 5 044D 20 B2# FD' 1223 TUIDDLE: 04509119 1224 04527902 1225 0454 E3 1226 0455 22 1227 10 1228 1229 * *************************************************************************** 1230 / THIS CODE GENERATES THE COMMAND SEQUENCE. THIS IS NECESSARY 15 1231 / AFTER A MESSAGE FORM THE INITIATOR HAS INTERRUPTED THE 1232 / NORMAL FLOW OF PHASES. 1233 * *************************************************************************** 04567903 1234 GET CMD: MOV R1,#03H /COMMAND REGISTER 20 0458742B 1235 ~ MOV A,#2BH /RECEIVE COMMAND SEQUENCE 045A F3 1236 MOVX 3R1,A 045B 20 B2# FD' 1237 WEIGHT: JB P3.2,WEIGHT /WAIT FOR INTERRUPT 045E 9119 1238 CALL IN_SER 046022 1239 RET 25 1240 1241 * *************************************************************************** 1242 /THIS ROUTINE GIVES A 10 MSEC DELAY 1243 30 * *************************************************************************** 0461 7F 1E 1244 04637E FF 1245 0465 DE FE> 1246 0467 DF FA' 1247 35 046922 1248 1249 * *************************************************************************** 1250 /THIS ROUTINE GIVES A ONE SECOND DELAY. R7,R6,R5 ARE ZERO AT EXIT. 40 1251 * *************************************************************************** 1252 1253 046A 7F OD 1254 WAIT SEC: MOV R7,#13 ,-21 45 046C 7E FF 1255 L2: " MOV R6,#255 /255 046E 7D FF 1256 L1: MOV R5,#255 /100 0470 DD FE' 1257 LO: DJNZ R5,L0 0472 DE FA' 1258 DJNZ R6,L1 1259 /PUSH ACC 50 1260 /MOV A,R0 1261 /PUSH ACC 1262 /MOV A,R7 1263 /PUSH ACC 1264 /MOV TDPH.A 55 1265 ,-MOV R0,#TDPH 1266 /MOV R4,#01 1267 /CALL TUBE 1268 /POP ACC 1269 /MOV R7,A 60 1270 /POP ACC 1271 /MOV R0,A 1272 /POP ACC 0474 DF F6' 1273 DJNZ R7.L2 0476 22 1274 RET 65 1275 1276 1277 * ************************************************************************** 1278 THIS ROUTINE TRANSFERS 0-255 BYTES OF DATA 1279 DPTR HOLDS THE TABLE OFFSET 10 1280 R7 HOLDS THE NUMBER OF BYTES TO TRANSFER [MSB] . 1281 R6 HOLDS THE NUMBER OF BYTES TO TRANSFER [LSB] . 1282 * **************************************************************************** 1283 15 1284 0477 1285 DTR: 04771204EB' 1286 CALL FLUSH FIFO 1287 ,*OV A,CMD~CODE /CHECK IF THIS IS A 1288 ,*JNE A,#08H,UP RD /MICROPROCESSOR READ 20 047A 79 00 1289 MOV R1,#00H /TRANSFER COUNT LSB 047C EE 1290 MOV A,R6 047D F3 1291 MOVX 3R1.A 047E 09 1292 INC R1 /TRANSFER COUNT MID 047F EF 1293 MOV A,R7 25 0480 F3 1294 MOVX 3R1.A 0481 79 OE 1295 MOV R1,#0EH /TRANSFER COUNT HI 0483 E4 1296 CLR A /ASSUME ALWAYS ZERO 0484 F3 1297 MOVX 3R1.A 1298 30 04857903 1299 MOV R1,#03H 048774 A2 1300 MOV A,#0A2H ;ISSUE SEND DMA COMMAND 0489 F3 1301 MOVX 3R1.A 048A 79 12 1302 MOV R1,#12H /DMA REGISTER ADDRESS 1303 35 1304 1305 * ********************************************************************* 1306 /IF THIS IS NOT A RED (OR A READ EXTENDED) THEN DATA WILL COME FROM 40 1307 /THE MICROPROCESSOR. 1308 * ********************************************************************* 048C E53D 1309 MOV A,CMD CODE 048E B40803' 1310 CJNE A,#08H,UP RD 45 0491 0204AV 1311 JMP DR RD 1312 1313 0494 E4 1314 UP RD: CLR 1315 ~ /SETB P3.1 /SET HARDWARE FOR DMA MODE 50 1316 /DACK* NOW AT E2---1X 1317 1318 * ************************************************************************ 1319 /THE FOLLOWING ROUTINE SENDS DATA FROM THE MICROPROCESSOR 55 THROUGH 1320 /THE DMA PORT OF THE 53C90 1321 * ************************************************************************ 1322 60 1323 1324 0495 93 1325 NXT BYTE: MOVC A,3A+DPTR 0496 F3 1326 ~ MOVX 3R1.A 0497 A3 1327 INC DPTR 65 0498 E4 1328 CLR A 1329 0499 30 B2# 2E ' 1330 POL: JNB P3.2, RETURN 049C 20 93# F6' 1331 JB DREQA.NXT BYTE 049F 80 F8' 1332 JMP POL 1333 10 1334 ************************************************************************ 1335 /ARRIVAL AT THIS POINT MEANS THAT A MEMORY READ IS TO TAKE PLACE 1336 ************************************************************************ 15 20 25 30 35 40 45 50 55 60 5 04CB 1382 IDTR: 1383 04CB 1204EB' 1384 04CE 7900 1385 /TRANSFER COUNT LSB O4D0 EE 1386 10 04D1 F3 1387 04D209 1388 /TRANSFER COUNT MID 04D3 EF 1389 04D4 F3 1390 04D5 79 OE 1391 /TRANSFER COUNT HI 15 04D7 E4 1392 /ASSUME ZERO 04D8 F3 1393 1394 04D97903 1395 04DB 74 A2 1396 /ISSUE SEND DMA COMMAND 20 04DD F3 1397 04DE 79 12 1398 /DMA REGISTER ADDRESS 1399 1400 1401 5 * ************************************************************************ 1402 /THE FOLLOWING ROUTINE SENDS DATA FROM THE MICROPROCESSOR THROUGH 1403 /THE DMA PORT OF THE 53C90 1404 30 .************************************************************************ 1405 1406 1407 04E0 E6 1408 NXT BITE: MOV A,3R0 35 04E1 F3 1409 " MOVX 3R1,A 04E208 1410 INC RO 1411 04E330 B2# E4' 1412 PUL: JNB P3.2,RETURN 04E62093# F7' 1413 JB DREQA,NXT_BITE 40 04E980 F8' 1414 JMP PUL 1415 1416 1417 * *************************************************************************** 45 ' 1418 / THIS ROUTINE CLEARS THE FIFO 1419 / R1 AND A ARE MODIFYED 1420 * *************************************************************************** 1421 50 1422 04EB 1423 FLUSH FIFO: 1424 04EB 7903 1425 MOV R1,#03H 04ED 7401 1426 MOV A,#01H 55 04EF F3 1427 MOVX 3R1.A 04F022 1428 RET 1429 1430 * **************************************************************************** 60 ' 1431 /THIS ROUTINE SENDS PREVIOUSLY LOADED DATA FROM THE FIFO 1432 * **************************************************************************** 04F1 1433 SEND DATA: 04F1 7803 1434 MOV R0,#03H 10 15 20 25 30 35 40 45 1475 50 1476 1477 * **************************************************************************** 1478 /THIS ROUTINE LOADS GOOD STATUS AND COMMAND COMPLETE MESSAGE INTO FIFO 55 1479 /AND ISSUES THE TERMINATE COMMAND 1480 * **************************************************************************** 051D 78 03 051 F 74 01 60 0521 F2 0522 78 02 0524 74 00 0526 E4 1488 1489 1490 1491 1492 1493 1494 NO FLAG: 1495 1496 1497 1498 WAIT MD: 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 LCMDONE: 1509 1510 NO LINK: 1511 1512 1513 1514 1515 WAIT FC: 1516 1517 1518 1519 1520 1521 1522 1523 BMP ADD: 1524 1525 45 1526 1527 * *********************************** 1528 • SIZING ROUTINE FOR RAM CARDS 1529 /AUTO SIZER ADDED FOR SGI 1530 * *********************************** 50 056B 12058E' 1531 CNT CRDS: CALL RTZ 1532 /OV CARDS,#03 1533 ;ET 056E 7562" FF 1534 MOV CARDS,#0FFH /ASSUME NO CARDS 0571 12058E' 1535 CALL RTZ /REZERO UNIT 55 0574 E562 1536 CRD LP: MOV A,CARDS /SET TOTAL BLOCKS 05762404 1537 ADD A,#04 /BUMP ONE FOR 32M OR 4 FOR 4MEG 0578 F562 1538 MOV CARDS,A /AND RESTORE 1539 /MOV CARDS,#07 /NAIL AT 7 CARDS 057A B43F 03' 1540 CJNE A,#63,NOT FULL 5 057D 02 058A' 1541 0580 B167 1542 /CLICK TO NEXT CARD 05829161 1543 /SETTLE 0584 79 FO 1544 /POINT AT SWITCH 0586 E3 1545 /AND READ TO ACC 10 058730 E6# EA' 1546 LP /LOOP IF CARD IS PRESENT 058A 12058E' 1547 /OTHERUISE RTZ 058D 22 1548 1549 1550 15 1551 ************************************ 1552 RTZ SETS RAM ADDRESS TO 1553 LOCATION ZERO, CARD ZERO 1554 ************************************ 1555 20 058E E4 1556 RTZ: 058F 7920 1557 0591 F3 1558 05927930 1559 0594 F3 1560 25 0595 7940 1561 0597 F3 1562 05987950 1563 059A F3 1564 059B C294 1565 30 059D D294 1566 059F 22 1567 1568 1569 1570 35 * ******************************************************************** 1571 / ZERO ALL REGISTERS UITHIN A GIVEN BANK 1572 * ******************************************************************** 1573 40 1574 1575 1576 05A0 E4 1577 ZREGS: CLR A 05A1 F8 1578 MOV R0,A 45 05A2 F9 1579 MOV R1,A 05A3 FA 1580 MOV R2,A 05A4 FB 1581 MOV R3,A 05A5 FC 1582 MOV R4,A 05A6 FD 1583 MOV R5,A 50 05A7 FE 1584 MOV R6,A 05A8 FF 1585 MOV R7,A 05A922 1586 RET 1587 1588 55 1589 1590 , * ********************************************************************* 1591 /Routine for sending serial data to the tube. 1592 /R4 CARRYS THE LENGTH IN BYTES 60 1593 ,-RO POINTS TO THE FIRST BYTE 10/25/93 14:47:06 1594 -********************************************************************* 1595 1596 TUBE: 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 SCR LOOP: 1610 1611 1612 1613 1614 BUFF: 1615 1616 BRATE: 1617 1618 1619 1620 1621 1622 1623 BRAT: 1624 1625 1626 1627 SPC: 1628 1629 1630 1631 1632 1633 1634 1635 INBL: 1636 1637 1638 1639 1640 1641 INBH: 1642 1643 1644 CR: 1645 1646 LF: JNB TI.LF POP DPL POP DPH POP SCON CLR TI RET END No lines contained errors. No lines contained warnings.

Claims: CLAIMS We claim: 1. An address generator for a memory device, the address generator connecting to a computer peripheral bus and providing an address to a memory array, the address generator comprising: an input port connectable to the computer peripheral bus; a multiplier circuit operatively connected to the input port and receiving two multiplicands from the port, a first multiplicand being a block number and a second multiplicand being a block length value, the multiplier circuit providing a product of the two multiplicands; and an output port operatively connected to the multiplier and receiving the product, the output port being connected to the memory array. 2. The address generator of Claim 1, wherein the multiplier comprises: a plurality of latches receiving the first multiplicand; a plurality of shift registers connected to the latches and receiving the first multiplicand from the latches; a counter connected to the shift register and receiving an output from the shift registers, the counter being connected to the output port; and a registered counter receiving and holding the second multiplicand, wherein the second multiplicand held in the registered counter controls a number of shifts by the shift register. 3. The address generator of Claim 2, wherein the registered counter receives the second multiplicand only at a power up time of the address generator. 4. The address generator of Claim 2, wherein the second multiplicand held in the registered counter also controls the counter. 5. The address generator of Claim 1, wherein the computer peripheral bus is a SCSI bus. 6. The address generator of Claim 2, wherein the registered counter has a load terminal, and further comprising a line connected to the load terminal for receiving an address generation signal. 7. The address generator of Claim 6, wherein the counter has a load terminal for receiving the address generation signal. 8. The address generator of Claim 2, wherein the second multiplicand is a function of and not equal to a block length. 9. A method of generating an address for addressing a memory array, comprising: receiving from a computer bus interface port a block number and a block size value; providing a multiplier circuit; multiplying the block number by the block size value in the multiplier circuit; and providing the product of the step of multiplying from the multiplier circuit to the address array as an address.

Inventors: TUMA GEORGE B, TUMA WADE B, TUMA, GEORGE, B., TUMA, WADE, B.
Applicants: DISK EMULATION SYST INC, DISK EMULATION SYSTEMS, INC.
Application year: 1994
Main classification: G06F9
IPC codes: G06F3