Combined equaliser and demultiplexer

Abstract: A reduced speed equalizer is provided which receives signal samples at a first rate but performs the equalizing operation at a second, lower rate which is below the rate at which symbols are transmitted across the channel. The equalizer is clocked to receive samples in a shift register at the first rate. Samples stored in the shift register are clocked into a set of buffers at the second rate. The equalizer coefficients are applied to the samples stored in the buffer set to generate a sequence of equalized symbols at the second rate.

Description: Technical Field This invention relates to apparatus for receiving telecommunications signals and, more particularly, to an apparatus and method for equalizing received signals. Background of the Invention As information service providers offer more services through cable television, the demand for cable television bandwidth will greatly increase. Similarly, the introduction of high definition television (HDTV) channels, which require a significantly larger bandwidth than conventional television channels, will consume a large portion of the available cable television bandwidth. The number of cable television channels and bandwidth available, however, are limited. One technique for improving the bandwidth efficiency of a channel is to multiplex multiple data signals for transmission on a single channel. This technique permits a greater amount of data to be transmitted over the channel for a given time period, but requires a receiver apparatus capable of operating at the higher data rate. As the data rate increases, so does the receiver complexity and cost. Consumer products, such as cable television reception equipment, however, must be reasonably priced if those products are to be widely successful in the marketplace. EP-A-0423921 discloses apparatus as set out in the preamble of claim 1, carrying out, in use, a method as set out in the preamble of claim 7. The apparatus converts digital video signals between two digital signal formats (D1 and D2) and carries out a combined band pass filtering, interpolation and matrixing function, while converting between a 13.5 MHz data rate for the D1 format and a 14.318 MHz data rate for the D2 format. Summary of the Invention Apparatus and method according to the invention are set out in the independent claims. Preferred forms are set out in the dependent claims. An improved equalizer is provided which receives signal samples at a first rate but performs the equalizing operation at a second rate which is lower than the signaling rate (i.e., the rate at which symbols are transmitted across the channel). The equalizer is clocked to receive samples in a shift register at the first rate. Selected samples from the shift register are clocked into a set of buffers at the second rate. The equalizer coefficients are applied to the samples stored in the buffer set to generate a sequence of equalized symbols. Moreover, because the equalizer outputs symbols at the lower, second rate, the effect of bursty noise in the receiver is mitigated. In an exemplary embodiment of the invention, the equalizer is an element of a receiver designed to operate on a received signal that was generated by multiplexing data streams from several different video sources. The equalizer generates equalized symbols which correspond to selected ones of the different video sources. Received signal samples are clocked into the shift register of the equalizer at or above the signaling rate. Samples from the shift register are clocked into the buffer set (and are equalized) at the rate at which symbols are generated by the video source. This reduced speed operation greatly simplifies the complexity of the equalizer. Brief Description of the Drawings In the drawings: FIG. 1 is a block diagram of a transmitter suitable for use with the equalizer of the present invention; FIG. 2 is a block diagram of a receiver constructed in accordance with the principles of the present invention; FIG. 3 is a block diagram of an illustrative embodiment of the channel encoder of FIG. 1;. FIG. 4 is an illustrative two-dimensional constellation suitable for use with the transmitter of FIG. 1; FIG. 5 is a table for constructing and partitioning a four-dimensional constellation using the constellation of FIG. 4; FIG. 6 is a block diagram of the trellis encoder of the channel encoder of FIG. 3; FIG. 7 is a schematic diagram of the equalizer of FIG. 2, constructed in accordance with the principles of the invention; FIG. 8 is a block diagram of the channel decoder of FIG. 2; FIG. 9 is a table of modifications required for using the trellis encoder of FIG. 6 with constellations of various sizes; FIG. 10 is a block diagram of the precoder referred to in FIG. 9 showing the bits input to and output from the precoder; and FIG. 11 is a table showing the input and output values for implementing the precoder of FIG. 10. Detailed Description FIG. 1 shows a block diagram of the transmitter 100. Transmitter 100 includes a plurality of channel encoders 102, a symbol multiplexer 104, and a modulator 106. A separate channel encoder 102 is used for each different video program to be transmitted on the same cable channel 108. In the exemplary embodiment shown in the figure, transmitter 100 includes twelve such channel encoders, each of which receives a different video program. Each channel encoder receives data at a nominal bit rate of 3.25 Mbps (the actual bit rate will be slightly lower as a result of overhead such as framing symbols to be added to the transmitted signal) and outputs to symbol multiplexer 104 a sequence of symbols {P n (i) } at a nominal symbol rate of 448 Kbaud The term "symbol" herein refers to a signal point of a two dimensional (2D) QAM constellation. Symbol multiplexer 104 multiplexes the twelve sequences of symbols received from the twelve channel encoders 102 into a single output sequence of symbols {Q n } at a symbol rate of 5.38 Mbaud. Symbol multiplexer 104 performs the multiplexing operation on a symbol-by-symbol basis. (While symbol multiplexer 104 is described herein for convenience as operating to multiplex symbols, it is to be understood that the multiplexer may actually multiplex the bit groups that correspond to the symbols from the various channel encoders on a bit group-by-bit group basis.) That is, the multiplexer takes one symbol from the sequence of symbols {P n (1) } followed by a symbol from the sequence of symbols {P n (2) }, and so on through {P n (12) }, and then repeats the process again by taking a symbol from the sequence of symbols {P n (1) } Symbol multiplexer 104 inserts the appropriate framing symbols required to distinguish between the symbols of the different input sequences. Framing is performed in a conventional manner. The multiplexed output sequence of symbols {Q n } is provided to modulator 106. As further described below, multiplexing on a symbol-by-symbol basis mitigates the effect of bursty noise - which includes impulse noise - and greatly reduces the processing speed requirement in the receiver. Multiplexing on a symbol-by-symbol basis separates the symbols from a given video source i on channel 108 by eleven symbols (corresponding to the symbols from the other eleven video sources), thereby mitigating the effect of bursty noise in the receiver. The operation of symbol multiplexer 104 further enables receiver 200 to selectively operate on only one symbol in any given sequence of twelve symbols received from channel 108 to recover data bits from a given video program i . Thus, the receiver can operate at a fraction of the rate at which symbols are transmitted across channel 108 (also referred to herein as the "signaling rate"). In the embodiment of FIGs. 1 and 2, receiver 200 operates at 1/12 of the signaling rate. This advantageously reduces the complexity of the receiver. Modulator 106 modulates the output sequence of symbols into a 6 MHz signal. It is to be understood that modulator 106 includes conventional pulse shaping filters and other conventional elements required to generate an output signal. The output of modulator 106 is transmitted on a single 6 MHz cable channel. In a typical application, a separate transmitter/modulator are provided for each 6 MHz cable channel, with each transmitter multiplexing several (e.g., twelve) video programs onto its respective cable channel. Alternatively, modulator 106 can be configured to perform subcarrier modulation by modulating the sequence of symbols {Q n } received from symbol multiplexer 104 to a convenient intermediate frequency that can be combined with other intermediate frequencies in a conventional manner for transmission over a common carrier frequency. FIG. 2 shows a receiver 200 for receiving a single video program i from a 6 MHz signal that has been received on cable channel 108. Receiver 200 includes a demodulator 202, an equalizer 204, and a channel decoder 206. Demodulator 202 demodulates the received 6 MHz signal and performs the necessary filtering and A/D converting operations to produce a sequence of complex samples at a sampling rate of 10.76 MHz. Equalizer 204, as described in greater detail below, receives the samples from demodulator 202 and outputs a sequence of equalized symbols {P ∼ n (i) } at a rate of 448 Kbaud, in accordance with the principles of the invention. The output sequence of symbols from equalizer 204 corresponds to one of the twelve video programs that were multiplexed by symbol multiplexer 104 into the 6 MHz cable signal. Equalizer 204 determines from the framing symbols which accompany the data symbols which of the symbols output from demodulator 202 are to be equalized Channel decoder 206 (described below) decodes the sequence of symbols received from equalizer 204 to output a stream of data bits corresponding to the selected video program i . Returning again to the description of transmitter 100, FIG. 3 shows an exemplary embodiment of channel encoder 102. Channel encoder 102 includes a Reed-Solomon (RS) encoder 300, a byte interleaver 302, a trellis encoder 304, and a constellation mapper 306. RS encoder 300 and trellis encoder 304 respectively are the outer and inner codes which form a concatenated code. Byte interleaver 302 (and its corresponding deinterleaver in the receiver) further enhances the receiver capability to handle bursty noise that may come from the channel and the front end of the receiver. Although the invention is described herein in the context of a concatenated code, it is to be understood that other codes, such as a trellis or RS code alone, could be used without departing from the scope of the invention as defined by the appended claims. I have realized that an important criterion in designing a code for use in transmitting data across a cable television channel is to obtain maximum Gaussian noise immunity while providing some protection against impulse noise. I have discovered that a concatenated code, comprising a multidimensional trellis code (i.e., a 2N-dimensional trellis code where N is an integer greater than one) as the inner code together with a RS code as the outer code, where the amount of redundancy introduced by the Reed-Solomon encoder is no more than 0.375 bits per symbol of the constellation, provides superior performance over prior coding schemes. In a preferred embodiment, the amount of redundancy introduced by the outer Reed-Solomon code does not exceed that introduced by the inner trellis coded modulation. However, where the dimensionality of the trellis code makes it desirable to have an RS code that generates more redundancy bits than the trellis encoder, the RS code preferably introduces at most an average of 0.375 redundancy bits per symbol of the constellation. In a more preferred embodiment, the trellis code is a 4-dimensional (4D) code, and the RS code is at most a triple error-correcting RS code. That is, the RS code corrects no more than three RS symbol errors per RS codeword. I have found that double error-correcting and triple error-correcting RS codes provide the best performance. I have realized that using an RS code that is more than triple error-correcting as the outer code causes a reduction in bandwidth and power efficiency which cancels any gain that may be achieved by using a more powerful RS code. Although the concatenated code has been described above in the context of an RS code which corrects a predetermined number of errors, those skilled in the art will appreciate that the RS code alternatively could correct two erasures in place of each error the code could correct. For example, a double error-correcting RS code is capable of correcting two errors, one error and two erasures, or four erasures. RS encoder 300 illustratively is a RS(120,116) over a finite field GF(2 8 ) capable of correcting two RS symbol errors. Each RS symbol here consists of eight bits. RS encoder 300 receives data for a selected video program i at a nominal rate of 3.25 Mbps and outputs data at 3.36 Mbps to byte interleaver 302. The RS encoder receives a frame of 116 RS symbols and outputs a frame of 120 RS symbols, including the received 116 RS symbols plus four redundancy RS symbols. Each frame of 120 RS symbols is referred to as a "RS codeword." Byte interleaver 302 interleaves the RS symbols output from RS encoder 300. Byte interleaver 302 includes a buffer (not shown) having 30 rows by 120 columns of RS symbols. RS symbols output from RS encoder 300 are read into the buffer on a row-by-row basis and are read from the buffer on a column-by-column basis. Byte interleaver then converts the sequence of RS symbols read from the buffer into a stream of bits, which are output to trellis encoder 304. Trellis encoder 304 illustratively is a 4D 8-state trellis encoder which encodes the bits from byte interleaver 302 and outputs the trellis encoded bits to constellation mapper 306 to select a symbol from the constellation shown in FIG. 4. FIG. 4 shows a 2D 256-QAM constellation. As used herein, a QAM constellation is a multiple amplitude, multiple phase constellation which need not be a square constellation. The constellation preferably is chosen to have a circular shape to reduce the peak and average powers of the transmitted signal. The constellation has 90 degree phase symmetries. That is, the constellation is invariant to 90, 180, and 270 degree phase rotations. The constellation is partitioned into four 2D subsets, A, B, C, and D. A 2 16 -point 4D constellation is then formed by concatenating a pair of 2D 256-QAM constellations. The 4D constellation is partitioned into eight 4D subsets 0 through 7. Each 4D subset consists of two pairs of 2D subsets as shown in FIG. 5. For example, 4D subset 0 consists of 2D-subset-pairs (A,A) and (B,B). FIG. 6 shows trellis encoder 304 of FIG. 3 in greater detail. Trellis encoder 304 includes a mod-4 differential encoder 600, a rate-2/3 convolutional encoder 602, a 2D subset-pair selector 604, and a bit grouping means 606. Trellis encoder 304 receives fifteen input bits, I1 n through I15 n , collected over two signaling intervals, n and n+1. Two of the input bits, I3 n and I2 n are differentially encoded by differential encoder 600 to provide immunity to 90-, 180-, and 270-degree phase rotations of the constellation. Differential encoder 600 illustratively is a mod-4 adder whose present output bit pair I3 n 'I2 n ' is the mod-4 sum of the previous input pair I3 n-2 'I2 n-2 ' and the present input bit pair I3 n I2 n . One differentially-encoded bit, I2 n ', together with another input bit, I1 n , enters convolutional encoder 602, which generates three output bits, Y2 n , Y1 n , and Y0 n . Conceptually, these three bits are first used to select a 4D subset Y2 n Y1 n Y0 n from the 4D constellation The other differentially-encoded bit, I3 n ' (which is re-named as Y3 n ), is next used to select a 2D-subset-pair from the selected 4D subset. The remaining twelve uncoded input bits (I4 n through I15 n ) are then divided into two groups. Each group is used to select a symbol from a 2D subset of the selected 2D-subset-pair. In actual implementation, the above three-step selection process is done as follows. Referring to FIG. 6, the four bits output from the differential and convolutional encoders, Y3 n , Y2 n , Y1 n , and Y0 n , are first converted by 2D-subset-pair selector 604 into another four bits Z1 n , Z0 n , Z1 n+1 , and Z0 n+1 . The table of FIG. 5 shows the detail of this conversion. Bit grouping means 606 divides the four converted bits and the remaining twelve uncoded input bits into two groups, {Z7 m , Z6 m , ..., Z0 m } for m=n and n+1. In particular, bits I10 n through I15 n are renamed as Z2 n through Z7 n , respectively, and bits I4 n through I9 n are renamed as Z2 n+1 through Z7 n+1 , respectively. Each group is used by constellation mapper 306 (of FIG. 3) to select a symbol P m from the 2D 256-QAM constellation. (This group of bits is the bit group mentioned above with respect to symbol multiplexer 104.) The selection can be performed according to the bit mapping shown in FIG. 4. To simplify the drawing, FIG. 4 shows only the mapping from Z7 m Z6 m ...Z2 m to symbols in subset A. To perform the selection, the following rules are applied: (1) the bit patterns of Z1 m Z0 m that correspond to subsets A, B, C, and D are 00, 10, 01, and 11, respectively; and (2) any four symbols that can be obtained from each other through a 90-, 180-, or 270-degree phase rotation are assigned with the same bit pattern of Z7 m Z6 m ...Z2 m . In the above described embodiment, the 4D trellis encoder generates an average of 0.5 redundant bits per symbol of the constellation. The RS(120,116) encoder generates an average of 0.25 redundant bits per symbol of the constellation. One skilled in the art will appreciate that various modifications can be made to transmitter 100 without departing from the scope of the invention as defined by the appended claims. For example, channel encoders 102 of FIG. 1 have been described as each including a constellation mapper 306 dedicated to mapping encoded data bits generated by the respective channel encoder (see FIG. 3). However, a single constellation mapper could be shared by the twelve channel encoders 102. The single constellation mapper would be disposed at the output of the symbol multiplexer, and the symbol multiplexer would multiplex the bit groups corresponding to symbols from the different video sources, as discussed above. Having described transmitter 100, the details of receiver 200 will now be described In particular, the details of equalizer 204 and channel decoder 206 are described below. Equalizer 204 equalizes the channel distorted signal samples output from demodulator 202 (FIG. 2) to produce a sequence of equalized symbols {P ∼ n (i) }. In accordance with the invention, equalizer 204 receives samples from demodulator 202 at or above the symbol rate of 5.38 Mbaud, but performs the equalizing operation at a fraction of the symbol rate. This reduced speed operation greatly simplifies the complexity of equalizer 204. Because the equalizer outputs only symbols generated by one of channel encoders 102 (in this instance, one of twelve channel encoders), the effect of bursty noise from the channel is mitigated. FIG. 7 shows an exemplary embodiment of equalizer 204. Equalizer 204 includes a shift register 700 having several storage elements connected in series and being clocked at a first clock rate, and a buffer set 702 which is clocked at a second, slower clock rate. Each of the buffers (or registers) in buffer set 702 is coupled to the output of a respective storage element of shift register 700. The signal samples stored in buffer set 702 are output to a conventional equalizer means 704. Equalizer means 704 includes multipliers 706 and an adder 708 which operate to apply equalizer coefficients to the signal samples received from the buffer set 702 to produce an equalized symbol P ∼ n (i) at the second clock rate. One skilled in the art will appreciate that equalizer means 704 may include conventional circuitry (not shown) for updating the equalizer coefficients according to channel conditions (i.e., equalizer means 704 is an adaptive equalizer). In the embodiment of FIG. 7, the storage elements of shift register 700 are spaced by T/2 seconds, where T is the signaling interval (1/5.38 µsec). Shift register 700 receives from demodulator 202 complex samples at 10.76 MHz, which corresponds to twice the symbol rate of the transmitter (2 x 5.38 Mbaud). Buffer set 702 is clocked at a rate of 448 KHz to generate an output sequence of equalized symbols {P ∼ n (i) } at 448 Kbaud. The clock rate of shift register 700 is an integral multiple of the clock rate of buffer set 202. In this example, the clock rate of shift register 700 is 24 times the clock rate of buffer set 202. If a second video program j that is carried by the same 6 MHz cable channel is to be received simultaneously with the first video program i , (for example, to permit two television programs to be watched simultaneously on a single screen), a second buffer set (not shown) can be coupled to shift register 700 in parallel with buffer set 702. The second buffer set has the same structure and operates in the same manner as buffer set 702 to receive samples from shift register 700. The second buffer set also is clocked at 448 KHz, but with a different clock phase. The signal samples stored in the second buffer set are then equalized, with the same equalizer coefficients and equalizer means 704 that are used to equalize the samples from buffer set 702, to generate a second output sequence of equalized symbols {P ∼ n (j) } FIG. 8 shows channel decoder 206 in greater detail. Channel decoder 206 performs the inverse operation of channel encoder 102. In particular, the sequence of equalized symbols {P ∼ n (i) } received from equalizer 204 is first processed by a conventional Viterbi decoder 800. Viterbi decoder 800 outputs a stream of bits to a byte deinterleaver 802 which outputs RS symbols to an RS decoder 804. RS decoder 804 outputs a stream of data bits corresponding to the decoded video program i . An important design criterion for a good digital communication system is that the system can be modified easily to transmit different data rates for different channel conditions. The modem described herein allows transmission at different data rates by changing the size of the constellation of FIG. 4. FIG. 9 shows the modifications that are required to trellis encoder 304 of FIG. 6 to use the same concatenated coding structure for constellations of different sizes. FIG. 9 shows a table identifying constellations of different sizes and the number of input bits collected by the trellis encoder over two signaling intervals, and the modifications required to vary the constellation size (and hence the data rate). For those constellations whose size is a power of two, the modifications required are simply to set some of the input bits in FIG. 6 to zero. For example, when bits I9 n and I15 n are set to zero, the same coding structure shown in FIGs. 4-6 will produce a sequence of symbols from a 128-QAM constellation. This 128-QAM constellation is indicated on FIG. 4 by reference number 402. For those constellations shown in FIG. 9 whose size is not a power of two, the modifications required precoding selected bits and possibly setting other selected bits to zero. The precoder, which receives three input bits from byte interleaver 302 and outputs four bits to trellis encoder 304, is shown in FIGs. 10 and 11. For example, when bits I9 n and I15 n are set to zero and bits I7 n , I8 n , I13 n , and I14 n are precoded, the coding structure shown in FIGs. 4-6 will produce a sequence of symbols from a 96-QAM constellation. One skilled in the art will appreciate that other modifications can be made to the disclosed embodiments without departing from the scope of the invention as defined by the appended claims. For example, changes to the size of the QAM constellation can be made together with changes in the parameters of the byte interleaver and the RS code if desirable, but the byte interleaver and RS code parameters need not be changed. For example, in the case of a 128-QAM constellation, the RS code could be changed to RS(104,100) and the byte interleaver modified to include a buffer having 26 rows and 104 columns. However, a 128-QAM constellation will work with a RS(120,116) and a byte interleaver buffer of 30 rows and 120 columns. Moreover, constellation sizes other than those shown on FIG. 9 could be used, provided the appropriate changes are made to the constellation mapper. Although the coding schemes have been described in the context of cable television applications, one skilled in the art will appreciate that these coding schemes are equally applicable to over-the-air HDTV broadcasting and digital subscriber loop applications. Over-the-air HDTV applications may use a Reed-Solomon code which corrects a greater number of errors but which still adds no more than 0.375 redundancy bits per symbol of the constellation. Although QAM constellations are described herein, the principles of the invention also s.can be used with vestigial sideband (VSB) modulation. For VSB, the two coordinates of a symbol are transmitted in two separate signaling intervals. Symbol multiplexer 104 operates as a coordinate multiplexer which multiplexes the coordinates of the symbols in the sequence on a coordinate-by-coordinate basis.

Claims: Apparatus including a shift register (700) having a plurality of storage elements, the shift register receiving signal samples from a channel (202) at first clock rate, a plurality of registers (702), each of the plurality of registers (702) being coupled to a different one of the storage elements to receive and store signal samples at a second clock rate, and means for combining the signal samples stored in the plurality of registers to generate an output symbol, characterized in that the second clock rate is lower than a symbol rate at which symbols are transmitted over the channel and in that the combining means is adapted to generate an equalized output symbol, said apparatus being an equalizer. The apparatus of claim 1 further characterized by a second plurality of registers, each of the second plurality of registers being coupled to a different one of the storage elements to receive and store signal samples at the second clock rate, the clocking of the second plurality of registers being out of phase with the clocking of the plurality of registers; and means for equalizing the signal samples stored in the second plurality of registers to generate a second equalized output symbol. The apparatus of claim 1 further characterized in that the symbol rate is an integral multiple of the second clock rate. The apparatus of claim 1 further characterized in that the first clock rate is the same as the symbol rate. The apparatus of claim 1 further characterized in that the first clock rate is higher than the symbol rate. The apparatus of claim 1 further charcterized in that the equalizer is adaptive. A method of processing signal samples received from a channel, the method including the step of receiving a plurality of signal samples at a first clock rate in a shift register (700) having a plurality of storage elements, storing selected ones of the plurality of signal samples in a plurality of registers (702) at a second clock rate, each of the plurality of registers being coupled to a different one of the storage elements, and combining the signal samples in the plurality of registers to generate an output symbol, characterized in that the second clock rate is lower than a symbol rate at which symbols are transmitted on the channel (12) and in that the combining step is an equalizing step, generating an equalized output symbol. The method of claim 7 further characterized in that the symbol rate is an integral multiple of the second clock rate. The method of claim 7 further characterized in that the first clock rate is the same as the symbol rate. The method of claim 7 further characterized in that the first clock rate is higher than the symbol rate. The method of claim 7 further characterized in that the equalizing step is adaptive. The method of claim 7 further characterized by the steps of storing other selected ones of the plurality of signal samples in a second plurality of registers at the second clock rate, each of the second plurality of registers being coupled to a different one of the storage elements; and equalizing the signal samples stored in the second plurality of registers to generate a second equalized output symbol.

Inventors: WEI LEE-FANG, WEI, LEE-FANG
Applicants: AT & T CORP, AT&T CORP.
Application year: 1994
Main classification: H04L25
IPC codes: H03H15, H04L25, H03H21, H04N7, H03M13, H04J3, H04N5, H04L27, H04B3, H03H17