Transistor circuit

Abstract: A transistor circuit comprises a MOS transistor (N1) with an open back gate, and control means (11) for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.

Description: The present invention relates to a circuit including an MOS transistor and, more particularly, to control of the drain-source breakdown voltage of an MOS transistor. US-A-5 086 365 describes an electrostatic discharge protection circuit comprising an MOS transistor with an open back gate in which a parasitic bipolar transistor switches on to divert negative electrostatic discharge pulses to ground. It is generally known that as the collector-emitter voltage is applied to a bipolar transistor having an open base, avalanche breakdown occurs at a certain voltage, causing a large current to flow between the collector and emitter. This is because the dark current between the collector and emitter causes an electron avalanche in the base area. This is described, for example, on pages 231-233 in "Physics and Technology of Semiconductor Devices" (John Wiley and Sons, Inc. 1976) by A.S. Grove. Although the aforementioned mechanism for causing avalanche breakdown is known, the avalanche breakdown voltage depends on the manufacturing process of semiconductor devices, such as the impurity concentration of the base, and cannot be changed once the device manufacturing process is determined. Accordingly, it is an object of the present invention to provide a transistor circuit which can electrically control the avalanche breakdown voltage even after the manufacturing process of semi-conductor devices is determined. A transistor circuit according to this invention comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor. The present inventors discovered that the avalanche breakdown voltage of a parasitic bipolar transistor formed by the source, back gate (substrate) and drain of a MOS transistor is controllable by changing the gate voltage of this MOS transistor, and the present invention has been devised in view of this discovery. If the avalanche breakdown voltage is controllable, it is possible to prevent the avalanche breakdown of the parasitic bipolar transistor of the MOS transistor from occurring, permit the avalanche breakdown to occur at an early stage, or delay the occurrence of the avalanche breakdown as much as possible. This invention can therefore accomplish a promising transistor circuit which can be used in a variety of applications and is very advantageous. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a diagram showing a circuit for testing a transistor used in the present invention; FIG. 2 is a chart showing characteristic curves obtained by the testing circuit; FIG. 3 is a chart showing characteristic curves obtained by the testing circuit; FIG. 4 is a circuit diagram of one embodiment of this invention; FIG. 5 is a circuit diagram of another embodiment of this invention; FIG. 6 is a circuit diagram of a different embodiment of this invention; FIG. 7 is a circuit diagram of a further embodiment of this invention; FIG. 8 is a circuit diagram of a still further embodiment of this invention; and FIG. 9 is a cross-section view of a main portion of the circuit diagram shown in FIG. 5. Embodiments of the present invention will now be described referring to the accompanying drawings. The present inventors studies the avalanche breakdown voltage of a parasitic bipolar transistor constituted by the drain, back gate and source of a MOS transistor in a MOS-transistor based semiconductor circuit and discovered that if a voltage is applied between the drain and source of the transistor with its back gate (substrate) open and a gate voltage is further applied, the avalanche breakdown voltage of the parasitic bipolar transistor decreases. This discovery was made by the results of obtaining the characteristics of the drain-source voltage Vds v.s. the drain-source current Ids when Vgs = 0V, 0.2V, 0.3V or 0.4V is applied to the gate of an NMOS transistor N1 using the measuring circuit shown in FIG. 1 while setting the back gate (P well substrate in this case) in an open state, as shown in FIG. 1. The obtained Vds v.s. Ids characteristics are shown in FIG. 2. The characteristic curves in FIG. 2 include the temperature dependency (Ta = -40°C, 25°C, 85°C) as a parameter. A sample having a threshold voltage Vth = 0.6V, W/Leff = 630 µm/1.0 µm (W is the channel width and Leff is the effective channel length) was used as the NMOS transistor N1. In FIG. 1, B1 is an npn bipolar transistor, which parasitizes the NMOS transistor 1 and is constituted by the drain, back gate and source thereof. From the characteristic curves in FIG. 2, it is understood that the current Ids rapidly increases from a certain gate potential Vgs. In the test, the current limit was 10 µA to prevent the device from breaking by the flow of such a huge current. It is however apparent from the sharp rise of the characteristic curves that avalanche breakdown has occurred. It is apparent from the characteristic curves that with the gate-source voltage Vgs = 0V, the avalanche breakdown voltage of the parasitic bipolar transistor itself is observed whereas when Vgs > 0V, the breakdown voltage becomes lower. FIG. 3 shows the characteristic curves of the breakdown voltage v.s. the gate potential as obtained from the characteristic curves in FIG. 2. The possible reason why the avalanche breakdown has occurred at a low gate voltage as shown in FIGS. 2 and 3 is that the application of a positive gate voltage to the gate of the transistor N1 changes the energy band mode of the semiconductor surface directly under the gate and the charge distribution, and the sub threshold current flows directly below the gate, triggering the avalanche breakdown. The above is the description given on an NMOS transistor. With regard to a PMOS transistor, the breakdown voltage is controllable as in the case of the NMOS transistor by setting the gate potential lower than the source potential. FIG. 4 is a circuit diagram of one embodiment of the present invention as adapted for a signal limiter. In this example, the NMOS transistor N1 has a source connected to the ground potential (V SS ), a drain connected to a signal line 12 (e.g., the output line) and an open back gate (base of a parasitic bipolar transistor (not shown) constituted by the drain, back gate and source of the NMOS transistor N1), and a control signal is applied to the gate (control gate). The output of a D/A (Digital-to-Analog) converter 11 is connected as the control signal to this control gate to digitally control the gate potential. For example, if 0.4V is applied as the output of the D/A converter 11, a voltage exceeding 4.3V is applied to the drain, causing avalanche breakdown, so that this circuit has a limit potential of 4.3V. The D/A converter 11 may be replaced with some bias generator or the like. By changing the digital input of the D/A converter 11 to alter its analog output, the gate-source voltage Vgs is changed to permit the drain-source breakdown voltage to be controllable as shown in FIG. 3. The circuit in FIG. 4 can therefore serve as a Zener diode which has a breakdown-voltage changing function. Even if the manufacturing process for the transistor N1 is fixed, therefore, the transistor N1 can have the desired avalanche breakdown voltage by controlling the gate input voltage. That is, the manufacturing process for the transistor N1 need not be altered to change the breakdown voltage. FIG. 5 shows the case where the present invention is used in a protection circuit for the internal circuitry of a semiconductor device against the electrostatic discharge (ESD). In this example, the present invention is applied only to the V SS side. The NMOS transistor N1 has a source connected to the ground potential V SS , an open back gate (P well and the base of the parasitic bipolar transistor), and a gate connected to the base of an NPN transistor BP1. The collector of the NPN transistor BP1 is connected to the drain of the NMOS transistor N1. The base of the transistor BP1 is connected to the ground V SS via its own resistor component Rp (e.g., the resistor component up to the V SS -biasing portion of the P well). The drain of the transistor N1 is connected to an external terminal 21 of an integrated circuit which constitutes the present circuit, and further to the gate of a MOS transistor T5, an element in the internal circuit. In FIG. 5, when a positive surge voltage (greater than the supply voltage) is applied to the drain node of the transistor N1 through the external terminal 21, the current flows through the base of the transistor BP1 due to the breakdown of the PN junction diode between the collector and base of the transistor BP1. Consequently, the base potential rises above V SS by the resistor component R P of the base of the transistor BP1 itself, forward-biasing the base and emitter (e.g., to 0.6V or higher). As a result, the transistor BP1 is turned on, causing the positive surge to escape toward V SS . As the base potential has risen, the gate potential of the NMOS transistor N1 also rises. As described above, therefore, breakdown occurs at a voltage much lower than the avalanche breakdown voltage when the back gate of the transistor N1 is at the ground potential, causing this surge to escape toward V SS . In other words, the force to permit the escape of the surge is enhanced by the circuit which is provided the MOS transistor N1 in addition to the transistor BP1 as shown in FIG. 2, as compared with the circuit employing only the transistor BP1. When a negative surge is applied to the external terminal 21, the negative surge flows through the resistor component R P and the transistor BP1. This current becomes the base current of the transistor BP1, turning this transistor BP1 on. This increases the gate bias of the transistor N1, lowering the avalanche breakdown voltage. As a result, the negative surge escapes toward V SS by the enabled transistor BP1 and the avalanche breakdown of the transistor N1. The breakdown of the MOS transistor T5 in the internal circuit is prevented in this manner. FIG. 6 shows the case where the present invention is applied to the power supply V CC side as well as the V SS side. Even if V SS is open and only the supply voltage V CC is applied, a positive surge can be allowed to escape toward V CC . More specifically, when a transistor BP2 is turned on by the input positive surge, the gate potential of an NMOS transistor N2 rises and the avalanche breakdown voltage of the parasitic bipolar transistor of the transistor N2 drops, allowing the positive surge to escape toward V CC via the parasitic bipolar transistor the transistor BP2 and NMOS transistor N2. In FIG. 5, the bipolar transistor BP1 may be accomplished by arranging N diffusion layers on a P substrate (well). Similarly, in FIG. 6, the bipolar transistors BP1 and BP2 may be accomplished by arranging N diffusion layers on P substrates (wells). For example, the structure of the NMOS transistor N1 and the bipolar transistor BP1 in FIG. 5 is as shown in FIG. 9. As shown in FIG. 9, the embodiment shown in FIG. 5 requires a P well structure on an N substrate 31 since it is necessary to separate the P substrate (well) 32 in which the NMOS transistor N1 is formed and the P substrate (well) 33 in which the bipolar transistor BP1 is formed from each other. Substantially the same is true to the embodiment shown in FIG. 6, though not shown. The transistors BP1 and BP2 in FIGS. 5 and 6 may respectively be replaced with NMOS transistors N3 and N4 formed on a P well different from the P well of the NMOS transistors N1 and N2, as shown in FIGS. 7 and 8. The sources and drains of those MOS transistors N3 and N4 correspond to the emitters and collectors of the bipolar transistors BP1 and BP2 in FIGS. 5 and 6, and the back gate (substrate) corresponds to the base. The gates of the transistors N3 and N4 are connected to V SS to increase the breakdown voltages of the transistors, so that the transistors are set off. In this case, the interval between the source and drain can be made narrower than that in the case where the N diffusion layers of the source and drain are simply set close to each other on the P substrate as shown in FIGS. 5 and 6, i.e., the base length can be shortened. The surge escaping performance can therefore be improved. The present invention is not limited to the above-described embodiments, but may be embodied in various other applications. For example, although this invention is adapted for an NMOS transistor in the embodiments, this invention can also be adapted for a PMOS transistor in principle. According to the present invention, as described above, since the avalanche breakdown voltage of a MOS transistor is controllable, it is possible to prevent the avalanche breakdown of the MOS transistor from occurring, permit the avalanche breakdown to occur at an early stage, or delay the occurrence of the avalanche breakdown as much as possible. This widens the fields of the application of MOS transistors, and can accomplish a transistor circuit which is very advantageous. According to this invention, the avalanche breakdown between the drain and source of a MOS transistor with an open back gate is controllable so that the MOS transistor is permitted to function like a Zener diode having a breakdown-voltage changing function. By the utilization of this function, a lower breakdown voltage than the conventional one can be obtained so that a transistor circuit having a high electrostatic breakdown can be provided.

Claims: A transistor circuit comprising: an MOS transistor (N1) with an open back gate; and control means (11) for controlling a voltage to be applied to a control gate of said MOS transistor, whereby said control means controls an avalanche breakdown voltage of a parasitic bipolar transistor formed by a drain, said back gate and a source of said MOS transistor. A transistor circuit according to claim 1, wherein the channel passage of said MOS transistor (N1) has one end connected to a power supply electrode (V CC , V SS ), and the other end connected to a signal line. A transistor circuit according to claim 1 or 2, wherein said voltage to be applied to said control gate by said control means (11) is variable. A transistor circuit according to claim 1, wherein said control means (11) comprises: surge detecting means (BP1, R P ) connected to a control gate of said MOS transistor, for detecting a surge voltage and applying a voltage according to a result of detection of said surge voltage to said control gate of said MOS transistor. A transistor circuit according to claim 4, wherein said surge detecting means (BP1, R P ) comprises a bipolar transistor (BP1) and a resistor (R P ) between a base of said bipolar transistor and one of power supply electrodes (V CC , V SS ), one of a collector and emitter of said bipolar transistor and one end of a channel passage of said MOS transistor (N1) are connected at least to an external terminal (21) of an integrated circuit constituting said MOS transistor (N1) and said surge detecting means, and the other one of said collector and emitter of said bipolar transistor and the other end of said channel passage of said MOS transistor are connected to one of said power supply electrodes (V CC , V SS ). A transistor circuit according to claim 5 further comprising: a second MOS transistor (N2) with an open back gate; and second surge detecting means (BP2, R P2 ), connected to a control gate of said second MOS transistor, for detecting a surge voltage and applying a voltage according to a result of detection of said surge voltage to said control gate of said second MOS transistor, said second surge detecting means (BP2, R P2 ) including a second bipolar transistor (BP2) and a second resistor (R P2 ) between a base of said second bipolar transistor and one of power supply electrodes (V CC , V SS ), one of a collector and emitter of said second bipolar transistor and one end of a channel passage of said second MOS transistor (N2) being connected at least to an external terminal of said integrated circuit, and the other one of said collector and emitter of said second bipolar transistor and the other end of said channel passage of said second MOS transistor being connected to the other one of said power supply electrodes (V CC , V SS ), whereby each of said surge detecting means respectively controls avalanche breakdown voltages of a parasitic bipolar transistor formed by a drain, said back gate and source of the respective MOS transistor. A transistor circuit according to claim 5, wherein said surge detecting means (BP1, R) is constituted by a parasitic bipolar transistor of an MOS transistor, and said parasitic bipolar transistor is used as said bipolar transistor (BP1) of said surge detecting means. A transistor circuit according to claim 6, wherein each of said surge detecting means (BP1, R; BP2, R P2 ) is constituted by a respective parasitic bipolar transistor of an MOS transistor (N1, N2), and said parasitic bipolar transistors are respectively used as the first-mentioned and second bipolar transistors (BP1, BP2).

Inventors: KINUGASA MASANORI, SHIGEHARA HIROSHI, KINUGASA, MASANORI, SHIGEHARA, HIROSHI, KINUGASA, MASANORI, C/O INTELLECTUAL PROPERTY DIV., SHIGEHARA, HIROSHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H03K19
IPC codes: H01L29, H03K17, H03K19, H01L27