Design for testability technique of CMOS and BiCMOS ICs

Abstract: A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected BICSs avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional I DDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node ( shadow line ) and a supply rail of the IC.

Description: FIELD OF THE INVENTION The present invention relates to a new Design-For-Testability (DFT) technique aimed at detecting critical bridging faults, i.e. faults producing unacceptable extra delays in signal propagation, in CMOS and BiCMOS ICs. The invention overcomes the most important drawbacks of known DFT techniques based on built-in current sensors, by not requiring test devices in series with the functional blocks, thus minimizing the effects on circuit performance. Moreover it is capable of selectively detecting only faults that are really critical for the circuit operation, thus optimizing the margin for device rejection. BACKGROUND OF THE INVENTION As it is known, the testing of CMOS and BiCMOS ICs cannot be based on the assumption that all significant faults be represented by means of the conventional stuck-at model as discussed in A). In practice, a large portion of failures encountered in real circuits can be explained by the use of the so-called (resistive) bridging model as discussed in B) (herein considered to include also so-called stuck-on transistor faults), which implies the presence of a conductive path between power supply and ground. Such ( resistive ) bridging faults cause two main consequences: 1) the voltage at the output of a functional circuit (macro-gate or macro-cell) may assume "intermediate" values; 2) a static current, commonly denoted I DDQ , flows from the power supply to ground. As a result of the first effect, logic errors may or may not be produced according to whether or not the intermediate output voltages assumed by faulty (macro-)cells, lay on the same side of the logic threshold level of the fan-out gates, as in the correct situation as discussed in C). Hereinafter, bridging faults (BFs) that may give rise to logic errors will be denoted LBFs, while others bridging faults that will not cause logic errors will be denoted as NLBFs. In general, BFs must be detected, essentially because they inevitably degrade the circuit dynamic performance, while other effects, such as the extra power consumption associated with the I DDQ current, may be disregarded in many applications. While LBFs can be detected essentially in the same way as stuck-at faults, NLBFs require special detection techniques. To this end, the second effect, mentioned above, may be exploited by sensing the presence of a "non-negligible" I DDQ as discussed in , D) and E). Indeed, this possibility is interesting, because a test for the presence of a static current could reveal the existence of both LBFs and NLBFs. Moreover, I DDQ testing is potentially very effective and concise, because it merely requires fault activation (also for the detection of LBFs). In general, faults giving rise to measurable I DDQ can be detected with a set of test vector as discussed in F) much smaller tnan those of conventional ATPG algorithms. For these reasons I DDQ testing is attracting considerable interest, and, in conjunction with the trend toward increasing use of Design-For-Testability (DFT) techniques, significant efforts have been dedicated to the development of Built-In Current Sensors (BICss) as discussed in G) , H) , I) and J) to be normally exploited as a complement tool of standard, stuck - at -model-oriented test methods, which are still largely implemented in an off-chip mode. A major drawback of all BICSs developed so far, is that they feature extra-devices (MOSFETs, BJTs, resistances,...) in series with the functional circuit. The presence of such devices tends to degrade the dynamic performance of the functional circuit and it is necessary to realize these "extra-devices" with a considerably large area in order to minimize their negative effect. Above all, the use of series connected current sensors is incompatible with the trend toward scaled-down power supplies. There is a need or utility for an improved DFT technique for testing for the existence of critical resistive bridging faults in CMOS and BiCMOS ICs that does not cause the above noted drawbacks of the known methods employing BICSs. SUMMARY OF THE INVENTION These objectives are satisfied by the DFT system of the present invention, as defined in detail in the appended claims 1 and 7, which is based on monitoring the presence of intermediate voltages at signal nodes of CMOS or BiCMOS logic ICs, rather than anomalously high static currents. Advantageously, the monitoring may be focused on a pre-established range of intermediate voltages, thus rendering the novel system of the invention intrinsically selective , namely able to reveal the presence of only BFs of actual concern for the correct operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows two typical schemes of resistive bridging faults that may occur in logic gates; Figure 2 shows the typical increase of propagation delay D' along a circuit path due to the presence of the type of faulty logic circuit depicted in Fig. 1 or another type of faults logic, as a function of the value of the bridging resistance R, here equivalently represented by a measured I DDQ ; Figure 3 shows the increase of propagation delay D' along a circuit path due to the presence of a faulty logic circuit, in function of intermediate output voltage assumed for the two examples of faulty gate of the preceding figures; Figure 4 is a schematic diagram of a DFT architecture of the invention; Figure 5 is a schematic diagram of a clocked-mode embodiment of a DFT architecture of the invention. Figure 6 shows an embodiment of the invention in a DFT arrangement for detecting bridging faults and also stuck-at faults in buffers. GENERAL DESCRIPTION OF THE INVENTION As pointed out before, the least tolerable effect of BFs is the degradation of the dynamic performance of the circuit. In turn, fault-induced extra delays unambiguously reveal the existence of BFs, namely of faults that produce a delay in excess of a certain maximum (t DMAX ) tolerable delay, along a critical signal path. A crucial point that has been recognized is that it is not possible to establish a reliably solid relationship between fault induced extra delays and the level of a static current, because I DDQ depends on the actual resistance of the fault induced conductive path between a power supply rail and ground, while the increase of propagation delay depends mainly on a ratio between competing conductances (also because of the incomplete driving of the fan-out (macro-)gates). In other words, the I DDQ value is not a good indicator for delay-oriented faults detection. This can be clearly seen in the diagram of Fig. 2, wherein the relative increase of the propagation delay along a typical signal path comprising a faulty logic circuit and two additional levels of fan-out logic (in order to account for a degradation of performance of fan-out gates), as a function of I DDQ (made to vary by changing the value R of the relative bridging fault resistance), is shown for the two types of faults a) and b) schematically depicted in Fig. 1. As can be observed, the same value of I DDQ may produce substantially different extra delays, depending on the structure of the circuit. The situation depicted in Figures 1 to 3, is substantially independent of the actual structure of a logic (macro-)cell taken in consideration, as verified by a large number of electrical level simulations. On the other hand, as clearly depicted in Fig. 3, it has been found that a useful strong relationship exists between extra delays and the value of the intermediate voltage assumed by the output node of a (macro-)cell affected by a BF. The most dangerous, fault induced intermediate voltages are those close to the cell's logic threshold. Such faulty conditions cause the maximum current diversion to the output node capacitance and the minimum transistor overdrive in fan-out cells, without necessarily producing (static) logic errors . The new test approach of the present invention, based on the sensing of these intermediate voltages, has been found to minimize the number of circuits that are not unable to pass the conventional I DDQ test. Such a test, in fact, has proved to be far too grossly severe and therefore caused the rejection of components that would be able to operate correctly, though in the presence of relatively high static current levels. In addition, the detection of fault-induced intermediate voltages at (macro-)cells outputs can be done without any need to interrupt or affect their normal operation. For these reasons, the present invention can be outstandingly useful also for implementing on-line testing of devices (i.e. to implement self-checking procedures), and this aspect represents per se another significant advantage compared with alternative prior art test methods. The method of the present invention can be implemented in a static mode as well as in a clocked one, as will be illustrated later and in either embodiment it may be implemented with a variety of possible design options. An essential feature of the DFT architecture of the present invention is the presence of at least an auxiliary (or shadow) supply line (AUX-LINE), beside the normal supply rails V DD and GND (ground) that power the functional logic (macro-)cells of the integrated circuit. Such a shadow supply line AUX-LINE may be "connected" through a load to either one of the two supply rails, to V DD or to GND, of the functional CMOS or BiCMOS (macro-)cells of the IC, indifferently. In the embodiments shown in the Figures 4 and 5, for purely illustrative purposes, the shadow supply line AUX-LINE is shown connected through a load (LOAD) to the V DD line, however it is clear that the DFT architecture of the invention may equally be realized by connecting the shadow line through a load to the other supply rail that is to ground. Another feature of the DFT scheme of the invention, is the realization of a test inverter for each (macro-)cell to be monitored. Each test inverter stage is electrically connected to a shadow supply rail AUX-LINE and to the other of the two supply rails of the functional CMOS or BiCMOS (macro-)cells of the IC and has an input connected to an output node of the monitored CMOS or BiCMOS (macro-)cell. Each test inverter stage monitors the intermediate voltage that is assumed by the output node of a respective gate or (macro-)cell, by providing a conductive path between the shadow supply line and the "other" supply rail of the circuit when the voltage assumed by the output node of the monitored cell has an intermediate level, falling within a pre-established intermediate voltage range that can be determined by appropriately designing the test inverter, that is the n-channel and p-channel transistors that compose the inverter stage. It is evident that each test inverter may be designed so as to define certain triggering levels that may be designed so as to be "safely" close to the logic threshold level of the cell being monitored by the inverter, thus implementing an accurately selective testing of the IC's (macro-)cells. In this way, the number of failures (rejects) can be narrowed to only those devices denouncing the existence of truly critical resistive bridging faults . Of course, an IC may have a large number of (macro-)cells monitored by a DFT structure as the one shown in Fig. 4, that will produce a cumulative test signal across the load impedance (for example a resistance) connecting the shadow supply line AUX-LINE to the supply rail of the functional circuits (V DD in the example shown). Of course, the DFT test arrangement depicted in Fig. 4, may also be repeated any number of times over the whole chip. In such a case of a "distributed" embodiment, a plurality of test signals, respectively produced across the load of each of a plurality of shadow supply lines, may be summed together in order to produce a single logic output that can be interpreted according to an appropriate algorhythm by a dedicated circuitry. According to a specific embodiment of the invention, logic circuits featuring at least two signal nodes that should always be in the same logic state may be tested also for the existence of stuck-at faults, by modifying the test scheme of the invention, as will be described later. STATIC IMPLEMENTATION A simplest, static, implementation of the invention, features a resistive load (LOAD) that may be realized typically with a simple transistor, in series with either the power supply line V DD (as shown in Fig. 4) or ground. This simple scheme, employing a resistive load toward the power supply line V DD , of Fig. 4, will now be discussed in some details, since other, functionally equivalent, alternative embodiments may be easily derived from this by a skilled person. The basic operation of such a static scheme is very simple. The presence of an intermediate voltage at the output of a monitored (macro-)cell, falling within a certain intermediate voltage range, will "open" a conductive path between the relative shadow supply (AUX-LINE) and ground, through the respective test inverter. Under these conditions, a static current will flow through the load, causing the voltage at the test node to drop. Such a voltage drop, can then be easily read by a suitable circuit, in order to produce a standard logic value at the output of the test circuitry. As already stressed, the method of the invention, does not require any element in series with the functional circuit, whose performance is therefore minimally affected by an increase in load impedance. When a plurality of test signals, readable on distinct test nodes, each relating to one of a plurality of DFT networks, as the one depicted in Fig. 4, are produced within the same IC, these test signals may be collected at the inputs of a network implementing a NOR (NAND) function, so as to produce a single logic output. In general, this arrangement will simplify the electrical design of the scheme (because it would lead to a more balanced inverter/load trade-off ratio), but it could also significantly complicate the layout of signal and power distribution on the chip. Therefore, for simplicity and convenience, reference will be made to the case of a single shadow line-single load per chip. DESIGN CONSIDERATIONS As far as the realization of the test inverters is concerned, a starting parameter for their design is the range of intermediate voltage to be detected. In principle, the design range of critical intermediate voltages will be determined by fixing the maximum tolerable extra delay. The minimum value of detectable current on the load, that will depend on the sensitivity of output circuitry of the test scheme, is the other design parameter to be kept in consideration. Once these parameters are fixed, the test inverters can be easily designed, by compensating also the presence of the load in order to maximize their static current for an input voltage equal to the logic threshold voltage of the functional (macro-)cell to be monitored. The resistive load that connects the shadow line to one or the other of the two supply rails, can be realized in various ways; typically a p- or an n-channel MOSFETs in series with the power supply or ground, respectively, will represent a satisfactory load. As far as the "overhead" layout is concerned, it is undoubtedly true that the necessity to realize a shadow supply line or a plurality of such shadow lines represents a burden. However, it should be recognized that such a shadow line may be rather resistive (because its resistivity can be considered to a large extent as a part of the resistive load). Therefore such a shadow line may be as narrow as allowed by the available patterning technology. Moreover, in view of the fact that it can simply run parallel to the "main" supply line, it can be realized as a parallel metal strip having a width that is a small fraction of the width of the main supply line, without significantly complicating the layout (routing). Once defined the maximum acceptable increase in rise/fall propagation delays of eventually faulty signal paths, a voltage threshold can be determined by referring to diagrams as that shown in Fig. 3. For example for a 5V IC, to a limit additional delay larger than 50% of the nominal propagation delay, could correspond an intermediate voltage threshold range comprised between 3.25V and 1.75V, if a symmetric gate design is assumed. In a situation as the one represented by the schemes and the diagrams of Figures 1 to 3, and by adopting a symmetric design of test inverters, the minimum current flowing through an inverter driven by a faulty gate output node could be approximately equal to 110 µA, which may correspond to about 40% of the current that would flow through the test inverter when the test inverter is on its logic threshold. CLOCKED IMPLEMENTATION The invention can also be readily implemented without employing a resistive load for connecting the shadow supply line, by employing a capacitor or exploiting the parasitic capacitance at the shadow power supply, according to a dynamic scheme, featuring a reset operation. This alternative embodiment is shown in Fig. 5. Again, for simplicity, the case of a single sensing circuit, instead of a "distribution" of a plurality of test circuits, is considered. Referring to the circuit diagram of Fig. 5, the capacitor C may be represented by the parasitic capacitance of the shadow supply line AUX-LINE. At the beginning of each clock period (CK), the test node is reset to V DD , that is the capacitor C is discharged, by turning on the transistor T R . Successively, when all transients in the functional circuit have decayed, T R is switched off. In this condition, if no critical intermediate voltage is present at a (macro-)cell output, the test node remains at a high voltage (of course, for a limited time, as in all dynamic circuits). If, instead, fault-induced intermediate voltages open conductive paths (through one or more test inverters connected to the shadow supply line), the test node rapidly discharges to ground potential and an error signal can be produced. In this case, given the range of intermediate signal voltages to be detected (recognized as faulty) and the clock period, the design of the test inverters can proceed as follows. The intermediate voltage to be detected specifies the transistor's overdrive of the test inverters, thus the current through such inverters can be fixed by considering the actual value of the capacitance C, to ensure a sufficiently fast discharging of the test node in the available fraction of the clock period. This clocked scheme has the advantage of producing a negligible power consumption during a test phase (because it does not produce static currents). Moreover, by turning off the transistor T R , during normal IC operation, the test inverters will not contribute to the dynamic power dissipation either. However, a clocked scheme may be slightly more complex and may require a somewhat larger silicon area (particularly in a version featuring a "distributed" test scheme with a number of distinct capacitances). BRIDGING AND STUCK-AT FAULTS DETECTION A modified embodiment of the invention is illustrated in Fig. 6. The particular application described in Fig. 6 relates to an efficient DFT testing scheme for revealing bridging faults and also stuck-at (and of course also transistor stuck-open) faults within buffers or in any other circuit featuring two nodes that should always have an identical logic value, under fault-free (LBF-free) conditions. In practice the scheme is able to reveal any fault that could result in any logic error. A three-stage buffer that may be composed of three cascaded inverters is considered, as an example. According to the present invention, the "monitoring" inverters SA, SB and SC have their respective inputs connected to the output nodes of the three cascaded inverters of the functional logic circuit. The monitoring or sensing inverters SA, SB and SC are electrically connected to the supply rail V DD and to a shadow supply rail AUX-LINE, which is connected to the ground rail through a load. The modification of the test scheme that is introduced for revealing also stuck-at 0/1 faults on the signal nodes A, B and C, is represented by the connection between the outputs of the first (SA) and of the last (SC) monitoring inverter, which functionally should be sensing signals of the same logic value. Also in this modified embodiment, the test scheme remains capable to detect intermediate voltages that would cause untolerable extra delays in signal propagation through the chain of inverters that form the buffer. Moreover, stuck-at 0/1 faults are revealed as follows. By assuming: IN=0 and the signal node B stuck-at 1, the values of B and C will differ from the values of a fault-free situation. In particular, A will be at a logic 1 value, while C will be at 0 instead of 1. Hence, the n-channel transistor of SA will be ON while the value of C maintains (incorrectly) ON a p-channel transistor of SC. Current may flow from V DD to ground through the path formed by the pull-down and the pull-up devices of SA and SC, respectively, thus revealing the stuck-at fault.

Claims: A method of assessing the existence of critical resistive bridging faults in CMOS or BiCMOS logic ICs, characterized by sensing when the voltage present on at least a signal node of the IC assumes a value comprised between a preset intermediate voltage range. A method as defined in claim 1, wherein the sensing is performed by means of a test inverter driven by said signal node and functionally connected to a supply rail though a load. A method according to claim 2, wherein said test inverter is designed in a manner to determine said preset intermediate voltage range. A method as defined in any of the preceding claims 1, 2 and 3, characterized by deriving a test signal across said load. A method according to claim 4, wherein said load is a resistive load. A method according to claim 4, wherein said load is replaced by a capacitor functioning in a clocked (or dynamic) manner. A circuit for testing for the existence of critical resistive bridging faults in CMOS and BiCMOS ICs, characterized by comprising at least a shadow supply rail (AUX-LINE) connected through a load (load) to one of two power supply rails (VDD, GND) of functional CMOS or BiCMOS circuits of the IC; at least a test inverter stage, electrically connected to said shadow supply rail (AUX-LINE) and to the other of said two supply rails (VDD, GND) of functional CMOS or BiCMOS circuits and having an input connected to an output (A,B,C) node of a respective CMOS or BiCMOS circuit to be tested of the IC. A circuit as defined in claim 7, wherein said load is a resistance. A circuit as defined in claim 7, wherein said load is virtually implemented by a capacitor (C) according to a clocked (CK) implementation of the system. A circuit as defined in claim 7, characterized by comprising at least two of said test inverters and a connection between output nodes of said two test inverters. A circuit as defined in claim 7, further comprising a circuit capable of sensing a signal across said load as an indication of the voltage present at the output node of a CMOS or BiCMOS gate being monitored of the IC, having a value sufficient to cause conduction through at least a monitoring test inverter stage. A circuit as defined in claim 10, characterized by comprising a plurality of test circuits as defined in claim 11, and wherein a plurality of signals derived across a plurality of loads of as many test circuits, are input to a network implementing a combinative logic function to produce a single output logic signal, representing a result of the test performed on the IC.

Inventors: FAVALLI MICHELE, PENZA LUIGI, RICCO' BRUNO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G06F11
IPC codes: G01R31, H01L21