Current detection in power conversion

Abstract: Power is delivered from an input source to a load via a first capacitor in a series of energy transfer cycles, and a rate of change of voltage across the first capacitor is sensed as an indication of current flowing in the first capacitor.

Description: This invention relates to current detection in power conversion. Power supplies include current limiting circuits for several reasons, among them, to protect internal components of the power supply from excessive power dissipation, to protect the source from overload, and to prevent damaging currents from entering a user's wiring and load. In addition, zero current switching (ZCS) converters of the type described in U.S. Patent 4,415,959, must limit their output current for proper operation since there is a value of load current above which zero-crossing will not occur. One such ZCS converter 10, shown in Figure 1, has a leakage-inductance transformer 12 that transfers power from a primary 11 to a secondary winding 13. The power transfer occurs in a series of energy transfer cycles, where the switching frequency of switch 16 varies the amount of power delivered to the load 20. Various control schemes may be implemented to keep I choke at or below a maximum value. For example, a resistive shunt 30 may be placed in the serial path which carries I choke , as shown in Figure 3. The voltage across this resistor 30, V shunt , indicates I choke , and may be input to appropriate control circuitry to limit the value of I choke . In other schemes, the output current may be sensed magnetically (e.g., by means of a transformer with a suitable core reset circuit; by means of a Hall-effect device). EP-A-0 432 603 of ANT Nachrichtentechnik GmbH measures a current by utilizing a current transformer to provide a scaled replica of the combined current of two capacitors. The scaled replica is passed through a resistor to develop a voltage which is integrated by a diode, resistor, capacitor combination to produce a voltage representative of the peak value of the combined currents of the two capacitors. According to a first aspect of the invention, we provide apparatus comprising power conversion circuitry adapted operatively to deliver power from an input source to a load via a first capacitor in a series of energy transfer cycles, wherein said power conversion circuitry is operatively adapted such that during at least a portion of each of said energy transfer cycles, substantially all of the current delivered to said load is delivered by said first capacitor, and characterised in that said power conversion circuitry further comprises measurement circuitry adapted operatively to derive a measure of the rate of change of voltage across said first capacitor without making a measurement of current flowing in the first capacitor or in a resistive element in series with the first capacitor, and to deliver an output which is indicative of current flowing in the first capacitor. The features of the invention in its first aspect may be related to the features of specifically described embodiments as set out below, but without intending any restriction by the reference to specific reference signs: thus, we describe below apparatus comprising power conversion circuitry adapted operatively to deliver power from an input source to a load (20) via a first capacitor (C res - 26) in a series of energy transfer cycles, the power conversion circuitry being operatively adapted such that during at least a portion of each of said energy transfer cycles, substantially all of the current delivered to said load (20) is delivered by said first capacitor (26), and the said power conversion circuitry further comprising measurement circuitry (C sense - 60, R sense - 62) adapted operatively to derive a measure of the rate of change of voltage across said first capacitor (26) without making a measurement of current flowing in the first capacitor or in a resistive element in series with the first capacitor, and to deliver an output which is indicative of current flowing in the first capacitor (26). In accordance with a second aspect of the invention, there is provided power converter apparatus comprising: a first capacitor connected operatively to feed a load, a rate of change of voltage across said capacitor being indicative of current flowing in said first capacitor; and wherein substantially all of the current delivered to said load is delivered by said first capacitor during at least a portion of the time, the apparatus being characterised in further comprising measurement circuitry adapted operatively to derive a measure of said rate of change of voltage without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, and to deliver an output which is indicative of the current flowing in said first capacitor, and in that said measurement circuitry comprises a sense capacitor and a sense resistor in series, said sense capacitor having a capacitance which is less than half of the capacitance of said first capacitor, said series connected capacitor and resistor being connected in parallel with said first capacitor to share a portion of said current flowing in said first capacitor, the voltage across said sense resistor being an output indicative of the rate of change of voltage across said first capacitor, and said voltage across said sense resistor is indicative of said current delivered to said load. The features of the invention in its second aspect may be related to the features of specifically described embodiments as set out below, but without intending any restriction by the reference to specific reference signs: thus, we describe below embodiments of power converter apparatus comprising a first capacitor (C res - 26) connected operatively to feed a load (20), a rate of change of voltage across said capacitor (26) being indicative of current flowing in said first capacitor (26); the apparatus further comprising measurement circuitry (C sense - 60, R sense - 62) adapted operatively to derive a measure of said rate of change of voltage without making a measurement of current flowing in said first capacitor (26) or in a resistive element in series with said first capacitor, and to derive an output which is indicative of the current flowing in said first capacitor (26), and said measurement circuitry (60, 62) comprising a sense capacitor (60) and a sense resistor (62) in series, said sense capacitor (60) having a capacitance which is less than half of the capacitance of said first capacitor (26), said series connected capacitor (60) and resistor (62) being connected in parallel with said first capacitor (26) to share a portion of said current flowing in said first capacitor (26), a voltage across said sense resistor (62) being an output indicative of the rate of change of voltage across said first capacitor (26), substantially all of the current delivered to said load (20) being delivered by said first capacitor (26) during at least a portion of the time, and said voltage across said sense resistor (62) being indicative of said current delivered to said load (20). The invention provides, in a third alternative aspect thereof, a method for use in power conversion comprising delivering power from an input source to a load via a first capacitor in a series of energy transfer cycles, whereby said power conversion is effected such that during at least a portion of each of said energy transfer cycles, substantially all of the current delivered to said load is delivered by said first capacitor; and characterised in deriving a measure of rate of change of voltage across said first capacitor, without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, as an indication of current flowing in said first capacitor; said deriving a measure step comprising providing an indication of current flowing through measurement circuitry connected across said first capacitor, which current is proportional to said current flowing in said first capacitor. In preferred arrangements in accordance with this method: the measuring (sensing) is done in a sense capacitor which is connected in parallel with the first capacitor to carry a current which is proportional to the current flowing in the first capacitor. A sense resistor is connected in series with the sense capacitor and the voltage across the sense capacitor is provided as a sense output. The capacitance of the sense capacitor is less than half, preferably less than 1%, of the capacitance of the first capacitor. A current fed to the load is controlled in response to the sense output. Energy is transferred to the first capacitor by zero-current switching power conversion, in a succession of energy transfer cycles, each of the energy transfer cycles including a first time period during which energy is transferred from the first capacitor to the load. In practical embodiments we have shown that the sense circuitry may have only an insignificant effect on conversion efficiency. It can use economical, small circuit components in a simple configuration which can be implemented without the need for special manufacturing processes and without the packaging or thermal implications of lossy resistive elements. According to a further alternative aspect of this invention, we provide a method for limiting output current of a power converter, the method comprising producing a signal indicative of rate of change of voltage across a first capacitor through which substantially all the output current flows during at least a portion of the time without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, and using the signal to prevent the output current from exceeding a predetermined value (for example by using the signal in a feedback control loop). Other advantages and features will become apparent from the following description. In the drawings: Figure 1 is a circuit diagram of a zero-current switching power supply; Figure 2 shows waveforms found during an operating cycle of the converter of Figure 1; Figure 3 is a circuit diagram of a power converter which includes a resistive output current measuring device; Figure 4 is a circuit diagram of a zero-current switching power converter which includes an output current detection device; Figure 5 is a diagram of an equivalent circuit model for a zero-current switching converter; Figures 6 and 7 show operating waveforms for the converter and current detection circuitry of Figure 5; and Figure 8 is a circuit diagram of a zero-current switching converter which includes output voltage and output current control circuitry. In the known current detection scheme of Figure 3, a resistive element 30 senses the instantaneous value of I choke 25. V shunt = I choke *R shunt and both the instantaneous and average value of V shunt 6 are proportional to the respective values of I choke . Therefore, by use of appropriate signal processing circuitry, the voltage V shunt may then be used for: (1) detecting when either the average or instantaneous value of I choke exceeds some predetermined level, and (2) asserting some predetermined control strategy to control the output current to remain at or below some value. This "current-limiting" action is usually required in a power supply to protect either the power supply, or the load, or both, under fault or overload conditions. The scheme of Figure 3 is inherently lossy. While in theory it is possible to reduce this loss simply by reducing the value of R shunt , this is often not possible in practice. As R shunt is reduced, so too is V shunt ; and circuitry which can reliably detect very low values of voltage (e.g., below a few tens of millivolts) within the relatively noisy environment of a switching power supply may be complex, costly or unreliable. Thus, there is usually some minimum design value of V shunt , V min (e.g., V min = 50 mV), which is practical for use as a current-limit detection threshold. In a power converter designed to deliver P out Watts at an output voltage 18 equal to V out volts, the loss in the resistive element, P det , as a fraction of converter output power rating, can be shown to be: P det /P out = V min /V out . It is noteworthy that, for a fixed V min , the loss in the shunt increases as V out drops. With contemporary system voltages trending lower (e.g., to 3.3, 2, and 1 volt), this implies lowered system efficiency. For example, in a converter delivering 5 volts to a load at 300 Watts, with a V min threshold of 50 mV, the loss in the shunt is 1%, or 3 Watts. On the other hand, for a similar converter delivering 1 volt, the loss is 5%, or 15 Watts. In a zero-current switching converter, an efficient current measuring scheme takes advantage of the fact that, during a portion of the energy transfer cycle, I choke is exclusively supplied by capacitor 26. Thus, during an energy transfer cycle of the zero-current switching converter of Figure 1 the load 20 is assumed to be operated at a constant DC voltage, V out (e.g., the load may contain filter capacitors, not shown, which act to reduce time variations in V out to an essentially negligible amount). The value of the output inductor 28 is also assumed to be relatively large in comparison to the secondary-reflected value of the leakage inductance of the transformer 12, L 1 , so that under steady state load conditions the value of I choke may be considered to be essentially constant over a converter operating cycle. Waveforms during an energy transfer cycle of the zero-current switching converter of Figure 1 are illustrated in Figure 2. Just prior to time t=t 1 a value of current, I choke is flowing in the loop formed by the output inductor 28, the load 20, and the diode 24. The diode prevents charging of the capacitor 26, holding the value of the capacitor voltage, V res , at essentially zero. At time t=t 1 , switch 16 is closed. Between time t=t 1 and t=t 2 the secondary-reflected value of the input source voltage is effectively impressed across the secondary-reflected leakage inductance of the transformer 12 and current in the forward rectifier 22, I f , ramps up to a value equal to I choke as current in the diode 24 ramps down to zero. After time t=t 2 , the diode 24 ceases conduction and between time t=t 2 and t=t 3 energy is transferred from the input source to the capacitor 26 via the leakage inductance of the transformer 12. During this time period both the current in the forward rectifier 22 and the voltage across the capacitor 26, V res , vary sinusoidally during an energy transfer cycle having a characteristic time scale of pi*sqrt(L 1 *C res ), where C res is the value of capacitor 26. At time t=t 3 the current I f returns to zero and the switch is opened. Between t=t 3 and t=t 4 the entire current I choke flows in the capacitor 26, discharging the capacitor until the voltage across the capacitor is once again limited to zero volts by diode 24. Thus, during the time period between t=t 3 and t=t 4 (e.g., the "discharge period") the rate-of-change of voltage, dV res /dt, across capacitor 26 is directly proportional to the current I choke . Between times t=t 4 and t=t 5 the current I choke again flows in the loop formed by the output inductor 28, the load 20, and the diode 24. At time t=t 5 another cycle begins. As shown in Figure 4, the rate-of-change of V res may be measured by a capacitor 60 in series with a resistor 62, placed in parallel with capacitor 26. Capacitor 60 has a small capacitance C sense , compared to that of capacitor 26 C res , and the resistance of resistor 62, R sense , is small, so that the voltage, V comp 64, across resistor 62 is small compared to the voltage V res 68 across capacitor 26. In Figure 4, the sum of the currents, I res + I sense , flowing in the capacitors 26, 60 is equal to I choke during the time period t=t 3 to t=t 4 . If, during this discharge period, the instantaneous value of voltage across the sense resistor is small compared to the instantaneous value of V res , then the currents may closely approximated by: I choke = I sense + I res I sense = C sense (dV res /dt) I res = C res (dV res /dt). Combining the preceding three equations, and noting that the voltage across the sense resistor, V comp , is equal to: V comp = I sense *R sense results in the close approximation: V comp = R sense *(C sense /(C sense + C res ))*I choke . Thus the voltage V comp is proportional to I choke during the discharge period, the constant of proportionality depending on the absolute and relative values of R sense , C sense and C res . The circuit of Figure 4 therefore produces a voltage directly proportional to the output current, and, as will be shown below, it can do so without introducing significant energy loss provided the value of C sense is small with respect to the value of C res . Operation of the current detection scheme described above may be described with reference to the equivalent circuit model of a zero-current switching converter (Figure 5). The circuit includes an input voltage source 29 having a value of 15 Volts; a switch 16; an inductance, L 1 , of 15 nanohenries; a capacitor, C res , of value 1 microfarad; a diode 24 in parallel with C res ; a sense capacitor, C sense , of value 470 picofarads; and a sense resistor, R sense , of value 10 ohms. The voltage source 29 and leakage inductance 69 are representative either of discrete circuit elements used in a non-isolated converter or of secondary-reflected equivalent circuit values in an isolated converter using a leakage-inductance transformer. In the example, for purposes of illustration, the (normally relatively large) output inductor is replaced with a constant current source 70. In the waveforms of Figure 6 the value of the current source is 80 Amperes; in Figure 7 the value of the current source is 40 Amperes. In both Figures 6 and 7 the switch is turned on to initiate an energy transfer cycle and is turned off when the current I forward returns to zero. During the time period beginning when the switch is turned off and ending when the voltage V res declines (linearly) to zero (e.g., the discharge period), the voltage developed at the junction of C sense and R sense , V comp , is seen to be essentially constant. The values of V comp during this time period are, respectively, -376 millivolts and -188 millivolts, which values are equal to those predicted by Equation 4 for the indicated values of the circuit elements and current sources. In the examples given above, I choke was assumed to be essentially constant throughout an operating cycle. This assumption was made to simplify the illustration and description of the inventive concepts. However, the concept (of indicating the absolute value of a current, I choke , by measuring the rate-of-change of a capacitor voltage during a period of time during which the entire amount of the current flows in the capacitor) is generally applicable to the more typical case in which I choke will exhibit some time variations during the operating cycle (due to the finite value of the output inductor). In such cases the value of V comp will still accurately indicate the absolute value of I choke during the discharge period. The power dissipated in the current detection circuit of Figure 5 is less than 0.02 Watts at a converter output current of 80 Amperes, and this essentially negligible loss is achieved despite the fact that a relatively large current sense signal (e.g., close to -0.4 Volt) is generated. This may be compared to a conventional current sense circuit using a resistive shunt. Assume, for example, that it is desired to deliver 80 Amperes to a load at a load voltage of 2 Volts. To achieve a 0.4 Volt current sense signal would result in an unacceptably large shunt dissipation of 32 Watts. If a 50 millivolt current sense signal were used instead, the loss would still be 4 Watts. In either case, the conventional sense circuit will result in a substantial loss in the resistive sense element and a reduction in overall conversion efficiency. Our present current detection circuit, however, will have an insignificant effect on conversion efficiency and will achieve this result using economical, small, circuit components in a simple circuit configuration which can be implemented without the need for special manufacturing processes (e.g., soldering of shunts) and which have none of the packaging or thermal implications of lossy resistive elements. Additional control circuitry, shown included in the power converter 71 of Figure 8, may be used to control output current I out in response to V comp . Power converter 71 includes a zero-current switching power train 10 (of the kind shown in Figure 4) governed by a zero-current switching controller 72. The controller turns switch 16 on and off at times of zero current at an operating frequency indicated by the signal V f (which is delivered to the controller by voltage error amplifier 73). The converter 71 includes both an output voltage control loop and a current limit circuit 100. The output voltage control loop consists of a high gain error amplifier 73 which receives two inputs: a voltage value V set and an input from a voltage divider consisting of resistors 102, 104. The voltage V set is generated by current source 106 feeding reference voltage circuit 108. The reference voltage circuit 108 clamps the voltage V set at a predetermined value, V ref2 . The voltage divider output, V div , is a fraction of the converter output voltage V out . The error amplifier adjusts the signal V f so as to maintain the V div essentially equal to V get . In this way the output voltage control loop acts to adjust the converter operating frequency so as to maintain V out at an essentially constant value which is dependent upon V ref2 and the ratio of the voltage divider resistors. The signal V comp has the time varying behavior shown in Figures 6 and 7, where the negative excursion of the signal subsequent to the switch 16 turning off (referred to hereafter as V neg ) is indicative of the output current of the converter. This signal is delivered to current limit circuit 100. The high gain, high speed error amplifier 110 compares the signal V comp to a negative reference of value V ref1 111. If the instantaneous value of V comp is positive with respect to V ref1 , the amplifier 110 will attempt to source current, I D , toward capacitor 112 (and the junction of current source 106 and reference voltage clamp 108). This is prevented, however, by the polarity of the diode 114 connected in series with the output of the amplifier 110. Should V comp become negative with respect to V ref1 , however, the amplifier will be able to sink current through diode 114 and this will cause current to be shunted away from the reference clamp 108. As the absolute value of V neg increases above V ref1 (e.g., as the output current exceeds an output current limit value indicated by V ref1 ) the amplifier will withdraw charge from smoothing capacitor 112 during a portion of each operating cycle and current source 106 will sink charge into the capacitor 112 during the balance of the cycle. This will cause the voltage V set to be pulled below the clamp value V ref2 and result in a concomitant reduction in V out . Because of the high gain of amplifier 110, the amplifier 110 will withdraw sufficient charge from capacitor 112 during the portion of the operating cycle that V comp is more negative than V ref1 to ensure that V set assumes a value (which is below V ref2 and smoothed by capacitor 112) which is just sufficient to hold V neg essentially equal to V ref1 . Thus, if the load is increased, the current limit circuit 100 will act to adjust the converter output voltage to a value which prevents the converter output current from exceeding some predetermined value. For example, if the circuit elements in the power train 10 of Figure 8 were the same as those cited in the example discussed in conjunction with Figures 5, 6, and 7, then the value of V ref1 might be set to 390 or 400 millivolts as a means of current limiting the converter output to a value close to 80 Amperes. Other embodiments are feasible. For example, the current limiting circuitry may also be integrated with the control circuitry used to control the output voltage V out , e.g., the feedback loop including error amp 73. All, or part, of the circuitry may be embodied as an integrated circuit or hybrid device. The current limiting control circuitry might cause the output current to "fold back" as V out declines in an overload condition.

Claims: Apparatus comprising power conversion circuitry adapted operatively to deliver power from an input source to a load via a first capacitor in a series of energy transfer cycles, wherein said power conversion circuitry is operatively adapted such that during at least a portion of each of said energy transfer cycles, substantially all of the current delivered to said load is delivered by said first capacitor, and characterised in that said power conversion circuitry further comprises measurement circuitry adapted operatively to derive a measure of the rate of change of voltage across said first capacitor without making a measurement of current flowing in the first capacitor or in a resistive element in series with the first capacitor, and to deliver an output which is indicative of current flowing in the first capacitor. Apparatus according to Claim 1, further characterised in that said measurement circuitry is connected to carry a current which is proportional to the current flowing in said first capacitor. Apparatus according to Claim 1 or Claim 2, further characterised in that said measurement circuitry is connected in parallel with said first capacitor and comprises a sense capacitor. Apparatus according to Claim 3, further characterised in that said measurement circuitry comprises a sense resistor in series with said sense capacitor and in that said output comprises the voltage across said sense resistor. Apparatus according to Claim 4, further characterised in that said sense capacitor has a capacitance which is smaller than the capacitance of said first capacitor. Apparatus according to Claim 5, further characterised in that said sense capacitor has a capacitance which is less than half, preferably less than 1%, of the capacitance of said first capacitor. Apparatus according to any preceding claim, characterised in further comprising a controller adapted operatively to control a current fed to said load in response to said output of said measurement circuitry. Apparatus according to any preceding claim, further characterised in that each of said energy transfer cycles comprises a first time period during which energy is transferred to said first capacitor, and a second time period during which energy is transferred from said first capacitor to said load. Apparatus according to any preceding claim, further characterised in that said power conversion circuitry comprises a zero-current switching conversion circuitry. Power converter apparatus comprising: a first capacitor connected operatively to feed a load, a rate of change of voltage across said capacitor being indicative of current flowing in said first capacitor; and wherein substantially all of the current delivered to said load is delivered by said first capacitor during at least a portion of the time, the apparatus being characterised in further comprising measurement circuitry adapted operatively to derive a measure of said rate of change of voltage without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, and to deliver an output which is indicative of the current flowing in said first capacitor, and in that said measurement circuitry comprises a sense capacitor and a sense resistor in series, said sense capacitor having a capacitance which is less than half of the capacitance of said first capacitor, said series connected capacitor and resistor being connected in parallel with said first capacitor to share a portion of said current flowing in said first capacitor, the voltage across said sense resistor being an output indicative of the rate of change of voltage across said first capacitor, and said voltage across said sense resistor is indicative of said current delivered to said load. A method for use in power conversion comprising delivering power from an input source to a load via a first capacitor in a series of energy transfer cycles, whereby said power conversion is effected such that during at least a portion of each of said energy transfer cycles, substantially all of the current delivered to said load is delivered by said first capacitor; and characterised in deriving a measure of rate of change of voltage across said first capacitor, without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, as an indication of current flowing in said first capacitor; said deriving a measure step comprising providing an indication of current flowing through measurement circuitry connected across said first capacitor, which current is proportional to said current flowing in said first capacitor. A method according to Claim 11, further characterised in that said measurement circuitry connected across said first capacitor comprises a sense capacitor in series with a sense resistor. A method according to Claim 12, further characterised in that said step of providing an indication comprises detecting the voltage across said sense resistor as an indication of current in said first capacitor. A method according to any of Claims 11 to 13, further characterised in controlling a current fed to said load in response to said indication of said current flowing in said first capacitor and said load. A method according to any of Claims 11 to 14, further characterised in that each of said energy transfer cycles comprises a first time period during which energy is transferred to said first capacitor, and a second time period during which energy is transferred from said first capacitor to said load. A method for limiting output current of a power converter, the method comprising producing a signal indicative of rate of change of voltage across a first capacitor through which substantially all the output current flows during at least a portion of the time without making a measurement of current flowing in said first capacitor or in a resistive element in series with said first capacitor, and using the signal to prevent the output current from exceeding a predetermined value. A method according to Claim 16, further characterised in that said signal is delivered in a feedback control loop.

Inventors: VINCIARELLI PATRIZIO, VINCIARELLI, PATRIZIO
Applicants: VLT CORP, VLT CORPORATION
Application year: 1994
Main classification: H02M3
IPC codes: G01R19, H02M3, G05F1