Method for erasing a common mode current signal and transconductor assembly using such method

Abstract: The transconductor system in accordance with the present invention is the type comprising a first transconductor circuit (C1) having differential mode transconductance equal to a first value and common mode transconductance equal to a second value and is characterised in that it comprises a second transconductor circuit (C2) connected in parallel with said transconductor circuit (C1) having common mode transconductance substantially equal in modulus to said second value and of opposite sign. In this manner the common mode current signal at the output is greatly reduced.

Description: The present invention relates to a transconductor system in accordance with the preamble of claims 1. Differential circuits are rather widespread and well known is also the problem of common mode signals, in general undesired. A known example of a differential transconductor having differential inputs and outputs is shown in FIG. 1. It consists of a structure exhibiting two symmetrical branches both connected on one side to a terminal VCC having a fixed reference potential (usually the power supply positive) and on the other to a common node ND. The common node ND is connected to another terminal GND having fixed reference potential (often ground or the poser supply negative) through a current generator. In FIG. 1 said current generator is represented by means of its equivalent parallel circuit consisting of the parallel connection of an ideal current generator G2 and an output impedance Z of the current generator. One branch consists of the series connection of a current generator G11, a BJT transistor T11 and a MOS transistor M11 and the other of a generator G12, a BJT T12 and a MOS M12. The bases of the BJTs T11 and T12 are connected together with a terminal UT having fixed polarisation potential. The control gates of the MOS transistors M11 and M12 are connected respectively to a first input IP1 and a second input IM1. A first output OP1 is connected to the collector of the BJT transistor T11 and a second output OM1 is connected to the collector of the BJT T12. Such a circuit exhibits a good common mode rejection relationship especially at low frequency but a certain voltage drop on the current generator G2 which constitutes a problem for circuits operating at low supply voltage (3V, for example). For this reason structures have been proposed and are referred to below as "pseudo-differential", quite similar to the "full differential" ones such as that illustrated above but in which the terminal ND is directly connected to the fixed potential terminal GND like that illustrated in FIG. 2 and described in patent application GB-A-2 175 763. Said structures solve the problems linked to low supply voltage but have the serious disadvantage of exhibiting very high common mode gain (equal to the differential mode gain in the circuit of FIG. 2). Also known from the patent application No. GB-A-2 010 038 is a stabilised MOS transistor operational amplifier circuit, i.e. a trasconductor system, comprising a differential amplifier, in turn comprising an off-set voltage compensating circuit. The purpose of the present invention is to obviate the disadvantages of the known art. Said purpose is achieved by means of transconductor system having the characteristics set forth in claim 1 . Further advantageous aspects of the present invention are set forth in the dependent claims. Connecting in parallel to a first transconductor circuit having high common mode transconductance a second transconductor circuit having common mode transconductance substantially equal in modulus to that of the first circuit and of opposite sign the transconductor system thus achieved exhibits substantially null common mode transconductance. The two circuits can then be advantageously integrated leading to a savings in the number of components and in the area required for integration and improving in addition the performance in accordance with the instructions of the system set forth in claim 1. The invention is clarified by the description given below taken together with the annexed drawings wherein: FIG. 1 shows the circuitry diagram of a transconductor of the "fully differential" type in accordance with the known art, FIG. 2 shows the circuitry diagram of a transconductor of the "pseudo-differential" type in accordance with the known art, FIG. 3 shows a block diagram of a transconductor system in accordance with the present invention, FIG. 4 shows the circuitry diagram of an embodiment of the system of FIG. 3, and FIG. 5 shows the circuitry diagram of another embodiment of a transconductor system in accordance with the present invention. The system in accordance with the present invention of FIG. 3 has two input terminals IP and IM respectively, and two output terminals, OP and OM respectively. It comprises a first transconductor circuit C1 having two input terminals IP1 and IM1 and two output terminals OP1 and OM1 and a second transconductor circuit C2 also having two input terminals IP2 and IM2 and two output terminals OP2 and OM2. The circuits C1 and C2 are connected in parallel with each other. By providing the transconductor system C2 in such a manner that it has a common mode transconductance substantially equal in modulus to that of the first transconductor circuit C1 and of opposite sign the transconductor system thus achieved has common mode transconductance substantially null. Naturally the same relationship must not apply simultaneously also between the differential mode transconductances so that the differential mode transconductance of the system is the sum of those of the two circuits C1 and C2 and has a finite value. FIG. 4 shows an embodiment of the system (hence of the two circuits C1 and C2) of FIG. 3 wherein there are not shown for the sake of drawing clarity the connections between the various input and output terminals. The topology of the first transconductor circuit C1 coincides exactly with that of the circuit of FIG. 2 while that of the transconductor circuit C2 coincides with that of the circuit of FIG. 2 except that the drain terminals of the MOS input transistors are also connected together electrically. This connection causes the common mode transconductance to remain unchanged while the differential mode transconductance becomes substantially null. The outputs of the two circuits C1 and C2 of FIG. 4 are to be connected through an appropriate circuitry, not explicitly indicated in FIG. 3 nor in FIG. 4, which permits achieving the desired sign inversion of the common mode transconductance, e.g. by means of current mirrors. The differential mode transconductance of the system of FIG. 3 will coincide substantially then with the differential mode transconductance of the transconductor circuit C1. These observations on transconductance up to this point do not allow for their variations with frequency. It is natural that they must be satisfied at least in the operating range of the transconductor system. One branch of the transconductor circuit C2 consists of the series connection of a current generator G21, a BJT transistor T21 and a MOS transistor M21 and the other of a generator G22, a BJT T22 and a MOS M22. The bases of the BJTs T21 and T22 are connected together with the terminal UT having a fixed polarisation potential. The control gates of the MOS transistors M21 and M22 are connected respectively to a first input IP2 and a second input IM2. A first output OP2 is connected to the collector of the BJT transistor T21 and a second output OM2 is connected to the collector of the BJT transistor T22. In the diagram of FIG. 4 is shown also another terminal UG having another fixed polarisation potential designed to control the current generated by the generators G11, G12, G21, G22. The potential of the terminal UG is usually chosen in such a manner that, if there were no transconductor circuit C2, by applying to the inputs of the transconductor circuit C1 a common mode voltage equal to that expected at the system input, under normal operating conditions, the current at the system output is null. In this manner the need to cancel the common mode is minimised. In a perfectly symmetrical structure like that of FIG.4 the homologous devices must be as nearly identical as possible. In this case the choice of potential of the terminal UG is considerably freer. The diagram of FIG. 5 constitutes a particularly advantageous embodiment of the present invention. It consists of a first transconductance circuit identical to transconductor circuit C1 of FIG. 3 in which the generators G11 and G12 were provided by means of two MOS transistors M31 and M32 and a second transconductor circuit similar to the transconductor circuit C2 of FIG. 3 in which the two BJT transistors T21 and T22 have been replaced by a single BJT transistor T2 and in which the two generators G21 and G22 have been replaced by a single MOS transistor M4. It is important to note that the terminal UG has been connected electrically to the drain terminal of MOS transistor M4. In this manner the MOS transistors M31 and M32 in combination with the MOS transistor M4 form two current mirrors. The current mirrored is that generated by the second transconductor circuit which is sensitive to the common mode voltage at its input. By choosing the area of the MOS transistors M21 and M22 equal to half that of the MOS transistors M11 and M12 there is obtained the weighed sum of the common mode signals at input. Through the mirror are then activated sign inversion and transfer of the common mode current signal on the output. As concerns the frequency performance of this circuit, it is limited by the speed of the current mirror. Under ideal conditions of the parameters of the electronic devices and assuming that the mirror introduces a pole, it can be verified that the common mode rejection can be increased at will even beyond the values obtainable with the "fully differential" type circuits provided said pole is sufficiently high, i.e. the mirror is fast. To speed up the mirror there can be used, instead of the structure of FIG. 5, a "cascode" structure permitting for equal output resistance use of devices with shorter channel and hence faster.

Claims: Transconductor system comprising a first differential transconductor circuit (C1) including a couple of input transistors (M11, M12) each having a corresponding conduction terminal (ND) directly connected to a common fixed potential terminal (GND) and respective drive terminals (IP1, IM1) receiving differential input signals; said first transconductor circuit (C1) further comprising at least one bias current generator (M31, M32); said system comprising a second differential transconductor circuit (M21, M22, T2) having its input directly connected to the input of said first transconductor circuit and a differential mode transconductance of substantially null value and having its output connected to said bias current generator (M31, M32), whereby said second differential transconductor circuit includes a couple of input transistors (M21, M22) having corresponding conduction terminals connected together and a bias current generator (M4) connected in a mirror structure to said at least one bias current generator (M31, M32) of said first transconductor circuit so that the output current of said first transconductor circuit (C1) remains unchanged with variation of the common mode voltage at the circuit inputs. System in accordance with claim 1 in which the bias current generator of the second differential transconductor circuit comprises a single MOS transistor (M4). System in accordance with claim 1 or 2 in which said bias current generator of the first differential circuit (C1) comprises two MOS transistors (M31, M32), one for each branch of the differential stage. System in accordance with claim 1 wherein the area of the input transistors (M21, M22) of the second trasconductor circuit is half the area of the input transistors (M11, M12) of the first transconductor circuit. System in accordance with claim 2 wherein a single BJT transistor (T2) is inserted between the bias current generator of said second transconductor circuit (M4) and said input transistors (M21, M22) of said second transconductor circuit.

Inventors: BASCHIROTTO ANDREA, CASTELLO RINALDO, REZZI FRANCESCO, BASCHIROTTO, ANDREA, CASTELLO, RINALDO, REZZI, FRANCESCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: H03F3
IPC codes: H03F3