Method for lowering the phase transformation temperature of a metal silicide

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10¹⁷ atoms/cm³. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C.

Description: FIELD OF THE INVENTION The present invention relates generally to integrated circuit devices and, more particularly, to a method for forming a metal silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the metal silicide has been reduced by the use of a second refractory metal. DESCRIPTION OF THE PRIOR ART Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi 2 has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi 2 exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. This second step is disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements, especially at smaller line-widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional heat cycles, as is required by the second anneal step. Also, silicon nitride peeling and cracking have been associated with the second annealing step. The generally accepted set of processing conditions for forming titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature less than about 700°C, (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700°C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept below 700°C in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50-200°C above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thicknesses continue to be scaled down, it becomes ever more desirable to eliminate the need for this second anneal step, as discussed further below. It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of the C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent. A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thicknesses decrease, the thermal energy required to affect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve. Thus, there is a need for an improved method for forming the C54 phase of titanium silicide without requiring a second high-temperature annealing step, as in the generally-accepted process above. Eliminating the second annealing step would reduce the problems and limitations resulting from agglomeration of silicide films during the phase transformation anneal. In the Journal of Vacuum Science and Technology, Part A, vol. 9, no. 5, pages 2721-2726, a study of interfacial reactions between thin films of Ti-Ta and Si is published. Alloys of Ta concentrations of 20 % or higher are codeposited on Si substrates. Higher Ta concentrations are regarded to stabilize the C49 structure of titanium silicide. In the Journal of Applied Physics, vol. 56, no. 8, pages 2341-2345, a study of silicide formation for Ta-V and Ti-V alloys on Si is published. Bi-layers and alloys are deposited, the V concentrations being 20 % and higher. Good results of silicide layers are reported for anneal temperatures of 850 °C. In the Journal of Applied Physics, vol. 53, no. 10, pages 6898-6905, a study of Ti-V contacts on Si is published. Codepositions with V concentrations of 20 % and higher are reported. SUMMARY OF THE INVENTION The present invention is based on the problem to provide alternative and improved methods for forming TiSi 2 layers in silicon semiconductor devices. According to the invention, this problem is solved by means of the methods according to appended claims 1 and 18. It is to be noted that claims 1 and 18 relate to non identical groups of refractory metals. In other words, the above discussed need is satisfied, the limitations of the prior art overcome, and other benefits realized in accordance with the principles of the present invention by a method for forming TiSi 2 overlying a silicon layer on a semiconductor wafer. According to this method, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal (comprising Ti and later used to form TiSi 2 ) is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form TiSi 2 from the precursory metal. It should be noted that the term "precursory" is used throughout for purposes of identification and clarity only and does not itself imply any chemical properties of the metal it identifies. In addition to the titanium itself, the precursory metal layer may also incorporate silicon, as for example in the known polycide process. When the precursory metal layer incorporates silicon, the final metal silicide is obtained by heating the wafer to a temperature sufficient to obtain the desired solid phase following deposition of the metal-silicon alloy (which in some cases may be stoichiometric). In addition to Si, the precursory metal layer may incorporate other elements from periodic table Groups IIB, IIIB, IVB, VB, and VIB, including B, C, N, O, Al, P , S, Zn, Ga, Ge, As, Se, Cd, In, Sn, Sb, Te, Mg, Tl, Pb and Bi. Preferably, the phase transformation temperature of TiSi 2 is lowered by the presence of the refractory metal at the surface of the silicon layer. The refractory metal is preferably a metal that is capable of forming a metal silicide when heated to a temperature greater than about 900°C, and the concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 17 atoms/cm 3 . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr (W, Ta being excluded from claim 18), and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. There are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of the surface, for example within about 2 Angstroms. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about 10 12 to 5x10 14 atoms/cm 2 , and more preferably a dose of about 10 13 to 10 14 atoms/cm 2 . The preferred implant energy is about 45 to 90 KeV. In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. Also, the refractory metal may be disposed by sputtering or by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. For example, the solution may be a dilute acid solution containing HCl or nitric acid. Under all of the above disposition approaches except implantation, the thickness of the disposed refractory metal layer on the silicon surface is preferably less than about 2.0 nm, and more preferably about 0.5 to 1.5 nm. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C. In one approach, this annealing is performed for at least about 5 seconds using rapid thermal annealing (RTA). Alternatively, annealing in a furnace for at least about 10 minutes may be used. According to the present invention, a titanium silicide layer is formed overlying a silicon layer on a semiconductor wafer. According to this approach, a refractory metal is disposed proximate to the surface of the silicon layer, a titanium layer is deposited overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the titanium silicide layer at least in part from the titanium layer. Preferably, the titanium silicide layer formed during this heating step substantially exhibits the C54 phase of TiSi 2 . Preferably, the titanium layer is deposited to a thickness of about 25-57.5 nm, and the TiSi 2 layer is formed at a temperature less than about 700°C, and more preferably about 600-700°C. Also, the refractory metal is preferably Mo, Co, or W and is preferably disposed by either ion implantation or metal evaporation. It has been found that Mo and Co give the best results, even relative to W. Ion implantation is preferably performed with an implant dose of about 10 13 to 10 14 atoms/cm 2 . Preferably, the optional annealing step described above is performed. In an alternative embodiment according to the present invention, TiSi 2 is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form TiSi 2 from the precursory metal layer, where the phase transformation temperature of said TiSi 2 is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, the precursory metal and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent. Said refractory metal is Mo, Co, Nb, Ru or Cr, in this embodiment. In a preferred approach according to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about 1 atomic percent of the combined titanium and refractory metal weight. An advantage of the present invention is that a phase transformation annealing step is eliminated. With respect to titanium silicide the desired C54 phase is substantially formed directly during the titanium silicide formation step. No second phase transformation anneal is required. Also, agglomeration is essentially eliminated because the titanium silicide film is exposed to lower processing temperatures. As other advantages of the present invention, there is improved ability to control the microstructure of the final C54 phase of the silicide film, and the small grain size of the C54 phase grains may be less than the critical dimensions of the devices being fabricated. The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-3 are cross-sections illustrating the formation of the C54 phase of titanium silicide according to a preferred approach of the present invention. FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention. FIGS. 5-8 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases with and without the use of an evaporated or implanted refractory metal according to the present invention. FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION In a preferred approach according to the present invention, a titanium silicide layer having the C54 phase as the dominant phase is formed on a silicon layer by a single silicidation heating step. Because the TiSi 2 layer is formed having substantially the C54 phase, a second annealing step, which is required with prior methods, is not needed to transform the TiSi 2 from the C49 to the C54 phase. In this preferred approach a refractory metal is disposed proximate to the surface of the silicon layer, and a titanium layer is deposited over the refractory metal and the silicon surface. The wafer is then heated to a temperature of about 600 to 700°C for a time period sufficient to form the C54 phase of titanium silicide. More specifically, with reference to FIG. 1, a silicon layer 10, which may be a monocrystalline silicon wafer (100) or polycrystalline silicon, is provided. Silicon layer 10 may be, for example, a polycrystalline N or P-type line or a monocrystalline N or P-type region. The refractory metal is disposed either on or near a top surface 12 of silicon layer 10, depending in part on the manner in which the metal is disposed. It is believed that the refractory metal acts to lower the surface energy barrier for the formation of the C54 phase of TiSi 2 , and therefore, that the presence of the refractory metal at or near the surface promotes the formation of the C54 phase. It is believed that a refractory metal-silicon alloy is formed near top surface 12. It is not known with certainty whether this is a metal-silicon complex or a metal-silicon compound. In general, some of the disposed refractory metal should be on or within a few Angstroms of top surface 12. Of course, the exact disposition of the refractory metal atoms will depend upon the manner of disposition. However, for purposes of this application each manner of diposition described herein is considered to dispose refractory metal atoms proximate to the silicon surface. Referring now to FIG. 2, a refractory metal 14 is shown proximate to the surface of silicon layer 10. First, it should be appreciated that FIG. 2 is for illustrative purposes only and that refractory metal 14 will not necessarily cover all of top surface 12. Second, it should be noted that distribution of refractory metal 14 will vary also depending upon the manner of disposition. For example, if refractory metal 14 is disposed by ion implantation, then most of the metal will be below top surface 12. On the other hand, if the metal is disposed by evaporation, then most of the metal will be disposed on top surface 12, rather than underneath it. With both the ion implantation and evaporation approaches, it is believed that it is the concentration of the refractory metal proximate to top surface 12 that lowers the C54 phase surface energy barrier. After refractory metal 14 is disposed, then a titanium layer 16 is deposited over refractory metal 14 by, say, sputtering or evaporation. For example, a thickness of 25 to 57.5 nm is used, although one skilled in the art will recognize that greater and lesser thicknesses may also be used. Top surface 12 is not explicitly shown in FIG. 2 because its position will vary according to the manner of refractory metal disposition used. In addition to sputtering or evaporation, titanium layer 16 may also be deposited over refractory metal 14 by chemical vapor deposition. Further, when deposited by one of these methods, instead of an essentially titanium layer, a layer containing an alloy of Ti and Si may be deposited. This alloy may be stoichiometric TiSi 2 , but this is not required, and the Ti-Si alloy may be either rich or lean in its silicon composition. When a Ti-Si alloy is deposited, the method according to the present invention is substantially similar to that described herein. Any required modifications will be recognized by one of skill in the art. Also, as used herein, the deposition of a titanium layer may alternatively refer to the deposition of a titanium-silicon alloy layer. In FIG. 3, a TiSi 2 film 18 has been formed over silicon layer 10 by heating silicon layer 10 to a temperature between about 600 and 700°C for a time period sufficient for the C54 phase of TiSi 2 to form. This time period is generally about 20 seconds for RTA to about 20 minutes for annealing in a conventional furnace. According to the method of the present invention, it is believed that the forming TiSi 2 film does not substantially pass through the C49 phase, but primarily goes directly to the C54 phase due to the lowered surface energy barrier. An optional annealing step has been found beneficial for further promoting the formation of the C54 phase of TiSi 2 , especially when forming the silicide at lower temperatures, say below about 650°C. This optional anneal is performed following the disposition of refractory metal 14 and prior to the deposition of Ti layer 16. In general, this anneal is performed at a wafer temperature of at least about 900°C, and more preferably 900-1000°C, for a time period of at least about 5 seconds when using RTA and of generally about 10-30 minutes when using a conventional quartz furnace. A preferred anneal is at a temperature of about 900°C for about 10 minutes in a furnace in a N 2 ambient. It is believed that this optional anneal may further promote the formation of the refractory metal-silicon alloy at the surface of the silicon layer, though this is not certain. In general, it is believed that the refractory metal according to the method of the present invention may be any metal capable of forming a metal silicide when heated in the presence of silicon to a temperature greater than about 900°C. For the purposes of this application, "refractory metal" is defined to include, without limitation, the following preferred metals: Mo, Co, W, Ta, Nb, Ru, or Cr. Mo and Co provide the most significant effect, and W provides a somewhat less significant effect than Mo or Co. It is believed that the above metals will in general work with any of the herein disclosed manners of disposition, but ion implantation and evaporation of Mo, Co, and W are preferred approaches. Discussing now the above silicidation process in greater detail, there are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of top surface 12. It is believed that the refractory metal atoms closest to the silicon interface are most active, but other more distant atoms are not excluded from the meaning of proximate as used herein. For example, atoms within about 2 Angstroms (i.e. about 0.2 nm) of the surface may be the most active. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about 10 12 to 5x10 14 atoms/cm 2 and even more preferably a dose of about 10 13 to 10 14 atoms/cm 2 . The preferred implant energy for these cases is about 45 to 90 KeV. One way for implanting refractory metals involves the use of the arc chamber of commercially available ion implant systems. Because the arc chamber is commonly made from, or in other cases lined with, refractory metals (such a molybdenum, niobium, tantalum, or tungsten), one method of implanting these metals is accomplished by using the arc chamber as the source of the metal to be implanted. The metal species to be implanted is selected by appropriately varying the arc chamber material and by adjusting the magnetic analyzer to select the desired atomic mass unit (AMU) of the metal species based on the known isotopes of the desired species. For example, an appropriate setting is 98 AMU for Mo, or 184 for W. Because W is also a common filament material in the ion source filament of the implant tool, W can be alternatively implanted by adjusting the analyzer magnet to 184 AMU for singly-ionized W, or to 92 AMU for doubly-ionized W. The dose and energy selected for a particular metal species will be limited by the capabilities of the ion implant system and the time devoted to performing the implant. For the specific case of a Mo implant, a Mo arc chamber is installed into the implant system, a boron triflouride source gas (BF 3 ) is introduced into the arc chamber. It is believed that ionized BF 3 acts to volatilize molybdenum from the arc chamber to provide an adequate Mo ion (98Mo+) beam current of about 200 mA with an implant energy of at least about 45 KeV. Because arc chambers sometimes become coated with other materials during use in other conventional applications, it is preferred that a clean or new source chamber be used to obtain the Mo ion beam current. When implanting Mo atoms under the above conditions (i.e. an energy of 45 KeV), it has been determined that the greatest concentration of Mo atoms occurs at a depth in the silicon layer of about 30 nm, corresponding to a peak Mo concentration of about 10 19 atoms/cm 3 . However, as discussed above, the Mo atom concentration of greatest interest is that at the surface. When using the optional anneal step above, SIMS data has indicated that the concentration of Mo atoms at the surface is about 5x10 18 atoms/cm 3 . It is expected that a surface concentration of the refractory metal at the silicon interface less than about 10 17 atoms/cm 3 may be desirable. In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. This may be by either e-beam evaporation or by resistive heating (e.g. placing the pellet in a crucible that is heated by a large electrical current). When using evaporation, it is important that the thickness of the refractory metal not be too great. For example, the thickness of a Mo layer disposed on the silicon layer is preferably less than about 2.0 nm. This is not an absolute maximum thickness, but as the thickness of the Mo layer increases above 2.0 nm, peeling of the silicide film has been observed. More preferably, a Mo thickness of about 0.5-1.5 nm is used. The desired thicknesses for other metals may vary somewhat. When evaporating such small thicknesses of refractory metal onto the silicon layer, it is sometimes difficult to control the rate of evaporation. As a result, in one evaporation approach a shutter is positioned over the evaporation metal source chamber to contain the refractory metal until ready for disposition on the silicon layer. Then, the shutter is opened and closed fairly rapidly (a so-called "flash" evaporation) to provide a thin refractory metal layer over the silicon layer. Other evaporation approaches could be used that better control the rate of evaporation. As an alternative to evaporation of the refractory metal, the refractory metal may instead be disposed by sputtering to a thickness on the silicon layer similar to that described for evaporation above. Modifications used with a sputtering approach will be recognized by one skilled in the art. In addition to the above, the refractory metal may be disposed on the silicon layer by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. In a preferred approach, the solution is aqueous and may contain a dilute acid, such as HCl or nitric acid. According to this method, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal comprising Ti is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form TiSi 2 from the precursory metal. It is believed that the phase transformation temperature of TiSi 2 is lowered by the presence of the refractory metal at the surface of the silicon layer. Because of the small grain size of C54-phase TiSi 2 films, it is believed that the activation energy for the phase transformation to the C54 phase is lowered. The refractory metal is preferably a metal that is capable of forming a metal silicide. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. These temperatures are preferred for TiSi 2 . The several approaches for disposing the refractory metal discussed above may in general be used for the general method of the invention. Preferably, the refractory metal atoms are placed on or within a few Angstroms of the surface, and the thickness of these atoms is sufficiently thin to avoid silicide delamination due to stress effects. As above, the wafer is optionally annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C. FIGS. 4-9 present experimental data for several TiSi 2 films formed according to the present invention. FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention. The data indicated as a standard film was formed without a refractory metal and without a second phase transformation anneal. The TiSi 2 films corresponding to the data point for W, and the data for Mo were formed by a 600°C anneal for 30 minutes in N 2 on (100) single-crystal silicon according to the present invention. An optional 5 second, 1000°C, RTA anneal was used following the implantation of the refractory metal (used for both W and Mo). The optional anneal is necessary when the TiSi 2 film is formed at about 600°C, but is not necessary for a formation temperature of about 700°C. The sheet resistance for each film is indicated by the data points in the graph. FIGS. 5-7 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases both with and without the use of an evaporated refractory metal according to the present invention. These measurements were made by continuously placing a four-point probe within a furnace during the formation of the TiSi 2 films. The refractory metal in FIGS. 5-7, where used, was disposed by the "flash" evaporation method described above. FIG. 8 is an in-situ scanning resistance graph for TiSi 2 films where an implanted, rather than evaporate, refractory metal was used. Common conditions for FIGS. 5-8 include the formation of a silicide film from a Ti layer of about 57.5 nm thickness previously deposited over an approximately 300 nm polysilicon layer. Each silicide film was formed by gradually increasing temperature at about 15°C per minute. Looking now at FIG. 5, curve 30 shows sheet resistance behavior for a titanium silicide film formed without the use of a refractory metal. Curve 30 exhibits the known and expected alloy effect at about point 32, with curve 30 forming a resistance peak at about 500°C. Above about 500°C, its resistance drops as indicated by arrow 34. As the temperature moves from about 500°C to about 700°C, the forming TiSi 2 film is substantially in the C49 phase. At about 700°C curve 30 flattens out into a so-called "knee" at point 36 in which the resistance is substantially constant with increasing temperature. This "knee" results from the failure of the silicide film to convert from the C49 phase to the C54 phase until even higher temperatures are reached. In contrast to curve 30, curve 40 illustrates resistance for a silicide film formed following the disposition of about 0.015 nm of Mo according to the present invention. Behavior is similar, but note that the "knee" observed for curve 30 above is substantially not present for curve 40 (see point 42). It is believed that the absence of this knee indicates that the C54 phase of TiSi 2 is directly formed to a substantial degree during silicidation without passing through the C49 phase. In FIG. 6, curve 50 shows sheet resistance behavior for a forming silicide film where about a 0.015 nm Ta layer was disposed by flash evaporation according to the present invention. As for curve 40 in FIG. 5, no significant knee is observed during the formation of the C54 phase of TiSi 2 . In FIG. 7, curve 60 illustrates sheet resistance versus temperature for a TiSi 2 film formed using about 0.015 nm of W according to the present invention. Curves 30 and 40 are shown for comparison with curve 60. Again, for curve 60 there is no significant knee and the C54 phase is substantially formed at a temperature less than about 700°C. FIG. 8 is an in-situ scanning resistance graph illustrating the sheet resistance of a titanium silicide layer formed using an implanted refractory metal according to the present invention. Curve 70 is a control silicide film formed without a refractory metal, for comparison purposes, and curve 80 is a TiSi 2 film formed where Mo has been implanted (at a dosage of 10 14 atoms/cm 2 and an implant energy of 45 KeV) prior to depositing Ti. After implanting Mo, an annealing step was performed at 900°C for 10 minutes also prior to depositing Ti. As for the conventional curve 30 above, curve 70 exhibits a knee at point 72, but curve 80 does not. The absence of a knee for curve 80 indicates that the C54 phase of TiSi 2 is substantially formed at temperatures below about 700°C. FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention. In addition to the data presented in FIGS. 4-9 above, there is further support that the C49 phase is substantially by-passed in silicidation by the present invention. Optical micrographs of the C54 phase of titanium silicide layers formed according to the present invention have indicated a grain size significantly smaller than in the conventional case without a refractory metal. This supports that the nucleation energy barrier of the C54 phase is significantly reduced by the method of the present invention. This becomes most important in VLSI circuits where the linewidths are less than the grain size of the C54 phase that would be formed if using the conventional approach. Although it is believed that the method according to the present invention described above is fairly robust, there are some precautions to its use. First, heat cycles above 700°C for extended periods must be avoided when using the present invention to prevent possible silicide instability problems. Second, if the thickness of the refractory metal layer is too great, then delamination of the silicide may result. Another advantage of the present invention is that it does not create an amorphous silicon layer at the top surface of the silicon layer. Specifically, when using the ion implantation method to dispose the refractory metal, the optional annealing step removes any amorphous silicon that may be present. The optional anneal is not necessary with the other manners of disposition in order to avoid amorphous silicon. It is desirable to avoid the presence of amorphous silicon because it has been associated with junction leakage failures. In an alternative embodiment according to the present invention, TiSi 2 is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains TiSi 2 and a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form TiSi 2 from the precursory metal layer, where the phase transformation temperature of said TiSi 2 is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, Ti and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent. The preferred refractory metals discussed above are expected to also be useful with this embodiment. However, W and Ta are not claimed in this context. According to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about one atomic percent of the combined titanium and refractory metal weight. The source of the titanium may be a sputtering target or evaporation pellet. Although the present invention has been described in detail above, it is not intended to be limited to the specific form set forth herein, but, on the contrary, it is intended to cover such alternatives and equivalents as can reasonably be included within the scope of the invention as defined by the appended claims.

Claims: A method for forming TiSi 2 in a layer overlying a silicon layer on a semiconductor wafer, comprising the steps of: disposing a refractory metal being Mo, Co, W, Ta, Nb, Ru or Cr, proximate to or on the surface of said silicon layer; depositing a precursory metal comprising essentially titanium and, optionally, silicon in a layer overlying said refractory metal; and heating said wafer to a temperature of 700°C or less and sufficient to form said TiSi 2 from said precursory metal layer. The method of claim 1 wherein a phase transformation temperature of said TiSi 2 is lowered by the presence of said refractory metal at the surface of said silicon layer. The method of claim 1 or 2 wherein said refractory metal forms a metal-silicon alloy at or a metal-silicon complex on the surface of said silicon layer. The method of any of the preceding claims 1 to 3 wherein said refractory metal is capable of forming a metal silicide having a metastable solid phase. The method of any of the preceding claims 1 to 4 wherein the surface of said silicon layer is substantially free of amorphous silicon. The method of any of the preceding claims 1 to 5 wherein said TiSi 2 substantially exhibits the C54 phase, said C54 phase being formed without an annealing step following said step of heating. The method of claim 6 wherein said titanium layer is deposited to a thickness of between about 25 to about 57.5 nm. The method of any of the preceding claims 1 to 7 wherein the concentration of said refractory metal at the surface of said silicon layer is less than about 5x10 18 atoms/cm 3 , preferably less than about 10 17 atoms/cm 3 . The method of any of the preceding claims 1 to 8 wherein said silicon layer is polycrystalline silicon. The method of any of the preceding claims 1 to 9 wherein said refractory metal is disposed on the surface of said silicon layer or within about 0,2 nm of the surface of said silicon layer. The method of any of the preceding claims 1 to 10 wherein said step of disposing said refractory metal is performed by ion implantation, by sputtering, by metal evaporation or by exposing the surface of said silicon layer to a solution containing said refractory metal. The method of claim 11 comprising said ion implantation, wherein the implant dose of said implantation of said refractory metal is about 10 12 to about 5x10 14 atoms/cm 2 , preferably about 10 13 to about 10 14 atoms/cm 2 and said implant energy is about 45 to about 90 KeV. The method of claim 11 wherein said solution is aqueous and comprises a dilute acid, preferably HCl or nitric acid. The method of any of the preceding claims 1 to 13 wherein said step of heating is performed at a temperature of 600°C or more. The method of any of the preceding claims 1 to 14 wherein said step of disposing provides a refractory metal layer on said silicon surface having a thickness of less than about 2 nm, preferably of between about 0.5 and about 1.5 nm. The method of any of the preceding claims 1 to 15 further comprising the step of annealing said wafer following said step of disposing a refractory metal and prior to said step of depositing a titanium layer, wherein said step of annealing is performed at a wafer temperature of 900°C or more, preferably 1000°C or less. The method of claim 16 wherein said step of annealing is performed for at least about 5 seconds using rapid thermal annealing or for at least about 10 minutes using a semiconductor wafer furnace, wherein said step of annealing promotes the formation of an alloy of said refractory metal and silicon at the surface of said silicon layer. A method for forming TiSi 2 in a layer overlying a silicon layer on a semiconductor wafer, comprising the steps of: depositing a precursory metal layer comprising essentially titanium and, optionally, silicon overlying said silicon layer, said titanium layer containing a small quantity of a refractory metal being Mo, Co, Nb, Ru or Cr; and heating said wafer to a temperature of 700°C or less and sufficient to form said TiSi 2 from said precursory metal layer, a C54 phase transformation temperature of said TiSi 2 being lowered by the presence of said refractory metal at the surface of said silicon layer. The method of claim 18 wherein said precursory metal layer and said refractory metal are deposited from the same source. The method of claim 19 wherein said source is a sputtering target or an evaporation pellet.

Inventors: CABRAL CYRIL JR, CLEVENGER LAWRENCE ALFRED, D HEURLE FRANCOIS MAX, HARPER JAMES MCKELL EDWIN, MANN RANDY WILLIAM, MILES GLEN LESTER, RAKOWSKI DONALD WALTER DOUGLAS, CABRAL, CYRIL, JR., CLEVENGER, LAWRENCE ALFRED, D'HEURLE, FRANCOIS MAX, HARPER, JAMES MCKELL EDWIN, MANN, RANDY WILLIAM, MILES, GLEN LESTER, RAKOWSKI, DONALD WALTER DOUGLAS
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1994
Main classification: C30B1
IPC codes: C23C20, H01L21, C30B1