Level shifter circuit

Abstract: There is provided a level shifter circuit which operates such that when the potential of the input signal changes from the ground potential to the first power source potential, the third transistor turns to be ON, and the fifth transistor turns to be OFF. On this instance, since the potential of the output signal is higher than the first power source potential, the second electrode of the first transistor is initiated to be charged up through the third and the fourth transistors. After that, the potential of the output signal falls down when the eighth transistor turns to be ON state. Since the potential of the second electrode of the first transistor has been charged up, the second transistor quickly turns to be OFF state so that the rush current is reduced flown from the second power source potential to the ground potential. When the potential of the output signal drops down enough, the fourth transistor turns to be OFF state so that the rush current flown from the second power source potential to the first power source potential is prevented.

Description: The present invention relates to a level shifter circuit which generates an output signal having a desired level in response to the level of an input signal and more particularly to a level shifter circuit effectively employed in a semiconductor device or the like. Fig. 1 is a circuit diagram illustrating a conventional level shifter circuit which converts the voltage level of an input signal 1, input from an input terminal 1, having an amplitude of the ground voltage Vss, into the voltage level of an output signal 2, output from an output terminal 2 to a second stage circuit, having an amplitude of the potential difference between the second power source voltage Vpp higher than the first power source voltage Vcc and the ground voltage Vss. The level shifter circuit shown in Fig. 1 incorporates therein an inverter 3 which inputs the input signal 1 and an inverter 4 which inputs the output of the inverter 3 through a node N3 and outputs an inverted signal of the output from the inverter 3. The level shifter circuit also incorporates P channel type field effect transistors (hereinafter referred as PMOS) 5 and 6, in which the power source voltage Vpp is applied to each source and each drain is cross-connected to the other each gate, and N channel type field effect transistors (hereinafter referred as NMOS) 7 and 8 which are respectively connected between the drains of each PMOS 5 and PMOS 6 and the ground Vss and turn on and off in accordance with a potential level of a node N3 or a node N4 input to each gate. The drain of NMOS 7 is connected, at a node N5, to the drain of PMOS 5, and PMOS 6 turns on and off in response to the potential of the node N5. The drain of NMOS 8 is connected, at a node N6, to the drain of PMOS 6, and PMOS 5 turns on and off for outputting the potential level of the node N6 in response to the potential of the node N6. Fig. 2 is a waveform chart illustrating various operational waveforms of the level shifter circuit shown in Fig. 1. Now, description will be made as to an operation of the level shifter circuit shown in Fig. 2 with reference to Fig. 2. When the potential level of the input signal 1 changes from the potential Vss to the potential Vcc, the potential level of the node N4 becomes Vcc by the two inverters 3 and 4, which causes NMOS 8 to turn on as shown in Fig. 2(a) so as to drop the potential of the output signal 2. Concurrently, NMOS 7 turns to be off-state so that the potential of the node N5 turns to be the potential Vpp through PMOS 5 having on-state, in response to the potential of the output signal 2. When the potential of the node N5 turns to be the potential Vpp, PMOS 6 turns to be off-state, which causes the level of the node N6 to be the ground level Vss so that the level of the output signal 2 becomes the ground potential Vss. Consequently, when the potential level of the input signal 1 changes from the potential level Vcc to the potential level Vss, the inverter 3 changes the level of the node N3 from the ground potential level Vss to the potential level Vcc and turns NMOS 7 to be on-state. The inverter 4 changes the level of the node N4 to be the ground potential level Vss. As a result, NMOS 8 turns to be off-state, the level of the node N5 drops down from the potential level Vpp to the potential level Vss, and PMOS 6 and PMOS 5 respectively turn to be on and off States. Accordingly, the level of the node N6 becomes the potential level Vpp and the level of the output signal 2 becomes the potential level Vpp. As described above, when the potential level of the input signal 1 changes from the potential level Vss to the potential level Vcc, the potential level of the output signal 2 shifts from the level Vpp to the level Vss. On the other hand, when the potential level of the input signal 1 changes from the level Vcc to the level Vss, the potential level of the output signal 2 shifts from the level Vss to the level Vpp. There is disclosed a conventional level shifter circuit similar to the aforementioned one shown in Fig. 1 applied to a DRAM word line driving circuit in, for example, an article entitled as "Circuit Techniques For a wide Word I/O Oath 64 Meg DRAM" authored by K. Komatsuzaki et al. and published in a VLSI symposium 91. Fig. 3 is a circuit diagram illustrating another level shifter circuit pertained to a prior art, and Fig. 4 is a waveform chart illustrating operational waveforms of the circuit shown in Fig. 3. The circuit shown in Fig. 3 is constructed by supplementing a latch circuit 10 in the level shifter circuit shown in Fig. 1. As a result, the level shifter circuit shown in Fig. 3 can perform a level conversion operation similarly as the conventional circuit shown in Fig. 1 if a control signal c is being supplied. However, if the control signal c is not being supplied, the output signal maintains a constant level regardless of the level of the input signal. The level shifter circuit employs the latch circuit 10 for holding a potential which connects therethrough respective drains of PMOS 5. PMOS 6, NMOS 7 and NMOS 8. The latch circuit 10 is constituted of two transistors NMOS 11 and NMOS 12, each gate and drain of which is mutually cross connected with each other between the drains of each PMOS 5 and PMOS 6, and each source of which is connected to the ground potential level Vss, and a switch circuit 13. The switch circuit 13 is constituted of NMOS 15 which connects PMOS 5 with NMOS 7 by applying the control signal c to its gate, and NMOS 16 which connects PMOS 6 with NMOS 8 by applying the control signal c to its gate. The level shifter circuit shown in Fig. 3 can operate in the same manner as the level shifter circuit shown in Fig. 1, the operational waveforms of which are shown in Fig. 4, provided that the control signal c is being supplied, and can operate in such a manner that NMOS 15 and 16 turn to be off state if the control signal c is not provided. Accordingly, the potential level of the output signal 2 is preserved regardless of the potential of the input signal 1. However, the conventional level shifter circuit encounters the following problems. When the potential of the input signal 1 changes from the potential Vcc to the potential Vss or from the potential Vss to the potential Vcc, a rush current flows from the second power source potential Vpp to the ground potential Vss. There is another problem that a delay time is long which is defined as a period of time during when the potential of the output signal 2 changes from the potential Vss to the potential Vpp after the potential of the input signal 1 has changed from the potential Vcc to the potential Vss or during when the potential of the output 2 changes from the potential Vpp to the potential Vss after the potential of the input signal 1 has changed from the potential Vss to the potential Vcc. In other words, when the input signal 1 changes, as shown in Fig. 2(a), from Vcc to Vss, the inverter 3 changes the potential of the node N3 from Vss to Vcc, thereby NMOS 7 turning to be on-state. However, since the output signal 2 still stays in the potential Vss, both of PMOS 5 and NMOS 7 turn to be ON-state so that a large amount of rush current I1 flows and it also takes time that the potential of the node N5 turns to be the potential Vss. Further, when the potential of the node N5 drops, causing to turn PMOS 6 on, a large amount of rush current flows up until when the potential of the node N4 turns to be the potential Vss. Next, when the potential of the input signal 1 changes, as shown in Fig. 2(b), from the potential Vss to the potential Vcc, the potential of the node N4 changes, by the inverters 3 and 4, from the potential Vss to the potential Vcc. Accordingly, NMOS 8 turns to be ON-state, causing to turn both of PMOS 6 and NMOS 8 on, so that a large amount of rush current flows. On the other hand, it is prevented that the potential of the output signal 2 turns to be the potential Vss. Although no rush current flows in the level shifter circuit shown in Fig. 3 if the control signal c is not input because level shift has not occurred, the rush current flows in the same way, like the circuit shown in Fig. 1, if the level shift has been occurred by inputting the control signal c. There is also a problem that the delay time is long during when the potential of the output signal 2 changes from the potential Vss to the potential Vpp after the potential of the input signal 1 has changed from the potential Vcc to the potential Vss or during when the potential of the output 2 changes from the potential Vpp to the potential Vss after the potential of the input signal 1 has changed from the potential Vss to the potential Vcc. As described above, the conventional technology has problems that the rush current has inevitably been generated and the delay time is long. In a semiconductor circuit, in particular, in which the second power source potential is generated internally, increase of the rush current imposes heavy burdens on the internal voltage elevation circuit, which has caused a problem to affect operations of the other circuits. Further level shifter circuits are known from US-patents 4897567, 4561702, 5148061 and 5068551. From figure 3 of US-patent 4897567 there is already known a level shifter circuit having first and second transistors (N2, N3), third and fourth transistors (P4, P5) connected to driving circuits (N4, N5, P2, P3) operating between a first power source potential and a ground potential. Further, from figure 1 of US-patent 5148061 there is already known a level shifter circuit having first and second transistors (44, 48) third and fourth transistors (38, 40) connected to driving circuits (12, 14, 24, 26, 28, 30, 32) operating between a first power source potential (V cc ) and a ground potential. It is therefore an object of the present invention to provide a level shifter circuit enabling to solve the problems that a large amount of rush current flows and a delay time is long. To accomplish the above object, there is provided a level shifter circuit for generating an output signal having a desired level in accordance with a level of an input signal driven by a first power source potential according to claim 1. Preferred embodiments are defined in the dependant claims 2-11. In the present invention, since the first and the driving circuits are constituted of transistors, a level shifter circuit can be realized which operates in a high speed and can be incorporated into a semiconductor integrated circuit. The embodiment of the present invention has the advantage that the rush current can reduce flow from the second power source potential to the first power source potential. As a result, there can be realized a level shifter circuit having a low rush current and a low power consumption. Further a level shifter circuit having a latch function with low power consumption can be realized. Also, when the switch circuit stays in OFF state, the potential of the output signal can be preserved regardless of the input signal. Embodyments of the present invention are described with reference to the drawings in which Fig. 1 is a circuit diagram illustrating a conventional level shifter circuit; Fig. 2 is a waveform chart illustrating various operational waveforms appeared in the conventional circuit shown in Fig. 1; Fig. 3 is a circuit diagram illustrating another conventional level shifter circuit; Fig. 4 is a waveform chart illustrating various operational waveforms appeared in the conventional circuit shown in Fig. 3; Fig. 5 is a circuit diagram illustrating a level shifter circuit according to an embodiment of the present invention; Fig. 6 is a waveform chart illustrating various operational waveforms appeared in the level shifter circuit shown in Fig. 5; Fig. 7 is a circuit diagram illustrating another circuit example of a potential holding circuit in the level shifter circuit shown in Fig. 5; and Fig. 8 is a circuit diagram illustrating another circuit example of a reset circuit in the level shifter circuit shown in Fig. 5. Fig. 5 is a circuit diagram illustrating a level shifter circuit according to an embodiment of the present invention. The level shifter circuit shown in Fig. 5 converts the level of an input signal 61, provided that the control signal c is applied thereto, having an amplitude of a potential difference between the first power source potential Vcc input through an input terminal 61 and the ground potential Vss into an output signal 62 having an amplitude of a potential difference between the second power source potential Vpp higher than the potential Vcc and the ground potential Vss, and provides the output signal 62 to a next stage circuit through an output terminal 62. The potential of the output signal 62 is maintained constant regardless of the potential of the input signal 61 when the potential of the control signal c is Vss. The level shifter circuit shown in Fig. 5 incorporates therein an inverter 63 for driving the input signal 61, the first and second transistors, PMOS 65 and PMOS 66, each source, the first electrode, of which is commonly connected to the potential Vpp and each drain and gate, the second electrode and the control electrode, of which is cross connected with each other, the third transistor, NMOS 67, the drain of which is connected to a node N65 connecting the drain of PMOS 65 with the gate of PMOS 66, and the fourth transistor, NMOS 68, the drain of which is connected to a node N66 connecting the drain of PMOS 66 with the gate of PMOS 65. The gates of NMOS 67 and NMOS 68 are connected to nodes N66 and N65, respectively. The level shifter circuit further incorporates thereinto a potential holding circuit 70 connected between each source of NMOS 67 and NMOS 68 for operating in accordance with a potential difference between the potential Vcc and the potential Vss and for holding the potentials of the nodes N67 and N68 each connected to the sources of NMOS 67 and NMOS 68, a switch circuit 80 for connecting each node N67 and N68 with the potential Vss in response to the control signal c, and the first and second driving circuits, NMOS 91 and NMOS 92, for connecting each node N67 and N68 with the potential Vss in accordance with the input signal 61 and the output potential of the inverter 63. The potential holding circuit 70 is constituted of inverters 70a and 70b, each of input and output terminals of one inverter is connected to each output and input terminals of the other inverter, whereas the switch circuit 80 is constituted of NMOS 81 and NMOS 82, to both gates of which the control signal c is applied. Fig. 6 is a waveform chart illustrating various operational waveforms appeared in the level shifter circuit shown in Fig. 5, in which are shown each potential of the input signal 61, the output signal 62, the nodes N63, N65, N67 and N68, respectively. Detailed description will be made as to the level shifter circuit shown in Fig. 5 with reference to Fig. 6. Assuming, as shown in Fig. 6(a), that the potentials of the input signal 61 and the control signal c are Vss and Vcc, respectively, each potential of the node N63, the node N67, the node N68, the node N65 and the output signal 62 is Vcc, Vss, Vcc, Vss and Vpp, respectively. In other words, all of PMOS 66, NMOS 67, NMOS 81 and NMOS 91 are in ON state. If the potential of the input signal 61 changes from Vss to Vcc, the potential of the node N63 changes from Vcc to Vss due to the inverter 63, thereby NMOS 91 turning to be OFF state. Then, NMOS 92 turns to be ON state and the potential of the node N68 becomes Vss so that the potential of the node N67 becomes Vcc due to the inverter 70b. Since the potential of the node N65 is precharged through NMOS 67, the rush current flown to the potential Vss through PMOS 66 is reduced. Also, the potential of the output signal 62 is discharged through NMOS 68 to the potential Vss. On the other hand, the node N65 is further precharged, up to the potential Vpp through PMOS 65, which reduces the rush current. If the potential of the control signal c stays in the potential Vss, both of two NMOS 81 and NMOS 82 are in OFF state so that the potentials of the node N67 and the node N68 are maintained with the potential Vss. Accordingly, the potential of the output signal 62 is kept in the potential Vss. When the potential of the input signal 61 changes from the potential Vss to the potential Vcc as shown in Fig. 6(b), the potential of the node N63 is caused to change by the inverter 63 from the potential Vss to the potential Vcc so that NMOS 92 turns to be OFF state. Then, NMOS 91 turns to be ON state, the potential of the node N67 turns to be the potential Vss and the potential of the node N68 is caused to change by the inverter 70a to the potential Vcc. As a result, since the potential of the output signal 62 is precharged through NMOS 68, the rush current flown to the potential Vss through PMOS 65 is suppressed and the potential of the node N65 is discharged to the potential Vss through NMOS 67. On the other hand, the potential of the output signal 62 is further precharged, through PMOS 66, to the potential Vpp, which reduces the rush current. As described above, the embodiment operates such that the potential of the input signal 61 varies between the potential Vss and the potential Vcc, each potential of the sources of NMOS 67 and NMOS 68, the nodes N67 and N68, is determined to be the potential Vcc or the potential Vss by the inverters 70a and 70b when NMOS 81 and NMOS 82 in the switch circuit 80 are in OH state and either the node N65 or the node N66 is precharged through NMOS 67 or NMOS 68. As a result, there can be realized a level shifter circuit having a latch function with small power consumption. Also, the potential of the output signal 62 can be preserved regardless of the input signal when NMOS 81 and NMOS 82 in the switch circuit 80 stay in OFF state. Fig. 7 shows another circuit example of the potential holding circuit 70 in the embodiment shown in Fig. 5, in which a circuit diagram of a potential holding circuit 100 constituted of MOS transistors is illustrated. The potential holding circuit 100 is constituted of the first and second transistors, PMOS 101 and PMOS 102, each source, the first electrode, of which is commonly connected to the power source potential Vcc and each drain and gate, the second electrode and the control electrode, of which is mutually cross connected with each other, the third transistor, NMOS 103, the drain of which is connected to a node N101 connecting the drain of PMOS 101 with the gate of PMOS 102, and the fourth transistor, NMOS 104, the drain of which is connected to a node N102 connecting the drain of PMOS with the gate of PMOS 101. Each gate of NMOS 103 and NMOS 104 is respectively cross connected to the node 102 and the node N101. There is provided NMOS 105, the drain of which is connected to both sources of NMOS 103 and NMOS 104, which turns on and off in accordance with an input signal 101 and connects the sources of NMOS 103 and NMOS 104 with the potential Vss when it is in ON state. The nodes N101 and N102 are respectively connected to points A and B in Fig. 5. Now, description will be made as to the operation of the level shifter circuit employing the potential holding circuit 100 shown in Fig. 7 with reference to Figs. 5 and 7. In this embodiment, since the potential holding Circuit 70 in the level shifter circuit according to the third embodiment is replaced by the potential holding circuit 100, NMOS 105 turns to be OFF state if the input signal 101 is set to the potential Vss when the input signal 61 varies. As a result, the rush current flown from the potential Vcc to the potential Vss is reduced. The other operations of the fourth embodiment are similar to those of the third embodiment and there can be also realized the level shifter circuit having a latch function with small power consumption. By turning NMOS 105 to be ON state when NMOS 81 and NMOS 82 in the switch circuit 80 stay in OFF state, the potential of the output signal 62 is preserved regardless of the input signal. Fig. 8 shows another circuit example of the reset circuit 80 according to the embodiment shown in Fig. 5. A reset circuit 110 is constructed such that terminals C and D are connected to the nodes N67 and N68 of the level shifter circuit shown in Fig. 5 and the potentials of the nodes N67 and N68 are determined in accordance with a reset signal r. The reset circuit 110 has the fifth transistor, NMOS 111, the first and second electrodes, the drain and the source, of which are connected to the terminal C and the potential Vss, respectively, and the sixth transistor, NMOS 112, the drain and source of which are connected to the potential Vcc and the terminal D, respectively. The reset signal r is input to the gate of NMOS 111 and also to the gate of NMOS 112 through an inverter 113. Now, description will be made as to the operation of the level shifter circuit employing the reset circuit 110 with reference to Fig. 5. If the potential of the reset signal r becomes Vcc, NMOS 111 turns to be ON state and the potential of the node N67 is set to Vss. Concurrently, the potential of the node N68 is set to Vcc and the potential of the output signal 62 turns to be Vpp. In other words, a reset operation is performed. When the potential of the reset signal r stays in the potential Vss without receiving the reset signal ρ, NMOS 111 and PMOS 112 stay in OFF state so that the level shifter circuit shown in Fig. 5 performs the normal operation as shown in Fig. 6. As described above, since the present embodiment employs the reset circuit 110 in the level shifter circuit, it can reset the output regardless of the potential of the input signal 61. It has to be noted that the present invention is not restricted to the above mentioned embodiments and various modifications can be accomplished. Followings are, for example, such modifications. (1) Each PMOS and NMOS utilized in the embodiment can be replaced by NMOS and PMOS. In this case, the level shifter circuit can be constructed such that the input signal is input having an amplitude of a potential difference between the potentials Vcc and Vss and converted to a signal having an amplitude of a potential difference between the potentials Vcc and Vbb which is lower than Vss. This case also reveals similar advantages common to those of the first through fifth embodiments and realizes a low power consumption and a high speed operation in the second power source potential. (2) Each PMOS and NMOS utilized in the embodiment can be also replaced by PNP type and NPN type bipolar transistors, respectively. (3) The reset circuit 110 can be connected in a reverse direction to the nodes N67 and N68. In this case, the potentials of the nodes N67 and N68 are respectively set to Vcc and Vss.

Claims: A level shifter circuit for generating an output signal having a desired level in response to a level of an input signal that is driven by a first power source potential, comprising: (a) a first and a second transistor (65, 66) of a first conductivity type each having a first, a second and a control electrode; each first electrode being connected to a second power source potential (V PP ) different from the first power source potential (V CC ); the second electrode of the first transistor (65) being connected to the control electrode of the second transistor (66) for controlling conductance between the first electrode and the second electrode of the second transistor (66); the second electrode of the second transistor being cross connected to the control electrode of the first transistor for controlling conductance between the first and second electrode of the first transistor (65); (b) a third transistor (67) of a second conductivity type having a first, a second and a control electrode; the second electrode being connected to the second electrode of the first transistor; the control electrode being directly connected to the second electrode of the second transistor; the first electrode being connected to an output stage of a first driving circuit (91); and (c) a fourth transistor (68) of the second conductivity type having a first, a second and a control electrode; the second electrode being connected to the second electrode of the second transistor; the control electrode being directly connected to the second electrode of the first transistor; the first electrode being connected to an output stage of a second driving circuit (92), (d) a potential holding circuit (70) connected between the first electrodes of the third and fourth transistors (67, 68) and operating between the first power source potential and a ground potential, to preserve potentials of the first electrode of the third and fourth transistors; (e) said first driving circuit (91) turning on and off in response to a potential of the input signal, for connecting the first electrode of the third transistor to the ground potential when the first driving circuit is in the ON state; (f) said second driving circuit (92) turning on and off complementarily relative to the state of the first driving circuit in response to the potential of the input signal, for connecting the first electrode of the fourth transistor with the ground potential when the second driving circuit is in the ON state. A level shifter circuit as set forth in claim 1, wherein a first conductivity type transistor is a PMOS transistor and a second conductivity type transistor is an NMOS transistor. A level shifter circuit as set forth in claim 1, wherein the second power source potential (V PP ) is higher than the first power source potential (V CC ). A level shifter circuit as set forth in claim 1, wherein the circuit further comprises a switch circuit (80) for connecting the first electrode of the third and fourth transistors with the first and second driving circuits, respectively, in accordance with a potential of a control signal. A level shifter circuit as set forth in claim 4, wherein the switch circuit (80) further comprises a fifth transistor (81) having a first, a second and a control electrode for receiving the control signal from the control electrode; the second electrode being connected to the first electrode of the third transistor; the first electrode being connected to the first driving circuit, and a sixth transistor (82) having a first, a second and a control electrode for receiving the control signal from the control electrode; the second electrode being connected to the first electrode of the fourth transistor; the first electrode being connected to the second driving circuit. A level shifter circuit as set forth in claim 4, wherein the potential holding circuit (70) is constituted of a first inverter (70a) and a second inverter (70b), each input and output terminal of which is cross connected to each output and input terminal of which is cross connected to each output and input terminal of the other inverter. A level shifter circuit as set forth in claim 4, wherein the potential holding circuit (70) further comprises: a seventh and an eighth transistor (101, 102) of the first conductivity type each having a first, a second and a control electrode; each first electrode being connected to the first power source potential; the control electrode and the second electrode being mutually cross connected; a ninth transistor (103) of the second conductivity having a first, a second and a control electrode; the second electrode being connected to the second electrode of the seventh transistor; which turns on and off in accordance with a potential of the second electrode of the eighth transistor, to connect the control electrode of the eighth transistor with the first electrode of the ninth transistor when in an ON state; a tenth transistor (104) of the second conductivity type having a first, a second and a control electrode; the second electrode being connected to the second electrode of the eighth transistor; which turns on and off in accordance with a potential of the second electrode of the seventh transistor, to connect the control electrode of the seventh transistor with the first electrode of the tenth transistor when in an ON state; and an eleventh transistor (105) for connecting the first electrode of the the ninth and tenth transistors to the wound potential in accordance with the potential of the potential holding input signal. A level shifter circuit as set forth in claim 7, wherein the first conductivity type transistor is a PMOS transistor and the second conductivity type transistor is an NMOS transistor. A level shifter circuit as set forth in claim 4, wherein the circuit further comprises a reset circuit (110) for resetting an output regardless of the potential of the input signal including: a twelfth transistor (111) connected to the first electrode of the third transistor, for tuning on and off in accordance with a potential of a reset signal and for connecting the first electrode of the third transistor with the ground potential when the twelfth transistor is in an ON state; and a thirteenth transistor (112) connected to the first electrode of the fourth transistor (68) with the first power source potential when the thirteenth transistor (112) is in an ON state. A level shifter circuit as set forth in claim 4, wherein the first electrode is a source and the second electrode is a drain and the control electrode is a gate. A level shifter as set forth in claim 1, wherein the control electrode of the third transistor (67) is further connected to a third output node (N66), and the control electrode of the fourth transistor (68) is further connected to a fourth output node (N65).

Inventors: TANABE TETSUYA, TANAKA YASUHIRO, TANOI SATORU, TANABE, TETSUYA, TANAKA, YASUHIRO, TANOI, SATORU
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1994
Main classification: H03K3
IPC codes: H03K3, H03K5, H03K19, G06F3