Graphics computer

Abstract: To reduce the hardware of the graphics computer in size and reduce the cost of the hardware by uniting the frame buffer and the main memory into one to process graphics data in the CPU. The frame buffer is arranged in the main memory, and a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer are provided for the said graphics computer. Especially, the said memories are formed so that the single function procedure and the multifunction procedure can be selected to suit the drawing object in them. In addition, the single function procedure includes the line drawing procedure that uses data tables and the multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one, the CPU has come to process graphics data. Thus, the graphics computer hardware has been reduced in size and the cost of the hardware has been reduced.

Description: This invention is related to graphics computers that process images to draw graphics data such as characters and graphic elements, and image data processing systems or graphics computers that use such an image processor. Especially, this invention is related to an image data processing system that expands and processes binary data of characters, symbols, etc. in a low-price and compact graphics computer, as well as to the memory configuration and control method to shorten the drawing time. The graphics computer that stores character codes and graphic elements and draws, displays, or prints out graphics data on the basis of them uses frame buffers to store the said data corresponding to the pixels to be displayed on screen (hereafter, to be referred to as pixel data). When drawing graphics data, drawing processings and display processings are needed. The drawing processing includes computing of pixel positions and pixel data itself from character codes and graphic elements and writing the pixel data in the frame buffer according to the pixel positions. The display processing includes repetitive and sequential reading of pixel data from the frame buffer corresponding to the pixels displayed on the screen synchronously with the raster scanning in the display device to display stable images on the screen. In this section, the conventional technology related to display data will be explained first. In order to reduce the price of a graphics computer, a well-known method is adopting a configuration in which the frame buffer is arranged in the large capacity main memory. Such the embodiment is disclosed in the graphics processing system described in Japanese Patent Laid-Open No.84192/1992, and by the display architecture designed by Robert P. Colwell and described in "IEEE 1st International Conference on Computer Workstation", (pp.30-37) (Nov., 1985), which is a scientific journal published in the United States. In those devices, a high access mode for DRAM, etc. used as a memory is used for display, reducing the display processing load. In other words, the horizontal direction of the frame buffer is aligned to the direction of the column addresses in the DRAM, etc. When drawing pixel data, however, accesses to addresses of different rows are often accessed in the frame buffer even for continuous pixels in the 2-dimensional coordinate system. For example, when drawing a line, which is almost vertical, those addresses are separated from each other as much as the width of the frame buffer horizontal memory even when they are adjacent in the 2-dimensional coordinate system. At present, the main current of the display format for personal computers is 640 pixels in the horizontal direction X, 480 pixels in the vertical direction, and one byte is assigned per pixel, but the number of bytes per pixel is changed now to 4 bytes. In other words, the horizontal memory width is 640 bytes or 2560 bytes. The column address width for DRAM, etc. is 1 KB to 4 KB. Since both are almost the same in size, addresses of different row are often accessed for the said vertical two consecutive pixels. The high speed access mode is effective only for accessing addresses of the same row. The said conventional technology may not be enough therefore to speed up the access satisfactorily for drawing. (1st conventional technology) As for the line drawing method among drawing processings, a method to find an equation to represent a line between two points from two coordinate points and find a coordinate point between the two points using the equation is described on pages 443 to 446 in "Computer Graphics" (published in 1984) written by James D. Foly and Andries Van Dam, and translated by Atsumi Imamiya. (2nd conventional technology) An embodiment of a high speed line drawing system is described in Japanese Patent Laid-Open No.200087/1982. (3rd conventional technology) According to this system, coordinates for drawing are found by reading the vector data represented by the increment of the Y coordinate when the X coordinate is increased by one. The vector data is expanded to dots beforehand and the result is stored in the vector data storage, and storing addresses are computed from the coordinates of start and end points. Another method is also described in Japanese Patent Laid-Open No.200087/1982. According to the method, vector data is expanded to dots beforehand, then stored in the vector data storage, and storing addresses are computed from the coordinates of start and end points. The coordinates for drawing are then found by reading the vector data represented by the increment of the Y coordinate when the X coordinate is increased by one. An embodiment of a character drawing system is described in "HD64410 ARTOP User's Manual" (pages 194 to 199) (4th conventional technology). The system draws pixel data in the frame buffer by expanding binary data such as characters to multivalue data. In this document, expansion of binary data represented by "0" and "1" in the format of 16 x 16 bits as shown in Figure 2 to multivalue data is described. This binary data, for example, means character and symbol data (hereafter, to be referred to as character data). A set of such character data is stored in a character generator ROM (CGROM). A character code is assigned to each character data and characters are accessed with those character codes. Therefore, the addresses of the character data corresponding to character codes stored in a memory can be found by computing numerals according to the characteristics of the arrangement of characters. The character data whose correspondence to such memory addresses is clear may be considered to be a coordinate system comprising 16 pixels in the X direction and 16 pixels in the Y direction and assuming the point that has row number 1 and column number 1 as the origin as shown in Figure 2. Expansion of binary data to multivalue data is done by converting character data represented by binary data of k and the addresses of the character data in CGROM to multivalue (colored and multigraded) data and its addresses in the frame buffer. The 5th conventional technology is a method for high speed drawing, which includs binary data mask processings. The method is described in Japanese Patent Laid-Open No.135162/1993 "Image Processing System". This conventional technology is related to expansion of binary data to multivalue data and using multi-colors for display. The method is a little different in handling color elements from the drawing technology mentioned here. In other words, since RGB color elements are taken into account for display, one pixel comprises 3 elements and more data is handled. As a result, processings become more complex than those of the said basic technology for multivalue expansion. In this invention, however, the same concept as the multivalue expansion to be made for drawing can be assumed by paying attention to one color element. This invention is featured by using a RAM to store multivalue data corresponding to "1" of binary data. In this RAM is stored expanded data for plural pixels. With this, plural pixels can be processed concurrently to speed up the expansion processing. The multivalue expansion processing is done by masking the multivalue data for the number of pixels stored in the RAM corresponding to "0" of binary data. EP-O-280523 described a computer system conversion apparatus in which data from a first address bus is converted by a conversion means and output to a second address bus. According to the 1st conventional technology, the access to the frame buffer is often done to addresses of different rows in memory. And, in the high speed memory access mode is allowed only within the addresses of the same row. Therefore, the access time may not be speeded up enough for drawing pixel data in the said conventional technology. According to the 2nd conventional technology, no line length is considered enough for drawing, and equations to compute coordinate points must be found regardless of the line length. The processing to find the equations to compute this coordinate point must be programmed with combinations of many instructions. Therefore, when drawing a short line, the processing time to compute those equations becomes longer than the drawing time. Furthermore, according to the 3rd conventional technology, the technology is effective to draw a line at high speeds, but the vector data capacity is not considered enough. Thus, a problem arises from the vector data storage capacity, which is needed more. According to the 4th conventional technology, every pixel data for a character code is expanded to multivalue data individually. This is why it is impossible to process pixel data at high speeds. In the speeding-up method of the 5th conventional technology, the data corresponding to "0" of binary data is always masked and it is not converted to a specific color. The method cannot cope with draw processings without a mask processing, and it cannot draw the background of a character as shown in Figure 5. If, when this speeding-up method is applied to a system that uses a CPU, memory access is restricted for writing the result of concurrently expanded plural pixels in the frame buffer, then the following problem will arise. The problem is that the memory access restriction may be needed, since CPU must speed up its internal processings. This memory access restriction, as described on pages 94 to 97 of "Computer Architecture A Quantitative Approach", means that when a memory is accessed in words or long words, the addresses must be even numbers or multiples of 4. The standard unit to access a memory is bytes. For example, when data is written in the frame buffer in long words, the address of the destination must be a multiple of 4. In other cases, writing is allowed only with a smaller size. According to the present invention there is provided a microcomputer provided with: a CPU that computes data to be displayed on a raster scanning type display unit, first address bus connected to memories used to store said data, a second address bus connected to said CPU and used to specify the destination of the said data, registers used to store address conversion data (MXC, TA, YS, XS) set by said CPU and an address converter that converts addresses from said second address bus and outputs them to said first address bus; characterised in that: said address converter is provided with first information (TA) that specifies an area in the said memory to which to convert addresses according to the address conversion information stored in said registers; said address converter converts addresses according to said first information (TA), when addresses are generated on the second address bus. Use of the present invention enables a reduction in the size and price of the subject graphics computer, as well as shorten the drawing time. In particular, it may speed up the access to the frame buffer arranged in the main memory when drawing pixel data by making good use of the high speed access mode of the main memory comprising DRAM, etc., although such a memory configuration has not been considered so far. (This corresponds to the 1st conventional technology.) In order to achieve the properties of this invention, the addresses of the same row in the general-purpose area in the main memory may be handled as continuous addresses from CPU or DMAC, since registers and an address converter are provided. On the other hand, the addresses of the same row in the frame buffer are arranged two-dimensionally when viewing them from CPU or DMAC. Thus, the pixels continued in the vertical direction can be accessed within the addresses of the same row. CPU programs are arithmetic operation data that are often continued one-dimensionally therefore can be stored in the said general-purpose area, while graphics pixel data that is often continued two-dimensionally can be stored in the frame buffer so that accesses for both drawings and other purposes can be speeded up significantly. An example of the invention will be more particularly described with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a graphics computer of an example of the invention. Figure 2 is an example of a binary data; Figure 3 is a 3rd Memory Internal Configuration; Figure 4 is a schematic diagram of a graphics computer; Figure 5 is an example of conventional frame buffer mapping; Figure 6 is an example of a frame buffer physical mapping; Figure 7 is a Timing Chart of Display; Figure 8 is another configuration of a graphics computer of the invention; Figure 9 is still another configuration of the graphics Computer; Figure 1 shows an embodiment of this invention that reduces the subject graphic computer in size and cut down its drawing time. The graphic computer described in this embodiment comprises a 20 MHz microcomputer 001; a 16-bit data width main memory 002 (DRAM) that integrates frame buffers 020; a 16-bit data width 2nd memory 003 (ROM) used to store application program 031 and graphic data 030; a display control unit 004 used to control display so that draw data can be displayed on an LCD 005; an external memory 006 comprising a CD-ROM unit or hard disk unit used to store mass graphic data and application programs; and an LCD display 005 (320 x 240 pixels) whose synchronization timing conforms to the TV NTSC system. In Figure 1, the liquid crystal display 005 is abbreviated as an LCD, which will be referred so hereafter. Although an LCD 005 is used as a display unit of the said graphic computer, it may be replaced with a raster scanning type display such as a cathode-ray tube without changing its real nature. The microcomputer 001 comprises a CPU 010, which is an operation means; and a 16-bit data width 3rd memory 013 (ROM) used to store display control procedures; a 16-bit data width 4th memory 014 (RAM); a direct memory access controller 011 used to read pixel data from the said frame buffer 020 and transfer the data to the display control unit 004; a display control signal generating means 012 used to generate display signals to synchronize with the LCD 005; a bus controller 015 that connects the 2nd bus 017, which is an internal bus of the computer 001, and the 1st bus 007, which is an external bus; and an oscillator 016 that generates the system clock 160. In Figure 1, the direct memory access controller 011 and the bus state controller 015 are abbreviated as DMAC and BSC respectively. Hereafter, they will be referred so. Hereafter, how a drawing will be done in this embodiment will be explained. The CPU 010 is an operation means that executes application program and generates graphic data such as characters and graphic elements according to the requests from the application program. The CPU 010 operation will be as follows; it executes arithmetic operations for the pixel positions and pixel data stored in the frame buffer 020 according to the plotting procedure stored in the 3rd memory 013 and the graphic data comprising characters and graphic elements given from the subject application program, then writes the pixel data in the pixel positions through the BSC 015 and the 1st bus 007. The BSC 015, which is connected to the 2nd bus 017 and the 1st bus 007, multiplexes row addresses and column addresses and generates bus control signals such as column address strobe and row address strobe to connect the main memory 002 that comprises the said DRAM to the microcomputer 001 directly through the 1st bus 007. Furthermore, the CPU 010 compares the row address in the previous accessing of the main memory 002 with the row address in the current accessing to detect an access that can use the high speed page mode automatically and generates an access in the high speed page mode automatically. This BSC 015 has enabled automatic access to the main memory 002 or the frame buffer 020 in the high speed page mode without adding any logical means. This embodiment that has also made possible to change the method to access the frame buffer according to the draw coordinate system to be explained later is mainly materialized as the BSC 015 function. The 3rd memory 013 stores as the draw procedures 131. These procedures, called from the subject application program, are fetched and executed in the CPU 010 sequentially through the 2nd bus 017. The CPU 010 draws graphic and character elements in the frame buffer and generates display control signals by executing these procedures. Figure 3 shows how data is stored in the 3rd memory 013. The display control procedure 130 calculates the number of notices to end the transfer operation of the DMAC 011 and judges according to this notice count whether or not the raster with which the DMAC has ended the transfer operation is the last one in the vertical direction on the LCD 005 screen. If it is not the last one, the DMAC 011 is initialized. This initialization means that the next start address, the number of words to be transferred corresponding to the pixel data for one raster, and the DMAC 011 are set in the status waiting for the DMA request signal 042. If the frame buffer 020 matches with the LCD 005 in size, the source address of the DMAC 011 is counted up for each access. In this case, it is no need to set the start address of the next raster as a source address. It is already generated. On the other hand, if the notice count indicates the last raster, the notice count is cleared, and the start address of the first raster, the number of words to be transferred corresponding to the pixel data for one raster, and the DMAC 011 are set in the status waiting for the DMA request signal 042. When the CPU 010 executes the above procedures sequentially, it becomes possible to scan the frame buffer 020 in the vertical direction. With the vertical scanning of the frame buffer 020 by software such way the price of the graphic computer can be reduced significantly. When the frame buffer 020 is widened more than the screen of the LCD 005 and the said display control procedure 130 is used, the scroll processing can be made smoothly. In general, it is known that the scroll processing can be done by moving the display area in the frame buffer step by step repetitively. Since the display control procedure 130 is used to specify the start addresses of rasters, those addresses are changed gradually to smooth the scroll processing in this invention. The pixel data for a raster is transferred to the display control unit 004 at the timing synchronized with the horizontal scanning of the LCD 005. The pixel data is then converted to analog RGB signals 040 in the display control unit 004 and output to the LCD 005. The drawing procedure 131 comprises two or more procedures, each of which is independent and corresponds to a pattern element. They are classified into single function procedures 132 and multiple function procedures 136. The multiple function procedures 136 are used to draw graphic elements according to the attribute specified by the subject application program corresponding to each graphic element. For this purpose, attributes must be judged and processings must be branched and executed according to the result of each judgment. The single function procedures 132 are used to draw graphic elements according to the specific attribute corresponding to each graphic element, not according to the specified attributes. Attributes to appear very frequently in each graphic element are used as these specific attributes. The details will be explained later. For example, the said specific attributes are those that are used very frequently for points, lines, and filled-in rectangular areas, and only a single color is used for them and they are overwritten on graphic elements already drawn. For such attributes, it is not need to change the color and compute for between the background pixel data and the pixel data to write. In other words, when the single function procedure 132 is used, the drawing can be done by writing computed pixel data in the computed pixel position merely. Since processings of attributes can be eliminated such way, the single function procedure 132 becomes faster than the multiple function procedures 136. In addition, this embodiment includes the high speed line draw procedure 133 that is specifically used to draw lines and the multiple values processing procedure 134 that processes multiple values at high speeds. The said procedures can therefore be classified into 3 types including the draw procedure 135 from which the said attribute processing is excluded. In spite of the description above, a few attributes must be specified for drawing some graphic elements, for example, when drawing a broken line. Such a case will be explained below. When drawing a broken line, the line is specified for the attribute that controls solid lines and broken lines. Then, the data that specifies the broken line pitch is specified and the multiple function procedure 136 is executed. This attribute is called a line style and the data that specifies the broken line pitch is called a line style pattern. In this case, since a judgment is done for whether to write pixel data for each pixel corresponding to the selected line style pattern, the processing time becomes longer than that of the single function procedure 132. As mentioned above, both the single function procedures 132 that processes simple attributes used very frequently at high speeds and the multiple function procedure 136 that processes complex attributes are provided in this embodiment to shorten the drawing time while keeping the general purpose properties of the graphics computer. Those multi-function procedure 136 and single function procedure 132 are built up as a graphics library that can be called from the subject application program described with a high class language. The high class language conforms to the C language standardized by ANSI. When drawing is possible only with the single function procedure 132, it is no need to connect the general purpose multi-function procedure 136 to the application program. In such a case, the capacity of the 3rd memory 013 can be saved. When the single function procedure 132 is not needed, it is no need to connect it to the application program. In such a case, the capacity of the 3rd memory 013 can also be saved. In the example of the vehicle navigation that uses this invention, which will be explained later, only a few procedures among the draw procedures for various graphic elements that belong to the single function procedure 132 are used. Therefore, only a few procedures are connected to the application program, and the application program is also stored in the 3rd memory 013. Draw procedures are provided for each graphic element such way, as well as both multi-function procedure 136 and the single function procedure 132 are provided for attributes of graphic elements so that only necessary draw procedures can be connected to the application program to reduce the capacity of the memory used for the said graphics computer and reduce the price of the graphics computer. In this section, another embodiment of the draw procedures will be explained, leaving the embodiment shown in Figure 1 for a while. Another embodiment of draw procedures has a configuration in which a procedure is provided for each graphic element. In this configuration, the single function procedure 132 is included in the multi-function procedure 136. In this case, the attribute specified for the subject graphic element is judged and when it matches with the said specific attribute, the single function procedure 132 is started. Also in this execution form, the drawing time can be shortened corresponding to the graphic element attribute. Furthermore, since one procedure is provided for each graphic element, the number of draw procedures can be reduced so that the application programmer can understand the said graphic library easily. In addition, since drawing is done according to the specified attributes, the application program can be debugged more easily. And, attributes of graphic elements are often already defined when the application program is created. Thus, judging specific attributes in the draw procedures like in this embodiment becomes a redundant processing when viewing it from the programmer's viewpoint. In other words, the drawing time cannot be shortened enough when compared with that of the embodiment shown in Figure 1. Now we return to Figure 1. The DMAC 011 reads the pixel data for a raster continuously from the frame buffer 020 through the 2nd bus 017, the BSC 015, and the 1st bus 007 according to the DMA request signal 042 synchronized with the horizontal scanning of the LCD 005, and transfers the data to the display control unit 004. At this time, the DMAC 011 issues the bus arbitration signal 100 to the BSC 015 to request an access to the 2nd bus. In response to this request, the BSC 015 stops the CPU 010, and gives the DMAC 011 the bus access right. Given the bus access right, the DMAC 011 issues read access signals continuously to read the specified number of pixels beginning at the start address of the raster set by the CPU 010 beforehand. Since two or more pixels can be obtained by an access, the number of read accesses becomes a value obtained by dividing the number of pixels of a raster by the number of pixels included in a word. In this embodiment, for example, since the 1st bus data is 16 bits in width and the pixel data comprises 8 bits (256 colors displayed at a time), one word contains 2 pixels. And since a raster (a row in the horizontal direction) of both the frame buffer 020 and the LCD 005 comprises 320 pixels, it is accessed by 160 times. The BSC 015 can access DRAM instead of accessing a specific address space according to the setting. In this embodiment, a DRAM is used as the main memory 002 that includes the frame buffer 020 to reduce the price of the memory. Therefore, the main memory 002 is arranged in the said specific address space and the BSC 015 is set so that it may access the DRAM instead of accessing this address space. The CPU 010 executes this setting under the control of the application program. The BSC 015 multiplexes the addresses issued by the DMAC 011 to row and column addresses and executes the DRAM random read cycle for the 2st bus 007. If the column address matches with that of the preceding DRAM access, a high speed page cycle is executed. In addition, since the access is done by the DMAC 011, the BSC 015 generates the DMA write signal 150 and writes the pixel data read from the frame buffer 020 in the display control unit 004 during the read access cycle. The time to access the DRAM (262144 words x 16 bits) used in this embodiment is 80 nsec and the cycle time is 150 nsec. The number of words in addresses of the same row is 512. The system clock 160 is 20 MHz. So, the BSC 015 is set so that 4 clocks may be assumed for a random access in which the DRAM access cycle is issued from a row address and 2 clocks for a high speed page access. The CPU 010 executes this setting under the control of the application program. In the first access to a raster, the DRAM row addresses often differ from those in the previous access, so that it becomes a random access. A row address may also be changed during a continuous access to a raster. Since 512 words exist in the addresses of a row and 160 words are accessed for a raster, this row address change is done at largest once. And at largest, a refresh cycle is also included in the transfer of a raster. The number of cycles required to access a raster entirely thus becomes 322 to 326 cycles. The accessing time becomes 16.1 msec to 16.3 msec. The average access time is 16.2 msec. The time to occupy the 1st bus per second becomes a value obtained by multiplying the access time per raster by the number of rasters on a screen (number of pixels in the vertical direction) and further multiplying the result by the vertical synchronous frequency. The number of rasters on a screen is 240. Since the LCD 005 conforms to the TV NTSC system, the vertical synchronous frequency is 59.9 Hz. From these properties, the time to occupy the 1st bus per second becomes 233 msec. When it is converted to the rate of bus occupation, it will become 23.3%. We will return to Figure 1 again, explaining the vertical scanning of the frame buffer 020. Transferring pixel data of a raster from the frame buffer 020 to the display control unit 004, the DMAC 011 notifies the CPU 010 of the end of the transfer through the 2nd interrupt signal 110. The CPU 010 executes the display control procedure 130 stored in the 3rd memory 013 as an interrupt processing. Next, how each unit is synchronized with others will be explained below. The display control signal generation means 012 fetches the system clock 160 to generate the horizontal synchronous signal 124, the horizontal display period signal 121, the vertical synchronous signal 123, and the vertical display period signal 120 used to control the horizontal or vertical scanning of the LCD 005. The CPU 010 sets the cycles, phases, and pulse widths of those 4 PWM signals under the control of the application program. The horizontal synchronous signal 124 is used to indicate the end and the start of a horizontal scanning of the LCD 005. The horizontal display period signal 121 is used to indicate the positions to start and end the display in each horizontal scanning of the LCD 005. The vertical synchronous signal 123 is used to indicate the end of a vertical scanning of the LCD 005 and the start of the next vertical scanning. The vertical display period signal 120 is used to indicate the positions to start and end the display in each vertical scanning of the LCD 005. The display area of the LCD 005 is determined when the horizontal direction display period indicated by the horizontal display period signal 121 match with the vertical direction display period indicated by the vertical display period signal 120. The display control signal generation means 012, synchronized with the vertical display period signal 120, requests the CPU 010 for an interrupt processing. The request is issued at both the start and end of a vertical display period. In this embodiment, an interrupt processing is requested with the 1st interrupt signal 125. Receiving this interrupt request, the CPU 010 starts up the drawing procedure 131 or display control procedure 130 stored in the 3rd memory 013. With this, the distortion to occur on the LCD 005 screen during drawing or displaying graphic elements can be reduced. Concretely, the said display area is changed by the display control procedure 130 according to the interrupt processing request issued at the end of a vertical display period. This can suppress the distortion like borderlines to occur on the screen of the LCD 005 during smooth scrolling. And according to the interrupt request issued at the start of a vertical display period, a draw processing whose vertical scanning speed is slower than that of the LCD 005 vertical scanning is started up. With this, unsightly imperfect patterns can be eliminated during drawing on the screen of the LCD 005. The filling-in processing for polygons and the copy processing for rectangular areas that belong to the single function procedure 132 are uncluded in such drawing processings. In this embodiment, starting up those drawing processings is synchronized with vertical scanning, as well as the procedures are set so that the scanning in those drawing processings may be done in the same direction of the vertical scanning of the LCD 005. As a result, the scanning in drawing processings never passes the vertical scanning of the LCD 005, and the vertical scanning in drawing processings is not passed by the vertical scanning of the LCD 005. The basic configuration of this invention is as mentioned above. Hereafter, the configuration to realize the 1st purpose of this invention will be explained more in detail. Figure 4 shows an embodiment of the microcomputer used in this invention that has reduced the graphics computer in size and shortened the drawing time. In Figure 4, only the configuration items necessary to realize the 1st purpose of this invention are selected from the basic configuration shown in Figure 1 for more detailed explanation. The graphics computer used to achieve the 1st purpose of this invention comprises a microcomputer 001; a 16-bit data width main memory 002 that integrates frame buffers 020; and a display control unit 004. The display control unit 004 stores two or more pixel data items transferred from the main memory in the serializer 043 temporarily and converts them pixel by pixel to color data in the color pallet 044 to output them to the LCD 005 as RGB signals 040. The display control unit 004 generates vertical synchronous signals and horizontal synchronous signals from the display synchronization control circuit and outputs them to the LCD 005, then synchronizes with horizontal synchronous signals generated from itself to output the DMA request signal 042 to request the microcomputer 001 to transfer data for a raster in the horizontal direction. The microcomputer 001 comprises a CPU 010, which is a computing means; a DMAC 011 that reads pixel data from the frame buffer 020 and transfers the data to the serializer 043 during a display processing; and the 2nd data bus 170 and the 2nd address bus 171, which are internal buses of the microcomputer 001. The 2nd data bus 170 and the 2nd address bus 171 are 32 bits in width respectively. They are elements of the 2nd bus 017 shown in Figure 1. The 2nd address bus 171 is connected to the 1st address bus 071, which is an external bus, through the effective address generator 152 and the address multiplexer 153 to exchange data with the main memory 002 and the display control unit 004. The 1st address bus 071 is equivalent to the lower 25 bits of the 2nd address bus 171. The 1st data bus 070 and the 1st address bus 071 are elements of the configuration of the 1st bus 007 shown in Figure 1. Decoded selection signals 155 and 156 are output to the upper 7 bits of each address. The 2nd data bus 170 is connected to the 1st data bus 070 through a bus buffer or transceiver. The 1st data bus 070 is 32 bits in width. The said bus buffer or transceiver are omitted in Figure 1, since they are not concerned with the essential qualities of this invention. Data is exchanged among the main memory 002, the display control unit 004, and the microcomputer 001 through the 1st data bus 070 and the 1st address bus 071. Speeding up of the access to the frame buffer 020 and the general-purpose area 021 is achieved by the memory control register 151 and the effective address generator 152 incorporated in the microcomputer. The memory control register 151 stores the 1st information TA that specifies the frame buffer 020. This 1st information TA is set by the CPU 010 and transferred to the effective address generator 152 to be compared with the field B of the 2nd address bus 171 for the size in the 1st area judgment. When the address field A indicates the specified space connected to the main memory 002 and the address field B is smaller than the 1st information TA, the address is judged to be the address of the frame buffer 020. At this time, the field C and the field D in the address are exchanged. The number of bits in the address field A is 7, so the maximum capacity of the main memory 002 becomes 33554432 bytes (225). The number of bits in the field B is 9, so the main memory 002 can be set for the frame buffer 020 in units of 65536 bytes (216). The sizes of the fields C and D, as well as the size of the field E are determined by the 2nd information YS and the 3rd information XS of the memory control register 151. Concretely, both the 2nd information YS and the 3rd information XS assign the number of bits necessary for each field. The number of bits in the fields C, D, and E is variable. Thus, the fields B and C may be overlapped with each other in some cases. If the number of overlapped bits is assumed to be n bits (n=YS+YS+X-16), the minimum unit of the frame buffer becomes 216+n practically. When the fields C and D used for the 1st area judgment are exchanged, the row addresses of the memory unit are arranged like a 2-dimensional block in the frame buffer while they are kept like a 1-dimensional block in the general purpose area 021. The address multiplexer 153 multiplexes and outputs row and column addresses to the DRAM (main memory 002) according to the 4th information MXC stored in the memory control register 151. At this time, the address multiplexer 153 judges whether or not the address field A is a space in the specified memory 002 and multiplexes the addresses only in the space in which the main memory 002 is put. With this, only the frame buffers in the main memory 002 can be arranged like a 2-dimensional block, allowing the access to pixels during drawing to be speeded up. Next, an embodiment in which the frame buffer 020 is provided to the conventional main memory will be explained using Figure 5. In this embodiment, one byte is assigned per pixel in the frame buffer 020. The number of pixels in the X direction is 1024, while the number of pixels in the Y direction is 512. When viewing it from the CPU 010, logical addresses are increased in the X direction. As the logical addresses are increased in the Y direction, they are increased in units of 1024 bytes, which is the memory width. In this embodiment, the main memory 002 uses two DRAMs (256 words x 16 bits each) to secure a space of 1 MB. In this case, since 2 KB exist in the addresses of a row, a consecutive access to 2 pixels in the Y direction can be made faster. However, a line in graphics data is about 20 pixels in size on average, addresses of two or more rows are accessed for drawing a line. The addressing would be slow when no measures are taken to speed it up. To speed it up, therefore, addresses of rows are mapped physically as shown in Figure 6. As a result, a line comprising up to 32 pixels in the Y direction can be stored within a row, improving the processing speed. In the X direction, 64 pixels are provided continuously. The performance of this invention can also be secured for filling in a rectangle to be scanned horizontally. In this embodiment, the 1st information TA stored in the memory control register 151 is 8, and the 2nd information YS is 5, and the 3rd information XS is 6. This setting is suitable for drawing a line whose direction is free, but for an application program that generates many polygons that are to be filled in, the 3rd information XS should be set greater to improve the speed of access to pixels for filling in. In other words, it is better to change the physical address mapping according to the subject application program. In this invention, the 2nd information YS and the 3rd information XS can be changed so that the configuration of frame buffers can be changed most appropriately to the subject application program even when the same microcomputer is used. Next, the relationship among the DMAC 011, the effective address generator 152, and the address multiplexer 153 will be explained using Figure 7. Since the 2nd data bus 170 is occupied to transfer rasters from the frame buffer 020 to the display control unit 004, the data bus should be as shorter as possible. For this purpose, as shown in the operation of the 1st data bus 070 in Figure 4, transfer of rasters is concentrated. Furthermore, the single address mode DMA transfer that reads from memory and writes data in I/O is executed in the same memory cycle is used. If the DMAC 011 that executes this DMA transfer exists outside the microcomputer 001, the DMAC 011 must generate 2-dimensional addresses. For this purpose, both the effective address generator 152 and the address multiplexer 153 must be incorporated in the DMAC 011. This makes the hardware increase. And to avoid this, the DMAC 011 has been incorporated in the microcomputer 001 and the effective address generator 152 and the address multiplexer 153 are designed so that they can be shared. Figure 8 shows another embodiment of this invention. A memory control register group 157 is provided in this embodiment. The register group 157 is used to control blocking of addresses in two or more areas. Control registers 1570, 1571, 1572, and 1573 are provided separately in 4 different areas (0 to 3). The effective address generator 152 and the address multiplexer 153 are united into the address converter 158. Figure 9 shows another embodiment of this invention, in which an address converter 158 that uses the table lookup function is used instead of the address converter 158 shown in Figure 8. Next, an embodiment to achieve the 2nd purpose of this invention will be explained below. The high speed line drawing system in this embodiment belongs to the single function procedure 132 of the draw procedures 131 stored in the 3rd memory 013. EXPLANATION OF NUMERALS 001 Microcomputer 002 Main Memory 003 2nd Memory 004 Display Control Unit 005 LCD 006 External memory 007 1st Bus 010 CPU 011 DMAC 012 Display Control Signal Generation Means 013 3rd Memory 014 4th Memory 015 SBC 016 Oscillator 017 2nd Bus 160 System Clock 110 2nd Interrupt Signal 125 1st Interrupt Signal 120 Vertical Display Period Signal 121 Horizontal Display Period Signal 123 Vertical Synchronous Signal 124 Horizontal Synchronous Signal 100 Bus Arbitration Signal 042 DMA Request Signal 150 DMA Write Interrupt 030 Graphic Data 031 Application Program 020 Frame Buffer 040 RGB 041 Synchronous Signal 130 Display Control Procedure 131 Drawing Procedure 132.. Single Function Drawing Procedure 133 High Speed Line Drawing Procedure 134 Multivalue Expansion Procedure 135 Other Drawing Procedure 136 Multifunction Drawing Procedure 170 2nd data Bus 171 2nd Address Bus 151 Memory Control Register 152 Effective Address Generation Unit 153 Address Multiplexer 070 1st Data Bus 071 1st Address Bus 021 General-Purpose Area 043 Serializer 044 Color Pallet 045 Display Synchronization Control Circuit 155 Select Signal 156 Select Signal 157 Memory Control Register Group 158 Address Converter 350 Address Converter

Claims: A microcomputer (001) provided with: a CPU (010) that computes data to be displayed on a raster scanning type display unit, first address bus (071) connected to memories (002) used to store said data, a second address bus (171) connected to said CPU and used to specify the destination of the said data, registers (151, 1570, 1571, 1573) used to store address conversion data (MXC, TA, YS, XS) set by said CPU and an address converter (158) that converts addresses from said second address bus and outputs them to said first address bus; characterised in that : said address converter (158) is provided with first information (TA) that specifies an area in the said memory to which to convert addresses according to the address conversion information stored in said registers; said address converter (158) converts addresses according to said first information (TA), when addresses are generated on the second address bus (171). The microcomputer (001) described in Claim 1, wherein said address converter (158), is further provided with second information (YS) used to distinguish the second field (C) of the YS bit from the third field (D) and third information (XS) used to obtain the first field (E) of the XS bit from the lower part of the address according to the address conversion information stored in said registers; and said address converter exchanges said second and said third fields in order to convert addresses. The microcomputer described in Claim 2, wherein said address converter exchanges the second and third fields when an address is generated on said second address bus according to said first information.

Inventors: KATSURA KOYO, MINAMI RIKA, OHBA MAMORU, WATANABE MITSURU, KATSURA, KOYO, MINAMI, RIKA, OHBA, MAMORU, WATANABE, MITSURU
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1994
Main classification: G06T11
IPC codes: G06T11