SRAM memory structure and manufacturing method thereof

Abstract: The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors (Q 3 , Q 4 ), a pair of driver transistors (Q 1 , Q 2 ), and a pair of load transistors (Q 5 , Q 6 ), wherein the impurity concentration profile and peaks are different for the driver transistors and the access transistors.

Description: The present invention relates generally to semiconductor memory devices and manufacturing methods thereof, and more specifically, to a memory structure for SRAM (Static Random Access Memory) and a manufacturing method thereof. Conventionally, SRAM is known as one kind of semiconductor memory device. Fig. 42 is an equivalent circuit diagram showing one memory cell of a conventional SRAM. Referring to Fig. 42, the memory cell uses a p type MOS (Metal Oxide Semiconductor) as a load, and is formed of six transistors. More specifically, a pair of driver transistors (for driving) Q 1 and Q 2 (n type MOS transistors) and a pair of load transistors Q 5 and Q 6 (p type MOS transistors) are connected with each other to constitute a flip-flop circuit. The source regions 110 and 111 of the pair of load transistors Q 5 and Q 6 are connected to a power supply V cc . The source regions of driver transistors Q 1 and Q 2 are connected to GNDs 112 and 113. A pair of access transistors Q 3 and Q 4 (n type MOS transistors) are connected to storage nodes 114 and 115, respectively. A bit line 107 is connected to one of the source/drain regions of access transistor Q 3 . A bit line 108 is connected to one of the source/drain regions of access transistor Q 4 . The gate electrodes of access transistors Q 3 and Q 4 are connected to a word line 109. Now, a conventional SRAM memory cell structure will be described by way of illustrating a document (International Electron Device Meeting 1991 Technical Digest pp. 481 - 484). Figs. 43A and 43B are plan views showing a conventional SRAM memory cell structure divided into two stages from the bottom layer. More specifically, Fig. 43A illustrates driver transistors Q1 and Q2 and access transistors Q 3 and Q 4 formed on a substrate, while Fig. 43B illustrates thin film transistors (TFT) Q 5 and Q 6 . Fig. 44 is a schematic sectional view taken along line G-G in Figs. 43A and 43B. Referring to Figs. 43A, 43B, and 44, in the conventional memory cell, a pair of driver transistors Q 1 and Q 2 and a pair of access transistor Q 3 and Q 4 are formed at a main surface of a p type well 120. Driver transistor Q 1 has a drain region 125a and a source region 125b opposing to each other with a channel region 125c therebetween, and a gate electrode 124. Driver transistor Q 2 has a drain region 126a and a source region 126b - opposing to each other with a channel region 126c therebetween, and a gate electrode 123. Access transistor Q 3 has a pair of source/drain regions 125d opposing to each other with a channel region 125e therebetween, and a gate electrode 121. Access transistor Q 4 has a pair of source/drain regions 126d opposing to each other with a channel region 126e therebetween, and a gate electrode 122. These transistors are formed of n type MOS transistors having source/drain regions formed on the main surface of p type well 120. The gate electrode 123 of driver transistor Q 2 is connected to the source/drain region 125d of access transistor Q 3 and the drain region 125a of driver transistor Q 1 through a contact portion 123a. The gate electrode 124 of driver transistor Q 1 is connected to the source/drain region 126d of access transistor Q 4 and the drain region 126a of driver transistor Q 2 through a contact portion 124a. The drain region 143a of load transistor Q 5 and the gate electrode 142 of load transistor Q 6 are connected to the gate electrode 124 of driver transistor Q 1 through a contact portion 143d. The drain region 144a of load transistor Q 6 and the gate electrode 141 of load transistor Q 5 are connected to the gate electrode 123 of driver transistor Q 2 through a contact portion 144d. A tungsten silicide layer 135 to be a GND line is formed at the position of an intermediate layer between driver transistor Q 1 , Q 2 and access transistor Q 3 , Q 4 , and load transistors Q 5 , Q 6 . A bit line 139 is connected to the source/drain region 125d of access transistor Q 3 with a plug layer 137 therebetween. The other bit line (not shown) is connected to the source/drain region 126d of access transistor Q 4 with a plug layer therebetween as in the case of bit line 139. Load transistors Q 5 and Q 6 each formed of a thin film transistor have gate electrodes 141 and 142 lying under channel regions 143c and 144c, respectively, and each constitutes a so-called bottom gate type transistor. Fig. 45 is a sectional view showing a typical cross section of a thin film transistor used for load transistors Q 5 and Q 6 . Referring to Fig. 45, the thin film transistor includes channel region 144c, drain region 144a, and source region 144b formed in a semiconductor layer such as of polycrystalline silicon. Gate electrode 142 is formed at a position opposing to channel region 144c with an insulating layer therebetween. Fig. 46 is a graphic representation showing the current characteristic of the above-described thin film transistor. In Fig. 46, Vd represents drain voltage, Vg gate voltage, and Id drain current. In such an SRAM, in order to increase the integration density of memory cells, an area occupied by each memory cell on plane must be reduced. More specifically, the area on plane occupied by driver transistors Q 1 , Q 2 , access transistors Q 3 , Q 4 , and load transistors Q 5 , Q 6 must be reduced. The above-described conventional memory cell is however encountered with the following two disadvantages in increasing integration density. The first disadvantage is instability in operation at the time of reading. Now, this disadvantage will be described in more detail. Figs. 47A and 47B are diagrams showing an equivalent circuit of the memory cell shown in Fig. 42 by dividing it into two inverter circuits related to reading operation. Referring to Figs. 47A and 47B, load transistors Q 5 and Q 6 are not illustrated, because current flowing across them is significantly small. The reading characteristic of the memory cell is produced from voltage change at the storage node thereof, with a bit line and a word line fixed to Vcc, while changing the gate voltage of a driver transistor (voltage at the storage node of the other side). Fig. 48 is a graphic representation showing the reading characteristic of the above-described SRAM. Referring to Fig. 48, the abscissa represents the voltage of storage node 115, while the ordinate represents the voltage of storage node 114. Curve α 1 represents the voltage change characteristic of storage node 114 when the voltage of storage node 115 is changed. Curve γ 1 represents the voltage change characteristic of storage node 115 when the voltage of storage node 114 is changed. Curves α 1 and γ 1 cross at three points P 1 , P 2 , and P 3 . Point P 3 corresponds to storage node 114 storing "High" data, while point P 1 corresponds to storage node 115 storing "High" data. Point P 2 is an unstable point, and voltage does not stop at point P 2 at the time of reading. In the figure, a region defined by circle h 1 is a so-called "memory cell eye". Generally, the larger the memory cell eye is, the more stable will be the reading operation. The memory cell eye is discussed in Evert Seevinck et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-22, No. 5, October 1987 pp. 748 - 754, and H. Shinohara et al., VLSI '82, pp. 106 - 107. There are several ways of enlarging a memory cell eye, and two approaches will be described in the following. The first method is to enlarge the driving capability ratio β of driver transistor and access transistor (in other words driving capability of driver transistor/driving capability of access transistor).- Fig. 49 is a graphic representation showing the reading characteristic when the driving capability ratio β is increased with respect to the case shown in Fig. 48. Referring to Fig. 49, the memory cell eye is enlarged from circle h 1 to circle h 2 . The second approach is to reduce threshold voltage V th of access transistor. Vcc- 1 (distance between Vcc and  1 ) and Vcc- 2 (distance between Vcc and  2 ) in Fig. 48 correspond to the threshold voltages V th of access transistors Q 3 and Q 4 , respectively. It is noted that  1 and  2 are High level voltages of the outputs of the respective inverters. Fig. 50 is a graphic representation showing the characteristic when the threshold voltage V th of access transistor is reduced with respect to the case of Fig. 48. Referring to Fig. 50, if the threshold voltages V th of access transistors Q 3 and Q 4 are reduced to Vcc- 3 and Vcc- 4 , respectively, the memory cell eye is enlarged from circle h 1 to circle h 3 . Referring to Fig. 43A, a conventional approach for enlarging a memory cell eye is to increase the gate widths W D of driver transistors Q 1 and Q 2 , or to reduce the gate widths W A of access transistors Q 3 and Q 4 . This is because the driving capability of a transistor is substantially proportional to its gate width. To increase the gate width W D of a driver transistor however hinders the memory cell from being reduced in size, and therefore is not preferable in view of high intensity integration. Meanwhile, to reduce the gate width W A of an access transistor gives rise to increase in the threshold voltage V th of the access transistor due to the narrow channel effect. Therefore, the memory cell eye is reduced conversely as described above, resulting in unstable reading operation. As described above, such a conventional SRAM memory cell structure can not provide increase in integration density while maintaining operation stability. The second disadvantage is due to the limits of manufacture by photolithography techniques. Now, the limits will be described in more detail. Load transistors Q 5 and Q 6 employed in the conventional SRAM memory cell structure shown in Figs. 43A and 43B are both bottom gate type thin film transistors. Referring to Fig. 43B in particular, the gates 141 and 142 of load transistors Q 5 and Q 6 are formed of one layer. More specifically, when load transistors Q 5 and Q 6 are formed, a conductive layer is formed first, and then gate electrodes 141 and 142 are formed from the conductive layer by patterning utilizing a photolithography technique or the like. In the present state of the art, a minimum manufacturing size in patterning by means of photolithography is about 0.35µm and therefore the size of each portion of gate electrodes 141 and 142 patterned by means of photolithography (L 3 and L 4 , for example) can not be smaller than 0.35µm. The source/drain regions of load transistor Q 5 , Q 6 and layers 143, 144 to be channel regions are both also formed of one layer. Accordingly, the size of each portion of layers 143 and 144 (L 5 for example) can not be smaller than 0.35µm either. As described above, with the limits in the manufacture utilizing photolithography techniques, it is difficult to reduce the occupied area of load transistors Q 5 and Q 6 on plane, and the conventional SRAM memory cell structure is not statable for high density integration in this regard as well. The structure of load transistors Q 5 , Q 6 which is less susceptible to the limits in the manufacture by photolithography techniques as described above is disclosed in Japanese Patent Laying-Open No. 3-34569. Meanwhile, Fig. 51 is a plan view schematically showing the structure of a load transistor in Japanese Patent Laying-Open No. 3-34569. Referring to Fig. 51, the pair of load transistors are formed of two polycrystalline silicon layers 301 and 303 piled upon each other with an insulating film (not shown) therebetween. A drain region 301a and a source region 301b are formed with a channel region 301c therebetween in polycrystalline silicon layer 301. A drain region 303a and a source region 303b are formed with a channel region 303c therebetween in polycrystalline silicon layer 303. A drain region 303a to be a gate electrode is present on the underlying channel region 301c with an insulating film therebetween. Drain region 301a to be a gate electrode is present under the overlying channel region 303c with the insulating film therebetween. Thus, in the structure of the pair of load transistors, one constitutes a bottom gate type transistor and the other a top gate type transistor. The drain region of one transistor uses the gate electrode of the other transistor. Therefore, the limits in the manufacture by photolithography described above are reduced. The load transistor structure is therefore suitable for high density integration. The drain region 301a of the underlying polycrystalline silicon film 301 is not covered with overlying polycrystalline silicon film 303. Accordingly, an impurity can be implanted into drain region 301a in a self-aligned manner. In the load transistor structure, however, channel regions 301c and 303c both has an approximately L-shape. If, for example, misregistration of a mask at the time of patterning polycrystalline silicon thin film 303 causes the overlying polycrystalline silicon thin film 303 to be shifted with respect to the underlying polycrystalline silicon thin film 301 in the direction indicated by arrow J or K, the sizes L 6 , L 7 , W 1 , and W 2 of the portions of channel regions 301c and 303c can easily be changed. Fig. 52 is a plan view schematically showing how the dimension of a channel region is changed by misregistration of a mask. Referring to Fig. 52, the load transistor pair structure shown in Fig. 51 has its channel region dimension easily changed. Accordingly, a load transistor having a desired characteristic can not be obtained. It is also difficult to provide stable operation. From Patent Abstracts Of Japan, vol. 016, no. 138 (E-1186), 7 April 1992, & JP-A-04 000757, 6 January 1992, a semiconductor memory device according to the preamble of claim 1 is known. The semiconductor memory device has different impurity concentrations for the channel regions of the access and driver transistors. Patent Abstracts Of Japan, vol. 016, no. 263 (E-1216), 15 June 1992, & JP-A-04 061377, 27 February 1992, discloses a semiconductor memory device having a reduced impurity concentration in a lower part of the channel region of an access transistor, wherein this impurity concentration is lower than the corresponding impurity concentration in a lower part of the channel region of a driver transistor. Patent Abstracts Of Japan, vol. 012, no. 124 (E-601), 16 April 1988, & JP-A-62 249474, 30 October 1987, discloses a semiconductor memory device having a deeper junction depth of the source/drain regions of driver transistors than the corresponding junction depth of access transistors. As described above, in load transistors employed for a conventional SRAM meory cell structure, it was not possible to provide a structure suitable for high intensity integration while maintaining stable operation. SUMMARY OF THE INVENTION It is an object of the invention to provide an SRAM memory cell structure suitable for high density integration. Another object of hte invention is to produce the size of an SRAM memory cell structure while maintaining stability in the operation of the SRAM. Yet another object of the invention is to provide an SRAM memory cell structure which is less restricted by the limits of dimension in the manufacture by photolithography, and permits stable operation. A still further object of the invention is to provide a method of manufacturing an SRAM memory cell structure suitable for high intensity integration. According to the present invention, these objects are achieved by a semiconductor memory device as defined in claim 1 and a method of manufacturing a semiconductor memory device as defined in claim 2, respectively. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Fig. 1 is a sectional view schematically showing an SRAM memory cell structure, useful for understanding the invention, in a cross section corresponding to Fig. 44; Fig. 2A is a schematic sectional view showing the structure of an access transistor in region A in Fig. 1 being enlarged; Fig. 2B is a schematic sectional view showing a driver transistor taken along line B-B in Fig. 1; Figs. 3A-8A and Figs. 3B-8B are cross sectional views schematically showing in the order of steps methods of manufacturing an access transistor and a driver transistor employed for the SRAM memory cell structure of Fig.1; Figs. 9A and 9B are sectional views showing manufacturing methods of the access transistor and driver transistor employed for the SRAM memory cell structure of Fig.1 when the material of the gate insulating films are changed; Figs. 10A and 10B are sectional views schematically showing the structure of the access transistor and driver transistor corresponding to Figs. 9A and 9B; Figs. 11A and 11B are sectional views schematically showing the access transistor and driver transistor employed for the SRAM memory cell structure of Fig.1 when the materials of the gate insulating films are changed; Figs. 12A-14A and Figs. 12B-14B are sectional views schematically showing in the order of steps methods of manufacturing the access transistor and driver transistor corresponding to Figs. 11A and 11B; Figs. 15A and 15B are sectional views schematically showing the structure of an access transistor and a driver transistor each having a gate insulating film formed of a single layer useful for understanding the invention; Figs. 16A and 16B are sectional views showing manufacturing methods of the access transistor and driver transistor employed for the SRAM memory cell structure of Fig.1 when the materials of the gate insulating films are changed; Figs. 17A and 17B are sectional views schematically showing the structure of the access transistor and driver transistor corresponding to Figs. 16A and 16B; Figs. 18A and 18B are sectional views schematically showing the structure of an access transistor and a driver transistor; Fig. 19 is a representation showing an impurity concentration distribution along X 0 -X 1 in Fig. 18A and an impurity concentration distribution along Y 0 -Y 1 in Fig. 18B in a comparison example; Fig. 20 is a representation showing an impurity concentration distribution along X 0 -X 1 in Fig. 18A and an impurity concentration distribution along Y 0 -Y 1 in Fig. 18B according to an embodiment of the invention; Figs. 21A and 21B and Figs. 21C and 21D are representations illustrating that threshold voltage V th is more reduced in the embodiment of the invention than the comparison example when a backgate effect is provided; Figs. 22A-24A and Figs. 22B-24B are sectional views schematically showing in the order of steps methods of manufacturing an access transistor and a driver transistor employed for an SRAM memory cell structure according to the embodiment of the invention; Figs. 25A and 25B are plan views schematically showing the structure of an access transistor, a driver transistor, and a load transistor employed for another SRAM memory cell structure; useful for understanding the invention Figs. 26A and 26B are schematic sectional views taken along lines C-C and D-D in Figs. 25A and 25B; Figs. 27A-31A and Figs. 27B-31B are sectional views corresponding to Figs. 26A and 26B schematically showing in the order of steps a method of manufacturing a load transistor employed for the SRAM memory cell structure of Figs. 25A and 25B; Fig. 32 is a view for use in illustration of an advantage in the load transistor employed for the SRAM memory cell structure of Figs. 25A and 25B; Fig. 33 is a plan view schematically showing the structure of a load transistor employed for another SRAM memory cell structure; useful for understanding the invention Fig. 34A and 34B are schematic sectional views taken along lines E-E and F-F in Fig. 33; Figs. 35A-39A and Figs. 35B-39B are sectional views corresponding to Fig. 34A and 34B schematically showing in the order of steps a method of manufacturing the load transistor employed for the SRAM memory cell structure of Fig. 33; Fig. 40 is a plan view schematically showing the structure of a conventional load transistor for two memory cell regions; Fig. 41 is a plan view schematically showing the structure of a load transistor employed for another SRAM memory cell structure for two memory cells; useful for understanding the invention Fig. 42 is an equivalent circuit diagram showing a general SRAM; Figs. 43A and 43B are plan views schematically showing a driver transistor, an access transistor, and a load transistor employed for a conventional SRAM memory cell structure; Fig. 44 is a sectional view taken along line G-G in Figs. 43A and 43B; Fig. 45 is a sectional view showing a thin film transistor forming a conventional load transistor; Fig. 46 is a representation showing the characteristic of the thin film transistor forming the conventional load transistor shown in Fig. 45; Figs. 47A and 47B are equivalent circuit diagrams for use in illustration of reading operation from a conventional SRAM memory cell; Fig. 48 is a representation showing characteristic curves in reading of data from a conventional memory cell; Fig. 49 is a representation showing characteristic curves in reading data showing the state of memory cell eyes when the driving capability ratio is increased; Fig. 50 is a representation showing characteristic curves in reading data showing the state of memory cell eyes when the threshold voltage V th of an access transistor is reduced; Fig. 51 is a plan view schematically showing the structure of a load transistor disclosed in a published document; and Fig. 52 is a representation for use in illustration of a disadvantage when mask misregistration is generated in the load transistor shown in Fig. 51. DESCRIPTION OF A PREFERRED EMBODIMENT Now, a preferred embodiment of the invention will be described in conjunction with the accompanying drawings. Fig. 1 is a schematic cross sectional view showing in a cross section a memory cell structure for an SRAM corresponding to Fig. 44. Fig. 2A is an enlarged cross sectional view showing the structure of an access transistor indicated by region A in Fig. 1, while Fig. 2B is a schematic cross sectional view showing a driver transistor taken along line B-B in Fig. 1. Referring to Figs. 1, 2A and 2B, a pair of driver transistors Q 1 , Q 2 , and a pair of access transistors Q 3 , Q 4 are formed on a main surface of a p well 20. Driver Q 1 has a drain region 25a and a source region 25b, and a gate electrode 23. Driver transistor Q 2 has a drain region 26a, a source region 26b, and a gate electrode 23. Driver transistors Q 1 and Q 2 have a gate insulating film formed of a silicon oxide film 27a and a silicon nitride film 27b piled thereon. Access transistor Q 3 has a pair of source/drain regions 25d and a gate electrode 21. Access transistor Q 4 has a pair of source/drain regions 26d and a gate electrode 22. Access transistors Q 3 and Q 4 have a gate insulating film of a single layer silicon oxide film 27c. The memory cell structure of the SRAM of Fig.1 is substantially identical to the memory structure of the conventional SRAM shown in Figs. 43A, 43B, and 44 except for the structure of the above-described driver transistors Q 1 , Q 2 , and access transistors Q 3 , Q 4 , and therefore description thereof is omitted. In the memory cell structure of the SRAM of Fig.1, materials having different dielectric constants are used for the gate insulating films of driver transistors Q 1 , Q 2 , and the gate insulating film of access transistors Q 3 , Q 4 . Therefore, the driving capability ratio β of driver transistor to access transistor can advantageously be increased. Hereinafter, this will be described by referring to Mitsumasa Koyanagi, SUBMICRON DEVICE I Maruzen Kabushiki Kaisha, pp. 4 - 8. The driving capability of a transistor is given as follows: W L · µ eff · C IN where W represents the gate width of a transistor, L the gate length, µ eff the effective degree of movement of electrons on the surface, and C IN the capacitance of the gate insulating film per unit area. C IN is given by the following expression: C IN = ε IN · ε 0 t IN where ε 0 is a vacuum dielectric constant, ε IN is the relative dielectric constant of the gate insulating film, t IN is the thickness of the gate insulating film. As described, the driving capability ratio β is represented as "driving capability of driver transistor"/"driving capability of access transistor". Accordingly, one method of increasing the driving capability ratio β is to reduce the driving capability of an access transistor relative to the driving capability of a driver transistor. Reducing the relative dielectric constant of the gate insulating film of access transistors Q 3 , Q 4 would reduce the driving capability of the access transistor from expressions (1) and (2). From expressions (1) and (2), as the relative dielectric constant ε IN of a gate insulating film is increased, the driving capability of the transistor is increased, while the relative dielectric constant ε IN of a gate insulating film is reduced, the driving capability of the transistor is reduced. Accordingly, if a material having a smaller dielectric constant than the gate insulating film of driver transistors Q 1 and Q 2 is used for the gate insulating film of access transistors Q 3 and Q 4 , the driving capability of access transistors Q 3 , Q 4 relative to driver transistors Q 1 , Q 2 can be reduced. As a result, the driving capability ratio β can be increased. In contrast, from the above-described expressions (1) and (2), as another approach the same material is used for the gate insulating film of driver transistors Q 1 , Q 2 , and the gate insulating film of access transistors Q 3 , Q 4 , only their film thicknesses t IN are made different, and then the driving capability ratio β would be increased as a result. This approach is disclosed in Japanese Patent Laying-Open No. 63-211751. In this prior art document, only silicon oxide films are used for the gate insulating films of both of access transistors Q 3 , Q 4 and driver transistors Q 1 , Q 2 . The thickness t IN1 of the gate oxide film of access transistors Q 3 , Q 4 is formed larger than the thickness t IN2 of the gate oxide film of driver transistors Q 1 , Q 2 , and therefore a larger driving capability ratio β is obtained. According to the approach disclosed in the above-described prior art document, however, the larger the driving capability ratio β is to be, the larger will be difference in the thicknesses (t IN1 -t IN2 ) of the gate oxide films of driver transistors Q 1 , Q 2 and access transistors Q 3 , Q 4 . Accordingly, difference in potential between the gate electrodes of driver transistors Q 1 , Q 2 and access transistors Q 3 , Q 4 is large. Therefore, failures in a pattern shape are encountered in patterning the upper layer of the gate electrodes by means of photolithography. In this SRAM, by arbitrarily selecting materials having different dielectric constants for the gate insulating films, the film thickness of the gate insulating films of access transistors Q 3 , Q 4 , and driver transistors Q 1 , Q 2 can be set to desired values. Accordingly, the film thicknesses of the gate insulating films of access transistors Q 3 , Q 4 , and driver transistors Q 1 , Q 2 can be set identical. In such a case, failures in patterns on the upper layer of the gate electrodes by photolithography will hardly be encountered. More specifically, as illustrated in Figs. 1, 2A and 2B, the gate insulating film of access transistors Q 3 , Q 4 remains to be silicon oxide film 27c, and a stacked structure of silicon oxide film 27a and silicon nitride film 27b is used for the gate insulating film of driver transistors Q 1 , Q 2 . In this case, the relative dielectric constant of the silicon oxide film ε OX ≒ 3.8-3.85, while the relative dielectric constant of the silicon nitride film ε N ≒ 7 which is about twice as large as that of the silicon oxide film. The gate insulating film for driver transistors Q 1 , Q 2 has a higher dielectric constant than access transistors Q 3 , Q 4 . As described above, in this SRAM, the driving capability ratio β can effectively be increased by controlling the material and thickness of the insulating film. Now, a manufacturing method will be described by way of illustrating driver transistor Q 2 and, access transistor Q 3 in Figs. 1, 2A and 2B. Figs. 3A-8A and Figs. 3B-8B are cross sectional views schematically showing, in the order of process, steps in a method of manufacturing an access transistor and a driver transistor used in the SRAM memory cell structure of Fig.1. Figs. 3A-8A show the access transistor, while Figs. 3B-8B show the driver transistor. Referring to Figs. 3A and 3B, a channel dope implantation is performed to p type well 20. A threshold voltage V th for the access transistor is determined by this implantation. Referring to Figs. 4A and 4B, photoresist 51a is formed on substrate 20 in an access transistor region (Fig. 4A), and then a channel dope implantation is performed to a driver transistor region (Fig. 4B) in well 20. These two channel dope implantations determine a threshold voltage for the driver transistor. Then, photoresist 51a is removed away. In the process shown in Figs. 3A and 3B, if an impurity is implanted to p type well 20 only into the access transistor region (Fig. 3A) covering only the driver transistor region (Fig. 3B) with resist for example and then implantation is performed to the driver transistor region (Fig. 4B) in p type well 20 by covering only the surface of access transistor region (Fig. 4A) with resist 51a in the process shown in Figs. 4A and 4B, the threshold voltage for the driver transistor can be determined by a single channel dope implantation. Referring to Figs. 5A and 5B, a thermal oxidation treatment is performed on the entire surface of the wafer, and a silicon oxide film 27a is formed on the surface of the wafer. A silicon nitride film 27b is formed on the entire surface of silicon oxide film 27a. Then, photoresist 51b is formed only on silicon nitride film 27b in the driver transistor region (Fig. 5B). Silicon nitride film 27b and silicon oxide film 27a in the access transistor region (Fig. 5A) are sequentially subjected to wet or dry etching utilizing photoresist 51b as mask. Then, photoresist 51b is removed away. Referring to Figs. 6A and 6B, the above-described etching exposes the surface of p type well 20 in the access transistor region (Fig. 6A.) Referring to Figs. 7A and 7B, a silicon oxide film 27c is formed on p type well 20 in the access transistor region (Fig. 7A) by a thermal oxidation treatment. In the thermal oxidation treatment, silicon nitride film 27b in the driver transistor region (Fig. 7B) is little oxidized. Accordingly, silicon oxide film 27c is formed only in the access transistor region (Fig. 7A). Referring to Figs. 8A and 8B, a polycrystalline silicon film is formed on the entire surface of the wafer 20. The polycrystalline silicon film, silicon nitride film 27b, and silicon oxide films 27c, 27a are sequentially etched away by means of photolithography and etching, and gate electrodes 21, 23, and gate insulating films 27c, 27a, 27b are formed. Then, an impurity is implanted using gate electrodes 21, 23, and an isolation oxide film (not shown) as mask. Thus, source/drain regions 25d, 26a, 26b as illustrated in Fig. 2 are formed. Assuming that the thickness of silicon oxide film 27c is t OX2 , the thickness of silicon oxide film 27a t OX1, and the thickness of silicon nitride film 27b t N , the driving capability ratio β can be increased provided that silicon oxide films 27a, 27c, and silicon nitride film 27b are formed satisfying the following expression: ε OX t OX2 < 1 t OX1 ε OX + t N ε N It is noted that in the above-described SRAM, silicon nitride film 27b is used as a material having a different dielectric constant, but any other insulating film may be used. In this case, not only silicon oxide film 27c is formed on substrate 20 in the access transistor region (Fig. 9A) as shown in Figs. 9A and 9B but also silicon oxide film 27d is formed on the surface of insulating film 27ba by a thermal oxidation treatment in the process as illustrated in Figs. 6A and 6B. Then, post-treatment as described above is performed to form access transistor Q 3 and driver transistor Q 2 shown in Figs. 10A and 10B. At the time, assuming that the thickness of insulating film 27ba is t a , dielectric constant ε a , and the thickness of silicon oxide film 27d t OX3 , each gate insulating film needs only be formed satisfying the following expression: ε OX t OX2 < 1 t OX1 ε OX + t a ε a + t OX3 ε OX Though in Figs. 2B and 10B the gate insulating film of the driver transistor is formed of a plurality of layers, it may be simply formed of a single insulating film layer having a dielectric constant different from the silicon oxide film. Furthermore, the device may be arranged so that the gate insulating film of the access transistor is formed of a plurality of layers, while the gate insulating film of the driver transistor is formed of a single layer. Referring to Figs. 11A and 11B, a stacked layer of a silicon oxide film 27e and a silicon nitride film 27f, for example, may be used for the gate insulating film of access transistor Q 3 , while a single layer of silicon oxide film 27g may be used for the gate insulating film of driver transistor Q 4 . A manufacturing method when access transistor Q 3 and driver transistor Q 4 are thus structured will be described. Figs. 12A-14A and Figs. 12B-14B are cross sectional views schematically showing in the order of the process a manufacturing method of the access transistor and driver transistor shown in Figs. 11A and 11B. Referring to Figs. 12A and 12B, a channel dope implantation is performed to p type well 20 in order to determine a threshold voltage for each transistor. This channel dope implantation is substantially identical to the process illustrated in conjunction with Figs. 3A and 3B, and Figs. 4A and 4B, and therefore the description thereof is omitted. After the channel dope implantation, a silicon oxide film 27e and a silicon nitride film 27f are sequentially stack upon each other on the entire surface of p type well 20. Photoresist 51c is formed on the surface of silicon nitride film 27f in an access transistor region (Fig. 12A). Silicon nitride film 27f and silicon oxide film 27e in a driver transistor region (Fig. 12B) are sequentially etched away using photoresist 51c as mask. Referring to Figs. 13A and 13B, this step of etching away exposes the surface of p type well 20 in the driver transistor region (Fig. 13B). Referring to Figs. 14A and 14B, a silicon oxide film 27g is formed on p type well 20 in the driver transistor region (Fig. 14B) by a thermal oxidation treatment. It is noted that since silicon nitride film 27f is hardly oxidized at the time, and little silicon oxide film is formed on silicon nitride film 27f in the access transistor region (Fig. 14A). Then, a polycrystalline silicon film is formed on the entire surface of the silicon substrate. The polycrystalline silicon film is patterned into a desired form, and then an impurity is implanted to form access transistor Q 3 and driver transistor Q 2 as illustrated in Figs. 11A and 11B. In the structure shown in Figs. 11A and 11B, assuming that the thickness of silicon oxide film 27e is t OX1 , the thickness of silicon nitride film 27f is t N , and the thickness of silicon oxide film 27g is t OX2 , each gate insulating film is formed satisfying the following expression: 1 t OX1 ε OX + t N ε N < ε OX t OX2 Also in Figs. 2A and 2B and Figs. 10A and 10B, the gate insulating film of a driver transistor is formed of a plurality of layers, it may simply be formed of a single layer of insulating film having a dielectric constant different from the silicon oxide film. Referring to Fig. 15, for example, gate insulating film 27k for access transistors Q 3 , Q 4 may be formed of a single layer of silicon oxide film and gate insulating film 27j for driver transistors Q 1 , Q 2 may be formed of a single layer of silicon nitride film. In this case, when the thickness t IN1 of silicon nitride film 27j and the thickness t IN2 of oxide film 27k are each 100Å, the dielectric constants of the silicon nitride film and the silicon oxide film are ε N ≒ 7 and ε OX ≒ 3.8, respectively, and the driving capability ratio β will be 7/3.8 ≒ 1.84 (times) as large. If another material having a dielectric constant different from the silicon oxide film is used in place of silicon nitride film 27f, the state shown in Figs. 16A and 16B is attained by a thermal oxidation treatment in the process shown in Figs. 13A and 13B. More specifically, silicon oxide film 27g is formed on p type well 20 in the driver transistor region (Fig. 15B) by thermal oxidation treatment, while silicon oxide film 27h is formed on the surface of an insulating film 27fa in the access transistor region. Then, post-treatment the same as described above is performed to form access transistor Q 3 and driver transistor Q 2 shown in Figs. 16A and 16B. In the structure as illustrated in Figs. 17A and 17B, assuming that the thickness of insulating film 27fa is t a , relative dielectric constant is ε a , and the thickness of silicon oxide film 27h is t OX3 , each gate insulating film is expected to be formed satisfying the following expression: 1 t OX1 ε OX + t a ε a + t OX3 ε OX < ε OX t OX2 In the above-described SRAM, silicon oxide films and silicon nitride films are mainly employed for the gate insulating film, and a film having an insulating characteristic and a different dielectric constant can be used for the gate insulating film. Also in the above-described SRAM, although access transistor Q 3 and driver transistor Q 2 are described by way of illustration, the above-structure can be employed for access transistor Q 4 and driver transistor Q 1 . A ferroelectric film or a paraelectric film may be used for each gate insulating film. Such a ferroelectric film includes a PT (relative dielectric constant = from 200 to 400), a PZT (relative dielectric constant = from 300 to 2000) and a PLZT (relative dielectric constant = from 300 to 1500). The paraelectric film includes (Ba, Sr) TiO 3 (relative dielectric constant = from 250 to 500), SrTiO 3 (relative dielectric constant = from 200 to 250), and Ta 2 O 5 (relative dielectric constant = 22). Now, the structure of an access transistor with a different threshold voltage V th according to an embodiment of the invention will be described. As described above, a method of reducing the threshold voltage V th of access transistor may be employed as a method of stabilizing reading operation by enlarging the memory cell eye. Figs. 18A and 18B are cross sectional views schematically showing the structure of an access transistor and a driver transistor. Referring to Figs. 18A and 18B, access transistor Q 3 has source/drain regions 25d, and a gate electrode 21 formed on the channel region with a gate insulating film 27 therebetween. Driver transistor Q 2 has a drain region 26a and a source region 26b, and a gate electrode 23 formed on the channel region with a gate insulating film 27 therebetween. A possible approach to reduce the threshold voltage V th of access transistor Q 3 is to reduce the amount of an impurity implanted into the channel region. Fig. 19 is a representation showing impurity concentrations corresponding to depth positions along line X 0 -X 1 in Fig. 18A and line Y 0 -Y 1 in Fig. 18B. Referring to Fig. 19, reducing the impurity concentration in the depthwise direction of access transistor Q 3 compared to driver transistor Q 2 results in reduction of the threshold voltage V th of the access transistor. This somewhat stabilizes the reading characteristic as a result. In recent years, however, demands for high density integration have increased in the field of SRAMs, and power supply voltage (Vcc) has been reduced as integration density has increased. More specifically, reducing the power supply voltage which has been 5V to 3V has been contemplated. In the environment in which the power supply voltage tends to be reduced as such, increase of the threshold voltage of an access transistor due to a back gate effect can not be ignored. Herein, the back gate effect indicates an effect created when bias voltage is applied to the source and substrate in an MOS transistor, and the depletion layer between the channel and the substrate is increased by the amount of the bias voltage to increase fixed charge (ionized acceptor or donor). Fixed charge in the depletion layer increases by the amount corresponding to the expansion of the depletion layer and the threshold voltage V th increases corresponding to the amount of increase of the fixed charge. In the arrangement of the access transistor shown in Fig. 19, if increase of the threshold voltage V th due to the backgate effect described above is to be prevented, current leakage is generated as follows. More specifically, in the structure of the access transistor shown in Fig. 19, in order to reduce the threshold voltage V th in the state in which bias due to the backgate effect is applied, fixed charge in the depletion layer should be reduced. In this case, however, fixed charge in the depletion layer without bias due to the backgate effect being applied is greatly reduced. Accordingly, the threshold voltage V th of the access transistor at back bias voltage = 0V becomes low, resulting in current leakage. In contrast, in the access transistor employed for the memory cell structure of the SRAM according to the embodiment of the invention, the amount of impurity implanted into the channel region is reduced, and the energy is reduced as well. Accordingly, as illustrated in Fig. 20, the impurity concentration peak (chain dotted line r 1 -r 1 ) is at a relatively shallow position from the substrate surface as compared to the case of driver transistor Q 2 . Therefore, the amount of fixed charge newly generated (the amount of impurity distributed in region S 1 ) is small even if bias voltage is applied and the depletion layer expands towards the lower side of channel region, and increase of the threshold voltage V th due to the substrate bias effect is restrained. Now, this will be described in more detail. Figs. 21A, 21B, 21C, and 21D are representations for use in illustration of the reasons why increase of the threshold voltage V th is restrained in the improved access transistor in view of the back gate effect. Referring to Figs. 21A, 21B, 21C and 21D, region S a1 and region S b1 each represent the amount of an impurity from the substrate surface of access transistor Q 3 of comparison example shown in Fig. 19 to the region in which the depletion layer is formed. Region S a2 and region S b2 each represent the amount of an impurity from the substrate surface of the improved access transistor Q 3 according to the embodiment shown in Fig. 20 to the region in which the depletion layer is formed. If bias voltage is not applied (V BB =0V), the amount of impurity S a1 (Fig. 21A) in the case of the comparison example simply reducing the amount of implantation is substantially equal to the amounts of impurity S a2 (Fig. 21B) in the case of this embodiment with the implantation energy reduced in addition. More specifically, the amounts of fixed charge of the comparison example (Fig. 21A) and the improved example (Fig. 21B) are substantially the same. Therefore, in this state free from the back gate effect, the threshold voltages Vth of access transistors in the comparison example (Fig. 21A) and the embodiment (Fig. 21B) are substantially identical. However, when bias voltage is applied (at V BB =-1V), the depletion layer expands toward the lower side of the channel region, and the amount of newly generated fixed charge is larger in the comparison example (Fig. 21C) than in the embodiment (Fig. 21D). Therefore, the threshold voltage V th of access transistor Q 3 of the embodiment reducing both the amount of impurity implanted and implantation energy can be more reduced when the back gate effect is present. The back biasing effect upon threshold voltage V th is given as follows: V th =V th0 +k V B +2 F V B is back bias voltage, V th0 is threshold voltage at V B = 0, and  F is Fermi potential. Comparison of the case with channel dope energy of 50keV in a dose amount of 5 x 10 12 /cm -2 and the case with channel dope energy of 35keV in a dose amount of 3.5 x 10 12 /cm -2 is set forth in the following table: Channel Dope Energy V th0 k V th at V B = -1V 50keV 0.75V 0.79 1.137V 35keV 0.75V 0.657 1.072V Note that the result is obtained at 2 F = 0.6. As can be seen from the result set forth in the table, as the channel energy is smaller, V th with back biasing effect applied can be reduced even with V th0 being the same. Therefore, the smaller k is, the smaller will be the back biasing effect. It is noted that the gate length of access transistor Q 3 is generally set larger than that of driver transistor Q 2 . Therefore, in access transistor Q 3 , the punch through margin becomes larger than in driver transistor Q 2 . Accordingly, even if the concentration peak of an impurity implanted into the channel region of access transistor Q 3 is set at a relatively shallow position, a punch through can be restrained from being generated at a relatively deep portion of the substrate. Now, a method of manufacturing an access transistor and a driver transistor according to an improved example giving the impurity concentration distribution shown in Fig. 20 will be described. Figs. 22A and 22B - Figs. 24A and 24B are schematic sectional views showing in the order of steps a method of manufacturing an access transistor and a driver transistor used for an improved SRAM memory cell according to the embodiment of the invention. Referring to Figs. 22A and 22B, photoresist 51d is formed on a p type well 20 in an access transistor region (Fig. 22A). An impurity is implanted into p type well 20 in a driver transistor region (Fig. 22B) using the photoresist 51d as mask with an implantation energy of 50keV. Then, the photoresist 51d is removed away. Referring to Figs. 23A and 23B, photoresist 51e is formed on p type well 20 in a driver transistor region (Fig. 23B). Using photoresist 51e as mask, an impurity is implanted into p type well 20 in the access transistor region (Fig. 23B) with an implantation energy of 20keV. Then, the photoresist 51e is removed away. Referring to Figs. 24A and 24B, gate electrodes 21 and 23 are formed on p type well 20 each with a gate insulating film 27 therebetween. Source/drain regions 25d, 26a, and 26b are formed by implanting an impurity utilizing these gate electrodes 21, 23 or the like as mask. Thus, access transistor Q 3 and driver transistor Q 2 of the embodiment are formed. It is noted that although in the description of the above embodiment transistor Q 3 and driver transistor Q 2 are illustrated by way of example, the structure may be applied to access transistor Q 4 and driver transistor Q 1 . Now, the structure of a load transistor used for another SRAM memory cell structure will be described. Figs. 25A and 25B are plan views schematically showing this SRAM memory cell structure divided into two stages from the bottom layer of the substrate surface. More specifically, Fig. 25A illustrates driver transistors Q 1 , Q 2 , and access transistors Q 3 , Q 4 formed on the substrate, while Fig. 25B illustrates the structure of load transistors Q 5 , Q 6 . Fig. 26A is a schematic cross sectional view taken along line C-C in Figs. 25A and 25B, while Fig. 26B is a schematic cross sectional view taken along line D-D in Figs. 25A and 25B. Referring to Figs. 25A, 25B, 26A and 26B, in this SRAM memory cell structure, a pair of driver transistors Q 1 , Q 2 and a pair of access transistors Q 3 , Q 4 are formed on a main surface of p type well 20. Driver transistor Q 1 has a drain region 25a, a source region 25b, and a gate electrode 24. Driver transistor Q 2 has a drain region 26a, a source region 26b, and a gate electrode 23. A gate insulating film 27 is formed under each of the gate electrodes 24 and 23 of driver transistors Q 1 and Q 2 . Access transistor Q 3 has a pair of source/drain regions 25d, and a gate electrode 21. Access transistor Q 4 has a pair of source/drain regions 26d, and a gate electrode 22. Access transistors Q 3 and Q 4 each have a gate insulating film 27 under gate electrodes 21 and 22. These transistors are formed of n type MOS transistors each having source/drain regions formed on the main surface of p type well 20. The gate electrode 23 of driver transistor Q 2 is connected to one of source/drain regions 25d of access transistor Q 3 and the drain region 25a of driver transistor Q 1 through a contact portion 23a. The gate electrode 24 of driver transistor Q 1 is connected to one of the source/drain regions 26d of access transistor Q 4 and the drain region 26a of driver transistor Q 2 through a contact portion 24a. Referring to Figs. 25B, 26A and 26B, the pair of load transistors Q 5 , Q 6 are formed by stacking two layers of polycrystalline silicon films 41 and 42 upon each other in a desired form. First polycrystalline silicon film 41 has strip portions 41m and 41n extending in a prescribed width. Second polycrystalline silicon film 42 has strip portions 42m and 42n extending in a prescribed width. Load transistor Q 5 has a drain region 41a and a source region 41b having a channel region 41c therebetween in the strip portion 41n of first polycrystalline silicon film 41, and a gate portion 42a formed opposite to channel region 41c in the strip portion 42m of second polycrystalline silicon film 42. Load transistor Q 6 has a drain region 42a and a source region 42b formed having a channel region 42c therebetween in the strip portion 42n of second polycrystalline film 42, and a gate portion 41 formed opposing to channel region 42c in the strip portion 41m of first polycrystalline silicon film 41. A portion 42a to be the gate portion of load transistor Q 5 is integrally connected to the drain region 42a of load transistor Q 6 . A portion 41a to be the gate of load transistor Q 6 is integrally connected to the drain region 41a of load transistor Q 5 . The drain region 41a of load transistor Q 5 is connected to the gate electrode 24 of underlying driver transistor Q 1 through a contact hole 41d. The drain region 42a of load transistor Q 6 is connected to the gate electrode 23 of underlying driver transistor Q 2 through a contact hole 42d. Load transistor Q 5 thus constitutes a so-called top gate type thin film transistor, while load transistor Q 6 constitutes a so-called bottom gate type thin film transistor. In the intermediate layer between the above-described driver transistor Q 1 , Q 2 and access transistor Q 3 , Q 4 , and thin film transistors Q 5 , Q 6 , a tungsten silicide layer 35 to be GND line is formed. Now, a method of manufacturing a load transistor used for the SRAM memory structure as illustrated in Figs. 25A, 25B, 26A, and 26B will be described in conjunction with cross sectional views corresponding to Figs. 26A and 26B. Figs. 27A-31A and Figs. 27B-31B are schematic cross sectional views showing in the order of the process a manufacturing method of the load transistor used for the SRAM memory cell in cross sections corresponding to Figs. 26A and 26B. Referring to Figs. 27A and 27B, driver transistors Q 1 , Q 2 , access transistors Q 3 , Q 4 and overlying tungsten silicide layer 35 are formed on a main surface of p type well 20. An insulating film 53 is formed to cover the surface of p type well 20. Then, a contact hole 41d is formed in the insulating film by means of photolithography and etching. Part of the surface of gate electrode 24 of driver transistor Q 1 is exposed from contact hole 41d. Referring to Figs. 28A and 28B, first polycrystalline silicon film 41 is formed on the surface of insulating film 53. First polycrystalline silicon film 41 is in contact with the gate electrode 24 of driver transistor Q 1 through contact hole 41d. Then, annealing is performed at a temperature in the range from 500°C to 700°C for about 1-24 hours, and grains of first polycrystalline silicon film 41 are developed. Then, first polycrystalline silicon film 41 is patterned by means of photolithography and etching. After the patterning, an impurity is implanted into a portion of the polycrystalline silicon film to form a gate for load transistor Q 6 . It is noted that the above-described annealing treatment may be performed after patterning first polycrystalline silicon film 41. An impurity may be implanted into part of the polycrystalline silicon film to be the gate of load transistor Q 6 after the patterning. Referring to Figs. 29A and 29B, an insulating film 54 to be a gate insulating film is deposited on the entire surface of the wafer. Then, a contact hole 42d is formed by means for photolithography and etching. Part of the surface of gate electrode 23 of driver transistor Q 2 is exposed from contact hole 42d. Referring to Figs. 30A and 30B, second polycrystalline silicon film 42 is formed on the entire surface of the wafer. Second polycrystalline silicon film 42 is in contact with the gate electrode 23 of driver transistor Q 2 through contact hole 41d. Thereafter, annealing is performed at a temperature in the range from 500°C to 700°C for a time period in the range from 1 to 24 hours to grow grains of second polycrystalline silicon film 42. Thereafter, second polycrystalline silicon film 42 is patterned by means of photolithography and etching. The above-described annealing treatment may be performed after the patterning of second polycrystalline silicon film 42. Referring to Figs. 31A and 31B, photoresist 51f is formed to cover portion 42c to be the channel region of load transistor Q 6 . Then, an impurity is implanted into the entire surface of the wafer, and a drain region 41a and a source region 41b are formed in first polycrystalline silicon film 41 with a channel region 41c therebetween. A drain region 42a and a source region 42b are formed with a channel region 42c therebetween in second polycrystalline silicon film 42. Thus, the source/drain regions of load transistors Q 5 , Q 6 are formed at a time. It is noted that if insulating film 54 to be the gate insulating film in the above-described manufacturing process can be formed at a temperature lower than 600°C, annealing treatment for growing grains of the polycrystalline silicon film may be performed only once after depositing second polycrystalline silicon film 42. Then, photoresist 51f is removed away to form load transistors Q 5 , Q 6 as illustrated in Figs. 26A and 26B. In the structure of load transistors Q 5 , Q 6 shown in Fig. 25B, load transistor Q 5 constitutes a top gate type thin film transistor, while load transistor Q 6 constitutes a bottom gate type thin film transistor. The drain region of one transistor shares the gate electrode of the other transistor. Accordingly, size in the manufacture is less restricted by the limit of photolithography than forming both into top gate type or bottom gate type as in the case of the conventional load transistors shown in Fig. 43B. More specifically, first polycrystalline silicon film 41 and second polycrystalline silicon film 42 are formed in different layers. Therefore, the lengths L 1 , L 2 between first and second polycrystalline silicon films 41 and 42 are not restricted by the limit of photolithography techniques. Accordingly, the lengths L 1 and L 2 between the first and second polycrystalline silicon films 41 and 42 may be reduced compared to the minimum manufacturing size (about 0.35µm) by photolithography. Therefore, in the structure of load transistors Q 5 , Q 6 according to this SRAM, the area occupied by load transistors Q 5 , Q 6 in plane can be reduced, and an SRAM memory cell structure suitable for high density integration can be provided. Furthermore, in the structure of load transistors Q 5 , Q 6 according to this SRAM, as illustrated in Fig. 32, the strip portion 41n of first polycrystalline silicon film 41 and the strip portion 42m of second polycrystalline silicon film 42 intersect and constitute a top gate type load transistor. In the top gate type load transistor Q. An impurity is implanted into the underlying semiconductor layer 41 using the strip portion 42m to be a gate electrode as mask. Accordingly, in channel region 41c formed by this impurity implantation, the channel length and channel width are defined by the width of each of strip portions 41 and 42 intersecting in the vertical direction. These intersecting strip portions 42m and 41n are each formed to extend in a prescribed width. Accordingly, even if strip portions 41 and 42 are formed shifted from prescribed positions due to misregistration of the mask for example, as illustrated in Fig. 32, the channel length and the channel width in the top gate type load transistor Q 5 do not change. Therefore, determining the widths of strip portions 42m and 41n can readily provide top gate type load transistor Q 5 having a desired characteristic. Thus, stable operation can be achieved. In addition, first polycrystalline silicon film 41 and second polycrystalline silicon film 42 are arranged in point symmetry when viewed two-dimensionally. This gives the following advantage to this SRAM memory cell structure. Generally, the same performance is requested for a pair of load transistors Q 5 and Q 6 . Referring to an equivalent circuit diagram in Fig. 42, if, for example, a storage node 114 is at "High", and a storage node 115 is at "Low", the potential of the High level side of storage node 114 falls at the time of reading and writing. Accordingly, after word line 109 is closed (after the memory cell is determined to be non-selected), the node potential of the High level side rises to Vcc. However, if ON current (current flowing in an ON state) is different between load transistors Q 5 and Q 6 , time for the potential of storage node 114 to rise to Vcc when storage node 114 is at High is different from time for the potential of storage node 115 to rise to Vcc when storage node 115 is at High. Generally, the higher the potential at the High level of a storage node is, the more hardly soft errors occur. Therefore, if time for rising to Vcc is different between storage nodes 114 and 115, soft error rates will be different between data (depending upon which is a High between storage nodes 114 and 115). Referring to an equivalent circuit diagram in Fig. 42, leakage current in a memory cell (referred to as stand-by current in the chip on the whole) at the time of stand-by (when address selection is not made) is determined by the OFF currents (current flowing in an OFF state) of load transistors Q 5 and Q 6 . This is because, the OFF currents of load transistors Q 5 and Q 6 of thin film transistors are larger than driver transistors Q 1 and Q 2 formed on the substrate. Assuming that storage node 114 is at "High", and storage node 115 is at "Low", the leakage current of a memory cell is determined by the OFF current of thin film transistor Q 6 on the side of storage node 115 (Low level). Accordingly, if the OFF current of thin film transistor Q 6 when storage node 115 is at Low is different from the OFF current of thin film transistor Q 5 when storage node 114 is at Low, the leakage current of the memory cell significantly changes depending upon storage data (depending upon which is at High between storage nodes 114 and 115). As described above, the performances of the pair of load transistors Q 5 and Q 6 are different, soft error ratios differ due to the difference between their ON currents, or the leakage current of a memory cell changes due to the difference between their OFF currents. The same performance is therefore required of load transistors Q 5 and Q 6 . If, for example, as illustrated in Fig. 51, the forms of polycrystalline silicon films in the upper layer and the lower layer are asymmetrical, the size of the channel region can easily be changed due to mask misregistration or the like as described above. Accordingly, asymmetrical forms of first and second polycrystalline silicon layers like load transistors shown in Fig. 51 makes it difficult to obtain the same performance for load transistors Q 5 and Q 6 and can be responsible for the above-described disadvantages. In contrast, in the case of load transistors Q 5 and Q 6 according to this SRAM, the two layers, polycrystalline silicon films 41 and 42 constituting a transistor have symmetrical forms. Accordingly, determining the size of one polycrystalline silicon layer makes it easier to set the channel regions of the two transistors Q 5 and Q 6 to be the same. Upon mask misregistration, the sizes of the channel regions 41c and 42c of load transistors Q 5 and Q 6 are maintained to be the same if polycrystalline silicon layers 41 and 42 are symmetrical in form. Accordingly, soft error ratio and memory cell leakage current are restrained from being different between the transistors. Now, a load transistor used for another SRAM memory cell structure will be described. Fig. 33 is a plan view schematically showing the structure of a load transistor employed for this SRAM memory cell structure. Figs. 34A and 34B are schematic cross sectional views taken along lines E-E and F-F in Fig. 33. Referring to Figs. 33, 34A and 34B, a pair of load transistors are formed of first and second polycrystalline silicon films 46 and 47. More specifically, one load transistor includes a drain region 46a and a source region 46b formed on the strip portion 46m of first polycrystalline silicon film 46 with a channel region 46c therebetween, and a portion 47c to be a gate formed on the strip portion 47m of second polycrystalline silicon film 47. The other load transistor includes a drain region 47a and a source region 47b formed at the strip portion 47m of second polycrystalline silicon film 47 with a channel region 47c therebetween, and a portion 46c to be a gate formed at the strip portion 46m of first polycrystalline silicon film 46. Thus, one load transistor forms a top gate type thin film transistor, while the other load transistor a bottom gate type thin film transistor. Channel regions 46c and 47c of the load transistors function as each other's gate electrode portions. The drain region 46a of first polycrystalline silicon film 46 is connected to the gate electrode (not shown) of one driver transistor through a contact hole 46d. The drain region 47a of second polycrystalline silicon film 47 is connected to the gate electrode (not shown) of the other driver transistor through a contact hole 47d. It is noted that the description of driver transistors, access transistors, etc. in Figs. 34A and 34B is omitted. However, for the structure of driver transistors and access transistors, the structure shown in Fig. 25A can be employed. Now, a method of manufacturing the load transistor pair shown in Figs. 33, 34A, and 34B will be described in conjunction with cross sectional views corresponding to Figs. 34A and 34B. Figs. 35A-39A and Figs. 35B-39B are schematic sectional views corresponding to Figs. 34A and 34B illustrating in the order of steps a method of manufacturing a load transistor used for this SRAM memory cell structure. Referring to Figs. 35A and 35B, an insulating film 56a is formed on the entire surface of a lower layer 20a including the substrate. Contact hole 46d is formed in insulating film 56a by means of photolithography and etching. The surface of the gate electrode (not shown) of one driver transistor is partially exposed from contact hole 46d. Referring to Figs. 36A and 36B, first polycrystalline silicon film 46 is formed on the entire surface of insulating film 56a. First polycrystalline silicon film 46 is in contact with the gate electrode (not shown) of one driver transistor through contact hole 46d. Subsequently, first polycrystalline silicon film 46 is subject to annealing at a temperature in the range from 500°C to 700°C for about 1-24 hours, to grow grains of first polycrystalline silicon film 46. Then, first polycrystalline silicon film 46 is patterned by photolithography and etching. It is noted that the above-described annealing process may be performed after patterning first polycrystalline silicon film 46. Referring to Figs. 37A and 37B, an insulating film 56b is formed on the entire surface of the wafer to cover the surface of first polycrystalline silicon film 46. A contact hole 47d is formed in insulating film 56 formed of insulating films 56a and 56b by photolithography and etching. The surface of the gate electrode (not shown) of the other driver transistor is partially exposed from contact hole 47d. Referring to Figs. 38A and 38B, second polycrystalline silicon film 47 is deposited on the entire surface of insulating film 56. Second polycrystalline silicon film 47 is in contact with the gate electrode (not shown) of the other driver transistor through contact hole 47d. Subsequently, second polycrystalline silicon film 47 is subject to annealing at a temperature in the range from 500°C to 700°C for about 1-24 hours, thus growing grains of second polycrystalline silicon film 47. Then, second polycrystalline silicon film 47 is patterned by photolithography and etching. It is noted that the above-described annealing process may be performed after patterning second polycrystalline silicon film 47. Referring to Figs. 39A and 39B, photoresist 51g is formed on portion 47c to be the channel region of second polycrystalline silicon film 47. An impurity is implanted using the photoresist 51g as mask, to form at a time the source/drain regions of a pair of bottom gate type and top gate type load transistors. More specifically, this impurity implantation forms drain region 47a and source region 47b with channel region 47c therebetween, and drain region 46a and source 46b with channel region 46c therebetween. Subsequently, photoresist 51g is removed away and the pair of load transistors formed of thin film transistors shown in Figs. 34A and 34B are produced. According to this SRAM, one of the load transistor pair is formed of a bottom gate type thin film transistor and the other is formed of a top gate thin film transistor. The channel region of each transistor shares a gate electrode with the other transistors. Accordingly, the pair of load transistors shown in Fig. 43B are both less subject to limitations of size in the manufacture by means of photolithography as compared to a pair of top gate type transistors or a pair of bottom gate type transistors. The channel regions 46c and 47c of the pair of load transistors oppose each other, with one functioning as the gate electrode of the other. Therefore, as opposed to the structure according to the SRAM shown in Fig. 25B, the crossing region of first and second polycrystalline silicon films 46 and 47 may be only one. Thus, the area occupied by the pair of load transistors in plane can be reduced. Therefore, an SRAM memory cell structure suitable for high density integration can be provided. In the structure of load transistors according to this SRAM, channel regions 46c and 47c are formed in the crossing region of first and second polycrystalline silicon films 46 and 47. Therefore, the channel length and channel width of each of the channel regions 46c and 47c are defined by the widths of strip shaped portions 46m and 47m. As a result, even if second polycrystalline silicon film 47 is shifted from first polycrystalline silicon film 46 due to mask misregistration, the channel length and channel width of each channel region 46c, 47c defined by the widths of strip portions 46m and 47m do not change. Consequently, a load transistor having desired characteristic can readily be provided. Thus, stable operation can be secured in operation. Generally, if a polycrystalline silicon film is deposited, the lower surface of the polycrystalline silicon film becomes rougher than the upper surface. More specifically, referring to Fig. 34A, generally, the lower surface 47ca of second polycrystalline silicon film 47 becomes rougher than upper surface 47cb. Accordingly, in a transistor utilizing the vicinity of the lower surface 47ca of polycrystalline silicon film 47 as a channel region as the bottom gate type shown in Fig. 34A, scattering attributable to the roughness of the surface region 47ca of the channel reduces the degree of movement of electrons flowing across channel region 47c. Therefore, the bottom gate type generally exhibits poorer performance than the top gate type. In the foregoing two SRAM memory cell structures in order to improve the performance of a bottom gate type transistor, the thickness of polycrystalline silicon film 47 in the upper layer in which the channel region 47c of the transistor is to be formed is made thick. More specifically, the thickness of the lower polycrystalline silicon film 46 is 1500Å, while the thickness of the upper polycrystalline silicon film 47 is 2000Å. Forming the thickness of the upper polycrystalline silicon film 47 thick reduces the influence of the unevenness of lower surface 47ca upon electrons moving across channel region 47c. More specifically, the ratio of electrons affected by the rough surface is reduced, and therefore the degree of movement of electrons is kept from decreasing. Now, the structure of a load transistor permitting further reduction of the size of another SRAM memory structure will be described. Fig. 40 is a schematic plan view in which the gate electrode is omitted from the load transistor shown in Fig. 43B. Referring to Fig. 40, conventionally, two Vcc interconnection regions 143b shown as the shadowed portion are disposed in the region surrounded by the dotted line (the region of one memory cell). Fig. 41 is a plan view schematically showing the structure of a load transistor used for this SRAM memory cell. Referring to Fig. 41, in this SRAM, one Vcc interconnection region 143a in oblique line is disposed in the region surrounded by the dotted line (the region of one memory cell). Accordingly, another Vcc interconnection region 143a is not necessary in the region surrounded by the dotted line, and therefore the size of the memory cell region can be reduced by the amount. Accordingly, the structure of a load transistor used for an SRAM memory cell suitable for high intensity integration can be provided. It is noted that although in the description of this SRAM the pair of load transistors forming a memory cell are both of top gate type or bottom gate type, one of the pair of load transistors may be of top gate type while the other may be of bottom gate type. It is noted that in the SRAM memory structures described above, the use of polycrystalline silicon films as semiconductor layers constituting the load transistors have been described, but the invention is not limited thereto, and films formed of silicon monocrystal may be utilized. Combining the above-described SRAM memory structures described above can provide an SRAM memory cell structure which can cope with high density integration while maintaining stable reading operation.

Claims: A semiconductor memory device including a static type memory cell having a pair of driver transistors of first type conductivity (Q 1 , Q 2 ) and a pair of load transistors of second type conductivity (Q 5 , Q 6 ) constituting a flipflop circuit, and a pair of access transistors (Q 3 , Q 4 ), comprising a semiconductor substrate (20) having a main surface; a first field effect transistor forming each of said driver transistors (Q 1 ,Q 2 ) formed on the main surface of said semiconductor substrates and a second field effect transistor forming each of said access transistors (Q 3 ,Q 4 ) formed on the main surface of said semiconductor substrate, said first field effect transistor having a pair of first source and drain regions (26a, 26b) formed a distance apart from each other at the main surface of said semiconductor substrate, a first channel region of said semiconductor substrate between said pair of first source and drain regions (26a,26b) having a first impurity concentration profile, the first impurity concentration profile having an impurity concentration peak at a first depth position (T 0 -r 0 ) from said main surface, said second field effect transistor having a pair of second source and drain regions (25d, 25d) formed a distance apart from each other at said semiconductor substrate, and a second channel region of said semiconductor substrate between said pair of second source and drain regions (25d,25d) having a second impurity concentration profile, characterized in that the second impurity concentration profile has an impurity concentration peak at a second depth position (r 1 -r 1 ) shallower than said first depth position (r 0 -r 0 ) from said main surface, and at a position deeper than said second depth position (r 1 -r 1 ), said first impurity concentration profile has a higher concentration value than said second impurity concentration profile. A method of manufacturing a semiconductor memory device including a static memory cell having a pair of driver transistors of first type conductivity (Q 1 , Q 2 ) and a pair of load transistors of second type conductivity (Q 5 , Q 6 ) constituting a flipflop circuit, and a pair of access transistors (Q 3 , Q 4 ), comprising the steps of: implanting an impurity into a semiconductor substrate (20) and forming a first channel region at a main surface of said semiconductor substrate so as to have a first impurity concentration profile having an impurity concentration peak at a first depth position (r 0 -r 0 ) from said main surface; implanting an impurity into said semiconductor substrate and forming a second channel region at the main surface of said semiconductor substrate so as to have a second impurity concentration profile having an impurity concentration peak at a second depth position (r 1 -r 1 ) shallower than the first depth position from said main surface and a lower concentration value than said first impurity concentration profile at a position deeper than the second depth position; (r 1 -r 1 ); forming a pair of first source and drain regions (26a, 26b) of said driver transistor with said first channel region therebetween; and forming a pair of second source and drain regions (25d, 25d) of said access transistor at the main surface of said semiconductor substrate with said second channel region therebetween, a first field effect transistor forming each of said driver transistors (Q 1 ,Q 2 ) thus being formed to include the pair of first source and drain regions, a second field effect transistor forming each of said access transistors (Q 3 ,Q 4 ) being formed to include the pair of second source and drain regions.

Inventors: KOHNO YOSHIO, KURIYAMA HIROTADA, MAKI YUKIO, KOHNO, YOSHIO, KURIYAMA, HIROTADA, MAKI, YUKIO
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H01L27
IPC codes: H01L21, H01L27