MOS differential voltage-to-current converter circuit

Abstract: A MOS differential voltage-to-current converter circuit has first and second MOS transistors forming a differential pair and a resistor connected between the sources of the first and second MOS transistors. These first and second MOS transistors are connected to the sources of third and fourth MOS transistors, at respective sources. By biasing the third and fourth MOS transistors, with a constant current, differential input voltage is supplied to the gates of the third and fourth MOS transistors. The drain outputs of the third and fourth MOS transistors are respectively connected to first and second signal transmission circuits for transmitting the drain outputs to the gates of the first and second MOS transistors through the first and second signal transmission circuits. With taking the current flowing through the first and second MOS transistors as a differential output, a voltage-to-current conversion characteristics not depending upon variable property of the MOS transistors can be obtained.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a MOS voltage-to-current converter circuit employing a field-effect MOS transistor formed on a semiconductor integrated circuit chip. More specifically, the invention relates to a MOS differential voltage-to-current converter circuit which suppresses fluctuation of a mutual conductance. Description of the Related Art Construction and operation of the conventional MOS differential voltage-to-current converter circuit will be discussed with reference to the drawings. Throughout the disclosure, a field-effect MOS transistor will be simply referred to as "MOSFET", N-channel field - effect MOS transistor will be referred to as "NMOSFET", and similarly, P-channel field-effect MOS transistor will be referred to as "PMOSFET". Concerning the reference signs to be used in the following disclosure, I, I*, I**, ΔI represent current, V, V*, V**, ΔV represent voltage, R, R*, R** represent resistance, β, β* represent gain coefficient of MOSFET, and gm, gm* represent mutual conductance of the differential voltage-to-current converter circuit.*,** represent numerals. One example of the circuit construction of the conventional differential voltage-to-current converter circuit (hereinafter referred to as "first prior art") is illustrated in Fig. 13. In Fig. 13, N 1 and N 2 represent first and second NMOSFET, 2R 0 represents one source resistance (resistance value 2R 0 ) mutually connecting the source terminals of N 1 and N 2 . V 1 and V 2 represent first and second input voltages of the differential voltage-to-current converter circuit, V B1 and V B2 represent backgate voltages. On the other hand, I 01 and I 02 represent first and second constant current sources, respectively. I 1 and I 2 represent first and second output currents of the differential voltage-current converter circuit, respectively. Here, it is assumed that currents I 01 and I 02 of the first and second constant current sources are equal to each other. Double of the current I 01 or I 02 is defined as a constant current I 00 which is expressed by the following equation (1). A differential output current ΔI and a differential input voltage ΔV are respectively expressed by the following equation (2). Discussion is now given for an input/output characteristics of the differential input voltage ΔV and the differential output current ΔI in the differential voltage-to-current converter circuit of Fig. 13. Assuming the gain coefficient of the MOSFET is β,a drain current I 0 is expressed by the following equation (3) in the saturated range. It should be noted that, in the equation (3), V GS represents a gate-source voltage, V T represents a threshold voltage. Accordingly, V GS can be expressed by the following equation (4). Applying Kirchhoff's law in the loops of V 1 ∼ V GS1 ∼ V 2R0 ∼ V GS2 ∼ V 2 , the following equation (5) can be established. Then, the differential input voltage ΔV can be expressed by the following equation (6) with taking the current flowing through a resistor 2R 0 between the sources being I R0 . It should be appreciated that, the gain coefficients β of N 1 and N 2 forming a differential pair in the equation (6) are mutually equal. From Kirchhoff's law, the following equation (7-a) can be established with respect to both ends of the resistor 2R 0 . Therefore, the current I R0 flowing through the source resistor 2R 0 is expressed by the following equation (7-b). Therefore, first and second output currents I 1 and I 2 are expressed by the following equation (7-c). Substituting the equation (6) with these, the following equation (8) expressing the input/output characteristics of the differential input voltage ΔV and the differential output current ΔI can be derived. The input/output characteristics (curve a in the drawing) of the differential voltage-to-current converter circuit of the first prior art, which characteristics is expressed by the equation (8), is illustrated in Fig. 14. A reciprocal of the mutual conductance g m of the differential voltage-to-current converter circuit can be obtained by differentiating ΔV with the differential output current ΔI, and expressed by the following equation (9). As shown in Fig. 14, the mutual conductance g m becomes the maximum value g mmax when the differential input voltage ΔV is 0. At this time, from the equation (8), ΔI becomes 0, the reciprocal of the maximum value g mmax is expressed by the following equation (10). It should be appreciated that the maximum value g mmax of the mutual conductance corresponds to the gradient of a tangent b of the input/output characteristics curve a of Fig. 14 at ΔV = 0, the tangent b is expressed by: ΔI = g mmax x ΔV A coefficient E expressing non-linearity of the input/output characteristics of the differential voltage-to-current converter circuit is defined by the equation (12-a). Namely, the non-linearity E can be obtained by obtaining a difference between the input/output characteristics curve a and the tangent b with respect to ΔV and by dividing the difference by the value (g mmax x ΔV) of the tangent b. Expressing the a rate of I 00 as double of the current of the first and second current source and the differential output current ΔI as a coefficient α (equation (11)), the non-linearity E can be expressed with the coefficient α and I 00 in the following equation (12-b). A curve in Fig. 15 is a plot of the non-linearity with respect to the differential input voltage ΔV (horizontal axis). Respective values shown in Figs. 14 and 15 are derived with taking the constant current I 00 = 1 (mA), gain coefficient β = 1 x 10 -3 (A/V 2 ), the source resistor R 0 = 1 (kΩ). It should be noted that the value (horizontal axis) of the non-linearity E is shown by % in Fig. 15. With reference to Fig. 15, at near the maximum value I 00 of the differential output current ΔI, the non-lineality E becomes approximately 17%. I 00 = 2I 01 = 2I 02 ΔI = I 1 - I 2 ΔV = V 1 - V 2 I D = β 2 (V GS - V T ) 2 V GS = V T + 2 I D β V 1 - (V GS1 + V 2R0 ) - V 2 + V GS2 = . 0 ΔV = V 1 - V 2 = V GS1 - V GS2 + V 2R0 = 2 I 1 β - 2 I 2 β + 2 R 0 I R0 I 1 - I R0 = I 01 , I 2 + I R0 = I 02 I R0 = ( I 1 - I 2 ) 2 = Δ I 2 I 1 = ( I o0 + Δ I ) 2 . I 2 = ( I o0 - Δ I ) 2 Δ V = I o0 + Δ I β - I o0 - Δ I β + R 0 • Δ I 1 g m = d Δ V d Δ I = 1 2 β( I o0 + Δ I ) + 1 2 β( I o0 - Δ I ) + R 0 1 g mmax = d Δ V d Δ I = 1 I o0 • β + R 0 (ΔI = 0) α = I o0 Δ I E = 1 g mmax Δ I Δ V - 1 = 1 + R 0 I o0 β α 2 + α - α 2 - α + R 0 I o0 β - 1 wherein (-I o0 ≦ ΔI ≦ I o0 ) (- 2 • I o0 β R 0 • IO0 ≦Δ V ≦ 2 • I o0 β + R 0 • I o0 ) From Figs. 14 and 15, it should be appreciated that the absolute value of the non-linearity E is increased according to increasing of the differential output current ΔI associated with increasing of the differential input voltage ΔV. This is caused due to I D -V GS characteristics of the MOSFET, in which a drain current I n does not vary in proportion to variation of a gate-source voltage V GS . In other words, as expressed in the equation (8), this is caused due to the fact that the differential input voltage ΔV and the voltage V 2R0 at opposite ends of the source resistor (accordingly, the differential output current ΔI) are not proportional to each other. The characteristics of the above-mentioned differential 1 voltage-to-current converter circuit is similarly applicable for the case where the first and second NMOSFETs are replaced with PMOSFETs. Figs. 16 shows another example of a circuit construction of the conventional the differential voltage-to-current converter circuit in which first and second resistors R 01 and R 02 are connected in common (hereinafter referred to as "second prior art"). As shown in Fig. 16, the second prior art is constructed by connecting first and second resistors R 01 and R 02 to source terminals of first and second MOSFETs N 1 and N 2 at each one end, and connecting one constant current source I 0 to a common junction of the first and second resistors R 01 and R 02 . V 1 and V 2 denote first and second inputs voltages, V B1 and V B2 denote a backgate terminal voltages, and I 1 and I 2 denote the first and second output currents. The resistance values of the first and second resistors R 01 and R 02 are assumed to be equal to each other. Then, the source resistor R 00 is defined as expressed in the following equation (13-a). Also, the differential output current ΔI is defined to be expressed by the following equation (13-b). The differential input voltage ΔV in the differential voltage-to-current converter circuit of Fig. 16 is derived in the similar manner to the foregoing first prior art by replacing the source resistor 2R 0 with 2R o0 and I o0 in the equation (1) with I 0 , and thus expressed by the following equation (14). The input/output characteristics of the second prior art is illustrated in Fig. 17, and the non-linearity E defined by the following equation (18) is illustrated in Fig. 18. R 00 = R 01 = R 02 ΔI = I 1 - I 2 ΔV = V 1 - V 2 = I 0 + Δ I β - I 0 - Δ I β + R 00 •Δ I 1 g m = d Δ V d Δ I = 1 2 β( I 0 + Δ I ) + 1 2 β( I 0 -Δ I ) + R 00 1 g mmax = d Δ V d Δ I = 1 I 0 • β + R 00 (Δ I = 0) α = I 0 Δ I E = 1 g mmax Δ I Δ V -1 = 1 + R 00 I 0 β α 2 + α - α 2 + α + R 00 I 0 β -1 wherein (-I o ≦ ΔI ≦ I o ) (- 2• I 0 β - R 00 • IO ≦Δ V ≦ 2• I 0 β + R 00 · I 0 ) Respective values in Figs. 17 and 18 are derived with assumption of constant current source I 0 = 1 (mA), gain coefficient β = 1 x 10 -3 (A/V 2 ), source resistance R 00 = 1 (KΩ). From Figs. 17 and 18, it should be appreciated that the absolute value of the non-linearity E is increased according to increasing of the differential output current ΔI associated with increasing of the differential input voltage ΔV. This is caused due to I D -V GS characteristics of the MOSFET, in which a drain current I n does not vary in proportion to variation of a gate-source voltage V GS . In other words, as expressed in the equation (14), this is caused due to the fact that the differential input voltage ΔV and the voltage V R at opposite ends of the source resistor (accordingly, the differential output current ΔI) are not proportional to each other. The characteristics of the above-mentioned the differential voltage-to-current converter circuit is similarly applicable for the case where the first and second NMOSFETs are replaced with PMOSFETs. Fig. 19 shows a circuit construction of the differential voltage-to-current converter circuit disclosed in Japanese Unexamined Patent Publication No. 57-46161 (hereinafter referred to as "third prior art). As shown in Fig. 19, the third prior art is designed for eliminating non-linearity of an amplifier element by combination of a differential amplifier and bipolar current-mirror circuit having two outputs. In the third prior art, assuming the current-mirror circuit and the constant current source are both ideal, the relationship between the differential output current ΔI and the differential input voltage ΔV can be expressed by the following equation (21). The input/output characteristics is shown in Fig. 20. The non-linearity E (expressed by the following equation (22)) of the differential voltage-to-current converter circuit of the third prior art is illustrated in Fig. 21. From Fig. 21, the non-linearity E becomes 0 in a range of the differential input voltage ΔV being ±RI 0 /3. Therefore, a linearity can be improved. However, in the third prior art, in order to take the current out, it becomes necessary to add new circuit, such as an output side transistor added for the bipolar current-mirror circuit. These circuit varies signals in non-linear fashion according to variation of the input current. Therefore, the non-linearity of the voltage-to-current converter circuit is increased beyond 0 in the equation (22) to degrade effect in improvement of the linearity. As shown in Figs. 20, 21, with the circuit construction in the third prior art, the range of the differential current, in which the non-linearity can be reduced, is in a range of 1/3 of the constant current I 0 . Accordingly, in order to obtain the output comparable with those in the prior arts 1 and 2, the constant current has to be three time grater, or, in the alternative, a size ratio between the bipolar transistors forming the mirror-current circuit has to be selected appropriately. ΔV = V 1 - V 2 R = 2R 01 = 2R 02 i 1 + i 2 = I 0 , i 3 + i 4 = I 0 /3, i 5 + i 6 = I 0 /3 i 1 = I 0 2 + Δ V 2• R , i 2 = I 0 2 - Δ V 2• R , i 5 = I 0 6 + Δ V 2• R , I 6 = I 0 6 - Δ V 2• R ΔI = i 5 - i 6 = Δ V R 1 g m = 1 g mmax = dΔV dΔI = R (Δ I = 0) E = 1 g mmax ΔI ΔV -1 = 0 wherein (- I 0 3 ≦ ΔI ≦ I 0 3 ) (- R • I 0 3 ≦Δ I ≦ R • I 0 3 ) In Fig. 22, the construction of the differential amplifier disclosed in Japanese Unexamined Utility Model Publication No. 63-44521 (hereinafter referred to as "fourth prior art"). In Fig. 23, the input/output characteristics of the fourth prior art is illustrated. In the fourth prior art, for respective first and second bipolar transistors, third and fourth bipolar transistors, bases and emitters of which are mutually connected, are employed. By applying the constant current to this, the linearity of the differential amplifier circuit is improved in the range of ±αI EE of the output current. As shown in Fig. 22, in the circuit construction of the fourth prior art, direct current is constantly applied to input signal sources V 1 and V 2 from emitters of fifth and sixth transistors Q 4 and Q 6 . Therefore, the input signal sources V 1 and V 2 are required drive performance for supplying the supplied current. Figs. 24 and 25 show a circuit construction of a differential amplifier disclosed in Japanese Unexamined Patent Publication No. 59-229909 (hereinafter referred to as "fifth prior art"). As shown, the differential amplifier of the fifth prior art is constructed by contacting the drain of a first FET forming differential pair to a load, the drain of a second FET forming the differential pair to the source of a third FET, and the gate of the third FET to a junction between the drain and the load of the first FET, and the drain of the third FET to the load. In the fifth prior art, the relationship between the input voltage and the output voltage of the differential amplifier in the range where the mutual conductance g m1 to g m4 of the FETs (M1 to M4) satisfy the condition expressed in the following equation (23), becomes as expressed in the following equation (24). Then, the linearity of the input/output characteristics can be improved. g m4 g m1 = g m3 g m2 g m1 = g m2 V out = 1 2 g m2 g m5 V in The condition defined in the equation (23) with respect to the differential amplifier of the fifth prior art can be only satisfied by a fine signal alternating operation near a certain direct current operation point of the circuit (in the case where amplitude of the voltage at respective points in the circuit is small). In the MOS differential voltage-to-current converter circuit in the foregoing first, second and fifth prior arts, a problem in degradation of the linearity of the input/output characteristics according to increasing of the differential output current ΔI associated with increasing of the differential input voltage ΔV and narrowing of a dynamic range, is encountered. There is further encountered a problem in increasing of non-linearity due to influence of variation of the properties of MOSFET, such as non-linearity of I D -V GS characteristics, fluctuation of gain coefficient β, variation of a threshold voltage V T due to a backgate effect, variation of I D -I GS characteristics up to MOS saturation range due to short channel effect and so forth. The third prior art is capable of reducing non-linearity of the differential amplifier circuit by combination of the differential amplifier circuit and the current-mirror circuit with two outputs employing the bipolar process. However, a new circuit is required for taking the current out. Also, the amplitude of the differential output current is merely 1/3 of the current value I 0 of the constant current source at the greatest. Accordingly, in the third prior art, it becomes necessary to provide the constant current I 0 three times greater in order to obtain comparable output to the first and second prior arts, or to appropriately adjust the size ratio of the bipolar transistors forming the current-mirror circuit. Therefore, there is encountered a problem in difficulty in reducing consumed current in the circuit construction of the third prior art. On the other hand, in the circuit construction of the third prior art, the currents flowing through the transistor of the bipolar current-mirror circuit and the differential MOSFET influence each other. For instance, since an Early voltage V A of the bipolar transistor is typically smaller than the Early voltage V A of the MOS transistor, the variation magnitude of the collector currents of the transistors Q 1 and Q 2 and the drain current of N 1 and N 2 in Fig. 19 becomes greater than that in the case where MOS transistors are employed as all transistors. Therefore, it becomes difficult to design the size and so forth of the transistor independently. Furthermore, the third prior art comprises the MOS transistors and the bipolar transistors. For fabricating these different types of transistors on-the common semiconductor chip, production process is inherently increased to cause rising of the production cost. Next, in the circuit construction of the foregoing fourth prior art, it is required the direct current constantly flowing into the input signal source and thus is required a driving performance to supply the current to the input signal source. Also, the performance of the whole circuit is significantly influenced by the external circuit (power source). Therefore, this circuit encounters a problem in difficulty of handling. In the differential amplifier of the fifth prior art, the condition expressed by the equation (23) is only satisfied by a fine signal alternating operation near a certain direct current operation point of the circuit (in the case where amplitude of the voltage at respective points in the circuit is small) and cannot be satisfied when amplitude of the voltage is large. A most differential voltage-to-current converter circuit according to the preamble part of claim 1 is known from EP-A-0 478 297. From IBM Technical Disclosure Bulletin Vol. 9, No. 7, page 949, E.F. DONNER et al., "Differential Amplifier", an amplifier is known with transistors the sources and drains of which are connected to each other. IEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, pp. 256-257, W. SANSEN et al., "Micropower Monolithic Data-Acquisition System" shows an amplifier, in which second and third constant current sources are used for supplying operation currents to the transistors and in which drain outputs of the transistors are transmitted to the gates of further transistors. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a MOS differential voltage-to-current converter circuit which can improve linearity by avoiding increasing of non-linearity due to various property of MOSFETs of a differential pair in a range of predetermined differential input voltage. Another object of the invention is to provide a MOS differential voltage-to-current converter circuit, in which a mutual conductance is determined only by the resistance value 2R 0 or (R 01 + R 02 ) between source (or drain) terminals of the differential pair MOSFET. These objects are solved by the features of the main claim. The sub-claims show advantageous embodiments of the converter circuit. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the present invention, but are for explanation and understanding only. In the drawings: Fig. 1 is an illustration showing a circuit construction of the first embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 2 is an illustration showing a circuit construction of the first embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 3 is an illustration showing an input/output characteristics of the first embodiment of the differential voltage-to-current converter circuit according to the invention; Fig. 4 is an illustration showing a non-linear characteristics of the first embodiment of the differential voltage-to-current converter circuit of the invention; Fig. 5 is an illustration showing a circuit construction of the second embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 6 is an illustration showing a circuit construction of the second embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 7 is an illustration showing an input/output characteristics of the second embodiment of the differential voltage-to-current converter circuit according to the invention; Fig. 8 is an illustration showing a non-linear characteristics of the second embodiment of the differential voltage-to-current converter circuit of the invention; Fig. 9 is an illustration showing a circuit construction of the third embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 10 is an illustration showing a circuit construction of the third embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 11 is an illustration showing a circuit construction of the fourth embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 12 is an illustration showing a circuit construction of the fourth embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 13 is an illustration of the circuit construction of the first prior art. Fig. 14 is an illustration showing an input/output characteristics of the first prior art; Fig. 15 is an illustration showing a non-linear characteristics of the first prior art; Fig. 16 is an illustration showing the circuit construction of the second prior art; Fig. 17 is an illustration showing the input/output characteristics of the second prior art; Fig. 18 is an illustration showing the non-linearity of the second prior art; Fig. 19 is an illustration showing the circuit construction of the third prior art; Fig. 20 is an illustration showing the input/output characteristics of the third prior art; Fig. 22 is an illustration showing the circuit construction of the fourth prior art; Fig. 23 is an illustration showing the input/output characteristics of the fourth prior art; Fig. 24 is an illustration showing the circuit construction of the fifth prior art; Fig. 25 is an illustration showing circuit construction of another example of the fifth prior art; Fig. 26 is an illustration showing one embodiment of a signal transmission circuit to be employed in the first and second embodiment of the invention; Fig. 27 is an illustration showing another embodiment of a signal transmission circuit to be employed in the first and second embodiment of the invention; Fig. 28 is an illustration showing one embodiment of a signal transmission circuit to be employed in the third and fourth embodiment of the invention; Fig. 29 is an illustration showing another embodiment of a signal transmission circuit to be employed in the third and fourth embodiment of the invention; Fig. 30 is an illustration showing first embodiment of a constant current source to be employed in the first to fourth embodiments of the invention; Fig. 31 is an illustration showing second embodiment of a constant current source to be employed in the first to fourth embodiments of the invention; Fig. 32 is an illustration showing third embodiment of a constant current source to be employed in the first to fourth embodiments of the invention; Fig. 33 is an illustration showing fourth embodiment of a constant current source to be employed in the first to fourth embodiments of the invention; Fig. 34 is an illustration showing a circuit construction of the fifth embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 35 is an illustration showing a circuit construction of the fifth embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 36 is an illustration showing an input/output characteristics of the fifth embodiment of the differential voltage-to-current converter circuit according to the invention; Fig. 37 is an illustration showing a non-linear characteristics of the fifth embodiment of the differential voltage-to-current converter circuit of the invention; Fig. 38 is an illustration showing a circuit construction of the sixth embodiment of a sink type differential voltage-to-current converter circuit according to the present invention; Fig. 39 is an illustration showing a circuit construction of the sixth embodiment of a source type differential voltage-to-current converter circuit according to the present invention; Fig. 40 is an illustration showing an input/output characteristics of the sixth embodiment of the differential voltage-to-current converter circuit according to the invention; and Fig. 41 is an illustration showing a non-linear characteristics of the sixth embodiment of the differential voltage-to-current converter circuit of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiments of a MOS differential voltage-to-current converter circuit according to the present invention will be discussed hereinafter with reference to the accompanying drawings. Figs. 1 to 4 show a circuit construction of the first embodiment of the MOS differential voltage-to-current converter circuit of the present invention, and an input/output characteristics thereof. As shown in Figs. 1 and 2, respective source terminals of first and second MOSFETs (N 1 and N 2 or P 1 and P 2 ) forming a differential pair in this embodiment are connected to first and second constant current sources I 01 and I 02 . Between the source terminals of the first and second MOSFETs, one source resistor 2R 0 is connected. Fig. 1 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 2 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. In Figs. 1 and 2, the circuit elements performing substantially the same functions to those in the first prior art illustrated in Fig. 13 will be represented by the same reference numerals. N 3 and N 4 of Figs. 1 and 2 denote third and fourth NMOSFETs, and A 1 and A 2 denote first and second signal transmission circuits. As the signal transmission circuits A 1 and A 2 in Fig. 1, circuit constructions illustrated in Figs. 26 and 27 can be employed On the other hand, as the signal transmission circuits A 1 and A 2 in Fig. 2, the circuit illustrated in Fig. 27 may be employed. As the constant current source of Fig. 1, various current-mirror circuits illustrated in Figs. 30 to 33 may be employed. Hereinafter, the construction and operation of the MOS differential voltage-to-current converter circuit constructed by employing direct connection of Fig. 26 in the first and second signal transmission circuits A 1 and A 2 in Fig. 1. As shown in Fig. 1, the third and fourth constant current sources I 03 and I 04 are connected to the drain terminals of MOSFET N 3 and N 4 , respectively for maintaining the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 constant. The source terminals of N 3 and N 4 are respectively connected to the source terminals of N 1 and N 2 to maintain the voltage between the first input terminal V 1 and the source terminal of N 1 and the voltage between the second input terminal V 2 and the source terminal of N 2 constant. The drain terminals of N 3 and N 4 are respectively connected to the gate terminals of N 1 and N 2 . It should be noted that the following condition is established with respect to the constant current sources I 01 , I 02 , I 03 and I 04 . ¦ I 03 ¦ ≦ ¦ I 01 ¦ ¦ I 04 ¦ ≦ ¦ I 02 ¦ Under the condition set forth above, the operation of the differential voltage-to-current converter circuit of Fig. 1 will be discussed hereinafter. A current which is double of the current of first or second constant current source I 01 or I 02 is assumed as I 00 (equation (25-a)). Also, a current double of the current of the third or fourth constant current source I 03 or I 04 is assumed as I 00 ' (equation (25-b)). The differential input voltage ΔV can be derived from a difference of the first and second input terminal voltages V 1 and V 2 (equation (26)). The voltage at opposite ends of the source resistor 2R 0 is expressed by ΔV R . Then, in the loop of V 1 ∼V GS3 ∼ΔV R ∼V GS4 ∼V 2 , the equation (28-a) can be established from Kirchhoff's law. The gate-source terminal voltages V GS3 and V GS4 of NMOSFET N 3 and N 4 can be expressed by the equation (27) in the saturation region. Here, V T3 and V T4 are threshold voltages of N 3 and N 4 . To the drain terminals of N 3 and N 4 , constant currents flow from respective constant current sources I 03 and I 04 . Therefore, as can be appreciated from the equation (27), the gate-source terminal voltages V GS3 and V GS4 become constant. Substituting the equation (27) with V GS3 and V GS4 of the equation (28-a), the equation (28-b) can be established. Values in the parenthesis of the equation (28-b), namely (V GS3 - V GS4 ), becomes a constant value independent of the differential input voltage ΔV. Expressing the term in the parenthesis as -b, ΔV R can be expressed with a linear equation of the differential input voltage ΔV. In this case, the constant b is an offset voltage. In the case where circuit elements arranged at symmetrical positions have the same characteristics, the currents of the third and fourth constant current sources I 03 and I 04 , the gains β 3 and β 4 , the threshold voltages V T3 and V T4 become mutually equal to each other, respectively. Therefore, V GS3 and V GS4 match to each other. Therefore, the constant b in the equation (28-c) becomes 0. Then, the voltage ΔV R becomes equal to the differential input voltage ΔV (equation (32-a)). Next, assuming the current flowing through the resistor 2R 0 is I R0 , the equation (29-a) can be established from the Kirchhoff's law with respect to the opposite ends of the resistor 2R 0 . Form this. the differential output current ΔI can be expressed by the equation (30-a). With respect to the voltage ΔV R at opposite ends of the resistor 2R 0 , I R0 can be derived from the equation (29-b). When, the equation (28-b) is employed as ΔV R , the equation (29-c) can be established. Substituting the equation (30-a) with the equation (29-c), the differential output current ΔI can be expressed by the equation (30-b). As can be appreciated from the equation (30-b), the differential output current ΔI is in a linear relationship with the differential input voltage ΔV. This relationship can be expressed by the equation (30-c). Here, constants c and d are respectively derived from the equation (30-d) and the constant b represents (-V GS3 + V GS4 ) similarly to (28-d). It should be noted that the constant c represents the mutual conductance and the constant d is an offset current. With respect to I 03 and I 04 satisfying Kirchhoff's law at opposite ends of the resistor 2R 0 , the drain voltages of NMOSFETs N 3 and N 4 are determined and applied to the gate terminals of the differential pair N 1 and N 2 . I 00 = 2 • I 01 = 2 • I 02 I 00 ' = 2 • I 03 = 2 • I 04 ΔV = V 1 - V 2 V GS3 = 2 • I 03 β 3 + V T3 , V GS4 = 2 • I 04 β 4 + V T4 I 1 = I 01 - I 03 + I R0 , I 2 = I 02 - I 04 - I R0 c = 1 R 0 , d = I 01 - I 02 - I 03 + I 04 + b R 0 In the case where the circuit elements located at the symmetric positions on the circuit diagram have the same characteristics, the equations (25-a) and (25-b) are established, and gain coefficients β 3 and β 4 of N 3 and N 4 and the threshold voltages V T3 and V T4 of N 3 and N 4 become equal to each other. Then, the constant d in the equation (30-c) becomes 0. Therefore, as shown in the equation (32-b), ΔI becomes proportional to ΔV. Similarly manner to the prior arts, the mutual conductance g m and non-linearity E of the shown embodiment of the differential voltage-to-current converter are derived (equations (33-b) and (34-b)). Then, the range of ΔV and ΔI, in which the satisfactory linearity is established is expressed by the equation (35). Fig. 3 shows the input/output characteristics of the shown embodiment of the differential voltage-to-current converter circuit and Fig. 4 shows the characteristics of the non-linearity E in relation to the differential input voltage ΔV. β' = β 3 = β 4 ∴ V GS3 = V GS4 b = 0, d = 0 ΔV R = ΔV (¦ΔI¦ ≤ I 00 - I 00 '), (¦ΔV¦ ≤ R 0 • (I 00 - I 00 ')) Referring to Figs. 3 and 4, in the differential voltage-to-current converter circuit in the shown embodiment, even when the differential output current ΔI is increased according to increasing of the differential input voltage ΔV, the non-linearity E is not increased and to be maintained at 0 within the range defined by the foregoing equation (35). Next, discussion will be given for the construction and operation of the differential voltage-to-current converter circuit in the case where the circuit shown in Fig. 27 is employed as the first and second signal transmission circuits A 1 and A 2 . Each of the source terminals of N 3 and N 4 which are connected to the constant current sources I 03 and I 04 at the drain terminals for maintaining the gate-source terminal voltages V GS3 and V GS4 constant, is connected to the source terminal of each of N 1 and N 2 as the differential pair so that the voltage between the first input terminal V 1 and the source terminal of N 1 and the voltage between the second input terminal V 2 and the source terminal of N 2 are constant. As shown in Fig. 27, the signal transmission circuit A 1 and A 2 respectively comprise differential amplifier circuits. To non-inverting inputs of the differential amplifiers A 1 and A 2 , the first and second input terminals V 1 and V 2 are connected. On the other hand, to the inverting inputs, the drain terminals of N 3 and N 4 are connected. Outputs of the differential amplifier circuits A 1 and A 2 are connected to the gate terminals of the first and second NMOSFETs N 1 and N 2 , respectively. The input/output characteristics, mutual conductance and non-linearity of the differential voltage-to-current converter circuit employing the differential amplifiers A 1 and A 2 as the first and second signal transmission circuits, can be derived in the similar manner to the case of the foregoing embodiment with direct connection. Discussion will be given hereinafter with respect to the operation of the differential voltage-to-current converter circuit employing the differential amplifier circuits A 1 and A 2 . When the voltage V 1 at the first input terminal is risen (the voltage V 2 of the second input terminal drops), the drain voltage of N 3 is lowered (the drain voltage of N 4 is risen). Then, the output of the differential amplifier circuit A 1 is risen and the output of the differential amplifier circuit A 2 is lowered. These outputs are applied to respective gate terminals of N 1 and N 2 of the differential pair. Therefore, the drain current of N 1 is increased and the drain current of N 2 is decreased. Then, the difference of the drain currents of N 1 and N 2 flows through the source resistor 2R 0 . Accordingly, the differential amplifier circuits A 1 and A 2 operate to maintain the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 . Namely, they compensate following up of the source terminals of N 3 and N 4 to the first and second input terminals and whereby stabilize the operation of the differential voltage-to-current converter circuit. If the amplification factors of the differential amplifier circuits A 1 and A 2 are sufficiently high, V GS3 and V GS4 can be maintained constant. Then, the mutual conductance g m and the non-linearity E can be expressed by the equations (33-b) and (34-b). Next, discussion will be given for the operation in the case where the differential amplifier circuits of Fig. 27 are employed as the signal transmission circuits A 1 and A 2 of the differential voltage-to-current converter circuit shown in Fig. 2. As shown in Fig. 27, non-inverting inputs of the differential amplifier circuits A 1 and A 2 are connected to first and second input terminals V 1 and V 2 , respectively. On the other hand, the inverting inputs are connected to the drain terminals of N 3 and N 4 . The outputs of the differential amplifier circuits A 1 and A 2 are connected to gate terminals of first and second PMOSFETs P 1 and P 2 . When the voltage V 1 at the first input terminal is risen (the voltage V 2 of the second input terminal drops), the drain voltage of N 3 is lowered (the drain voltage of N 4 is risen). Then, the output of the differential amplifier circuit A 1 is risen and the output of the differential amplifier circuit A 2 is lowered. These outputs are applied to respective gate terminals of P 1 and P 2 of the differential pair. Therefore, the drain current of P 1 is decreased and the drain current of P 2 is increased. Then, the difference of the drain currents of P 1 and P 2 flows through the source resistor 2R 0 . The differential amplifier circuits A 1 and A 2 operate to maintain the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 . Namely, they compensate following up of the source terminals of N 3 and N 4 to the first and second input terminals and whereby stabilize the operation of the differential voltage-to-current converter circuit. If the amplification factors of the differential amplifier circuits A 1 and A 2 are sufficiently high, V GS3 and V GS4 can be maintained constant. Then, the mutual conductance g m and the non-linearity can be expressed by the equations (33-b) and (34-b). In this embodiment, the input/output characteristics and the non-linearity of the differential voltage-to-current converter circuit may be derived in the similar manner even when the inputs of the first and second signal transmission circuits A 1 and A 2 are first and second input terminals. On the other hand, in the shown embodiment, it is possible to similarly handle the circuit even when the NMOSFET is replaced with the PMOSFET, PMOSFET is replaced with NMOSFET, and the direction of the constant current source is reversed. Figs. 5 ∼ 8 show the circuit construction, input/output characteristics of the second embodiment of the MOS differential voltage-to-current converter circuit according to the present invention. As shown in Figs. 5 and 6, respective source terminals of first and second MOSFETs (N 1 and N 2 or P 1 and P 2 ) forming a differential pair in this embodiment are connected to one terminals of first and second resistors R 01 and R 02 . The other terminals of the first and second source resistors R 01 and R 02 are commonly connected. To the junction of common connection of the first and second resistors R 01 and R 02 is connected to a constant current source I 0 . Fig. 5 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 6 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. In Fig. 5, the functionally common elements to those in Fig. 16 which illustrates the second prior art will be represented by the same reference numerals. In Fig. 5, N 3 and N 4 are third and fourth NMOSFETs, and V B3 and V B4 are backgate terminals and voltages. As the signal transmission circuits A 1 and A 2 in the shown embodiment, circuit constructions illustrated in Figs. 26 and 27 can be employed On the other hand, as the signal transmission circuits A 1 and A 2 in Fig. 6, the circuit illustrated in Fig. 27 may be employed. As the constant current sources of Figs. 5 and 6, various current-mirror circuits illustrated in Figs. 30 to 33 may be employed. Hereinafter, the construction and operation of the MOS differential voltage-to-current converter circuit constructed by employing direct connection of Fig. 26 in the first and second signal transmission circuits A 1 and A 2 in Fig. 5. As shown in Fig. 5, the constant current sources I 03 and I 04 are connected to the drain terminals of MOSFET N 3 and N 4 , respectively for maintaining the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 constant. The source terminals of N 3 and N 4 are respectively connected to the source terminals of N 1 and N 2 to maintain the voltage between the first input terminal V 1 and the source terminal of N 1 and the voltage between the second input terminal V 2 and the source terminal of N 2 constant. The drain terminals of N 3 and N 4 are respectively connected to the gate terminals of N 1 and N 2 . It should be noted that the following condition is established with respect to the constant current sources I 0 , I 03 and I 04 . ¦ I 03 ¦ + ¦ I 04 ¦ ≦ ¦ I 0 ¦ Under the condition set forth above, the operation of the differential voltage-to-current converter circuit of Fig. 5 will be discussed hereinafter. The voltage at opposite ends of the first and second resistors R 01 and R 02 are expressed by ΔV R . Then, in the loop of V 1 ∼V GS3 ∼ΔV R ∼V GS4 ∼V 2 , the equation (38-a) can be established from Kirchhoff's law. Substituting the equation (27) with V GS3 and V GS4 of the equation (38-a), the equation (38-b) can be established. Term in the parenthesis of the equation (38-b), becomes independent of the differential input voltage ΔV. Expressing the term in the parenthesis as -b, ΔV R can be expressed with a linear equation (equation (38-c)). Assuming the current of the first and second resistors R 01 and R 02 of Fig. 5 are I R01 and I R02 , and the equation (39) is established on the basis of Kirchhoff's law with respect to the common junction, the voltage ΔV R at opposite ends of the resistors R 01 and R 02 is expressed by the equation (40), From the equations (39) and (40), the currents I R01 and I R02 can be expressed by the equation (41). From the equation (39) based on Kirchhoff's law, the differential output current ΔI is expressed by the equation (42-a). By substituting the equation (42-a) with I R01 and I R02 of the equation (41), the equation (42-b) can be established. By substituting ΔV R of the equation (42-b) with the equation (38-b), the equation (42-c) is established. Thus, a linear relational expression of the differential output current ΔI and the differential input voltage ΔV can be derived (equation (42-d). It should be noted that constants c and d are defined by equations (42-e) and (42-f). In the case where circuit elements arranged at symmetrical positions have the same characteristics, the equations (36-a), (36-b) and (43) are established. Then, the constant b becomes 0. Therefore, ΔV R becomes equal to ΔV, and ΔI becomes proportional to ΔV (equations (45-a) and (45-b)). Fig. 7 shows the input/output characteristics of the shown embodiment. R 00 = R 01 = R 02 ΔI 00 ' = 2 • I 03 = 2 • I 04 ΔV = V 1 - V 2 I 0 = I R01 + I R02 , I R01 = I 1 + I 03 , I R02 = I 2 + I 04 R 01 I R01 - R 02 I R02 = ΔV R I R01 = Δ V R + R 02 I 0 R 01 + R 02 , I R02 = R 01 I 0 - Δ V R R 01 + R 02 c = 2 R 01 + R 02 d = - R 01 - R 02 R 01 + R 02 I 0 - I 03 + I 04 + 2 b R 01 + R 02 The mutual conductance g m , non-linearity E and the range to be established are defined by the equations (46) to (48). The characteristic curve of the non-linearity E is illustrated in Fig. 8. β' = β 3 - β 4 V GS3 = V GS4 b = 0, d = 0 ΔV R = ΔV ΔI = Δ V R 00 (¦ΔI¦ ≤ I 00 - I 00 '), (¦ΔV¦ ≤ R 00 • (I 00 - I 00 ')) From the equation (47-b) and Figs. 7 and 8, it should be appreciated that even when the differential output current ΔI is increased according to increasing of the differential input voltage ΔV, the non-linearity E is not increased, and maintained 0 within the range defined by the equation (48). In the shown embodiment, it is possible to similarly handle the circuit even when the NMOSFET is replaced with the PMOSFET, PMOSFET is replaced with NMOSFET, and the direction of the constant current source is reversed. Next, discussion will be given for the operation in the case where the differential amplifier circuits of Fig. 27 are employed as the signal transmission circuits A 1 and A 2 of the shown embodiment of the differential voltage-to-current converter circuit. The non-inverting inputs of the differential amplifier circuits A 1 and A 2 are connected to first and second input terminals V 1 and V 2 , respectively. On the other hand, the inverting inputs are connected to the drain terminals of N 3 and N 4 . The outputs of the differential amplifier circuits A 1 and A 2 are connected to gate terminals of first and second NMOSFETs N 1 and N 2 . The input/output characteristics and the non-linearity E can be derived in the similar manner to the foregoing first embodiment. Also, the operation is as set forth above, the differential amplifier circuits A 1 and A 2 operate to maintain the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 . Namely, they compensate following up of the source terminals of N 3 and N 4 to the first and second input terminals and whereby stabilize the operation of the differential voltage-to-current converter circuit. The mutual conductance g m and the non-linearity E are defined by the equations (46-b) and (47-b). In the case where the differential amplifier circuits of Fig. 27 are employed as the signal transmission circuits A 1 and A 2 of the differential voltage-to-current converter circuit of Fig. 6, the non-inverting inputs of the differential amplifier circuits A 1 and A 2 are connected to first and second input terminals V 1 and V 2 , respectively. On the other hand, the inverting inputs are connected to the drain terminals of N 3 and N 4 . The outputs of the differential amplifier circuits A 1 and A 2 are connected to gate terminals of first and second PMOSFETs P 1 and P 2 . The input/output characteristics and the non-linearity E of the differential voltage-to-current converter circuit constructed as set forth above can be derived in the similar manner to the foregoing first embodiment. The differential amplifier circuits A 1 and A 2 operate to maintain the gate-source terminal voltages V GS3 and V GS4 of N 3 and N 4 . Namely, they compensate following up of the source terminals of N 3 and N 4 to the first and second input terminals and whereby stabilize the operation of the differential voltage-to-current converter circuit. The mutual conductance g m and the non-linearity E are defined by the equations (46-b) and (47-b). Figs. 9 and 10 shows the third embodiment of the differential voltage-to-current converter circuit of the present invention. Fig. 9 shows the differential voltage-to-current circuit which is constructed by replacing NMOSFETs N 1 and N 2 in the differential voltage-to-current converter circuit of Fig. 1 with PMOSFETs P 1 and P 2 . Also, Fig. 10 shows the embodiment, in which the PMOSFETs P 1 and P 2 of Fig. 2 with NMOSFETs N 1 and N 2 . The resistor 2R 0 is connected between the drain terminals of P 1 and P 2 or N 1 and N 2 of the differential pair, In Figs. 9 and 10, like circuit elements to those of Figs. 1 and 2 will be represented by the same reference numerals. Fig. 9 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 10 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. As the signal transmission circuits A 1 and A 2 in the shown embodiment, circuit constructions illustrated in Figs. 28 and 29 can be employed On the other hand, as the signal transmission circuits A 1 and A 2 in Fig. 10, the circuit illustrated in Fig. 28 may be employed. As the constant current source, various current-mirror circuits illustrated in Figs. 30 to 33 may be employed. The input/output characteristics and the non-linearity E of the shown embodiment can be derived in the similar manner to the first embodiment. Thus, equivalent characteristics to the first embodiment can be obtained. Figs. 11 and 12 shows the third embodiment of the differential voltage-to-current converter circuit of the present invention. Fig. 9 shows the differential voltage-to-current circuit which is constructed by replacing NMOSFETs N 1 and N 2 in the differential voltage-to-current converter circuit of Fig. 1 with PMOSFETs P 1 and P 2 . Also, Fig. 10 shows the embodiment, in which the PMOSFETs P 1 and P 2 of Fig. 2 with NMOSFETs N 1 and N 2 . The first and second resistors R 01 and R 02 are connected between the drain terminals of P 1 and P 2 or N 1 and N 2 of the differential pair, In Figs. 11 and 12, like circuit elements to those of Figs. 5 and 6 will be represented by the same reference numerals. Fig. 11 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 12 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. As the signal transmission circuits A 1 and A 2 in the shown embodiment of Fig. 11, circuit constructions illustrated in Figs. 28 and 29 can be employed On the other hand, as the signal transmission circuits A 1 and A 2 in Fig. 12, the circuit illustrated in Fig. 29 may be employed. As the constant current source, various current-mirror circuits illustrated in Figs. 30 to 33 may be employed. The input/output characteristics and the non-linearity E of the shown embodiment can be derived in the similar manner to the second embodiment. Thus, equivalent characteristics to the first embodiment can be obtained. Concerning the first to fourth embodiments of the present invention, it is regarded that the constant current I 0 connected to the common junction of the first and second resistors and the first and second constant currents I 01 and I 02 connected to the source terminals of the first and second MOSFETs are ideal constant currents. Also, it is assumed that respective currents satisfies the following equation, then these embodiments of the differential voltage-to-current converters may show equivalent characteristics. I 0 = 2I 01 = 2I 02 , R 0 = R 01 = R 02 On the other hand, the first and second signal transmission circuits A 1 and A 2 in the foregoing first to fourth embodiments of the invention may be constructed by source followers, voltage followers having amplification factor being 1 or so forth, in addition to the differential amplifiers and direct connection. As set forth in the first and second embodiments, in the differential voltage-to-current converter circuit according to the shown embodiments, the linearity of the input/output characteristics can be maintained even when the constant current sources I 01 to I 04 , MOSFETs N 1 to N 4 or P 1 to P 4 and so forth placed at symmetric positions on the circuit diagram do no have the same characteristics. Namely, even when the characteristics of each pair of circuit elements are not the same, the relationship between the differential input voltage ΔV and the voltage ΔV R at opposite ends of source (drain) resistor can be expressed by the general equation V R = ΔV + b (b: constant) as expressed in the equations (28-c) and (38-c). Therefore, the relationship between the differential input voltage ΔV and the differential output current ΔI can be expressed by the linear equation of ΔI = cΔV + d (c, d: constants) as expressed in the equations (30-c) and (42-c). Therefore, in either case, linearity can be maintained. Concerning the mutual conductance and the non-linearity E of the shown embodiments of the differential voltage-to-current converter circuits, the relationship expressed by the equations (33-b) and (34-b) or (46-b) and (47-b) within a range defined by the equation (49) or (50). (¦ ΔI ¦ ≦ I 01 + I 02 - I 03 - I 04 ) (¦ ΔV ¦ ≦ R 00 • (I 01 + I 02 - I 03 - I 04 )) (¦ ΔI ¦ ≦ I 0 - I 03 - I 04 ) (/Δ V / ≦ R 0 + R 01 2 • ( I 0 - I 03 - I 04 )) Figs. 34, 35, 36 and 37 show the circuit construction, and input/output characteristics of the fifth embodiment of the differential voltage-to-current converter circuit according to the present invention. The shown embodiment (Figs. 34 and 35) of the differential voltage-to-current converter circuit is constructed by connecting the first and second constant current sources I 01 and I 02 to the first and second MOSFETs (N 1 and N 2 or P 1 and P 2 ). One resistor 2R 0 is connected between the source terminals of the first and second MOSFETs. Fig. 34 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 35 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. The source terminals of the third and fourth MOSFETs are connected to the source terminals of the first and second MOSFETs. The drain terminals of the third and fourth MOSFETs are connected to respective input sides of the first and second current mirror circuits M 1 and M 2 . The output terminals of the first and second current-mirror circuits M 1 and M 2 are connected to the third and fourth constant current sources and gate terminals of the first and second MOSFETs. Accordingly, when the input V 1 is risen for example, the gate-source terminal voltage V GS3 is temporarily increased. Associating therewith, the drain current of N 3 and the input current of M 1 are also risen. Here, since I 03 is constant, the gate voltage of N 1 is swiftly risen. Therefore, I 1 is increased. Subsequently, the voltages at the source terminals of N 1 and N 2 are risen. This increasing of V GS3 can be suppressed. As can be appreciated, such operation is a kind of feedback operation to make the operation of the differential voltage-to-current converter circuit stable. In short, as far as M 1 is in operation in the saturating region, the gate voltage of N 1 converges to the voltage to maintain the current flowing through N 2 constant. Therefore, the voltage V GS3 between V 1 and the source terminal of N 1 and the voltage V GS4 between V 2 and the source terminal of N 2 become constant. As set forth above, in the same reason, the output current and linearity equivalent to the first and second embodiments can be obtained. Figs. 38 to 41 show the circuit construction, and input/output characteristics of the sixth embodiment of the differential voltage-to-current converter circuit according to the present invention. The shown embodiment of the differential voltage-to-current converter circuit is constructed by connecting one terminals of the first and second resistors R 01 and R 02 to the source terminals of the first and second MOSFETs (N 1 and N 2 or P 1 and P 2 ). The other terminals of the first and second resistors R 01 and R 02 are connected in common. The constant current source I0 is connected to the junction of the common connection between the first and second resistors R 01 and R 02 . Fig. 38 shows the circuit construction of a sink type MOS differential voltage-to-current converter circuit and Fig. 39 shows the circuit construction of a source type MOS differential voltage-to-current converter circuit. Here, respective signs in Figs. 38 and 39 have the same meaning to the corresponding signs in Fig. 16 which illustrates the second prior art. N 3 and N 4 represent third and fourth NMOSFETs. The constant current source can be constructed as shown in Figs. 30, 31, 32 and 33. Discussion will be given hereinafter with respect to the operation of the circuit construction of Fig. 38. The source terminals of the third and fourth MOSFETs are connected to the source terminals of the first and second MOSFETs. The drain terminals of the third and fourth MOSFETs are connected to respective input sides of the first and second current mirror circuits M 1 and M 2 . The output terminals of the first and second current-mirror circuits M 1 and M 2 are connected to the third and fourth constant current sources and the gate terminals of the first and second MOSFETs. Accordingly, when the input V 1 is risen for example, the gate-source terminal voltage V GS3 is temporarily increased. Associating therewith, the drain current of N 3 and the input current of M 1 are also risen. Here, since I 03 is constant, the gate voltage of N 1 is swiftly risen. Therefore, I 1 is increased. Subsequently, the voltages at the source terminals of N 1 and N 3 are risen. This increasing of V GS3 can be suppressed. As can be appreciated, such operation is a kind of feedback operation to make the operation of the differential voltage-to-current converter circuit stable. In short, as far as M 1 is in operation in the saturating region, the gate voltage of N 1 converges to the voltage to maintain the current flowing through N 2 constant. Therefore, the voltage V GS3 between V 1 and the source terminal of N 1 and the voltage V GS4 between V 2 and the source terminal of N 2 become constant. As set forth above, in the same reason, the output current and linearity equivalent to the first and second embodiments can be obtained. As set forth above, the MOS differential voltage-to-current converter circuit according to the present invention establishes the negative feedback with the shown construction, in which the source (drain) resistors are provided, the source(drain terminals of the first and second MOSFETs are connected to the source terminals of the third and fourth MOSFETs, the drain terminals of the third and fourth MOSFETs are respectively connected to the input sides of the first and second current mirror circuits M 1 and M 2 , and the outputs of the current-mirror circuits M 1 and M 2 are connected to the constant current source and the gate terminals of the first and second MOSFETs. As a result, as long as the operation is taken placed in the region where M 1 and M 2 are saturated, the gate voltage of N 1 and N 2 are converged at the voltage where the current I 03 flowing through N 3 and the current I 04 flowing through N 4 are equal to each other so that V 1 , the voltage V GS3 between the source terminal of the N 1 and the voltage V GS4 between V 2 and the voltage V 2 and the source terminal of N 4 become constant. Furthermore, there is provided the first and second signal transmission means which has the inputs connected to the respective of the first and second input terminals and/or to the drain terminals of the third and fourth MOSFETs, and the outputs connected to respective gate terminals of the first and second MOSFETs. By the presence of the signal transmission means, the mutual conductance g m of the differential voltage-to-current converter circuit can be determined only by the resistance value 2R 0 , R 01 + R 02 between the source (drain) terminals. Also, even when the differential output current is increased associating with increasing of the differential input voltage, the non-linearity E can be held 0. Therefore, with the differential current-to-voltage converter circuit according to the present invention, it becomes possible to avoid increasing of non-linearity due to influence of various property of the differential MOSFET (such as, non-linearity of I D -V GS characteristics, fluctuation of the gain coefficient β, variation of the threshold voltage V T due to backgate effect, saturation of MOS due to end channel effect and so forth, variation of the I D -V DS characteristics within the non-saturated range and so forth), within a predetermined range of the differential input voltage. Characteristics variation factor of the MOSFET is quite large in comparison with that of the bipolar transistor and is specific to the MOSFET. Conventionally, such characteristics variation was inevitable in the MOSFET circuit. According to the present invention, even when the circuit elements located at symmetric positions on the circuit diagram do not have the same characteristics, the relationship between the differential input voltage ΔV and the voltage ΔV R at opposite ends of the source (drain) resistor and the relationship between the differential input voltage ΔV and the differential output current ΔI can be maintained linear without depending upon the characteristics variation of the MOSFETs. Therefore, the linearity of the differential voltage-to-current converter can be significantly improved. Furthermore, the differential voltage-to-current converter circuit can be fabricated through a MOS process, which can simply the fabrication process contributing lowering of the production cost. Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the scope of the present invention as defined in the claims. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set out in the appended claims.

Claims: A MOS differential voltage-to-current converter circuit, comprising: first and second MOS transistors (N 1 , N 2 , P 1 , P 2 ); a resistor (2R 0 ) connected between the sources of said first and second MOS transistors; a first constant current source (I 0 ) for supplying operation current for said first and second MOS transistors; third and fourth MOS transistors (N 3 , N 4 ) having sources respectively connected to the source of said first and second MOS transistors and receiving a differential input voltage at the gates thereof; second and third constant current sources (I 03 , I 04 ) for supplying operation currents for said third and fourth MOS transistors, characterized in that said second and third constant current sources are connected to the drains of said third and fourth MOS transistors (N 3 , N 4 ), respectively, in such a way that the voltage between the gate terminal and the source terminal of both said third and fourth transistors (N 3 , N 4 ) are constant; and first and second signal transmission means (A 1 , A 2 ) are provided for transmitting drain outputs of said third and fourth MOS transistors (N 3 , N 4 ) to the respective gates of said first and second MOS transistors (N 1 , N 2 , P 1 , P 2 ) for taking the current flowing through said first and second MOS transistors as a differential output. A MOS differential voltage-to-current converter circuit as set forth in claim 1, wherein said first and second signal transmission means (A 1 , A 2 ) comprises one of an amplifier circuit, an attenuation circuit and a voltage follower circuit. A MOS differential voltage-to-current converter circuit as set forth in claim 1, comprising: a first differential amplifier circuit forming the first transmission means (A 1 ) and receiving a gate input and a drain output of said third MOS transistor (N 3 ) as inputs and applying an output as said differential output to the gate of said first MOS transistor; and a second differential amplifier circuit forming the second transmission means (A 2 ) and receiving a gate input and a drain output of said fourth MOS transistor (N 4 ) as inputs and applying an output as said differential output to the gate of said second MOS transistor for taking the current flowing through said first and second MOS transistors as a differential output. A MOS differential voltage-to-current converter circuit as set forth in claim 1, comprising: a first current-mirror circuit (M 1 ) receiving the drain output of said third MOS transistor (N 3 ) as a current input and having a current output terminal connected to the gate of said first MOS transistor (N 1 ); and a second current-mirror circuit (M 2 ) receiving the drain output of said fourth MOS transistor (N 4 ) as a current input and having a current output terminal connected to the gate of said second MOS transistor (N 2 ) for taking the current flowing through said first and second MOS transistors as a differential output. A MOS differential voltage-to-current converter circuit as set forth in claim 4, said second and third constant current sources (I 03 , I 04 ) respectively sinking the output current of said first and second current-mirror circuits. A MOS differential voltage-to-current converter circuit as set forth in claim 1, 3 or 4, wherein said first constant current source (I 0 ) comprises two constant current sources (I 01 , I 02 ) respectively supplying operation currents to respective of said first and second MOS transistors. A MOS differential voltage-to-current converter circuit as set forth in claim 1, 3 or 4, wherein all of said first to fourth MOS transistors (N 1 , N 2 , N 3 , N 4 ) are transistors of the same conductive type. A MOS differential voltage-to-current converter circuit as set forth in claim 1, 3 or 4, wherein said first and second MOS transistor (P 1 , P 2 ), and said third and fourth MOS transistors (N 3 , N 4 ) have mutually opposite conductive types. A MOS differential voltage-to-current converter circuit as set forth in claim 1, 3 or 4, wherein said resistor (2R 0 ) comprises first and second resistor elements (R 01 , R 02 ) which are connected in series, and said first constant current source (I 0 ) supplies the operation current at the junction of series connection of said first and second resistor elements.

Inventors: DEGUCHI KOJI, DEGUCHI, KOJI, DEGUCHI, KOJI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03F1
IPC codes: H03F1, H03F3