ACTIVE MATRIX SUBSTRATE AND THIN FILM TRANSISTOR, AND METHOD OF ITS MANUFACTURE

Abstract: In forming a thin film transistor (620) whose OFF-current characteristics are improved, the source and drain regions (602 and 603) of low impurity concentration are formed. In this process, all the ions (indicated by arrow Ion-1) of around 80 keV energy produced from a mixed gas (doping gas) containing 5% PH₃ and the rest of H₂ gas, are implanted into a polycrystalline silicon film (604) so that the concentration of impurities in a range of 3 x 10¹³/cm² to 1 x 10¹⁴/cm² in terms of P⁺ ions. Then all the ions (indicated by arrow Ion-2) of about 20 keV energy produced from a doping gas of pure hydrogen are implanted into a low concentration region (604a) so that the concentration of impurities is in a range of 1 x 10¹⁴/cm² to 1 x 10¹⁵/cm² in terms of H⁺ ions. After that, the impurities are activated by thermally treating the low concentration region (604a) in a nitrogen atmosphere at a temperature of approximately 300 °C for approximately one hour.

Description: FIELD OF THE INVENTION The present invention relates to an active matrix circuit board, and method of manufacturing it, and relates particularly to a technology improving the electrical characteristics of the thin-film transistor. DESCRIPTION OF THE PRIOR ART Thin-film transistors (hereafter "TFT") using a polycrystalline silicon film are used as pixel transistors in liquid crystal display panels and other active matrix circuit boards. Of available liquid crystal display panels, built-in drive circuit type (built-in peripheral circuit type) active matrix circuit boards in which the drive circuit is formed using TFT in the area peripheral to the pixel area are used in liquid crystal display panels for viewfinders and projectors due to the packaging technology problem that making electrical connections to narrow pitch terminals is difficult. As a result, TFT for the drive circuit area and TFT for the pixel area are both formed on a single active matrix circuit board. Of these TFT, a low OFF current is required in the TFT of the pixel area so that the charge written through the pixel electrodes can be held. Polycrystalline silicon TFT, however, may use an offset gate structure wherein a source-drain area is provided at a position separated from the edge of the gate electrodes because the OFF current is high. In addition, a low concentration area may be provided at the edge of the drain area, and a drain structure (LDD structure) used with the field strength in this area reduced. The following manufacturing method is conventionally used to manufacture thin-film transistors with such a structure. When n-channel type TFT 1200a in the drive circuit area, p-channel type TFT 1200b in the drive circuit area, and n-channel type TFT 1200c in the pixel area are formed as shown in Fig. 23 (a) from left to right facing the figure, first, second, and third silicon films 1202, 1202, 1203 are first formed on the surface side of substrate 1201. The surface sides of the first, second, and third silicon films 1202, 1202, 1203 are then covered by gate insulation film 1211. After that, a conductive film forming the gate electrode is formed on the surface side of the gate insulation film 1211, this is masked with resist 1213 for patterning, and gate electrode 1212 is formed. Next, as indicated by arrow 1214, an impurity that will be the donor is ion implanted, and source-drain area 1207 is formed. Next, gate electrode 1212 is over-etched with resist 1213 as the mask, and gate electrode 1212 is narrowed as shown in Fig. 23 (b). As a result, the length of gate electrode 1212 is shorter than the length of the area (channel formation area) in first, second, and third silicon films 1202, 1202, 1203 in which the impurity is not introduced, and the offset gate structure is formed. Next, as shown in Fig. 23 (c), an impurity that will be the acceptor is ion implanted (arrow 1221) to the second silicon film 1202 with the first and third silicon films 1202, 1203 covered by resist 1215. Because the donor impurity was previously introduced to second silicon film 1202, the acceptor impurity is introduced at a high concentration. It is to be noted that when TFT 1200a and 1200c are formed with an LDD structure, resist 1215 is removed after injecting the acceptor impurity, and a donor impurity is ion injected at an appropriate dosage. In the TFT thus formed, the OFF current level can be sufficiently lowered because concentration of the electrical field at the drain edge can be alleviated due to the offset structure or LDD structure. The following problems exist with the conventional manufacturing method thus described, however. First, even though TFT electrical characteristics vary with the gate length, this method sets the gate length by over-etching the gate electrode, and it is therefore difficult to control the gate length. For example, when a gate electrode composed of polycrystalline silicon is plasma etched, it is possible to determine the completion of etching because the plasma emission strength changes at the etching end point if patterning is normal, but it is difficult to reliably control the end point because the plasma emission strength does not change with over-etching. In addition, it is also difficult to control over-etching when over-etching is controlled by the etching time because the etching speed varies slightly with the operating conditions, etc., of the etching equipment. As a result, the ON current characteristic and other electrical characteristics of TFT manufactured with conventional methods inevitably vary due to variations in gate length and offset length. Variations of this type are fatal defects in drive circuit TFT formed by the same process. Due to over-etching, it is also difficult to increase device pitch. More specifically, the active matrix circuit board must be designed with a large pattern dimension to accommodate variations in gate electrode over-etching, and designs with such large margins result in large waste in the active matrix circuit board design. In addition, conventional manufacturing methods are not suited to high resolution liquid crystal display panels, and are an obstruction to reducing the basic pattern dimension of the active matrix circuit board from 5 µm to 2 µm or 3 µm, or even smaller dimensions. Second, high temperature processing exceeding 600°C is required to activate the ion injected impurity in LDD structures. With such high temperature processing, however, it is not possible to use low-cost glass substrates. As a result, conventional manufacturing methods also interfere with increasing display panel screen size and reducing display panel cost. Furthermore, conventional ion injection technologies are not well suited to processing large circuit boards because of the narrow injection area. Technologies for implanting the generated ions without mass separation have been studied with the objective of solving these problems. For example, a method for using a mixture of an impurity gas diluted with hydrogen as the doping gas and implanting the ions generated from this mixture without mass separation has been studied, and the impurity has been activated at a relatively low temperature of about 300°C. However, this method cannot activate a silicon film implanted with a low ion concentration where the impurity concentration is 1 x 10 19 /cm 3 or less, and it is still not possible to manufacture an LDD structure TFT in a low temperature process. An active matrix circuit board according to the prior art portion of claim 1 is disclosed in EP-A-0 342 925. JP-A-4-293023 discloses a similar active matrix circuit board in which the impurity density in the channel area of TFTs in the pixel area is greater than that in the channel area of TFTs in the drive circuit area. The document JP-A-63-204769 discloses a TFT having an LDD structure with source and drain regions each composed of two portions, a first portion next to the channel and a second portion contiguous to the first portion on the side remote from the channel. The second portions have a higher impurity concentration and are used as contact regions for contact with a source and drain electrode, respectively. The document EP-A-0 544 229 (prior art according to Article 54(3) EPC) discloses an active matrix circuit board having a drive circuit area equipped with a CMOS circuit comprising a first thin-film transistor of a first conductivity type and a second thin-film transistor of a second conductivity type, and a pixel area comprising a third thin-film transistor of said first conductivity type, wherein said source-drain area is not formed self-aligned to the gate electrode. All three transistors have an LDD structure with The low concentration region of the source-drain area of pixel transistor is lower than that of the first transistor though not specified. The object of the present invention is to improve the structure of the source-drain area and the manufacturing process therefor, and to thus achieve an active matrix circuit board, a thin-film transistor, and a conductive silicon film in which the OFF current characteristics can be improved, and a manufacturing method therefor. DESCRIPTION OF THE INVENTION This object is achieved with an active matrix circuit board as claimed in claim 1 and a method as claimed in claim 6, respectively. Preferred embodiments of the invention are subject-matter of the dependent claims. The first conductive type and second conductive type are opposite conductive types, meaning that if the first conductive type is an n-type, then the second conductive type is a p-type. Inversely, if the first conductive type is a p-type, then the second conductive type is an n-type. In addition, "impurity ions" in this invention mean ions that are either donors or acceptors. Details and advantages of the present invention will be explained below with reference to embodiments and the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simple block diagram of an active matrix circuit board with a built-in drive circuit. Fig. 2 is a simple block diagram typically showing the structure of the pixel area of an active matrix circuit board. Fig. 3 is a cross sectional diagram typically showing the basic structure of a liquid crystal display panel. Fig. 4 is a cross sectional diagram typically showing the TFT structure formed in the pixel area and drive circuit area of an active matrix circuit board according to the first embodiment of the present invention. Fig. 5 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 4. Fig. 6 is a graph showing the relationship between the gate voltage Vg and drain current Id when the impurity concentration of the source-drain area is varied in an n-channel type TFT. Fig. 7 is a cross sectional diagram typically showing the TFT structure formed in the pixel area and drive circuit area of an active matrix circuit board according to the second embodiment of the present invention. Fig. 8 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 7. Fig. 9 is a cross sectional diagram typically showing the TFT structure formed in the pixel area of an active matrix circuit board according to the third embodiment of the present invention. Fig. 10 is a graph showing the relationship between the ion dosage to the source-drain areas and the contact resistance of the ITO and source-drain area. Fig. 11 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 9. Fig. 12 is a simple structural diagram of the ion implantation apparatus used in the manufacturing method of the conductive silicon film of the fourth and fifth embodiments of the invention. Fig. 13 is a graph showing the relationship between hydrogen ion dosage to the polycrystalline silicon film and sheet resistance in the manufacturing method of an n-type conductive silicon film according to the fourth embodiment of the invention. Fig. 14 is a graph showing the relationship between phosphorus ion dosage in the first doping process and sheet resistance in the manufacturing method of an n-type conductive silicon film according to the fourth embodiment of the invention. Fig. 15 is a graph showing the relationship between hydrogen ion dosage to the polycrystalline silicon film and sheet resistance in the manufacturing method of a p-type conductive silicon film according to the fifth embodiment of the invention. Fig. 16 is a graph showing the relationship between boron ion dosage in the first doping process and sheet resistance in the manufacturing method of a p-type conductive silicon film according to the fifth embodiment of the invention. Fig. 17 is a cross sectional diagram typically showing the TFT structure formed in the pixel area and drive circuit area of an active matrix circuit board according to the sixth embodiment of the present invention. Fig. 18 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 17. Fig. 19 is a cross sectional diagram typically showing the TFT structure formed in the pixel area and drive circuit area of an active matrix circuit board according to the seventh embodiment of the present invention. Fig. 20 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 19. Fig. 21 is a cross sectional diagram typically showing the TFT structure formed in the pixel area and drive circuit area of an active matrix circuit board according to the eighth embodiment of the present invention. Fig. 22 shows a process flow of the manufacturing method of the active matrix circuit board in Fig. 21. Fig. 23 shows a process flow of the manufacturing method of conventional TFT. OPTIMUM CONFIGURATIONS FOR ACHIEVING THE INVENTION First embodiment Before describing the structure of an active matrix circuit board according to the present embodiment, the basic structure of an active matrix circuit board with a built-in drive circuit and used in liquid crystal display panels is described. Fig. 1 is a simple block diagram of an active matrix circuit board with a built-in drive circuit, Fig. 2 is a simple block diagram typically showing the structure of the pixel area of an active matrix circuit board, and Fig. 3 is a cross sectional diagram typically showing the basic structure of a liquid crystal display panel. In Fig. 1, active matrix circuit board 10 is divided into a pixel area 10a and drive circuit areas 10b, 10c (peripheral circuit part). Pixel region 13 is divided and formed in pixel area 10a by scanning lines (gate lines) 11a, 11b... (11) connected to drive circuit area 10b (scanning line drive circuit), and data lines 12a, 12b... (12) connected to drive circuit area 10c (data line drive circuit) as shown in Fig. 2. TFT 10d, which switches between a state connecting and a state interrupting the data line 12 side and the pixel electrode side based on the scanning signal from scanning line 11, is formed in pixel region 13. A CMOS circuit is also formed in drive circuit areas 10b, 10c by thin-film transistors of a different conductive type. Of these thin-film transistors, a small OFF current characteristic is required in TFT 10d of pixel area 10a so that a sufficient charge can be held in liquid crystal capacitance 10f. Because high speed operation compatible with high quality display operation is required in the thin-film transistor of drive circuit areas 10b, 10c, a thin-film transistor with a self-alignment structure is generally used in drive circuit areas 10b, 10c. It is to be noted that, as shown in Fig. 2, there are cases in which storage capacitance 10e is formed in pixel region 13, and this storage capacitance 10e may be constructed overlaid with part of the preceding scanning line 11 as the top pole and part of the drain electrode of TFT 10d as the bottom pole. Therefore, if the OFF current of TFT 10d of pixel area 10a is large, it is necessary to increase storage capacitance 10e, and the aperture ratio of pixel region 13 is decreased. Note that liquid crystal capacitance 10f is the capacitance when active matrix circuit board 10 and counter circuit board 16 on which counter electrode 15 is formed are placed in opposition sandwiching liquid crystals 17 as shown in Fig. 3. Thus, three types of thin-film transistors, including a pair of opposite conductive type thin-film transistors in the drive circuit area and a thin-film transistor in the pixel area, are formed because the characteristics required in the thin-film transistors are different in a built-in drive circuit type active matrix circuit board 10. The following structure and manufacturing method are therefore used in the present invention as will be described below so that different types of thin-film transistors can be efficiently manufactured. Fig. 4 is a cross sectional diagram typically showing, of the thin-film transistors (hereafter "TFT") formed in the active matrix circuit board of the present embodiment, the structure of the TFT formed in the pixel area and the n-channel type TFT and p-channel type TFT formed in the drive circuit area. In Fig. 4, in active matrix circuit board 100 of the present embodiment, n-channel type TFT-A of the drive circuit area, p-channel type TFT-B of the drive circuit area, and n-channel type TFT-C of the pixel area are formed on a transparent insulated substrate 101 in order from the left side as looking at the figure. The CMOS circuit is formed in the drive circuit area by TFT-A and TFT-B. Gate insulation film 114 is formed on the surface side of channel formation area 111 and source-drain areas 112, 113, and gate electrode 115 is formed on the surface side of this gate insulation film 114 in TFT-A. Source-drain areas 112, 113 are n + high concentration areas with an impurity concentration equal to or greater than 1 x 10 19 /cm 3 , e.g., 1 x 10 20 /cm 3 , and are formed self-aligned to gate electrode 115. Gate insulation film 124 is formed on the surface side of channel formation area 121 and source-drain areas 122, 123, and gate electrode 125 is formed on the surface side of this gate insulation film 124 in TFT-B. Source-drain areas 122, 123 are p + high concentration areas with an impurity concentration equal to or greater than 1 x 10 19 /cm 3 , e.g., 1 x 10 20 /cm 3 , and are formed self-aligned to gate electrode 125. Gate insulation film 134 is formed on the surface side of channel formation area 131 and source-drain areas 132, 133, and gate electrode 135 is formed on the surface side of this gate insulation film 134 in TFT-C. Source-drain areas 132, 133 are formed as n - low density areas with an impurity concentration equal to or less than 1 x 10 19 /cm 3 , e.g., 5 x 10 18 /cm 3 , and are formed self-aligned to gate electrode 135. Therefore, a large ON current can be obtained in TFT-A and TFT-B of the drive circuit area. In addition, the OFF current is small in the TFT-C of the pixel area because source-drain areas 132, 133 are low concentration of impurities. As a result, high resolution, high quality display can be achieved in a liquid crystal display panel using the active matrix circuit board 100 of this embodiment because high speed operation is possible in the drive circuit area and the written charge can be sufficiently maintained in the pixel area. The manufacturing method of active matrix circuit board 100 of such a structure is described with reference to Fig. 5. Fig. 5 shows a process flow of the manufacturing method of the active matrix circuit board of the present embodiment. First, as shown in Fig. 5 (a), after forming a polycrystalline silicon film on the surface side of insulated substrate 101, this is patterned to form silicon films 110, 120, 130. Silicon film 110 is a first silicon film for forming TFT-A in the drive circuit area, and silicon film 120 is a second silicon film for forming TFT-B in the drive circuit area. Silicon film 130 is a third silicon film for forming TFT-C in the pixel area (first process). Next, gate insulation films 114, 124, 134 are formed on the surface side of each silicon film 110, 120, 130 (second process). Next, after forming a polycrystalline silicon film on the surfaces of gate insulation films 114, 124, 134 (the entire surface of insulated substrate 101), a high concentration impurity is introduced into it. The polycrystalline silicon film into which an impurity was introduced is then patterned using photoetching technologies to form gate electrodes 115, 125, 135. The gate lines are simultaneously formed with the same materials when forming gate electrodes 115, 125, 135 (third process). It is to be noted that because the etching end point can be positively confirmed due to dry etching using CF 4 plasma being used in the present embodiment for patterning the polycrystalline silicon film, the dimensions of the silicon film after patterning can be precisely controlled. Next, as shown by arrow P + , low concentration phosphorus ions are implanted at a 5 x 10 13 /cm 2 dose to silicon films 110, 120, 130 using gate electrodes 115, 125, 135 as a mask (low concentration area formation process). As a result, low concentration areas 110a, 120a, 130a with a 5 x 10 18 /cm 3 impurity concentration are formed self-aligned to gate electrodes 115, 125, 135 in silicon films 110, 120, 130. Low concentration area 130a becomes source-drain areas 132, 133 of TFT-C without further ion implanting in the following processes. In addition, that part of silicon film 130 positioned directly below gate electrode 135 becomes channel formation area 131. Next, as shown in Fig. 5 (b), after masking the side with silicon films 120, 130 with resist 140, high concentration phosphorus ions are implanted at a 1 x 10 15 /cm 2 dose to silicon film 110 (low concentration area 110a) as shown by arrow P + (fourth process). As a result, low concentration area 110a becomes source-drain area 112, 133 (n + high density area) with a 1 x 10 20 /cm 3 impurity concentration formed self-aligned to gate electrode 115. In addition, that part of silicon film 110 positioned directly below gate electrode 115 becomes channel formation area 111. Next, as shown in Fig. 5 (c), after masking the sides with silicon films 110, 130 with resist 150, high concentration boron ions are implanted at a 1 x 10 15 /cm 2 dose to silicon film 120 (low concentration area 120a) as shown by arrow B + (fourth process). As a result, low concentration area 120a becomes source-drain areas 122, 123 (p + high density area) with a 1 x 10 20 /cm 3 impurity concentration formed self-aligned to gate electrode 125. In addition, that part of silicon film 120 positioned directly below gate electrode 125 becomes channel formation area 121. In this way, even when three types of TFT are formed on one active matrix circuit board 100, a low concentration impurity is also implanted to the drive circuit area side in the process forming the low concentration area on the pixel area side, and a high concentration area is formed there by the high concentration impurity implanted to the drive circuit area side. Therefore, the impurity concentration of each area can be separately controlled while holding the number of masking operations to a minimum. Therefore, a TFT having an optimal structure can be manufactured by the manufacturing method of the present embodiment without side etching the gate electrode. As a result, the display definition of the liquid crystal display panel can be improved because the ON current characteristic of the drive circuit area TFT and the OFF current characteristic of the pixel area TFT can be improved, and the electrical characteristics are stable. The electrical characteristics of the TFT-A and TFT-C formed in this way are described with reference to Fig. 6. Fig. 6 is a graph showing the relationship between the gate voltage Vg and drain current Id when the impurity concentration of the source-drain area is varied in an n-channel type TFT. In Fig. 6, solid line 5E13 shows the characteristics of the TFT with phosphorus implanted at a 5 x 10 13 /cm 2 dose to the source-drain area. Solid line 1E14 shows the characteristics of the TFT with phosphorus implanted at a 1 x 10 14 /cm 2 dose to the source-drain area. Solid line 5E14 shows the characteristics of the TFT with phosphorus implanted at a 5 x 10 15 /cm 2 dose to the source-drain area. As will be known by comparing these characteristics, the ON current drops because the electrical resistance of the source-drain area increases as the dose is reduced. Furthermore, the OFF current drops because electrical field strength between the drain area and gate electrode is decreased in addition to the electrical resistance of the source-drain area increasing as the dose is reduced. Therefore, it is sufficient to form the source-drain area as a low concentration area in the pixel area TFT where a small OFF current is required. Because a low OFF current is required in the TFT-C in the pixel area through the gate voltage Vg range from 0 V to approximately -10 V, the impurity dose to the source-drain areas 132, 133 is less than or equal to 1 x 10 14 /cm 2 , and preferably less than 5 x 10 13 /cm 2 . However, because the level of the TFT-C OFF current differs according to the setting conditions and the specifications of the liquid crystal display panel in which active matrix circuit board 100 is mounted, the impurity concentration of source-drain areas 132, 133 is set to an optimal level according to the specifications and setting conditions. The ON current of TFT-A and TFT-B in the drive circuit area is generally, however, preferably greater, and when gate voltage Vg is 10 V, drain current Id must be 10 µA or greater. Therefore, the impurity dose to the source-drain area of TFT-A and TFT-B must be approximately 1 x 10 14 /cm 2 or greater. It is to be noted that the TFT ON current and OFF current are also dependent on the film thickness of the polycrystalline silicon film in the channel formation area and the film thickness of the gate insulation film, in addition to the impurity concentration of the source-drain area. Furthermore, the electrical resistance of the source-drain area affecting the ON current and OFF current is also dependent on the film thickness and polycrystallinity of the source-drain area. Moreover, in addition to the dosage, the impurity concentration of the source-drain area is also affected by the ion energy during implantation and the film thickness of the gate insulation film. Therefore, the dosage is set as may be required with consideration for the ion energy and the film thickness of the gate insulation film. Second embodiment The structure of an active matrix circuit board according to the present embodiment is basically the same as the structure of the active matrix circuit board according to the first embodiment, and only that a pad area, which is a high concentration area, is formed in the source-drain area differs. Therefore, parts with functionality common to the first embodiment are identically labelled, and further identification in the figures and detailed description are omitted. Fig. 7 is a cross sectional diagram typically showing the structure of the pixel area TFT formed in an active matrix circuit board according to the present embodiment. In active matrix circuit board 100a of this embodiment, source-drain areas 112, 113 of TFT-A are n + high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, e.g., 1 x 10 20 /cm 3 , and are formed self-aligned to gate electrode 115. Source-drain areas 112, 113 are composed of thin upper layer source-drain areas 112a, 113a and thick bottom layer source-drain areas 112b, 113b formed from a polycrystalline silicon film the same as channel formation area 111. Source-drain areas 122, 123 of TFT-B are p + high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, e.g., 1 x 10 20 /cm 3 , and are formed self-aligned to gate electrode 125. Source-drain areas 122, 123 are composed of thin upper layer source-drain areas 122a, 123a and thick bottom layer source-drain areas 122b, 123b formed from a polycrystalline silicon film the same as channel formation area 121. Source-drain areas 132, 133 of TFT-C are formed self-aligned to gate electrode 115, and are composed of thin upper layer source-drain areas 132a, 133a and thick bottom layer source-drain areas 132b, 133b formed from a polycrystalline silicon film the same as channel formation area 131. Of these, the top layer source-drain areas 132a, 133a are n - low concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or less, e.g., 5 x 10 18 /cm 3 . Relative to this layer, the bottom layer source-drain areas 132b, 133b are n + high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, e.g., 1 x 10 20 /cm 3 . In TFT-A and TFT-B of the drive circuit area thus formed, source-drain areas 112, 113, 122, 123 are formed self-aligned to gate electrodes 115, 125, and, moreover, are formed as high concentration areas with a low electrical resistance. Furthermore, because source-drain areas 112, 113, 122, 123 are formed in two layers with a thick film thickness, the electrical resistance is low. Therefore, a high ON current can be obtained in TFT-A and TFT-B of the drive circuit area. In addition, because the film thickness is thick and source-drain areas 132b, 133b, which are high concentration areas, are formed in source-drain areas 132, 133 of the TFT-C of the pixel area, the electrical resistance there is low and the ON current is thus high. Regardless of this, however, that part of source-drain areas 132, 133 near the edge of gate electrode 135 in the TFT-C of the pixel area is the thin film thickness, low concentration area source-drain areas 132a, 133a, and a sufficiently low OFF current can therefore be obtained. As a result, high speed operation is possible in the drive circuit area and the written charge can be sufficiently maintained in the pixel area. In the manufacturing method of active matrix circuit board 100a thus constructed, after forming a thick film thickness polycrystalline silicon film on the surface side of insulated substrate 101, this is patterned to form silicon films 161, 162, 163 for forming source-drain areas 112b, 113b, 122b, 123b, 132b, 133b of the bottom layer as shown in Fig. 8 (a). Next, as shown in Fig. 8 (b), high concentration boron ions are implanted to silicon film 162 at a 1 x 10 15 /cm 2 dose with silicon films 161, 163 masked by resist 164 to form source-drain areas 122b, 123b of the bottom layer. Next, as shown in Fig. 8 (c), high concentration phosphorus ions are implanted to silicon films 161, 163 at a 1 x 10 15 /cm 2 dose with silicon film 162 masked by resist 165 to form source-drain areas 112b, 113b, 132b, 133b of the bottom layer. Heat treatment is then applied to activate the implanted impurity. This activation may be applied after forming the other component areas during the heat treatment applied to activate those areas. Next, as in the process described in the first embodiment with reference to Fig. 5 (a), after forming a thin polycrystalline silicon film over the entire surface of insulated substrate 101, it is patterned to form silicon films 110, 120, 130. Thereafter, the same processes described in the first embodiment with reference to Figs. 5 (a) to Fig. 5 (c), including formation of the gate insulation film and gate electrodes on the surface side of silicon films 110, 120, 130, are applied, and further description is therefore omitted. It is to be noted that because high concentration boron ions are implanted to silicon film 120 using resist 150 covering the TFT-A and TFT-C formation areas in the following processes as shown in Fig. 5 (c), the process shown in Fig. 8 (b) may be omitted and the bottom layer source-drain areas 122b, 123b formed in the process shown in Fig. 5 (c). By means of this method, the increase in the number of processes can be held to a minimum even when forming different conductive type pads (source-drain areas 112b, 113b, 122b, 123b, 132b, 133b of the bottom layer). Third embodiment The structure of an active matrix circuit board according to the present embodiment is basically the same as the structure of the active matrix circuit board according to the first embodiment, and only the structure of the TFT in the pixel area differs. Therefore, parts with functionality common to the first embodiment are identically labelled, and further identification in the figures and detailed description are omitted. Fig. 9 is a cross sectional diagram typically showing the structure of the TFT of the pixel area formed in an active matrix circuit board according to the present embodiment. In active matrix circuit board 200 of this embodiment, the n-channel type TFT-C of the pixel area is formed over transparent insulated substrate 101 in Fig. 9, and n-channel type TFT-A and p-channel type TFT-B of the drive circuit area are formed over the same insulated substrate 101 as shown in Fig. 4. As described in the first embodiment, source-drain areas 112, 113, 122, 123 of TFT-A and TFT-B are high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, and are formed self-aligned to gate electrodes 115, 125. Again, in Fig. 9, gate insulation film 234 is formed on the surface side of source-drain areas 232, 233 and channel formation area 231 in TFT-C, and gate electrode 235 is formed on the surface side of this gate insulation film 234. Layer insulation film 260 is formed on the surface side of gate electrode 235, source electrode 271 is connected to source-drain area 232 through the first contact hole 261, and pixel electrode 272 is connected to source-drain area 233 through second contact hole 262. In this embodiment, those parts of source-drain areas 232, 233 corresponding to the openings of first contact hole 261 and second contact hole 262 are high concentration contact areas 232a, 233a with an impurity concentration of 1 x 10 19 /cm 3 or greater, e.g., 1 x 10 20 /cm 3 , and the remaining areas are low concentration source-drain areas 232b, 233b with an impurity concentration of 1 x 10 19 /cm 3 or less, e.g., 5 x 10 18 /cm 3 . Therefore, that part of TFT-C positioned near the edge of gate electrode 235 is an LDD structure, i.e., low concentration source-drain areas 232b, 233b. As a result, the OFF current of TFT-C is small as shown by solid line 5E13 in Fig. 6. The TFT-C ON current is also high because high concentration contact areas 232a, 233a are formed in source-drain areas 232, 233. Specifically, in addition to the overall electrical resistance of the source-drain areas 232, 233 dropping due to high concentration contact areas 232a, 233a, the TFT-C ON current is high, equivalent to the characteristic shown by solid line 5E14 in Fig. 6 because the contact resistance of source-drain area 233 (drain area) and pixel electrode 272 formed from ITO is low. Fig. 10 is a graph showing the relationship between the dosage of impurity ions to the area connected by pixel electrode 272 formed from ITO and the contact resistance there. As shown in Fig. 10, if the dosage to source-drain area 233 is increased, the contact resistance tends to drop, and the contact resistance becomes severely low in particular when the dosage exceeds 1 x 10 14 /cm 2 . Note that even in the connection of source electrode 271, which is an aluminum electrode, and source-drain area 232 (source area), the contact resistance tends to drop the higher the impurity concentration in the area to which source electrode 271 connects. However, because the contact resistance of aluminum and polycrystalline silicon is basically low, the contribution to improving the ON current characteristic is less than when the contact resistance of the pixel electrode 272 and source-drain area 233 is reduced. Furthermore, when the length in the lateral direction of low concentration source-drain areas 232b, 233b in source-drain areas 232, 233 (the distance in the lateral direction from the edge of high concentration contact areas 232a, 233a to the edge of gate electrode 235) was varied in the range from 1 µm to 4 µm , and the ON current characteristics and OFF current characteristics of the TFT-C were studied, it was confirmed that the OFF current does not change and the ON current changes only a slight 10+% in this range. Therefore, in the present embodiment, by setting the length dimension of low concentration source-drain areas 232b, 233b to approximately 2 µm, variation in the ON current characteristics can be held to 10% or less even when there is a ± 1 µm variation in this dimension. The manufacturing method of an active matrix circuit board of such construction is described with reference to Fig. 11. Fig. 11 shows a process flow of the manufacturing method of the active matrix circuit board of this embodiment. First, as shown in Fig. 11 (a), after forming a polycrystalline silicon film on the surface side of insulated substrate 101, this is patterned to form silicon films 110, 120, 230. Silicon film 110 is a first silicon film for forming TFT-A, and silicon film 120 is a second silicon film for forming TFT-B. Silicon film 230 is a third silicon film for forming TFT-C (first process). Next, gate insulation films 114, 124, 234 are formed on the surface side of each silicon film 110, 120, 230 (second process). Next, after forming a polycrystalline silicon film on the surfaces of gate insulation films 114, 124, 134 (the entire surface of insulated substrate 201), a high concentration impurity is introduced into it. The polycrystalline silicon film is then patterned using photoetching technologies to form gate electrodes 115, 125, 235. The gate lines are simultaneously formed with the same materials when forming gate electrodes 115, 125, 235 (third process). Next, as shown by arrow P + , phosphorus ions are implanted at a 5 x 10 13 /cm 2 dose to silicon films 110, 120, 230 using gate electrodes 115, 125, 235 as a mask. As a result, low concentration areas 110a, 120a, 230a with a 5 x 10 18 /cm 3 impurity concentration are formed self-aligned to gate electrodes 115, 125, 235 in silicon films 110, 120, 230 (low concentration area formation process). Next, as shown in Fig. 1 (b), the side with silicon films 120, 230 is masked with resist 240. Openings 241, 242 are formed here in that part of low concentration area 230a of silicon film 230 corresponding to where the high concentration contact areas 232a, 233a are to be formed. In this state, high concentration phosphorus ions are implanted at a 1 x 10 15 /cm 2 dose to silicon films 110, 230 as shown by arrow P + (fourth process). As a result, low concentration area 110a becomes source-drain areas 112, 133 (n + high concentration area) with a 1 x 10 20 /cm 3 impurity concentration formed self-aligned to gate electrode 115. With respect to this, high concentration contact areas 232a, 233a with an impurity concentration of 1 x 10 20 /cm 3 are formed in low concentration area 230a of silicon film 230, and that part to which high concentration ions were not implanted becomes low concentration source-drain areas 232b, 233b with an impurity concentration of 5 x 10 18 /cm 3 . In addition, that part of silicon film 230 positioned directly below gate electrode 235 becomes channel formation area 231. Next, as shown in Fig. 11 (c), after masking the sides with silicon films 110, 230 with resist 250, high concentration boron ions are implanted at a 1 x 10 15 /cm 2 dose to silicon film 120 as shown by arrow B + (fifth process). As a result, low concentration area 120b becomes source-drain areas 122, 123 (p + high concentration areas) with a 1 x 10 20 /cm 3 impurity concentration formed self-aligned to gate electrode 125. Because the dosage conditions can be independently set for the n-channel type TFT-A of the drive circuit area, the p-channel type TFT-B of the drive circuit area, and the n-channel type TFT-C of the pixel area by means of the manufacturing method of this embodiment as thus described, a TFT with optimum electrical characteristics can be manufactured. Furthermore, because high concentration contact areas 232a, 233a are formed while forming the LDD structure by twice implanting ions to source-drain areas 232, 233 in TFT-C, the electrical resistance and the contact resistance of the overall source-drain areas 232, 233 can be reduced with the OFF current held low. It is to be noted that in the first through third embodiments the low concentration area formation process can be applied after either the third, fourth, or fifth process. In addition, the order of the fourth and fifth processes can be reversed. Fourth embodiment The manufacturing method of a conductive silicon film is described as the fourth embodiment. Fig. 12 is a structural diagram of the ion implantation device used to manufacture the n-type conductive silicon film of this embodiment. In Fig. 12, an extraction electrode 53 for extracting impurity ions 52 from plasma source 51, and acceleration electrode 54 for accelerating the impurity ions 52 to a predetermined energy level are provided in ion implantation machine 50, and a voltage is applied to extraction electrode 53 and acceleration electrode 54. As a result, impurity ions 52 extracted from plasma source 51 can be implanted to the polycrystalline silicon film formed on the surface of glass substrate 55. A mass separator for applying mass separation to the ions generated from the dopant gas is not provided in ion implantation machine 50, and all ions generated from the dopant gas are implanted to the polycrystalline silicon film without mass separation. In the manufacturing method (impurity activation method) of the conductive silicon film according to this embodiment using a ion implantation machine 50 of this type, a polycrystalline silicon film with a thickness of, for example, 500 Å, is first formed on the surface of a glass substrate, and on the surface of the polycrystalline silicon film is formed a 1200 Å thick silicon dioxide film (SiO 2 film). When forming a TFT from the polycrystalline silicon film, it is preferable to form the polycrystalline silicon film with a crystallization rate of 75% or higher, and it is even more preferable to form it with a 90% or higher rate. Next, using ion implantation machine 50, all ions generated from a mixed gas (dopant gas) containing 5% PH 3 with the remainder being hydrogen are implanted to the polycrystalline silicon film through the silicon dioxide film at an 80 keV energy level without mass separation (first ion doping process). The dosage of the ions implanted at this time is 1 x 10 14 /cm 2 converted to P + ions. As a result, the P + ion concentration peak in the polycrystalline silicon film will be approximately 1 x 10 19 /cm 3 . Continuing, using ion implantation machine 50, ions generated from a 100% pure hydrogen gas are implanted to the polycrystalline silicon film through the silicon dioxide film at a 20 keV energy level without mass separation (second ion doping process). In this embodiment, most of the ions generated from the pure hydrogen gas are H 2 + , and by setting the implantation energy level to 20 keV in this case, the concentration peak in the H 2 + depth direction can be controlled to be positioned at the boundary of the polycrystalline silicon film and the silicon dioxide film. Heat treatment with a temperature of approximately 300°C is then applied for approximately one hour to the polycrystalline silicon film implanted with an impurity (P + ions) (heating process). The heat treatment temperature here is in the range from approximately 300°C to approximately 600°C, and preferably in the range from approximately 300°C to approximately 550°C. Furthermore, in the TFT manufacturing process, when a low-cost glass substrate is used as the insulated substrate, the heat treatment temperature is preferably set within the range from approximately 300°C to approximately 450°C. The relationship between the hydrogen ion dose to the polycrystalline silicon film thus formed and the sheet resistance is shown in Fig. 13. In Fig. 13 the hydrogen ion does is converted to a H + ion quantity. As shown in Fig. 13, the resistance of the polycrystalline silicon implanted with a small quantity of impurity is low when the dose of implanted H + ions is in the range from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 , or specifically when the concentration peak of H + ions in the polycrystalline silicon film is in the range from 6 x 10 18 /cm 3 to 1 x 10 20 /cm 3 . The reasons for this are believed to be the result of competition between the effect of dangling bonds in the polycrystalline silicon film terminating due to hydrogen ion implantation, and the effect of defects being created by hydrogen ion implantation. Furthermore, the relationship between the phosphorus ion dose in the first doping process and sheet resistance is shown in Fig. 14 when the conditions of the second ion doping process are set so that ions generated from pure hydrogen are implanted without mass separation to the polycrystalline silicon film at a dose from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 to achieve a concentration peak of H + ions in the polycrystalline silicon film in the range from 6 x 10 18 /cm 3 [sic] to 1 x 10 20 /cm 3 . In Fig. 14, the phosphorus ions are shown converted to a P + ion quantity. As shown in Fig. 14, the sheet resistance drops if the P + ion dose is changed to the range from 5 x 10 12 /cm 2 to 1.5 x 10 15 /cm 2 , and the P + ion concentration peak is increased from 5 x 10 17 /cm 3 to 1.6 x 10 19 /cm 3 . Therefore, a low concentration polycrystalline silicon film can be made conductive according to this embodiment by heat treatment at a relatively low temperature of approximately 300°C by implanting ions generated from a pure hydrogen gas to the silicon film without mass separation after implanting all ions generated from a mixed gas, which contains an impurity gas for generating an impurity with the remainder being hydrogen, to the silicon film without mass separation. As a result, an LDD structure TFT can be formed on a low-cost glass substrate because a TFT low concentration source-drain area can be formed even in a low temperature process. In addition, because an electrode material with a low electrical resistance can be used as a result of the heat resistance limitations of the gate electrode etc., being relaxed, the gate signal delay can be reduced and the display quality in a liquid crystal display panel can be improved. In addition, productivity is high because ions can be implanted to a wide area of the substrate because mass separation is not used. It is to be noted that the energy level during ion implantation is a property that must be set to the optimum conditions based on the thickness and type of the silicon dioxide film formed on the surface of the polycrystalline silicon film, and the type of ions implanted, and there is therefore no limit on the conditions. For example, when the generated ions are primarily H + , if the implantation energy is set to 10 keV, the concentration peak in the H + depth direction can be controlled to a position at the boundary of the polycrystalline silicon film and the silicon dioxide film. In addition, when the thickness of the silicon dioxide film is approximately 800Å, using ion implantation machine 50, all ions generated from a mixed gas containing 5% PH 3 with the remainder being hydrogen are implanted to the polycrystalline silicon film through the silicon dioxide film at a 50 keV energy level without mass separation. To achieve a P + ion concentration peak in the polycrystalline silicon film of approximately 1 x 10 19 /cm 3 , the ion dose is set to 6.5 x 10 13 /cm 2 converted to P + ions (first doping process). Continuing, using ion implantation machine 50, ions generated from pure hydrogen are implanted to the polycrystalline silicon film through the silicon dioxide film at a 12 keV energy level without mass separation (first doping process). Thereafter, heat treatment at approximately 300°C is applied to the polycrystalline silicon film implanted with an impurity (P + ions) for approximately one hour (heating process). Fifth embodiment Next, the manufacturing method of a p-type conductive silicon film is described as the fifth embodiment. It is to be noted that the ion implantation machine 50 used in the fourth embodiment is also used in this embodiment, and with this device all ions generated from the dopant gas are implanted to the polycrystalline silicon film without mass separation. In the conductive silicon film manufacturing method according to this embodiment using this type of ion injection device 50, a polycrystalline silicon film with a thickness of, for example, 500 Å, is first formed on the surface of a glass substrate, and on the surface of the polycrystalline silicon film is formed a 1200 Å thick silicon dioxide film (SiO 2 film). When forming a TFT from the polycrystalline silicon film, it is preferable to form the polycrystalline silicon film with a crystallization rate of 75% or higher, and it is even more preferable to form it with a 90% or higher rate. Next, using ion implantation machine 50, all ions generated from a mixed gas (dopant gas) containing 5% B 2 H 6 with the remainder being hydrogen are implanted to the polycrystalline silicon film through the silicon dioxide film at an 80 keV energy level without mass separation (first ion doping process). The dosage of the ions implanted at this time is 1 x 10 14 /cm 2 converted to B + ions. As a result, the B + ion concentration peak in the polycrystalline silicon film will be approximately 1 x 10 19 /cm 3 . Continuing, using ion injection device 50, ions generated from a 100% pure hydrogen gas are implanted to the polycrystalline silicon film through the silicon dioxide film at a 20 keV energy level without mass separation (second ion doping process). In this embodiment, most of the ions generated from the pure hydrogen gas are H 2 + , and by setting the implantation energy level to 20 keV in this case, the concentration peak in the H 2 + depth direction can be controlled to be positioned at the boundary of the polycrystalline silicon film and the silicon dioxide film. Heat treatment with a temperature of approximately 300°C is then applied for approximately one hour to the polycrystalline silicon film implanted with an impurity (B + ions) (heating process). The heat treatment temperature here is in the range from approximately 300°C to approximately 600°C, and preferably in the range from approximately 300°C to approximately 550°C. Furthermore, in the TFT manufacturing process, when a low-cost glass substrate is used as the insulated substrate, the heat treatment temperature is preferably set within the range from approximately 300°C to approximately 450°C. The relationship between the hydrogen ion dose to the polycrystalline silicon film thus formed and the sheet resistance is shown in Fig. 15. In Fig. 15 the hydrogen ion does is converted to a H + ion quantity. As shown in Fig. 15, the resistance of the polycrystalline silicon implanted with a small quantity of impurity is low when the dose of implanted H + ions is in the range from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 , or specifically when the concentration peak of H + ions in the polycrystalline silicon film is in the range from 6 x 10 18 /cm 3 to 1 x 10 20 /cm 3 . The reasons for this are believed to be the result of competition between the effect of irregular bonds in the polycrystalline silicon film terminating due to hydrogen ion implantation, and the effect of defects being created by hydrogen ion implantation. Furthermore, the relationship between the boron ion dose in the first doping process and sheet resistance is shown in Fig. 16 when the conditions of the second ion doping process are set so that ions generated from pure hydrogen are implanted without mass separation to the polycrystalline silicon film at a dose from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 to achieve a concentration peak of H + ions in the polycrystalline silicon film in the range from 6 x 10 18 /cm 3 [sic] to 1 x 10 20 /cm 3 . In Fig. 16, the boron ion is shown converted to a B + ion quantity. As shown in Fig. 16, the sheet resistance drops if the B + ion dose is changed to the range from 5 x 10 12 /cm 2 to 1.5 x 10 15 /cm 2 , and the B + ion concentration peak is increased from 5 x 10 17 /cm 3 to 1.6 x 10 19 /cm 3 . Therefore, a low concentration polycrystalline silicon film can be made conductive according to this embodiment by heat treatment at a relatively low temperature of approximately 300°C by implanting ions generated from a pure hydrogen gas to the silicon film without mass separation after implanting all ions generated from a mixed gas, which contains an impurity gas for generating an impurity with the remainder being hydrogen, to the silicon film without mass separation. It is to be noted that in this embodiment, too, the energy level during ion implantation is a property that must be set to the optimum conditions based on the thickness and type of the silicon dioxide film formed on the surface of the polycrystalline silicon film, and the type of ions implanted, and there is therefore no limit on the conditions. For example, when the generated ions are primarily H + , if the implantation energy is set to 10 keV, the concentration peak in the H + depth direction can be positioned at the boundary of the polycrystalline silicon film and the silicon dioxide film. Furthermore, because the ions generated from the mixed gas containing 5% B 2 H 6 with the remainder hydrogen are primarily B 2 H x + ions, implantation can use an energy level of approximately 40 keV when primarily B + ions are generated even though ions were implanted at 80 keV in this embodiment. Sixth embodiment Three different types of thin-film transistors are formed in an active matrix circuit board with a built-in drive circuit because the characteristics required of the thin-film transistors are different. In the present embodiment, therefore, a method for manufacturing different types of thin-film transistors is described applying the manufacturing method for conductive silicon films according to the fourth and fifth embodiments. Fig. 17 is a cross sectional diagram typically showing, of the thin-film transistors (hereafter "TFT") formed in the active matrix circuit board of the present embodiment, the structure of the TFT formed in the pixel area and the n-channel type TFT and p-channel type TFT comprising a CMOS circuit formed in the drive circuit area. In Fig. 17, in active matrix circuit board 700 of the present embodiment, n-channel type TFT-A of the drive circuit area, p-channel type TFT-B of the drive circuit area, and n-channel type TFT-C of the pixel area are formed on a glass substrate 701 (insulated substrate) in order from the left side as looking at the figure. Source-drain areas 712, 713 of TFT-A are formed as high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, and are formed self-aligned to gate electrode 715. Source-drain areas 722, 723 of TFT-B are formed as high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, and are formed self-aligned to gate electrode 725. Source-drain areas 732, 733 of TFT-C are formed as low concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or less, and are formed self-aligned to gate electrode 735. Therefore, a high ON current can be obtained in TFT-A and TFT-B of the drive circuit area. In addition, a sufficiently low OFF current can be obtained in TFT-C of the pixel area because source-drain areas 732, 733 are formed as low concentration areas. The manufacturing method of active matrix circuit board 700 of such construction is described with reference to Fig. 18. Fig. 18 shows a process flow of the manufacturing method of the active matrix circuit board of the present embodiment. First, as shown in Fig. 18 (a), after forming a polycrystalline silicon film with a film thickness of approximately 500 Å on the surface side of glass substrate 701, this is patterned to form silicon films 710, 720, 730. Silicon film 710 is a first silicon film for forming TFT-A, and silicon film 720 is a second silicon film for forming TFT-B. Silicon film 730 is a third silicon film for forming TFT-C (first process). Next, gate insulation films 714, 724, 734 with a film thickness of approximately 1200 Å are formed on the surface side of each silicon film 710, 720, 730 (second process). Next, a metal layer such as tantalum, aluminum, or chrome is formed by sputtering, etc., on the surface of gate insulation films 714, 724, 734, and is patterned to form gate electrodes 715, 725, 735 with a film thickness of approximately 6000 Å (third process). Next, as shown by arrow ion-1, low concentration phosphorus ions are implanted to silicon films 710, 720, 730 using gate electrodes 715, 725, 735 as a mask. In this process, in ion implantation machine 50 shown in Fig. 12, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose in the range from 3 x 10 13 /cm 2 to 1 x 10 14 /cm 2 (first ion doping process). As a result, polycrystalline silicon films 710, 720, 730 become low concentration areas 710a, 720a, 730a with a phosphorus ion concentration peak in the range from 3 x 10 18 /cm 3 to 1 x 10 19 /cm 3 . Continuing, as shown in Fig. 18 (b), in ion implantation machine 50 shown in Fig. 12, all ions (shown by arrow Ion-2) generated from a doping gas of pure hydrogen are implanted to low concentration areas 710a, 720a, 730a at an approximately 20 keV energy level to achieve a H + ion dose in the range from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 (second ion doping process). As a result, the hydrogen ion concentration peak in low concentration areas 710a, 720a, 730a is in the range from 6 x 10 18 /cm 3 to 1 x 10 20 /cm 3 (above, the low concentration area formation process). Next, as shown in Fig. 18 (c), after masking the side with silicon films 720, 730 with resist 740 as a mask, high concentration phosphorus ions are implanted to low concentration area 710a as shown by arrow Ion-3 (fourth process). Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose of 1 x 10 15 /cm 2 or greater (fifth process). As a result, low concentration area 710a becomes source-drain areas 712, 713 (n + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 715. In addition, that part of silicon film 710 positioned directly below gate electrode 715 becomes channel formation area 711. Next, as shown in Fig. 18 (d), after masking the sides with silicon films 710, 730 with resist 750, high concentration boron ions are implanted to low concentration area 720a as shown by arrow Ion-4 (fifth process). Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% B 2 H 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a B + ion dose of 1 x 10 15 /cm 2 or greater. As a result, low concentration area 720a becomes source-drain areas 722, 723 (p + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 725. In addition, that part of silicon film 720 positioned directly below gate electrode 725 becomes channel formation area 721. Then, the impurity is activated in polycrystalline silicon films 710, 720, 730 implanted with the impurity by heat treatment for approximately one hour at approximately 300°C in a nitrogen atmosphere (heating process). The processes following thereafter are identical to the normal TFT manufacturing method, and description is therefore omitted. As described hereinabove, by means of the manufacturing method of this embodiment, TFT with optimum electrical characteristics can be manufactured because the dosage conditions of TFT-A, TFT-B, and TFT-C can be set independently. In addition, because the heat treatment temperature is low, the low heat resistance materials can be used for electrodes, and a low cost glass substrate 701 can be used. Seventh embodiment The structures of an active matrix circuit board according to the present embodiment and the eighth embodiment described after this embodiment are basically the same as the structure of the active matrix circuit board according to the sixth embodiment, and only the structure of the TFT in the pixel area differs. Therefore, parts with functionality common to the first embodiment are identically labelled, and further identification in the figures and detailed description are omitted. Fig. 19 is a cross sectional diagram typically showing the structure of the TFT formed in an active matrix circuit board according to the present embodiment. In Fig. 19, TFT-A, TFT-B, and TFT-C are formed in active matrix circuit board 800 of this embodiment on glass substrate 701. As described in the description of the sixth embodiment, source-drain areas 712, 713, 722, and 723 of TFT-A and TFT-B are high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, and are formed self-aligned to gate electrodes 715, 725. In source-drain areas 832, 833 of TFT-C, that area positioned near the edge of gate electrode 835 is low concentration source-drain area 832b, 833b with an impurity concentration of 1 x 10 19 /cm 3 or less, and the other areas are high concentration contact areas 832a, 833a with an impurity concentration of 1 x 10 19 /cm 3 or greater. Therefore, the OFF current of TFT-C is low. In addition, the overall electrical resistance of source-drain areas 832, 833 is low because high concentration contact areas 832a, 833a are formed in source-drain areas 832, 833. Moreover, because the source electrode and drain electrode can be connected to high concentration contact area 832a, 833a, the contact resistance there can be reduced. The manufacturing method of an active matrix circuit board of such configuration is described with reference to Fig. 20. First, as shown in Fig. 20 (a), after forming a polycrystalline silicon film with a film thickness of approximately 500 Å on the surface side of glass substrate 701, this is patterned to form silicon films 710, 720, 830. Silicon film 830 is a third silicon film for forming TFT-C (first process). Next, gate insulation films 714, 724, 834 with a film thickness of approximately 1200 Å are formed on the surface side of each silicon film 710, 720, 830 (second process). Next, gate electrodes 715, 725, 835 with a film thickness of approximately 6000 Å are formed from tantalum, aluminum, chrome, etc. on the surface of gate insulation films 714, 724, 834 (third process). Next, as shown by arrow Ion-1, low concentration phosphorus ions are implanted to silicon films 710, 720, 830 using gate electrodes 715, 725, 835 as a mask. In this process, in ion implantation machine 50 shown in Fig. 12, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose in the range from 3 x 10 13 /cm 2 to 1 x 10 14 /cm 2 (first ion doping process). As a result, polycrystalline silicon films 710, 720, 830 become low concentration areas 710a, 720a, 830a with a phosphorus ion concentration peak in the range from 3 x 10 18 /cm 3 to 1 x 10 19 /cm 3 . Continuing, as shown in Fig. 20 (b), in ion implantation machine 50 shown in Fig. 12, all ions (shown by arrow Ion-2) generated from a doping gas of pure hydrogen are implanted to low concentration areas 710a, 720a, 830a at an approximately 20 keV energy level to achieve a H + ion dose in the range from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 (second ion doping process). As a result, the hydrogen ion concentration peak in low concentration areas 710a, 720a, 830a is in the range from 6 x 10 18 /cm 3 to 1 x 10 20 /cm 3 (above, the low concentration area formation process). Next, as shown in Fig. 20 (c), after masking the side with silicon films 720, 830 with resist 840, high concentration phosphorus ions are implanted to low concentration area 710a as shown by arrow Ion-3 (fourth process). Here, resist 840 covers the area around gate electrode 835 on the side with silicon film 830, and ions are implanted in this state. Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose of 1 x 10 15 /cm 2 or greater. As a result, low concentration area 710a becomes source-drain areas 712, 713 (n + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 715. In addition, that part of silicon film 710 positioned directly below gate electrode 715 becomes channel formation area 711. Also, high concentration contact areas 832a, 833a with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater are formed in low concentration area 830a, and that area to which high concentration ions are not implanted becomes low concentration source-drain area 832b, 833b with a phosphorus ion concentration peak in the range from 3 x 10 18 /cm 3 to 1 x 10 19 /cm 3 . Next, as shown in Fig. 20 (d), after masking the sides with silicon films 710, 830 with resist 850, high concentration boron ions are implanted to low concentration area 720a as shown by arrow Ion-4 (fifth process). Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% B 2 H 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a B + ion dose of 1 x 10 15 /cm 2 or greater. As a result, low concentration area 720a becomes source-drain areas 722, 723 (p + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 725. In addition, that part of silicon film 720 positioned directly below gate electrode 725 becomes channel formation area 721. Then, the impurity is activated in polycrystalline silicon films 710, 720, 830 implanted with the impurity by heat treatment for approximately one hour at approximately 300°C in a nitrogen atmosphere. The processes following thereafter are identical to the normal TFT manufacturing method, and description is therefore omitted. As described hereinabove, by means of the manufacturing method of this embodiment, TFT with optimum electrical characteristics can be manufactured because the dosage conditions of TFT-A, TFT-B, and TFT-C can be set independently. In addition, because the heat treatment temperature is low, the low heat resistance material can be used for electrodes, and a low cost glass substrate 701 can be used. Eighth embodiment Fig. 21 is a cross sectional diagram typically showing the structure of the TFT formed in an active matrix circuit board according to the present embodiment. In Fig. 21, TFT-A, TFT-B, and TFT-C are formed on glass substrate 701 in active matrix circuit board 900 of this embodiment. As described in the description of the sixth embodiment, source-drain areas 712, 713, 722, and 723 of TFT-A and TFT-B are high concentration areas with an impurity concentration of 1 x 10 19 /cm 3 or greater, and are formed self-aligned to gate electrodes 715, 725. In source-drain areas 932, 933 of TFT-C, that area positioned near the edge of gate electrode 935 is low concentration source-drain area 932b, 933b with an impurity concentration of 1 x 10 19 /cm 3 or less, and the other areas are high concentration contact areas 932a, 933a with an impurity concentration of 1 x 10 19 /cm 3 or greater. Therefore, the OFF current of TFT-C is low. In addition, the overall electrical resistance of source-drain areas 932, 933 is low because high concentration contact area 932a, 933a are formed in source-drain areas 932, 933. Moreover, because the source electrode and drain electrode can be connected to high concentration contact area 932a, 933a, the contact resistance there can be reduced. The manufacturing method of an active matrix circuit board of such configuration is described with reference to Fig. 20. Fig. 22 shows a process flow of the manufacturing method of the active matrix circuit board of the present embodiment. First, as shown in Fig. 22 (a), after forming a polycrystalline silicon film with a film thickness of approximately 500 Å on the surface side of glass substrate 701, this is patterned to form silicon films 710, 720, 930. Silicon film 930 is a silicon film for forming TFT-C (first process). Next, gate insulation films 714, 724, 934 with a film thickness of approximately 1200 Å are formed on the surface side of each silicon film 710, 720, 930 (second process). Next, gate electrodes 715, 725, 935 with a film thickness of approximately 6000 Å are formed from tantalum, aluminum, chrome, etc. on the surface of gate insulation films 714, 724, 934 (third process). Next, as shown by arrow Ion-1, low concentration phosphorus ions are implanted to silicon films 710, 720, 930 using gate electrodes 715, 725, 935 as a mask. In this process, in ion implantation machine 50 shown in Fig. 12, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose in the range from 3 x 10 13 /cm 2 to 1 x 10 14 /cm 2 (first ion doping process). As a result, polycrystalline silicon films 710, 720, 930 become low concentration areas 710a, 720a, 930a with a phosphorus ion concentration peak in the range from 3 x 10 18 /cm 3 to 1 x 10 19 /cm 3 . Continuing, as shown in Fig. 22 (b), in ion implantation machine 50 shown in Fig. 12, all ions (shown by arrow Ion-2) generated from a doping gas of pure hydrogen are implanted to low concentration areas 710a, 720a, 930a at an approximately 20 keV energy level to achieve a H + ion dose in the range from 1 x 10 14 /cm 2 to 1 x 10 15 /cm 2 (second ion doping process). As a result, the hydrogen ion concentration peak in low concentration areas 710a, 720a, 930a is in the range from 6 x 10 18 /cm 3 to 1 x 10 20 /cm 3 (above, the low concentration area formation process). Next, as shown in Fig. 22 (c), after masking the side with silicon films 720, 930 with resist 940, high concentration phosphorus ions are implanted to low concentration area 710a as shown by arrow Ion-3 (fourth process). Here, openings 941, 942 are formed in resist 940 at the position corresponding to the intended formation area of high concentration contact areas 932a, 933a in the surface side of silicon film 930. Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% PH 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a P + ion dose of 1 x 10 15 /cm 2 or greater. As a result, low concentration area 710a becomes source-drain areas 712, 713 (n + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 715. In addition, that part of silicon film 710 positioned directly below gate electrode 715 becomes channel formation area 711. Also, high concentration contact areas 932a, 933a with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater are formed in low concentration area 930a of silicon film 930, and that area to which high concentration ions are not implanted becomes low concentration source-drain area 932b, 933b with a phosphorus ion concentration peak in the range from 3 x 10 18 /cm 3 to 1 x 10 19 /cm 3 . Next, as shown in Fig. 22 (d), after masking the sides with silicon films 710, 930 with resist 950, high concentration boron ions are implanted to low concentration area 720a as shown by arrow Ion-4 (fifth process). Ion implantation machine 50 shown in Fig. 12 is used for this ion implantation, too. In other words, all ions generated from a doping gas containing 5% B 2 H 3 with the remainder being H 2 gas are implanted at an approximately 80 keV energy level to achieve a B + ion dose of 1 x 10 15 /cm 2 or greater. As a result, low concentration area 720a becomes source-drain areas 722, 723 (p + high concentration areas) formed with a phosphorus ion concentration peak of 1 x 10 20 /cm 3 or greater self-aligned to gate electrode 725. In addition, that part of silicon film 720 positioned directly below gate electrode 725 becomes channel formation area 721. Then, the impurity is activated in polycrystalline silicon films 710, 720, 930 implanted with the impurity by heat treatment for approximately one hour at approximately 300°C in a nitrogen atmosphere. The processes following thereafter are identical to the normal TFT manufacturing method, and description is therefore omitted. As described hereinabove, by means of the manufacturing method of this embodiment, TFT with optimum electrical characteristics can be manufactured because the dosage conditions of TFT-A, TFT-B, and TFT-C can be set independently. In addition, because the heat treatment temperature is low, the method is not limited by the heat resistance of the wiring material, and a low cost glass substrate 701 can be used. It is to be noted that in embodiments six through eight the low concentration area formation process may be executed after either of the third, fourth, or fifth processes. In addition, the sequence of the fourth and fifth processes may be reversed. Moreover, a silicon dioxide film with a film thickness of approximately 2000 Å may be formed on top of glass substrate 701 before performing the first process to prevent diffusion of heavy metals from the side of glass substrate 701 to the component areas.

Claims: An active matrix circuit board having on the surface side of an insulated substrate (101) a drive circuit area (10b, 10c) equipped with a CMOS circuit comprising a first thin-film transistor (TFT-A) of a first conductivity type and a second thin-film transistor (TFT-B) of a second conductivity type, and a pixel area (10a) comprising a third thin-film transistor (TFT-C) of said first conductivity type, characterized that the impurity concentration of the source-drain area (132, 133) of the third thin-film transistor is low relative to the impurity concentration of the source-drain area of the first thin-film transistor, the impurity concentration of the source-drain area of the third thin-film transistor being 1 x 10 19 /cm 3 or less, and the impurity concentration of the source-drain area of the first thin-film transistor being 1 x 10 19 /cm 3 or greater. A circuit board according to Claim 1 wherein the source-drain area (232, 233) of the third thin-film transistor (TFT-C) has a high concentration contact area (232a, 233a) with an impurity concentration of 1 x 10 19 /cm 3 or greater, and the source-drain electrodes (271, 272) are conductively connected to the source-drain area of the third thin-film transistor through this high concentration contact area. A circuit board according to Claim 2 wherein the distance in the lateral direction between the high concentration contact area (232a, 233a) and the edge of the gate electrode (235) in the third thin-film transistor (TFT-C) is approximately 4 µm or less. A circuit board according to any of Claims 1 through 3 wherein, in the third thin-film transistor (TFT-C), the source-drain area (132, 133; 652, 653) has a double layer structure composed of first and second silicon films of which the first silicon film (132a, 133a; 652b, 653b) is thinner than and formed on the second silicon film (132b, 133b; 652a, 653a), and the channel formation area has a single layer structure composed of only the first one of said first and second silicon films. A circuit board according to Claim 1, wherein the source-drain area (232, 233) of the third thin-film transistor (TFT-C) has an LDD structure including a high impurity concentration area and wherein the source-drain electrodes (271, 272) are conductively connected to the source-drain area of the third thin-film transistor (TFT-C) through the high impurity concentration area of said LDD structure. A manufacturing method for the active matrix circuit board of claim 1, comprising a first process for forming, on the surface side of the insulated substrate (101), first and second silicon films (110, 120) for forming the first thin-film transistor (TFT-A) of a first conductivity type and the second thin-film transistor (TFT-B) of a second conductivity type in the drive circuit area, and a third silicon film (130) for forming the third thin-film transistor (TFT-C) of a first conductivity type in the pixel area, a second process for forming gate insulation films (114, 124, 134) on the surfaces of the first, second, and third silicon films, a third process for forming gate electrodes (115, 125, 135) on the surface side of the gate insulation films, a fourth process for ion implanting an impurity of the second conductivity type to the second silicon film at a dose of 1 x 10 14 /cm 2 or greater with the first and third silicon films covered by a first mask, and a fifth process for ion implanting an impurity of the first conductivity type to the first silicon film at a dose of 1 x 10 14 /cm 2 or greater with the second and third silicon films covered by a second mask, wherein said fourth and fifth processes are performed after said third process, characterized by a low concentration area formation process of ion implanting an impurity of the first conductivity type at a dose of 1 x 10 14 /cm 2 or less to the first, second, and third silicon films after either of the third through fifth processes. A manufacturing method for an active matrix circuit board according to Claim 6 wherein in the fifth process that part of the second mask corresponding to a connection area of source-drain electrodes (271, 272) to the source-drain areas (232, 233) of the third thin-film transistor is opened, and ions are also implanted to the third silicon film. A manufacturing method for an active matrix circuit board according to Claim 6 or 7 wherein said low concentration area formation process comprises (a) a first ion doping process for implanting to the silicon film without mass separation all ions generated from a mixed gas containing an impurity gas for generating impurity ions with the remainder being hydrogen gas, and (b) a second ion doping process for implanting ions generated from a pure hydrogen gas to the silicon film without mass separation, said fourth and fifth processes each comprises (c) an ion doping process for implanting to the silicon film without mass separation all ions generated from a mixed gas containing an impurity gas for generating impurity ions with the remainder being hydrogen gas, and heat treatment at a temperature of approximately 300°C or greater is performed after each of steps (b) and (c) for activating the ions implanted to the silicon film.

Inventors: MATSUO MINORU, TAKENAKA SATOSHI, YUDASAKA ICHIO, MATSUO, MINORU, TAKENAKA, SATOSHI, YUDASAKA, ICHIO
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1994
Main classification: H01L29
IPC codes: H01L27, H01L21, G02F1, H01L29