High gain differential amplifier capable of reducing offset voltage

Abstract: A high gain differential amplifier including a differential transistor pair (M₁, M₂) having first and second transistors (M₁, M₂) whose gates are connected to first and second input terminals (t₁, t₂); a current mirror circuit wherein the drain of the transistor (M₁) is connected to an output terminal; a transistor (M₅) whose gate and drain are connected to the drain of transistor (M₁) and output terminal of the current mirror circuit, and to the output terminal (t₃) and the drain of transistor (M₂), respectively; a transistor (M₆) whose drain and gate are connected to an input terminal of the current mirror circuit, and to a bias power supply terminal, respectively; and constant-current source (I₁, I₂) which are connected to the common sources of differential transistor pair (M₁, M₂) and a source of the transistor (M₆), respectively. The addition of the sixth transistor (M₆) permits a voltage between the drain and source of the third and fourth transistors (M₃, M₄) to be nearly equal. As a result, a drain current ratio between the third and fourth transistors (M₃, M₄) can be precisely determined and thus an input offset voltage can be reduced to nearly zero.

Description: BACKGROUND OF THE INVENTION The present invention relates to a differential amplifier having high gain at a low frequency signal input. Description of the Related Arts Examples of prior art differential amplifiers with offset- compensation or offset voltage control are known from US- A- 5 045 806 and US- A- 4 658 157, respectively. As a prior art on the present invention, one differential amplifier has been proposed, as disclosed in the published Japanese Patent Application JP-A-6-045 844. Fig. 1 shows a conventional typical differential amplifier as disclosed in JP-A-6-045844. In this case, a pair of FETS (field-effect transistors) M101 and M102 whose sources are coupled with each other in common and whose gates are connected to respective input terminals t1 and t2 constitute a differential transistor pair. One end of a first constant-current source I101 is coupled with the common source connection point of the FETs M101 and M102 and the other end of the first constant-current source I101 is connected to a low power supply terminal t4. The drain and gate of an FET M103 are coupled with each other and the source of the FET M103 is connected to a high power supply terminal t5. The gate of another FET M104 is connected to the gate of the FET M103, and the source to the high power supply terminal t5, and the drain to the drain of the FET M101. The FETs M103 and M104 constitute a current mirror circuit. The gate of an FET M105 is connected to the drains of the FETs M101 and M104, and the source to the high power supply terminal t5, and the drain to an output terminal t3 and to the drain of the FET M102. One end of a second constant-current source I102 is coupled with the drain and gate of the FET M103 and the other end to the low power supply terminal t4. Next, the operation of this differential amplifier will now be described. First, the differential transistor pair composed of the FETs M101 and M102 distributes the current of the first constant-current source I101 depending on signal voltages applied to the input terminals t1 and t2 to flow a drain current. The current mirror circuit including the FETs M103 and M104 outputs a current which is fixed and equal to the current value determined by the second constant-current source I102 and hence the variation of the drain current of the FET M101 is transferred to the gate of the FET M105. The variation of the drain current of the FET M101 is amplified by the FET M105 and the amplified current is output from the output terminal t3. On the other hand, the variation of the drain current of the FET M102 turns to a value to negate the variation of the drain current of the FET M101 and is also picked up from the output terminal t3. Hence, from the output terminal t3, the variation of the current largely amplified can be picked up and Fig. 1 discloses the differential amplifier having large voltage gain. However, in the prior arts, although the conventional differential amplifier has the large voltage gain, the difference of the operating point voltage among the transistors causes a difference in a balance point operating current of the differential transistor pair and as a result, an input offset voltage occurs. That is, in the conventional differential amplifier shown in Fig. 1, the current value of the first constant-current source I101 is set to twice as much as that of the second constant-current source I102 and the same transistor is used for the FETs M103 and M104 so that the operating point current of the two FETs M101 and M102 constituting the differential pair may be equal. However, in the conventional differential amplifier, since the voltages between the drain and source of the two FETs M103 and M104 of the current mirror circuit are largely different, the operating current is somewhat different in the transistors M103 and M104. Hence, the operating current turns out to be unequal in the two transistors M101 and M102 and as a result, an input offset voltage is caused between the input terminals t1 and t2. This offset voltage reaches several mV depending on the situation and thus the application of this circuit to a high accuracy device is restricted. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a low offset differential amplifier having high gain in view of the aforementioned problems of the prior art, which is capable of reducing an offset voltage. This object is achieved by the features of Claim 1. In accordance with one aspect of the present invention, there is provided a differential amplifier, comprising a current mirror circuit; a differential transistor pair including first and second transistors connected to first and second input terminals, respectively, for distributing current depending on signal voltages applied to the first and second input terminals; a first constant-current source for supplying the current to be distributed by the differential transistor pair, one end and another end of which are connected to the differential transistor pair and to a first power supply terminal, respectively; a third field-effect transistor whose drain and gate are coupled and whose source is connected to a second power supply terminal; and a fourth field-effect transistor whose gate, source and drain are connected to the gate and drain of the third field-effect transistor, to the second power supply terminal and to the first transistor, respectively; a fifth field-effect transistor whose gate, source and drain are connected to the first transistor and the drain of the fourth field-effect transistor, to the second power supply terminal and to an output terminal and the second transistor, respectively; a sixth transistor which is connected to the gate and drain of the third field-effect transistor and to a third power supply terminal, for equalizing a voltage between the drain and source of the third and fourth field-effect transistors; and a second constant-current source, one end and another end of which are connected to the sixth transistor and to the first power supply terminal, respectively. In a preferable case, the first and second transistors of the differential transistor pair are field-effect transistors whose gates are connected to the respective first and second input terminals and whose sources are coupled in common with one end of the first power supply terminal, and a drain of the first field-effect transistor is connected to the drain of the fourth field-effect transistor. The drains of the first and fourth field-effect transistors are connected to the gate of the fifth field-effect transistor, and a drain of the second field-effect transistor is coupled with the output terminal and the drain of the fifth field-effect transistor. The sixth transistor is a field-effect transistor whose drain, source and gate are connected to the gate and drain of the third field-effect transistor, to one end of the second constant-current source and to the third power supply terminal, respectively. In another preferable case, the first and second transistors of the differential transistor pair are bipolar transistors whose bases are connected to the respective first and second input terminals and whose emitters are coupled in common with one end of the first power supply terminal, and a collector of the first bipolar transistor is connected to the drain of the fourth field-effect transistor. The collector of the first bipolar transistor and the drain of the fourth field-effect transistor are connected to the gate of the fifth field-effect transistor, and a collector of the second bipolar transistor is coupled with the output terminal and the drain of the fifth field-effect transistor. The sixth transistor is a bipolar transistor whose collector whose collector, emitter and base are connected to the gate and drain of the third field-effect transistor, to one end of the second constant-current source and to the third power supply terminal, respectively. In accordance with another aspect of the present invention, there is provided a differential amplifier, comprising a current mirror circuit; a differential transistor pair including first and second bipolar transistors whose emtters are coupled in common and whose bases are connected to first and second input terminals, respectively; a first constant-current source, one end and another end of which are connected to the common emitters of the first and second bipolar transistors of the differential transistor pair and to a first power supply terminal, respectively; a pair of third and fourth bipolar transistors whose bases are coupled in common with a second power supply terminal and whose emitters are connected to collectors of the respective first and second bipolar transistors; a first field-effect transistor whose drain and gate are coupled and whose source is connected to a third power supply terminal; and a second field-effect transistor whose gate, source and drain are connected to the gate and drain of the first field-effect transistor, to the third power supply terminal and to a collector of the third bipolar transistor, respectively; a third field-effect transistor whose gate, source and drain are connected to the collector of the third bipolar transistor and the drain of the second field-effect transistor, to the third power supply terminal and to an output terminal and a collector of the fourth bipolar transistor, respectively; a fifth bipolar transistor whose collector and base are connected to the gate and drain of the first field-effect transistor and to the second power supply terminal, respectively; a sixth bipolar trainsistor whose collector and base are connected to an emitter of the fifth bipolar transistor and to a fourth power supply terminal, respectively; and a second constant-current source, one end and another end of which are connected to an emitter of the sixth bipolar transistor and to the first power supply terminal, respectively. In accordance with a further aspect of the present invention, there is provided a differential amplifier, comprising a current mirror circuit; a differential transistor pair including first and second bipolar transistors whose emitters are coupled in common and whose bases are connected to first and second input terminals, respectively; a first constant-current source, one end and another end of which are connected to the common emitters of the first and second bipolar transistors of the differential transistor pair and to a first power supply terminal, respectively; a pair of third and fourth bipolar transistors whose bases are coupled in common with a second power supply terminal and whose emitters are connected to collectors of the respective first and second bipolar transistors; a fifth bipolar transistor whose collector and base are coupled and whose emitter is connected to a third power supply terminal; and a sixth bipolar transistor whose base, emmiter and collector are connected to the collector and base of the fifth bipolar transistor, to the third power supply terminal and to a collector of the third bipolar transistor, respectively; a seventh bipolar transistor whose base, emitter and collector are connected to the collectors of the third and sixth bipolar transistors, to the third power supply terminal and to an output terminal and a collector of the fourth bipolar transistor, respectively; an eighth bipolar transistor whose collector and base are connected to the collector and base of the fifth bipolar transistor and to the second power supply terminal, respectively; a ninth bipolar transistor whose collector and base are connected to an emitter of the eighth bipolar transistor and to a fourth power supply terminal, respectively; and a second constant-current source, one end and another end of which are connected to an emitter of the ninth bipolar transistor and to the first power supply terminal, respectively. BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawing in which: Fig. 1 is a circuit diagram of a conventional differential amplifier; Fig. 2 is a circuit diagram of a first embodiment of a differential amplifier according to the present invention; Fig. 3 is a circuit diagram of a second embodiment of a differential amplifier according to the present invention; Fig. 4 is a circuit diagram of a third embodiment of a differential amplifier according to the present invention; and Fig. 5 is a circuit diagram of a fourth embodiment of a differential amplifier according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in connection with its preferred embodiments with reference to the accompanying drawings, wherein like reference characters designate like or corresponding parts throughout the views and thus the repeated description thereof can be omitted for brevity. In Fig. 2, there is shown the first embodiment differential amplifier according to the present invention. A differential transistor pair is composed of first and second FETs M1 and M2 whose sources are coupled with each other in common and whose gates are connected to first and second input terminals t1 and t2, respectively. One end of a first constant-current source I1 is connected to the common sources of the FETs M1 and M2 and the other end to a low power supply terminal t4. The drain and gate of a third FET M3 is coupled with each other and the source of the same is connected to a high power supply terminal t5. The gate of a fourth FET M4 is coupled with the gate of the third FET M3, and the source with the high power supplhy terminal t5, and the drain with the drain of the first FET M1. The third and fourth FETs M3 and M4 constitute a current mirror circuit. The gate of a fifth FET M5 is connected to the drains of the first and fourth FETs M1 and M4, and the source to the high power supply terminal t5, and the drain to an output terminal t3 and to the drain of the second FET M2. The drain of a sixth FET M6 is connected to the drain of the third FET M3, and the gate to a bias power supply terminal t6. One end of a second constant-current source I2 is connected to the source of the sixth FET M6 and the other end of the same to the low power supply terminal t4. Next, the operation of the aforementioned differential amplifier will now be described. First, the differential transistor pair composed of the first and second FETs M1 and M2 distributes the current of the first constant-current source I1 depending on the signal voltages applied to the first and second input terminals t1 and t2 to flow the drain current. The current mirror circuit including the third and fourth FETs M3 and M4 outputs a current which is fixed and equal to the current value determined by the second constant-current source I2 and the sixth FET M6 and hence the variation of the drain current of the first FET M1 is transferred to the gate of the fifth FET M5. The variation of the drain current of the first FET M1 is amplified by the fifth FET M5 and the amplified current is output from the output terminal t3. On the other hand, the variation of the drain current of the second FET M2 turns to a value to negate the variation of the drain current of the first FET M1. That is, the drain current of the second FET M2 reduces in proportion to the increase of the drain current of the first FET M1. Hence, when the output is taken out as the voltage from the output terminal t3, a voltage gain AV in a low frequency of the differential amplifier is obtained as follows: AV =(1/2) · gm1 · {ro1 · ro4 · ri5/(ro1 · ro4 + ro4 · ri5 + ri5 · ro1)} · gm5 · {ro2 · ro5/(ro2 + ro5)} + (1/2) · gm2· {ro2· ro5/(ro2 + ro5)} wherein gm1, gm2 and gm5 represent transfer conductances of the first, second and fifth FETs M1, M2 and M5, respectively, and ro1, ro2, ro4 and ro5 represent output resistances of the first, second, fourth and fifth FETs M1, M2, M4 and M5, respectively, and ri5 represents an input resistance of the fifth FET M5. For example, one calculation with numeric values is instantiated as follows: when gm1 = gm2 = 4×10 -3 [siemens], gm5 = 2×10 -3 [siemens], ro1 = ro2 = 500 [kΩ], ro4 = ro5 = 200 [kΩ], and ri = 100 [kΩ], AV = (1/2) × 4 × (1000 × 17) × 2 × (1000/7) + (1/2) × 4 × (1000/7) ≒ 33899 [times] = 90.6 [dB] As described above, the differential amplifier shown in Fig. 2 has a very large voltage gain AV of approximately 91 [dB] in the low frequency. Further, in this differential amplifier shown in Fig. 2 or the conventional differential amplifier shown in Fig. 1, in general, the current value of the first constant-current source I1 is determined to twice as much as that of the second constant-current source I2 and the same transistor is used for the third and fourth FETs M3 and M4 so that the operating point current of the first and second FETs M1 and M2 constituting the differential transistor pair may be equal. In this embodiment, the insertion of the sixth FET M6 between the second constant-current source I2 and the pair of third and fourth FETs M3 and M4 of the current mirror circuit permits the voltages between the drain and source of the third and fourth FETs M3 and M4 to be nearly equal and hence the input offset voltage between the first and second input terminals t1 and t2 can be made nearly zero in the differential amplifier. Fig. 3 shows the second embodiment of a differential amplifier according to the present invention. In this embodiment, first, second and sixth bipolar transistors Q1, Q2 and Q6 are used in place of the respective first, second and sixth FETs M1, M2 and M6 of the first embodiment described above. In general, bipolar transistors have a better pair matching in integrated circuits than field-effect transistors. Thus, in this case, the input offset voltage can approach more close to zero. Fig. 4 illustrates the third embodiment of a differential amplifier according to the present invention. In this embodiment, different from the second embodiment shown in Fig. 3, third, fourth and eighth bipolar transistors Q3, Q4 and Q8 whose bases are coupled with another bias power supply terminal t7 are inserted between the first bipolar transistor Q1 and the fourth FET M4, between the second bipolar transistor Q2 and the fifth FET M5, and between the sixth bipolar transistor Q6 and the third FET M3, respectively. In this case, the addition of the pair of common base transistors Q3 and Q4 to the differential transistor pair of the first and second bipolar transistors Q1 and Q2 permits the increase of the voltage gain and further remarkable improvement against frequency characteristic degradation due to a Miller capacitance at the input terminal portions in addition to the effects obtained in the second embodiment shown in Fig. 3. Fig. 5 shows the fourth embodiment of a differential amplifier according to the present invention. In this embodiment, bipolar transistors Q15, Q16 and Q17 are used in place of the third, fourth and fifth FETs M3, M4 and M5 of the third embodiment shown in Fig. 4. In this case, the same effects as described above can also be obtained. Although in the second and third embodiments shown in Figs. 3 and 4, a bipolar-CMOS process is required in the production process of the integrated circuit and a producing cost rises, in the fourth embodiment, since the differential amplifier can be produced by a pure bipolar process, it is possible to provide a high gain, high speed, low offset differential amplifier at a lower cost. Further, the bipolar transistors, the field-effect transistors and the constant-current sources can, of course, be arranged in the reversed polarity in the circuits shown in Fig. 2 to Fig. 5 with the same effects. As described above, according to the present invention, a differential amplifier which has a large voltage gain at a low frequency signal input and is capable of reducing the input offset voltage of the conventional problem to nearly zero can be obtained and as a result, can be applied to a high accuracy signal processing circuit. While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope of the present invention.

Claims: A differential amplifier comprising: a differential transistor pair including first and second transistors (M 1 , Q 1 , M 2 Q 2 ) connected to first and second input terminals (t 1 , t 2 ), respectively, for distributing current depending on the voltage signal at first and second input terminals (t 1 , t 2 ), respectively; a first-constant current source (L 1 ) for supplying the current to be distributed by the differential transistor pair; a current mirror circuit comprising: a third transistor (M 3 , Q 15 ) whose drain or collector and gate or base are connected together and whose source or emitter is connected to a second power supply terminal (t5) and a fourth transistor (M 4 , Q 16 ) whose gate or base, source or emitter and drain or collector are respectively connected to the gate or base of the third transistor, to the second power supply and to the first transistor; a second constant-current source (I 2 ), connected in series with the third transistor; amplifying means for providing an amplified output characteristic of the difference between the distributed current comprising a fifth transistor (M 5 , Q 17 ) whose gate or base, source or emitter and drain or collector are respectively connected to the junction between the first transistor and the drain or collector of the fourth transistor, to the second power supply terminal, and to an output terminal (t 5 ), whereby the output terminal is connected to the second transistor; characterised in that the amplifier further comprises equalising means (M 6 , Q 6 ) for equalising the voltages between the respective drains or collectors and sources or emitters of the third and fourth transistors thereby minimising an offset voltage between the first and second input terminals (t 1 ,t 2 ). A differential amplifier according to Claim 1, wherein the first constant-current source (I 1 ) has one end connected to the differential transistor pair and the other end connected to a first power supply terminal (t 4 ); said equalising means equalises the voltages between the third and fourth transistor is a sixth transistor (M 6 , Q 16 ) whose drain or collector is connected to the drain or collector of the third transistor and whose gate or base is connected to a third power supply terminal (t 6 ); and a second constant-current source (I 2 ), one end and another end of which are connected to the source or emitter of the sixth transistor and to the first power supply terminal (t 4 ), respectively. A differential amplifier according to Claim 2, characterised in that the third, fourth and fifth transistor are field-effect transistors (M 3 , M 4 , M 5 ). A differential amplifier according to Claim 3, characterised in that the first and second transistors of the differential transistor pair are field-effect transistors (M 1 , M 2 ) and the sixth transistor is a field-effect transistor (M 6 ). A differential amplifier according to Claim 2, characterised in that the third, fourth and fifth transistors are bipolar transistors (Q 15 , Q 16 , Q 17 ). A differential amplifier according to Claim 3 or 5, characterised in that the first and second transistors of the differential transistor pair are bipolar transistors (Q 1 , Q 2 ) and the sixth transistor is a bipolar transistor (Q 6 ). A differential amplifier according to Claim 6, further comprising three more bipolar transistors (Q 3 , Q 4 , Q 8 ) in which: the collectors of said first, second and sixth transistors (Q 1 , Q 2 Q 6 ) are instead connected to the emitters of said third, fourth and eight bipolar transistors (Q 3 , Q 4 , Q 8 ) respectively; the collector of said third bipolar transistor (Q 3 ) is connected to the drain of the fourth field-effect transistor (M 4 ); the collector of the fourth bipolar transistor is coupled with the output terminal (t 3 ) and the drain of the fifth field-effect transistor (M 5 ); the collector of the eighth bipolar transistor (Q 8 ) is connected to the gate and drain of the third field effect transistor (M 3 ); and the bases of said third, fourth and eighth transistors (Q 3 , Q 4 , Q 8 ) are connected to a fourth power supply terminal (t 7 ).

Inventors: SONE KAZUYA, SONE, KAZUYA, SONE, KAZUYA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03F3
IPC codes: H03F3