Di-electric isolated type semiconductor device

Abstract: A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions (5, 6, and 7) are formed as active regions on a surface portion of an islandish semiconductor region (100) which is isolated from an adjacent semiconductor region (200) by means of an isolation trench (9a). According to a first aspect of the present invention, an N type crystalline defect suppression region (11) doped at a high concentration and deeper than the high-concentration regions (5, 6, and 7) is formed over the entire surface of an adjacent semiconductor region (200). According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region (110) is provided on a surface portion of a P type high-concentration region (50) is formed with identical structure and by an identical production process. By means of these N type regions (11, 110), crystalline defects are reduced.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolated type semiconductor device. 2. Description of the Related Arts Conventionally, an dielectric isolated type semiconductor device having an island semiconductor region the bottom of which is isolated from a semiconductor substrate and the side of which is isolated from an adjacent semiconductor region by means of an isolation trench, with active elements such as transistors and diodes formed in this island semiconductor region, has been widely produced. In such a dielectric isolated type semiconductor device, it is important to reduce crystalline defects in order to improve the characteristics of the active elements formed in the island semiconductor region, but conventionally the addition of complex production processes was required for this purpose. In particular, compression stress on the surface of an island semiconductor region in a dielectric isolated type semiconductor device is large in comparison with a semiconductor device of PN junction isolated type, and so crystalline defects easily occur. Further information relating to the prior art can be found in the following documents. EP-A-0 628 996, which is comprised in the prior art in accordance with Art. 54(3) EPC, describes a semiconductor device comprising a semiconductor layer of a first conductivity type formed over a substrate; an island-like semiconductor region of a second conductivity type formed from the surface of said semiconductor layer into the inside thereof and higher in impurity concentration than said semiconductor layer; a side dielectric isolation region formed from the surface of said semiconductor layer into the inside thereof and formed deeper than said island-like semiconductor region and separates an element region formed within said island-like semiconductor region from the other semiconductor layer regions; and an adjacent semiconductor region disposed in adjacency to said element region with said side dielectric isolation region therebetween; wherein a voltage that allows a depletion layer between a semiconductor layer within said element region and said island-like semiconductor region to reach said side dielectric isolation region is applied to between the semiconductor layer within said element region and said island-like semiconductor region, and wherein said adjacent semiconductor region has electric potential that is more approximate to that at said island-like semiconductor region rather than to that at said element region. EP-A-0 615 286, which is comprised in the prior art in accordance with Art. 54(3) EPC, describes a semiconductor device in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant. US-A-5, 241, 210 discloses a high breakdown voltage semiconductor device that includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region. A fifth semiconductor region having an impurity concentration lower than that of the second or fourth semiconductor region is formed on a bottom portion of the first semiconductor region. When a reverse bias is applied between the second and fourth semiconductor regions, a depletion layer extends vertically in the first semiconductor region and laterally in the fifth semiconductor region. The applied voltage is divided in both the directions and a high breakdown voltage can be obtained. WO-A-93/08596 discloses a method for fabrication of a semiconductor device that is directed to prevent step breakage and short-circuit of wires resulting from steps of isolation trenches formed in an SOI substrate. An oxide film for a pad is formed on a main plane of an SOI layer formed on an insulating substrate and furthermore, a silicon nitride film and an SiO 2 film are sequentially formed. Thereafter, isolation trenches reaching the insulating substrate are formed by RIE using the SiO 2 film as the mask. An insulating film is then formed on the inner wall of the isolation grooves by thermal oxidation, and polycrystalline silicon is filled into the insolation trenches. This polycrystalline silicon is etched back while control is made so that the upper end of polycrystalline silicon inside the isolation trenches is above the upper end of the silicon nitride film, and the excessive polycrystalline silicon deposited on the substrate surface is removed. Next, polycrystalline silicon inside the isolation trenches and the silicon nitride film are used as an etching stopper to etch and remove the SiO 2 film used as the mask at the time of the formation of the isolation trenches. Since this etching and removal of the SiO 2 film used as the mask is carried out after polycrystalline silicon is filled into the isolation trenches, the oxide film for isolating the substrates inside the SOI substrate is not etched when the mask is removed. When the masking SiO 2 film is etched and removed, polycrystalline silicon and the silicon nitride film inside the isolation trenches function as the etching stopper, and the oxide film for the pad as the lower layer and the insulating rilm formed on the inner wall of the trenches are prevented from being etched, and flatness in the trench portions is not lost. In light of the foregoing problem point, it is the object of the present invention to provide a dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process. This object is solved by the advantageous features indicated in the characterizing part of claim 1. In a favorable state, the N type crystalline defect suppression region of claim 1 is formed with doping 1 x 10 19 atoms/cm 3 or more of phosphorus. In this arrangement, a high-concentration region is formed as an active region on a surface portion of an island semiconductor region the side of which is isolated from an adjacent semiconductor region by means of an isolation trench. It was ascertained by experimentation that a semiconductor device in which the above-mentioned N type crystalline defect suppression region is formed according to the present invention can markedly reduce crystalline defects in comparison with a semiconductor device of identical structure and formed by an identical production process but not formed with the foregoing N type crystalline defect suppression region. Moreover, it was ascertained that a semiconductor device according to the present invention providing a high-concentration N type crystalline defect suppression region on a surface portion of a P type high-concentration region can markedly reduce crystalline defects in comparison with a prior art semiconductor device of identical structure and formed by an identical production process but not formed with the foregoing N type crystalline defect suppression region. The above-mentioned mode of operation is hypothesized to be due to a gettering effect of heavy-metal ions causing crystalline defects by means of phosphorus ions which become the dopant of the N type region. That is to say, it is known that the doping diffusion coefficient in an insulation material of oxide film or the like normally has a difference in order of several decimal places in comparison with that within a semiconductor region, and diffusion speed is extremely slow; consequently, it was thought that heavy metal contamination of an islandish semiconductor region isolated by means of insulation material did not become a problem, but according to the present experimentation it is conjectured that even if an isolation region existed, heavy metal contamination via the isolation region would exist to a certain extent, and heavy metal contamination could be prevented by means of an N type crystalline defect suppression region. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and characteristics of the present invention will be appreciated from a study of the following detailed description, the appended claims, and drawings, all of which form a part of this application. In the drawings: FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a sectional view indicating a production process of the first embodiment; FIG. 3 is a sectional view indicating a production process of the first embodiment; FIG. 4 is a sectional view indicating a production process of the first embodiment; FIG. 5 is a partial plan view of a semiconductor device according to the first embodiment; FIG. 6 is a diagram describing effects of a semiconductor device according to the first embodiment; FIG. 7 is a diagram describing effects of a semiconductor device according to the first embodiment; FIG. 8 is a sectional view of a semiconductor device according to an example not forming part of the present invention; FIG. 9 is a partial plan view of a semiconductor device according to the example not forming part of the present invention; FIG. 10 is a graph showing a forward bias characteristic of a semiconductor device according to the example not forming part of the invention; FIG. 11 is a graph showing a forward bias characteristic of a conventional semiconductor device; and FIG. 12 is a sectional view of a semiconductor device according to an example not forming part of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a high withstand voltage NPN bipolar transistor as a first embodiment according to a first aspect of the present invention. In FIG. 1, 1 is a P - silicon substrate (semiconductor substrate), 2 is a buried silicon oxide film as bottom insulation for an island semiconductor region, 3 is an N + buried collector region, 4 is an N - collector withstand voltage region, 5 is a P + base region, 6 is an N + emitter region, 7 is an N + surface collector region, 8 is a polysilicon region filling a trench, and 9a is a silicon oxide film (isolation trench) surrounding the sides of the island buried collector region 3 and collector withstand voltage region 4 immediately thereabove. The regions 5, 6, and 7 are so-called high-concentration regions according to the present invention. Additionally, 10 is a surface silicon oxide film, E, B, and C are respectively an emitter contact electrode, base contact electrode, and collector contact electrode composed of aluminum, 40 is an N - region surrounding the lateral periphery of this bipolar transistor with the silicon oxide film 9a interposed therebetween, 11 is an N + region (the so-called N type crystalline defect suppression region according to the present invention) formed deeply in this N - region 40, 12 is an N + contact region formed on the surface portion of this N + region 11, and 30 is a buried N + region immediately below the N - region 40. A production process of this transistor will be described hereinafter. Firstly, as shown in FIG. 2, an N - type (110) monocrystalline silicon substrate 40 of relative resistance 3 to 5 Ohm-cm which is mirror polished is prepared, and antimony is diffused to 3 µm in the surface thereof with a vapor phase diffusion method to form an N + diffusion layer 30. Additionally, after one main face of the P - substrate 1 is separately mirror polished, thermal oxidation is performed to form the silicon oxide film 2 with a thickness of approximately 1.0 µm. These silicon substrate 1 and silicon substrate 40 are heated with an H 2 O 2 -H 2 SO 4 liquid mixture, undergo hydrophilic treatment, are joined in a clean atmosphere at room-temperature, and are heated for two hours in a 1,100°C N 2 atmosphere to bond. Next, mirror polishing is performed until for example the substrate 40 side reaches a thickness of 15 µm to form an SOI substrate. Next, a field oxide film of approximately 0.5 µm is formed on the surface of this SOI substrate with thermal oxidation, and a 0.1 µm silicon nitride film is formed thereon with an LPCVD method. Next, a resist mask is formed on the silicon nitride film, plasma etching and reactive ion etching by means of fluorine etching gas are performed, and a trench T1 is formed around the region where the bipolar transistor is to be formed and extending to the silicon oxide film 2. This trench T1 has a plane layout as shown in FIG. 5, and later becomes the polysilicon region 8. The surface of this trench T1 is oxidized to form the silicon oxide film 9a. Subsequently, polysilicon deposition is performed with the LPCVD method, the trench T1 is buried. Then, excess polysilicon deposited on the silicon nitride film surface is removed, the polysilicon surface exposed on the trench T1 surface is oxidized, and subsequently the silicon nitride film is removed by dry etching. By means of this, a polysilicon region 8 surrounded by the silicon oxide film 9a is formed in the interior of the trench T1, as shown in FIG. 3. That is to say, an island N + buried collector region 3 and N - collector withstand voltage region 4 as the so-called island semiconductor region 100 according to the present invention are isolated from the N + diffusion layer 30 and N - region 40 by means of this silicon oxide film 9a. Accordingly, the remaining N + region 30 and N - region 40, which surround this island semiconductor region 100 with the silicon oxide film 9a disposed therebetween, constitute a so-called adjacent semiconductor region 200 according to the present invention. Next, as shown in FIG. 4, the region other than the adjacent semiconductor region 200, i.e., the island semiconductor region 100, is covered with a mask 300 and ion implantation of phosphorus ions is performed at approximately 10 16 dose/cm 2 with 100 keV, the implanted ions are driven in under conditions of 1,170°C for five hours, and by means of this the N type crystalline defect suppression region 11 of a doping concentration of 10 19 atoms/cm 3 or more is formed in the n - region 40 of the adjacent semiconductor region 200. Next, as shown in FIG. 1, the P + base region 5, N + emitter region 6, N + surface collector region 7, and N + contact region 12 are formed by a known series of processes, i.e., photolithographic process, ion implantation process, and drive-in process, and subsequently contact holes for electronic contact use are formed in the oxide film 10, and the respective electrodes E, B, C, and 13 are provided. An example of parameters of the respective portions will be given below. The doping concentration of the N - collector withstand voltage region 4 was set at 1 x 10 15 atoms/cm 3 , the doping concentration at the surface of the P + base region 5 was set at 3 x 10 18 atoms/cm 3 , the doping concentration of the N + emitter region 6 was set at 1 x 10 20 atoms/cm 3 , the thickness of the collector withstand voltage region 4 between the base region 5 and buried collector region 3 was set at 4 µm, the doping concentration of the polysilicon region 8 filled within the trench was set at 1 x 10 20 atoms/cm 3 , the width thereof was set at 1 µm, the thickness of the silicon oxide film 9a was set at 0.7 µm, and the junction depth of the base region 5 was set at 3 µm. Furthermore, the width of the adjacent semiconductor region 200 was set at approximately 10 µm, the depth of the N type crystalline defect suppression region 11 was set at approximately 10 µm, and the plane dimensions W1 x W2 of the island semiconductor region 100 were set at 50 µm x 100 µm. A partial plan view is indicated in FIG. 5. Next, FIG. 6 and FIG. 7 indicate the numbers of occurrence of crystalline defects per unit of square area (here 9 mm 2 ) in cases where the N type crystalline defect suppression region 11 was or was not formed. FIG. 7 is the average number of crystalline defects within the island semiconductor region 100, and FIG. 6 is the average number of crystalline defects within the adjacent semiconductor region 200 (20 samples). It was understood through this experimentation that crystalline defects can be markedly reduced by means of formation of the N type crystalline defect suppression region 11. Additionally, according to the foregoing embodiment, the N type crystalline defect suppression region 11 was doped after trench T1 formation. This is for the purpose of preventing lateral spread of the N type crystalline defect suppression region 11 due to drive-in. However, it is also possible to dope the N type crystalline defect suppression region 11 before trench T1 formation. FIG. 8 shows a high withstand voltage junction diode as an example of a dielectric isolated type semiconductor device not forming part of the present invention. This embodiment is an example of a junction diode formed in an island semiconductor region 100, with 50 being a P + region constituting an anode thereof, 60 being an N + region constituting a cathode thereof, 28 being an anode electrode, and 29 being a cathode electrode, composed respectively of doped polysilicon (or aluminum). In particular, according to the present example an N type crystalline defect suppression region 110 with a doping concentration of 10 20 to 10 21 atoms/cm 3 is formed on the surface portion of the P + region 50 in a state allowing a contact region of the anode electrode 28 and P + region 50 to remain. In addition to this, 1 is a P - silicon substrate (semiconductor substrate), 2 is a buried silicon oxide film for bottom insulation use, 3 is an N + buried region, 4 is an N - withstand voltage region, 8 is a polysilicon region filled in a trench (a so-called adjacent semiconductor region according to the present invention), and 9a is a silicon oxide film (isolation trench) surrounding the sides of the island buried N + region 3 and N - withstand voltage region 4 immediately thereabove. Additionally, 18 is a LOCOS oxide film and 19 is a silicon oxide film formed thereabove. The production process of this diode is fundamentally the same as the transistor of FIG. 1; the N type crystalline defect suppression region 110 and N + region 60 are formed with the same process as the emitter region 6 and collector region 7 of FIG. 1, and the P + region 50 is formed with the same process as the base region 5 of FIG. 1, but as shown in FIG. 8, the P + region 50 and N + region 60 are formed by means of ion implantation utilizing the opening of the LOCOS oxide film 18. In concrete terms, after the formation of the openings on the LOCOS oxide film 18, a resist mask is applied to the LOCOS oxide film 18 to form the P + region 50, the foregoing resist mask is subsequently removed, a new resist mask is applied to form the N + region 60 and N type crystalline defect suppression region 110, and subsequently the foregoing resist mask is removed. Then, after a silicon oxide film 19 is deposited, patterning is performed on the silicon oxide film 19 to form contact openings and next the electrodes 28 and 29 are provided. The electrode 28 contacts both the P + region 50 and the N type crystalline defect suppression region 110. Further, the P + region 50 has a doping concentration of 1 x 10 18 atoms/cm 3 or more, which is less than the N type crystalline defect suppression region 110. Additionally, according to this example, the foregoing N type crystalline defect suppression region 11 of the first embodiment is not formed in an adjacent region. An example of parameters of the respective portions will be given below. Parameters which are not stated are the same as for the first embodiment. In FIG. 9, the plane dimensions L1 x L4 of the P + region 50 were set equal to approximately 50 µm x 20 µm, the junction depth thereof was set at approximately 3 µm, the width L3 of the N + region 60 was set at approximately 10 µm, the interval L2 between the P + region 50 and N + region 60 was set at approximately 10 µm, the distance d1 from the P + region 50 to the isolation region was set at approximately 5 µm, d2 was set at approximately 5 µm, and the junction depth of the N type crystalline defect suppression region 110 was set at approximately 2 µm. FIG. 10 indicates the forward bias characteristics of the above-described diode, and FIG. 11 indicates the average forward bias characteristics (20 samples) in a case of identical production process and identical masking as the foregoing diode but no doping of the N type crystalline defect suppression region 110. It is understood from FIG. 10 and FIG. 11 that a junction diode according to the present example has excellent characteristics. FIG. 12 shows a high withstand voltage PNP transistor as an embodiment of a dielectric isolated type semiconductor device according to an example not forming part of the present invention. This example shows a lateral PNP bipolar transistor formed in an island semiconductor region 100, with 50 being a P + region constituting an emitter region thereof, 60 being an N + region constituting a surface base region thereof, 70 being a P + region constituting a collector thereof, 71 being a P + region for leak current cutting-off use, 110 being an N type crystalline defect suppression region, 28 being an emitter electrode, and 29 being a base electrode, and 30 being a collector electrode, composed respectively of doped polysilicon (or aluminum). As can be immediately understood by comparing FIG. 12 and FIG. 8, the lateral PNP bipolar transistor of FIG. 12 is formed by the identical process as the junction diode production process of FIG. 8. That is to say, the N type crystalline defect suppression region which constitutes a characteristic of this embodiment can also be incorporated within the P + emitter or P + collector of a PNP bipolar transistor. Additionally, the N type crystalline defect suppression region 11 provided in the adjacent semiconductor region of the embodiment may also be provided in an adjacent semiconductor region of the shown examples. While the present invention has been shown and described with reference to the foregoing preferred embodiment, it will be apparent to those skilled in the art that changes in form and detail may be made therein without departing from the invention as defined in the appended claims.

Claims: A dielectric isolated type semiconductor device comprising an island semiconductor region (100), the bottom of which is isolated from a semiconductor substrate (1) and an adjacent semiconductor region (200) electrically isolated from, and disposed proximate to, said island semiconductor region (100), so that the upper surface of said island semiconductor region (100) is flush with the upper surface of the adjacent semiconductor region, said island semiconductor region (100) having a high-concentration region (5, 6, 7) formed in a portion directly beneath its upper surface; characterized in that said adjacent semiconductor region surrounds said island semiconductor region (100); and said adjacent semiconductor region comprises an N type crystalline defect suppression region (11) doped at a high concentration, said N type high concentration region (11) extending from said upper surface to a depth larger than the depth from the upper surface of said high concentration region within said island semiconductor region. The dielectric isolated type semiconductor device according to claim 1, further comprising an isolation trench (T1) disposed between said island semiconductor region (100) and said adjacent semiconductor region (200), whereby a side of said island semiconductor region (100) is isolated from said adjacent semiconductor region (200). The dielectric isolated type semiconductor device according to claim 2, wherein said N type crystalline defect suppression region (11) is formed on an entire surface of said adjacent semiconductor region (200). The dielectric isolated type semiconductor device according to any preceding claim, wherein said N type crystalline defect suppression region (11) is formed with doping 1 x 10 19 atoms/cm 3 or more of phosphorus.

Inventors: IIDA MAKIO, MIURA SHOJI, SAKAKIBARA TOSHIO, SUGISAKA TAKAYUKI, IIDA, MAKIO, MIURA, SHOJI, SAKAKIBARA, TOSHIO, SUGISAKA, TAKAYUKI
Applicants: DENSO CORP, DENSO CORPORATION
Application year: 1994
Main classification: H01L21
IPC codes: H01L21, H01L29