Synchronized clocking disable and enable circuits

Abstract: A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation. The clocking disable and enable circuit herein is also well suited for providing temporary halt to the connected digital or analog circuit as well as providing periods of selective demodulation associated with frequency tracking communication systems.

Description: This invention relates to an electronic circuit and more particularly to a synchronized clocking disable and enable circuit. A clocking circuit used for generating a plurality of pulses is well known. The pulses are preferably produced with extreme regularity and are often synchronized with the operation of digital circuits attached to the output of the clocking circuit. The clocking pulses are thereby used to control the speed of operation of the digital circuits which may be contained on the same monolithic circuit as that of the clocking circuit. In order to ensure optimal performance of the digital circuit receiving the pulses, each pulse must have a set duration and the duration must not substantially vary. For example, a high level voltage pulse must remain high for a minimum duration but not to exceed that of a maximum duration. Likewise, a low level voltage pulse must also remain low more than and less than a minimum and maximum duration, respectively. If a high or low pulse is less than an acceptable time duration, then a "glitch" may occur causing possible failure of the connected digital circuits. It is oftentimes desirable to temporarily disable the stream of clocking pulses produced from the clocking circuit. By disabling the clocking pulses, certain attached digital circuits can be temporarily placed in a halt condition. For example, microprocessor or microcontroller operations can generally be halted in such a manner. To perform a temporary disable of the clocking pulses, a clocking disable and enable circuit is generally placed between the clocking circuit and the corresponding digital circuits. The clocking disable and enable circuit receives free-running, continuous periods of clocking pulses, and also receives a disable signal which can exceed several clocking periods. When the disable signal is activated, the clocking disable and enable circuit sends to the digital circuits a steady state output indicating a momentary halt of clocking pulses. During the time in which the clocking disable and enable circuit receives the disable signal, a transitional glitch often occurs in the output of conventional disable and enable circuits causing the connected digital circuits to malfunction. The glitch, defined herein as a clocking pulse having a duration less than the target pulse duration, may cause the attached digital circuits to lose or misplace operational status or data (stored or modulated data). Accordingly, many conventional disable and enable circuits generally provide one or more glitches each time the output transitions from the clocking state to the disable or steady state. Likewise, when the disable and enable circuit re-enables clock pulses, one or more glitches may also appear at the output during transitions from the steady state to the clocking state. The problems outlined above are in large part solved by the synchronized clocking disable and enable circuit we shall describe herein. That is, the disable and enable circuit hereof ensures that no glitches occur during the output transition between a free-running clocking state and a steady state. Steady state output does not occur until after an entire high or low pulse duration of the clocking pulses has occurred but before the next pulse. Likewise, when the disable signal ceases, the disable and enable circuit output transitions after an entire high or low pulse duration of the clocking pulses has occurred but before the next pulse. After disable has ended, the disable and enable circuit output transitions back to a clocking state, wherein the clocking state is substantially equal to and in sync with the clocking pulses produced from the clocking circuit. By assuring a glitch-free transition, the circuit is suited for applications requiring a disable and enable circuit output synchronized with the clocking pulses output from the clocking circuit. Such applications include, but are not limited to, demodulators and microprocessor-based timing circuitry. Microprocessors which are designed for static operation (i.e., those which are capable of retaining their state when the internal clock is held in a constant state) can easily incorporate the present invention in order to smoothly transition from dynamic to static operation and vice versa. Furthermore, microprocessors which require a phase locked loop (PLL) clocking configuration and output find it necessary to provide a smooth dynamic to static, or static to dynamic transition. Yet a PLL cannot provide such a transition when it is stopped and restarted on the fly. PLLs generally require a long startup period in order to synchronize or lock onto a clocking output. Thus, it is desirable to allow the PLL to run freely, and to place a synchronizing disable/enable circuit of the present invention between the PLL and the internal clock drivers of the microprocessor (or digital circuitry). The PLL can continue running while the disable/enable circuit disables or enables the internal drivers in sync with the PLL clocking pulses. A substantial amount of power is consumed when a microprocessor's internal clock runs. Disabling the internal clock at synchronized moments and placing the processor into a static state is a very desirable feature. Momentary disable of the processor will control the power consumption, resulting in cooler operating temperatures and, in a battery operated environment, providing longer battery life between charges. US-A-4,540,945 discloses a highly stable tunable oscillator circuit that includes a multiple stage latching circuit, and a logic gate coupled to the output of the latching circuit, the logic gate having two inputs and a single output and the latching circuit receiving the clocking signal. According to the present invention there is provided a clocking disable and enable circuit comprising a multiple stage latching circuit having a latching input and a latching output, and a logic gate coupled to the output of the latching circuit, the logic gate having two inputs and a single output, and the latching circuit receiving a clocking signal (CLK) and further receiving a clock disable/enable signal (D/E) at its latching input to provide a delayed disable/enable signal (D.D/E) at its latching output in response to the clocking signal (CLK), one input of the logic gate being coupled to receive the delayed disable/enable signal (D.D/E) and other logic input being coupled to receive the clocking signal (CLK), the logic gate thereby producing a logic output signal synchronized with the clocking signal, characterized in that each transition of the disable/enable signal (D/E) is propagated through the latching circuit to produce a corresponding subsequent transition of the delayed disable/enable signal (D.D/E), such that each rising transition of the delayed disable/enable signal corresponds to a prior rising edge of the disable/enable signal, and each falling transition of the delayed disable/enable signal corresponds to a prior falling edge of the disable/enable signal, wherein the latching circuit includes at least three stages, so arranged that a second stage of the three stages is configured to respond to an inverted clocking signal with respect to a first and third stage of the three stages, such that an oppositely-directed transition of the clocking signal is needed for disable/enable signal transmission through the second stage as compared to the first and third stages, and such that the clock disable/enable signal (D/E) is delayed by a variable period of at least one half cycle of the clocking signal. The three stages of the latching circuit are preferably connected in series, each stage including a selectively conductive path in series with a latch. The variable delay period introduced by the latching circuit provides a glitch-free transition between the clocking signal and the steady state voltage, the delay being dependent on the transition time of the disable/enable signal relative to the rising and falling edges of the clocking signal. The steady state voltage can be either a logic level high or a logic level low depending upon the configuration of the clocking disable circuit. The clocking disable and enable circuit can be configured to receive opposite polarities of the clocking signals and, depending upon the polarity configuration chosen, the clocking disable and enable circuit can produce either a relatively high steady state voltage or a relatively low steady state voltage at its output. If, for example, the steady state output from the clocking disable and enable circuit is at a relatively low voltage level, then the logic gate is preferably configured as a NAND gate and the low steady state output is produced at the transition of the clocking signal from a relatively high voltage level to a relatively low voltage level during times in which the nand gate receives the delayed disable signal. Conversely, and as a further example, if steady state output is at a relatively high voltage level, then the logic gate is preferably configured as a nor gate and the high steady state output is produced at the transition of the clocking signal from a relatively low voltage level to a relatively high voltage level during times in which the nor gate receives the delayed disable signal. In the former example, the steady state output signal is of opposite polarity to and begins immediately after the high voltage pulse duration of one cycle of the clocking signal has occurred and continues until immediately after another high voltage pulse duration of a subsequent cycle of the clocking signal has occurred. Conversely, in the latter example, the steady state output signal is of opposite polarity to and begins immediately after the low voltage pulse duration of one cycle of the clocking signal has occurred and continues until immediately after another low voltage pulse duration of a subsequent cycle of the clocking signal has occurred. The clocking circuit can be used in a carrier signal frequency tracking system. The tracking system includes an oscillator. The clocking circuit has one input coupled to receive a clocking signal from the oscillator and another input coupled to receive the disable/enable signal. The tracking system further includes a frequency shift detector circuit having two detector inputs and a detector output. The detector output varies in voltage magnitude depending upon the frequency difference between a carrier signal placed on one detector input. Accordingly, the oscillator can be voltage controlled and the frequency shift detector can be placed within the feed-back loop of the voltage controlled oscillator to form a demodulator or phase-locked loop. Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which, by way of example only: Fig. 1 is a block diagram of an exemplary carrier signal frequency tracking system according to the present invention; Fig. 2 is a circuit diagram of one embodiment of the clocking disable and enable circuit according to the present invention; Fig. 3 is a circuit diagram of another embodiment of the clocking disable and enable circuit according to the present invention; Fig. 4 are timing diagrams of various signals received and produced by the clocking disable and enable circuit shown in Fig. 2; and Fig. 5 are timing diagrams of various signals received and produced by the clocking disable and enable circuit shown in Fig. 3. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is cover all modifications, equivalents and alternatives falling within the scope of the appended claims. Turning now to the drawings, Fig. 1 illustrates a block diagram of an exemplary carrier signal frequency tracking system 10 of the present invention. Tracking system 10 includes terminal 12 capable of receiving an input signal. The input signal can be sent or modulated on a carrier signal, wherein the carrier signal is fixed at a carrier frequency. In order to demodulate the input signal from the carrier signal, it is important that system 10 be synchronized to track the carrier frequency. Tracking techniques often utilize a phase-locked loop (PLL) common in the art. The phase-locking occurs by using a phase detector 14 for receiving the modulated input signal. Feedback information from the phase-locked loop arise at phase detector 14 such that phase detector 14 acts as a mixer. A low pass filter 16 transmits substantially DC voltage at its output. Depending upon the difference between the carrier signal frequency and the output of oscillator 18, varying DC offset voltage occurs at the output of low pass filter 16. Oscillator 18 is a voltage controlled oscillator which produces a PLL output clocking signal (CLK signal) of varying frequencies depending upon the change in DC offset voltage output from filter 16. Accordingly, oscillator 18 transmits CLK signal to phase detector 14. If the frequency of the clocking signal matches the carrier frequency at terminal 12, then phase detector 14 produces little or no DC offset. Minimum amounts of offset will not cause oscillator 18 to change frequency output. Oscillator 18 output, or clocking signal, is therefore said to be "locked" in frequency and in phase with the carrier frequency. If any change occurs in the carrier frequency, then offset will exist causing a corresponding change in the clocking signal (or CLK signal). In many instances it is necessary that clocking signals be disabled momentarily or that tracking system 10 be temporarily halted. If such is the case, a disable and enable circuit 20 may be incorporated between oscillator 18 and internal clock drivers 21. Clock drivers 21 provide necessary output levels for driving an attached digital circuit or processor (not shown). Upon receiving a disable/enable signal (D/E signal), circuit 20 will force clocking signal to become disabled in either a steady state high or low voltage depending upon the configuration of circuit 20. A particular advantage of circuit 20 as described hereinbelow is the ability to disable the clocking signal at a clocking signal transition and then subsequently re-enable the clocking signal at a clocking signal transition. Disable and enable occur without any glitches being produced at the clocking disable/enable signal (CLK D/E signal). The clocking disable/enable signal sent from circuit 20 to internal clock drivers 21 is therefore in sync with the input clocking signal. Transfers between a clocking state and a steady state occur in sync with the input clocking signal such that system 10 remains in clocking signal sync even after momentary halting operation. Continued synchronization is necessary to achieve optimal performance of system 10. The PLL can run freely even though disable/enable circuit 20 output is halted. It is important to note, however, that a PLL need not always be used in conjunction with disable/enable circuit 20. Circuit 20 can in such instances be used to allow an asynchronous clock disable and enable output. Referring to Fig. 2, a circuit diagram of one embodiment of clocking disable and enable circuit 20 is shown. Circuit 20 includes a multiple stage latching circuit 22. Each stage of latching circuit 22 comprises a transmission gate or pass gate 24, reverse-coupled inverters 26 and 28 (shown in a latching configuration), and another inverter/buffer 30. There are three latching stages shown in latching circuit 22 of Fig. 2. In order for the output of circuit 22 to transition without glitches, at least three stages are needed to provide the necessary delaying of the disable/enable signal. By using three stages, the delay disable/enable signal (D. D/E signal) is ensured of toggling at least one half a clocking signal cycle after the time in which the disable/enable signal (D/E signal) is transitioned. By delaying the disable/enable signal at least one half a clocking cycle, the delayed disable/enable signal does not toggle until all transients of the disable/enable signal are resolved. The delayed disable/enable signal also synchronizes with a falling edge of the input CLK (shown in the embodiment of Fig. 2) or synchronizes with the rising edge of input CLK (shown in the embodiment of Fig. 3). Clocking signal (CLK signal) activates the first and third stages of circuit 22 during the relatively low clocking cycles/pulses. Likewise, clocking signal activates the second stage of circuit 22 during high clocking cycles/pulses. The selectively conductive paths formed by modulated transmission gates 24 allow disable/enable signal to be transmitted via the clocking signal to an output of circuit 22. The transmitted disable/enable signal is delayed at least one half a clocking cycle, and is presented as delayed disable/enable signal (D. D/E signal). A logic gate 32 receives the delayed disable/enable signal and combines that signal with the clocking signal. In the embodiment shown in Fig. 2, the disable/enable signal and clocking signal are nanded together and, after inversion, form a clocking disable/enable signal (CLK D/E signal) as shown. Clocking disable/enable signal is in a clocking state and synchronized with the clocking signal during times in which the delayed disable/enable signal is not active. During times in which delayed disable/enable signal is active, clocking disable/enable signal assumes a steady state value. An important advantage of the present invention is not only the ability to synchronize the clocking disable/enable signal with the clocking signal, but also to delay the disable/enable signal until after all transients associated with the signal have passed. Still further, changes in state of the clocking disable/enable signal between a steady state and a synchronized clocking occur without any glitches, and the resulting clocking state always remains of the same polarity and synchronized with the clocking signal when the delayed disable/enable is not active. The embodiment shown in Fig. 2 illustrates one example of circuit 20 connected such that the delayed disable/enable signal transitions coincident with the clocking signal from a high to low state, and the resulting clocking disable/enable signal will then disable to a low voltage state. Conversely, during times in which the delayed disable/enable signal transitions from a low to a high state, clocking disable/enable signal will follow the clocking signal. The following table I illustrates the operation of circuit 20 shown in Fig. 2, wherein the delayed disable/enable signal represents a similar but delayed polarity signal of the disable/enable signal: D. D/E Signal CLK Signal CLK D/E Signal 1 1 1 1 0 0 0 1 0 0 0 0 Referring to Fig. 3, an alternative embodiment of disable and enable circuit 20 is shown. In particular, circuit 20 can be configured having a multiple stage latching circuit similar to that shown in Fig. 2. However, instead of logic gate 32 being a nand gate, as shown in Fig. 2, logic gate 32 can be a nor gate, as shown in Fig. 3. The delayed disable/enable signal can be nored with the clocking signal to produce, after inversion, clocking disable/enable signal as shown. Using a nor gate instead of a nand gate is preferred if it is desirable that clocking disable/enable signal be disabled in a steady state high voltage level. Thus, either embodiment shown in Figs. 2 and 3 can be used depending upon the design requirements of the steady state output of clocking disable/enable signal. The embodiment of Fig. 2 produces a low voltage steady state disabled output, while the embodiment of Fig. 3 produces a high voltage steady state disabled output. Depending upon the value of disable/enable signal-desired, one of the two alternative embodiments may be chosen. If a clock disable is desired in a low transition state, then the embodiment shown in Fig. 2 is preferred. Conversely, if a clock disable is desired in a high state, then the embodiment shown in Fig. 3 is preferred. The following table II illustrates the operation of circuit 20 shown in Fig. 3, wherein the delayed disable/enable signal represents a similar but delayed polarity signal of the disable/enable signal: D. D/E Signal CLK Signal CLK D/E Signal 1 1 1 1 0 1 0 1 1 0 0 0 Further details regarding the operation of disable and enable circuit 20 for either embodiment is illustrated in Figs. 4 and 5. Specifically, Fig. 4 shows a timing diagram for various signals produced according to the embodiment of Fig. 2. Fig. 5 shows a timing diagram for various signals produced according to the embodiment of Fig. 3. Referring to Fig. 4, disable/enable signal can toggle from a high voltage state to a low voltage state at any time within a clocking signal period (i.e., between time T1 and T2). The delayed disable/enable signal will always be delayed at least one half clocking cycle from the disable/enable signal transition (i.e., delayed to time T3). Regardless of whether disable/enable signal transitions early at T1, late at T2, or any time therebetween, delayed disable/enable signal will always transition at least one half a clocking cycle and at most one and one half clocking cycle thereafter. By delaying the disable/enable signal by at least one half the clocking cycle, clocking disable/enable signal will transition to its steady state or disabled value in sync with the clocking signal. Specifically, clocking disable/enable signal will transition at time T3 from a high voltage state to a low voltage state corresponding with the high-to-low transition of the clocking signal and coincident delayed disable/enable signal high-to-low transition. The circuit operation of Fig. 2, shown in Fig. 4, also provides synchronous enable. At any time T4 through T5, disable/enable signal can transition back to a high state causing the delayed disable/enable signal to transition at least one half a clocking cycle thereafter. When delayed disable/enable signal transitions, coincident with clocking signal transition (i.e., during time T6), the clocking disable/enable signal will resume clocking state, albeit at a low pulse level, synchronized with the clocking signal. Thus, beginning at time T6, clocking disable/enable signal is substantially equal to the clocking signal. Referring to Fig. 5, operational conditions of various signals within the embodiment of Fig. 3 is shown. Specifically, disable/enable signal can toggle low at a time between T1 and T2, and thereafter toggle high at a time between T4 and T5. Delayed disable/enable signal is activated at time T3, at least one half a clocking cycle and at most one and one half clocking cycle after the disable/enable signal is activated. Once activated, delayed disable/enable signal transitions coincident with the clocking transition causing clocking disable/enable signal to transition to a steady state high value at time T3. After the delayed disable/enable signal is no longer activated at time T6, the clocking disable/enable signal transitions back to a clocking state, initially high. It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to be capable of applications with numerous types of synchronized digital and analog circuits. The disable and enable circuit hereof provides and maintains clocking synchronization to the connected digital and/or analog circuits throughout the disable and re-enable periods. It is also to be understood that the form of the invention shown and described is to be taken as presently preferred embodiments. Various modifications and changes may be made without departing from the scope of the invention as set forth in the claims. An exemplary modification might be one which uses more than three latching stages. Moreover, logic gate 32 can include other types of logic functions beyond a nand gate, nor gate or combinations thereof. Provided the clocking disable/enable signal is synchronized with the clocking circuit during non-disable periods and transitions to a steady state in sync with clocking signal transitions during disable periods, any modifications to the multiple latching stages or logic gate can be performed and still remain within the scope of the present invention as defined by the following claims.

Claims: A clocking disable and enable circuit (20) comprising a multiple stage latching circuit (22) having a latching input and a latching output, and a logic gate (32) coupled to the output of the latching circuit, the logic gate having two inputs and a single output, and the latching circuit receiving a clocking signal (CLK) and further receiving a clock disable/enable signal (D/E) at its latching input to provide a delayed disable/enable signal (D.D/E) at its latching output in response to the clocking signal (CLK), one input of the logic gate (32) being coupled to receive the delayed disable/enable signal (D.D/E) and other logic input being coupled to receive the clocking signal (CLK), the logic gate thereby producing a logic output signal synchronized with the clocking signal, characterized in that each transition of the disable/enable signal (D/E) is propagated through the latching circuit to produce a corresponding subsequent transition of the delayed disable/enable signal (D.D/E), such that each rising transition of the delayed disable/enable signal corresponds to a prior rising edge of the disable/enable signal, and each falling transition of the delayed disable/enable signal corresponds to a prior falling edge of the disable/enable signal, wherein the latching circuit (22) includes at least three stages, so arranged that a second stage of the three stages is configured to respond to an inverted clocking signal with respect to a first and third stage of the three stages, such that an oppositely-directed transition of the clocking signal is needed for disable/enable signal transmission through the second stage as compared to the first and third stages, and such that the clock disable/enable signal (D/E) is delayed by a variable period of at least one half cycle of the clocking signal. The clocking circuit as claimed in claim 1, wherein the three latching stages of the latching circuits are connected in series, and each stage includes a selectively conductive path (24) connected in series with a latch. The clocking circuit as claimed in claim 2, wherein the selectively conductive path is regulated upon receiving the clocking signal. The clocking circuit as claimed in any one of the claims 1-3, wherein the logic gate (32) comprises a NAND gate and the transition of the clocking signal is from a high voltage level to a low voltage level. The clocking circuit as claimed in any one of the claims 1-3, wherein the logic gate (32) comprises a NOR gate and the transition of the clocking signal is from a low voltage level to high voltage level. The clocking circuit as recited in any one of the preceding claims, wherein the steady state output signal continues for a duration equal to a set period of multiple half cycles of the clocking signal. The clocking circuit as recited in any one of the preceding claims, wherein the steady state output signal occurs completely after a low-to-high voltage transition of one cycle of the clocking signal has occurred. The clocking circuit as recited in any one of the claims 1-6, wherein said steady state output signal begins completely after a high-to-low voltage transition of one cycle of the clocking signal has occurred. The use of the clocking circuit according to any one of the preceding claims in a carrier signal frequency tracking system (10), the system further comprising: an oscillator (18); and a frequency shift detector circuit having two detector inputs and a detector output, wherein the detector output varies in voltage magnitude depending upon the frequency difference between a carrier signal place on one detector input and said logic output signal placed on the other detector input. The use of the clocking circuit as recited in claim 9, wherein said oscillator includes an oscillator input for receiving a voltage level and an oscillator output for delivering said clocking signal of a varying frequency dependent upon said voltage level. The use of the clocking circuit as recited in claim 9, wherein said oscillator is a voltage controlled oscillator, and said frequency shift detector includes a phase detector.

Inventors: LOWE WILLIAM M, LOWE, WILLIAM M.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1994
Main classification: H03K5
IPC codes: H03K17, H03K3, H03K19, H03K5