High density dynamic bus

Abstract: An improved signal line routing scheme includes a plurality of dynamic signal lines disposed in parallel to each other, and a plurality of static signal lines disposed in parallel to each other and also disposed in parallel with the plurality of dynamic signal lines, wherein at least one of the plurality of static signal lines is disposed immediately adjacent to each one of the plurality of dynamic signal lines.

Description: The present invention relates to data transmission schemes, and, more particularly, to data transmission schemes including mechanisms for reducing unwanted coupling between signal paths. For any data transmission event, a received signal consists of the transmitted signal, modified by various distortions imposed by the transmission signal, plus additional unwanted signals that are inserted somewhere between transmission and reception. The latter, undesired signals are referred to as noise. It is noise that is the major limiting factor in communications system performance. Noise may generally be divided into four categories: thermal noise, intermodulation noise, impulse noise and crosstalk. Each of these four categories of noise is discussed in an individual paragraph immediately below. Thermal noise is noise caused by thermal agitation of electrons in a conductor. It is present in all electronic devices and transmission media and is a function of temperature. Thermal noise is uniformly distributed across the frequency spectrum and hence is often referred to as white noise. Thermal noise cannot be eliminated and therefore places an upper bound on communications system performance. Intermodulation noise can arise when signals at different frequencies share the same transmission medium. The effect of intermodulation noise is to produce signals at a frequency which is the sum or difference of the two original frequencies or multiples of those frequencies. Intermodulation noise is produced when there is some nonlinearity in the transmitter, receiver, or intervening transmission system. Nonlinearity can be caused by component malfunction or by use of excessive signal strength. Impulse noise is unpredictable and noncontinuous, consisting of irregular pulses or noise spikes of short duration and of relatively high amplitude. It may be generated from a variety of causes, including external electromagnetic disturbances, such as lightening, and faults and flaws in the communications system. Crosstalk, the fourth major category of noise, is an unwanted coupling between signal paths. There is inevitably a certain amount of parasitic capacitance between long lines routed in parallel. This capacitance can cause coupling problems; specifically, a line can unintentionally change polarity if adjacent lines change, resulting in incorrect data being transferred. Historically, crosstalk has been generally considered to be a problem of the same order of magnitude as, or less than, thermal noise. Crosstalk has also been considered to be much less of a problem than impulse noise, which has been generally regarded to be the primary source of error in digital data communication. However, as greater densities and smaller geometries have become increasingly sought and obtained in integrated circuit (IC) manufacture, crosstalk has become a more significant problem. Current trends in IC manufacture have caused parasitic capacitance increases following spacing decreases and line length increases. This has, in turn, exacerbated crosstalk in those circuits. An example of how crosstalk can arise may be helpful at this point. Supposing there are three dynamic lines -- DYNAMIC1, DYNAMIC2, and DYNAMIC3 -- that are precharged to one (1), and further supposing that the data being transferred on the lines is zero (0), one (1) and zero (0), respectively: the two zeros (0s) on DYNAMIC1 and DYNAMIC3 can cause the data on DYNAMIC2 to change from one (1) to (0) through coupling. Heretofore, those skilled in the art have attempted to reduce coupling problems by changing the ratios of the gates which receive the dynamic data, that is, by changing their threshold voltages. However this technique has made the gates slower and more susceptible to signal noise. This technique also often costs more die area. A second solution has been to increase spacing between bus lines. This definitely requires additional die area, which means larger dies must be used, and increases costs. Based upon the foregoing, those skilled in the art should understand and appreciate that it is a shortcoming and deficiency of the prior art that there has not yet been developed a data transmission routing scheme for small, dense circuits which does not suffer from coupling problems. There is disclosed in D1, Patent Abstracts of Japan 14(239), (E-930) an arrangement in which digital signal lines are separated by shielding lines which carry a shielding power supply which may be the power voltage, an earth voltage, or a stable voltage between which hardly fluctuates. The present invention provides an integrated circuit having dynamic signal lines such as bus lines and generally static signal lines such as bus control lines, comprising: a plurality of dynamic signal lines disposed in parallel to each other; and a plurality of generally static signal lines disposed in parallel to each other and also disposed in parallel with said plurality of dynamic signal lines, wherein at least one of said plurality of generally static signal lines is disposed immediately adjacent to each one of said plurality of dynamic signal lines, characterised by means for ensuring that an immediately adjacent dynamic signal line and generally static signal line do not change signal level simultaneously. The present invention also provides a method for routing signal lines in an integrated circuit having dynamic signal lines such as bus lines and generally static signal lines such as bus control lines, said method comprising the steps of: laying a plurality of dynamic signal lines parallel to each other; and laying a plurality of generally static signal lines in parallel to each other and also in parallel with the plurality of dynamic signal lines, and further so that at least one of said plurality of generally static signal lines is disposed immediately adjacent to each one of said plurality of dynamic signal lines, characterised by providing means for ensuring that an immediately adjacent dynamic signal line and generally static signal line do not change signal level simultaneously. We will describe, therefore, an arrangement to reduce or eliminate crosstalk between long adjacent dynamic lines in a high density layout. We will describe a scheme and method for eliminating crosstalk between long adjacent dynamic lines, which scheme and method does not require increasing the die area. We will describe an inexpensively implemented scheme to reduce problems caused by parasitic capacitance in high density layouts. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, advantages, and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings in which: FIG. 1 is a cross sectional view of a signal line routing scheme according to the teachings of the present invention. FIG. 2 (which consists of FIGS. 2A, 2B, and 2C) depicts a dynamic line A, a static line B, and a dynamic line C; FIG. 3 is a detailed diagram of a circuit used to obtain parameters that can be used in embodiments of the present invention; FIG. 4 depicts simulated failure in the circuit of FIG. 3 because of insufficient distances between dynamic lines; and FIG. 5 depicts simulated proper action in the circuit of FIG. 3 because the dynamic lines therein were spaced apart sufficiently. DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings wherein like reference numerals designate the same or similar elements throughout the several views, and further wherein the various elements shown are not necessarily drawn to scale. FIG. 1 depicts a signal line routing scheme according to the teachings of the present invention. Three distinct signal lines are depicted in FIG. 1. Those signal lines are dynamic signal line A 10, static signal line B 12, and dynamic signal line C 14. Also depicted in FIG. 1 are capacitances among the various lines, i.e., capacitance C m1 between dynamic line 10 and static line 12, capacitance C m2 between static line 12 and dynamic line 14, and capacitance C c between dynamic line 10 and dynamic line 14. Capacitances between the various lines and an underlying substrate 16 are also depicted in FIG. 1, i.e., capacitance C g1 + C f1 between dynamic line 10 and the substrate 16, capacitance C g2 + C f2 between static line 12 and the substrate 16, and capacitance C g3 + C f3 between dynamic line 14 and the substrate 16. Additionally, FIG. 1 provides some indication of appropriate spacings in embodiments of the present invention. As previously mentioned, it is generally desired to keep the capacitance C c as low as possible. Capacitance C c is, as indicated in FIG. 1, directly proportional to 1/t, where t is equal to the minimum width of the metal plus two times the minimum metal-to-metal spacing. With that it mind, it may be noted in FIG. 1 that the inventors of the present invention have found about 1.05 microns to be a suitable distance to put between a dynamic line and a static line (i.e., lines 10 and 12 in FIG. 1). In somewhat more detail, as those skilled in the art are generally aware, dynamic signal lines are precharged high during a first phase, and then evaluated during a second, subsequent phase. Multiple sources or gates are generally present and able to pull down the dynamic signal. If none of the sources are on, the dynamic signal should remain high. This is when parasitic coupling can cause problems. When a given dynamic signal line that should remain high is surrounded by two dynamic lines being pulled low, charge may be pulled out of the surrounded dynamic line. This inherently causes current to drain out of the surrounded dynamic line, possibly even to the point that it can be effectively, and improperly, pulled low. In general, the scheme proposed herein and depicted in FIG. 1 is based upon the concept of alternating dynamic signal lines with static signal lines. As those skilled in the art are aware, there are often sufficient static signal lines routed along a dynamic bus to control the driving and latching of the bus. According to the teachings of the present invention, any static line may be disposed so as to separate one dynamic line from another as long as it does not change at the same time as the dynamic bus. If a static signal line does change at the same time as the dynamic bus, a slight analog delay can be added to either the static signal or the bus so they change at different times. Given a plurality of static and dynamic signals to route in parallel, a preferred embodiment of the present invention would be DYNAMIC1, STATIC1, DYNAMIC2, STATIC2, DYNAMIC3, STATIC3. If there are not enough static signals, another option would be to route DYNAMIC1, DYNAMIC2, STATIC1, DYNAMIC3, DYNAMIC4, STATIC2. This option, which effectively ensures that no dynamic line is immediately adjacent in the same plane to two other dynamic lines, could often be sufficient to reduce the parasitic capacitance enough to eliminate any crosstalk problem. Referring now to FIG. 2 there is shown an alternative, and more detailed view, of the lines 10, 12, 14 introduced in FIG. 1. More specifically, FIG. 2A is a detailed view of the dynamic signal line 10. The upper portion of FIG. 2B is a detailed view of a static signal line 12 that changes at a different time from the adjacent dynamic signal lines 10, 14. The lower portion of FIG. 2B is a detailed view of a static signal line 12 that changes at the same time as one or both of the adjacent static signal lines 10, 12; therefore, an analog delay (represented by a conventional delay element 18) is included in that line 12. Finally, FIG. 2C, like FIG. 2A, is a detailed view of a dynamic signal line (but, line 14 rather than line 10). Although the structure and operation of the dynamic lines 10 and 14 depicted in FIGs 2A and 2C should be well understood by those skilled in the art, a few additional observations may appropriately made here about the static lines 12 shown in FIG. 2B. In generally, static lines are always hot driven by some source. However, static lines can change at different times. For example, the uppermost depicted static line in FIG. 2B is a type of static line that changes during a precharge stage. This type of static line is a preferred type in embodiments of the present invention. The bottommost depicted static line in FIG. 2B is a type of static line that changes during the evaluation stage. This type of static line can change at the same time as an adjacent dynamic line; accordingly, element 18 is included in the line to delay any change in the static signal line to a time after any change in an adjacent dynamic signal line. Referring now to FIG. 3, there is shown a simulated circuit illustrating a preferred arrangement of the present invention. In FIG. 3, lines XICSP1, XICSP2, and XICSP3 are dynamic lines. Line XICSP0 is a dynamic line running below and in parallel to dynamic lines XICSP1, XICSP2, and XICSP3. FIGs. 4 and 5 are related to FIG. 3 insofar as they depict voltage changes over time in the circuit. FIG. 5 uses spacing of 3.5 microns between dynamic lines; FIG. 4 depicts conventional spacing of about 1.5 microns. In both FIGs. 4 and 5 the voltage of interest is the voltage level of a dynamic line surrounded by two other dynamic lines. FIG. 4 effectively simulates a situation where three dynamic lines are immediately adjacent. With larger distances involved, FIG. 5 effectively simulates static lines disposed between a central dynamic line and two outer dynamic lines. FIG. 4 shows that parasitic capacitance can cause XICSP to go low (at the point generally designated by reference numeral 20); FIG. 5, on the other hand, shows that although parasitic capacitance pulls down on XICSP, it does not go low. This "success" is because of the greater distances between dynamic lines, which greater distances can be readily achieved using the teachings of the present invention. Although the discussion above has focused on lines routed in the same layer (i.e., on a single plane parallel to a substrate surface), those skilled in the art should understand and appreciate that the instant teachings can be used to solve crosstalk problems arising because of capacitance between or among lines in multiple layers. In fact, the inventors of the present invention envision that as the number of metal layers in processes increase, which seems to be a present trend, crosstalk arising because of capacitance between or among lines in multiple layers will become more of a problem. Obviously, numerous modifications and variations are possible in view of the teachings above. Accordingly, within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described hereinabove.

Claims: An integrated circuit having dynamic signal lines such as bus lines and generally static signal lines such as bus control lines, comprising: a plurality of dynamic signal lines (10,14) disposed in parallel to each other; and a plurality of generally static signal lines (12) disposed in parallel to each other and also disposed in parallel with said plurality of dynamic signal lines, wherein at least one of said plurality of generally static signal lines is disposed immediately adjacent to each one of said plurality of dynamic signal lines, characterised by means (18) for ensuring that an immediately adjacent dynamic signal line and generally static signal line do not change signal level simultaneously. An apparatus as claimed in claim 1, wherein said means for ensuring that an immediately adjacent dynamic signal line and generally static signal line do not change signal level simultaneously comprises an analog delay element disposed on said generally static signal line. An apparatus as claimed in claim 1, wherein said means for ensuring an immediately adjacent dynamic signal line and a generally static signal line do not change signal level simultaneously comprises an analog delay element disposed on Said dynamic signal line. An apparatus as claimed in any of claims 1 to 3, wherein at least two of said plurality of generally static signal lines are disposed immediately adjacent to each one of said plurality of dynamic signal lines. A method for routing signal lines in an integrated circuit having dynamic signal lines such as bus lines and generally static signal lines such as bus control lines, said method comprising the steps of: laying a plurality of dynamic signal lines (10,14) parallel to each other; and laying a plurality of generally static signal lines (12) in parallel to each other and also in parallel with the plurality of dynamic signal lines, and further so that at least one of said plurality of generally static signal lines is disposed immediately adjacent to each one of said plurality of dynamic signal lines, characterised by providing means (18) for ensuring that an immediately adjacent dynamic signal line and generally static signal line do not change signal level simultaneously. The method as claimed in claim 5, further comprising the step of delaying the generally static signal so that said generally static signal does not change at the same time said dynamic signal changes. The method as claimed in claim 5, further comprising the step of delaying the dynamic signal so that said dynamic signal does not change at the same time as said generally static signal changes. A method as claimed in claims 5, 6 or 7, wherein said step of laying a plurality of generally static signal lines comprises the step of laying at least two of said plurality of signal lines immediately adjacent to each one of said plurality of dynamic signal lines.

Inventors: KROMER STEPHEN C, PETERS JOE, TAN TEIK-CHUNG, KROMER, STEPHEN C., PETERS, JOE, TAN, TEIK-CHUNG
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1994
Main classification: H01L23
IPC codes: H03K19, H01L21, H01L23, H04B3, H01L27