Arc detection using current variation

Abstract: In an electric circuit supplying AC line current to a load (30, 31) from an AC source (26) of given frequency providing repetitive cycles, arc detection is provided by sensing cycle to cycle changes in the AC line current. The AC line current is sampled with a harmonic notch filter (72) at a plurality of n phases Θ₁ through Θ n during each of a plurality of m cycles of the AC source (26), to provide a plurality of currents I n,m , where n is the phase and m is the cycle. The differences (I n,m )-(I n,m-x ), where x is a designated number of cycles, provide a plurality of current difference signals. The absolute values of these current difference signals ID are accumulated in a synchronous summer (94) over the m cycles. An arc indicative signal is generated in response to given conditions and given combinations of conditions (116) of the cumulative absolute current difference signals ID. Cycle to cycle changes in AC line voltage are also sensed with a harmonic notch filter (146), and the arc indicative signal is disarmed in response to a given voltage condition. In further embodiments, subcycle changes are sensed.

Description: BACKGROUND AND SUMMARY The invention relates to protection techniques for electric circuits, and more particularly to the detection of arcs which are too small to trip a circuit breaker or the like. The invention arose during development efforts in electric circuit protection techniques, including residential, commercial and industrial applications having overcurrent protection and/or ground fault interrupter (GFI) systems for preventing property damage and/or personal injury. Overcurrent protection systems typically include a load center or panelboard receiving electrical power from the utility company transformer, and routing the electrical power through a main circuit breaker or fuse and then through branch circuit breakers or fuses to designated branch circuits, each supplying current to one or more electrical loads. The circuit breakers or fuses are designed to interrupt the electrical current if it is excessive or outside the design limits of the conductors and loads or demonstrates a current imbalance, to reduce the risk of injury and damage, including fires. Circuit breakers are more commonly preferred because they are reusable simply by resetting same. A circuit breaker has a thermal/magnetic trip characteristic. The thermal characteristic is operative in response to overload current of extended duration which heats a bimetal member, causing movement of the latter, which in turn releases a latch to trip open a set of contacts. For example, the thermal characteristic would respond to 30 amps being drawn in a 15 amp circuit. The magnetic characteristic is operative in response to a sudden high magnitude current overload condition, and uses the magnetic field generated in a magnetic core to attract an armature, which movement releases the latch to open the contacts. As an example, the magnetic type actuation occurs in response to a short circuit wherein the hot line conductor becomes directly connected with ground or neutral, bypassing the load. A further type of circuit protection is provided by a ground fault interrupter, which trips the breaker to an open circuit condition in response to an imbalance of currents between the line and neutral conductors of a given circuit. This is particularly desirable in the event that a person is in the path to ground. The present invention addresses a further type of electric circuit protection and monitoring, namely the detection of arcing in the electric circuit. The arcs to be monitored include not only a discharge of electricity through a gas or across an insulating medium, but also high impedance faults or other intended or unintended circuit paths which do not have sufficient energy or current flow to trip a breaker, but nevertheless can generate damaging heat or other undesirable effects. An arc may occur in series or parallel with the load, and may have numerous causes, for example loose connections, worn or aged wiring or insulation, prior mechanical or electrical stressing such as caused by crimping or twisting, overuse, prior lightning strikes, etc. The current in such arcs may be below the thermal and magnetic trip settings of the breaker or a fuse, and/or may not present an imbalance of currents between the line and neutral conductors, and hence such arcs can go undetected. A particular hazard due to arcing is hot spots along electrical wiring in a residence or the like, which is a fire risk. This wiring can include wall conductors, junction boxes, receptacles, switches, plugs, cords such as extension cords, and the load devices themselves. The present invention provides effective arc detection. The invention is particularly well suited to discriminating between potentially damaging arcs and either non-arcing events or momentary short duration switching events, which is desirable in order to prevent nuisance tripping. The invention does not trip in response to all arcs, nor all seemingly arc-like events, but rather relies upon statistical probabilities to provide an arc indicative signal in response to an event which has a strong likelihood of being an arc. To attempt to respond to all arcs would involve an unacceptably high occurrence of nuisance tripping, which is undesirable because it may shut down machinery or safety equipment which should remain running, except for those events actually having a high statistical probability of being an arc. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic illustration of an electrical current distribution circuit, and is taken from Fig. 1 of U.S. Patent 5,185,685, incorporated herein by reference. Fig. 2 is a schematic illustration of a portion of the circuit of Fig. 1, and is similar to Fig. 2 of the noted incorporated '685 patent. Fig. 3 is a functional block diagram of an arc detector in accordance with the invention. Fig. 4 is a waveform diagram showing AC line current for one particular example. Fig. 5 is a waveform diagram illustrating operation of a portion of the circuit of Fig. 3. Fig. 6 is a waveform diagram illustrating operation of a portion of the circuit of Fig. 3. Figs. 7-11 are waveform diagrams illustrating cumulative operation of a portion of the circuit of Fig. 3. Fig. 12 is a functional circuit block diagram of the arc detector of Fig. 3. Figs. 13 and 14 show a reference sine wave with points related in phase labelled. DETAILED DESCRIPTION Fig. 1 shows an electrical current distribution circuit 20 including a load center 22 having a line side 24 for receiving electrical power from a voltage source 26 of predetermined excitation frequency, and a load side 28 distributing the electrical power to loads such as 30 and/or 31. The voltage source can be a power utility company transformer supplying electrical power on first and second line conductors at 240 volts, and a neutral conductor at 120 volts relative to the first and second line conductors, all at, e.g., 60 Hz. The invention is not limited to such example, and can be applied to any AC system operating at any voltage and frequency, including 480 and 660 volts, and 50, 60 and 400 Hz. The load center has a main electro-responsive circuit breaker 32 receiving the electrical power from transformer 26 and distributing the electrical power to branch circuit breakers 34, 36, etc. The branch circuit breakers in turn supply the electrical power on branch circuits such as 38 to electrical outlets 40, 42, etc. into which load 30 is plugged at plug 44, or branch circuit 38 which is wired directly to load 31. Branch circuit 38 includes a line conductor 46, Fig. 2, and a neutral conductor 48 supplying the electrical power to load 30. Branch circuit 38 may also include a ground conductor 50. Circuit breaker 34 includes an overload trip mechanism 52 having a thermal/magnetic characteristic tripping breaker contacts 54 to an open circuit condition in response to a given circuit overload condition, to disconnect load 30 from the voltage source 26, as is known in the prior art. It is also known in the prior art to provide circuit breaker 34 with ground fault interrupter circuitry 56 responding to a line or neutral to ground fault to gate SCR 58 into conduction to in turn energize coil 60 which opens breaker contacts 54. An example of a GFI circuit is shown in U.S. Patent Re30,678, incorporated herein by reference. The present invention, provides an arc detector 64 and arc detection method for the electric circuit supplying AC line current to load 30 from AC source 26 of given frequency providing repetitive cycles, e.g. 60 Hz providing repetitive cycles each having a period of 16.67 milliseconds. Arc detector 64 senses cycle to cycle changes in AC line current and generates difference signals representing such changes, to be described, and responds to given conditions of the difference signals to generate an arc indicative trip signal on line 67 providing a gating signal supplied to the gate of SCR 58 to gate the SCR into conduction and energize coil 60 to open breaker contacts 54. The outputs of circuits 56 and 64 are connected at a common node 65 to the gate of SCR 58. If the circuit breaker does not have GFI circuit 56, the SCR 58 and coil 60 are added. Fig. 3 shows arc detector 64. AC line current is shown as current waveform 70, Figs. 3 and 4, which is the AC current supplied on line 46, Fig. 2, from AC source 26 to-load 30. The current is preferably sensed with a current transformer, for example as shown at 68 in the incorporated '685 patent, though the current may be sensed with other current sensors. The sensed AC line current is sampled with a harmonic notch filter 72 at a plurality of sampling points or phases n during a plurality of cycles m, with the relative phase of the respective sampling point being the same cycle to cycle. For example, referring to Fig. 4, the AC line current is sampled at a phase Θ 1,1 during a first cycle of the AC source to provide a first sampled current I 1,1 . The first subscript is the phase or sampling point and the second subscript is the cycle; hence, I 1,1 is the current at the first phase or sampling point in the first cycle. The AC line current is sampled at a first phase or sampling point Θ 1,2 during a second cycle of the AC source to provide a sampled current I 1,2 , which is the current at the first phase or sampling point in the second cycle. The AC line current is sampled at the same relative phase during each of the first and second cycles, i.e. Θ 1,1 equals Θ 1,2 . Stated another way, Θ 1,1 and Θ 1,2 are spaced or separated by one cycle, or 360°, of the AC source, or an integral multiple thereof. In the case of a 60 Hz AC source, Θ 1,1 and Θ 1,2 are spaced by 1/60 of a second, i.e. 16.67 milliseconds, or an integral multiple thereof. The noted difference signals are provided by subtracting I 1,1 from I 1,2 . The AC line current is sampled with the harmonic notch filter at a plurality of phases Θ 1,1 through Θ n,1 during a first cycle of the AC source to provide a plurality of sampled currents I 1,1 through I n,1 for the first cycle. The AC line current is sampled with the harmonic notch filter at a plurality of phases Θ 1,2 through Θ n,2 during a second cycle of the AC source to provide a plurality of sampled currents I 1,2 through I n,2 for the second cycle. Θ 1,1 through Θ n,1 equals Θ 1,2 through Θ n,2 , respectively, i.e. the first sampling point in the first cycle occurs at the same relative phase as the first sampling point in the second cycle, the second sampling point in the first cycle occurs at the same relative phase as the second sampling point in the second cycle, and so on. The sampled currents I 1,1 through I n,1 are subtracted point for point from the sampled currents I 1,2 through I n,2 , respectively, by the harmonic notch filter, to provide the noted difference signals. It is preferred that the first, second and so on cycles be consecutive. Harmonic notch filter 72 performs the noted point for point subtraction of I 1,1 through I n,1 from I 1,2 through I n,2 , respectively, to provide harmonic notch filter current difference signals HNFI, the absolute value of which provides current difference signals ID. For example, sampled current I 1,1 , which was the current sampled at the first sampling point in the first cycle, i.e. at Θ 1,1 , is subtracted from sampled current I 1,2 , which is the current sampled at the first sampling point in the second cycle, i.e. at Θ 1,2 , to provide an HNFI difference signal, the absolute value of which provides a current difference signal ID 1,2-1 , i.e. the absolute value of the difference in sampled current between the first and second cycles at the first phase or sampling point. Likewise, the AC line current is sampled at phase Θ 1,3 during a third cycle of the AC source to provide a sampled current I 1,3 , where Θ 1,2 equals Θ 1,3 . I 1,2 , which is the sampled current at the first sampling point in the second cycle, is subtracted from I 1,3 , which is the sampled current at the first sampling point in the third cycle, to provide an HNFI difference signal, the absolute value of which provides a current difference signal ID 1,3-2 , which is the absolute value of the difference between the sampled current at the first sampling phase point in the third cycle and the sampled current at the first sampling phase point in the second cycle. Fig. 5 shows the current for the present cycle in solid line, and the current for the immediately preceding cycle in dashed line. Thus, in the first cycle, the first cycle current I 1 is shown in solid line, and the current from the previous or initial cycle is shown at I 0 in dashed line. Likewise, in the second cycle, the second cycle current I 2 is shown in solid line, and the first cycle current I 1 is shown in dashed line, and so on for cycles 3 through 5. In the particular implementation shown in Fig. 5, the point for point subtraction of I 0 from I 1 during the first cycle yields the HNFI difference signals shown in span 74 in Fig. 6. In the second cycle in Fig. 5, the point for point subtraction of the previous cycle current I 1 from the present cycle current I 2 yields the HNFI difference signals shown in span 76 in Fig. 6. In the third cycle in Fig. 5, the point for point subtraction of I 2 from I 3 yields the HNFI difference signals shown in span 78 in Fig. 6. In the fourth cycle in Fig. 5, the point for point subtraction of I 3 from I 4 yields the HNFI difference signals shown in span 80 in Fig. 6. In the fifth cycle in Fig. 5, the point for point subtraction of I 4 from I 5 yields the HNFI difference signals shown in span 82 in Fig. 6. Harmonic notch filter 94 performs point for point subtraction of AC line currents to provide harmonic notch filter current difference signals HNFI, the absolute value of which provides current different signals ID at time t according to: ID ( t ) = | HNFI ( t )| = | I ( t )- I ( t - T )| Eq .1 where I(t) is the sampled current at time t, and I(t-T) is the sampled current one cycle earlier, i.e. at a time T seconds ago, where T is the period of the AC cycle, i.e. 16.67 milliseconds. Equation 1 defines the harmonic notch filter in the time domain. The absolute current difference signals ID are synchronously summed at synchronous summer 94, Fig. 3, to provide a sum S(t) according to: S ( t ) = ID ( t )+ ID ( t - T )+ ID ( t -2 T )+ ID ( t -3 T )+ ID ( t -4 T ) Eq .2 Referring to Fig. 6, the absolute of the difference signals over span 74 are added point for point with the absolute value of the difference signals over span 76 which are added point for point with the absolute value of the difference signals over span 78 which are added point for point with the absolute value of the difference signals over span 80 which are added point for point with the absolute value of the difference signals over span 82. In the example shown, five cycles of cumulative absolute value current difference signals ID are summed, yielding S 5 (t), i.e. the summation of the five ID signals. The accumulation of the ID signals is shown sequentially in Figs. 7-11. Fig. 7 shows the ID signals over span 74 after one cycle, yielding S 1 (t). Fig. 8 shows the accumulated ID signals over spans 74+76 after two cycles, yielding S 2 (t). Fig. 9 shows the accumulated ID signals over spans 74+76+78 after three cycles, yielding S 3 (t). Fig. 10 shows the accumulated ID signals over spans 74+76+78+80 after four cycles, yielding S 4 (t). Fig. 11 shows the accumulated ID signals over spans 74+76+78+80+82 after five cycles, yielding S 5 (t). The absolute value current difference signals ID are synchronously summed for each phase for five consecutive cycles, to provide the cumulative current difference signals shown in Fig. 11 at 83. If given conditions of cumulative current difference signals are met, related to features 84, 86, 88, 90, to be described, then an arc indicative trip signal is generated on line 67, to be described. In general, AC line current is sampled at a plurality of phases Θ 1 through Θ n during each of a plurality of m cycles. Harmonic notch filter 72 provides n cycle to cycle current difference signals ID, one for each of the phases Θ 1 through Θ n . Synchronous summer 94 sums m of the current difference signals at phase Θ 1 for cycles 1 through m to provide a first cumulative current difference signal. The summing is continued through the n th phase including summing m of the current difference signals at phase Θ n for cycles 1 through m to provide an n th cumulative current difference signal. In the present embodiment, n equals 1,341, i.e. during each cycle, there are 1,341 sampling points or phases. Also in the present embodiment, m equals 5, i.e. synchronous summer 94 sums the current difference signals ID over 5 cycles, to yield S 5 (t), as defined in Equation 2, and shown in Fig. 11. The cycle to cycle current difference signals are preferably calculated by taking the difference between consecutive cycles, though they need not be. The first through n th cumulative current difference signals provide the trace shown over span 83 in Fig. 11, m=5. Condition checker 116 of Fig. 3 responds to given conditions, such as 84, 86, 88, 90, Fig. 11, of the cumulative current difference signals to generate the arc indicative trip signal, to be described. Harmonic notch filter 72 samples AC line current at the noted plurality of n phases Θ 1 through Θ n during each of the noted plurality of m cycles of the AC source, where Θ 1,1 equals Θ 1,2 equals...Θ 1,m , and where Θ 2,1 equals Θ 2,2 equals...Θ 2,m ,...,and where Θ n,1 equals Θ n,2 equals...Θ n,m for each of the m cycles, to provide a plurality of currents I n,m , where n is the phase and m is the cycle. The harmonic notch filter performs equation 1 to determine the difference (I n,m )-(I n,m-x ), where x is a designated number of cycles or periods, to provide a plurality of current difference signals ID. In the preferred embodiment, x equals 1, to provide consecutive cycle current difference signals, though cycle to cycle current variation can be determined for cycles which are not consecutive. Synchronous summer 94 accumulates the current difference signals ID over a given number of cycles, preferably 5, i.e. m equals 5, though other values of m may be used. Synchronous summer 94 performs equation 2, adding ID 1,1-(1-x) + ID 1,2-(2-x) +...+ ID 1,m-(m-x) to provide a first cumulative current difference signal ID 1 at phase Θ 1 , and adding ID 2,1-(1-x) + ID 2,2-(2-x) +...+ ID 2,m-(m-x) to provide a second cumulative current difference signal ID 2 at phase Θ 2 , and continuing the adding through the n th phase including adding ID n,1-(1-x) + ID n,2-(2-x) +...+ ID n,m(m-x) to provide an n th cumulative current difference signal ID n at phase Θ n . As noted above in the preferred embodiment, n equals 1,341, m equals 5, and x equals 1. As noted above, condition checker 116 responds to given conditions of the accumulated current difference signals ID from synchronous summer 94, S(t), to generate an arc indicative trip signal. In general, such sum is S m (t), and in the preferred embodiment m=5. Also in the preferred embodiment, S 5 (t) is evaluated once every five cycles. In an alternate embodiment, S 5 (t), or some other S m (t), may be evaluated every cycle on a sliding window basis. A first of the noted conditions for S(t), as checked by condition checker 116, Fig. 3, is that the average of the cumulative current difference signals ID 1 through ID n exceeds a given threshold current, which in the preferred embodiment is 0.4 amp for m=5, i.e. for S 5 (t). The arc indicative trip signal is generated only if the average exceeds the given threshold current. If the average of accumulated ID 1 through ID n , i.e. S 5 (t), exceeds 0.4 amp, then a high input is provided on line 118 to AND gate 120. Referring to Fig. 11, for m=5, if the average value of the current trace across span 83 exceeds 0.4 amp, then a high input is provided on line 118 to AND gate 120. A second of the noted conditions for S(t), as checked by condition checker 116, Fig. 3, is that the peak to average ratio of the cumulative current difference signals ID 1 through ID n exceeds a given threshold ratio, where the peak is the maximum value of S(t), and the average is the average value of S(t). The arc indicative trip signal is generated only if the peak to average ratio exceeds the noted given threshold ratio. In the preferred embodiment, for m=5, the given threshold ratio is 4. If the peak to average ratio of the cumulative current difference signals ID 1 through ID n exceeds 4, then a high input is provided on line 122 to AND gate 120. Referring to Fig. 11, for S 5 (t), the peak is shown at 86. A third of the noted conditions for S(t), as checked by condition checker 116, Fig. 3, is that there be at least two quiet zones per cycle, each quiet zone being of a minimum time length, where a quiet zone is a portion of a cycle wherein none of the respective cumulative current difference signals ID therein rise above a given current activity threshold. For example, in Fig. 11, there are two quiet zones 88 and 90. During these quiet zones, S(t) stays below a given current activity threshold. The arc indicative trip signal is generated only if there are at least two quiet zones per cycle. The relative phase of point 89a in the AC waveform is the same as the relative phase of point 89b, such that zone 90 wraps upon itself. In the preferred embodiment, the minimum time length is the same for each of the quiet zones, and is 1.56 milliseconds. The given current activity threshold is 1.5 times the average of the cumulative current difference signals ID 1 through ID n , i.e. 1.5 times the average value of S(t). For example in Fig. 11, the current activity at each of portions 88 and 90 is less than 1.5 times the average current value across span 83, and hence the noted third condition is satisfied, and a high input is provided on line 128 to AND gate 120. In the preferred embodiment, any non-quiet zone having a duration less than 0.311 milliseconds is ignored, to avoid high frequency anomalies. In other words, it is required that a quiet zone last longer than 0.311 milliseconds to be considered valid. If the current activity S(t) signal rises above the noted 1.5 threshold, such as at 84 or 86, but has a duration less than 0.311 milliseconds, then it is considered part of, and absorbed by, the quiet zone. A fourth of the noted conditions for S(t), as checked by condition checker 116, Fig. 3, is that there be no quiet zone longer than a given quiet time upper limit. The arc indicative trip signal is disabled if any quiet zone such as 88 or 90 lasts longer than the given quiet time upper limit. In the preferred embodiment, the given quiet time upper limit is 9.17 milliseconds. If any quiet zone lasts longer than 9.17 milliseconds, then a low input is provided on line 130 to AND gate 120. A fifth of the noted conditions for S(t), as checked by condition checker 116, Fig. 3, is that the output of synchronous summer 94 be zero for no longer than a given null time upper limit. The arc indicative trip signal is disabled if any zero output of the synchronous summer lasts longer than the given null time upper limit. In the preferred embodiment, the given null time upper limit is 1.24 milliseconds. If the output of synchronous summer 94 is zero for longer than 1.24 milliseconds, then a low input is provided on line 132 to AND gate 120. If each of the noted five conditions is satisfied, then each of the inputs 118, 122, 128, 130, 132 to AND gate 120 is high, and a high output signal is provided on line 138, which in turn enables generation of the arc indicative trip signal. The first condition is that the average of S(t) over span 83, Fig. 11, exceeds a given threshold current, to provide a high state on line 118. The second condition is that the peak to average ratio of S(t) exceeds a given threshold ratio, to provide a high state on line 122. The third condition is there be at least two quiet zones per cycle, each of a minimum time length, to provide a high state on line 128. The fourth condition is that there be no quiet zone longer than a given quiet time upper limit, to provide a high state on line 130. If a quiet zone lasts longer than the given quiet time upper limit, then a low state is provided on line 130, which in turn disables AND gate 120, to in turn disable the arc indicative trip signal. The fifth condition is that the output of synchronous summer 94 providing S(t) be zero for no longer than a given null time upper limit, to provide a high state on line 136. If the synchronous summer output S(t) is zero for longer than the given null time upper limit, then a low state is provided on line 132, which in turn disables AND gate 120, to in turn disable the arc indicative trip signal. The purpose of the noted first condition requiring the average of the cumulative current difference signals, S(t), to exceed a given threshold current such as 0.4 amp is to ensure that there is some minimum activity above noise level. This condition also reduces nuisance tripping wherein a non-arc transient may cause a thin spike in Fig. 11, much thinner than spikes 84 or 86. In the case of a thin spike in Fig. 11, the average across the entire cycle in Fig. 11 including the thin spike may not rise above 0.4 amp. Thus, if a peak or spike in Fig. 11 does not have sufficient width or thickness, the average across the cycle does not rise above the given threshold current, and hence the test is failed, and thus a low state is provided on line 118, Fig. 3. In this manner, thin-spike transients or other operations, such as phase controlled loads operating at a constant duty cycle, are ignored, to reduce nuisance tripping. The purpose of the noted second condition requiring the peak to average ratio of the cumulative current difference signals, S(t), to exceed a given threshold ratio is to ensure that the spikes such as 84 and 86 in Fig. 11 are not too wide. A spike in Fig. 11 which is too wide, i.e. lasts too long, is typically not caused by an arcing event, but rather is indicative of asynchronous activity such as a start-up transient. The wider the spike in Fig. 11, the greater is the average across the cycle of the cumulative current difference signals, and hence the peak to average ratio does not exceed the noted given threshold, e.g. 4, thus failing such test and providing a low state on line 122, Fig. 3. The combination of the noted first and second conditions provide arc discrimination by ensuring that an arc indicative peak in Fig. 11 has some minimum width, and height, but is not too wide. It is this intermediate width and activity which distinguishes an arcing event from other events. The purpose of the noted third condition requiring at least two quiet zones per cycle, such as shown at 88 and 90 in Fig. 11, is to ensure that there are two spikes or pulses such as 84 and 86 per cycle. A characteristic of an arc is that it typically fires or occurs on both the positive and negative half cycles of the sinusoidal AC source 26. Fig. 11 shows the absolute value of the cumulative current difference signals. If there were only one spike in Fig. 11, then the causal event occurred during only one of the half cycles of AC source 26 and is typically not an arcing event. Without this third condition or test, many half-wave loads could cause nuisance tripping. The noted third condition enables the arc detector to ignore events causing a spike in only one of the half cycles of the AC source, and reduces nuisance tripping. The unpredictableness of an arc may occasionally result in non-firing thereof during a half cycle of perhaps one of the five accumulated cycles in Figs. 7-11. Even if an arc causes only a single spike in one or two of the five cycles, the remaining cycles can still build-up and accumulate a sufficient current difference signal in Fig. 11 to provide the second spike. It has been observed that arcs almost always occur during both half cycles of the AC source, and this characteristic is usefully employed by the noted third condition as another test to discriminate against non-arcing events. It has further been observed that many arcs have four peaks per cycle in Fig. 11. This is caused by a strike and recovery and a re-strike and recovery during each half cycle. The time length of the requisite quiet zones are selected to accommodate such re-strike, i.e. to allow four peaks across the cycle in Fig. 11. The purpose of the noted fourth condition requiring that no quiet zone last longer than a given quiet time upper limit is to ensure that the two peaks 84 and 86 in Fig. 11 are roughly 180° out of phase and have the noted intermediate thickness or width. The given quiet time upper limit is chosen to be 55% of the cycle, i.e. 9.17 milliseconds is 55% of 16.67 milliseconds. In accordance with this disable condition or test, if any quiet zone such as 88 or 90, Fig. 11, is longer than 55% of the cycle, then the causal event is ignored and deemed not an arc. Without this fourth condition or test, a number of nuisance trips are experienced on various loads, such as most variable speed drills which operate half-wave at low RPM. The noted fifth condition requiring that no zero output of the synchronous summer last longer than a given null time upper limit is included to enable a cost reduction for commercialability. If cost were no factor, a wide dynamic range would be desirable, which in turn requires a more expensive current sensor, more digital memory, and a larger available supply voltage range. If the extra cost is objectionable, then lower cost elements can be used, which may saturate at less than the peak of the incoming AC wave, which in turn reduces dynamic range. The input AC wave is thus clipped at such saturation point defined by the system resolution, which in turn artificially creates two null zones, at which the output of the synchronous summer is absolutely zero. The fifth condition limits such null zone to a given null time upper limit, e.g. 1.24 milliseconds, such that any longer lasting saturation is deemed a non-arcing event. From a technical standpoint, it is preferred that the noted fifth condition or test not be included. From a commercial cost-saving standpoint, it is preferred that the noted fifth condition or test be included. An arc occurs randomly and unpredictably. It is this randomness, wherein the arc and its relative time of occurrence is never quite the same cycle to cycle, that enables detection by arc detector 64. If there were no cycle to cycle changes of the current, there would be no current difference signal ID out of the harmonic notch filter 72. If randomness is the only arc characteristic desired to be checked, then the output of the harmonic notch filter itself provides arc detection indication. It is preferred that the above noted additional characteristics also be checked before providing an arc indicative trip signal. The synchronous summing and the condition checking are desirable in order to reduce nuisance tripping. Where nuisance tripping is not a problem, or where further cost savings are desired, the output of harmonic notch filter 72 may provide an arc indicative trip signal, relying on the characteristic that an arc is random and does not strike at the same relative phase point in each cycle. In this latter case, the given test conditions may be the existence of the current difference signals themselves. It is the purpose of the additional rules or conditions to establish concentration of random activity into regions within an AC cycle which enables discriminating an arc from normally operating loads. Section checker 140 checks the signal on line 138 from AND gate 120 over a given number of sections of the AC line current. As above noted, synchronous summer 94 accumulates absolute current difference signals ID over m cycles, e.g. m equals 5, to provide a first section, shown in Fig. 3 as section 1. Synchronous summer 94 repeats the accumulation of the m cycles over a plurality of sections. In the preferred embodiment, approximately one second (actually 55 AC cycles) of the AC line current waveform is divided into eleven sections, each having five cycles. Section checker 140 has a high output on line 142 only if its input 138 from AND gate 120 is high for a given number of sections. In the preferred embodiment, the signal on line 138 must be high for three out of eleven consecutive sections, i.e. the noted five conditions checked by condition checker 116 must be met in at least three of eleven consecutive sections. Thus, the arc indicative trip signal is generated only if the noted conditions are met in a given number of sections during a span of a predetermined number of consecutive sections. A high signal on line 142 enables AND gate 144 which in turn outputs the arc indicative trip signal on line 67 if a voltage condition is met, to be described. The purpose of section checker 140 is to discriminate against switching events, e.g. a light switch being turned on or off. Eleven consecutive sections is 55 cycles, which is nearly 1 second long. If a light switch is turned on or off, the noted conditions checked by condition checker 116 may be satisfied for one or perhaps at most two sections, but it is highly unlikely that such conditions are satisfied for three out of eleven consecutive sections, because such switching event is typically of shorter duration. Without section checker 140, short duration switching events may otherwise cause a false arc indicative trip signal, which is considered a nuisance trip. The inclusion of section checker 140 reduces such nuisance tripping. Voltage harmonic notch filter 146, Fig. 3, senses cycle to cycle changes in AC line voltage and generates voltage difference signals representing these changes. The arc indicative trip signal is disarmed when the voltage difference signals exceed a given threshold. Harmonic notch filter 146 performs point for point subtraction of AC line voltages to provide harmonic notch filter voltage difference signals HNFV, the absolute value of which provides voltage difference signals VD at time t according to: VD ( t ) = | HNFV ( t )| = | V ( t )- V ( t - T )| Eq .3. The AC line voltage change is preferably sensed between consecutive cycles, though other or intermittent cycle to cycle changes may be sensed. The voltage is preferably sensed through a voltage divider ohmically connected to line 46, though other voltage sensors may be used, for example as shown at 66 in the incorporated '685 patent. AC line voltage is sampled at a phase Φ 1,1 during a first cycle of the AC source to provide a voltage V 1,1 , where the first subscript is the sampling point or phase, and the second subscript is the cycle. The AC line voltage is sampled at a phase Φ 1,2 during a second cycle of the AC source to provide a voltage V 1,2 , where Φ 1,1 equals Φ 1,2 , i.e. the voltage is sampled at the same relative phase or sampling point during first and second cycles. V 1,1 is subtracted from V 1,2 to provide the HNFV difference signal, the absolute value of which is the voltage difference signal VD. The AC line voltage is sampled with harmonic notch filter 146 at a plurality of phases Φ 1,1 through Φ p,1 during a first cycle of the AC source to provide a plurality of sampled voltages V 1,1 through V p,1 . In the preferred embodiment, p equals n, and hence there are 1,341 voltage sampling points or phases, which span in the preferred embodiment 16.67 milliseconds. The AC line voltage is sampled with harmonic notch filter 146 at a plurality of phases Φ 1,2 through Φ p,2 during a second cycle of the AC source to provide a plurality of sampled voltages V 1,2 through V p,2 , where Φ 1,1 through Φ p,1 equals Φ 1,2 through Φ p,2 , respectively. V 1,1 through V p,1 is subtracted point for point from V 1,2 through V p,2 , respectively, to provide HNFV difference signals, the absolute value of which provides voltage difference signals VD 1 through VD p . Summer 148 sums the absolute value of the voltage difference signals VD over the p sampling points or phases to provide a sum. When such sum exceeds a given threshold, as determined by threshold detector 150, then the arc indicative trip signal is disarmed. In the preferred embodiment, the threshold is 3.73 times the number of sampling points or phases p. For example, AC line voltage is sampled at a first phase Φ 1,1 during a first cycle of the AC source to provide a voltage V 1,1 . AC line voltage is sampled at a second phase Φ 2,1 during the first cycle of the AC source to provide a voltage V 2,1 . AC line voltage is sampled at a first phase Φ 1,2 during a second cycle of the AC source to provide a voltage V 1,2 , wherein Φ 1,1 equals Φ 1,2 . AC line voltage is sampled at a second phase Φ 2,2 during the second cycle of the AC source to provide a voltage V 2,2 , where Φ 2,1 equals Φ 2,2 . V 1,1 is subtracted from V 1,2 to provide an HNFV difference signal, the absolute value of which provides a voltage difference signal VD 1,2-1 . V 2,1 is subtracted from V 2,2 to provide an HNFV difference signal, the absolute value of which provides a voltage difference signal VD 2,2-1 . Summer 148 sums VD 1,2-1 and VD 2,2-1 to provide a sum indicating voltage change from the first cycle to the second cycle. As noted above, preferably p equals n equals 1,341. The number of sampling points or phases p may be varied according to application. The AC line voltage is sampled at a plurality of phases Φ 1 through Φ p during a cycle. Harmonic notch filter 146 provides p cycle to cycle absolute voltage difference signals VD 1 through VD p , one for each of the phases Φ 1 through Φ p . Each voltage difference signal VD represents the absolute value of the difference between the voltage at its respective phase in the present cycle and the voltage at the same respective phase in a previous cycle, preferably the immediately preceding cycle. Summer 148 sums the first through the p th absolute voltage difference signals to provide a summed voltage change activity signal. When the summed voltage change activity signal from summer 148 exceeds the noted given threshold, then the output of threshold detector 150 on line 152 goes high. The high state on line 152 is inverted low by inverter 154, which provides a low state on line 156 which is input to AND gate 144 to disable the latter, and hence disarm or prevent generation of an arc indicative trip signal on line 67. The high state on line 152 also provides a reset signal at 158 to section checker 140 to interrupt any ongoing checking process and restart same to begin counting eleven consecutive sections upon receipt of a high state on line 138. A high state on line 138 activates section checker 140 to begin counting eleven consecutive sections. As soon as a high state is present for any two of the next ten sections, then output 142 goes high, and does so without waiting for any remaining sections. For example, if line 138 is high for sections 1, 3 and 8, then output 142 goes high at section 8, without waiting for the remaining sections 9 through 11. The reset signal at 158 interrupts the section checking, regardless of how many sections have been counted, and initiates a 0.1 second delay during which section checker 140 is cleared and then becomes available to begin counting upon the next-received high state on line 138, which high state initiates the eleven section counting process. Such next-received high state occurs in section 1 of the newly started counting process and provides the first of the three required sections in order to generate an arc indicative trip signal. A high state on line 152 indicates that the voltage change is coming from the supply side of the distribution circuit 20, i.e. the left side of the circuit in Fig. 2, at AC source 26, rather than from the load side, i.e. the right side of the circuit in Fig. 2, at load 30 or 31. If there are cycle to cycle changes in both current and voltage, as sensed by current harmonic notch filter 72 and voltage harmonic notch filter 146, respectively, then the arc indicative trip signal is disabled because the changing supply side voltage may be causing the current changes, or at least it is unknown whether an arc is causing the current changes. In this situation, it is desired that the breaker not be tripped due to events on the supply side, and hence the trip signal on line 67 is disabled when line 152 goes high indicating the noted voltage change. If there are cycle to cycle current changes as sensed by current harmonic notch filter 72, but not the noted voltage change, then the arc is on the load side. The absence of appropriate voltage change maintains line 152 low, which in turn enables AND gate 144 to generate the arc indicative trip signal on line 67 as controlled by the state of line 142. An arc is a kind of variable impedance. When the impedance changes, the current changes, but the supply voltage from the AC source 26 provided by the utility company is relatively stiff and does not change. Hence, there is no voltage change sensed by voltage harmonic notch filter 146, and line 152 remains low. The changing current sensed by current harmonic notch filter 72 is caused by some event other than changing supply voltage from source 26. As above noted, it is desired that changing supply voltage from source 26 not be identified as an arc to trip breaker 34. Fig. 12 further shows arc detector 64. AC line current is sensed with current sensor 170 provided by a current transformer, as above noted, terminated with a high impedance load and providing an approximation of the first derivative of current with respect to time which is fed to an operational amplifier 172 with gain and providing integration of the DI/DT signal back to a current signal. The current signal is fed through a 2-pole Butterworth anti-aliasing filter 174 and an 8-pole Butterworth low pass switched capacitor filter 176. The total filter has ten poles which reduces the signal down 60 dB at the Nyquist frequency. The signal is then supplied to a 12-bit A/D converter 178, provided by an Analog Devices, Inc. AD7886, converting the analog input to a digital output which is fed into field programmable gate array, FPGA, 180, provided by an Actel Corp. A1280-1PQ160C. AC line voltage is sensed with a voltage sensor 182, preferably provided by a voltage divider including passive filtering, and then supplied through op amp 184, 2-pole Butterworth filter 186, 8-pole Butterworth filter 188, and 12-bit A/D converter 190, provided by an Analog Devices, Inc. AD7886, to FPGA 180. FPGA 180 provides the noted 60 Hz harmonic notch filters and the synchronous summer, and is externally controlled by a power-on-reset generator 192 and a clock generator 194 providing 4.9152 MHz and 16 MHz clock signals. Memory 196 is provided by an Integrated Device Technology Corp. IDT71586, including 4K by 16 RAM for the current harmonic notch filter, 4K by 16 RAM for the voltage harmonic notch filter, and 4K by 16 RAM for the synchronous summer. FPGA 180 is linked by a first-in-first-out, FIFO, buffer 198, provided by an Advanced Micro Devices, Inc. AM7204-35, to a 16-bit microprocessor 200, provided by a Motorola MC68HC000, for transferring synchronous summer data therebetween. Microprocessor 200 is provided with a memory 202, provided by an Integrated Device Technology Corp. IDT71586, including 4K by 16 synchronous summer RAM, 4K by 16 data RAM, and 8K by 16 code ROM. Microprocessor 200 and FPGA 180 are operated in accordance with Fig. 3. It is expected that in future development the FPGA and perhaps the microprocessor will be replaced by an ASIC, application specific integrated circuit. Digital signal processing is preferred, though the invention may be implemented in an analog processing system if desired. The above described arc detection method involves sensing cycle to cycle changes in AC line current and generating difference signals representing such changes, and responding to given conditions of such difference signals to generate an arc indicative signal. This is shown in Fig. 13 where current I 1,1 at the first sampling point or phase in the first cycle, Θ 1,1 , is subtracted from the current I 1,2 sensed at the first sampling point or phase in the second cycle, Θ 1,2 . This provides the noted cycle to cycle sensing of changes in AC line current. An alternate method involves sensing subcycle changes in AC line current and generating difference signals representing such changes, and responding to given conditions of such difference signals to generate an arc indicative signal, wherein the subcycle is less than the cycle of the AC source. This is illustrated in Fig. 14 where the AC line current is sensed at Θ a , Θ b , Θ c and Θ d . First considering the subcycle from Θ a to Θ c , Fig. 14, it is seen that the AC line current at point Θ a of the AC waveform has the same absolute value as the AC line current at point Θ c of the AC waveform, absent a disturbance, such as an arc or a transient. Hence, the absolute value of the current difference signal between the current sensed at Θ c and the current sensed at Θ a is normally zero in the absence of an arc. Points Θ a and Θ c have the same relative spacing from a respective zero crossing of the AC waveform. It is likewise noted that the AC line current at point Θ a , Fig. 14, has the same absolute value as the AC line current at Θ b , absent a disturbance, such as an arc. Hence, the absolute value of the current difference signal between the AC line current at Θ b and Θ a is normally zero in the absence of an arc. Points Θ a and Θ b have the same relative spacing from a respective zero crossing of the AC waveform. The same relationship exists between Θ c and Θ d , between Θ b and Θ d , between Θ b and Θ c , and between Θ a and Θ d . The various time intervals between the various noted points is less than one cycle of the AC source. The time interval between points Θ a and Θ c , and between Θ b and Θ d , is one-half of the cycle of the AC source. The time interval between points Θ a and Θ b , and between Θ b and Θ c , and between Θ c and Θ d , is less than one-half of the cycle of the AC source. The time interval between points Θ a and Θ d is less than one cycle of the AC source and greater than one-half of the cycle of the AC source. When determining the difference between AC line currents at phases in opposite half-cycles, the algebraic sign of one or the other of the currents is inverted. For example, when determining the difference between the AC line current at point Θ c and Θ a , the negative value of the current at Θ c is inverted to a positive value, and the positive valued current at Θ a is subtracted from the positive valued current at Θ c to provide the noted HNFI difference signal, the absolute value of which provides the noted current difference signal ID. There is no need for such algebraic sign inversion when determining current differences at phase points within the same half-cycle or when the phase points are both in a negative half-cycle or when the phase points are both in a positive half-cycle. In general, the present method involves sensing changes in AC line current at predetermined points of the AC waveform, e.g. Θ 1,1 and Θ 1,2 in Fig. 13, Θ a and Θ c in Fig. 14, Θ a and Θ b in Fig. 14, etc., and generating difference signals representing such changes, and responding to given conditions of such difference signals to generate an arc indicative signal. The noted points of the AC waveform have the same absolute value absent a disturbance, such as an arc, such that the difference of the absolute values of the current difference signals is normally zero in the absence of an arc. The noted points have the same relative spacing from a respective zero crossing of the AC waveform. In the preferred embodiment, the time interval between the noted sampling points is equal to one cycle of the AC source, i.e. time interval T, Figs. 3 and 13. In another embodiment, the period between the sampling points is greater than one cycle of the AC source, and an integral multiple thereof. In another embodiment, the period between the sampling points is less than one cycle of the AC source. In another embodiment, the period between the sampling points is one divided by a multiple of the noted AC source frequency, where the multiple is an integer. In another embodiment, it would be possible to compare a point in one cycle with a corresponding point in another cycle not an integral number of cycles away, e.g. points Θ a and Θ e , Fig. 14. The present method includes sensing harmonic changes in AC line current by measuring the AC line current at predetermined periodic points in the AC waveform and generating difference signals representing such changes, and responding to given conditions of such difference signals to generate an arc indicative signal. There are some events which clearly should lead to an arc indicative trip signal. Examples are contacts which are teased, contaminated, or slowly moving, e.g. defective snap action, bimetallically controlled, etc. The present invention provides an arc indicative trip signal in response to these events. A class of equipment which can provide current signals having arc-like characteristics are certain SCR (silicon controlled rectifier) controlled commutated loads, for example when operated in the full wave mode at low speed (relative to maximum), i.e. partial duty cycle, and having a commutation mechanism, e.g. brushes. The reason for an arc-like current signature is that the phase controlled duty cycle under full wave conditions insures the existence of two quiet zones, while the commutation provides the cycle to cycle variations required. The solution to nuisance tripping or other false arc indication in such implementation depends on using a feature of SCR controlled loads, namely that they turn off the current at a zero crossing (self commutate) leading to a very low power factor trace at low mechanical speeds. Detecting this, e.g. by relating the synchronous sum features, e.g. peak, to the phase of the voltage, e.g. detected by a zero crossing, can provide a condition that could be used in the condition checker to prevent an arc indicative output trip signal. A small percentage of constant speed commutated (brush) motors, particularly aged motors, can lead to noisy traces which may provide undesirable arc indication. In such case, it has been found that the total number of transitions of the synchronous summer waveform from below to above the quiet zone threshold is very large compared to the number corresponding to an arc. This characteristic can he used to prevent nuisance tripping, for example by requiring less than a given number of peaks such as 84 and 86, Fig. 11, per cycle, i.e. by requiring that the current difference signals cross a given threshold no more than a given number of times during a given interval. It is recognized that various equivalents, alternatives and modifications are possible within the scope of the appended claims.

Claims: Apparatus (64) for detecting arcs in an electric circuit (20) supplying AC line current to a load (30) from an AC source (26) of given fundamental frequency providing repetitive cycles, said apparatus comprising: sensing means (170, 182) including means (170) sensing said AC line current to generate a sensed AC current signal; means (72) generating from said sensed AC current signal a filtered signal having the given fundamental frequency and harmonics thereof removed; means (94) for generating from said filtered signal a cumulative signal derived from said filtered signal over a selected number of cycles of said AC current, and for maintaining in said cumulative signal phase and magnitude information from said filtered signal over a selected number of cycles of said AC current; and condition checker means (116) responsive to selected conditions of said cumulative signal representative of an arc for generating an output signal. The apparatus (64) of Claim 1 wherein said means (72) generating said filtered signal comprises a harmonic notch filter generating difference signals between magnitudes of said sensed AC current signal at corresponding points in said sensed AC current signal, and wherein said means (94) generating said cumulative signal comprises a synchronous summer which generates said cumulative signal as a sum of absolute values of said difference signals at said corresponding points for said selected number of cycles of said AC current. The apparatus (64) of Claim 2 wherein said means (94) generating said cumulative signal repetitively generates said cumulative signal for successive sections of said AC signal, said sections each comprising a selected number of cycles of said AC current, and wherein said condition checker (116) further includes section checker means (140) enabling said output signal only when said condition checker (116) detects said selected conditions for a given nmnher of sections out of a predetermined number of consecutive sections of said AC signal. The apparatus (64) of Claim 3 wherein said means (94) generating said cumulative signal repetitively generates said cumulative signal for successive sections of said AC signal wherein said selected number of cycles comprising each section is five cycles of said AC current, and wherein said section checker (140) enables said output signal only when said condition checker detects said selected conditions for said given number of sections which is at least three sections out of said predetermined number of consecutive sections which is eleven consecutive sections of said AC signal. The apparatus (64) of any of Claims 1 through 4 wherein said condition checker (116) generates said output signal in response to a condition selected from a group of conditions consisting of: detection of a peak-to-average ratio of said cumulative signal exceeding a given ratio threshold, detection of an average value of said cumulative signal exceeding a given average threshold, detection of at least two quiet zones in said cumulative signal per cycle with each quiet zone being a portion of a cycle substantially throughout which said cumulative signal does not rise above a given current activity threshold and lasting for at least a minimum interval, detection of no quiet zone in said cumulative signal lasting longer than a given quiet zone upper time limit, detection of said cumulative signal having a null for no longer than a given null time upper limit, and combinations of said conditions. The apparatus (64) of any of Claims 1 through 4 wherein said condition checker (116) generates said output signal in response to each of the following conditions: detection of a peak-to-average ratio of said cumulative signal at least as-great as about 4, detection of an average value of said cumulative signal at least as great as about 0.4 amperes, detection of at least two quiet zones in said cumulative signal per cycle with each quiet zone lasting for an interval of at least about 1.5 milliseconds, detection of no quiet zone which exists for more than about 9 milliseconds, and detection of no null in said cumulative signal which lasts longer than about 1 24 milliseconds. The apparatus (64) of either Claim 1 or Claim 2 wherein said sensing means (170, 182) includes AC voltage sensing means (182) responsive to AC voltage provided by said AC source and disabling means (146 - 154) responsive to said voltage sensing means (182) for disabling said output signal in response to given conditions of said voltage. The apparatus of Claim 7 wherein said disabling means (146 - 154) comprises a harmonic notch filter (146) generating difference signals magnitudes of said AC voltage at corresponding points in said AC voltage, a summer (148) which generates a cumulative voltage signal as a sum of absolute values of said difference signals for a selected number of cycles, and means (150 - 154) generating a disable signal which disables said output signal when said cumulative voltage signal exceeds a given cumulative voltage threshold. An arc detection method for an electric circuit (20) supplying AC line current to a load (30) from an AC source (26) of given frequency providing repetitive cycles, said method comprising the steps of sensing the AC current to generate a sensed current signal, generating difference signals equal to the difference between the sensed current signal at corresponding phases in said cycles of AC current, accumulating absolute values of the difference signals over a selected number of cycles to generate cumulative difference signal, generating an arc indicative signal in response to a condition of said cumulative difference signals selected from a group of conditions consisting of : (i) a peak-to-average ratio of said cumulative difference signals exceeding a given ratio threshold, (ii) an average value of said cumulative difference signals exceeding a given average threshold, (iii) at least two quiet zones in said cumulative difference signals per cycle, with each said quier zone being a portion of a cycle wherein said cumulative difference signal does not substantially arise above a given current activity threshold and lasting for at least a given minimum interval, (iv) no quiet zone in said cumulative difference signals lasting longer than a given quiet zone upper limit, (v) said cumulative difference signals having a null for no longer than a given null time upper time limit, and any combination of said conditions. The method of Claim 9 wherein said cumulative difference signals are accumulated for a section of said AC line current comprising a selected number of cycles of said AC current and wherein said are detection signal is enabled only when said condition is detected for a given number of sections of said AC current out of a predetermined number of sections.

Inventors: TENNIES CHARLES JOSEPH, ZUERCHER JOSEPH CHARLES, TENNIES, CHARLES JOSEPH, ZUERCHER, JOSEPH CHARLES
Applicants: EATON CORP, EATON CORPORATION
Application year: 1994
Main classification: H02H1
IPC codes: H02H3, G01R31, H02H1