Input buffer circuit and bidirectional buffer circuit for plural voltage systems

Abstract: An input buffer circuit (200) for feeding to an internal circuit an "H" level or an "L" level input to a pad (11) via which a signal is transferred from or to an external circuit, comprising: an inverter (201); an N-channel transistor (204) disposed between said pad (11) and an input terminal of said inverter (201) with its gate connected to a power source (Vdd); and a feedback circuit for raising the input terminal potential of said inverter (201) to the power source potential when an "H" level signal is input to said pad (11). The input buffer circuit (200) may be employed in a bi-directional buffer circuit together with an output buffer circuit (100) sharing the same pad (11) for input and output of signals.

Description: The present invention relates to a semiconductor integrated circuit operable under circumstances where a plurality of supply voltages are coexistent, as in an instance where the integrated circuit is mounted on a board which is so designed as to operate with a power source including a plurality of supply voltages, and/or bearable against live disconnection. In respect of designing a circuit board, there is recently adopted a technique of reducing a supply voltage to, e.g., 3V for some partial device's while applying 5V to operate the other devices. In most cases, the reason is based on an attempt to realize suppression of the entire power consumption or on the specification that the rated supply voltage for some partial devices is lower than 5V. Under such circumstances where mutually different supply voltages are coexistent for the individual operations, there may arise a problem that, when a signal is fed from a 5V device to a lower-voltage device or the devices operated at mutually different voltages are connected to the same bus, a current comes to flow from the 5V device to the lower-voltage device. Such an undesired current flow may cause considerable disadvantages including an increase of the power consumption, latch-up of the devices and, due particularly to the voltage of 5V, breakdown of transistors in the latest miniaturized high-density devices. Fig. 9 typically shows how a 3V-operated device and a 5V-operated device are coexistent on a board while being connected to a common bus, and Fig. 10 is a schematic circuit diagram of a known conventional bi-directional buffer circuit enclosed with a circle in Fig. 9. When a 3V device and a 5V device are connected to a common bus as shown in Fig. 9, there arise the following problems (1) to (3) in the circuit of Fig. 10. (1) Upon input of 5V from an external bus 10 via a pad 11, a parasitic diode 12a for a P-channel transistor 12 in the final output stage is turned on to consequently form a current path (1), whereby a great leakage current is caused to flow therethrough. (2) Since merely 3V is applied to the gate of the P-channel transistor 12, this transistor 12 fails to be completely turned off and is therefore placed in a weak on-state, so that a current path (2) is formed therein also. (3) As 5V is applied to both an N-channel transistor 13 in the final output stage and an N-channel transistor 14 in the initial input stage, a high electric field is generated to eventually arouse some problems relative to the withstand voltage of gate oxide films, hot carriers and so forth, whereby the N-channel transistors 13 and 14 may be broken down. Fig. 11 typically shows conventional means contrived for solving the problems mentioned above. In this diagram, there is included merely its output buffer circuit alone. For the purpose of preventing a leakage current when the supply voltage is 5V with regard to the bus 10 on the board, 5V is applied to the final output stage. Further, the oxide film of the transistor only in the final output stage is processed to be thicker so that this transistor may not be deteriorated even if 5V is applied to the final output stage. In addition to such countermeasure, a level shift circuit for converting a 3V signal into a 5V one is incorporated to achieve complete turn-off of the P-channel transistor in the final output stage, wherein a 3V signal in a 3V system circuit is converted into a 5V signal, which is then supplied to the gate of the P-channel transistor in the final output stage. As a result of the means mentioned, there is contrived an improved circuit system where both a 3V-operated device and a 5V-operated device are rendered connectable to the common bus 10. However, for effecting the measures shown in Fig. 11, it is unavoidable that some processing steps are increased inclusive of forming a thicker oxide film only partially, and a longer time is required for manufacture of a chip to eventually bring about a rise of the production cost. Furthermore, it becomes necessary to supply voltages of two systems, i.e., 3V and 5V, to the devices to consequently induce additional complication of the wiring on the board with a disadvantageous increase in the number of required pins on the chip. In Japanese Patent Laid-open No. Hei 4 (1992)-290008, there is disclosed an off-chip driver circuit which comprises a single pull-up transistor; an output terminal; a voltage source for providing a supply voltage of a predetermined value in an arrangement where the pull-up transistor is disposed between the voltage source and the output terminal; a control transistor connected between the gate electrode of the pull-up transistor and the output terminal, and having a gate electrode connected to a first reference potential point; a bus gate; a predriver circuit coupled via the bus gate to the gate electrode of the pull-up transistor; and means for selectively applying to the output terminal a voltage considerably higher than the aforesaid supply voltage of a predetermined value. However, this known driver circuit also has some disadvantages that, since the substrate (back gate) of the pull-up transistor is biased from the power source via the control transistor, the back gate resistance is rendered high and therefore a latch-up problem is prone to be raised. Further, when a partial circuit board is inserted into and/or extracted from a connector of a main system without cutting power supply thereof, voltage may be applied to the pad without supplying voltage to the output buffer circuit due to disconnection of the connector. Also in this live disconnection case, the same current paths (1) (2) as shown in Fig. 10 cause in prior art output buffer circuit. So, there is a problem in a reliability. More specifically, when "H" is inputted to the pad 11 through connector pin under the condition that power supply 3V to the last stage transistor 12 is cut down (off) to 0V, currents (1) (2) as shown in Fig. 10 flow within transistor 12 so that parasitic diode 12a and then transistor 12 turned on. JP-A-62 090 020, which corresponds to the preamble of Claim 1, discloses an input buffer circuit having an N-channel and a P-channel MOS transistor in series between an input terminal and an input gate of the buffer circuit and between a power terminal and the input gate respectively. A clock signal is applied to the gate of the N-channel MOS transistor. An embodiment of the present invention can provide an input buffer circuit and a bi-directional buffer circuit producible without the necessity of any additional processing step, wherein merely a single power source is incorporated and there is permitted the application of a voltage higher than that of the single power source to a common bus. According to the present invention, an input buffer circuit for receiving an "H" level or an "L" level from an external circuit to an internal circuit through a pad, via which a signal is transferred from or to an external circuit, comprises: an inverter; an N-channel transistor disposed between the pad and the input terminal of the inverter with its gate connected to the power source; and a feedback circuit for raising the input terminal potential of the inverter to the power source potential at the time of inputting an "H" level to the pad; wherein: said feedback circuit includes a feedback P-channel transistor disposed between said power source and the input terminal of said inverter; and a gate of said feedback P-channel transistor is connected to an output terminal of a second inverter which is independent of the first inverter, and an input terminal of said second inverter is connected to an input terminal of said first inverter. Further, a bi-directional buffer circuit according to an embodiment of the present invention comprises an output buffer circuit, and an input buffer circuit consisting of the elements specified above, wherein the output and input buffer circuits are connected to the same pad. In a buffer circuit of the present invention, mutual connection between the gate of each transistor and the power source or the ground may be either direct or indirect through an impedance element such as a resistor. In an input buffer circuit embodying the present invention, the following measure is adopted to solve the above-mentioned problem (3). Since the N-channel transistor specified above is additionally provided, the high voltage is dispersed to this N-channel transistor and the inverter specified above so that generation of any high electric field exceeding the withstand voltage thereof is prevented. In addition, the feedback circuit specified above serves to raise the input voltage of the inverter to the regular value to consequently ensure a proper operation of the inverter. Thus according to the present invention, improvements are attained in the input buffer circuit and the bi-directional buffer circuit producible without the necessity of any change or addition of the processing steps, wherein merely a single power source is required. The preferred embodiment will be described with reference to the drawings, wherein like elements have been denoted throughout the figures with like reference numerals, and wherein: Fig. 1 is a circuit diagram showing a bi-directional buffer circuit; Fig. 2 is a circuit diagram similar to Fig. 1, showing the states of individual elements when an "H" (high) level (3V) signal is outputted to a pad; Fig. 3 is a circuit diagram similar to Fig. 1, showing the states of the individual elements when an "L"(low) level (0V) signal is outputted to the pad; Fig. 4 is a circuit diagram similar to Fig. 1, showing the state where a high impedance is outputted to the pad from the output buffer circuit and an "H" level (5V) is applied to the pad from an external circuit; Fig. 5 is a circuit diagram similar to Fig. 1, showing the state where a high impedance is outputted to the pad from the output buffer circuit and an "L" level (0V) is applied to the pad from the external circuit; Fig. 6 is a circuit diagram showing an embodiment of the bi-directional buffer circuit according to the present invention; Fig. 7 is a circuit diagram showing a bi-directional buffer circuit; Fig. 8 is a circuit diagram similar to the circuit of Fig. 7 rewritten with partial modification of its output buffer circuit; Fig. 9 typically shows how a 3V-operated device and a 5V-operated device are coexistent with mutual connection to a common bus on a board; Fig. 10 is a circuit diagram showing a conventional bi-directional buffer circuit of the prior art enclosed with a circle in Fig. 9; and Fig. 11 typically shows the known measures adopted in the prior art. Hereinafter the preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. Fig. 1 is a circuit diagram of a bi-directional buffer circuit. Before describing the input buffer circuit which is the main subject of the invention, an output buffer circuit will be described by way of background explanation. The output circuit 100 Fig. 1 serves for outputting an "H" level, an "L" level or a high impedance to a pad 11. In the output buffer circuit 100, there is a successive series connection of a first P-channel transistor 101 and a second P-channel transistor 102 between a 3V power source Vdd and the pad 11 in this order, wherein a back gate of the first P-channel transistor 101 is connected to the power source Vdd while aback gate of the second P-channel transistor 102 is connected to the pad 11. Also in the output buffer circuit 100, there is a successive series connection of a first N-channel transistor 103 and a second N-channel transistor 104 between the pad 11 and a ground GND in this order. A gate of the first P-channel transistor 101 is connected to an output terminal of a first inverter 105, and a signal D1 is inputted to the first inverter 105. In this circuit, an output terminal 121 of the first inverter 105, i.e., a gate terminal of the first P-channel transistor 101, corresponds to a first signal input terminal, and therefore the signal D1 is the one obtained by inverting the logic of the first signal. The gate of the second P-channel transistor 102 is connected to an output terminal 121 of the first inverter 105 via a third N-channel transistor 106 and a fourth N-channel transistor 107 which are connected in series between the output terminal 121 of the first inverter 105 and the gate of the second P-channel transistor 102. Further a third P-channel transistor 108, whose back gate is connected to the pad 11, is connected between the gate of the second P-channel transistor 102 and the pad 11. An enable signal EN is inputted to the gate of the third N-channel transistor 106. In this circuit, the gate terminal of the third N-channel transistor 106 corresponds to an enable signal input terminal. A gate of the fourth N-channel transistor 107 and a gate of the third P-channel transistor 108 are both connected to an input terminal 123 of a second inverter 109. And a signal D2 is inputted to the second inverter 109. A gate of the first N-channel transistor 103 is connected to the power source Vdd, while a gate of the second N-channel transistor 104 is connected to an output terminal 122 of the second inverter 109. In this circuit, the output terminal 122 of the second inverter 109, i.e., the gate terminal of the second N-channel transistor 104, corresponds to a second signal input terminal; and the input terminal 123 of the second inverter 109, i.e., each gate terminal of the fourth N-channel transistor 107 and the third P-channel transistor 108, corresponds to a third signal input terminal. Therefore the signal D2 corresponds to the third signal, and the signal obtained by inverting the third signal in the second inverter 109 corresponds to the second signal. The input buffer circuit 200 employed in the bi-directional buffer circuit of Fig. 1 comprises an inverter 201 which consists of a pair of P-channel transistor 202 and N-channel transistor 203 connected in series between a power source Vdd and a ground GND, a fifth N-channel transistor 204 disposed between the pad 11 and an input terminal of the inverter 201 with its gate connected to the power source Vdd, a feedback P-channel transistor 205 disposed between the power source Vdd and the input terminal of the inverter 201 with its gate connected to an output terminal of the inverter 201, and a third inverter 206 whose input terminal is connected the output terminal of the inverter 201. Fig. 2 is a circuit diagram similar to Fig. 1, showing the states of individual elements when an "H" level (3V) signal is outputted to the pad 11. In outputting an "H" level to the pad 11, both of the signals D1 and D2 are transited to an "H" level, while the enable signal EN is held at an "H" level. When the signals D1 and D2 are transited to an "H" level in the state where the enable signal EN is held at an "H" level, an "L" level is applied to the gate of the first P-channel transistor 101, so that the first P-channel transistor 101 is turned on and then a parasitic diode 102a of the second P-channel transistor 102 is bulk-charged to thereby start transition of the pad 11 to an "H" level. Since the third N-channel transistor 106 and the fourth N-channel transistor 107 are both turned on, the second P-channel transistor 102 is also turned on thereafter, whereby an "H" level is outputted to the pad 11 via the first P-channel transistor 101 and the second P-channel transistor 102. And simultaneously an "L" level is applied to the gate of the second N-channel transistor 104 to thereby turn off the same. In this stage of the operation, an "H" level is applied to the input buffer circuit 200 as well, and due to the application of 3V from the power source Vdd to the gate of the fifth N-channel transistor 204, the input terminal of the inverter 201 receives a voltage (Vdd - Vth) which is lower than the source voltage Vdd by a threshold voltage Vth, e.g., 2.2V when Vth = 0.8V. Consequently the potential at the output terminal of the inverter 201 is lowered to thereby turn on the P-channel transistor 205, so that the source voltage Vdd = 3V is applied via the P-channel transistor 205 to the input terminal of the inverter 201. As a result, the output terminal of the inverter 201 is completely turned to an "L" level, and this signal is supplied via the third inverter 206, which then transits the signal D3 to an "H" level. The above operation is performed in the input buffer circuit 200 in response to the "H" level output to the pad 11, but normally the signal D3 is not used at the time of outputting the signal from the output buffer circuit 100 to the pad 11. As described, this bi-directional buffer circuit performs a satisfactory operation without any problem when outputting an "H" level signal to the pad 11. Fig. 3 is a circuit diagram similar to Fig. 1, showing the states of the individual elements when an "L" level (0V) signal is outputted to the pad 11. In outputting an "L" level to the pad 11, both of the signals D1 and D2 are transited to an "L" level. Meanwhile the enable signal EN is still held at an "H" level at this time as well. When the signals D1 and D2 have both been transited to an "L" level in the state where the enable signal EN is held at an "H" level, the second N-channel transistor 104 is turned on. Since the first N-channel transistor 103 is also in its on-state at this time, the pad 11 and the ground GND are connected to each other via the first and second N-channel transistors 103 and 104, whereby an "L" level (0V) is outputted to the pad 11. In this stage of the operation, an "H" level is applied to the gate of the first P-channel transistor 101 to consequently turn off the same, whereby the gate potential of the second P-channel transistor 102 is rendered indefinite. However, as its back gate is connected to the pad 11, the potential is changed to 0V so that the second P-channel transistor 102 is also turned off. And simultaneously, an "L" level is applied to the input terminal of the inverter 201 in the input buffer circuit 200, thereby turning the output terminal of the inverter 201 to an "H" level while turning the output signal D3 of the third inverter to an "L" level. Thus, the bi-directional buffer circuit of Fig. 3 performs a satisfactory operation without any problem also when outputting an "L" level signal to the pad 11. Fig. 4 is a circuit diagram similar to Fig. 1, showing the state where a high impedance is outputted from the output buffer circuit 100 to the pad 11 and an "H" level (5V) is applied from an external circuit to the pad 11. In this stage of the operation, an "L" level is inputted as the enable signal EN, while an "L" level and an "H" level are inputted as the signals D1 and D2 respectively. At this time, an "H" level is applied to the gate of the first P-channel transistor 101, which is thereby turned off. And simultaneously therewith, 3V of the signal D2 is applied to the gate of the third P-channel transistor 108 while 5V of the pad 11 is applied to the back gate thereof, so that a current denoted by reference numeral (2) in Fig. 10 flows in the third P-channel transistor 108 to thereby cause application of 5V to the gate of the second P-channel transistor 102. Consequently the second P-channel transistor 102 is placed completely in its off-state. In this stage of the operation, the fourth N-channel transistor 107 is in its on-state as an "H" level (3V) of the signal D2 is applied to the gate thereof, but since it is an N-channel transistor, the potential at the junction of the third N-channel transistor 106 and the fourth N-channel transistor 107 is 2.2V for example, so that any high electric field exceeding the withstand voltage is not generated in the fourth N-channel transistor 107 either. Further the potential difference between the source and the drain of the third N-channel transistor 106 is suppressed to be as low as 0.8V. Since an "L" level is applied simultaneously therewith to the gate of the second N-channel transistor 104, this transistor 104 is turned off and then 5V applied to the pad 11 is divided to the first N-channel transistor 103 and the second N-channel transistor 104, so that any high electric field exceeding the withstand voltage is not generated in the first N-channel transistor 103 or the second N-channel transistor 104 either.' A voltage of 5V applied to the pad 11 is subsequently applied to the fifth N-channel transistor 204 in the state where 3V is being applied to the gate of this transistor 204, so that 2.2V is applied to the input terminal of the inverter 201. As a result, merely 2.8V is applied between the source and the drain of the fifth N-channel transistor 204, and consequently any high electric field exceeding the withstand voltage is not generated therein. Subsequently, as mentioned, 3V is applied to the input terminal of the inverter 201 via the feedback P-channel transistor 205, and then the output of the inverter 201 is turned to an "L" level while the output signal D3 of the third inverter 206 is turned to an "H" level, and thereafter the "H"-level signal D3 thus obtained is fed to the inside. As described above, when a high impedance is outputted from the output buffer circuit 100 in this manner and 5V is applied to the pad 11 from an external circuit, there arises none of the problems (1) to (3) described with reference to Fig. 10, and the 5V "H"-level signal applied to the pad 11 is converted to a 3V "H"-level signal and then is fed to the inside. Fig. 5 is a circuit diagram similar to Fig. 1, showing the state where a high impedance is outputted from the output buffer circuit 100 to the pad 11 and an "L" level (0V) is applied from the external circuit to the pad 11. In this case, each transistor operates in such a manner as shown in Fig. 5, and the "L"-level signal (0V) applied to the pad 11 is fed to the inside without causing any of the problems (1) to (3) described with reference to Fig. 10. Thus, according to the circuit shown in Fig. 1, an improved bi-directional buffer circuit can be realized without the necessity of any modification or addition in the processing steps, wherein merely a single 3V power source is incorporated and application of an external voltage of 5V is permitted. In this circuit, the back gate (substrate) of the first P-channel transistor 101, which serves as a power supply side pull-up transistor with its source electrode connected to the power source Vdd, is connected directly to the power source Vdd, and the second P-channel transistor 102 is existent between the first P-channel transistor 101 and the pad 11, so that it becomes possible to prevent occurrence of a latch-up trouble. Fig. 6 is a circuit diagram of an embodiment which represents the bi-directional buffer circuit of the present invention. A description will now be given below only on the difference from the aforementioned first embodiment shown in Fig. 1. A gate of a first N-channel transistor 103 in the second embodiment is connected to an output terminal 121 (first signal input terminal) of a first inverter 105. Meanwhile a gate of a fourth N-channel transistor 107 is connected to an input terminal 123 of a second inverter 109, and a gate of a third P-channel transistor 108 is connected to a power source Vdd. The connection of each gate of such first N-channel transistor 103 and third P-channel transistor 108 constituting an output buffer circuit 100 may be changed individually as shown in Fig. 1 or Fig. 6. A gate of a feedback P-channel transistor 205 in an input buffer circuit 200 of the second embodiment is connected to an output terminal of an inverter 207, and an input terminal the inverter 207 is connected to an input terminal of an inverter 201. In this manner, the feedback circuit for raising the input terminal potential of the inverter 201 from 2.2V to 3V may be formed into a variety of configurations without being limited to the aforementioned example alone. Fig. 7 is a circuit diagram of a bi-directional buffer circuit. A description will now be given below only on the difference from the aforementioned circuit shown in Fig. 1. In Fig. 7, a junction 110 of a first P-channel transistor 101 and a second P-channel transistor 102 is connected to.a junction 111 of a first N-channel transistor 103 and a second N-channel transistor 104. Fig. 8 is a circuit diagram similar to Fig. 7 rewritten with partial modification of its output buffer circuit. Due to the mutual connection of the two junctions 110 and 111, the second P-channel transistor 102 and the first N-channel transistor 103 are connected in parallel to each other as shown in Fig. 8. It may be possible in both of the first and second embodiments as well to drive fast an external load connected to the pad 11 by turning on the parasitic diode at the time of a level transition. Meanwhile, in the third embodiment where the second P-channel transistor 102 and the first N-channel transistor 103 are in parallel connection, a greater current is permitted to flow in comparison with the first and second embodiments when the signal of the pad 11 is changed from an "L" level to an "H" level or from an "H" level to an "L" level, whereby the external load can be driven at a higher speed. For example, a Bi-directional buffer circuit comprises a second P-channel transistor (102) whose back gate is connected to a pad (11), a third P-channel transistor (108) disposed between a gate of the second P-channel transistor (102) and the pad (11) with its back gate connected to the pad (11), and a first N-channel transistor (103) and a fifth N-channel transistor (204) whose gates are connected to a power source (Vdd), so that an output buffer circuit (100), an input buffer circuit (200) and a bi-directional buffer circuit can be produced without necessity of any additional processing step, wherein merely a single power source is incorporated, and a voltage higher than the source voltage is permitted to be applied to a common bus. Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the scope of the invention as set forth in the following Claims.

Claims: An input buffer circuit (200) for feeding to an internal circuit an "H" level or an "L" level input to a pad (11) via which a signal is transferred from or to an external circuit, comprising: an inverter (201); an N-channel transistor (204) disposed between said pad (11) and an input terminal of said inverter (201) with its gate connected to a power source (Vdd); and a feedback circuit for raising the input terminal potential of said inverter (201) to the power source potential when an "H" level signal is input to said pad (11); wherein: said feedback circuit includes a feedback P-channel transistor (205) disposed between said power source (Vdd) and the input terminal of said inverter (201); characterized in that a gate of said feedback P-channel transistor (205) is connected to an output terminal of a second inverter (207) which is independent of the first inverter (201), and an input terminal of said second inverter (207) is connected to an input terminal of said first inverter (201). The input buffer circuit (200) according to claim 1, wherein the gate of said N-channel transistor (204) is connected via an impedance element to said power source (Vdd) or a ground (GND). A bi-directional buffer circuit including an output buffer circuit (100) and said input buffer circuit (200) according to claim 1 or 2, wherein said output buffer circuit (100) and said input buffer circuit (200) are both connected to the same pad (11).

Inventors: KEIDA HISAYA, KOBAYASHI KENICHIRO, KEIDA, HISAYA, KOBAYASHI, KENICHIRO, KEIDA, Hisaya, c/o Kawasaki Steel Corporation, Kobayashi, Kenichiro, c/o Kawasaki Steel Corp.
Applicants: KAWASAKI MICROELECTRONICS INC, KAWASAKI MICROELECTRONICS, INC.
Application year: 1994
Main classification: H03K19
IPC codes: H03K19