Solid state imaging device including monitoring pixel

Abstract: A solid state imaging device includes a plurality of picture photosensitive pixels (pixel trains P₁-P n ) for generating signal charges corresponding to an incident light amount, a shift gate (12) and a charge coupled device (CCD) register (13) for sequentially transferring the signal charges outputted from the picture photosensitive pixels, and a monitor photosensitive pixel (11) for generating signal charges in proportion to a mean value of the incident light amount of a predetermined number of the picture photosensitive pixels. The device further includes a single output circuit for converting both signal charges, one of which are generated in the picture photosensitive pixels and transferred through the shift gate and CCD register, and the other of which are generated in the monitor photosensitive pixels, into an output signal, thereby providing the solid state imaging device capable of accurately measuring a mean value of the signal charges of the picture photosensitive pixels.

Description: BACKGROUND OF THE INVENTION The present invention relates to a solid state imaging device including a photosensitive pixel for monitoring, and applicable to an automatic focusing device for a camera and the like. A charge coupled device (CCD) image sensor has been well known as a solid state imaging device. There has been also well known a CCD image sensor including a photosensitive pixel for monitoring, which is applicable to the sensor used in an automatic focusing device of the camera and like, in order to control a storage time of a signal charge in each photosensitive pixel (for a picture) and a gain of an output circuit which converts the signal charge into an output signal. A solid state imaging device according to the preamble of claim 1 is known from US-A-4 701 626. A similar conventional device is described hereinbelow with reference to Fig. 1 of the drawings. In FIG. 1 a plurality of photosensitive pixels for a picture are arranged in a matrix shape on a semiconductor substrate (not shown) so as to form a plurality of pixel trains P 1 through P n . A photosensitive pixel 1 for a monitor generates signal charges in proportion to a mean value of an incident light amount of the photosensitive pixels for a picture. The signal charges generated in the photosensitive pixel 1 for a monitor are outputted as a signal V AGC through an output buffer 2 so as to supply to a control circuit (not shown) externally provided. The control circuit opens a shift gate 3 at each time when the supplied signal V AGC reaches a predetermined threshold value, so as to transfer the signal charges to a charge coupled device (CCD) register 4. Each of the signal charges transferred into the CCD register 4 are converted into an output signal in an output circuit 5 so as to be externally outputted. Here, the output circuit 5 comprises an output buffer 6, a voltage amplifying circuit 7, and a clamp circuit 8. The voltage amplifying circuit 7 changes over a gain according to an instruction from the control circuit when the signal V AGC is less than the threshold value, for example, because an incident light amount is little. Furthermore, the clamp circuit 8 causes the output signal of the output circuit 5 to be within an input range of an analog/digital (A/D) converter provided in the latter stage, in which the lower and upper most values are set by the control circuit. In this manner, in the CCD image sensor as shown in FIG. 1, the monitor photosensitive Pixel 1 is provided as means for measuring the mean value of the signal charges of each picture photosensitive pixel constituting the pixel trains P 1 -P n . However, since the conventional CCD image sensor includes the output circuit 5 having the output signal of the output buffer 2 and the output signal V AGC which have different voltage gain and off-set voltage, the monitor photosensitive pixel 1 has a very bad accuracy as the measuring means for the mean value as described above. Therefore, the CCD image sensor as shown in FIG. 1 also has the bad accuracy at the time when the threshold value is determined at opening the shift gate 3. Accordingly, such the CCD image sensor can not set the optimum threshold value corresponding to the incident light amount. Furthermore, since the accuracy of the output signal V AGC is wrong, it is impossible to set the optimum values of the gain of the voltage amplifying circuit 7 and the upper and lower most values of the clamp circuit 8 by using the output signal V AGC . Therefore, it has been general to set the gain of the voltage amplifying circuit 7 and the upper and lower most values of the clamp circuit 8 to be the optimum value by using as a reference value the signal charges which are generated in a shaded, pixel provided at the head of the pixel trains P 1 -P n and which is a signal pixel when the incident light amount is zero. However, in the method of using the signal charges of such the shaded pixel, since the lowest level is used as the reference level without the mean level, it is impossible to sufficiently and accurately set the gain of the voltage amplifying circuit 7 and the upper- and lower-most values of the clamp circuit 8. Such a fault becomes obvious according to the case where the contrast is small in the incident light amount of the pixel trains P 1 to P n . From US-A-4 843 474 it is known to use common output means for converting first signal charges constituting image charges, and second signal charges constituting photometric or exposure charges, for converting both said first and second signal charges into first and second output signals. US-A-4 809 077 discloses a solid state imaging device including a plurality of picture photosensitive pixels for generating first signal charges corresponding to an incident light amount, signal charge transfer means for transferring the first signal charges outputted from the picture photosensitive pixels, and a monitor photosensitive pixel for generating second signal charges, wherein an amplifying circuit for amplifying an output signal is controlled for setting a gain of the amplifying circuit. SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid state imaging device according to the preamble of claim 1 so as to improve the accuracy of the second signal charges in proportion to the mean value. According to the present invention, this object is attainded by the features of the characterizing part of claim 1. Further improvements of the present invention are specified in the sub-claims. The solid state imaging device according to the present invention includes a plurality of picture photosensitive pixels for generating first signal charges corresponding to an incident light amount, signal charge transfer means for transferring in order the first signal charges outputted from the picture photosensitive pixels, and a monitor photosensitive pixels for generating second signal charges in proportion to the means value of the incident light amount of the picture photosensitive pixels having a predetermined number, in which the solid state imaging device comprises output means for converting both of the first and second signal charges into first and second output signals, in which the first signal charges are generated in the picture photosensitive pixels and transferred by the signal charge transfer means, and the second signal charges are generated in the monitor photosensitive pixels. As an aspect of the present invention, the solid state imaging device is desired to further comprise a clamp circuit which is provided in the output means for clamping the output signal which is generated by converting the first signal charges transferred from the signal charge transfer means, and a control circuit for setting an upper limit or low limit voltage of the clamp circuit on the basis of the output signal which is generated by converting the second signal charges of the monitor photosensitive pixels by the output means. As a second aspect of the present invention, the solid state imaging device is desired to further comprise an amplifying circuit for amplifying the output signal which is converted from the first signal charges transferred from the signal charge transfer means, and a control circuit for setting a gain of the amplifying circuit on the basis of the output signal which is converted from the second signal charges outputted from the monitor photosensitive pixels. By the above construction, since the voltage gain and the off-set voltage of the first and second signal charges are caused to be equal to each other by the same output means which outputs the first signal charges generated in the picture photosensitive pixels and the second signal charges generated in the monitor photosensitive pixels, it is possible to accurately measure the means value of the first signal charges of the picture photosensitive pixels. Furthermore, since it is possible to accurately measure the mean value of the first signal charges of the picture photosensitive pixels in the above way, the optimum value can accurately be set with respect to the gain of the voltage amplifying circuit and the upper limit and low limit values of the clamp circuit by using the mean value. As described above, the solid state imaging device according to the present invention can accurately measure the mean value of the signal charges of the picture photosensitive pixels. Accordingly, it is possible to precisely set the optimum value with respect to the gain of the voltage amplifying circuit and the upper limit and low limit values of the clamp circuit both provided in the output circuit. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a block diagram schematically showing a constitution of the conventional solid state imaging device; FIG. 2 is a block diagram schematically showing a constitution of a solid state imaging device according to a first embodiment of the present invention; FIG. 3 is a graph showing a change with lapse of time in a output signal of an output circuit shown in FIG. 2; FIG. 4 is a circuit diagram showing an output circuit according to a second embodiment of the present invention as a detailed circuitry of the output circuit of the solid state imaging device according to the first embodiment; FIG. 5 is graph showing a change of the output signals of the output circuit shown in FIG. 4; FIG. 6 is a graph showing an input/output relationship for explaining an operating point of an output buffer in the output circuit shown in FIG. 4; FIG. 7 is a circuit diagram showing an output circuit according to a third embodiment of the present invention including a different and detailed constitution; FIG. 8 is a graph showing an input/output relationship for explaining an operating point of an output buffer in the output ci'rcuit shown in FIG.7; FIG. 9 is a block diagram showing a solid state imaging device according to a fourth embodiment of the present invention; FIG. 10 is a block diagram showing a solid state imaging device according to a fifth embodiment of the present invention; FIG. 11 is a block diagram showing a solid state imaging device according to a sixth embodiment of the present invention; FIG. 12 is a circuit diagram showing a solid state imaging device according to a seventh embodiment of the present invention; FIG. 13 is a graph showing a change with lapse of time in an output signal of an output circuit shown in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS There will be described in detail a solid state imaging device by using a CCD image sensor as an example according to preferred embodiments of the present invention in reference with the attached drawings. FIG. 2 shows a block diagram schematically showing a constitution of a CCD image sensor according to a first embodiment of the present invention. In FIG. 2, a plurality of picture photosensitive pixels are arranged in a matrix shape on a semiconductor substrate (not shown), in which each line of the picture photosensitive pixels forms pixel trains P 1 -P n . Here, signal charges. occurring in each picture photosensitive pixel can be transferred to the direction for a shift gate 12. Monitor photosensitive pixel 11 is arranged along two sides of a region in which the pixel trains P 1 -P n are arranged as shown in FIG. 2, so as to generate signal charges in proportion to a mean value of an incident light amount of these picture photosensitive pixels. A shift gate 12 comprises a portion which transfers the signal charges from the pixel trains P 1 -P n to the CCD register 13, and a portion which transfers the signal charges from the monitor photosensitive pixel 11. Opening and closing of the shift gate 12 are controlled by a control circuit 18 which will be mentioned later. The CCD register 13 takes into the signal charges occurring in the pixel trains P 1 -P n from the shift register 12 as a parallel signal so as to convert the parallel signal into a serial signal, thereby outputting the serial signal to an output circuit 14 which will be mentioned later. When the signal charges occurring in the monitor photosensitive pixel 11 are taken by the shift gate 12, the signal charges are transferred to the output circuit 14 as they are. The output circuit 14 comprises an output buffer 15, a voltage amplifying circuit 16, and a clamping circuit 17, which are the same constitution as the conventional CCD image sensor. A control circuit 18 takes in order an output signal V AGC which is obtained by converting in the output circuit 14 the signal charges occurring in the monitor photosensitive pixel 11. At each time when an integral value of the signal V AGC reaches to a predetermined threshold value, any gate of the shift gate 12 is opened for transferring the signal charges occurring in the corresponding pixel in the picture photosensitive pixels P 1 -P n to the CCD register 13. Furthermore, the control circuit 18 changes over the gain in the voltage amplifying circuit 16 corresponding to a value of the signal V AGC . Moreover, the circuit 18 changes over the upper limit or low limit value of the clamping circuit 17 corresponding to the value of the signal V AGC . Next, there will be described operation of the CCD image sensor shown in FIG. 2 in accordance with FIG. 3 which is a graph showing a change with lapse of time of a voltage level in an output signal of the output circuit 14. First, the control circuit 18 opens a gate corresponding to the monitor photosensitive pixel 11 the shift gate 12. By this, the signal charges occurring in the monitor photosensitive pixel 11 are transferred by the CCD register 13 into the output circuit 14 in which the signal charges are converted into the output signal V AGC . The signal V AGC is supplied to the control circuit 18 in which the value of the signal V AGC accurately corresponds to the mean value of the signal charges of the picture photosensitive pixels constituting the pixel trains P 1 -P n . The control circuit 18 uses the inputted signal V AGC and determines the threshold value for opening and closing the shift gate 12, the gain of the voltage amplifying circuit 18, and the upper limit and low limit values of the clamp in the clamping circuit 17 during a time T 1 . Here, the gain of the voltage amplifying circuit 16 is controlled by comparing the signal V AGC with a plurality of judge levels (represented here as V 1 , V 2 , ...) in order. For example, the gain may be set to the different values when V 1 > V AGC > V 2 , or when V 2 > V AGC > V 3 . In the first embodiment, since the signal V AGC is clamped by the clamping circuit 17, it is possible to easily set the judge levels from the upper or low limit value of a clamping. Furthermore, the upper and low limit values of a clamp in the clamping circuit 17 are determined along the standard of the signal V AGC . Accordingly, since the value of the signal V AGC precisely corresponds to the mean value of the signal charges of the picture photosensitive pixels as has been described, it is unnecessary to determine the upper and low limit values of the clamp by using as the standard the signal charges which are generated in the shaded pixels. Therefore, in the first embodiment, since it is easy to set the optimum value with respect to the upper and low limit values, a high quality picture signal can be obtained even though there is a case where a contrast is small with respect to each signal charge in the picture photosensitive pixels. Furthermore, the threshold value for opening and closing the shift gate 12 is determined by an integral result of the signal V AGC supplied during the time T 1 . When the threshold value is determined, the control circuit 18 continuously inputs the signal V AGC and integrates the inputted signal V AGC . When the integral result reaches to the threshold value, the circuit 18 closes the gate corresponding to the monitor photosensitive pixel 11 in the shift gate 12, and opens the gate corresponding to the picture photosensitive pixel trains P 1 -P n . By this, the signal charges occurring in the picture photosensitive pixels are transferred to the CCD register 13 in which the charges are converted from a parallel signal into a serial signal so as to sequentially input into the output circuit 14. These signal charges are converted into voltage signals by an output buffer 15, which are amplified in the voltage amplifying circuit 16. The clamping circuit 17 clamps the amplified voltage signals so as to be outputted to an analog/digital converter (not shown) as the next stage. In this manner, in the CCD image sensor according to the first embodiment, the single output circuit 14 converts the first signal charges occurring in the pixel trains P 1 -P n and the second signal charges occurring in the monitor photosensitive pixel 11 into the output signal to be outputted.' Accordingly, since the voltage gain and the off-set are the same in these signal charges, it is possible to improve the accuracy of the mean value of the signal charges of the picture photosensitive pixels measured by the monitor photosensitive pixel 11. Therefore, it is possible for the first embodiment to precisely set the optimum value with respect to the gain of the voltage amplifying circuit 16 and the upper and low limit values of the clamping circuit 17. In the first embodiment the monitor photosensitive pixel is arranged along two sides of the region in which the pixels P 1 -P n are arranged. Furthermore, even though the first embodiment adopts the configuration in which the shift register 12 and the CCD register 13 transfer the signal charges occurring in the monitor photosensitive pixel 11 into the output circuit 14, the present invention may comprise means for transferring the signal charges into the output circuit 14. Moreover, even though the first embodiment comprises only one monitor photosensitive pixel, another monitor photosensitive pixel and output buffer-may be provided in addition to the pixel 11 and output buffer 15. In the solid state imaging device according to the first embodiment shown in FIG. 2, if the output circuit 14 is described in detail, there is an output circuit 20 according to a second embodiment shown in FIG. 4. In FIG. 4, components attached by the same numerals in FIG. 2 are the same components in the solid state imaging device according to the first embodiment. The CCD register 13 comprises an N-channel metal oxide semiconductor (MOS) transistor 131, and a capacitor 132, in which a signal V 1 is detected from a junction point between a drain of the transistor 131 and the capacitor 132. Furthermore, a control potential C 4 is detected from an electrode of the CCD register 13, and a control potential C 1 is supplied to a gate of the MOS transistor 131. The output buffer 15 comprises an N-channel MOS transistor 151 having a gate to which the signal V 1 is supplied, and an N-MOS transistor 152 as a constant current source which is connected in series with the transistor 151. A potential of a junction point between the transistors 151 and 152 is stored in a capacitor 161 in the voltage amplifier circuit 16. The voltage amplifier circuit 16 comprises the capacitor 161, and N-MOS transistors 162-164, and has a characteristic in which an output operating point of the voltage amplifier circuit 16 is determined by a junction voltage V 20 between a drain-gate of the transistors 162 and 164 and the capacitor 161 and a junction potential V 2 between a source of the transistor 162 and a junction point of the transistors 163 and 164, as shown in FIG. 6. The control potential C 2 is supplied to a gate of the transistor 162. The clamping circuit 17 comprises a capacitor 171 and transistors 172-174, in which the capacitor 171 stores a junction potential V 2 of the voltage amplifier circuit 16. A control potential C 3 is supplied to a gate of the transistor 172, and a source of the transistor 172 is connected to a reference potential V ref . A potential of a junction point between the capacitor 171 and a drain of the transistor 172 is supplied to a gate of the transistor 173, and a potential V 3 of a junction point between a drain of the transistor 173 and a source of the transistor 174 as a constant current source is supplied to a control circuit 18 as the signal V AGC . A potential of each portion in FIG. 4 can be shown in a timing chart of FIG. 5, in which an output potential V 1 , V 2 and V 3 of the output buffer 15, voltage amplifying circuit 16 and clamping circuit 17 respectively have a wave form shown in FIG. 5. Control potentials C 1 -C 4 respective have timings shown in FIG. 5. In this manner, the mean value is clamped. Next, using FIGS. 7 and 8, there is described a solid state imaging device according to a third embodiment of the present invention. FIG. 7 shows an output circuit 30 as a modified example of the output circuit 20 shown in FIG. 4. The output circuit 30 includes a voltage amplifying circuit 16A comprising transistors 165 and 169 both gates of which gains G 1 and G 2 are supplied in the manner that signal levels "H" and "L" are alternatively changed over, in the place of the voltage amplifying circuit 16 as shown in FIG. 4. An output operating point of the voltage amplifying circuit 16A is shown in FIG. 8, and also a relationship between an output potential V' 2 and input potential V' 20 of the voltage amplifying circuit 16A is shown in FIG. 8. FIG. 9 shows a solid state imaging device according to a fourth embodiment, and is a modified example of the first embodiment shown in FIG. 2. In FIG. 9, a plurality of storage portions 40 and a plurality of charge drain portions 41 are provided between the picture photosensitive pixels P 1 -P n and shift gates 12. Each of the charge drain portions 41 comprises a gate 42 and a drain portion 43. By the constitution, even though an idling current occurs in the same manner of other pixels in the monitor photosensitive pixel, the idling current is compensated by the storage portions 40 and the charge drain portions 41. FIGS. 10-13 show various modifications with respect to an arrangement between the picture photosensitive pixels P 1 -P n and the monitor photosensitive pixel 11. A solid state imaging device according to a fifth embodiment shown in FIG. 10 has the same constitution as the solid state imaging device according to the first embodiment. In FIG. 10, shift gates 12 are provided corresponding to the monitor photosensitive pixel 11 and the picture photosensitive pixels P 1 -P n , respectively. In the figure, a region shown by an oblique line is a photosensitive pixel region. In this example, it is possible to clamp at a head of one line output. A solid state imaging device according to a sixth embodiment shown in FIG. 11 shows an example for clamping at the end of one line to the contrary with the solid state imaging according to the ninth embodiment. Accordingly, the monitor photosensitive pixel 11B is provided at a latter stage of the last picture photosensitive pixel P n . FIG. 12 shows a constitution of a solid state imaging device according to an seventh embodiment, In the figure, a monitor photosensitive pixel 11C passes through second and third picture photosensitive pixels P 2 and P 3 , and opposes to the shift gate 12. The solid state imaging device according to the seventh embodiment is an example of changing over AGC/gain by an output of the monitor photosensitive pixel 11C. In FIG. 13 for explaining operation of the seventh embodiment, a clamp/operating point is set during a time interval W 1 by outputs of the shaded pixels P 1 and P 2 . Then, an AGC/gain are changed over by an output W 2 of the monitor photosensitive pixel. The judgement of the gain and the set of clamp/operating point are simultaneously performed during the time interval W 3 by an output of the shaded pixel P 3 .

Claims: A solid state imaging device including a plurality of picture photosensitive pixels (P1-Pn) for generating first signal charges corresponding to an incident light amount; signal charge transfer means (13) for transferring in the order the first signal charges outputted from the picture photosensitive pixels (P1-Pn); and a monitor photosensitive pixel (11; 11B; 11C) for generating second signal charges in proportion to a mean value of the amount of light incident on the picture photosensitive pixels (P1-Pn); characterized by common output means (14) for converting both said first and second signal charges into first and second output signals, in which the first signal charges are generated in the picture photosensitive pixels (P1-Pn) and transferred by the signal charge transfer means (13), and the second signal charges are generated in the monitor photosensitive pixel (11; 11B; 11C) and transferred by the signal charge transfer means (13); and a common signal charge path including a CCD register and provided between said common output means (14) and said picture photosensitive pixels (P1-Pn) and said monitor photosensitive pixel (11; 11B; 11C); wherein said monitor photosensitive pixel (11; 11B; 11C) has a predetermined area extending along two sides of a region in which said picture photosensitive pixels (P1-Pn) are arranged so as to generate signal charges in proportion to said mean value of the amount of light incident on said picture photosensitive pixels (P1-Pn). The solid state imaging device according to claim 1, characterized by a clamping circuit (17) provided in the output means (14) for clamping the output signal which is generated by converting the first signal charges transferred from the signal charge transfer means (13); and a control circuit (18) for setting an upper limit or low limit voltage of the clamping circuit (17) on the basis of the output signal which is generated by said output means (14) by converting the second signal charges of the monitor phototsensitive pixel (11; 11B; 11C). The solid state imaging device according to claim 1 or 2, characterized by an amplifying circuit (16) for amplifying the output signal which is converted from the first signal charges transferred from the signal charge transfer means (13); and a control circuit (18) for setting a gain of the amplifying circuit (16) on the basis of the output signal which is converted from the second signal charges outputted from the monitor photosensitive pixel (11; 11B; 11C). The solid state imaging device according to any of claims 1 to 3, characterized in said that another monitor phototsensitive pixel and output buffer are provided in addition to said monitor photosensitive pixel (11; 11B; 11C) and output buffer (15).

Inventors: MAKOTO MONOI, MAKOTO, MONOI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H04N5
IPC codes: H04N5, H04N3