Barcode printer

Abstract: A universal controller interface for use in a number of different barcode printers is disposed between the printer's microprocessor and a number of the printer's input and output devices including the printhead. The controller includes a microprocessor interface that allows the controller to be used with various types of printer microprocessors. The controller also includes a printhead control circuit that allows the controller to be used with various types of printheads such as an intelligent thermal printhead or a non-intelligent thermal printhead. The controller also includes a programmable serial input/output port and a programmable baud rate generator so as to further increase its flexibility and use with various types of barcode printer input and output devices. A memory protection circuit of the controller allows various portions of the printer's random access memory to be protected if desired.

Description: The present invention is directed to a barcode printer having a processor with an associated memory that can be written to and read from with a memory protection means. BACKGROUND OF THE INVENTION Barcode printers are known to include interface circuitry between a microprocessor of the printer and the input and output devices of the printer that typically include a keyboard for data entry, a printhead for printing and a motor for advancing past the printhead a supply of the material to be printed on such as labels, tags, etc. In accordance with the present invention a controller of the printer includes a memory protection feature for the printer's RAM. More particularly, when an area of the printer's RAM stores at least one program according to which the printer's processor operates or other information to be protected, the present invention prevents a user from writing into that area of the RAM. The controller further includes means for disabling this memory protection feature to allow a new program or new information to be written into the previously protected area of the printer's RAM. Details of an illustrated embodiment of the invention will be more fully understood from the following description and from the drawing. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a block diagram of a barcode printer utilizing a controller in accordance with the present invention: Fig. 2 is a block diagram illustrating the microprocessor interface circuit depicted in Fig. 1; Fig. 3 is a block diagram illustrating a portion of the printhead data and control circuit depicted in Fig. 1; Fig. 4 is a block diagram illustrating a further portion of the printhead data and control circuit depicted in Fig. 1; Fig. 5 is a timing diagram illustrating the control signals generated for heat control in an intelligent printhead; Fig. 6 is a timing diagram illustrating the control signals generated for heat control in a non-intelligent printhead; Fig. 7 is a block diagram illustrating the serial input/output port depicted in Fig. 1; Fig. 8 is a block diagram illustrating the baud rate generator depicted in Fig. 1; Fig. 9 is a block diagram illustrating the memory protection circuit depicted in Fig. 1; and Fig. 10 is a timing diagram illustrating the operation of the baud rate generator depicted in Fig. 1. DESCRIPTION OF THE PREFERRED EMBODIMENT A barcode printer 10 is shown in Fig. 1 having a controller 12 in accordance with the present invention. The controller 12 provides an interface between the printer's microprocessor 14, with associated RAM 16 and ROM 18, and a number of the printer's input and output devices such as a thermal printhead 20. The microprocessor 14 controls the thermal printhead 20 through the controller 12 to print on a web of record members such as labels, tags or the like. The web of record members forms a supply that is advanced through the printer 10 by a stepper motor 22 or a D.C. motor that is also controlled by the microprocessor 14. Although a printhead and motor for advancing the supply are necessary for various types of barcode printers, other of the input and output devices depicted in Fig. 1, such as the display 24, keyboard 26, beeper 28, etc., are not necessary and will vary in accordance with the type of printer in which the controller 12 is used. The controller 12 is thus designed for flexibility so that it can be used in a very sophisticated, high-cost printer having all or most of the depicted input and output devices as well as in a lower-cost printer having-only a few of the input and output devices depicted. Because of this design, a low-cost printer having the controller 12 can be upgraded to provide additional functions without changing the basic architecture of the machine. For example, the controller 12 may be used in one barcode printer that prints data entered via a keyboard 26 in response to actuation by a user of a trigger key 30. The same controller 12 may also be used in a printer that does not include a keyboard 26 or a trigger 30 but that receives printing data from a host computer or the like via, for example, a RS 232 communication interface 32 coupled to the controller 12 wherein the data includes a print command for automatically controlling the barcode printer 10 to print. As shown in Fig. 1, the controller 12 includes a microprocessor interface 34 that allows the controller 12 to communicate with at least two types of microprocessors so that the controller 12 can be used in a barcode printer 10 having any one of the supported microprocessors. A memory protection circuit 36 is provided so as to prevent a user from writing data into a protected area of the RAM 16. This feature is desirable in printers that allow software for controlling the operation of the microprocessor 14 to be downloaded into the RAM 16 of the printer via the communication interface 32 from a host computer. A display interface 38, keyboard interface 40 and trigger interface 42 are provided to respectively interface between the microprocessor 14 and the display 24, keyboard 26 and trigger 30. A serial input/output port 44 is programmable so as to allow a variable the number of serial bits to be shifted, variations in the data direction and variations in the shift direction. Thus, the serial input/output port 44 is extremely flexible and can be used with a large variety of external serial data devices. A printhead protection circuit 44 is included in the controller 12 to prevent the printhead from burning out by insuring that the printhead elements are not energized too long to cause damage thereto. A general purpose input/output port 46 is provided wherein each pin of this port is independently programmable as to whether it is an input or an output. A printhead data and control circuit 48 controls the transfer of print data to the thermal printhead 20 as well as controlling the heater lines that are coupled to the thermal printhead 20 to control the amount of heat generated when a printhead element is energized. The heater control portion of the circuit 48 allows the controller 12 to be used with an intelligent thermal printhead or a non-intelligent thermal printhead. As is well-known in the art, an intelligent thermal printhead itself controls the length of time that each printhead element is energized in accordance with the energization history of that particular printhead element as well as the energization history of the surrounding printhead elements by selecting a particular one of a number of timing pulses supplied thereto. This is opposed to a non-intelligent printhead that relies on the printer's microprocessor 14 to control the energization period of the printhead element. A stepper motor control 50 is responsive to the output of a pulse width modulation generator 52 to generate the drive signals for the stepper motor 22 of the barcode printer 10. The pulse width modulation generator 52 also generates signals for use by a beeper interface 54 that drives a beeper 28. A dual universal asynchronous receiver/transmitter (DUART) 56 is clocked by the output of a baud rate generator 58 so as to be able to communicate with the communication interface 32. The baud rate generator is programmable so as to accept input clock pulses at different frequencies from a reference frequency generator 60 wherein each input frequency has an associate clock pulse pattern for generating output clock pulses at a desired frequency. The baud rate generator 58 utilizes asymmetrical division to generate the desired frequency from the available reference frequency. Internal status and control registers 62 are utilized to provide status information and to generate various interrupts for the microprocessor 14. The microprocessor interface 34 as shown in Fig. 2 allows the controller 12 to communicate with a microprocessor 14 of a first type or configuration such that the microprocessor communicates via an address bus and a separate data bus. An example of such a microprocessor is the Motorola MC68331 microprocessor hereinafter referred to as the '331 microprocessor. The interface 34 also allows the controller 12 to communicate with a microprocessor of a different type or configuration such as an Intel 80C186XL, hereinafter referred to as the '186 microporcessor, that utilizes a time multiplexed address-data bus. In order to minimize the number of pins necessary to communicate with these two diverse microprocessors, the microprocessor interface 34 includes groups of pins for communicating one set or type of signals between the controller 12 and one type of microprocessor; wherein the same group of pins is used to communicate a different set or type of signals between the controller 12 and a microprocessor of the other type. More particularly, the microprocessor interface 34 includes a mode multiplexer 70 having a mode pin associated with line 76 for receiving information identifying the type of microprocessor 14 coupled to the controller 12. The multiplexer 70 also includes a number of pins associated with a bus 72 which forms in a '186 microprocessor mode a multiplexed address-data bus for the signals ADO-AD15. In the '331 microprocessor mode, the bus 72 associated with these same pins forms a data bus for inputting and outputting only data represented by the signals D0-D15. A number of pins associated with the multiplexer 70 are coupled to a bus 74 which carries address signals representing A16-A19 in both the '186 microprocessor mode and the '331 microprocessor mode. The microprocessor interface 34 also includes a latch 72. In the '186 microprocessor mode a bus 78 forms an output bus connected to a group of pins of the latch 72 to provide the latched addresses A1L-A6L and A12L-A15L. However, in the '331 microprocessor mode the bus 78 forms an input bus coupled to the same pins of the latch 72 for providing addresses A1-A6 and A12-A15 that are input to the controller 12. A bus 80 is used to provide the latched addresses A0L, A7L-A11L and A16L-A19L that are output from the controller 12 in the '186 microprocessor mode only. Further, in the '186 microprocessor mode, the '186 microprocessor provides a latch enable signal, ALE that is coupled to the latch 72 to enable the addresses to be latched therein. The latch 72 is also responsive to a mode signal output from the multiplexer 70 on a line 82 to determine whether the latch is to accept information input on bus 78 or to output information on bus 78 and bus 80. In the input mode, the latch 72 transfers the above-described address information from the '331 microprocessor from bus 78 to a bus 84 for the internal use by the controller 12. In the output mode, the latch 72 latches the address information on bus 84 and a bus 86 to the output buses 78 and 80. It is noted that other pins of the microprocessor interface 34 may be used to carry different information between the controller 12 and the microprocessor 14 depending upon the mode. Further, the microprocessor interface 34 does include a number of pins dedicated solely to the use of only one type of microprocessor. The printhead data loading portion of the printhead control circuit 48 is depicted in Fig. 3. As shown therein, a double buffered parallel to serial shift register 90 includes a first buffer into which the parallel data on bus 88 is first shifted into and a second buffer into which the data from the first buffer is transferred in parallel, the data being serially shifted out from the second buffer and coupled to the thermal printhead 20 via a line 96. A counter 92 is coupled to the output of the shift register 90 so as to count the number of data bits representing thermal printhead elements to be energized to print a line of information. The data in the counter 92 is coupled back to the microprocessor 14 via the data bus 88 so that the microprocessor 14 can use the counter information for energy management and printhead monitoring functions. An output on line 98 from the double buffered shift register 90 represents the empty or full status of the first buffer so that when the status of the first buffer is empty, a direct memory access request is asserted so as to provide an interrupt for the microprocessor 14 indicating that the shift register 90 can accept data for the next line to be printed. The empty/full status line 98 is also coupled to an internal status register 94 for storage so that the microprocessor 14 can poll the status register 94 to determine the state of the first buffer of the double buffered shift register 90. The printhead heater control portion of the circuit 48 of the controller 12 is depicted in Fig. 4. As shown therein, a square wave register 100 is provided to determine whether the printhead logic will provide an output control for an intelligent thermal printhead or a non-intelligent thermal printhead. When the square wave register 100 is programmed with a zero value, the circuit provides the heat control outputs H0, H1, H2, H3 and H4 for an intelligent printhead from respective printhead heater registers 102-106. The heat control signals H0-H4 are each active low signals the length of which represents a selectable power level in the form of a selectable energization period for the elements of the thermal printhead 20 to control the amount of heat generated by a print element to print a dot. For example, the control signal H0 may be formed of an 800 microsec. active low signal; the control signal H1 may be formed of a 600 microsec. active low signal; the H2 control signal may be formed of a 500 microsec. active low signal; the H3 control signal may be formed of a 400 microsec. active low signal whereas the H4 control signal may be formed of a 200 microsec. active low signal. Because each of the printhead heater registers 102-106 is of the same configuration, only the register 102 will be described in detail. As shown for the register 102, when operating in accordance with the intelligent printhead mode, a number representing the length of the active low period for the H0 control signal, i.e. 800 microsec. in the above example, is written from the data bus 88 into a register 108. A clock signal on a line 110 clocks a counter 112 to count during which time the output of the register 102 is low. The register output goes high when the value in the counter 112 is equal to the value stored in the register 108 as determined by a comparator 114. The registers 103-106 similarly generate the control signals H1-H4. For non-intelligent thermal printhead control, the square wave register 100 is programmed with a non-zero value to control the period of a square wave output from the register 102 on the line associated with the control signal H0 and the period of the square wave's compliment output from the register 103 on the line associated with the control signal H1. This H0 control signal controls the amount of heat generated for one-half of the non-intelligent printhead whereas the H1 control signal controls the amount of heat generated for the other half of the non-intelligent printhead. Although the non-zero value in the register 100 represents the period of the square wave signals Ho and H1, the total length of the HO and H1 signals is determined by the number, for example 800 microsec., stored in the register 10. A line interval counter 116 is loaded with a value representing the number of clocks signals to be used to synchronize the loading and heating of the printhead 20. The counter 116 generates a signal, PH LATCH, on a line 122 and a complimentary signal, LINE INTERVAL OUT, on a line 123 when a line interval counter equals a count of one. The PH LATCH signal is used to latch the print data to the thermal printhead 20; whereas the LINE INTERVAL OUT signal is used to indicate that the controller 12 is ready to process the data for the next line to be printed. It is noted that the LINE INTERVAL OUT signal on line 123 can be used directly or the signal can be applied to an interrupt generator 120 to generate an interrupt. An internal control register 118 is further provided to generate a printhead start signal that begins the synchronized printhead heating cycle. Figs. 5 and 6 are timing diagrams illustrating the control signals H0-H4 generated for an intelligent printhead and the signals H0 and H1 generated for a non-intelligent printhead as described above as well as other printhead control signals. The serial input/output port 44 of the controller 12 is shown in Fig. 7. The serial input/output port includes an output parallel to serial shifter 130 that receives data on the parallel data bus 88 to be shifted out serially on a line 136. The serial input/output port 44 also includes an input serial to parallel shifter 132 that receives serial data on a line 138 to be shifted in to the port 44 so as to be coupled to the parallel data bus 88. A data count register 134 controls the output shifter 130 and the input shifter 132 in response to data received from the bus 88, the data representing the number of bytes to be serially shifted; the data direction i.e. whether the data is to be shifted out from the port 44 or shifted into the port 44; and the shift direction i.e., whether the registers 130 and 132 respectfully shift from the most significant bit to the least significant bit or from the least significant bit to the most significant bit. In response to the data received from the bus 88, the data count register 134 generates clock signals on line 140 if data is to be shifted out from the port 44 or it generates clock signals on a line 142 to the shifter 132 if data is to be shifted into the port 44. A mode signal on the respective lines 144 and 146 directs the respective shifter 130 or 132 to shift either the most significant bit first or the least significant bit first. The data count register also generates a chip select signal 148 in response to data being written to the data count register from the bus 88 and also generates a serial synchronization clock signal on a line 150. It is noted that the data count register 134 can be read to determine the status of a data transfer by the microprocessor polling the register to see of the count contained therein has expired indicating the completion of the data transfer. The programmable baud rate generator 58 as shown in Fig. 8 generates various operating frequencies for the Duart 56 from an input clock signal received on line 152 from the reference frequency generator 60. The frequency that must be provided to the Duart 56 is 16 times the desired baud rate. Therefore, to support a baud rate of 19.2K, the minimum frequency that can be input to the Duart 56 is 16 x 19.2KHz = 307.2KHz. All standard baud rates from 75 baud to 19.2K baud can be generated from 307.2KHz utilizing the baud rate generator 58. Because the required 19.2K baud rate should be supported when the microprocessor 14 is operating at a low operating frequency which is approximately 524KHz for one type of microprocessor and 500KHz or 625KHz. for another type of microprocessor, neither microprocessor can provide clock signals that are integer multiples of 307.2KHz at their lower operating frequencies. However, an approximately correct frequency can be generated by the programmable baud rate generator 58 by performing asymmetric division. An asymmetric divider 154 of the baud rate generator 58 performs the asymmetric division by forming each output clock pulse from a number of input clock pulses in a predetermined pattern. Each input frequency requires a different division pattern 156 to provide approximately the same basic output frequency. The asymmetric divider 154 is responsive to the input frequency, which is set in a frequency register 158 by the microprocessor 14, to select the appropriate clock divisors to generate the particular division pattern that is required to generate the output clock pulses of a desired frequency from the clock input pulses. For example, where the frequency of the input clock pulses on line 152 is 500KHz, a 13:8 divisor circuit of the divider 154 produces a 307.69KHz output clock signal (500KHz ÷ 13/8 = 307.69KHz). The 13:8 division utilizes either one or two input clock cycles in the following pattern sequence: 2 - 2 - 1 - 2 - 2 - 1 - 2 - 1 repeating continuously over each 13 input clock cycles to produce one output clock cycle. For a 524KHz input clock signal, a 17:10 divisor circuit is utilized to produce a 308.46KHz clock which is within .34% of the desired 307.2KHz rate. The 17:10 division uses either one or two input clock cycles in the following pattern: 2 - 2 - 1 - 2 - 2 - 1 - 2 - 2 - 2 - 1, repeating continuously over each 17 input clock cycles to produce one output clock cycle. For an input clock pulse frequency of 625KHz, a 64:63 divisor circuit is used to produce a 615.23KHz clock which is within 0.13% of an optimum 614.4KHz rate. The 64:63 division utilizes a repeating pattern of 64 input clock pulses with each input clock pulse, except for the 64th clock pulse, producing an output clock pulse. Therefore, each group of 64 input clock pulses produces 63 output clock pulses. Fig. 10 illustrates the various clock patterns generated for reference frequencies of 500KHz, 524KHz and 625KHz as discussed above. The memory protection circuit shown in Fig. 9 allows an area of a memory, in particularly the RAM 16, to be protected so that information cannot be accidentally written over the information stored in the protected area. The memory protection circuit 36 includes a protection limits register 160 into which is written the high limit of the address range to be protected and the lower limit of the address range to be protected. The address of the RAM 16 that is being written to is compared to the high limit value and to the low limit value by respective comparators 162 and 164 to determine whether the write address is within the protected address range. If it is not, that address of the RAM 16 may be written to. However, if the write address is within the protected address range, the memory protection circuit 36 blocks the write signal so as to prevent the protected area of the RAM from being written to. The memory protection circuit 36 may be disabled in order to allow a new program to be downloaded, for example from the communication interface 32 into the RAM 16. The memory protection circuit 36 is disabled by a password followed by simultaneous actuation of particular keys of the keyboard 26 with the keyboard interface controller 40 in a write protection disable mode. This sequence of events informs the microprocessor 14, through an internal status register 62, that the write protection has been disabled. Once the write protection has been disabled, the previously protected area of the RAM 16 can be written into. In order to again protect a new area of the RAM 16, new high limit and lower limit values are written into the register 160 after the next system reset. The controller 12 is very flexible so that it can accommodate different types of printer microprocessors 14, different types of printheads 20, various types of serial input and output devices to be used in the printer 10 and various software storage schemes with the software being protected in the printer's memory. Thus, the controller 12 of the present invention can be used in various types of printers without change thereto so as to decrease the development time and costs associated with new barcode printers.

Claims: A barcode printer having a processor with an associated memory (16) that can be written to and read from with a memory protection means (36) characterized by: a programmable register (160) for storing information representing a range of addresses in said memory defining the area of said memory to be protected and means (162, 164) for comparing a write address defining a location of said memory to be written to with said stored range of addresses, said comparing means (162, 164) preventing information from being written to said location in said memory if said write address is within said range of addresses represented by information stored in said programmable register (160).

Inventors: HELMBOLD JAMES E, LONG DAVID N, RILEY DAVID W, STERN MITCHELL G, HELMBOLD, JAMES E., LONG, DAVID N., RILEY, DAVID W., STERN, MITCHELL G.
Applicants: MONARCH MARKING SYSTEMS INC, MONARCH MARKING SYSTEMS, INC.
Application year: 1994
Main classification: G06K15
IPC codes: G06K1