Trench capacitor cell structure of dram

Abstract: The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench (22) is formed in the surface of a substrate such that it is connected to a conductive region (18) for a transistor. The structure is characterized by comprising a capacitor electrode (5) formed on the inner peripheral surface of the trench (22) and having its upper edge portion located below the conductive region (18), an insulating layer (9) projecting inward of the trench at least from the upper edge portion of the capacitor electrode (5) to the conductive region (18), thereby narrowing the diameter of the trench, a capacitor insulating film (10) coated on the capacitor electrode (5), and a capacitor electrode (11) filling the trench and contacting the capacitor insulating film (10). The insulating layer (9) can be produced by selectively oxidizing part of a polysilicon layer (5) or part of the sustrate.

Description: This invention relates to a semiconductor device, more particularly to a trench capacitor structure of a DRAM (Dynamic Random Access Memory), and also to a method for manufacturing the structure. An example of a DRAM having a sheath-plate type trench capacitor is known from "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring" published in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 8, August 1988, and written by Toru KAGA, Yoshifumi KAWAMOTO, Tokuo KURE, Yoshinobu NAKAGOME, Masakazu AOKI, Hideo SUNAMI, Tohachi MAKINO, Nagatoshi OHKI and Kiyoo ITOH. Reference is also made to EP-A-0 287 056, JP-A-2 009 166 and EP-A-0 234 891. FIG. 1 is a cross sectional view, showing a conventional sheath-plate type trench capacitor. As is shown in FIG. 1, a trench is formed in a semiconductor substrate 21 in contact with a field oxide film 1. An area which includes a trench inner wall oxide film 4, a silicon oxide/silicon nitride (SiO 2 /SiN) film 10, a polysilicon film 14, a diffusion layer 16 and part of the substrate 21 serves as a gate control diode. When a potential has been applied to the polysilicon film 14 (or to a polysilicon film 11 formed in a deep portion of the trench), a depletion layer grows in the vicinity of a peripheral portion of the trench inner wall oxide film 4, thereby forming an inversion layer such that it extends from the diffusion layer 16 along the outer periphery of the trench. As a result, the amount of a junction leak current between the substrate 21 and the diffusion layer 16 contacting the polysilicon film 14 increases. To reduce the influence of the potential applied to the polysilicon films 11 and 14, it is necessary to make the oxide film 4 thick. However, increasing the thickness of the oxide film 4 inevitably reduces the area of a capacitor insulating film and hence the capacitance of the trench capacitor. In the conventional structure, the potential applied to the polysilicon film filled in the trench increases the junction leak current between the substrate and the diffusion layer contacting the polysilicon film. To avoid this, it is necessary to reduce the capacitance of the capacitor to some extent. Actually, however, the capacitance is excessively reduced since an increase in junction leak current is prevented by increasing the thickness of the trench inner wall oxide film. It is the object of the invention to provide a method of manufacturing a highly reliable semiconductor device having a sufficient trench capacitor capacitance and a small junction leak current. This object is achieved by a method as defined in claim 1. In the invention that portion of the insulating layer, which extends from the upper edge portion of the first capacitor electrode to the conductive region and in which junction leak can easily occur, is formed thick such that it projects inward of the trench, thereby interrupting at that portion continuous formation of an inversion layer extending along the outside of the trench. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross sectional view, showing a conventional sheath-plate type trench capacitor; FIG. 2 is a cross sectional view, showing a trench capacitor employed in a DRAM according to a first embodiment of the invention; FIGS. 3 - 6 are views, useful in explaining essential steps of a method for forming the structure shown in FIG. 2; FIG. 7 is a cross sectional view, showing a trench capacitor employed in a DRAM according to a second embodiment of the invention; FIGS. 8 - 10 are views, useful in explaining essential steps of a method for forming the structure shown in FIG. 7; FIG. 11 is a cross sectional view, showing a step for obtaining a structure shown in FIG. 12; FIG. 12 is a cross sectional view, showing essential part of a sheath-plate type trench capacitor employed in a DRAM not being part of the invention; FIG. 13 is a cross sectional view, showing a step for obtaining a structure shown in FIG. 14; FIG. 14 is a cross sectional view, showing essential part of a sheath-plate type trench capacitor employed in a DRAM according to a third embodiment of the invention; FIG. 15 is a cross sectional view, showing a first structure of the substrate of a sheath-plate type trench capacitor of a DRAM corresponding to the DRAM of FIG. 2 but more specific than the same; FIG. 16 is a cross sectional view, showing a first structure of the substrate of a sheath-plate type trench capacitor of a DRAM corresponding to the DRAM of FIG. 7 but more specific than the same; FIG. 17 is a cross sectional view, showing a second structure of the substrate of a sheath-plate type trench capacitor of a DRAM corresponding to the DRAM of FIG. 2 but more specific than the same; and FIG. 18 is a cross sectional view, showing a second structure of the substrate of a sheath-plate type trench capacitor of a DRAM corresponding to the DRAM of FIG. 7 but more specific than the same. FIG. 2 is a cross sectional view, showing a trench capacitor employed in a DRAM according to a first embodiment of the invention. As is shown in FIG. 2, the source/drain regions 18 of a memory cell transistor (MOS transistor) are formed in the p-type surface of a monocrystal silicon semiconductor substrate 21. Reference numeral 17 denotes the gate electrode of the transistor. A trench 22 is formed in a portion of the substrate 21 adjacent to one of the source/drain regions 18. A polysilicon film 5 is formed in an inner peripheral portion of the trench 22. The film 5 has an upper edge portion located below the source/drain region 18, and serves as a first capacitor electrode. A SiO 2 film 9 extends from the upper edge portion of the film 5 to the source/drain region 18 such that it projects inward, thereby reducing the diameter of the trench 22. A SiO 2 film 4 having a thickness thinner than the film 9 extends therefrom and covers the inner periphery of the trench 22. A SiO 2 /SiN film 10 covers the polysilicon film 5 and serves as a capacitor insulating film. A polysilicon film 11 which serves as a second capacitor electrode is filled in the trench 22 such that it contacts the SiO 2 /SiN film 10 and the drain region 18. FIGS. 3 - 6 are views, useful in explaining essential steps of a method for forming the sheath-plate type trench capacitor shown in FIG. 2. Referring first to FIG. 3, the trench 22 which has a depth of 5 µm and a diameter of 0.5 µm is formed in the p-type surface region of the monocrystal silicon substrate 21 which is adjacent to the field oxide film 1, using a SiN film 3 as a mask. Then, the SiO 2 film 4, which has a thickness of 20 nm, is formed on the inner periphery of the trench 22 by oxidation at high temperature. That part of the SiO 2 film 4 which is formed on the bottom of the trench 22 is selectively etched by unisotropic etching. Subsequently, the polysilicon film 5 with a thickness of 50 nm, a SiN film 6 with a thickness of 12 nm and a SiO 2 film 7 with a thickness of 50 nm are deposited in this order by the CVD method. The polysilicon film 5 serving as a capacitor electrode is doped with phosphorus of high density while or after the film 5 is formed. Thereafter, an exposed portion of the SiO 2 film 7 is removed by a buffer HF aqueous solution, using as a mask a resist layer 8 having a thickness of 3 µm and formed on the bottom of the trench. Then, as is shown in FIG. 4, the resist layer 8 is removed, and an exposed portion of the SiN film 6 is removed by a hot H 3 PO 4 aqueous solution, using as a mask the SiO 2 film 7 shown in FIG. 3. Subsequently, the SiO 2 film 7 is removed by a buffer HF aqueous solution. The resultant structure is subjected to a high temperature thermal oxidation treatment, thereby oxidizing a shallow portion of the trench exposed after removing the SiN film 6, i.e., an upper edge portion of the polysilicon film 5. As a result, a SiO 2 film 9 having a thickness of 50 nm is formed. The remaining SiN film 6 is removed by the hot H 3 PO 4 aqueous solution. The polysilicon film 5 may be doped in this stage. Then, a SiN film (10) having a thickness of 10 nm is deposited by the CVD method, and a surface portion thereof is oxidized by high temperature oxidation, thereby forming a capacitor insulating film 10 of high quality. Alternatively, the SiN film 6 may not be removed after forming the SiO 2 film 9, and used as the capacitor insulating film. Subsequently, a polysilicon film 11 having a thickness of 400 nm is formed in the trench by the CVD method, thereby almost completely filling the trench. The film 11 thus formed serves as another capacitor electrode. As in the case of the polysilicon film 5, phosphorus is injected into the polysilicon film 11. Thereafter, the polysilicon film 11 is selectively etched back by isotropic dry etching to have a thickness of 4 µm from the bottom of the trench. Then, a surface portion of the polysilicon film 11 is oxidized by high temperature oxidation, forming a SiO 2 film 12 with a thickness of 10 nm. Then, as is shown in FIG. 5, an exposed portion of the SiO 2 /SiN film 10 is selectively etched by the isotropic dry etching. Subsequently, that surface portion of the SiO 2 film 9 which extends to the upper surface of the polysilicon film 11 is selectively removed by unisotropic etching, together with the SiO 2 film 12. Thereafter, as is shown in FIG. 6, the resultant structure is coated with a resist layer 13, an opening is formed by a lithography technique to expose a portion of the trench, and the side wall oxide film 4 is removed by the use of the buffer HF aqueous solution. Thereafter, a structure as shown in FIG. 2 is obtained. Specifically, the resist layer 13 is removed, a highly doped polysilicon film 14 is filled in the trench, and that portion of the polysilicon film 14 which extends from the surface to the lower end of the SiN film 3 is removed by the isotropic dry etching. Then, a surface portion of the polysilicon film 14 is oxidized by thermal oxidation, thereby forming a SiO 2 film 15 with a thickness of 30 nm. Phosphorus or arsenic injected in the polysilicon film 14 is diffused to the outside of the trench, thereby forming a diffusion layer 16. Subsequently, the SiN film 3 is selectively etched by the isotropic dry etching. Thereafter, a memory cell of the DRAM is formed by a known technique. Specifically, a gate electrode 17 is selectively formed on the SiO 2 film 15, and source/drain regions 18 one of which contacts the diffusion layer 16 are formed (FIG. 2). In the above-described embodiment, the SiO 2 film 9 which is located just below the diffusion layer 16 connecting the polysilicon film 14 to the substrate 21 (in other words, the film 9 which extends from an upper edge portion of the polysilicon film 5 serving as a capacitor electrode, to the diffusion layer 16), and in which junction leak will occur, is formed to have a thickness thicker than the SiO 2 film 4 which extends to the bottom of the trench. As a result, an inversion layer along the outside of the trench is hard to form in the vicinity of the film 9. This means that the thick SiO 2 film 9 prevents an inversion layer formed along the outside of the trench from being connected to the diffusion layer 16 by the influence of a potential applied to the polysilicon film 14 (or 11). Further, since in the embodiment, only the SiO 2 film 9 is formed thick and the substantial area of the capacitor located under the film 9 is not reduced, the amount of the junction leak can be restrained without reducing the capacitance of the trench capacitor. FIG. 7 is a cross sectional view, showing a sheath-plate type trench capacitor employed in a DRAM according to a second embodiment of the invention. As is shown in FIG. 7, source/drain regions 18 for a memory cell transistor (MOS transistor) are formed in the p-type surface of the monocrystal silicon semiconductor substrate 21. Reference numeral 19 denotes a gate electrode for the transistor. A trench 23 is formed in that portion of the substrate 21 which is located adjacent to one of the source/drain regions 18, and a polysilicon film 5 serving as a first capacitor electrode is formed on the inner peripheral wall and the bottom of the trench 23 such that an upper edge portion thereof is located below the source/drain region 18. A thick SiO 2 film 9 projects inward from the peripheral wall of the trench such that it narrows the diameter of the trench 23 in an area ranging from the upper edge portion of the polysilicon film 5 to the source/drain region 18. Reference numeral 27 denotes a diffusion layer formed around the trench 23 as a result of diffusion of an impurity injected in the polysilicon film 5. A SiO 2 /SiN film 10 serving as a capacitor insulating film is formed on the polysilicon film 5. A polysilicon film 11 serving as a second capacitor electrode is filled in the trench 23 such that it contacts the SiO 2 /SiN film 10 and also the drain region 18. FIGS. 8 - 10 are views, useful in explaining essential steps of a method for forming the structure shown in FIG. 7. Elements similar to those in the first embodiment are denoted by corresponding reference numerals. As is shown in FIG. 8, a trench 23 having a depth of 5 µm is formed in the p-type surface of a monocrystal silicon substrate 21. Then, a polysilicon film 5 having a thickness of 60 nm, a SiN film 6 having a thickness of 12 nm and a SiO 2 film 7 having a thickness of 50 nm are deposited by the CVD method in this order. Subsequently, an exposed portion of the SiO 2 film 7 is removed by a buffer HF aqueous solution, using as a mask a resist layer 8 having a thickness of 3 µm and formed on the bottom of the trench. Then, as is shown in FIG. 9, the resist layer 8 is removed, and an exposed portion of a SiN film 6 is removed by a hot H 3 PO 4 aqueous solution, using as a mask the SiO 2 film 7. Subsequently, the SiO 2 film 7 is removed by the buffer HF aqueous solution. At this time, only that portion of the SiN film 6 having been located under the SiO 2 film remains. Then, that exposed portion of the polysilicon film 5 on which the SiN film 6 does not remain is oxidized by thermal oxidation, thereby forming a SiO 2 film 9 with a thickness of 50 nm. The SiN film 6 is removed by the hot H 3 PO 4 aqueous solution. The polysilicon film 5 may be doped with phosphorus or arsenic of high density in this stage. Phosphorus or arsenic is diffused from the polysilicon film 5 to the outside of the trench, thereby forming a diffusion layer 27. Then, as is shown in FIG. 10, a SiN film (10) having a thickness of 10 nm is deposited by the CVD method, and a thin surface portion thereof is oxidized by high temperature oxidation, thereby forming a capacitor insulating film 10 of high quality. Alternatively, the SiN film 6 may not be removed after forming the SiO 2 film 9, and used as the capacitor insulating film. Subsequently, a polysilicon film 11 having a thickness of 400 nm is formed in the trench by the low pressure CVD method such that it almost completely fills the trench. As in the case of the polysilicon film 5, phosphorus is injected into the polysilicon film 11. Thereafter, the polysilicon film 11 is selectively etched back by isotropic dry etching to have a thickness of 4.5 µm from the bottom of the trench. Then, a surface portion of the polysilicon film 11 is oxidized by high temperature oxidation, thereby forming a SiO 2 film 12 with a thickness of 10 nm. Thereafter, a memory cell of the DRAM shown in FIG. 7 is formed in a process similar to that employed in the first embodiment. Specifically, the trench is filled with a polysilicon film 14, a surface portion of the polysilicon film 14 is oxidized (thereby forming a SiO 2 film 15), a gate electrode 19 is selectively formed on the SiO 2 film 2, and source/drain regions 18 are formed such that one of the regions 18 contacts the diffusion layer 16. FIG. 12 is a cross sectional view, showing essential part of a sheath-plate type trench capacitor employed in a DRAM not being part of the invention. FIG. 11 is a cross sectional view, showing a step for obtaining the structure shown in FIG. 12. Elements similar to those employed in the first or second embodiment are denoted by corresponding reference numerals. Referring to FIG. 11, a trench with a depth of 5 µm and a diameter of 0.5 µm is formed in the p-type surface of a monocrystal silicon substrate 21. Then, a SiN film 6 with a thickness of 12 nm and a SiO 2 film 7 with a thickness of 50 nm are deposited in this order by the CVD method. Subsequently, the SiO 2 film 7 is removed by a buffer HF aqueous solution, using as a mask a resist layer 8 having a thickness of 3 µm and formed on the bottom of the trench. Then, as is shown in FIG. 12, the resist layer 8 is removed, and an exposed portion of the SiN film 6 is removed by a hot H 3 PO 4 aqueous solution, using as a mask the SiO 2 film 7. Subsequently, the SiO 2 film 7 is removed by a buffer HF aqueous solution. Then, that portion of the silicon substrate which has been exposed after removing the SiN film 6 is subjected to high temperature oxidation, thereby forming a SiO 2 film 9 having a thickness of 50 nm. The SiO 2 film 6 is then removed by the hot H 3 PO 4 aqueous solution. Subsequently, an exposed portion of the substrate in the trench is doped with phosphorus or arsenic of high density to form a diffusion layer 27. Thereafter, as in the case of FIG. 10, a SiN film (10) with a thickness of 10 nm is deposited by the CVD method, a shallow surface portion thereof is oxidized, thereby obtaining capacitor insulating film 10 of high quality. Thereafter, a memory cell of the DRAM can be formed in a process similar to that employed in the first or second embodiment. FIG. 14 is a cross sectional view, showing essential part of a sheath-plate type trench capacitor employed in a DRAM according to a third embodiment of the invention, while FIG. 13 is a cross sectional view, showing a step for obtaining the structure shown in FIG. 14. Elements similar to those employed in the first embodiment are denoted by corresponding reference numerals. Referring to FIG. 13, a trench with a depth of 5 µm and a diameter of 0.5 µm is formed in the p-type surface of a monocrystal silicon substrate 21. Then, a polysilicon film 5 with a thickness of 60 nm and a SiN film 6 with a thickness of 12 nm are deposited in this order by the CVD method. The polysilicon film 5 is doped with phosphorus or arsenic of high quality while or after it is formed. Phosphorus or arsenic injected in the film 5 diffuses into the substrate in a heating step performed later. Subsequently, a shallow surface portion of the SiN film 6 is oxidized, and a polysilicon film 11 with a thickness of 400 nm is deposited in the trench by the CVD method. Then, the polysilicon film 11 is selectively etched back by isotropic dry etching to have a thickness of 3 µm from the bottom of the trench, and en exposed portion of the SiN film 6 is removed by the use of a hot H 3 PO 4 aqueous solution. Subsequently, as is shown in FIG. 14, an exposed portion of the polysilicon film 5 is completely oxidized by high temperature oxidation, forming a SiO 2 film 9. At the same time as the oxidation of the polysilicon film 5, part of the substrate may be oxidized. An upper surface portion of the polysilicon film 11 is oxidized, thereby forming a SiO 2 film 12 (not shown). Then, that portion of the SiO 2 film 9 which extends to the upper surface of the polysilicon film 11 is removed by unisotropic etching. The SiO 2 film 12 is removed together with the SiO 2 film 9. Thereafter, a memory cell of the DRAM can be formed in the same process as employed in the second embodiment. The second through third embodiments can provide the same advantage as obtained by the first embodiment. That is, in the sheath-plate type trench capacitor structure, the portion of an oxide film which extends from an upper edge portion of a capacitor electrode formed on the trench inner wall to the conductive region (drain region 18) of the transistor is formed thick such that it projects inward of the trench, so as to prevent that portion from changing to an inversion layer. Therefore, a junction leak current can be reduced without reducing a substantial area of the capacitor located below that portion. In the above embodiments, the monocrystal silicon semiconductor substrate 21 may be a p-type well region 211 formed on an n-type substrate 212 as shown, for example, in FIG. 15 corresponding to FIG. 2 or FIG. 16 corresponding to FIG. 7; or may be a p-type region 211 formed on a p-type substrate 213 as shown, for example, in FIG. 17 corresponding to FIG. 2 or FIG. 18 corresponding to FIG. 7. In the latter case shown in FIG. 17, an n-type region 31 for supplying a potential and connecting another trench (not shown) is provided in the p-type substrate 213 such that it contacts the polysilicon film 5 serving as a first capacitor electrode. The diffusion layer 27 as shown in FIGS. 7, 12 and 18 has the same function as the n-type region 31 mentioned above. The n-type region 31 may be a diffusion layer formed by diffusing an impurity from the bottom of the trench to the substrate, or may be a diffusion layer beforehand embedded in the substrate.

Claims: A method of manufacturing a trench capacitor for a dynamic random access memory (DRAM) cell, comprising the steps of: forming in a semiconductor substrate (21) a trench (22, 23); forming a conductive film (5) on wall surfaces of the trench (22, 23); coating an oxidation resistant material (6) in the trench (22, 23) except for the conductive film (5) on the upper edge portion thereof; and oxidizing the conductive film (5) on the upper edge portion of the trench (22, 23), thereby selectively forming an insulating layer (9) projecting inward of the trench (22, 23). The method according to claim 1, further comprising the step of forming an insulating film (4) on an inner peripheral surface of the trench before forming the first conductive film (5), and wherein the conductive film (5) is formed on the insulating film (4) and on the bottom of the trench (22). The method according to claim 1, characterized by further comprising the step of oxidizing, at the same time as forming the insulating layer (9), that portion of the semiconductor substrate (21) which is located in the vicinity of the insulating layer (9). The method according to claim 1, characterized by further comprising the steps of: forming a conductive diffusion region (18) for a cell transistor of the DRAM, in a portion of the substrate (21) adjacent to the upper edge portion of the trench (22, 23); removing a portion of the insulating layer (9) which is located in the vicinity of the upper edge portion of the trench (22, 23); and filling the trench (22, 23) with a conductive layer (11, 14); wherein the conductive layer (11, 14) is electrically connected to the conductive region (18). The method according to claim 4, further comprising the steps of: coating a capacitor insulating film (10) on those portions of the conductive film (5) which remain unoxidized. The method according to claim 5 wherein the unoxidized portion of said conductive film (5) forms a first electrode of said trench capacitor; and said conductive layer (14) forms a second electrode of said trench capacitor. The method according to claim 6, wherein said conductive layer (14) is insulatively spaced from the unoxidized portion of said conductive film (5) by said oxidation resistant material (6). The method according to claim 6, comprising the further steps of: removing said oxidation resistant material (6) after oxidizing said conductive film (5); and forming said capacitor insulating film (10) at least on the unoxidized portion of said conductive film (5) prior to forming said conductive layer (14), wherein said capacitor insulating film (10) insulatively spaces said conductive layer (14) from said unoxidized portion of said conductive film (5). The method according to claim 8, wherein said capacitor insulating film (10) comprises a silicon dioxide (SiO 2 )/silicon nitride (Si 3 N 4 ) film. The method according to claim 6, wherein said conductive film (5) and said conductive layer (14) each comprise a doped polycrystalline silicon film. The method according to claim 6, wherein said conductive layer (14) is electrically coupled to said diffusion region (18) of said transistor by a diffusion layer (16) formed by outdiffusing impurities from said conductive layer (14). The method according to claim 6, wherein said conductive film (5) is formed directly on portions of said semiconductor substrate (21) exposed by said trench (23). The method according to claim 6, wherein the step of forming said conductive layer comprises: forming a first conductive layer (11) in said trench (22, 23); etching back said first conductive layer (11); etching a portion of said insulating layer (9) to expose said semiconductor substrate (21); and forming a second conductive layer (14) which electrically connects said first conductive layer (11) to the exposed portion of said semiconductor substrate (21). The method according to claim 1, wherein said coating step comprises the steps of: forming an oxidation resistant material (6) on said conductive lining (5); forming a conductive layer (14) on said oxidation resistant material (6); etching back said conductive layer (14) to a level in said trench (22, 23); etching the oxidation resistant material (6) exposed by the etching back of said conductive layer (14) to expose a portion of said conductive film (5) at an upper portion of said trench (22, 23);

Inventors: IBA JUNICHIRO, KOHYAMA YUSUKE, IBA, JUNICHIRO, KOHYAMA, YUSUKE, IBA, JUNICHIRO, C/O INT.PTY.DIV., K.K. TOSHIBA, KOHYAMA, YUSUKE, C/O INT.PTY.DIV., K.K. TOSHIBA
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1994
Main classification: H01L27
IPC codes: H01L27, H01L21