Chemical mechanical planarization of shallow trenches in semiconductor substrates

Abstract: A new method for planarization of shallow trenches is presented. Shallow trenches (11-14) are patterned into a semiconductor substrate (5) that has been coated with a layer of silicon nitride (7). A conformal coating of oxide (10) is deposited onto the wafer to fill the trenches. A thin layer (15) of etch-stop silicon and a second layer (20) of oxide are then deposited. The second layer (20) of oxide is patterned with a filler mask (26) using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.

Description: BACKGROUND OF THE INVENTION This invention relates to a method of fabricating semiconductor devices and more specifically to a planarization process for use during the fabrication of semiconductor devices. Very Large Scale Integrated (VLSI) and Ultra Large Scale Integration (ULSI) circuits utilize a variety of devices having different feature sizes or device dimensions. Such devices include, but are not limited to, transistors, diodes, capacitors, resistors and wires. The minimum state of the art device dimensions have shrunk to the submicron level. Some devices may have submicron feature sizes while others may simultaneously have much greater feature sizes. Shallow trenches of constant height and varying widths are used to isolate individual devices. These trench widths can vary greatly. These trenches are typically filled with a dielectric material, such as silicon oxide. Because of the complex topography, especially when shallow trenches of greatly varying widths are used, a problem often encountered is how to achieve a uniform oxide fill, in those trenches, independent of trench size and device density. For such VLSI and ULSI circuits, topology management during fabrication has become a critical process step. As feature sizes or device dimensions are scaled downward, more stringent requirements on deposition, photo, and etching processing are posed. Surface-clearing planarization processes, such as are used to create oxide-filled trench isolation, often require that the planarized material thickness be controlled to within a very tight tolerance. When simultaneously achieved over all topographies this condition is referred to as "global" planarization. As compared to conventional Local Oxidation of Silicon (LOCOS) isolation, shallow trench isolation (STI) offers improved isolation between devices and greater packing density. Additionally STI offers a higher degree of planarity, which becomes increasingly important as the photolithographic depth of focus budget continues to shrink with decreasing minimum line width. A common method for planarizing shallow trenches is a combined resist etch-back (REB)/chemical mechanical polish (CMP). This combined REB/CMP process sequence is as follows. The isolation trenches are patterned onto a semiconductor wafer or substrate, generally a silicon substrate. Oxide is deposited conformally onto the wafer with patterned trenches. Photoresist filler blocks then are patterned into the gaps above the trenches. A second resist layer then is coated onto the wafer to create a relatively planar surface. The filler blocks prevent resist from flowing down into the depressions above the trenches, reducing variations in resist thickness across various active area and trench dimensions. This provides a relatively planar surface for the subsequent etch-back. The wafer then is etched, leaving a small amount of oxide on the active areas. Finally, CMP is used to polish the oxide back to the silicon nitride that caps the active area mesas. However, this REB/CMP process is pattern-dependent. During the REB step, small active areas adjacent to trenches that are too small to receive a resist filler block (due to photolithographic tolerances), but too large to fill during oxide deposition, will have less resist than large active areas. Therefore, these small active areas will have less oxide following the etch. With regard to CMP, the small isolated active areas will polish faster than large dense active areas. These adverse pattern effects are well known. Dishing, an undesirable polishing of oxide in wide trenches due to polishing pad deformation, also will occur during the CMP step. The result of these pattern dependencies is that the silicon nitride thickness will vary significantly across various feature sizes following the REB/CMP process, adversely impacting final planarity. Another method to obtain better planarization of a silicon wafer is to utilize three resist layers. This is accomplished by depositing a conformal oxide onto the silicon wafer followed by patterning filler resist blocks and coating a second resist layer, similar to the two resist layer process previously described above. The second resist layer is etched back to the conformal oxide, and then a third resist layer is applied. This method produces better planarization than the conventional two resist layer method described above. However, some variation in oxide thickness will still exist. Further, the additional etch and coat steps reduce the process window due to accumulated non-uniformities. Accordingly, although various improvements in planarization techniques have been developed, manufacturability problems still exist related to final nitride thickness variation between isolated and dense areas as well as non-uniform resist coat and etch-back. Prior art IBM Bulletin titled "Fully Recessed Oxide Isolation Planarization Without the Dip Normally Found in Wide Area", in IBM Disclosure Bulletin of February 1987, US, vol. 29, number 9, pages 4136-4137, discloses a planarization method whereby a dip is likely to develop in wider openings when deposited with planarizing material. A reflow glass is used as the planarization fill material and a mask is used to etch some of the planarization material deposited over the wider opening, thus preventing a dip when subsequently polished. EP Publication 0 597 603 A2, which is a document falling under Article 54(3) EPC, teaches trench isolation planarization using a hard mask in place of conventional photoresist material. US Patent 5,175,122 to Wang et al. teaches a planarization process for trench isolation where the trenches may be of varying widths. Three successive layers of photoresist are applied as taught in the US Wang patent. IBM Bulletin "Method for Planarizing Over Shallow Trenches Filled With Silicon Dioxide", at pages 439-440 from IBM Technical Disclosure Bulletin of February 1990 US, teaches depositing a thin layer of polysilicon on an earlier deposited layer of conformal silicon dioxide SiO 2 . Large trenches are protected by photoresist, and SiO 2 is etched away from the other areas. Polysilicon is deposited and planarized. Polysilicon is removed rapidly while SiO 2 is removed slowly, in a polishing planarization process. SiO 2 acts as a planarization stop when polysilicon exposed surface becomes very small. European published patent application Al 0 340 524 teaches a method of planarizing wide dielectric fill isolation trenches. A self-aligned mask is formed in the depression over wide trenches to protect the dielectric from etching during the planarization steps. SUMMARY OF THE INVENTION Now, an improved method for planarizing a semiconductor substrate having shallow trenches has been developed. This invention, which places in one embodiment an oxide block in the depressions above the trenches following an initial oxide deposition, substantially reduces polish rate dependency on feature size and density. The invention in its broad form resides in a method of fabricating an integrated circuit device, as recited in claim 1. As described hereinafter, a semiconductor substrate, typically coated with a silicon nitride layer, is patterned to form trenches. The regions between the trenches define active regions of variable or consistent size and density. A conformal dielectric layer is deposited onto the substrate, followed by a second conformal polish-assist layer. The second conformal polish-assist layer is patterned using conventional techniques and etched to the dielectric layer, leaving polish-assist blocks in the depressions above the trenches and polish-assist spacers along the sidewalls of the depression. The polish-assist layer and the dielectric layer then are polished back to the top of the active regions to provide highly planarized shallow trenches with excellent global planarity and minimal thickness variation across active areas of various size and density. BRIEF DESCRIPTION OF THE DRAWINGS A more detailed understanding of the invention may be had from the following description of a preferred embodiment, given by way of example and to be studied in conjunction with the accompanying drawing wherein: Figure 1 shows a cross-section of a portion of a substrate layered with material necessary to produce active regions. Figure 2 shows a cross-section of a portion of a substrate containing trenches and active regions of different widths, after a first conformal oxide layer has been formed. Figure 3 depicts the structure of Figure 2 after a etch-stop layer of polysilicon followed by a conformal polish-assist oxide layer has been formed. Figure 4 depicts the structure of Figure 3 after resist blocks are patterned into depressions above the trenches and the conformal polish-assist oxide layer has been etched to form oxide blocks and spacers. Figure 5 depicts the structure of Figure 4 after the polish-assist layer, the etch-stop layer, and the first conformal oxide layer are polished back to the active region layer. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS A planarization method to obtain a planar substrate which is substantially independent of substrate surface geometry or the chip density is described. Figure 1 shows a semiconductor substrate or wafer 5 with a thermally grown oxide layer 6 and a chemical vapor deposition ("CVD") silicon nitride layer 7. Figure 2 depicts the wafer 5 with shallow trenches 11, 12, 13 and 14 which, typically, are of varying size and density. The shallow trenches are patterned into the wafer using conventional photolithographic and reactive ion etching techniques ("RIE"). The silicon nitride layer 7 and oxide layer 6 are etched, preferably, in a nitrogen trifluoride (NF3) plasma, and the silicon is etched, preferably, in a chlorine/hydrogen bromide (Cl 2 /HBr) chemistry. A typical trench depth, as depicted in 11, 12, 13 and 14, is approximately 450 nm (4500Å). The surface geometry of the substrate 5 thus contains active areas 21, 22, and 23 of near constant height which are separated by trenches of varying widths (horizontal distances) 11, 12, 13 and 14. Generally, when shallow trenches such as 11, 12, 13, and 14 need to be formed in a wafer, the ultimate objective is to fill the trenches with a dielectric material, so as to obtain a flat or planar substrate having shallow trenches. The dielectric material can be any dielectric or a material convertible to a dielectric. Such materials include silicon, silicon oxide, silicon nitride, silicon implanted with nitrogen, and the like. Generally, silicon oxide is the preferred dielectric material, and will be use used in the description below. Tetraethylorthosilicate (TEOS)-based CVD oxide is particularly preferred as the dielectric material. To obtain a globally planar surface, a series of processing steps are necessary and are described by the method of this invention. A conformal oxide film 10 is formed, as shown in Figure 2, generally using CVD methods, which are well known in the art of making semiconductor devices. The first conformal CVD oxide layer 10 is of thickness such that the oxide in the trenches will be about the same height as the top surface of the active area mesas, preferably such that the top of the first conformal CVD oxide layer is slightly higher than the top surface of the active area mesas. A typical oxide thickness is approximately 550 nm (5500Å). As depicted in Figure 3, a conformal polish-assist layer 20 is deposited on the first layer of conformal CVD oxide 10. The polish-assist layer can be any material of a compatible polish rate with the first conformal dielectric layer, so as not to cause excessive dishing during polishing. Preferably, the polish-assist layer is a dielectric material such as silicon, silicon oxide, silicon nitride, and the like. Most preferably, the polish-assist layer is the same material as the first conformal dielectric layer, described in this example as a CVD oxide. When the polish-assist layer and the dielectric layer have similar etch rates, as in this example, a thin etch-stop layer 15, preferably a deposited silicon, either amorphous or polysilicon, may be desirable. The second layer of conformal oxide 20 is preferably of a thickness such that the top of the oxide layer 20 above the trenches will be approximately level with the top of the first layer of conformal CVD oxide 10 on the active area mesas. A typical preferred thickness is approximately 530 nm (5300Å). The silicon etch-stop layer 15, sandwiched between the two conformal CVD oxide films 10 and 20, should be of thickness sufficient to provide adequate etch stop during the oxide etch, typically about 100 nm (1000Å). Figure 4 illustrates that following the second conformal CVD oxide deposition, resist blocks 25 and 26 are patterned into depressions of sufficient width above trenches 13 and 14 using a filler mask. The filler mask is a reverse tone of the active area mask that is undersized or reduced such that the resist blocks 25 and 26 can sit on the CVD oxide 20 and in the depressions above the trenches 13 and 14 without encroaching onto the sidewalls 27 of the second layer of conformal CVD oxide 20. The oxide is then etched forming oxide blocks 28 and 29. Preferably, the etch is a CHF3/CF4/Ar chemistry with high selectivity, preferably greater than 10 to 1 (oxide to silicon). Preferably, the oxide over-etch can be minimized to leave oxide spacers 20A that will further enhance the degree of oxide "fill". The spacers are particularly useful in trench 12 where the width of the space is too small to receive an oxide block, unlike trenches 13 and 14, and too large to fill during the conformal oxide and silicon depositions, unlike trench 11. The resist is stripped from the wafer 5, and the wafer is polished back to the silicon nitride 7, as shown in Figure 5. During the polishing step, the patterned conformal oxide blocks bridge the polishing pad between active area mesas. This bridging eliminates dishing of the oxide 10 located in the trenches and minimizes overpolish requirements by preventing polishing pad deformation across large active area mesas. Additionally, the oxide blocks in combination with the oxide spacers significantly reduce the variation in polish rate between active area mesas of varying size and pattern density. It should be noted that conventional KOH-based silica slurry, used for chemical mechanical polishing of oxide, polishes silicon at approximately 1.5 times faster than thermal oxide. Therefore, the silicon etch-stop remaining on the oxide after the oxide etch is easily polished, and does not impact final planarity. The method of this invention is described in the context of forming dielectric-filled planar shallow trenches of constant or varying widths in a silicon substrate by way of example only. It will, however, be apparent to one skilled in the art that the present invention disclosed is not limited to the specific embodiment described above and depicted in Figures 1-5. This invention is equally applicable to any substrate surface geometry which has regions of a near constant height, separated by same or different lateral distances. It should be also noted that the starting surface geometry of substrate which is to be planarized could be at any one of a number of different stages during the wafer fabrication process. The regions separating the trenches could represent active regions, as described herein, or islands. Also the regions could represent metal lines needing interlevel dielectric so that subsequent metal lines could be patterned. Various other modifications of the disclosed embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description, or may be made without departing from the scope of the invention defined in the appended claims.

Claims: A method of fabricating an integrated circuit device, comprising the following sequence of steps of: (a) forming trenches (11,12,13,14) on a face of a semi-conductor substrate (5), the regions between the trenches at the face defining active region mesas (21,22,23); (b) forming a first conformal dielectric layer (10) on the face to fill in the trenches; (c) forming a second conformal polish-assist layer (20), on the first conformal dielectric layer (10) said second conformal polish-assist layer having a compatible polish rate with said first conformal dielectric layer; (d) patterning resist blocks (25,26) onto the second conformal polish-assist layer (20) such that said resist blocks will sit in spaces of depressions occuring above said trenches without encroaching on side wells (27) of said depressions; (e) forming from the second conformal polish-assist layer polish-assist blocks (28, 29) under the resist blocks (25,26) and polish-assist spacers (20A) along the side walls of depressions above the trenches by etching the second conformal polish-assist layer (20) to said first conformal layer (10); (f) stripping the resist blocks (25,26) away from the polish-assist blocks (28,29); and (g) polishing back said polish-assist blocks (28,29) and said spacers (20A) and the first conformal dielectric layer (10), to the top of the active region mesas (21,22,23), forming a globally planar surface. A method as claimed in claim 1, in which the semi-conductor substrate comprises silicon, the first conformal dielectric layer comprises an oxide film, the second conformal polish-assist layer comprises an oxide film. A method as claimed in claim 1 or claim 2, in which the first conformal dielectric layer fills the trenches to a level greater than, or substantially level with, the top of the active region mesas (21,22,23), the second conformal polish-assist layer (20) is formed at a thickness such that the top of the second conformal polish-assist layer above the trenches is substantially level with the top of the first conformal dielectric layer (10) over the active area mesas, and the resist blocks (25,26) are formed into depressions of the second conformal polish-assist layer (20). A method as claimed in any preceding claim, further comprising the step of forming a layer of polysilicon etch-stop (15) on the first conformal dielectric layer (10) prior to forming the second conformal polish-assist layer (20). A method as claimed in any preceding claim, in which the trenches (11,12,13,14) and active region mesas (21,22,23) are of varying dimensions, and in which the first conformal dielectric layer (10) is a silicon oxide. A method as claimed in claim 5, in which the first conformal dielectric layer (10) is a TEOS oxide layer. A method as claimed in any preceding claim, in which the resist blocks (25,26) are patterned into the depressions above the trenches using a mask. A method as claimed in claims 5-7 in combination with claim 4, in which the second conformal polish-assist layer is etched with selectivity utilising a CHF 3 /CF 4 /Ar chemistry, wherein the CHF 3 /CF 4 /Ar chemistry has a selectivity greater than 10:1 of oxide:polysilicon. A method as claimed in claim 8, in which the patterned polish-assist blocks are of sufficient width to bridge a polishing pad between active areas during the polishing. A method as claimed in claims 5-9 in combination with claim 4, in which the second conformal polish-assist layer (20) is of the same type of material as the first conformal dielectric layer (10).

Inventors: COOPERMAN STEVEN SCOTT, NASR ANDRE ILYAS, COOPERMAN, STEVEN SCOTT, NASR, ANDRE ILYAS
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1994
Main classification: H01L21
IPC codes: H01L21