Apparatus for recording and reproducing digital video signal

Abstract: Data rates of a first video signal and a second video signal which are significantly different in the data rates are converted to respective predetermined data rates, and both the video signals of one frame are divided into respective numbers of macro block. A ratio of the number of macro block of the first video signal to the number of macro block of the second signal is made to 1:n (n: natural number), and a ratio of the number of pixel in one macro block of a color difference signal of the first video signal to the number of pixel in one macro block of the color difference signal of the second video signal is made to 1:m (m: natural number), a ratio of the data rate of the color difference signal of the first video signal to the data rate of the color difference signal of the second video signal is made to 1:n×m and a ratio of a moving speed of a magnetic tape in the first video signal to a moving speed of the magnetic tape in the second video image is made to 1:n.

Description: FIELD OF THE INVENTION AND RELATED ART STATEMENT 1. FIELD OF THE INVENTION The present invention relates to an apparatus for recording and reproducing a digital video signal, and particularly to an apparatus for recording and reproducing digital video signals of video images of plural different video systems. 2. DESCRIPTION OF THE RELATED ART In an example of an apparatus for recording and reproducing a digital video signal, first, one frame of a video image is divided into a plurality of image blocks. Second, the known DCT block (discrete cosine transform block) composed of 64 pixels (8 pixel × 4 lines × 2 fields) is defined as the unit of image. One image block comprises one DCT block representing a color difference signal (R-Y), one DCT block representing another color difference signal (B-Y) and four DCT blocks representing a luminance signal Y. Therefore, in the PAL system (hereinafter referred to as 625/50 system) for example, one frame of the video image is divided into 45 image blocks in the horizontal direction and 36 image blocks in the vertical direction. Consequently, one frame of the video image is divided into 1620 image blocks. Data of each image block divided as mentioned above is converted into a coded data. A main component of the coded data of each image block is stored in one synchronizing block (hereinafter is referred to as SYNC block). Subsequently, one frame of the video image is divided into 12 sections in the vertical direction. The SYNC block data having the coded data of the image blocks in each section are recorded on one video track of a magnetic tape. In the recording operation, the order of arrangement of the SYNC block data to be recorded on one video track is set so that the image blocks corresponding to those SYNC block data are substantially arranged at neighboring locations on an original video image. The video data of one frame divided into 12 sections are recorded in 12 video tracks. In the NTSC system (hereinafter is referred to as 525/60 system), one frame of a video image is divided into 22.5 image block in the horizontal direction and 60 image blocks in the vertical direction, and consequently one frame is divided into 1350 image blocks. The data of each image block is converted into a coded data, and is stored in a corresponding SYNC block. Subsequently, one frame of the video image is divided into 10 sections in the vertical direction. A similar operation to the 625/50 system is applied to the data of the image blocks of each section. The SYNC block data having the coded data of the image blocks in each section are recorded in one track of the magnetic tape. Consequently, the video data of one frame is recorded on 10 video tracks. In the above-mentioned recording methods, the signal processing method in the 625/50 system is similar to the signal processing method in the 525/60 system, and a common circuit is usable for both the systems. Moreover, in case of high speed reproduction of the recorded data, the video images reproduced from the video data of one video track are substantially arranged at neighboring locations on the reproduced video image. In the conventional apparatus for recording and reproducing of the digital video signal, in the case that the number of pixel per one frame is not greatly different from each other between two separate systems such as the 525/60 system and the 625/50 system, the same signal processing circuit is usable for both the systems. However, for example, in the case that the number of pixel per one frame in a video system is several times as much as the number of pixel per one frame in the 625/50 system, such as the HDTV system versus 625/50 system, for example, it is difficult to use the same signal processing circuit. OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to provide a method and an apparatus for recording and reproducing a digital video signal which are capable of processing plural video signals having a greatly different number of pixel per one frame from a common signal processing circuit. This object is solved by a method for recording and reproducing a digital video signal according to claim 1 and an apparatus for recording and reproducing a digital video signal according to claim 5. While the novel features of the invention are set forth particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram of an apparatus for recording and reproducing a digital video signal of a first embodiment of the present invention; FIG.2 is a block diagram of a data rate conversion circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.3 is a block diagram of a first example of a blocking circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.4 is a block diagram of a coding circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.5 is a block diagram of a SYNC block data generation circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.6 is a block diagram of a recording signal processing circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.7 is a diagram representing a macro block of one frame of the 625/50 system in the apparatus for recording and reproducing the digital video signal; FIG.8 is a diagram representing a macro block of one frame of the 1250/50 system and 1125/60 system in the apparatus for recording and reproducing the digital video signal; FIG.9 is a diagram representing arrangement of super blocks in one frame of the 625/50 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.10 is a diagram representing arrangement of super blocks in one frame of the 1250/50 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.11 is a diagram representing arrangement of macro blocks in a super block in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.12A is a diagram representing SYNC block data of the 625/50 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.12B is a diagram representing SYNC block data of the 1250/50 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.13 is a diagram representing video tracks in a magnetic tape on which a video signal of 625/50 system is recorded in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.14 is a block diagram representing video tracks in the magnetic tape on which a video signal of 1250/50 system is recorded in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.15 is a diagram representing arrangement of pixels in a macro block of the video signal of 1250/50 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.16 is a block diagram of a second example of the blocking circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.17 is a block diagram of a third example of the blocking circuit in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.18 is a diagram representing arrangement of super blocks in one frame of the video signal of the 525/60 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.19 is a diagram representing arrangement of super blocks in one frame of the video signal of the 1050/60 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.20A is a diagram representing arrangement of super blocks in one frame of the video signal of the 1125/60 system in the apparatus for recording and reproducing the digital video signal of the first embodiment; FIG.20B is a diagram representing changed arrangement of the super blocks shown in FIG.20A; FIG.20C is a diagram representing arrangement of macro blocks in the super blocks shown in FIG.20A; FIG.20D is a diagram representing changed arrangement of the macro blocks in the super blocks shown in FIG.20C; FIG.21 is a block diagram of the apparatus for recording and reproducing the digital video signal of the second embodiment of the present invention; FIG.22 is a block diagram of a blocking circuit in the apparatus for recording and reproducing the digital video signal of the second embodiment; FIG.23 is a block diagram of a 3CH/2CH conversion circuit in the apparatus for recording and reproducing the digital video signal of the second embodiment; FIG.24 is diagrams representing division of video image of one frame in the apparatus for recording and reproducing the digital video signal of the second embodiment. It will be recognized that some or all of the Figures are schematic representations for purposes of illustration and do not necessarily depict the actual relative sizes or locations of the elements shown. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.1 is a block diagram of the apparatus for recording and reproducing a digital video signal of a first embodiment of the present invention. In the description of the first embodiment of the present invention, a first video signal is of the 625/50 system (hereinafter is referred to as PAL signal), and a second video signal is of the 1250/50 system (hereinafter is referred to as HDTV signal), for example. In FIG.1, first, an analog PAL signal is inputted to a first input terminal 1, or an analog HDTV signal is inputted to a second input terminal 2. Finally, the digital PAL signal or the digital HDTV signal is recorded in a magnetic tape 15, for example. Recording and reproducing heads of the magnetic tape recording apparatus comprises combination heads. The combination head comprises two head elements. In each combination head, a first recording combination head is composed of heads 13A and 14A, and a second recording combination head is composed of heads 13B and 14B. Reproducing combination heads 16A, 17A and 16B, 17B are configurated in a manner similar to the recording combination heads. Therefore, signals of two channels may be simultaneously recorded on the magnetic tape 15 and reproduced therefrom. The magnetic tape 15 is wound around the known rotary cylinder (not shown) for about 180 degrees of central angle. Two recording combination heads 13A, 14A and 13B, 14B are disposed on the rotary cylinder at both opposed positions of 180 degrees of central angle. Both the combination heads are adjusted so as to helically scan on the surface of the magnetic tape. [Recording of PAL signal] In the first embodiment of the apparatus for recording and reproducing the digital video signal, first, recording operation of the PAL signal is described hereafter. The analog PAL signal is inputted to a data rate conversion circuit 3 through the input terminal 1. A detailed configuration of the data rate conversion circuit 3 is shown in a block diagram of FIG.2. Referring to FIG.2, switches 37, 38 and 39 are linked for simultaneous operation and select either one of a first video signal inputted from the first input terminal 1 or a second video signal inputted from the second input terminal 2. In FIG.2, the switches 37, 38 and 39 contact respective upper contacts, and analog to digital converters (hereinafter is referred to as ADC) 31, 32 and 33 are connected to a known first-in and first-out circuit (hereinafter is referred to as FIFO) 40 and filters 45 and 46, respectively. A luminance signal Y (hereinafter is referred to as Y signal) of the first image signal inputted from the input terminal 1 is sampled with a clock signal of 13.5 MHz and is converted to a digital signal by the ADC 31. The digital signal is applied to the FIFO 40. On the other hand, a color difference signal (R-Y) (hereinafter is referred to as (R-Y) signal) of the first video signal is sampled with a clock signal of 6.75 MHz and is converted to a digital signal by the ADC 32. The digital signal is applied to a filter 45 and an FIFO 41 through the switch 38. Moreover, a color difference signal (B-Y) (hereinafter is referred to as (B-Y) signal) of the first video signal is sampled with the clock signal of 6.75 MHz and is converted to a digital signal by the ADC 33. The digital signal is applied to the filter 46 and an FIFO 43 through the switch 39. An FIFO 42 is connected between the output of the FIFO 41 and the filter 45, and an FIFO 44 is connected between the output of the FIFO 43 and the filter 46. The FIFOs 40 --- 44 serve as 1H delay memories for delaying the PAL signal by one horizontal scanning period and store it. The stored Y signal is output to a terminal 47. The (R-Y) signal and (B-Y) signal are decimated on alternate scanning lines and are output to respective terminals 48 and 49. Consequently, the PAL signal is converted into the digital data of the known 4:2:0 format. The number of "effective pixels" of the Y signal is represented by 720 pixels in the horizontal direction and 288 scanning lines in the vertical direction per one field. The number of effective pixels of the (R-Y) signal is represented by 360 pixels in the horizontal direction and 144 scanning lines in the vertical direction per one field, and the number of effective pixels of (B-Y) signal is also represented by 360 pixels in the horizontal direction and 144 scanning lines in the vertical direction per one field. The digital signal converted to the 4:2:0 format is inputted to a blocking circuit 4 of a first embodiment. A detailed configuration of a first example of the blocking circuit 4 is shown by a block diagram of FIG.3. The blocking circuit 4 is composed of a first blocking circuit 76 and a second blocking circuit 77. The Y signal output from the terminal 47 of the data rate conversion circuit 3 is inputted to FIFOs 54, 55 and 56 through a terminal 51 of the first blocking circuit 76. Moreover, the (R-Y) signal output from the terminal 48 of the data rate conversion circuit 3 is inputted to an FIFO 57 through a terminal 52, and the (B-Y) signal output from the terminal 49 of the data rate conversion circuit 3 is inputted to an FIFO 58 through a terminal 53 of the first blocking circuit 76. The Y-signal, (R-Y) signal and (B-Y) signal are selected by a selector 59 and are inputted to a memory 61 of the second blocking circuit 77. In the second blocking circuit 77, the inputted data are successively stored in the memory 61 on the basis of a control signal of a write address control circuit 64. Subsequently, the stored data are read out from the memory 61 on the basis of a control signal of a read address control circuit 65, and the read data are structured to an image block (hereinafter is referred to as macro block), and is applied to an FIFO 66 or an FIFO 69. The configuration of a macro block 108 in the 625/50 system is shown in FIG.7. In one macro block 108, the Y signal is represented by four DCT blocks 108A, 108A, 108A, 108A. Each one DCT block 108A is composed of data of two fields of the product of four pixels in the horizontal direction by four lines in the vertical direction. The (R-Y) signal and (B-Y) signal are formed by one DCT block, respectively. Subsequently, the video image of one frame is divided into a plurality of "super blocks". FIG.9 is a diagram representing arrangement of the super blocks in one frame. Referring to FIG.9, one frame is divided into twelve sections in the vertical direction and five sections in the horizontal direction, and finally is divided into 60 super blocks. A super block is represented by S i,j (i = 0, ···, 11; j = 0,···, 4). Each super block S i,j comprises 27 macro blocks. Arrangement of 27 macro blocks in a super block is represented by M i,j,k (k = 0, 1,···, 26). In the example shown in FIG.11, a first macro block M i,j,0 is placed upper left, and successive macro blocks M i,j,1 and M i,j,2 are arranged downward in numerical order. At the bottom, the successive macro block M i,j,3 is arranged rightward, and macro blocks M i,j,4 and M i,j,5 are arranged upward in numerical order. At the top, the successive macro block M i,j,6 is placed rightward, and macro blocks M i,j,7 and M i,j,8 are arranged downward in numerical order. Remaining macro blocks M i,j,k are arranged in a manner mentioned above, and the final macro block M i,j,26 is placed lower right in the super block. In the FIFO 66 shown in FIG.3, a "video segment" is formed by plural macro blocks M i,j,k inputted from the memory 61. The video segment is described in detail hereafter. The data of the video segment is output to a terminal 74 through a selector 72. One video segment is composed of five macro blocks. In five super blocks which are located at separate positions in the video image, one macro block is designated with respect to each super block, and one video segment is formed by the designated five macro blocks. A video segment is represented by V i,k , and five macro blocks M i,j,k represented by Equation (1) correspond to a video segment V i,k as follows: Referring to Equation (1), a representation "(i+2) mod 12" in a term "I" of subscripts of "M" represents "modulo operation" for deriving a remainder by dividing the value of (i+2) by 12. The values 2, 6, 8, 0 and 4 in the respective parentheses are arbitrarily selected. Numerals in a term "J" of the subscripts represent the values of "j" for designating the positions of the super blocks in the horizontal direction. These numerals are also arbitrarily selected. A term "K" of the subscripts represents the macro block number "k". A video segment "V i,k " is comprised of five macro blocks having the same number "k" in five super blocks selected as shown by Equation (1). In the Equation (1), a super block S i,j and a macro block M i,j,k in the case of "i = 2" and "k = 1" are shown in Table 1. Super block Macro block S 4, 2 M 4, 2,1, S 8, 1 M 8, 1,1, S 10,3 M 10,3,1, S 2, 0 M 2, 0,1, S 6, 4 M 6, 4,1, In Table 1, addresses of the super blocks (see FIG.9) are shown in the left column, and the order from the top to the bottom represents a "first arrangement order of super blocks". Namely, the first order of arrangement of the super blocks is designated by the Equation (1). The addresses of the macro blocks in each super block are shown in the right column (the macro blocks having the number (1) in FIG.11. In the term "J" of the subscripts of Equation (1), the order of the numerals "2, 1, 3, 0, 4" designates positions in the horizontal direction on the video image as shown in FIG.9. The numeral "2" represents a central area in the video image. In a similar manner, the numerals "1" and "3" represent both areas neighboring to the central area "2", and the numerals "0" and "4" represent both end areas. As shown by Equation (1), the macro block of the central part on the video image is arranged on the top line in Equation (1), and the macro block of the end part on the video image is arranged in the bottom line in Equation (1). In the data processing of the embodiment, the macro block of the upper line in Equation (1) has priority over the macro block of the lower line, because the macro block of the upper line is located on the important central part of the video image and the macro block of the lower line is located on the end part of the video image which is relatively lower in importance. By the above-mentioned selection of the skipped numerals such as 2, 6, 8, 0 and 4, five super blocks located at the separated positions may be designated in the horizontal direction and the vertical direction on the video image. The order of the video segments V i,k is as follows: In the above-mentioned expression of the order of the video segments, the video segments are output in the order from left to right in each horizontal line starting from the top line, and are output in the order shown by successive lower lines. The macro blocks in the video segment are applied to the coding circuit 5 in the order shown in Equation (1) and are encoded in the order. The coded data are output to a terminal 94 of the coding circuit 4. In the coded data of each macro block of the video segment, in the case that the data of the macro block of the top line in Table 1 overflow by exceeding a predetermined data length, the overflow data are stored in a data area for the macro block of the subsequent lower line in Table 1. In a similar manner, data overflowed from the macro block of the upper line are successively stored in a data area for the macro block of the lower line. Consequently, in the case that overflowed data can not be stored in the data area for the macro block of the bottom line in Table 1, the overflowed data are abandoned. However, since the macro block of the bottom line has the image data of peripheral parts of the video image, even if the data of the macro block of the bottom line is abandoned, the reproduced video image is deteriorated only on the peripheral parts. Consequently, damage in the quality of the reproduced image is relatively small. In a similar operation, other video segment is formed from macro blocks in FIFOs 69, 70 and 71 and a selector 73, and is output to a terminal 75. An order of arrangement of the macro blocks in the video segment is represented by Equation (2). V i,k = { M (i+2) mod 12, 2, k , M (i+6) mod 12, 1, k , M (i+8) mod 12, 3, k , M (i+0) mod 12, 0, k , M (i+4) mod 12, 4, k } (i = 1, 3, 5, 7, 9, 11; k = 0, 1, 2, 3,···,26). The order of the video segments V i,k is as follows: In the video segment V i,k shown in the Equation (1), since "i" is 0, 2, 4, 6, 8 or 10, the video segment is configurated from the macro blocks M i,j which belong to the super blocks S i,j having even number in the vertical direction of the video image. Moreover, in the segment V i,k shown in the Equation (2), "i" is 1, 3, 5, 7, 9 or 11, the video segment is configurated by the macro blocks M i,j,k which belong to the super blocks S i,j of lines having odd number in the vertical direction of the video image. The block data output from the terminal 74 is applied to a first coding circuit 5, and the block data output from the terminal 75 is applied to a second coding circuit 6. The first coding circuit 5 and the second coding circuit 6 are configurated by the known coding circuit as shown in FIG.4. The block data represented by the Equation (1) and the Equation (2) are inputted to respective terminals 81, and are data-compressed by a DCT circuit 82, quantization circuit 83 and a VLC circuit 84, and are output to respective terminals 85. The output of the first coding circuit 5 is applied to the known first synchronizing block data generation circuit 7 (hereinafter is referred to as first SYNC block data generation circuit), and in a similar manner, the output of the second coding circuit 6 is applied to a second SYNC block data generation circuit 8. Detailed configurations of the first SYNC block data generation circuit 7 and the second SYNC block data generation circuit 8 are shown in FIG.5. Referring to FIG.5, the block data inputted to a terminal 90 is applied to a memory 94 and a data length detection circuit 91. In the data length detection circuit 91, the length of the block data is detected, and a detected signal is applied to a write address control circuit 92. The block data inputted from the terminal 90 is written in a predetermined address of the memory 94 by a control signal from the write address control circuit 92. A plurality of memory areas of the SYNC block data 110 as shown in FIG.12A are prepared in the memory 94, and one SYNC block data 110 corresponds to one memory area. The coded data of one macro block are stored in predetermined image data areas 113 --- 118 which are allotted to the DCT blocks of the macro block. In the storing operation, a low frequency component in the coded data of the video image is given priority. A part of the coded data which overflows from the image data area is stored in an image data area having allowance in the image data areas 113 --- 118. Coded data which overflows the image data area is stored in other SYNC block data having allowance. Moreover, additional information is stored in an additional information area 112 of the SYNC block data 110. By the above-mentioned operation, the low frequency component of the video signal (hereinafter is referred to as a main component of the coded data) is stored in a corresponding area of one SYNC block data. Subsequently, in FIG.5, the coded data is read out from the memory 94 in compliance with the control signal of a read address control circuit 94 in units of one SYNC block data, and is output to a terminal 95. Referring to FIG.1, the coded data output from the first SYNC block data generation circuit 7 and the second SYNC block data generation circuit 8 are applied to a first recording signal processing circuit 9 and a second recording signal processing circuit 10, respectively. The SYNC block data is represented by U i,j,k and one SYNC block data U i,j,k comprises the main component of the data-compressed data of one macro block M i,j,k . The first recording signal processing circuit 9 and the second recording signal processing circuit 10 are configurated by the known circuit as shown in FIG.6. Referring to FIG.6, the SYNC block data inputted from a terminal 101 is written in a memory 104 by a control signal from a write address control circuit 102. Subsequently, the written SYNC block data is rearranged to a predetermined order by the control signal from a read address control circuit 103 and read out from the memory 104. The data read out of the memory 104 is applied to an error correction coding circuit 105, and the known outer coding operation or inner coding operation is applied thereto. Subsequently, predetermined SYNC pattern and predetermined ID data are added to each SYNC block data in a SYNC-ID addition circuit 106, and is output to a terminal 107. Referring to FIG.1, the SYNC block data output from the first recording signal processing circuit 9 is applied to the recording heads 13A and 13B through a recording amplifier 11, and the SYNC block data output from the second recording signal processing circuit 10 is applied to the recording heads 14A and 14B through a recording amplifier 12. Consequently, the SYNC block data are recorded on the magnetic tape 15. In the recording operation of the PAL signal, recording signals are output from the first and second recording signal processing circuits 9 and 10 only when the first combination heads 13A and 14A scan on the magnetic tape 15. Namely, the recording operation is performed during a half revolution period of the rotating cylinder. The moving speed of the magnetic tape 15 is predetermined so that the magnetic tape 15 is moved by a width of the recording track formed by one head, for example the head 13A, in the half rotation period of the rotating cylinder. Consequently, the recording tracks are formed on the magnetic tape 15 by the first combination heads 13A and 14A without blank. In the recording operation on the magnetic tape 15, five super blocks S 0,0 , S 0,1 , S 0,2 , S 0,3 and S 0,4 in the horizontal direction in FIG.9 are recorded on one track. In a similar manner, five super blocks S 1,0 , ... S 1,4 are recorded on the successive one track. Consequently, the super blocks S i,j of one frame are recorded in twelve tracks 128 --- 139 as shown in FIG.13. Referring to FIG.13, the tracks 128, 130, 132, 134, 136 and 138 having even numbers are recorded by the recording head 13A, and the tracks 129, 131, 133, 135, 137 and 139 having odd numbers are recorded by the recording head 14A. The order of the SYNC block data U i,j,k of data T i which are recorded from the starting point to the end point of a track having a number "i" in the twelve tracks is represented by Equation (3). T i = { U i, 0, 0 , ···,U i, 0, 26 , U i, 1, 0 , ···,U i, 1, 26 , U i, 2, 0 , ···,U i, 2, 26 , U i, 3, 0 , ···,U i, 3, 26 , U i, 4, 0 , ···, U i, 4, 26 } (i = 0, ···, 11). [Recording operation of HDTV signal (1250/50) in the first embodiment] Recording operation of the HDTV signal is described hereafter. Referring to FIG.1, an analog HDTV signal is inputted to the terminal 2 and is applied to the data rate conversion circuit 3. In the detailed signal rate conversion circuit 3 in FIG.2, the switches 37, 38 and 39 are connected to ADCs 34, 35 and 36, respectively. The Y signal of the HDTV signal is sampled with the clock signal of 40.5 MHz and is converted into a digital signal by an ADC 34. The converted digital signal is applied to the FIFO 40 through the switch 37. The (R-Y) signal of the HDTV signal is sampled with the clock signal of 13.5 MHz and is converted into a digital signal by an ADC 35. The converted digital signal is applied to the filter 45 and the FIFO 41 through the switch 38. Moreover, the (B-Y) signal of the HDTV signal is sampled with the clock signal of 13.5 MHz and is converted into a digital signal by an ADC 36. The converted digital signal is applied to the filter 46 and the FIFO 43 through the switch 39. When the switches 37, 38 and 39 are connected to the ADCs 34, 35 and 36, respectively, the FIFOs 40, 41, 42, 43 and 44 serve as 1H delay memories of the HDTV signal, and the (R-Y) signal and (B-Y) signal are decimated every two lines. Consequently, the HDTV signal is converted into the signal of the known 12:4:0 format. The converted Y signal is output to the terminal 47, the (R-Y) signal is output to the terminal 48, and the (B-Y) signal is output to the terminal 49. Effective pixels of the Y signal per one field is represented by 1080 pixels in the horizontal direction and 576 scanning lines in the vertical direction. In a similar manner, effective pixels of the (R-Y) signal per one field are represented by 360 pixels in the horizontal direction and 288 scanning lines in the vertical direction, and effective pixels of the (B-Y) signal per one field are represented by 360 pixels in the horizontal direction and 288 scanning lines in the vertical direction. The output signals of the data rate conversion circuit 3 are applied to the blocking circuit 4 in FIG.3, and the data rate of the HDTV signal is made to about three times of the data rate of the PAL signal. Therefore, three memories 61, 62 and 63 in the blocking circuit 4 are used for rearranging the data of the HDTV signal. Referring to FIG.3, the signals of address data output from the write address control circuit 64 and the read address control circuit 65 are applied to the three memories 61, 62 and 63. The Y signal of the HDTV signal is applied to the FIFOs 54, 55 and 56 through the terminal 51. Moreover, the (R-Y) signal is applied to the FIFO 57 through the terminal 52, and the (B-Y) signal is applied to the FIFO 58 through the terminal 53. The inputted data are converted in the data rate and are formed to data block by these FIFOs 54 --- 58. In the Y signal, one horizontal scanning line of the video image is divided into a plurality of sections each having 24 pixels, and the section having the 24 pixels is divided into three data each having 8 pixels. The three data are applied to the FIFOs 54, 55 and 56, respectively. Subsequently, the three data are simultaneously output from the FIFOs 54, 55 and 56. The output data of the FIFO 54 is applied to the memory 61 through the selector 59, the output data of the FIFO55 is applied to the memory 62 through the selector 60, and the output data of the FIFO 56 is applied to the memory 63. The (R-Y) signal and (B-Y) signal are alternately inputted to the blocking circuit 4 by skipping one horizontal scanning line. In the (R-Y) signal and (B-Y) signal, one horizontal scanning line of the video image is divided into a plurality of segments each having 8 pixels. The data of the (R-Y) signal of a segment and the data of the (B-Y) signal of a segment at the same vertical position on neighboring two horizontal scanning lines are simultaneously output from the FIFO 57 and the FIFO 58. The output data of the FIFO 57 is applied to the memory 61 through the selector 59. Moreover, the output data of the FIFO 58 is applied to the memory 62 through the selector 60. The Y signal and the (R-Y) and (B-Y) signals are inputted to the three memories 61, 62 and 63 in turn. Subsequently, data of two mini-blocks are output from the first blocking circuit 76. The data of the first mini-block represent the Y signal of a segment having 24 pixels on one horizontal scanning line. The data of the second mini-block represent the (R-Y) signal of a segment having 8 pixels and the (B-Y) signal of a segment having 8 pixels on two horizontal scanning lines. The data of the Y signal, the (R-Y) signal and the (B-Y) signal are written in the memories 61, 62 and 63 in units of one block of data on the basis of the control signal of the write address control circuit 64. The written data are read out of the memories 61, 62 and 63 on the basis of the control signal of the read address control circuit 65, and thereby macro blocks are formed. The macro blocks are applied to the FIFO 66, FIFO 67 and FIFO 68 or the FIFO 69, FIFO 70 and FIFO 71. FIG.8 is a diagram of the macro block 109 in the 1250/50 system, 1125/60 system and 1050/60 system. One DCT block 109A comprises data of 4 horizontal segment each having 8 pixels per one field. Consequently, the number of data is represented by 8 x 4 × 2 per one frame. The data of the Y signal is comprised of 6 DCT blocks. In a similar manner, each of the (R-Y) signal and the (B-Y) signal is comprised of one DCT block. Consequently, the macro block 109 is comprised of data of 16 horizontal segment each having 24 pixels on 16 horizontal scanning lines. The number of data per one macroblock is represented by the product of 24 by 16. In FIGs. 7 and 8, the ratio of the number of pixel (64 pixels) in the color difference signal in one macro block 109 of 1250/50 system to the number of pixel (64 pixels) in the color difference signal in one macro block 108 of 625/50 system is made to a predetermined natural number "m". The number "m" is "1" in the first embodiment. Detailed configuration of the macro block 109 is shown in FIG.15. Referring to FIG.15, the DCT blocks 171 --- 176 are data blocks of the Y signal, and DCT blocks 177 and 178 are data blocks of the (R-Y) signal and the (B-Y) signal, respectively. In the macro block 109 shown in FIG.15, a first mini-block is composed of data of 24 pixels in the top line of the three DCT blocks 171, 172 and 173 such as "Y 0,0,··· , Y 0,7 ; Y 0,8, ··· , Y 0,15 ; Y 0,16, ··· , Y 0,23 ". The data of the first mini-block are inputted to the FIFOs 66, 67 and 68 from the memories 61, 62 and 63 in FIG.3. Subsequently, data of a second mini-block are composed of data r 0,0,··· , r 0,7 ; b 0,0, ··· , b 0,7 of the DCT block 177 and 178, for example. The data of the second mini-block are inputted to the FIFOs 66 and 67. Consequently, the data of the DCT blocks 171, 174 and 177 are inputted to the FIFO 66, the data of the DCT blocks 172, 175 and 178 are inputted to the FIFO 67, and the data of the DCT blocks 173 and 176 are inputted to the FIFO 68. The data of the DCT blocks 171 --- 178 are output from the FIFOs 66 --- 68 to the terminal 74 in a predetermined order through the selector 72. In the above-mentioned operation, the data of 24 pixels are divided into three groups each having 8 pixels. The three groups of data are simultaneously written at the same address in the three memories 61, 62 and 63 by the control signal of the write address control circuit 64. In read-out operation, three groups of data are simultaneously read out of the memories 61, 62 and 63 by the control signal of the read address control circuit 65. The data of 8 pixels of (R-Y) signal and the data of 8 pixels of (B-Y) signal are also simultaneously written at the some address of the memories 61 and 62, and are simultaneously read out therefrom. Therefore, the three memories 61, 62 and 63 may be controlled by a single control signal, and the write address control circuit 64 and read address control circuit 65 are simplified. FIG.10 is a diagram of arrangement of super blocks in one frame of the video image of 1250/50 system. The video image of one frame is divided into a plurality of super blocks as shown in FIG.10. The video image of one frame comprises 45 macro blocks in the horizontal direction and 72 macro blocks in the vertical direction. The video image of one frame is divided into 5 sections in the horizontal direction and 24 sections in the vertical direction. Consequently, the video image of one frame is divided into 120 super blocks as shown in FIG.10. A super block is represented by "S i,j (i = 0, 1, ···, 22, 23; J = 0, · · ·,4). Each super block S i,j comprises 27 macro blocks M i,j,k (k = 0, 1, · ··,25, 26) as shown in FIG.11. In FIG.9 and FIG.10, the ratio of the number of the super blocks in one frame of the 1250/50 system to the number of the super blocks in one frame of the 625/50 system is made to a predetermined natural number "n". The number of macro blocks in one super block of the 1250/50 system is equal to that of the 625/50 system. Therefore, the ratio of the number of macro blocks in one frame of the 1250/50 system to the number of macro blocks in one frame of the 625/50 system is "n". The number "n" is "2" in the first embodiment. The data of macro blocks output from the terminal 74 in FIG.3 are formed to a video segment V i,k . One video segment comprises 5 macro blocks and arrangement of the macro blocks in each video segment is represented by Equation (4). V i,k = { M (i+4) mod 24, 2, k , M (i+12) mod 24, 1, k , M (i+16) mod 24, 3, k , M (i+0) mod 24, 0, k , M (i+8) mod 24, 4, k } (i = 0, 2, 4, 6, ···,20, 22; k = 0,···,26). Referring to Equation (4), the data of macro blocks of which subscript "i" is even number are output from the terminal 74. The data of macro blocks output from the terminal 75 are also formed to a video segment. The arrangement of the macro blocks in each video segment is represented by Equation (5). V i,k = { M (i+4) mod 24, 2, k , M (i+12) mod 24, 1, k , M (i+16) mod 24, 3, k , M (i+0) mod 24, 0, k , M (i+8) mod 24, 4, k } (i = 1, 3, 5, 7, ··· ,21, 23; k = 0, ···,26). Referring to Equation (5), the data of macro blocks of which subscript "i" is odd number are output from the terminal 75. Referring to FIG.1, the block data output from the terminal 74 is inputted to the first coding circuit 5, and the block data output from the terminal 75 is inputted to the second coding circuit 6. In the first coding circuit 5 and the second coding circuit 6, the rate of data compression of the HDTV signal is about 4/3 times as large as the PAL signal. The data output from the first coding circuit 5 and the second coding circuit 6 are applied to the first SYNC block data generation circuit 7 and the second SYNC block data generation circuit 8, respectively. In the SYNC block data generation circuits 7 and 8 shown in FIG.5, the memory 94 comprises a plurality of areas of SYNC block data 111 as shown in FIG.12B. One SYNC block data 111 corresponds to one macro block M i,j,k . The coded data of a macro block M i,j,k are stored in predetermined image data areas 119 --- 126 in units of one DCT block. In the storing operation, the low frequency component of the data of video image has priority. Data which overflows from an image data area is stored in other image data area having space in the same image data areas 119 --- 126. Data which overflow from the image data areas 119 --- 126 are stored in areas of other SYNC block data. Additionally, the data of "additional information" 127 is also stored. Consequently, the coded data of a macro block M i,j,k is stored in a corresponding SYNC block data 111. Referring to FIG.5, the SYNC block data 111 is read out from the memory 94 in compliance with the control signal of the read address control circuit 93, and is output to the terminal 95. The output data of the first SYNC block data generation circuit 7 and the second SYNC block data generation circuit 8 are inputted to the first recording signal processing circuit 9 and the second recording signal processing circuit 10, respectively. A SYNC block data is represented by U i,j,k , and one SYNC block data U i,j,k comprises main components of the data after data compression operation of one macro block M i,j,k . In the first recording signal processing circuit 9 and the second recording signal processing circuit 10, a predetermined SYNC pattern and ID data are attached to the SYNC block data, and is output to the terminal 107. Subsequently, the SYNC block data are applied to the recording heads 13A, 13B, 14A and 14B through the respective recording amplifiers 11 and 12, and are recorded in the magnetic tape 15. The recording operation of the HDTV signal is performed by the first combination heads 13A and 14A and the second combination heads 13B and 14B. The tape moving speed for recording the HDTV signal is substantially as fast as twice of the tape moving speed in the PAL signal. Two recording tracks are formed by first combination heads 13A and 14A during a half revolution period of the rotating cylinder, and successive two recording tracks neighboring to the former two recording tracks are formed by the second combination heads 13B and 14B during successive half revolution period. Consequently, the video signal of one frame is recorded in 24 video tracks 140 --- 163 as shown in FIG.14. Referring to FIG.14, the video tracks of even number are formed by heads 13A and 13B and the video tracks of odd number are formed by heads 14A and 14B. The order of the SYNC block data of data Ti which are recorded on a video track of the number "i" in the 24 video tracks is represented by Equation (6). T i = { U i, 0, 0 ,···, U i, 0, 26 , U i, 1, 0 ,···, U i, 1, 26 , U i, 2, 0 ,···, U i, 2, 26 , U i, 3, 0 ,···, U i, 3, 26 , U i, 4, 0 ,···, U i, 4, 26 } (i = 0, ···, 23). As mentioned above, in the apparatus for recording and reproducing the digital video signal in the first embodiment, when the PAL signal or the HDTV signal is inputted to the input terminal 1 or 2, respectively, the switches 37, 38 and 39 are activated by a control circuit (not shown), and the inputted video signal is applied to the FIFOs 40 --- 44 and the above-mentioned operation performed. [Reproducing operation in the first embodiment] In the apparatus for recording and reproducing the digital video signal in the first embodiment, the reproducing operation of the recorded data is described hereafter with reference to FIG.1. The recorded data is reproduced by reproducing combination heads 16A, 17A and 16B, 17B, and are applied to a first reproducing signal processing circuit 20 and a second reproducing signal processing circuit 21 through respective amplifiers 18 and 19. The reproduced SYNC block data is converted to the coded data in the units of one macro block in a first coded data restoration circuit 22 or a second coded data restoration circuit 23. Subsequently, the coded data is converted to the original macro block data in a first decoding circuit 24 or a second decoding circuit 25. The macro block data is converted to an analog signal by a deblocking circuit 26 and a data rate inversion circuit 27, and the analog PAL signal is output to a terminal 28. On the other hand, in a similar manner, a reproduced HDTV signal is output to a terminal 29. The circuit configuration for the reproducing operation as shown in FIG.1 is well known in the art, and the detailed description is omitted. Though the HDTV signal of 1250/50 system is converted to the known 12:4:0 format in the above-mentioned embodiment, the HDTV signal may be converted to the known 16:8:0 format. In this case, one macro block comprises 8 DCT blocks of the Y signal,2 DCT blocks of the (R-Y) signal and 2 DCT blocks of the (B-Y) signal. One macro block is made to correspond to one SYNC block data in the 16:8:0 format. The ratio of the number of macro blocks of HDTV signal to that of the PAL signal is 2:1, and the recording operation may be performed by the above-mentioned circuit configuration as shown in FIG.1. [Second embodiment of blocking circuit] The second example of the blocking circuit 4A is shown in FIG.16. Referring to FIG.16, terminals 180, 181 and 182 correspond to the terminals 51, 52 and 53 in FIG.3, respectively. Terminals 198 and 199 correspond to the terminals 74 and 75 in FIG.3, respectively. Since the operation of the blocking circuit 4A in the PAL signal is similar to the operation in the blocking circuit 4 shown in FIG.3, the description is omitted. In the signal processing operation of the HDTV signal, two memories 188 and 189 are used in parallel to rearrange the data of the HDTV signal. In operation, common address data are applied to two memories 188 and 189 from a write address control circuit 190 or a read address control circuit 191 to control the two memories 188 and 189. The Y signal is applied to FIFOs 183 and 184 through a terminal 180, the (R-Y) signal is applied to an FIFO 185 through a terminal 181 and the (B-Y) signal is applied to an FIFO 186 through a terminal 182. The data rate of inputted data is converted by the FIFOs 183 --- 186, and block data are formed. In the Y signal, one horizontal line is divided into plural sections each having 24 pixels. Moreover, the 24 pixels are divided into 16 pixels and 8 pixels. The data of 16 pixels is inputted to the FIFO 183, and the data of 8 pixels is inputted to the FIFO 184. In the (R-Y) signal and (B-Y) signal, one horizontal line is divided into plural sections each having 8 pixels. Subsequently, the data of 8 pixels is output from the FIFO 184 in synchronism with output of the data of 16 pixels from the FIFO 183. Moreover, the data of 8 pixels is output from the FIFO 185 or the FIFO 186. Since the (R-Y) signal and the (B-Y) signal exist on alternate horizontal lines, the data of the (R-Y) signal or the (B-Y) signal which exists on each horizontal line is inputted to the selector 187. The Y signal of 16 pixels is inputted to the memory 188, and the Y signal of 8 pixels and the (R-Y) signal or the (B-Y) signal of 8 pixels are inputted to the memory 189 through the selector 187. Consequently, data of a mini-block comprising Y signal of 24 pixels and the (R-Y) signal of 8 pixels and the (B-Y) signal of 8 pixels in one horizontal line are written in two memories 188 and 189 on the basis of the control signal of the write address control circuit 190. Subsequently, the stored data are read out from the memories 188 and 189 on the basis of the control signal of the read address control circuit 191, and are inputted to an FIFO 192 or an FIFO 194 in units of macro block. Moreover, the data read out from the memory 189 is inputted to an FIFO 193 or an FIFO 195 in units of macro block. In FIG.15, a mini-block is composed of the data of pixel Y 0,0, ··· , Y 0,23 and r 0,0, ··· , r 0,7 or a mini-block is composed of the data of pixels Y 0,0, ··· , Y 0,23 and b 0,0, ··· , b 0,7 , for example. The data of each macro block is output to a terminal 198 through a selector 196 or output to a terminal 199 through a selector 197. The orders of macro blocks output from the terminals 198 and 199 are shown by Equations (4) and (5), respectively. [Third embodiment of blocking circuit] FIG.17 is a block diagram of a third example of blocking circuit 4B. Referring to FIG.17, terminals 200, 201 and 202 correspond to the terminals 51, 52 and 53 as shown in FIG.3, respectively. Terminals 212 and 213 correspond to the terminals 74 and 75 as shown in FIG.3, respectively. Signal processing operation of the PAL signal is similar to that of the first example of the blocking circuit 4, and the description is omitted. Signal processing operation of the HDTV signal is described hereafter. In the blocking circuit 4B, one memory 207 is used to rearrange the data. The Y signal is inputted to an FIFO 203 through the terminal 203. Moreover, the (R-Y) signal is inputted to an FIFO 204 through the terminal 201, and the (B-Y) signal is inputted to an FIFO 205 through the terminal 202. The inputted data are formed to block data by these FIFOs 203, 204 and 205. In Y signal, one horizontal line of the video image is divided into plural sections each having 24 pixels. In the (R-Y) signal and (B-Y) signal, one horizontal line is divided into plural sections each having 8 pixels. The Y signal of 24 pixels is written in the memory 207 through a selector 206. Moreover, the (R-Y) signal or the (B-Y) signal of 8 pixels is alternately written in the memory 207 through the selector 206. Consequently, the data of the mini-block comprising the Y signal of 24 pixels and the (R-Y) signal or Y signal of 24 pixels and (B-Y) signal of 8 pixels are stored in the memory 207 on the basis of a control signal of a write address control circuit 208. Subsequently, the stored data are read out from the memory 207 on the basis of a control signal of a read address control circuit 209 so as to form macro blocks, and are applied to an FIFO 210 or an FIFO 211. For example, the mini-block is composed of data of pixels Y 0,0, ··· ,Y 0,20 and r 0,0, ··· , r 0,7 , or data of Y 0,0, ...,Y 0,23 and b 0,0, ··· , b 0,7 . The data of each macro block are output to terminals 212 and 213. The orders of the macro blocks output from the terminals 212 and 213 are represented by Equations (4) and (5), respectively. In the apparatus for recording and reproducing the digital video signal in the first embodiment, the NTSC signal (525/60 system) is inputted as the first video signal. The second video signal is the HDTV signal (1050/60 system). [Recording operation of NTSC signal] Referring to FIG.1, the NTSC signal is inputted to the terminal 1 of the data rate conversion circuit 3. In FIG.2, the FIFOs 40 --- 44 serve as delay elements for delaying a time period corresponding to several pixels, and a digital video signal of the known 4:1:1 format is output from the terminals 47 --- 49. In the blocking circuit 4 shown in FIG.3, the video image of one frame is converted to macro blocks of 4:1:1 format, and the order of the macro block M i,j,k (i = 0, 1, ···, 8, 9; j = 0, 1, 3, 4; k = 0, 1, · · ·,25, 26) is set. Moreover, the video image of one frame is divided into 22.5 macro blocks in the horizontal direction and 60 macro blocks in the vertical direction, and divided into 50 super blocks S i,j as shown in FIG.18. The above-mentioned blocking operation is realizable by the blocking circuit 4A or 4B shown in FIG. 16 and FIG.17, respectively. By the above-mentioned blocking operation, video segments V i,k represented by Equations (7) and (8) are output. V i,k = { M (i+2) mod 10, 2, k , M (i+6) mod 10, 1, k , M (i+8) mod 10, 3, k , M (i+0) mod 10, 0, k , M (i+4) mod 10, 4, k } (i = 0, 2,···,8; k = 0,···,26). V i,k = { M (i+2) mod 10, 2, k , M (i+6) mod 10, 1, k , M (i+8) mod 10, 3, k , M (i+0) mod 10, 0, k , M (i+4) mod 10, 4, k } (i = 1, 3, ···,9; k = 0,···,26). As shown in the Equation (7), the macro blocks M i,j,k in the super blocks S i,j having even number in the vertical direction are output from the terminal 74. Moreover, as shown in the Equation (8), the macro blocks M i,j,k in the super blocks S i,j having odd number in the vertical direction are output from the terminal 75. The data of one video segment represented by the Equation (7) are processed, in a manner similar to the first embodiment, by the first coding circuit 5, the first SYNC block data generation circuit 7 and the first recording signal processing circuit 9, and are applied to the heads 13A and 13B through the recording amplifier 11. The data of the other video segment data are processed by the second coding circuit 6, the second SYNC block data generation circuit 8 and the second recording signal processing circuit 10, and are applied to the heads 14A and 14B through the recording amplifier 12. In a manner similar to the first embodiment, one SYNC block data U i,j,k comprises the main components of data after data compression of one macro block M i,j,k , and the video signal of one frame is recorded in ten video tracks of the magnetic tape 15. The order of the SYNC block data of the data Ti which are recorded in the video track having the number "i" is represented by Equation (9). Ti = { U i, 0, 0 ,···, U i, 0, 26 , U i, 1, 0 ,···,U i, 1, 26 , U i, 2, 0 ,···,U i, 2, 26 , U i, 3, 0 ,···,U i, 3, 26 , U i, 4, 0 , ···,U i, 4, 26 } (i = 0, ···, 9). [Recording operation of HDTV signal (1050/60 system)] Subsequently, recording operation of the HDTV signal of 1050/60 system is described hereafter. In the data rate conversion circuit 3 of FIG.1, the Y signal of one frame is converted to data of the product of 1080 pixels in the horizontal direction by 960 lines in the vertical direction, the (R-Y) signal is converted to the data of the product of 360 pixels in the horizontal direction by 480 lines in the vertical direction and the (B-Y) signal is converted to the data of the product of 360 pixels in the horizontal direction by 480 lines in the vertical direction. Consequently, the video image of one frame is converted to the digital data of the known 12:4:0 format. In the blocking circuit 4, the video image of one frame is divided into 45 sections in the horizontal direction and 60 sections in the vertical direction. Consequently, the video image of one frame is divided by the macro block 109 as shown in FIG.8. Moreover, as shown in FIG.19, the video image of one frame is divided into a plurality of super blocks S i,j . The arrangement of the macro blocks M i,j,k (i = 0, 1, · · ·,19; J = 0, 1, 2, 3, 4; k = 0, 1, ···, 26) in one super block S i,j is shown in FIG.11. The video segments V i,k output from two terminals 74 and 75 of the blocking circuit 4 are represented Equations (10) and (11), respectively. V i,k = { M (i+4) mod 20, 2, k , M (i+12) mod 20, 1, k , M (i+16) mod 20, 3, k , M (i+0) mod 20, 0, k , M (i+8) mod 20, 4, k } (i = 0, 2, ···,16, 18; k = 0,···,26). V i,k = { M (i+4) mod 20, 2, k , M (i+12) mod 20, 1, k , M (i+16) mod 20, 3, k , M (i+0) mod 20, 0, k , M (i+8) mod 20, 4, k } (i = 1, 3, ···, 17, 19; k = 0, ···, 26). As shown by the Equation (10), the macro blocks M i,j,k in the super blocks S i,j having even number in the vertical direction are output to the terminal 74. Moreover, as shown by the Equation (11), the macro blocks M i,j,k in the super blocks S i,j having the odd number in the vertical direction are output from the terminal 75. As mentioned above, the video segments V i,k output from the blocking circuit 4 are processed in a manner similar to the first embodiment, and are applied to the heads 13A, 13B, 14A and 14B through the respective recording amplifiers 11 and 12. One SYNC block data U i,j,k comprises the main components of the data after data compression of one macro block M i,j,k , and the video signal of one frame is recorded in 20 video tracks of the magnetic tape 15. The order of SYNC block data U i,j,k of the data Ti which are recorded in the video track having the number "i" is represented by Equation (12). T i = { U i, 0, 0 , ···, U i, 0, 26 , U i, 1, 0 ,···,U i, 1, 26 , U i, 2, 0 ,···, U i, 2, 26 , U i, 3, 0 ,···,U i, 3, 26 , U i, 4, 0 ,···,U i, 4, 26 } (i = 0, ··· , 19). [Recording operation of HDTV signal (1125/60 system)] In the apparatus for recording and reproducing the digital video signal as shown in FIG.1, the HDTV signal of 1125/60 system is inputted to the terminal 2 of the data rate conversion circuit 3 as the second video signal. In the data rate conversion circuit 3, the Y signal of one frame is converted to the data of the product of the 1008 pixels in the horizontal direction by 1024 lines in the vertical direction, the (R-Y) signal is converted to the data of the product of 336 pixels in the horizontal direction by 512 lines in the vertical direction and the (B-Y) signal is converted to the data of the product of 336 pixels in the horizontal direction by 512 lines in the vertical direction. Consequently, the video image of one frame is converted to the digital video data of 12:4:0 format. In the blocking circuit 4, as shown in FIG.20A, the video image 401 of one frame is divided into 42 sections in the horizontal direction and 64 sections in the vertical direction, and the macro blocks of the product of 42 by 64 (2688) are formed. Subsequently, the video image 401 of one frame is divided into super blocks S i,j (i = 0, 1, ···, 19; j = 0, 1, 2, 3) having 9 macro blocks in the horizontal direction and 3 macro blocks in the vertical direction in the central portion of the video image 401. Subsequently, the area of 2 macro blocks in the vertical direction on the upper portion of the video image 401 is divided into sections each having 9 macro blocks in the horizontal direction and 1 macro block in the vertical direction, and hence blocks A 0, , A 1 , A 2 , A 3 , A 4 , A 5 , A 6 and A 7 are formed. Moreover, the area of 2 macro blocks in the vertical direction on the lower portion of the video image 401 is divided into sections each having 9 macro blocks in the horizontal direction and 1 macro block in the vertical direction, and blocks A 10 , A 11 , A 12 , A 13 , A 14 , A 15 , A 16 and A 17 are formed. Moreover, the right portion of the video image 401 is divided into super blocks S' i,j (i = 0, 1, 2, · ,18, 19; j = 4) of a first type which comprise 6 macro blocks in the horizontal direction and 3 macro blocks in the vertical direction. The upper portion and the lower portion of the right end part of the video image 401 is divided into blocks A 8 , A 9 , A 18 and A 19 of a second type each having 6 macro blocks in the horizontal direction and 1 macro block in the vertical direction. The blocks as shown in FIG.20A are rearranged to the block arrangement of 45 macro blocks in the horizontal direction and 60 macro blocks in the vertical direction as shown in FIG.20B. In the rearrangement operation, as shown in FIG.20C, the block A i (i = 0, 1, ···, 7, 10, 11, ···, 17) in the block configuration as shown in FIG.20A is rearranged to a block Bi of a third type as shown in FIG.20D. Referring to FIG.20C and FIG.20D, a belt-shaped block A i is rearranged to a square block B i . On the other hand, a belt-shaped block A i (i = 1, 9, 18, 19) is also rearranged to a square block B i , but the latter square block B i has only 6 macro blocks, and 3 blocks in the lower part of the block Bi is filled with 3 "dummy macro blocks" D.' The dummy macro blocks D have no video image data. In FIG.20B, the block S' 0,4 and the block B 0 are collected to a super block S 0,4 . In a similar manner, the blocks S' 1,4 and B 1 are collected to S 1,4 , the blocks S' 2,4 and B 2 are collected to S 2,4 and the blocks S' 19,4 and B 19 are collected to S 19,4 . Consequently, blocks S 1,4 , S 2,4 , ···,S 19,4 are formed. By the above-mentioned rearrangement of the data block, the HDTV signal of 1125/60 system is converted to the same format as the HDTV signal of the above-mentioned 1050/60 system. Therefore, the HDTV signal of the 1125/60 system may be processed in the order represented by the Equations (10) and (11). Finally, SYNC block data of the HDTV signal in the 1125/60 system are formed and the SYNC block data of one frame is recorded in the 20 video tracks of the magnetic tape 15 as shown in FIG. 14. In the above-mentioned first embodiment, the first and second coding circuits 5 and 6, the first and second SYNC block data generation circuits 7 and 8 and the first and second recording signal processing circuits 9 and 10 are configurated by two channel circuits. When both the PAL signal and HDTV signal are processed by two channel circuits, the processing time for the PAL signal is half of that of the HDTV signal. In actual use, the PAL signal or NTSC signal may be processed by both the first and second recording signal processing circuits 9 and 10 through the first coding circuit 5 and the first SYNC block data generation circuit 7. In this case, the data represented by Equation (1) is processed by the first recording signal processing circuit 9, and the data represented by Equation (2) is processed by the second recording signal processing circuit 10. The HDTV signal may be processed by the two channel circuits. [Second embodiment of apparatus for recording and reproducing the digital video signal] FIG.21 is a block diagram of the apparatus for recording and reproducing the digital video signal in the second embodiment. In the second embodiment, the data rate conversion circuit 303 is substantially identical with the data rate conversion circuit 3 in FIG. 1. The blocking circuit 304 is illustrated in detail in FIG.22. A first coding circuit 305, a second coding circuit 306 and a third coding circuit 307 are configurated by the circuit shown in FIG.4. A first SYNC block data generation circuit 308, a second SYNC block data generation circuit 309 and a third SYNC block data generation circuit 310 are configurated by the circuit shown in FIG.5. A 3CH/2CH conversion circuit 311 is illustrated in detail in FIG. 23. The first recording signal processing circuit 9, the second recording signal processing circuit 10, the recording amplifiers 11 and 12 and the heads 13a, 13b, 14a and 14b are identical with the elements having the same reference numerals in FIG.1. The first video signal of the PAL signal is inputted to a terminal 301, and the second video signal of the HDTV signal(1250/50 system) is inputted to a terminal 302 of the data rate conversion circuit 303. In the data rate conversion circuit 303, the inputted video signal is converted into a digital signal and the data rate thereof is also converted. Consequently, the PAL signal is converted into the known 4:2:0 format and the HDTV signal is converted into the known 12:4:0 format. [Recording operation of PAL signal in the second embodiment] In the blocking circuit 304 as shown in FIG.22, the Y signal is applied to the memory 355 through an input terminal 340, a FIFO 343 and a selector 352. Moreover, the (R-Y) signal is applied to the memory 355 through a terminal 341, a FIFO 346 and the selector 352, and the (B-Y) signal is applied to the memory 355 through a terminal 342, a FIFO 349 and the selector 352. The data of 16 pixels of the Y signal and data of 8 pixels of the (R-Y) signal or the (B-Y) signal are written in the memory 355 as a mini-block, by a control signal from a right address control circuit 358. Subsequently, the data of the macro block are read out of the memory 355 in the orders of the data represented by the Equations (1) and (2), and output to a terminal 360. The data of the macro blocks are inputted to the first coding circuit 305 and are coded. The coded data are applied to the first SYNC block data generation circuit 308, and thereby the SYNC block data is generated in a manner similar to the first embodiment. The SYNC block data is inputted to a 3CH/2CH conversion circuit 311 as shown in detail in FIG.23. In the 3CH/2CH conversion circuit in FIG.23, the data inputted from terminal 370 is distributed to a FIFO 373 or a FIFO 376 in units of SYNC block data. The SYNC block data output from a terminal 381 of the 3CH/2CH conversion circuit 311 is a SYNC block data including main components after data compression of the macro blocks represented by Equation (1). The SYNC block data output from a terminal 382 of the 3CH/2CH conversion circuit 311 through the FIFO 376 and a selector 380 includes main components after data compression of the macro blocks represented by the Equation (2). Consequently, the SYNC block data inputted from the input terminal 370 is distributed to two output terminals 381 and 382. These SYNC block data are applied to the respective first recording signal processing circuit 9 and the second recording signal processing circuit 10, and are recorded in the magnetic tape 15 in a manner similar to the first embodiment. The order of the SYNC block data to be recorded in a video track is represented by the Equation (3). [Recording operation of HDTV signal (1250/50 system) of the second embodiment] Subsequently, recording operation of the HDTV signal (1250/50 system) is described hereafter. Referring to FIG.21, the HDTV signal inputted to the terminal 302 is converted to a digital signal in the data rate conversion circuit 303, and the data rate is also converted. The digital data is inputted to the blocking circuit 304. In the blocking circuit 304 shown in FIG.22, the data of Y signal of one horizontal line is divided into sections each having 24 pixels, and the data of the sections are inputted to the FIFOs 343, 344 and 345 in turn through the terminal 340. Moreover, the (R-Y) signal of one horizontal line is divided into sections each having 8 pixels, and the data of sections are inputted to the FIFOs 346, 347 and 348 in turn through a terminal 341. And the (B-Y) signal of one horizontal line is also divided into sections each having 8 pixels and the data of sections are inputted to FIFOs 349, 350 and 351 in turn through a terminal 342. Subsequently, the data are read out from the FIFOs 343, 346 and 349, and are applied to the memory 355 through the selector 352. The data read out from the FIFOs 344, 347 and 350 are inputted to the memory 356 through the selector 353. Moreover, the data read out from the FIFOs 345, 348 and 351 are inputted to the memory 357 through the selector 354. The data inputted to the memory 355 is designated by "channel 1", the data inputted to the memory 356 is designated by "channel 2" and the data inputted to the memory 357 is designated by "channel 3". Consequently, the video image of one frame is divided into rectangular areas which are sectioned in the horizontal direction every 24 pixels. The rectangular area is designated by channel 1, channel 2, and channel 3 in the order of from left to right in the video image. The number of pixel of one section in the horizontal direction is identical with the number of pixel of one macro block. The data of three channels are simultaneously written in the three memories 355, 346 and 357 by the control signal of the write address control circuit 358. Namely, the data of pixels of three macro blocks in the horizontal direction are simultaneously written in the memories. Subsequently, data of successive three macro blocks in the horizontal direction are read out from the memories 355, 346 and 357 by the control signal of the read address control circuit 359. The data of the macro blocks of the channels 1, 2 and 3 are applied to the first coding circuit 305, the second coding circuit 306 and the third coding circuit 307 through the terminals 306, 361 and 362, respectively. The configuration of the first coding circuit 305, the second coding circuit 306 and the third coding circuit 307 are identical with the coding circuit 5 shown in FIG.5 and perform the same operation as the coding circuit 5. The output data of the first coding circuit 305 is applied to the first SYNC block data generation circuit 308, the output data of the second circuit 306 is applied to the second SYNC block data generation circuit 309 and the output data of the third coding circuit 307 is applied to the third SYNC block data generation circuit 310. The circuit configurations of the first SYNC block data generation circuit 308, the second SYNC block data generation circuit 309 and the third SYNC block data generation circuit 310 are identical with the circuit configuration of the SYNC block data generation circuit 7 shown in FIG.5. The SYNC block data generated by the first, second and third SYNC block data generation circuits 308, 309 and 310 are applied to the 3CH/2CH conversion circuit 311. The input data of three channels are converted to two channels by the 3CH/2CH conversion circuit 311, and are output to the terminal 381 as the SYNC block data including main components after data-compression of one macro block as shown by Equation (4). Moreover, SYNC block data as shown by Equation (5) is output to the terminal 382. These SYNC block data are recorded on the magnetic tape 15 which is moved at about twice speed with respect to the tape moving speed in the PAL signal through the respective recording signal processing circuits 9 and 10 and recording amplifiers 11 and 12. The order of data which are recording on the video tracks are represented by Equation (6). [Reproducing operation of PAL signal] In the reproducing operation of the PAL signal, in a manner similar to the first embodiment, reproduced data by the reproducing heads 16A and 16B are applied to the 2CH/3CH conversion circuit 325 through the reproducing amplifier 18 and the first reproducing signal processing circuit 20 and the reproduced data by the reproducing heads 17A and 17B are applied to the 2CH/3CH conversion circuit 325 through the first reproducing signal processing circuit 19 and the second recording signal processing circuit 21. In the 2CH/3CH conversion circuit, the data of the PAL signal is converted to the data of one channel, and is applied to the first coded data restoration circuit 326. The PAL signal is output to the terminal 334 through the first decoding circuit 329, deblocking circuit 332 and the signal rate inversion circuit 333. [Reproducing operation of the HDTV signal in the second embodiment] In the reproducing operation of the HDTV signal, reproduced data by the reproducing heads 16A and 16B are applied to the 2CH/3CH conversion circuit 325 through the reproducing amplifier 18 and the first reproducing signal processing circuit 20, and the reproduced data by the reproducing heads 17A and 17B are applied to the 2CH/3CH conversion circuit 325 through the reproducing amplifier 19 and the second reproducing signal processing circuit 21. The data of the HDTV signal are converted to three channel data by the 2CH/3CH conversion circuit 325. The data of three channels are applied to the deblocking circuit 332 through the respective coded data restoration circuits 326, 327 and 328 and decoding circuits 329, 330 and 331. Consequently, the HDTV signal is output to the terminal 335 through the deblocking circuit 332 and the signal rate inversion circuit 333. As mentioned above, in the apparatus for recording and reproducing the digital video signal of the second embodiment, the PAL signal of 625/50 system and the HDTV signal of 1250/50 system are recorded or reproduced. Moreover, in the apparatus for recording and reproducing the digital video signal of the second embodiment, the NTSC signal (525/60 system) and the HDTV signal (1050/60 system) or the NTSC signal and the HDTV signal (1125/60 system) may be recorded and reproduced in a similar manner mentioned above. In FIG.20B, the super blocks of the HDTV signal of 1125/60 system comprise the macro blocks of a multiple of 3 in the horizontal direction. Therefore, the HDTV signal of 1125/60 system is easily processed by the blocking circuit 304 having three channels as shown in FIG.22. The unit for processing the macro block data at the end part of the video image is equalized to the unit for processing the macro block data in the central portion of the video image. Therefore, rearrangement of the data in the blocking circuit 304 is easily performed. Moreover, as shown in FIG.23, 3CH/2CH conversion circuit 311 may be configurated by a relatively simplified circuit. Data of the HDTV signal of 1125/60 system may be processed by rearrangement of data as shown in FIG.20A, FIG.20B, FIG.20C and FIG.20D, and three channel processing operation may be performed by dividing the video image in a manner similar to FIG.24. Incidentally, in the case that only the HDTV signal is recorded in the apparatus for recording and reproducing the digital video signal in the above-mentioned embodiments, only three ADCs 31,32 and 33 are required in the data rate conversion circuit 3.

Claims: A method for recording and reproducing digital video signals representing pixels of frames of television signals, the method comprising the steps of: selecting a low resolution digital video signal or a high resolution digital video signal for input, the high resolution digital video signal representing frames having a higher number of pixels than the frames represented by the low resolution digital video signal; inputting data representing one frame of the selected video signal; forming the inputted data representing one frame to a number of video segments (V i,k ); data-compressing the video segments (V i,k ); generanting synchronizing block data by storing the data-compressed video segments in synchronizing blocks; recording the synchronising block data on a recording medium; the step of forming the number of video segments (V i,k ) comprising the steps of: dividing the frame into a number of macro blocks (M i,j,k ), this number being higher for the high resolution digital video signal than for the low resolution digital video signal; dividing the frame into a number of super blocks (S i,j ), this number being higher for the high resolution digital video signal than for the low resolution digital video signal; wherein each superblock (S i,j ) is formed by a predetermined number of macro blocks (M i,j,k ), this predetermined number being equal for both the high resolution digital video signal and the low resolution digital video signal; setting up an order of macro blocks in one super block and sequentially designating each macroblock in this order as a designated macro block, forming a number of video segments (V i,k ) wherein each video segment is formed of corresonding designated macroblocks in selected ones of said super blocks (S ij ). The method according to claim 1, wherein the low resolution digital video signal has 625 scanning lines per one frame and 50 fields per one second, the high resolution digital video signal has 1250 scanning lines per one frame and 50 fields per one second, the low resolution digital video signal is converted to 4 : 2 : 0 format, the high resolution digital video signal is converted to 12 : 4 : 0 format, the number of pixels of the macro block of the low resolution digital video signal is 256 pixels of a luminance signal, namely 16 pixels horizontally times 8 lines vertically times 2 fields, 64 pixels of a first color difference signal (R-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and 64 pixels of a second color difference signal (B-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and the number of pixels of the image block of the high resolution digital video signal is 384 pixels of the luminance signal, namely 24 pixels horizontally times 8 lines vertically times 2 fields, 64 pixels of the first color difference signal (R-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and 64 pixels of the second color difference signal (B-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields. The method according to claim 1, wherein the low resolution digital video signal has 525 scanning lines per one frame and 60 fields per one second, the high resolution digital video signal has 1050 or1125 scanning lines per one frame and 60 fields per one second, the low resolution digital video signal is converted to 4 : 1 : 1 format, the high resolution digital video signal is converted to 12 : 4 : 0 format, the number of pixels of the macro block of the low resolution digital video signal is 256 pixels of a luminance signal, namely 32 pixels horizontally times 4 lines vertically times 2 fields, 64 pixels of a first color difference signal (R-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and 64 pixels of a second color difference signal (B-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and the number of pixels of the image block of the high resolution digital video signal is 384 pixels of the luminance signal, namely 24 pixels horizontally times 8 lines vertically times 2 fields, 64 pixels of the first color difference signal (R-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields, and 64 pixels of the second color difference signal (B-Y), namely 8 pixels horizontally times 4 lines vertically times 2 fields. The method according to one of claims 1 to 3, wherein twenty seven macro blocks (M i,j,k ) form each superblock (S i,j ) in an arrangement of nine macro blocks horizontally and three macro blocks vertically. An apparatus for recording and reproducing digital video signals representing pixels of frames of television signals by performing the method according to one of claims 1 to 4, the apparatus comprising: input means (51, 52, 53) for inputting a low resolution digital video signal or a high resolution digital video signal, the high resolution digital video signal representing frames having a higher number of pixels than the frames represented by the low resolution digital video signal; means (4) for forming the inputted data representing one frame to a number of video segments (V i,k ); compressing means (5, 6) for data-compressing the video segments (V i,k ); synchronizing block data generation means (7, 8) for generating synchronizing block data by storing the data-compressed video segments in synchronizing blocks; recording means (9, 10, 11, 12, 13, 14) for recording the synchronizing block data on a recording medium; said means (4) for forming the video segments comprising: means (61, 62, 63, 64, 65) for dividing the frame into a number of macro blocks (M i,j,k ), this number being higher for the high resolution digital video signal than for the low resolution digital video signal; means (61, 62, 63, 64, 65) for dividing the frame into a number of super blocks (S i,j ), this number being higher for the high resolution digital video signal than for the low resolution digital video signal; wherein each superblock (S i,j ) is formed by a predetermined number of macro blocks (M i,j,k ), this predetermined number being equal for both the high resolution digital video signal and the low resolution digital video signal; means for setting up an order of macroblocks in one superblock, for sequentially designiating each macroblock in this order as a designated macroblock and for forming video segments (V i,k ); wherein each video segment is formed of corresponding designated macroblocks in selected ones of the superblocks (S i,j ).

Inventors: JURI TATSURO, NISHINO MASAKAZU, UCHIDA HIROFUMI, JURI, TATSURO, NISHINO, MASAKAZU, UCHIDA, HIROFUMI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H04N9
IPC codes: H04N9, H04N5, G11B20