Combination drive-summing circuit for rail-to-rail differential amplifier

Abstract: A combination driver/summing circuit for rail-to-rail operation of a differential amplifier includes a differential amplifier input stage (Q I1 -Q I4 ) that amplifies an input signal and a current control circuit (Q I5 ) that regulates the operating currents through the active elements of the differential amplifier input stage. A summing circuit (Q S1 -Q S8 ) divided into first and second segments and supplied with current from a single common floating current source (15) combines internal currents supplied by the differential amplifier input stage. A class A-B driver/output stage (Q D1 -Q D8 /Q O1 -Q O8 )is coupled to the summing circuit to derive at least one output signal representative of the input signal and which is operative over nearly the full rail-to-rail supply voltage range.

Description: BACKGROUND OF THE INVENTION The present invention relates generally to the field of differential amplifiers and operational amplifiers and more particularly to an amplifier of this kind fabricated in integrated circuit technology and having a rail-to-rail common mode range at the amplifier input and output. There are times when an operational amplifier is required which can linearly amplify an input signal over nearly the full supply voltage range, especially in the case of a supply voltage as low as 1.5 volts. Operational amplifiers to be used with low supply voltages should utilize as much as possible of the available supply voltage range in order to obtain the best signal-to-noise ratio. This requirement is especially severe in the case of low power applications or when the supply voltage is low as in battery powered systems. U.S. Patent 4,555,673 issued 11/26/85 in the name of J.H. Huijsing et al and an article by J.H. Huijsing et al in the IEEE JSSC, vol. SC-20, No. 6, 12/85, entitled "Low Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges", describe circuits which generally work well to amplify an input signal while using a large part of the supply voltage range. The Huijsing et al article describes an operational amplifier having rail-to-rail input, a so-called folded cascode stage and a rail-to-rail class A-B output stage. The input stage with a rail-to-rail common-mode input voltage range provides a constant transconductance over the full common-mode range. However, this operational amplifier also requires an intermediate stage to increase the gain and a completely separate class A-B quiescent bias network. Another disadvantage of the Huijsing et al operational amplifier is that it requires a fairly large number of integrated circuit components. In the Huijsing et al patent and article the rail-to-rail common-mode voltage swing at the amplifier input is obtained by using two differential amplifier input stages in parallel and operating same such that the common-mode (CM) voltage of one stage can reach the positive supply voltage rail and that of the other the negative supply voltage rail. Three common-mode input voltage ranges are present in these circuits. In a first range, which extends from the negative supply voltage to an intermediate range, only one differential amplifier input stage is operative. In a second range extending from the positive supply voltage to the intermediate range, the other differential amplifier input stage is operative. In the intermediate range, both differential amplifier stages are in operation. The Huijsing et al patent describes an improved differential amplifier with a rail-to-rail input capability which attempts to correct the problem of a variation in the amplifier transconductance as the input common-mode voltage varies across the supply voltage range. The patent describes a current steering control circuit that regulates the operating currents for the two differential amplifiers such that the overall amplifier transconductance is controlled to be substantially constant as the common-mode voltage of the amplifier input signal varies across the supply voltage range. A summing circuit selectively combines internal currents supplied by the two differential amplifiers so as to derive at least one output signal representative of the input signal. Another prior art operational amplifier is described in an article by D.M. Monticelli entitled "A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing, in the IEEE JSSC, Vol. SC-21, No. 6, December 1986. This article describes a Quad CMOS amplifier which includes a class A-B output stage with quiescent current biasing. This op-amp circuit does not have a rail-to-rail input and does not use a folded cascode arrangement. It also requires two independent matched internal current sources for class AB quiescent current biasing so that any mismatch therebetween will result in a contribution to the input offset voltage. Furthermore, the Monticelli circuit does not eliminate the dependence of the quiescent bias current in the output transistors of the class A-B output stage on the voltage supply. Further background information can be obtained from a review of U.S. Patents 4,893,091 (1/9/90); 4,958,933 (9/18/90) and 4,797,631 (1/10/89). U.S. Patent 4,797,631 describes a rail-to-rail input stage and folded cascode stage. The circuit does not include a class A-B output stage or floating current source. Although this patent shows an input stage and a folded cascode stage, it does not include the current steering transistor of the Huijsing et al patent in the differential input stage and which transfers current from one current source transistor to the other as the input signal traverses the input common mode range. Thus, it does not maintain a constant current gain in the input stage, as is accomplished in the op-amp described in Huijsing et al patent discussed above. U.S. Patent 4,958,133 also describes a rail-to-rail input stage and a folded cascode stage, but again does not include a class A-B output stage, floating current source or current steering transistors in the input stage. A disadvantage of this circuit is that it does not maintain the bias currents constant. U.S. Patent 4,893,091 describes an amplifier with a class A-B output stage. However, this patent uses an intermediate gain stage between the input and output and wherein the output is a common collector driver. The requirement of an intermediate amplifier stage is a major disadvantage of this patent. In the article "A digital process compatible with high-drive CMOS op-amp with rail-to-rail input and output ranges" by WEN-CHUNG S. WU et al. on pages 692 to 695 of the Proceedings of the 33rd Midwest Symposium or Circuits and Systems hold in Calgary, Alberta, Canada on 12-15 August 1990, a differential amplifier is shown which uses a floating current source which is formed from two current mirrors. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide a combined driver and summing circuit for a rail-to-rail operational amplifier which avoids the above enumerated disadvantages of prior art operational amplifiers. Another object of the invention is to provide an improved operational amplifier which is simple and inexpensive and provides a high gain without the use of an intermediate gain stage. A further object of the invention is to provide an operational amplifier in which the input offset and noise voltage are of the same low level as in the case where an intermediate gain stage was employed. A still further object of the invention is to provide an operational amplifier circuit in which the quiescent current in the output transistors is relatively independent of the supply voltage and of the input common mode voltage. In accordance with the present invention, the above objects are achieved by the provision of a combination driver and summing circuit for a rail-to-rail operational amplifier that includes a rail-to-rail input stage composed of a pair of input differential amplifiers made up of complementary field effect transistors. The input stage may also include a current steering network. A summing circuit is provided which combines the internal currents supplied by the input differential amplifiers. A class A-B driver output stage is supplied with signal currents by the summing circuit and produces in turn one or more output signal currents as a function of an input signal received by the pair of input differential amplifiers. The class A-B driver output stage includes a pair of complementary control transistors coupled in parallel to control electrodes of the output transistors. The summing circuit comprises a folded cascode stage that includes a floating current source which provides a constant quiescent bias current for the output transistors of the class A-B output stage which is independent of the supply voltage, and which also is constant even if the common mode input voltage swings from rail to rail, which causes the complementary input stage to alternatively dump positive and negative bias current into the summing circuit. The present invention maintains the quiescent bias current in the class A-B output stage constant by using the floating current source to compensate for the finite output impedance of the class A-B bias control transistors. An intermediate amplifier stage is eliminated by the use of the folded cascode summing circuit stage with class A-B bias control transistors which present a high impedance to signal currents. A further feature is the provision of a constant current gain in the input stage. The invention provides operating characteristics equal to or superior to the prior art circuits and accomplishes this on an integrated circuit chip that is substantially smaller in size than that which is required by the known circuits. The provision of the folded cascode stage with a single floating current source eliminates the current mismatch problem in the Monticelli quad CMOS operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and the advantages thereof, reference will now be made to the following description taken in conjunction with the accompanying drawing which schematically illustrates a combination driver and summing circuit for a rail-to-rail operational amplifier, in which: Fig. 1 is a schematic circuit diagram of a differential amplifier in accordance with the invention, Fig. 2 is a circuit diagram showing a preferred embodiment of the floating current source, class A-B bias control and the output stage in the amplifier of Fig. 1, and Fig. 3 is a circuit diagram in which the floating current source is biased independently of the bias control circuit. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, Fig. 1 shows a combined class A-B driver and summing circuit for a rail-to-rail operational amplifier. A differential amplifier input stage comprises a first differential amplifier consisting of a first pair of P-channel field effect transistors Q I1 and Q I2 having their source electrodes connected in common to the positive rail V SP of the supply voltage via a current source 10 which supplies a constant current I B . A second input differential amplifier consisting of a second pair of field effect transistors Q I3 and Q I4 of the N-channel type have their source electrodes connected together to the drain electrode of a field effect transistor Q I7 . The source electrode of Q I7 is connected to the negative supply voltage rail V SN . The gate electrodes of transistors Q I1 and Q I3 are connected in common to a first signal input terminal 11 and the gate electrodes of transistors Q I2 and Q I4 are connected in common to a second signal input terminal 12. The input terminals 11 and 12 receive a differential input signal represented by voltages V I1 and V I2 in the drawing. A current control circuit which steers current through the input transistors Q I1 -Q I4 includes a control transistor Q I5 having its source electrode connected to a junction point between the current source 10 and the common connection of the source electrodes of field effect transistors Q I1 and Q I2 . The drain electrode of field effect transistor Q I5 is connected to the drain electrode of a diode-connected field effect transistor Q I6 whose source electrode is connected to the negative supply voltage rail V SN . The gate electrodes of transistors Q I6 and Q I7 are connected together so that transistors Q I6 and Q I7 together function as a current mirror circuit 13. The gate electrode of current control transistor Q I5 is connected to a terminal supplying a bias voltage V B . When the common-mode input voltage(V I1 + V I2 )/2 is below the voltage V B at the gate of the current steering control transistor Q I5 , the P-channel input differential amplifier pair Q I1 and Q I2 is active, which allows the common mode range to include the negative supply voltage V SN . Conversely, when the common mode input voltage is higher than the gate bias voltage V B , the control transistor Q I5 steers the tail current I B away from the transistor pair Q I1 , Q I2 and directs it instead through the diode-connected transistor Q I6 of the current mirror circuit 13. By means of the current mirror action, a tail current now flows through transistor Q I7 from the input transistor pair Q I3 , Q I4 . This allows the common mode range to include the positive supply voltage V SP . Transistors Q I1 -Q I4 are all turned on when the common mode voltage (V CM ) is in a middle range, whereas transistors Q I1 and Q I2 are conductive when V CM is in a low range extending from the bottom of the middle range to the negative supply voltage V SN . The opposite pair of input transistors Q I3 and Q I4 are conductive when V CM is in the high range extending between the top of the middle range and the positive supply voltage rail V SP . The output currents of the four input transistors Q I1 -Q I4 are added in the summing circuit 14, which includes the field effect transistors Q S1 -Q S8 and a common floating current source 15 which produces a current I S . The summing circuit is composed of two segments. The top half of the summing circuit comprises two series connected field effect transistors Q S1 and Q S5 coupled between the positive supply voltage rail V SP and a terminal 16 of the single floating current source 15. A second pair of field effect transistors Q S2 and Q S6 are serially connected between the positive rail V SP and the terminal 17. The gate electrodes of transistors Q S1 and Q S2 are connected together as are the gate electrodes of transistors Q S5 and Q S6 . The gate electrodes of transistors Q S1 and Q S2 are also directly connected to terminal 16 and the gate electrodes of transistors Q S5 and Q S6 are connected to a terminal which supplies a bias voltage V S1 . The common node labelled A between transistors Q S1 and Q S5 is connected by a connection (not shown) to the drain electrode of input transistor Q I3 . This connection is indicated by showing the drain of transistor Q I3 connected to a node also labelled A. In a similar manner, the common node B between transistors Q S2 and Q S6 is connected to the drain electrode of input transistor Q I4 , which is indicated by labelling the latter electrode B. The top half segment of the summing circuit constitutes a current mirror circuit. The bottom half segment of the summing circuit includes field effect transistors Q S7 and Q S3 serially connected between terminal 18 of the current source and the negative supply voltage rail V SN . In addition, field effect transistors Q S8 and Q S4 are serially connected between a terminal 19 of the summing circuit and the negative voltage rail. The gate electrodes of transistors of Q S3 and Q S4 are connected in common to the terminal 18 and the gate electrodes of transistors Q S7 and Q S8 are connected in common to a terminal which supplies a bias voltage V S2 . The common junction points C and D between transistors Q S7 and Q S3 and between transistors Q S8 and Q S4 , respectively, are connected to the drain electrodes of input transistors Q I1 and Q I2 , respectively, as indicated by the circuit points labelled C and D of the input transistors. The bottom half of the summing circuit also constitutes a current mirror circuit. A class A-B bias control and rail-to-rail output stage 20 is connected to terminals 17 and 19 and includes field effect transistors Q D1 -Q D8 , output field effect transistors Q O1 and Q O2 and a current source 21 providing a current I DB . An output current is derived at output terminal 22. A complementary pair of class A-B bias control transistors Q D1 and Q D2 are connected in parallel, i.e. head-to-tail, to the terminals 17 and 19 and supply drive currents I D1 and I D2 in parallel to the output field effect transistors Q O1 and Q O2 , respectively. The output transistors Q 01 and Q 02 are serially connected between the supply voltage rails V SP and V SN and have their drain electrodes connected in common to the output terminal 22. The gate of transistor Q 01 is connected to terminal 17 and the gate of transistor Q 02 to the terminal 19.Diode-connected field effect transistors Q D3 and Q D4 are serially connected with current source 21 between the supply voltage rails V SP and V SN . Field effect transistors Q D5 and Q D6 are serially connected with diode-connected field effect transistors Q D7 and Q D8 between the positive and negative supply voltage rails. The gate electrodes of transistors Q D3 and Q D5 are connected together as are the gate electrodes of transistors Q D4 and Q D6 . The top half of this circuit also forms a current mirror network. The gate electrode of transistor Q D1 is connected to a junction between diode Q D4 and the current source 21 and the gate electrode of transistor Q D2 is connected to a junction between transistor Q D6 and diode Q D7 . As described in U.S. Patent 4,555,673, which is hereby incorporated by reference, the current steering control circuit consisting of the current source 10, the control transistor Q I5 and the current mirror circuit 13 operates over the signal input range so as to control the current distribution in the input transistors Q I1 - Q I4 and hence the currents in the branches of the summing circuit 14. When the common-mode input voltage is below the reference voltage V B at the gate of control transistor Q I5 , the differential amplifier input pair Q I1 and Q I2 are conductive over the low range extending from the negative supply voltage V SN to the bottom of the middle range. The input transistors Q I3 and Q I4 are cut-off in the low range. Conversely, when the common-mode input voltage is higher than the bias voltage V B , the control transistor Q I5 redirects the current I B away from input transistors Q I1 and Q I2 , which are then nonconductive, and directs it instead to input transistors Q I3 and Q I4 via the current mirror circuit 13. The common-mode range, i.e. the high range, now includes the positive supply voltage V SP . In between the high and low ranges is a middle range in which all four input transistors are allowed to conduct. The foregoing operation is described in greater detail in U.S. Patent 4,555,673. The output currents of the four input transistors are added together in the summing circuit 14 consisting of transistors Q S1 - Q S8 . The current mirror circuits Q S1 ,Q S2 and Q S3 ,Q S4 mirror the currents at circuit points A and C and adds these currents to the currents at the circuit points B and D so as to provide drive currents for the driver output stage 20. The output transistors Q 01 and Q 02 are driven in parallel by driver currents I D1 and I D2 . The class AB driver control transistors Q D1 , and Q D2 are connected so that the common-mode component of the driver currents is unattenuated. The common-mode current drives the output transistor Q 01 or Q 02 or both transistors. The bias control transistors, however, control the differential-mode component of the driver currents such that class AB operation of the output transistors is obtained and with a low quiescent current through these transistors when there is no differential mode component in the driver current. In the quiescent condition, output transistor Q 01 is biased by the sum of the gate-source voltages of transistors Q D3 and Q D4 minus the gate-source voltage of transistor Q D1 , i.e. V GS01 = V GSD3 + V GSD4 - V GSD1 . Similarly for output transistor Q 02 , V GS02 = V GSD7 + V GSD8 - V GSD2 . When a positive output current flows, the current in the output transistor Q 01 is increased while that in output transistor Q 02 is decreased. The decrease of the gate-source voltage of transistor Q 02 is controlled by the increase of the gate-source voltage of transistor Q D2 . The source of transistor Q D2 draws the drive current away from the gate of transistor Q 02 while this drive current is added to that of the gate of transistor Q 01 . In order to provide a constant quiescent current in the summing and bias control circuit that is independent of which pair of input transistors is operating, it is possible to connect a first current source (e.g. I S1 ) to terminal 16 and a second current source (e.g. I S2 ) to terminal 18. Thus, the upper and lower current mirror circuits in the summing circuit would be individually driven by the first and second current sources, respectively. A disadvantage of this solution is that any inequality of the currents I S1 and I S2 would contribute to the input offset and noise voltage. The provision of a single common floating current source 15, as shown, produces superior performance in that it maintains a constant quiescent current while avoiding the disadvantages associated with the use of two separate current sources for the upper and lower sections of the summing circuit. The present invention thus provides a superior operational amplifier including an output class A-B bias control stage and a floating current source to bias the cascode summing circuit stage thereby to provide a constant quiescent bias current for the output transistors of the class A-B stage. The amplifier includes a current steering transistor network in the differential amplifier input stage which transfers current therebetween as the input signal traverses the input common-mode range, thereby maintaining a constant current gain in the input stage, another important characteristic for an operational amplifier. The floating current source maintains constant bias currents so as to compensate for the output impedance of the class A-B bias control transistors. The intermediate amplifier stage required by the prior art is eliminated by means of the invention. Rail-to-rail operation is provided and the operational amplifier can be accommodated on an integrated circuit chip that is smaller than commercially available devices. This is made possible by the floating current source and the class A-B bias control transistors within the cascode stage thereby eliminating the intermediate gain stage and complicated class A-B control of the prior art circuits. Figure 2 shows an improvement of the circuit of Fig. 1 in which the floating current source is made up of complementary field effect transistors Q S9 and Q S10 connected in parallel between terminals 16 and 18 of the summing circuit. The gate electrode of transistor Q S9 is connected to the gate electrode of driver control transistor Q D1 and the gate of transistor Q S10 is connected to the gate of driver control transistor Q D2 . The remainder of the circuit is similar to the circuit of Fig. 1 and corresponding elements are identified by means of the same reference labels as are used in Fig. 1. The input stage and the current steering circuit are omitted for the sake of brevity. In this embodiment, the current from the floating current source is slightly dependent on the voltage supply through the output impedance of Q S9 and Q S10 . As the voltage supply changes, the change in current compensates for the output impedance of Q D1 and Q D2 so as to maintain the gate-source voltage V GS (Q D1 and Q D2 ) constant, which in turn reduces the dependence of the quiescent bias current in the output stage on the voltage supply. This latter feature is extremely important where a battery is used as the supply voltage source. Figure 3 shows a further modification of the operational amplifier circuit of Fig. 1 in which the floating current source is independently biased from the driver circuit. A pair of complementary field effect transistors Q S9 and Q S10 are connected in parallel between the terminals 16 and 18 with connections similar to those of the driver control transistors Q D1 and Q D2 . An N-channel field effect transistor Q S11 is connected in series with a source of reference current 23 to the positive supply voltage rail V SP at the drain of transistor Q S11 . The gate electrode of transistor Q S9 is connected to the source electrode of transistor Q S11 and the gate of transistor Q S11 is connected to the source electrode of transistor Q S9 . In a similar manner, a P-channel field effect transistor Q S12 is connected in series with a source of reference current 24 to the negative supply voltage rail coupled to the drain electrode of transistor Q S12 . The gate of transistor Q S10 is connected to the source electrode of transistor Q S12 and the gate of transistor Q S12 is connected to the source electrode of transistor Q S10 . The floating current source described immediately above is biased independently of the driver circuit. As in Fig. 2, the differential amplifier input circuit and the current steering network have been omitted from Fig. 3 for the sake of brevity. Elements similar to those in Figs. 1 and 2 have the same reference labels. Aside from the differences in the floating current source, the circuits of Figs. 2 and 3 otherwise operate in a manner similar to that of the circuit of Fig. 1. While the invention has been described with reference to particular embodiments thereof, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor elements of opposite polarity to those described above may be employed to accomplish the same results. Alternatively, bipolar transistors could be used instead of the field effect transistors described herein. Thus, various modifications and changes may be made by those skilled in the art without departing from the true scope of the invention as defined by the appended claims.

Claims: A differential amplifier with rail-to-rail common-mode range comprising: a positive supply voltage rail (V SP ), a negative supply voltage rail (V SN ), first and second amplifier input terminals (11, 12) for receiving a signal to be amplified, a differential amplifier input stage (Q I1 -Q I4 ) comprising: input means coupled to said first and second amplifier input terminals (11, 12), output means (A, B, C, D), a first pair of transistors (Q I1 , Q I2 ) connected as a first differential amplifier to said positive supply voltage rail (V SP ) via a first current source (10), and a second pair of transistors (Q I3 , Q I4 ) connected as a second differential amplifier to said negative supply voltage rail (V SN ) via a second current source (Q I7 ). a current summing circuit (14) coupled to the output means (A, B, C, D) of the differential amplifier means, an output stage (20) including first and second output transistors (Q 01 , Q 02 ) coupled to at least one signal output terminal (22) and having input means coupled to the current summing circuit (14), said current summing circuit (14) comprising a first current mirror circuit (Q S5 , Q S1 , Q S2 , Q S6 ) coupled between the positive supply voltage rail (V SP ) and a first terminal (16) of a floating current source (15) and a second current mirror circuit (Q S7 , Q S3 , Q S4 , Q S8 ) coupled between the negative supply voltage rail (V SN ) and a second terminal (18) of the floating current source (15), the output stage (20) comprising first and second complementary bias control transistors (Q D1 , Q D2 ) connected in parallel between an output terminal (17) of the first current mirror circuit (Q S5 , Q S1 , Q S2 , Q S6 ) and an output terminal (19) of the second current mirror circuit (Q S7 , Q S3 , Q S4 , Q S8 ), characterized in that said floating current source (15) comprises third and fourth complementary transistors (Q S9 , Q S10 ) connected in parallel between said first and second terminals (16, 18) of the floating current source (15). A differential amplifier as claimed in claim 1 wherein the floating current source (15) further comprises: a fifth transistor (Q S12 ) connected in series with a third current source (24) to the positive supply voltage rail (V SP ), a sixth transistor (Q S11 ) connected in series with a fourth current source (23) to the negative supply voltage rail (V SN ), and means coupling a control electrode of the fourth transistor (Q S10 ) and a control electrode of the third transistor (Q S9 ) to first and second junction points between the fifth transistor (Q S12 ) and third current source (24) and between the sixth transistor (Q S11 ) and fourth current source (23), respectively. A differential amplifier as claimed in claim 1 or 2, wherein the output stage (20) comprises said first and second output transistors (Q 01 , Q 02 ) connected in series circuit between the positive and negative supply voltage rails (V SP , V SN ), and means coupling a control electrode of the first output transistor (Q 01 ) to said output terminal (17) of the first current mirror circuit (Q S5 , Q S1 , Q S2 , Q S6 ) and a control electrode of the second output transistor (Q 02 ) to the output terminal (19) of the second current mirror circuit (Q S7 , Q S3 , Q S4 , Q S8 ). A differential amplifier as claimed in claim 1 further comprising; a control transistor (Q I5 ) connected in series circuit with said first and second current sources (10, Q I7 ) between said positive and negative supply voltage rails(V SP , V SN ) and with a control electrode of the control transistor (Q I5 ) connected to a DC reference voltage (V B ). A differential amplifier as claimed in claim 4, wherein the second current source comprises: a current mirror circuit (13) having a first circuit branch (Q I7 ) coupling said second pair of transistors (Q I3 , Q I4 ) to the negative supply voltage rail (V SN ) and a second circuit branch (Q I6 ) connected in series circuit with the control transistor (Q I5 ) and the first current source (10) between said positive and negative supply voltage rails (V SP , V SN ).

Inventors: HUIJSING JOHAN HENDRIK, TERO JOHN, HUIJSING, JOHAN HENDRIK, TERO, JOHN
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1994
Main classification: H03F3
IPC codes: H03F3, G06G7