A charge transferring device having an FDA type charge detecting section and a method for producing the same

Abstract: A charge transfer device includes: a transfer channel for transferring a charge in a charge transfer direction; a charge detecting section having a diffusion layer for storing the charge transferred through the transfer channel and for inducing a voltage corresponding to the amount of the stored charge; and a transistor for detecting the induced voltage, the transistor having: a gate electrode formed on the diffusion layer, the gate electrode being in direct contact with the diffusion layer; a gate insulating film formed on the gate electrode; and a channel region formed above the gate electrode.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a charge transfer device and a method for producing the same, and more particularly to a charge transfer device including an FDA (Floating Diffusion Amplifier) type charge detecting section and a method for producing the same. 2. Description of the Related Art: Figure 6 shows in part a conventional charge transfer device 101 . As is shown in Figure 6 , the charge transfer device 101 includes a transfer channel 102 for transferring a charge, a charge detecting section 103 for detecting a charge, and a source follower amplifier 104 . Figure 7 is a circuit diagram showing the source follower amplifier 104 . As is shown in Figure 7 , the source follower amplifier 104 includes transistors Q 1 , Q 2 , Q 3 , and Q 4 . The transistors Q 2 and Q 3 are not shown in Figure 6 for conciseness and clarity. A charge is transferred in the transfer channel 102 when a two-phase clock pulse of 1 and 2 is applied to transfer electrodes 105 . The charge in the transfer channel 102 is transferred to the charge detecting section 103 in accordance with a timing of an output gate pulse OG applied to an electrode 106 , and is stored in the charge detecting section 103 . The signal charge is converted into an output signal in the form of a voltage at the source follower amplifier 104 (charge/voltage conversion). More specifically, a voltage which is in proportion to the amount of the charge stored in the charge detecting section 103 is detected by the transistor Q 1 in the source follower amplifier 104 , and is amplified in the source follower amplifier 104 so as to be detected as an output signal. When the output signal is detected, the charge in a charge detecting section 103 is drained to a reset drain RD in accordance with a timing of a reset gate pulse RG. Hereinafter, the charge detecting section 103 and the transistor Q 1 will be described in more detail, with reference to Figure 8 . Figure 8 is a view showing an 8 - 8 cross section of the charge transfer device 101 shown in Figure 6 . As is shown in Figure 8 , a P - -type first diffusion layer 111 is formed in a semiconductor substrate 110 . The charge detecting section 103 is composed of an N + -type floating diffusion layer 112 formed in the first diffusion layer 111 . Second diffusion layers 113 to 115 are also formed in the first diffusion layer 111 . The transistor Q 1 includes a portion 116 of the first diffusion layer 111 as a channel thereof, the portion 116 being interposed between the second diffusion layers 114 and 115 . The transistor Q 1 further includes a gate insulating film 117 formed on the portion 116 and a gate electrode 118 formed on the gate insulating film 117 . The floating diffusion layer 112 is electrically connected tothe gate electrode 118 through a wire 119 . As is shown in Figure 6 , a source 120 and a drain 121 are formed so as to interpose the gate electrode 118 therebetween. A charge q transferred in the charge transfer device 101 is converted into a voltage V in accordance with equations (1) and (2) shown below: C FD = C d + C g + C l V = q / C FD wherein C d represents the junction capacitance of the floating diffusion layer 112 ; C g represents the gate capacitance of the transistor Q 1 ; and C l represents parasitic capacitance that is mainly derived from a wire between the floating diffusion layer 112 and the transistor Q 1 . A sum total of the capacitances C d , C g , and C l equals the detection capacitance C FD that contributes to charge/voltage conversion. Currently, in the case of a CCD (Charge Coupled Device) solid imaging device using a charge transfer device mentioned above, the detection capacitance C FD is approximately 10 to 15 fF, in which the capacitance components C d , C g , and C l make substantially equal contributions to the overall detection capacitance C FD . As is seen from the equation (2), the voltage V increases as the detection capacitance C FD decreases, given that the detected charge q is constant. In recent years, there has been a demand for increasing the number of the pixels of a video camera, etc. in which a CCD solid imaging device is used, as well as a demand for miniaturizing such a video camera, etc. There has been a corresponding demand for a smaller and higher-performance charge transfer device. In particular, improvement in the charge/voltage conversion efficiency of such CCD solid imaging devices has been desired. One method to meet the above-mentioned demands is to lower the detection capacitance C FD . As is described above, the voltage V increases as the detection capacitance C FD decreases, given that the detected charge q is constant. Accordingly, as is seen from the equation (2), the detection capacitance C FD can be reduced by lowering capacitance components C d , C g , and/or C l . While it is possible to reduce the capacitance component C d by reducing the size of the floating diffusion layer 112 , a channel width in the range of about 5 to 10 µm must be secured so that a charge is securely transferred from the transfer channel 102 . Therefore, it is undesirable to make the floating diffusion layer 112 as small as the current fine-processing technique allows it to be. As will be appreciated, reduction of the gate capacitance C g and the parasitic capacitance C l is critical to the improvement of the charge/voltage conversion efficiency. US 4,984,045 relates to a charge transfer device with a charge transfer buried channel region which is formed continuously with a charge-sensing buried channel region which forms part of a charge-sensing MOS transistor. Patent Abstracts of Japan, 5,78 and JP-A-5026467 relate to a MOS transistor which is embedded in a semiconductor substrate to protect it from contamination. WO 88/02186 describes an output circuit for an image sensor comprising a transfer channel and a charge detecting section in the form of a floating diffusion layer which is connected to a transistor in a source-follower amplifier by means of aluminium contacts. SUMMARY OF THE INVENTION A charge transfer device according to the present invention is as set out in claim 1. In one embodiment of the invention, the gate electrode is in contact with the diffusion layer in a smaller area than an area in which the gate electrode is in contact with the channel region via the gate insulating film. In another embodiment of the invention, the transistor is a part of a source follower amplifier. In still another embodiment of the invention, the charge transfer device further includes; an output gate electrode formed on the transfer channel, the output gate electrode being elongated in a direction perpendicular to the charge transfer direction; and a reset gate electrode formed on the transfer channel; wherein the transistor is disposed between the output gate electrode and the reset gate electrode and the direction of a channel length of the transistor is perpendicular to the charge transfer direction. According to another embodiment of the invention, the charge transfer device includes: a transfer channel for transferring a charge; a charge detecting section including a diffusion layer for storing a charge transferred through the transfer channel and for inducing a voltage corresponding to the amount of the stored charge; and a transistor for detecting the induced voltage, the transistor including: an insulating film formed on the diffusion layer; a channel region formed above the diffusion layer; and a source and a drain each electrically connected to the channel region, the transistor controlling a current that flows in the channel region in accordance with the induced voltage. In one embodiment of the invention, the channel width of the channel region is substantially the same as or larger than the width of the diffusion layer. In another embodiment of the invention, the charge transfer device further includes a control gate electrode formed on the channel region, an insulating film being interposed between the control gate electrode and the channel region. In still another embodiment of the invention, the charge transfer device further includes; an output gate electrode formed on the transfer channel, the output gate electrode being elongated in a direction perpendicular to a charge transfer direction; and a reset gate electrode formed on the transfer channel; wherein the transistor is disposed between the output gate electrode and the reset gate electrode and the direction of the channel length of the transistor is perpendicular to the charge transfer direction. According to the invention, there is also provided a method as set out in claim 10. A charge transfer device according to an embodiment of the present invention includes a thin film transistor on a floating diffusion layer of a charge detecting section, the thin film transistor constituting a part of a source follower amplifier. As a result, no wiring for electrically interconnecting the floating diffusion layer and the source follower amplifier is required, thus reducing the parasitic capacitance included in such wiring. The parasitic capacitance included in such wiring is, while depending on the layout pattern of the charge detecting section and fabricating conditions, estimated to account for some 30% of the charge to be normally detected by the charge detecting section. Moreover, a first stage driver transistor for converting the charge into an output signal is provided on the charge detecting section. This makes it unnecessary to dispose other transistors for further amplifying the output signal so as to be in the vicinity of the charge detecting section, since the location of those transistors does not affect the charge/voltage conversion efficiency of the charge transfer device. Thus, the parasitic capacitance included in the charge to be detected by the charge detecting section is reduced, thereby improving the charge/voltage conversion efficiency. It is also made possible to miniaturize the device and to relatively freely lay out the transistors constituting the source follower amplifier. Thus, the invention described herein makes possible the advantages of (1) providing a small, high-performance charge transfer device in which the charge detection capacity is reduced so as to improve the charge/voltage conversion efficiency, and a method for the production thereof; and (2) minimizing restrictions concerning the layout of a charge transfer device, so that the charge transfer device can be fabricated at low costs and with a high yield. These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view showing a portion of a charge transfer device according to a first example of the present invention. Figure 2 is a view showing a 2 - 2 cross section of the charge transfer device shown in Figure 1. Figure 3 is a cross-sectional view showing a variant of the charge transfer device according to the first example of the present invention. Figure 4A is a cross-sectional view showing a charge transfer device according to a second example of the present invention. Figure 4B is a plan view showing a transistor section of the charge transfer device shown in Figure 4A . Figure 5 is a cross-sectional view showing a variant of the charge transfer device according to the second example of the present invention. Figure 6 is a plan view showing a portion of a conventional charge transfer device. Figure 7 is a circuit diagram showing an exemplary source follower amplifier to be used in a charge transfer device. Figure 8 is a view showing an 8 - 8 cross section of the charge transfer device shown in Figure 6 . DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described by way of examples, with reference to the accompanying drawings. Example 1 Figure 1 is a plan view showing in part a charge transfer device 11 according to the present invention. As is shown in Figure 1 , the charge transfer device 11 includes a transfer channel 12 for transferring a charge and a charge detecting section 13 for detecting a charge. The transfer channel 12 includes a transfer region 15 formed in a semiconductor substrate 14 and a plurality of transfer electrodes 16 formed on the transfer region 15 . The transfer electrodes 16 are elongated in a direction perpendicular to the charge transfer direction shown by the arrow. An output gate electrode 17 , a reset gate electrode 18 , and a reset drain electrode 19 are formed on the transfer region 15 . The charge detecting section 13 is formed in a portion of the transfer region 15 that is located between the output gate electrode 17 and the reset gate electrode 18 . A charge is transferred in the transfer region 15 in the direction of the arrow shown in Figure 1 , in accordance with a two-phase clock pulse of 1 and 2 applied to the transfer electrodes 16 . The charge is transferred to the charge detecting section 13 formed in the transfer region 15 in accordance with an output gate pulse OG applied to the output gate electrode 17. A transistor Q 1 having a drain 20 and a source 21 is disposed on the charge detecting section 13 . The transistor Q 1 further has a channel region (not shown in Figure 1 ) between the drain 20 and the source 21 . The direction of a channel length of the transistor Q 1 is perpendicular to a charge transfer direction shown by the arrow. A voltage in proportion to an amount of charge stored in the charge detecting section 13 is detected by the transistor Q 1 as an output signal. The output signal is applied to a gate electrode 24 of a transistor Q 3 through a wire 23 connected to the source 21 of the transistor Q 1 . The wire 23 is also connected to a transistor Q 2 (not shown) through a wire 25 . The transistors Q 1 , Q 2 , Q 3 , and Q 4 (not shown) constitute a source follower amplifier 104 shown in Figure 6 and serve to amplify the output signal. When the output signal is detected, a reset gate pulse RG is applied to the reset gate electrode 18 , and the charge stored in the charge detecting section 13 is drained to the reset drain electrode 19 . Hereinafter, the charge transfer device 11 according to the present example will be described in more detail, with reference to Figure 2 . Figure 2 is a view showing the 2 - 2 cross section of the charge transfer device 11 shown in Figure 1 . As is shown in Figure 2 , a P - -type first diffusion layer 26 is formed in the semiconductor substrate 14 . A portion of the first diffusion layer 26 defines the transfer region 15 . In the vicinity of a surface of the semiconductor substrate 14 excluding the transfer region 15 , a P + -type second diffusion layer 27 is formed. A LOCOS oxide film 28 is formed on the P + -type second diffusion layer 27 . In the portion of the transfer region 15 located in the vicinity of the surface of the semiconductor substrate 14 , the charge detecting section 13 is formed. The charge detecting section 13 is composed of an N + -type diffusion layer, and approximately accounts for the area of a rectangular having the sides of lengths L 1 and W 1 (not shown). L 1 is measured along the direction of the channel length of the transistor Q 1 and W 1 is measured along the direction perpendicular to the channel length. A gate electrode 29 is formed on the charge detecting section 13 . An oxide film 30 is formed so as to cover the LOCOS oxide film 28 , the transfer region 15 , and the gate electrode 29 . The gate electrode 29 is formed so as to be larger at the top than at the bottom. The top portion of the gate electrode 29 constitutes a rectangular having the sides of lengths L 2 and W 2 (not shown), but accounts for a larger area than that of the charge detecting section 13 . L 2 is also measured along the direction of the channel length of the transistor Q 1 and W 2 is measured along the perpendicular direction the channel length. On the oxide film 30 , the drain 20 , the source 21 , and a channel region 31 interposed between the drain 20 and the source 21 are formed. A portion 32 of the oxide film 30 that is interposed between the channel region 31 and the gate electrode 29 functions as a gate oxide film (hereinafter the portion 32 will be referred to as 'the gate oxide film' 32 ). The transistor Q 1 is composed of the drain 20 , the source 21 , the channel region 31 , the gate electrode 29 , and the gate oxide film 32 . A passivation film 33 is formed so as to cover the transistor Q 1 . The output drain electrode 22 and the drain 20 are interconnected via a contact hole 34 . The wire 23 and the source 21 are interconnected via a contact hole 35 . As a charge which has been transferred through the transfer channel 12 is stored in the charge detecting section 13 , a voltage is induced in the charge detecting section 13 . The voltage is determined based on the detection capacitance C FD and the amount of the charge stored in the charge detecting section. Since the gate electrode 29 is in direct ohmic contact with the charge detecting section 13 , a voltage induced in the charge detecting section 13 is applied to the gate electrode 29 of the transistor Q 1 . As a result, in the transistor Q 1 , a current in accordance with the voltage applied to the gate electrode 29 flows from the drain 22 to the source 21 . Furthermore, the current is amplified by the transistors Q 2 to Q 4 . As is described above, the charge detecting section 13 and gate electrode 29 of the transistor Q 1 which works as a first driver of the source follower amplifier are in direct contact with each other. As a result, the parasitic capacitance C l shown in the equation (1) is eliminated, whereby the detection capacitance C FD is reduced. Therefore, as is seen from the equation (2), a larger voltage V is applied to the gate electrode 29 corresponding to a conventional amount of charge being stored in the charge detecting section 13 . Thus, the charge/voltage conversion efficiency of the charge detecting section 13 is improved. Moreover, the charge is converted into an output signal in the form of a current or a voltage at the transistor Q 1 formed on the charge detecting section 13 . In other words, the charge/voltage conversion has already been performed at the transistor Q 1 . Therefore, the detection capacitance C FD is not influenced by the parasitic capacitance of the wire 23 interconnecting the transistor Q 1 and the transistors Q 2 to Q 4 . This makes it unnecessary to locate the transistors Q 2 to Q 4 closely to the transistor Q 1 . The transistors Q 2 to Q 4 can be located relatively arbitrarily unless the resistance of the wire 23 creates an unfavorable effect. In addition, the transistor Q 1 is formed on the charge detecting section 13 and between the output gate electrode 17 and the reset gate electrode 18 so that the direction of the channel length is perpendicular to the charge transfer direction. Such configuration needs no additional space for the transistor Q 1 . Therefore, the charge transfer device 11 of the present invention can be made smaller than a convention charge transfer device. As is shown in Figure 2, the charge detecting section 13 can be formed as small as possible so as to minimize the junction capacitance C d of the charge detection section 13 . On the other hand, the lengths L 2 and W 2 can be determined at minimum values which allows satisfactory operation of the transistor Q 1 without punch through, regardless of the size of the charge detecting section 13 , by forming the gate electrode 29 in a general mushroom shape. Therefore, the present invention allows incorporation of a source follower amplifier with a sufficient amplitude as well as an improved charge/voltage conversion efficiency of the charge transfer device. Hereinafter, a method for producing the charge transfer device 11 will be described, with reference to Figure 2 . First, the semiconductor substrate 14 composed of N-type silicon is doped with P-type impurities, whereby the P - -type first diffusion layer 26 is formed. The doping with the P-type impurities is further conducted for the semiconductor substrate 14 excluding a portion thereof which defines the transfer channel 12 , whereby the P + -type second diffusion layer 27 is formed. The surface of the second diffusion layer 27 is oxidized to form the LOCOS oxide film 28 having a thickness of about 100 nm. Next, a portion of the transfer channel 12 is doped with N-type impurities, whereby the charge detecting section 13 composed of an N + -type floating diffusion layer is formed. The charge detecting section 13 is formed so as to approximately occupy the area of a rectangular having the sides of lengths of L 1 and W 1 . The L 1 and W 1 should be set at small values so long as the gate electrode 29 can be satisfactorily in contact with the charge detection section 13 . Such minimum values are determined by a design rule for producing the charge transfer device 11 . After a silicon oxide film 30a is formed over the entire surface of the semiconductor substrate 14 , a contact hole (not shown) having approximately the same area as that of the charge detecting section 13 is formed. Thereafter, a Ti-W alloy is deposited and is patterned to form the gate electrode 29 . The gate electrode 29 should preferably be heat-resistant, and may be formed of N + polysilicon or the like. The gate electrode 29 is formed so as to approximately occupy the area of a rectangular having the sides of lengths L 2 and W 2 . The gate electrode 29 can be formed of a size which allows the transistor Q 1 to have predetermined properties. However, the lengths L 2 and W 2 are preferably determined at minimum values which allows satisfactory operation of the transistor Q 1 without punch through. Next, a silicon oxide film 30b is formed over the entire surface of the semiconductor substrate 14 . A portion of the silicon oxide film 30b that is located on the gate electrode 29 functions as the gate insulating film 32 . An amorphous silicon film (not shown) having a thickness in the range of 50 to 100 nm is deposited on the silicon oxide film 30b at a temperature of 500° to 600°C by the use of a low pressure CVD (Chemical Vapor Deposition) method, and thereafter is subjected to a heat treatment for 10 to 20 hours under a nitrogen atmosphere to form a polycrystalline silicon film (not shown). The semiconductor substrate 14 , excluding a portion thereof that defines the channel region of the transistor Q 1 , is doped with N-type impurities, and the polycrystalline silicon film is patterned to form the drain 20 , source 21 , and channel region 31 . After depositing the passivation film 33 over the entire surface of the semiconductor substrate 14 and forming the contact holes 34 and 35 , the output electrode 22 and the wire 23 are formed. No description is offered as to the fabrication of component elements such as the transfer electrode 16 shown in Figure 1 in the above-described fabrication method. However, it is appreciated that the transfer electrode 16 , the transistors Q 2 to Q 4 , and other component elements mentioned above can be fabricated at certain steps during the above-described fabrication method. Moreover, the above-mentioned fabrication steps can be incorporated with a method for producing an apparatus to which the charge transfer device of the present invention is applied, such an imaging device, shift resister, memory device, etc. One feature of the present invention is that the transistor Q 1 for converting the detected charge into an output signal is formed on the charge detecting section 13 without use of any wires. Various bottom gate-type TFTs (Thin Film Transistors) can be used as the transistor Q 1 . For example, as is shown in Figure 3 , the transistor Q 1 may be an amorphous silicon TFT having a channel region 41 composed of amorphous silicon or polysilicon , a source 42 composed of N + -type amorphous silicon or polysilicon, and a drain 43 composed of N + -type amorphous silicon or polysilicon. An insulating film 44 insulates the source 42 from the drain 43 . Example 2 Figure 4A shows a cross section of a charge transfer device 51 according to the second example of the present invention, the cross section being taken in the vicinity of a charge detecting section 13 . The charge transfer device 51 of the present example has the same configuration as that of the charge transfer device 11 of Example 1 except for the portion thereof shown in Figure 2 . Descriptions for any other portion than the said portion will be omitted. Component elements corresponding to those of the charge transfer device 11 are indicated by the same reference numerals. As is shown in Figure 4A , a P - -type first diffusion layer 26 is formed in a semiconductor substrate 14 . A portion of the first diffusion layer 26 defines a transfer region 15 . In the vicinity of the surface of the semiconductor substrate 14 excluding the transfer region 15, a P + -type second diffusion layer 27 is formed. A LOCOS oxide film 28 , is formed on the P + -type second diffusion layer 27 . In the portion of the transfer region 15 located in the vicinity of the surface of the semiconductor substrate 14 , a charge detecting section 13 is formed. The charge detecting section 13 is composed of an N + -type diffusion layer. An oxide film 52 is formed so as to cover the LOCOS oxide film 28 and the transfer region 15 . On the oxide film 52 , there are formed a drain 53 , a source 54 , and a channel region 55 interposed between the drain 53 and the source 54 . The drain 53 , the source 54 , and the channel region 55 constitute a transistor Q 1 for a first driver transistor of a source follower amplifier. The charge detecting section 13 functions as a gate electrode of the transistor Q 1 . A passivation film 33 is formed so as to cover the entire area of the semiconductor substrate 14 . An output drain electrode 22 and the drain 53 are interconnected via a contact hole 34 . A wire 23 and the source 54 are interconnected via a contact hole 35. As a charge which has been transferred through a transfer channel (not shown) is stored in the charge detecting section 13 , a voltage is induced in the charge detecting section 13 . The voltage is determined based on the capacitance of the charge detecting section 13 and the amount of the charge that has been transferred. The induced voltage forms a depletion layer directly in the channel region 55 of the transistor Q 1 , without being transmitted through a gate electrode, so as to control current that flows from the drain 53 to the source 54 . Furthermore, the current is amplified by transistors Q 2 to Q 4 . As is described above, the charge detecting section 13 itself functions as a gate electrode of the transistor Q 1 . Therefore, it is unnecessary to incorporate any gate electrode made of refractory metals, as well as any wire to connect the charge detecting section 13 and the transistor Q 1 . Therefore, no gate electrode made of refractory metals is formed in the charge transfer device 51 , whereby the fabrication steps are simplified as compared to the fabrication of the charge transfer device 11 of Example 1. In the transistor Q 1 of the charge transfer device 51 , a current that flows in the channel region 55 is controlled by a voltage induced in the charge detecting section 13 . If the channel region 55 is formed so as to be longer than the charge detecting section 13 in the direction of the channel width of the transistor Q 1 , thus hanging or protruding over the charge detecting section 13 , the protruding portion of the channel region 55 can not be controlled by the voltage induced in the charge detecting section 13 . Therefore, it is preferable that the channel width of the channel region 55 in the transistor Q 1 is the same or smaller than the width of the charge detecting section 13 . This will be described below in more detail with reference to Figure 4B , which is a plan view showing the transistor section of the charge transfer device 51 . The channel region 55 should be formed in such a way that the channel width W 3 of the transistor Q 1 is the same or smaller than the width W 1 of the charge detecting section 13 . Moreover, the length L 1 of the charge detecting section 13 should be so small that the junction capacitance C d does not become large. However, the length L 1 should be large enough so that a depletion layer with a sufficient size for controlling a current flowing the channel region 13 is formed. For this reason, the length L 1 should preferably be approximately the same as the channel length L 3 . As one modification of Example 2 of the invention, a control gate may further be incorporated in the charge transfer device 51 . Figure 5 shows a cross section of a charge transfer device 61 having a control gate electrode 62 , the cross section being taken in the vicinity of a charge detecting section 13 of the charge transfer device 61 . As is shown in Figure 5 , in the charge transfer device 61 , a control gate electrode 62 is formed above a channel region 55 , with a portion of a passivation film 33 interposed therebetween. A wire 63 for applying a voltage is connected to the control gate electrode 62 . The control gate electrode 62 accounts for substantially the same area as that of the channel region 55, so that a depletion layer is formed in the entire channel region 55 so as to control a current that flows therein. Accordingly, a transistor Q 1 satisfactorily detects a charge stored in the charge detecting section 13, whereby an output signal is obtained. The above-described charge transfer devices 51 and 61 can be fabricated by a method similar to that for the charge transfer device 11 of Example 1. The channel region 55 of the transistor Q 1 is formed of polysilicon. The present invention can be applied to various kinds of devices and apparatuses which essentially include a charge transfer device having a charge detection section. It is appreciated that the invention is suitable for use in a CCD solid state imaging device, a delay element, a transversal filter, etc. Application of the Invention to such a device makes the device small and provides the device with the improved charge/voltage conversion efficiency. Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the invention.

Claims: A charge transfer device (11, 51) comprising: a transfer channel (12) for transferring a charge in a charge transfer direction; a charge detecting section (13) for storing the charge transferred through the transfer channel (12) and for inducing a voltage corresponding to the amount of the stored charge; and a transistor (Q 1 ) for detecting the induced voltage, wherein, the charge detecting section (13) includes a floating diffusion layer (13), characterised in that the transistor (Q 1 ) includes: a gate electrode (29; 13) which is either formed on and in direct contact with the diffusion layer (13) or formed by the diffusion layer (13); an insulating film (30b; 52) formed on the gate electrode (29; 13); and a channel region (31; 55) formed over the gate electrode (29; 13). A charge transfer device (11) according to claim 1, wherein the gate electrode (29) is in contact with the floating diffusion layer (13) in a smaller area than the area in which the gate electrode (29) is in contact with the channel region (31) via the gate insulating film (32). A charge transfer device (11) according to claim 1, wherein the transistor (Q 1 ) is a part of a source follower amplifier. A charge transfer device (11) according to claim 1, wherein the transistor (Q 1 ) includes a thin film transistor. A charge transfer device (51) according to claim 1, wherein the transistor (Q 1 ) includes a source (54) and a drain (53) each electrically connected to the channel region (55), and the transistor (Q 1 ) controls a current that flows in the channel region (55) in accordance with the induced voltage. A charge transfer device (51) according to claim 5, wherein the channel width of the channel region (55) is substantially the same as or smaller than a width of the floating diffusion layer (13). A charge transfer device (51) according to claim 5 further comprising a control gate electrode (62) formed on the channel region (55), an insulating film (33) being interposed between the control gate electrode (62) and the channel region (55). A charge transfer device (11, 51) according to claim 1 or 5 further comprising; an output gate electrode (17) formed on the transfer channel (12), the output gate electrode (17) being elongated in a direction perpendicular to the charge transfer direction; and a reset gate electrode (18) formed on the transfer channel (12); wherein the transistor (Q 1 ) is disposed between the output gate electrode (17) and the reset gate electrode (18) and the direction of the channel length of the transistor (Q 1 ) is perpendicular to the charge transfer direction. A method for producing a charge transfer device (11, 51) comprising the steps of: forming a transfer channel (12) for transferring a charge in a charge transfer direction; forming a charge detecting section (13) for storing the charge transferred through the transfer channel (12) and for inducing a voltage corresponding to the amount of the stored charge; and forming a transistor (Q 1 ) for detecting the induced voltage, wherein, the step of forming the charge detecting section (13) includes the step of forming a floating diffusion layer (13), characterised in that the step of forming the transistor (Q 1 ) includes the steps of: forming a gate electrode (29; 13) which is either on and in direct contact with the diffusion layer (13) or using the diffusion layer (13); forming an insulating film (30b; 52) on the gate electrode (29; 13); and forming a channel region (31; 55) over the gate electrode (29; 13). A method for producing a charge transfer device (11, 51) according to claim 9, wherein the transistor (Q 1 ) includes a thin film transistor.

Inventors: HASHIGUCHI KAZUO, NAGAKAWA TADASHI, HASHIGUCHI, KAZUO, NAGAKAWA, TADASHI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1994
Main classification: H01L29
IPC codes: H01L29, H01L21