Test method for writable nonvolatile semiconductor memory device

Abstract: A test method for a writable nonvolatile semiconductor memory, comprising: a writing step for writing data; an aging step wherein the nonvolatile semiconductor memory is placed under prescribed aging conditions; and a verification step where data is read out and compared with the data written in the writing step for verification. The test method is characterised in that the aging step incorporates a step of forming a coating film for alleviating the stress applied to the nonvolatile semiconductor memory during assembly.

Description: The present invention relates to a test method for a writable nonvolatile semiconductor memory. More particularly, the invention relates to a test method, wherein testing can be conducted easily to check whether the fabricated semiconductor device has a prescribed performance. Semiconductor memories such as DRAM and SRAM are widely used, and flash memory has been attracting attention as an electrically erasable nonvolatile memory. Each memory cell of a flash memory consists of a single transistor. This transistor is called a memory cell transistor. A memory cell transistor of the flash memory has the structure of an n-channel MOS transistor with a floating gate formed beneath its gate. For erasure, a control gate is left open, and a high voltage is applied to a source, which causes a charge to be drawn through the source, leaving almost zero charge on the floating gate. In this situation, when an appropriate voltage is applied to the control gate, the transistor conducts. When a high voltage is applied to the control gate and the drain, avalanche breakdown occurs, and some of the electrons that have gained high energy near the drain are captured by the floating gate. This operation is called writing. Once writing is done, the charge remains accumulated on the floating gate, so that the transistor will not conduct even when a voltage is applied to the control gate. Data is defined according to whether the transistor conducts or not. In the flash memory, the writing and erasure of information can be accomplished electrically, as described above. Flash memories require different voltages for different operating modes, read, write, and erasure, for application to various elements, and accordingly, their control operations are complex: Furthermore, a read or erase operation is usually followed by a verify operation to verify the processed data by reading it. Such operations have previously been done by applying prescribed voltages to designated terminals of the flash memory by using a writer or other external equipment. This puts a great deal of load on the writer and other external equipment used for write and erase operations. To simplify such complex control algorithms, the recent flash memory design incorporates automatic circuitry that allows the writing and erasure of flash memory cells to be accomplished just by entering simple control commands from the outside. Such a flash memory design is becoming predominant. In a flash memory equipped with such automatic circuitry, once an external control command is accepted, all processing is automatically done internally until a cell write or erase operation is completed. It is therefore usual to provide a status register facility as a means for allowing external monitoring of the device status. Once the automatic circuitry is activated, it is not possible to know the status of internal circuitry without reading out the status register. After the fabrication of a semiconductor device is completed, various tests are performed to check whether the semiconductor device has the prescribed performance. In the case of a nonvolatile memory such as a flash memory, for example, a test is performed to check whether the status register functions properly. The status register provides an external indication of the status of write and erase operations performed by the operational logic circuit; that is, the bit values in the status register indicate whether the write or erase operation has been completed correctly. Therefore, to verify whether the status register is functioning correctly, the operational logic circuit is actually made to perform various operations to produce various status conditions, and the status register is tested to see whether it reflects the status correctly. In the status register test procedure above, only the operation of the status register is tested. For example, when the operation of the status register for write mode is tested, the test result of normal or failure is set into the status register without performing real write and verify operations. Therefore, the procedure does not guarantee that the status register will function properly when a failure occurs in the memory cell matrix or a sense amplifier/write amplifier. Namely, with the status register test for a flash memory explained above, it is only possible to verify the status register function and part of the whole circuit operation. In the testing of memories, with increasing memory capacity, the test time is increasing by a large extent, which pushes the test costs even higher than before. To reduce the test costs, it is important to be able to identify defects in the shortest possible time, but at the same time, it is also important to combine various tests into a single comprehensive test process to reduce the test time and minimize the increase in test costs. Therefore, in the status register test also, it is desirable that the test be performed in a more comprehensive manner, not limiting the test to the parts mentioned above. The test method currently practiced is not sufficient from this point of view. Among tests unique to a nonvolatile memory such as a flash memory, there is a test to guarantee proper retention of the stored data for long periods of time after power to the memory is removed. Since such a long-period test cannot be performed under actual conditions, the data retention test is usually conducted by an accelerated test called an aging test. In the aging test, after writing is done up to a prescribed level, accelerating stresses are applied to stress the data retention conditions by holding the device at a temperature higher than normal, and after that, the threshold level is detected. As described above, each individual device is subjected to the aging test after it is assembled and sealed in a package. However, since the aging test as described above is performed in the final test step after the device assembly, a sufficiently high temperature cannot be applied to the device assembled in a plastic package, thus requiring a long aging time to guarantee the reliability of data retention, and hence increasing the number of steps. There has been proposed another process different from the above process in which the aging test is performed between a passivation layer growing step and the coating film growing step. In this process, after writing is done up to a prescribed level, accelerating stresses are applied in the aging step where the device is held for one hour at 300°C. Then, the data level is verified. With the aging test described above, while it can guarantee the device reliability since the devices are subjected to aging on the wafer, it still involves a problem in that it increases the number of steps. US-A-5 287 313 and JP-A- 05 047 894 disclose a test method according to the preamble of claim 1. In this test method, the verification step is carried out after assembly of the nonvolatile semiconductor memory, in order to allow a baking treatment (aging step) to take place under more severe conditions. The present invention has been made in view of the above enumerated problems, and may provide a test method for a nonvolatile semiconductor memory, which can sufficiently guarantee the data retention reliability of the nonvolatile semiconductor memory, while minimizing the cost increase due to an increased number of steps. According to the present invention, there is provided a test method for a writable nonvolatile semiconductor memory, which comprises, in sequence: a writing step for writing data; an aging step where the nonvolatile semiconductor memory is placed under prescribed aging conditions; and a verification step where data is read out and compared with the data written in the writing step for verification, the test method being characterized in that the aging step is performed by forming a coating film for alleviating the stress applied to the nonvolatile semiconductor memory during assembly, without performing any separate aging step. In the test method for a nonvolatile semiconductor memory according to the present invention, since the aging step is performed on the semiconductor memory fabricated on a wafer, the memory can be subjected to a high temperature. Furthermore, in the step of forming a coating film that serves as a stress relieving film during assembly, the memory is held at a high temperature for a prescribed period of time which also provides aging conditions. This achieves a reduction in the number of test steps. The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: Figs. 1A through 1C are diagrams showing a memory cell structure of a flash memory; Fig. 2 is a block diagram showing the configuration of a prior art flash memory; Figs. 3A and 3B are flowcharts showing processes incorporating an aging test according to the prior art; Fig. 4 is a flowchart showing a process incorporating an aging test according to a second embodiment; Fig. 5 is a flowchart showing a process incorporating an aging test according to a third embodiment; and Fig. 6. is a diagram showing a coating film growing process. Before proceeding to a detailed description of the preferred embodiments of the present invention, prior art nonvolatile semiconductor memories will be described, with reference to the accompanying drawings relating thereto, for a clearer understanding of the differences between the prior art and the present invention. An example of the memory cell transistor of the flash memory is shown in Figs. 1A through 1C: Fig. 1A shows a top plan view, Fig. 18 shows an A-A' cross section, and Fig. 1C shows a B-B' cross section. Reference numeral 91 indicates a p-type silicon (Si) substrate, 92 indicates a floating gate (FG) formed from polysilicon, 93 indicates a control gate (CG) formed from polysilicon capacitively coupled to the FG 92, 94 and 95 indicate n-type regions which form the source and drain, and 96 indicates an oxide film. Fig. 2 is a block diagram showing the configuration of a prior art flash memory. Throughout the drawings, the same reference numerals are used to indicate the same functional elements, while the reference numerals with an alphabetic character suffixed thereto indicate elements having similar, but not the same, functions. The numeral 1 indicates a command register circuit, 2 indicates a status register circuit, 3 indicates an operational logic circuit, 4 indicates a column address buffer, 5 indicates a row address buffer, 6 indicates a block address buffer, 7 indicates a write/erase switching circuit, 8A indicates a data comparator circuit, 9A indicates a write/erase timing generating circuit, 10 indicates a column decoder, 11A indicates a row decoder, 12 indicates a block decoder, and 13A indicates a write/erase test signal input circuit which, only when a test signal is input to it, forcibly activates the write/erase timing generating circuit 9A while inhibiting the data comparator function of the data comparator circuit 8A. The numeral 14 indicates an input/output buffer, 15 indicates a sense amplifier/write amplifier, 16 indicates a Y-gate, 17A indicates a memory cell matrix, and 18 indicates an erasure source control circuit. As described above, flash memories put a great deal of load on the writer and other external equipment used for write and erase operations. To simplify such complex control algorithms, the recent flash memory design incorporates automatic circuitry that allows the writing and erasure of flash memory cells to be accomplished just by entering simple control commands from the outside. A flash memory equipped with such automatic circuitry usually provides a status register facility as a means for allowing external monitoring of the device status. Once the automatic circuitry is activated, it is not possible to know the status of internal circuitry without reading out the status register. After the fabrication of a semiconductor device is completed, a test is performed to check whether the status register functions properly. The status register provides an external indication of the status of write and erase operations performed by the operational logic circuit; that is, the bit values in the status register indicate whether the write or erase operation has been completed correctly. Therefore, to verify whether the status register is functioning correctly, the operational logic circuit is actually made to perform various operations to produce various status conditions, and the status register is tested to see whether it reflects the status correctly. As described above, a nonvolatile memory such as a flash memory requires a test to guarantee proper retention of the stored data for long periods of time after power to the memory is removed. This data retention test is usually conducted by an accelerated test called an aging test. In the aging test, after writing is done up to a prescribed level, accelerating stresses are applied to the data retention conditions by holding the device at a temperature higher than normal, and after that, the threshold level is detected. Fig. 3A is a flowchart showing the sequencing of an aging test in a prior art semiconductor device fabrication process. In the process shown in Fig. 3A, after a wafer fabrication step 601, a passivation layer growing step 602, a coating film growing step 603, a probe test step 604, and an assembly step 605, each individual complete semiconductor device undergoes a final test step 606 where the aging test is performed. In the final test step 606, prescribed operations including writing are performed in a first final-test step 607; then, in an aging step 608, the device is held for several tens of hours at 150°C, for example, and in a second final-test step 609, a second final-test including the measurement of the stored data level is performed. As described above, in Fig. 3A, each individual device is subjected to the aging test after it is assembled and sealed in a package. However, since the aging test as described in Fig. 3A is performed in'the final test step after the device assembly, a sufficiently high temperature cannot be applied to the device assembled in a plastic package, thus requiring a long aging time to guarantee the reliability of data retention, and hence increasing the number of steps. The process shown in Fig. 3B is different from that shown in Fig. 3A in that the aging test is performed between the cover film growing step 702 and the coating film growing step 706. After writing is done up to a prescribed level in step 703, accelerating stresses are applied in the aging step 704 where the device is held for one hour at 300°C. In the next step 705, the data level is verified. With the aging test shown in Fig. 3B, while it can guarantee the device reliability since the devices are subjected to aging on the wafer, it still involves a problem in that it increases the number of steps. When measuring the power supply margin for the sense amplifier, the test is performed using a circuit that separates the sense amplifier power supply from the cell gate power supply. Such a test, however, cannot be performed in the usual test process, but a separate test step for that purpose needs to be provided. The problem here is that the extra test in addition to the usual test steps will introduce an extra cost which will be reflected in the final chip cost. These problems are addressed by the present invention. Fig. 4 is a flowchart showing a process incorporating an aging test according to a first embodiment of the invention. In this embodiment, a wafer is fabricated in step 201, a passivation layer is grown in step 202, and a first probe test is performed in step 203, where a charge is injected into the floating gate. Each cell transistor is thus set to the nonconducting state, its output being a "0". In step 204, a coating film is grown; at this time, since the wafer is held at a high temperature for about one hour, the same effect as aging can be achieved, as will be described later. In step 205, a second probe test is performed to check that the output is "0" when reading is done under conditions with a prescribed margin. This completes the data retention test. Next, in step 206, assembly is done, and in step 207, the final test is performed. In the final test step, a first final test is performed to check prescribed performance items, which is followed by burn-in where the devices are operated continuously for a prescribed period of time. After that, a second final test to test the performance is performed, which completes the final test process. In the first embodiment, after the coating film growing step in step 204, the second probe test is performed to check the retained charge, but alternatively, this test may be performed in the final test step. Fig. 5 is a flowchart showing the process according to a second embodiment wherein the second probe test described in the first embodiment is incorporated in the final test step. The process shown is different from that shown in the flowchart of Fig.4 in that the second probe test is omitted and in that the first final test in step 307 includes a test to check whether the charge injected in step 303 is retained after going through the coating film growing step 304 and the assembly step 305. The second embodiment is advantageous in terms of the process since the second probe test can be omitted. For reference purposes, Fig. 6 shows a flowchart for the coating film growing process. In the figure, the curing step in step 407 is a process for drying the grown film, where the devices are held at high temperatures from 300°C to 350°C for 60 minutes. This provides conditions very similar to those of aging, so that the coating film growing step can be used to replace the aging step. In the test method of the first and second embodiments, since the aging step is performed on the semiconductor memory fabricated on a wafer, the memory can be subjected to a high temperature. Furthermore, in the step of forming a coating film that serves as a stress relieving film during assembly, the memory is held at a high temperature for a prescribed period of time which also provides aging conditions. This achieves a reduction in the number of test steps.

Claims: A test method for a writable nonvolatile semiconductor memory, comprising, in sequence; a writing step (203,303) for writing data; an aging step (204,304) where said nonvolatile semiconductor memory is placed under prescribed aging conditions; and a verification step (205,307) where data is read out and compared with the data written in said writing step for verification, said test method being characterised in that said aging step (204,304) is performed by forming a coating film for alleviating the stress applied to said nonvolatile semiconductor memory during assembly, without performing any separate aging step. A test method for a nonvolatile semiconductor memory according to claim 1, wherein said writing step (203) and said verification step (205) are performed by contacting probes with said nonvolatile semiconductor memory on a semiconductor wafer. A test method for a nonvolatile semiconductor memory according to claim 1, wherein said writing step (303) is performed by contacting probes with said nonvolatile semiconductor memory on a semiconductor wafer and said verification step (307) is performed during a final test process after said nonvolatile semiconductor memory is assembled. A test method for a nonvolatile semiconductor memory according to claim 1, 2, or 3, wherein said nonvolatile semiconductor memory is assembled in a plastic package.

Inventors: KASA YASUSHI, KUMAKURA SINSUKE, WATANABE HISAYOSHI, YAMAZAKI HIROKAZU, KASA, YASUSHI, KUMAKURA, SINSUKE, WATANABE, HISAYOSHI, YAMAZAKI, HIROKAZU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1994
Main classification: G11C29
IPC codes: G11C5, G11C29, G11C7