Coding apparatus for image compression

Abstract: A coding apparatus for image compression of the present invention comprises a transformer that transforms image data into a plurality of transform coefficients, a quantizer that quantizes each of the transform coefficients into a coefficient data of a predetermined number of bits, a data divider that divides the coefficient data into a fixed-length data part and a variable-length data part and a variable-length encoder that encodes the variable-length data part into a variable-length code.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to coding apparatus for image compression that compresses the data of a digital image signal. 2. Description of the Related Art As a highly efficient compression technique for encoding natural images, there has been proposed a method of performing a 2-dimensional discrete cosine transform (called DCT hereafter) and quantizing the transform coefficients to encode them into variable-length codes. This method is adopted by the JPEG (Joint Photographic Experts Group) of CCITT/ISO. The variable-length coding part of this method uses a single table of codes to perform variable-length coding. However, if statistical properties of input symbols and characteristics of the variable-length coding are in disagreement, the efficiency of coding declines. Therefore, a method of preparing several tables of variable-length codes and selecting one of them for encoding was proposed (for example, JP-A-4-87469). In this method, the variance of the DCT coefficients after quantizing in each block is obtained, and one of the several tables of variable-length codes is selected based on the variance to perform variable-length coding. However, the statistical properties of occurring symbols vary not only from block to block but also greatly vary depending on the order of the transformed domain in each block. Therefore, by the above method, a table of variable-length codes can not be selected depending on the order of the transformed domain. Further, the method requires much more overhead information for indicating a selected table of variable-length codes. SUMMARY OF THE INVENTION The object of the present invention is therefore to solve the above problems and to provide a coding apparatus for image compression that improves the efficiency of variable-length coding. In order to achieve the aforementioned objective, according to the present invention, there is provided a coding apparatus for image compression comprising a transform means which transforms image data into a plurality of transform coefficients, a quantization means which quantizes each of said transform coefficients into a coefficient data word of a predetermined number of bits, a data division means which divides each coefficient data word corresponding to a low-frequency domain into a first data part and a second data part, a multiplexer means which multiplexes the second data part and a coefficient data word corresponding to a high-frequency domain, and a variable-length coding means which encodes the output from said multiplexer means into a variable-length code. Further advantageous embodiments are defined in the dependent claims. By this composition, statistical properties of occurring symbols representing run length and gray level can be made similar in all the transformed blocks, so that the efficiency of variable-length coding is improved. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram of a coding apparatus for image compression of a first embodiment in accordance with the present invention; Fig. 2 is a block diagram of a coding apparatus for image compression of a second embodiment in accordance with the present invention; Fig. 3 is a block diagram of a coding apparatus for image compression of a third embodiment in accordance with the present invention; Fig. 4 is a block diagram of a coding apparatus for image compression of a fourth embodiment in accordance with the present invention; Fig. 5 is a conceptual schema for describing zigzag scanning of a DCT; Fig. 6 shows a quantization table in the quantization step for DCT coefficients; Fig. 7 is a conceptual schema for describing the operation of a first data-division circuit in the present embodiments; Fig. 8 shows an example of DCT coefficient data after being quantized in the present embodiments; Fig. 9 is a conceptual schema for describing the operation of a second data-division circuit in the present embodiments; Fig.10 is a block diagram of a decoding apparatus for decoding compression-coded data according to the present invention; and Fig. 11 is a conceptual schema for describing integration operation of fixed-length data and variable-length data to be preformed by the decoding apparatus of Fig. 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments according to the present invention will be described below with reference to the accompanying drawings. Fig. 1 is a block diagram of a coding apparatus for image compression of a first embodiment in accordance with the present invention. In Fig. 1, numeric reference 1 denotes a terminal for inputting image data, 10 denotes a blocking circuit that segments the image data into 8 × 8 blocks, 20 denotes a DCT circuit that performs a DCT of each 8 × 8 block, 30 denotes a zigzag-scanning conversion circuit, 40 denotes a quantization circuit that quantizes DCT coefficients into coefficient data words, 50 denotes a symbol generating circuit that counts the length of consecutive zero coefficient data (zero-run) and obtains the group number of the succeeding non-zero coefficient data (run-level) to output a combination of the zero-run and run-level and overhead bits, 60 denotes a 2-D Huffman coding circuit that deems the run-level as a symbol and generates a variable-length code corresponding to the symbol by looking up a table of 2-dimensional Huffman codes and multiplexes the code with the overhead bits, 70 denotes a terminal for outputting the result. 80 denotes terminal for outputting the DC component of the DCT coefficients, 100 denotes a first data-division circuit that divides each coefficient data word corresponding to a low-frequency domain into a first data part and a second data part, 110 denotes an output terminal for outputting the first data parts as fixed-length data parts, 120 denotes a multiplexer that multiplexes the second part output from first data-division circuit 100 and high-frequency components of coefficient data. The operation of the coding apparatus for image compression composed as above is described in the following with reference to Fig. 1. First, image data input through input terminal 1 is segmented into 8 × 8 blocks by blocking circuit 10 and is transformed into 8 × 8 (= 64) DCT coefficients by DCT circuit 20. The DCT coefficients are reordered by zigzag-scanning conversion circuit 30 to be output in the zigzag-scanning order as shown in Fig. 5, and are quantized by quantization circuit 40 with quantizing values as shown in Fig. 6. After the quantization, the DC component of the quantized DCT coefficients is encoded into a fixed-length code and output to output terminal 80. Of the AC components of the quantized DCT coefficients, the first 4 coefficient data in the zigzag-scanning order, which correspond to a low-frequency domain, are output to first data-division circuit 100, and the remaining coefficient data of the AC components are output to multiplexer 120. First data-division circuit 100 divides an input coefficient data word (consisting of 11 bits including a sign bit in the present embodiment) into the first data part consisting of the lowest one bit and the second data part consisting of the remaining upper 10 bits, as shown in Fig. 7. The second data part is output to multiplexer 120, and the first data part is output to output terminal 110. Multiplexer 120 multiplexes four coefficients of a low-frequency domain in the variable-length data part output from first data-division circuit 100 and 59 coefficient data of the remaining AC components output from quantization circuit 40 to output the result into symbol generating circuit 50. Symbol generating circuit 50 outputs overhead bits and a run-level symbol obtained by combining a zero-run and the group number of the succeeding non-zero coefficient data into 2-D Huffman coding circuit 60. 2-D Huffman coding circuit 60 generates a variable-length code corresponding to the input run-level symbol and overhead bits to output the code to output terminal 70. In the following, the characteristics of the present embodiment of a coding apparatus for image compression is compared with an apparatus of the JPEG. Fig. 8 shows an example of the DCT coefficient data after being quantized in the present embodiment. Table 1 is a look-up table of the 2-dimensional Huffman codes. Table 2 is the look-up table of the correspondence between the values of non-zero coefficient data and group numbers and the numbers of overhead bits. Table 3 shows an example of variable-length coding in a JPEG apparatus and the required number of bits. The results in Table 3 was obtained by performing the variable-length coding of the DCT coefficient data shown in Fig. 8. Value of AC coefficient Group number Number of overhead bits -1,1 1 1 -3,-2,2,3 2 2 -7,-6,-5,-4,4,5,6,7 3 3 -15,-14,..,-8,8,..14,15 4 4 -31,-30,..,-16,16,..,30,31 5 5 -63,-62,..,-32,32,..,62,63 6 6 -127,-126,..,-64,64,..,126,127 7 7 -255,-254,..,-128,128,..254,255 8 8 -511,-510,..,-256,256,..510,511 9 9 -1023,-1022,..,-512,512,..,1022,1023 10 10 Run-level symbol 2-D Huffman code Number of overhead bits 0-4 1011(4bit) 4bit 0-4 1011(4bit) 4bit 0-4 1011(4bit) 4bit 0-4 1011(4bit) 4bit 1-3 1111001(7bit) 3bit 0-3 100(3bit) 3bit 3-1 111010(6bit) 1bit EOB 1010(4bit) Total 59bit Table 4 shows the output data of the signal processing for variable-length coding in the present embodiment for the DCT coefficient data shown in Fig. 8. In Table 4, (a) shows the processing of dividing each of the netted 4 coefficient data of a low-frequency domain into a fixed-length first data part of one bit and a variable-length second data part of 10 bits. (b) shows the input data to symbol generating circuit 50, and (c) shows the variable-length coding of the AC components and the required number of bits. (a) Data division of 4 coefficient of a low-frequency domain Coefficient data (11bit) Variable-length data part (10bit) Fixed-length data part (1bit) -14 -7 0 (11111110010) (1111111001) -9 -5 1 (11111110111) (1111111011) 8 4 0 (00000001000) (0000000100) -8 -4 0 (11111111000) (1111111100) (b) Input to the symbol generating circuit DC -7 0 5 0 0 0 0 -5 -4 -6 0 0 0 0 0 4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) The number of bits required for encoding the AC components Run-level symbol 2-D Huffman code Number of overhead bits Fixed-length data part 0-3 100(3bit) 3bit 0(1bit) 0-3 100(3bit) 3bit 1(1bit) 0-3 100(3bit) 3bit 0(1bit) 0-3 100(3bit) 3bit 0(1bit) 1-3 1111001(7bit) 3bit 0-3 100(3bit) 3bit 3-1 111010(6bit) 1bit EOB 1010(4bit) Total 55bit As seen from Tables 3 and 4, the encoding of the AC components requires 55 bits in the present embodiment, while the encoding of the AC components in a JPEG apparatus requires 59 bits. Therefore, the efficiency of encoding is improved in the present embodiment. Table 5 shows the correspondence between DCT coefficient data and the group numbers in a JPEG apparatus and the correspondence between the coefficient data and the variable-length data parts in the present embodiment. As seen from Table 5, the group number of a coefficient data in the present embodiment is almost always one less than the group number of the same coefficient data word in a JPEG apparatus, so that the number of overhead bits decreases by one. As the group numbers decline, shorter variable-length codes are assigned to the generated run-revel symbols, so that efficiency is improved. The improvement in the number of bits is due to these shorter variable-length codes, and the decrease in the number of overhead bits are canceled by the increase in the number of bits required for the one-bit fixed-length data part. As described above, according to the present embodiment, there is provided a data division means for dividing each of the 4 coefficient data of a low-frequency domain of the AC components into a first data part of one bit and a second data part of 10 bits. The first data parts are encoded into fixed-length codes, and the second data parts are encoded into variable-length codes together with the remaining 59 coefficient data of the AC components. As a result, efficiency of variable-length coding is improved, and the number of bits required for encoding the AC components is reduced. Although, in the present embodiment, each lowest one bit of the 4 coefficient data of a low-frequency domain of the AC components is selected as a fixed-length data part, the number of coefficient data to be divided and the number of bits to be assigned to the fixed-length data part are not limited to these particulars. If they are varied depending on the characteristics of input image data and the quantization step or the order of DCT coefficient data, then further improvement can be expected. Table 6 shows the output data of each section of signal processing in case the bit assignment for the fixed-length data part is changed. The number of coefficient data to be divided remains 4, and the number of bits assigned to the fixed-length data parts are 2, 2, 2, and 1. (a) Data division of 4 coefficient of a low-frequency domain Coefficient data (11bit) Variable-length data part Fixed-length data part -14 -4 2 (11111110010) (111111100) (10) -9 -3 3 (11111110111) (111111101) (11) 8 2 0 (00000001000) (000000010) (00) -8 -4 0 (11111111000) (111111100) (0) (b) Input to the symbol generating circuit DC -4 0 5 0 0 0 0 -3 -4 -6 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) The number of bits required for encoding the AC components Run-level symbol 2-D Huffman code Numer of overhead bits Fixed-length data part 0-3 100(3bit) 3bit 10(2bit) 0-2 01(2bit) 2bit 11(2bit) 0-2 01(2bit) 2bit 00(2bit) 0-3 100(3bit) 3bit 0(1bit) 1-3 1111001(7bit) 3bit 0-3 100(3bit) 3bit 3-1 111010(6bit) 1bit EOB 1010(4bit) Total 54bit In Table 6, (a) shows the data division, (b) shows the variable-length data parts and the remaining 59 coefficient data of the AC components, which are input to symbol generating circuit 50, and (c) shows the 2-dimensional Huffman coding of the AC components and the required number of bits. The results show the number of bits required for encoding the AC components declines to 54 bits, so that further improvement is achieved. Next, an image decoding apparatus for decoding codes compression-coded according to the image compression-coding apparatus of the present invention will be explained herein below with reference to Fig. 10 showing a block diagram of the image decoding apparatus. As shown in Fig. 10, the image decoding apparatus comprises an input terminal 400 of a fixed-length data, an input terminal 410 of a variable-length data, an input terminal 420 of a DC component, a 2-D Huffman decoding circuit 430 for decoding the input variable-length data to coefficient data, a data integration circuit 440 for integrating the fixed-length data and variable-length data input from the input terminals 400 and 410, respectively, a multiplexer 445 for multiplexing DC component and AC component of coefficient data, an inverse quantization circuit 450, a zigzag scan inverse conversion circuit 460, an inverse DCT circuit 470, a block-resolving circuit 480 for converting the blocked image signal into data of an original format input to the input terminal 410 and an output terminal 490 for outputting an output corresponding to the input image. In operation of the compression decoding apparatus, the variable-length codes input from the input terminal 410 are variable-length decoded by 2-D Huffman decoding circuit 430 and output as coefficient data. Among output coefficient data, first four coefficients are output to the data integration circuit 440 and remaining six coefficients as AC components are output to the multiplexer 445. The data integration circuit 440, as shown in Fig. 12, integrates a fixed-length data of 1 bit input from the input terminal 400 and a coefficient data of 10 bits decoded by 2-D Huffman decoding circuit 400 and outputs a coefficient data of 11 bits with a sign to the multiplexer 445. The multiplexer 445 multiplexes a DC component input from the input terminal 420, first four coefficient data of a zigzag scan data input from the integration circuit 440 and remaining coefficient data and the multiplexed data are output to the inverse quantization circuit 450. The inverse quantization circuit 450 inverse-quantizes the quantized coefficient data to output it to the zigzag-scan inverse conversion circuit 460. The zigzag-scan inverse conversion circuit 460 rearranges the DCT coefficients once arranged in the order shown in Fig. 6 to the original order and outputs it to the inverse DCT circuit 470. The inverse DCT circuit 470 converts DCT conversion coefficients to an image data forming a block, and the block resolving circuit 480 converts the image data divided into blocks into the original format as input to the input terminal 1 and outputs the converted image data through the output terminal 490. Thus, the image data decoding apparatus having the above mentioned composition is able to decode an output signal from the image data compression-coding apparatus input divided into fixed-length and variable-length coded blocks and obtain an image data decoded. In the following is described a second embodiment in accordance with the present invention with reference to the accompanying drawings. Fig. 2 is a block diagram of a coding apparatus for image compression of the present embodiment. In Fig. 2, a block that has the same function as in Fig. 1 is denoted by the same numeral. In Fig. 2, 130 is a second data-division circuit that divides each coefficient data word corresponding to a low-frequency domain into a first data part including the sign bit and a second data part, and 200 is a data conversion circuit that converts the second data parts. The operation of the coding apparatus for image compression composed as above is described in the following with reference to Fig. 2. First, image data input through input terminal 1 is segmented into 8 × 8 blocks by blocking circuit 10 and is transformed into 8 × 8 (= 64) DCT coefficients by DCT circuit 20. The DCT coefficients are reordered by zigzag-scanning conversion circuit 30 to be output in the zigzag-scanning order, and are quantized by quantization circuit 40. The DC component of the quantized DCT coefficients is encoded into a fixed-length code and output to output terminal 80. Of the AC components of the quantized DCT coefficients, the first 4 coefficient data in the zigzag-scanning order, which correspond to a low-frequency domain, are output to second data-division circuit 130, and the remaining coefficient data of the AC components are output to multiplexer 120. Second data-division circuit 130 divides an input coefficient data word (consisting of 11 bits including a sign bit) into a first data part consisting of a sign bit and a second data part consisting of the remaining 10 bits. The second data part is output to data conversion circuit 200, and the fixed-length data part is output to output terminal 110. Data conversion circuit 200 performs the following data conversion depending on the lowest bit of the input second data part. If the lowest bit is 1, then the lowest bit is discarded and the remaining 9 bits are inverted. If the lowest bit is 0, then the lowest bit is discarded. The second data parts converted in this way and the remaining coefficient data of the AC components other than the 4 coefficient data of a low-frequency domain are multiplexed by multiplexing circuit 120, and output to symbol generating circuit 50. Symbol generating circuit 50 processes the converted variable-length data part of the 4 coefficient data and the remaining 59 coefficient data as in a JPEG apparatus. Finally 2-D Huffman coding circuit 60 outputs a variable-length code to output terminal 70. In the following, the characteristics of the present embodiment of a coding apparatus for image compression is compared with an apparatus of the JPEG. Table 7 shows the output data of the signal processing for variable-length coding in the present embodiment for the DCT coefficient data shown in Fig. 8. (a) Data division of 4 coefficients of a low-frequency domain Coefficient data (11bit) Fixed -length data part (lbit) Variable-length data part (10bit) Converted variable-length data part (9bit) -14 1 -14 -7 (11111110010) (1) (1111110010) (111111001) -9 1 -9 4 (11111110111) (1) (111110111) (000000100) 8 0 8 4 (00000001000) (0) (0000001000) (000000100) -8 1 -8 -4 (11111111000) (0) (1111111000) (111111100) (b) Input to the symbol generating circuit DC -7 0 5 0 0 0 0 4 -4 -6 0 0 0 0 0 4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) The number of bits required for encoding the AC components Run-level symbol 2-D Huffman code Numer of overhead bits Fixed-length data part 0-3 100(3bit) 3bit 1(1bit) 0-3 100(3bit) 3bit 1(1bit) 0-3 100(3bit) 3bit 0(1bit) 0-3 100(3bit) 3bit 1(1bit) 1-3 1111001(7bit) 3bit 0-3 100(3bit) 3bit 3-1 111010(6bit) 1bit EOB 1010(4bit) Total 55bit In Table 7, (a) shows the processing of dividing the netted 4 coefficients of a low-frequency domain into a fixed-length first data part of one sign bit and a variable-length second data part of 10 bits. (b) shows the converted second data part and the remaining 59 coefficient data of the AC components, which are input to symbol generating circuit 50. (c) shows the variable-length coding of the AC components and the required number of bits. As seen from Table 3, which shows the number of bits required for variable-length coding in a JPEG apparatus, and Table 7, the encoding of the AC components requires 55 bits in the present embodiment, while the encoding of the AC components in a JPEG apparatus requires 59 bits. Therefore, the efficiency of encoding is improved in the present embodiment. Table 8 shows the correspondence between DCT coefficient data and the group numbers in the JPEG apparatus and the correspondence between the coefficient data and the variable-length data parts in the present embodiment. As seen from Table 8, the group number of a coefficient data in the present embodiment is almost always one less than the group number of the same coefficient data in the JPEG apparatus, so that the number of overhead bits decreases by one. As the group numbers decline, shorter variable-length codes are assigned to the generated run-revel symbols, so that efficiency is improved. The improvement in the number of bits is due to these shorter variable-length codes, and the decrease in the number of overhead bits are canceled by the increase in the number of bits required for the one-bit fixed-length data part. In order to recover the original coefficient data, each of the converted variable-length data parts are first reproduced, and the result is combined with the corresponding fixed-length data part. The reproduction of variable-length data part is described in the following with reference to Table 8. If the exclusive OR of a converted variable-length data part and the sign bit of a corresponding fixed-length data part is the logical value 1, then the converted variable-length data part is inverted, then shifted left by one bit, and the lowest bit is made 1. For example, if the converted variable-length data part is -4, and the sign bit of the fixed-length data part is 0, then the converted variable-length data part becomes 3 by inversion, and then becomes 6 by one-bit left shift, and becomes 7, which is the original coefficient data word, by the addition of 1 in the lowest bit. If the exclusive OR of a converted variable-length data part and the sign bit of a corresponding fixed-length data part is the logical value 0, then the converted variable-length data part is shifted left by one bit, and the lowest bit is made 0. For example, if the converted variable-length data part is 4, and the sign bit of the fixed-length data part is 0, then the converted variable-length data part becomes 8 by the one-bit left shift, and becomes 8, which is the original coefficient data word, by the addition of 1 in the lowest bit. The other converted variable-length data parts are similarly reconverted to the original variable-length data parts. As described above, according to the present embodiment, there are provided a data division means for dividing each of the 4 coefficient data of a low-frequency domain of the AC components into a first data part of one sign bit and a second data part of 10 bits and a data conversion means for converting the variable-length data part. The first data part is encoded into a fixed-length code, and the converted second data parts are encoded into variable-length codes together with the remaining 59 coefficient data of the AC components. As a result, efficiency of variable-length coding is improved, and the number of bits required for encoding the AC components is reduced. In the present embodiment, each sign bit of the 4 coefficient data words of a low-frequency domain of the AC components is selected as a fixed-length data part, and no lower bits were assigned to the fixed data part. However, the number of bits to be assigned to the fixed-length data part is not limited to this particular. Fig. 8 shows the output data of each section of signal processing in case the bit assignment for fixed-length data parts is changed. The number of coefficient data to be divided remains 4, and in addition to the sign bit, the number of the lowest bits assigned to the fixed-length data parts are 1, 1, 1, and 0. (a) Data division of 4 coefficients of a low-frequency domain Coefficient data part (11bit) Fixed-length data part Variable-length data part Converted variable -length data part -14 2 -7 3 (11111110010) (10) (111111001) (00000011) -9 3 -9 2 (11111110111) (11) (111111011) (00000010) 8 0 8 2 (00000001000) (00) (000000100) (00000010) -8 1 -8 -4 (11111111000) (1) (1111111000) (111111100) (b) Input to the symbol generating circuit DC 3 0 5 0 0 0 0 2 -4 -6 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) The number of bits required for encoding the AC components Run-level symbol 2-D Huffman code Numer of overhead bits Fixed-length data part 0-2 01(2bit) 2bit 2(2bit) 0-2 01(2bit) 2bit 3(2bit) 0-2 01(2bit) 2bit 0(2bit) 0-3 100(3bit) 3bit 1(1bit) 1-3 1111001(7bit) 3bit 0-3 100(3bit) 3bit 3-1 111010(6bit) 1bit EOB 1010(4bit) Total 52bit In Table 9, (a) shows the data division, the converted variable-length second data parts, and the fixed-length first data parts. (b) shows the second data parts and the remaining 59 coefficient data of the AC components to be input to symbol generating circuit 50, and (c) shows the 2-dimensional Huffman coding of the AC components and the required number of bits. The results show the number of bits required for encoding the AC components declines to 52 bits, so that further improvement is achieved. In the following is described a third embodiment in accordance with the present invention with reference to the accompanying drawings. Fig. 3 is a block diagram of a coding apparatus for image compression of the present embodiment. In Fig. 3, a block that has the same function as in Figs. 1 and 2 is denoted by the same numeral. In Fig. 3, 300 is a first absolute-value conversion circuit that converts a coefficient data word into its sign bit and absolute value. The operation of the coding apparatus for image compression composed as above is described in the following with reference to Fig. 3. First, image data input through input terminal 1 is segmented into an 8 × 8 block by blocking circuit 10 and is transformed into 8 × 8 (= 64) DCT coefficients by DCT circuit 20. The DCT coefficients are reordered by zigzag-scanning conversion circuit 30 to be output in the zigzag-scanning order as shown in Fig. 5, and are quantized by quantization circuit 40. The DC component of the quantized DCT coefficients is encoded into a fixed-length code and output to output terminal 80. Of the AC components of the quantized DCT coefficients, the first 4 coefficient data in the zigzag-scanning order, which correspond to a low-frequency domain, are first converted into a data word expressed by the combination of its sign bit and absolute value and then output to second data-division circuit 130, and the remaining coefficient data words of the AC components are output to multiplexing circuit 120. As shown in Fig. 9, second data-division circuit 130 divides an input data word (consisting of one sign bit and 10 absolute-value bits) into a first data part consisting of the sign bit and a second data part consisting of the remaining 10 bits expressing the absolute value. The second data part is output to data conversion circuit 200, and the first data part is output to output terminal 110. Data conversion circuit 200 performs the following data conversion depending on the lowest bit of the input variable-length data part. If the lowest bit is 1, then the lowest bit is discarded and the remaining 9 bits are inverted. If the lowest bit is 0, then the lowest bit is discarded. The second data parts converted in this way and the remaining 59 coefficient data words of the AC components other than the 4 coefficient data words of a low-frequency domain are multiplexed by multiplexing circuit 120 and converted to 2-dimensional Huffman codes through symbol generating circuit 50 and 2-D Huffman coding circuit 60 to be output to terminal 70. The present embodiment performs data conversion in first absolute-value conversion circuit 300 as preprocessing for the second data division circuit 130 in the second embodiment. Table 10 shows the correspondence between DCT coefficient data and the group numbers in the JPEG apparatus and the correspondence between the coefficient data and the variable-length data parts in the present embodiment. As seen from Table 10, the group number of a coefficient data word in the present embodiment is almost always one less than the group number of the same coefficient data word in the JPEG apparatus, so that the number of overhead bits decreases by one. As the group numbers decline, shorter variable-length codes are assigned to the generated run-revel symbols, so that efficiency is improved. As described above, according to the present embodiment, there are provided an absolute-value conversion means for obtaining the absolute values of the 4 coefficient data words of a low-frequency domain of the AC components, a data division means for dividing an input data word into a first data part of one sign bit and a second data part of 10 bits expressing the absolute value, and a data conversion means for converting the second data part. The first data part is encoded into a fixed-length code, and the second data parts are encoded into variable-length codes together with the remaining 59 coefficient data words of the AC components. As a result, efficiency of variable-length coding is improved, and the number of bits required for encoding the AC components is reduced. Although, in the present embodiment, each one sign bit of the 4 coefficient data words of a low-frequency domain of the AC components is selected as a fixed-length data part, the number of coefficient data words to be divided and the number of bits to be assigned to the fixed-length data part are not limited to these particulars. A fourth embodiment in accordance with the present invention is described in the following with reference to the accompanying drawings. Fig. 4 is a block diagram of a coding apparatus for image compression of the present embodiment. In Fig. 4, a block that has the same function as in Figs. 1, 2, and 3 is denoted by the same numeral. In Fig. 4, 310 is a second absolute-value conversion circuit that converts a variable-length data part into its absolute value. The operation of the coding apparatus for image compression composed as above is described in the following with reference to Fig. 4. First, image data input through input terminal 1 is segmented into 8 × 8 blocks by blocking circuit 10 and is transformed into 8 × 8 (= 64) DCT coefficients by DCT circuit 20. The DCT coefficients are reordered by zigzag-scanning conversion circuit 30 to be output in the zigzag-scanning order, and are quantized by quantization circuit 40. The DC component of the quantized DCT coefficients is encoded into a fixed-length code and output to output terminal 80. Of the AC components of the quantized DCT coefficients, each of the first 4 coefficient data words in the zigzag-scanning order, which correspond to a low-frequency domain, is input to second data-division circuit 130, and the remaining coefficient data words of the AC components are output to multiplexing circuit 120. As shown in Fig. 9, second data-division circuit 130 divides an input data word (consisting of one sign bit and 10 absolute-value bits) into a first data part consisting of the sign bit and a second data part consisting of the remaining 10 bits. The second data part is output to second absolute-value conversion circuit 310, and the fixed-length data part is output to output terminal 110. Second absolute-value conversion circuit 310 converts the input second data part into its absolute value based on the sign bit and outputs the result to data conversion circuit 200. Data conversion circuit 200 performs the following data conversion depending on the lowest bit of the input second data part. If the lowest bit is 1, then the lowest bit is discarded and the remaining 9 bits are inverted. If the lowest bit is 0, then the lowest bit is discarded. The second data parts converted in this way is output to symbol generating circuit 50 via multiplexing circuit 120. Symbol generating circuit 50 processes the converted second data parts of the 4 coefficients and the 59 coefficient data words of the remaining AC components as in the first, second, and third embodiments to output overhead bits and run-level symbols. 2-D Huffman coding circuit 60 outputs a variable-length code for each run-level symbol and its overhead bits. The present embodiment performs data conversion in second absolute-value conversion circuit 310 as post-processing for second data-division circuit 130 in the second embodiment. In the present embodiment, since the fixed-length data part consists of one sign bit, the correspondence between the coefficient data words and the variable-length data parts is the same as in the third embodiment as shown in Table 10. However, if lower bits of the coefficient data word are assigned to its fixed-length data part in addition to its sign bit, the correspondence table becomes different from Table 10. As in the third embodiment, the group number of a coefficient data word in the present embodiment is often less than the group number of the same coefficient data word in the JPEG apparatus, so that the number of overhead bits decreases by one. As the group numbers decline, the shorter variable-length codes are assigned to the generated run-revel symbols, so that efficiency is improved. As described above, according to the present embodiment, there are provided a data division means for dividing each of the 4 coefficient data words of a low-frequency domain of the AC components into a first data part of one sign bit and a second data part of 10 bits, an absolute-value conversion means for converting each second data part into the absolute value of the coefficient data word, and a data conversion means for converting the absolute value of the second data part. The first data part is encoded into a fixed-length code, and the converted second data parts are encoded into variable-length codes together with the remaining 59 coefficient data words of the AC components. As a result, efficiency of variable-length coding is improved, and the number of bits required for encoding the AC components is reduced. Although, in the present embodiment, each one sign bit of the 4 coefficient data words of a low-frequency domain of the AC components is selected as a fixed-length data part, the number of coefficient data words to be divided and the number of bits to be assigned to the fixed-length data part are not limited to these particulars. Further, in the present first to fourth embodiments, the input image data was transformed by a DCT. However, the image data can be difference data between two frames, and the method of transformation can be other than a DCT. For example, an LOT, subband coding, and a wavelet transform can be applied to obtain similar effects.

Claims: A coding apparatus for image compression comprising a transform means (20, 30) which transforms image data into a plurality of transform coefficients, a quantization means (40) which quantizes each of said transform coefficients into a coefficient data word of a predetermined number x of bits, a data division means (100; 130) which divides each coefficient data word corresponding to a low-frequency domain into a first data part and a second data part, a multiplexer means (120) which multiplexes the second data part and a coefficient data word corresponding to a high-frequency domain, and a variable-length coding means (60) which encodes the output from said multiplexer means (120) into a variable-length code. The coding apparatus for image compression as defined in claim 1 wherein said first data part consists of a lower y bits of the coefficient data (y ≥ 1), The coding apparatus for image compression as defined in claim 2 wherein the bit number y of said first data part is fixed at a predetermined number. The coding apparatus for image compression as defined in claim 2 wherein the bit number y of said first data part is varied depending on the order of said transform coefficient. The coding apparatus for image compression as defined in claim 1, wherein said quantization means (40) quantizes each of transform coefficients preselected among all of said transform coefficients into a coefficient data word of predetermined number of bits, said data division means (130) divides each coefficient data word corresponding to a low-frequency domain into a first data part consisting of sign bit and lower z bits of said coefficient data (z ≥ 0) and a second data part consisting of remaining of said coefficient data, a data conversion means (200) is provided which , if the lowest bit of said second data part is logical 1, discards the lowest bit of said second data part and then inverts the result and, if the lowest bit of said second data part is logical 0, discards the lowest bit of said second data part, and said multiplexer means (120) multiplexes the converted second data part and the coefficient data word corresponding to the high-frequency domain. The coding apparatus for image compression as defined in claim 5 wherein said number (z) of lower bits is varied depending on the order of said transform coefficient. The coding apparatus for image compression as defined in claim 1, wherein an absolute-value conversion means (300) is provided which converts the transform coefficient data words preselected among all of said transform coefficients into its sign bit and (x - 1) bits expressing its absolute value, said data division means (130) divides each converted coefficient data word corresponding to a low-frequency domain into a first data part consisting of its sign bit and lower w bits (w ≥ 0) and a second data part consisting of the remaining (x - w - 1) bits, a data conversion means (200) is provided which, if the lowest bit of said second data part is logical 1, discards the lowest bit of said second data part and then inverts the result and, if the lowest bit of said second data part is logical 0, discards the lowest bit of said second data part, and said multiplexer means (120) multiplexes the converted second data part and the coefficient data word corresponding to the high-frequency domain. The coding apparatus for image compression as defined in claim 7 wherein said number w of lower bits is varied depending on the order of said transform coefficient. The coding apparatus for image compression as defined in claim 1, wherein said data division means (130) divides each transform coefficient data word corresponding to a low-frequency domain and preselected among all of said transform coefficient words into a first data part consisting of its sign bit and lower v bits (v ≥ 0) and a second data part consisting of the remaining (x - v- 1) bits, an absolute-value conversion means (320) is provided which converts said second data part into its absolute value of (x - v - 1) bits based on its sign bit, a data conversion means (200) that, if the lowest bit of said second data part is logical 1, discards the lowest bit of said second data part and then inverts the result and, if the lowest bit of said second data part is logical 0, discards the lowest bit of said second data part, and said multiplexer means (120) multiplexes the converted second data part and the coefficient data word corresponding to the high-frequency domain. The coding apparatus for image compression as defined in claim 9 wherein said number v of lower bits is varied depending on the orders of said transform coefficient.

Inventors: BANNAI TATSUSHI, MIYASHITA MITSUHIRO, BANNAI, TATSUSHI, MIYASHITA, MITSUHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: G06T9
IPC codes: H03M7, H04N1, G06T9