BiCMOS CURRENT MODE DRIVER AND RECEIVER

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Description: BiCMOS CURRENT MODE DRIVER AND RECEIVER FIELD OF THE INVENTION The present invention relates to the field of circuit design, and specifically to transmission of differential signals within an integrated circuit. BACKGROUND OF THE INVENTION In digital logic circuits information in the form of digital signals is processed so as to cause the logic circuit to perform a specific task or function. A digital signal generally has two states; a high level state and a low level state. Each logic state corresponds to some voltage potential. In other words the high logic state corresponds to a first voltage potential and the low state corresponds to a second voltage potential. The voltage potentials are determined by the design of the logic circuit. A digital signal is also characterized by its peak-to-peak voltage. The peak-to-peak voltage of a given digital signal is equal to its maximum signal voltage (i.e., the voltage potential corresponding to the high logic state) minus its minimum signal voltage (i.e., the voltage potential corresponding to the low logic state). Often times, certain applications within a logic circuit require a digital signal and the inverse of that digital signal (referred to as a differential signal) to be utilized. Typically, to transmit a differential signal from one part of an integrated circuit (IC) to another you need a transmitter to drive two interconnect lines with the differential signal and a receiver to detect the signals on these lines. The traditional method for differential signal transmission utilizes high power buffers for driving the interconnect lines. The buffers, (also referred to as line drivers), are differential amplifiers comprising two emitter-coupled transistors each having a resistive load coupled between their collector and a supply voltage. Their emitters are coupled to a current source. For differential signal transmission, a signal and its inverse is coupled to each of the bases of the emitter-coupled transistors. The differential amplifier compares the two input base signals. Depending on whether one of the base signals is less than or greater than the other, the differential amplifier steers the current established by the current source through one of the emitter-coupled transistors. This current flow causes a corresponding voltage drop across only one of the load resistors. At the same time, because no current flows through the other transistor, the collector of that transistor remains at approximately ground potential. The output of the differential amplifier is typically taken at the collector of each of the emitter- coupled transistors. Thus, one collector is always at a voltage potential corresponding to a low logic level and the other collector is at a voltage potential corresponding to a high logic level. The differential voltage signal outputted by the collectors is coupled to a pair of interconnect lines for transmission to receivers in other parts of the IC. Similar to the line drivers, the receivers comprise a pair of emitter coupled transistors each having a resistive load coupled between their collector and a supply voltage. A current source is coupled to their common emitters. The transmitted differential signal is coupled between the bases of the emitter-coupled pair and the output of the receiver is taken at their collectors. The receiver, in response to voltage changes on the interconnect lines, outputs a corresponding differential signal. Since this type of transmission system functions such that it detects changes in voltage in the transmitted signal, it is referred to as a voltage mode transmission system. Often times signals need to be transmitted along relatively long lines within the IC. A finite delay occurs from the time the signal transitions at the output of the transmitter to the time the input of the receiver detects the transition. This delay is directly related to the resistive loading of the line and its associated capacitance. For very long lines, delays can become large. The amount of delay of a transmitted signal due to line capacitance is also determined by the signals peak-to-peak voltage. For a given line having a specific associate line capacitance and resistive loading, longer delays occur for transmitted signals having relatively high peak-to-peak voltages than for lower voltages. For instance, a longer transition delay occurs on a specific interconnect line for a 700 mV peak-to-peak signal than a 20 mV peak-to-peak signal having the same current. The reason for this is because it takes a longer time for a signal to reach a 700 mV peak voltage as opposed to a 20 mV peak voltage. Thus, transmitting signals having low peak-to-peak voltages equates to reduced delay times. One type of transmission system that reduces delays by reducing peak-to-peak voltages operates in a manner in which differential current changes on the interconnect lines are detected instead of differential voltage changes. In a system in which differential current changes are detected, the signals are referred to as current mode signals; (as opposed to a system that detects voltage changes in voltage mode signals). Thus, instead of driving interconnect lines with differential voltage mode signals having relatively large changes in voltage, interconnect lines are driven with current mode signals having relatively large differential changes in current and small peak-to-peak voltage changes. Since peak voltages are reduced, so are the associated transmission delays. Examples of circuits for driving common mode signals are described in the article, "Current-Mode Techniques For High Speed VLSI Circuits With Application To Current Sense Amplifier For CMOS SRAM's," by E. Seevinck et al., USSC Vol. 26, No. 4 April, 1991. The current mode driver is basically the same as the voltage mode line driver except that the load resistors coupled to the collectors of the emitter-coupled transistors are eliminated. Specifically, the collectors of the emitter-coupled pair are coupled directly to the interconnect lines. Thus, instead of a differential voltage being developed across the interconnect lines, a reference current is routed through either one or the other interconnect line. This causes a differential current signal to be developed across the interconnect lines. This differential current signal is detected by the current mode receiver. One prior art current mode receiver, referred to as a cascode clamp, converts current mode signals into differential voltage mode signals while clamping the interconnect lines to a voltage of approximately 60 mV. The cascode clamp comprises two transistors each having their bases coupled to a reference voltage, VDD. A resistor is also coupled between each of their collectors and VDD. Each of the differential interconnect lines are coupled to one of the emitters of the cascoded pair. When a difference in current is detected at the emitters of the cascode pair, a corresponding differential voltage is established across their emitters. The magnitude of this differential voltage is an exponential function of the ratio of the current difference in the emitters of the cascoded pair. For bipolar transistors coupled in this manner, a 10: 1 ratio in the differential current results in a 60 mV voltage difference across the emitters at 25 degrees Celsius. Thus, for a current mode transmission system utilizing a pair of bipolar cascoded transistors, transmission delays are reduced because the cascode circuit clamps the differential peak-to-peak voltages on the interconnect lines. However, these reduced peak-to-peak voltage swings are still large enough to cause significant delays for very long distance signal transmission. The present invention is a circuit design for transmitting current mode signals. The current mode transmission system of the present invention utilizes a differential amplifier feedback circuit to clamp peak-to-peak voltages on interconnect lines while providing output signals peak voltage swings compatible with ECL logic. As a result, transmission delays associated with line capacitance are significantly reduced. SUMMARY OF THE INVENTION The present invention is a current mode signal transmission circuit. The transmission circuit includes a current mode driver and receiver. The receiver utilizes feedback to clamp peak-to-peak voltages of signals on differential interconnect lines while outputting signals having peak-to-peak swings compatible with ECL circuit design. The current mode driver of the present invention includes first pair of emitter-coupled transistors. The emitters of this first pair of transistors are coupled to a current source. In one embodiment the current source is an n-type metal oxide silicon (NMOS) device having its gate coupled to a reference voltage. The input differential signal to be transmitted is coupled to the bases of the emitter-coupled pair which causes a current mode differential signal to be established across the collectors of the emitter coupled pair. The collectors are coupled to a pair of interconnect lines. This current mode differential signal is transmitted along the interconnect lines to the current mode receiver of the present invention. The receiver converts the current mode signal to a voltage mode signal having a greater peak-to-peak voltage swing than the current mode signal. The receiver includes a second pair of transistors. Each of the emitters of the second pair of transistors are coupled to one of the interconnect lines. One embodiment of the present invention also includes MOS current sources coupled to each of the emitters of the second pair of transistors to bias them in their low resistance operating range. The bases of the third and fourth transistors are coupled to a feedback circuit. The feedback circuit is a differential amplifier having a third pair of emitter-coupled transistors, a current source, and a pair of load resistors. The differential amplifier's function is to drive the bases of the second pair of transistors in the opposite direction from which their corresponding emitters are moving. In this way, the interconnect lines are clamped to a voltage swing that is much less than the swing the receiver is trying to achieve. In one embodiment, a single current mode driver is coupled to a single current mode receiver. In this embodiment, the output of the receiver is taken at the collectors of the second pair of transistors. In another embodiment multiple drivers are coupled to a single receiver. In this case, the output of the receiver is at the collectors of the third pair of emitter-coupled transistors. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and wherein: Figure 1 is a circuit schematic diagram which illustrates the current mode driver and receiver of the present invention. Figure 2 is another embodiment of the present invention having multiple drivers coupled to a single receiver. DETAILED DESCRIPTION In the following description, a current mode driver and receiver is described in which numerous specific details are set forth, such as specific conductivity types, circuit configurations, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known structures and circuits have not been shown in detail in order to avoid unnecessarily obscuring the present invention. Figure 1 shows a circuit schematic diagram of one embodiment of the present invention. Matched NPN bipolar transistors Ql and Q2 and NMOS transistor Ml comprise the current mode line driver portion of the present invention. The emitters of Ql and Q2 are coupled to the drain of Ml. The source of Ml is coupled to a first supply voltage referred to as VSS. In the preferred embodiment, VSS is equal to -3 volts, however a 5 volt VSS is also acceptable. The gate of Ml is coupled to reference voltage VREF. VREF biases Ml to function as a constant current source such that Ml supplies a current equal to IREF. An input differential signal comprising IN and IN/ is coupled to the bases of Ql and Q2. It should be noted that IN/ is the inverse signal of IN. Consequently, when IN is high, IN/ is low and when IN/ is high, IN is low. As a result, the input differential signal causes either Ql or Q2 to be biased on and the other to be biased off. As is typical of differential amplifiers, the current supplied by current source Ml, is routed through either Ql or Q2 to either interconnect line 10 or 11. Thus, in the steady state the current through one of the interconnect lines is zero and the current through the other interconnect line is IREF. Interconnect lines 10 and 11 are coupled to the current mode receiver of the present invention. It should be noted that although interconnect lines 10 and 11 are represented as relatively short lines they can be any length. The current mode receiver comprises a cascode clamp portion and a feedback portion. The cascode clamp portion of the receiver includes matched NPN transistors Q5 and Q6, their resistive loads R3 and R4, and current source biased NMOS devices M2 and M4. The feedback portion includes matched transistors Q3 and Q4, their resistive loads Rl and R2, and current source biased NMOS device M3. As can be seen, VREF provides the bias voltage to the gates of M2, M3 and M4. These transistors are sized so they each provide the desired current. The differential amplifier portion of the receiver functions such that when the base-to-emitter voltages of Q3 and Q4 are equal, the current supplied by M3, i.e., 13, is split equally between Q3 and Q4. Thus, the current through each of the branches of the differential amplifier when V Q3) = V be (Q4) is (I3)/2. However, when the base-to- emitter voltage for one of the transistors is greater than the other, more current will be flowing through the transistor with the higher base-to-emitter voltage. Since more current is flowing in one branch and less current is flowing through the other, the voltage at one of the collectors of the emitter-coupled transistors will begin to fall while the other rises. In other words, a differential voltage signal is developed across the collectors of Q3 and Q4. The cascode portion of the receiver functions similar to prior art cascode clamp designs, in that when the current through their emitters are unequal, their base-to-emitter voltages correspondingly adjust. Specifically, V bc (Q5) - V^Qό) = (NT) x In(I5/I6), ignoring the base resistance (Rb) of Q5 and Q6. In the embodiment shown in Figure 1, where the cascode pair are ΝPΝ transistors, when the ratio of the emitter currents of Q5 and Q6 is 10: 1 the difference between their base-to-emitter voltages is equal to about 60 mV (at a temperature of 25 degrees Celsius). In the case when the current mode receiver is in a state in which the driver is not supplying any current to interconnect lines 10 and 11, i.e. I(line 10) = I(line 11) = 0, then 15 = 12, 16 = 14 and 13 is split equally between the branches of the receiver's differential amplifier. As a result voltage potentials are mirrored throughout the receiver, i.e., V(node 1 ) = V(node 3) and V(node 2)= V(node 4). Further, the differential voltage between the output lines OUT and OUT/ is zero since V(OUT) = V(OUT/). . In the case where IN is high and IN/ is low, IREF is steered through Ql. As a result the current through line 10 is equal to IREF and the current through line 11 is approximately zero. This causes 15 to start to increase and 16 to remain equal to 14. Because Q5 and Q6 function as a cascode pair, when 15 begins to increase, the emitter of Q5 (node 2) begins to drop below the emitter of Q6 (node 4). In addition, as 15 increases, the collector current of Q3 decreases. Q3 operates in the region in which its collector current is related to its base-to-emitter voltage (V b .) such that Ic = IS(e Vbe vl , (where IS is the saturation current of Q3 and ignoring the base resistance of Q3). So, as 15 increases, Ic(Q3) decreases, because the V-^ of Q3 decreases. This is due to the node 2 potential going negative with respect to node 4. At this point, 13 no longer splits equally between the two branches of the differential amplifier. Instead, more of 13 is routed through Q4 and R2. Thus, the current through Rl decreases while the current through R2 increases. This causes a corresponding increase in voltage potential at node 1 and a decrease in voltage potential at node 3. Node 1 increases and node 3 decreases, as node 2 decreases until the delta ^ of Q6 and Q5 is such that the above equation is satisfied. As mentioned above, node 2 (the emitter of Q5) tries to approach a voltage potential equal to [(VT) x In(I5/I6)] below node 4 (the emitter of Q6). However, due to the movement of nodes 1 and 3, node 2 never reaches that potential. In other words, instead of the voltage potential at node 2 dropping below node 4 by [(VT) x In(I5/I6)] to adjust for the difference in currents between Q5 and Q6, the potentials on node 1 and 3 contribute to part of the delta(vbe) between Q5 and Q6. Resistors Rl and R2 are chosen so that they supply the appropriate potential to the bases Q5 and Q6 to achieve the minimum stable differential voltage at nodes 2 and 4. As can be seen, the peak-to-peak voltage of interconnect line 10 is clamped to a voltage potential less than (VT) x In(I5/I6), (i.e., less than 60 mV at 25 degrees Celsius for an NPN cascode pair clamp). The magnitude of the voltage swing on nodes 1 and 3 is much higher than that of nodes 2 and 4. However, since nodes 1 and 3 are generally low capacitance short interconnect lines relative to interconnect lines 10 and 11, signal delays on these lines are minimal. Thus, the present invention reduces delays by reducing the voltage swing of the differential signals sent along logic circuit interconnect lines 10 and 11. The outputs of the receiver, OUT and OUT/, are taken at the collectors of Q5 and Q6. For the example in which IREF is flowing through interconnect line 10, OUT/ is equal to VDD - (R3 x IREF) and OUT is VDD-(R4 x 14). Since IREF is much greater than 14, OUT is high and OUT/ is low. Resistors R3 and R4 are chosen so that the receiver outputs the desired peak-to-peak voltage. The output of the receiver needs to have a peak-to-peak swing that interfaces with subsequent logic gates. Consequently, the selected magnitude of the peak-to-peak voltages, (and R3 and R4) depend on the type of logic design to be utilized. For instance, for emitter-coupled logic (ECL) the typical peak-to-peak voltage is 750 mV. In general, logical output peak-to-peak voltages range from 250 mV - 750 mV. Current sources M2 and M4 in Figure 1 function to provide a low level current to bias the cascode clamp transistors in their low resistance region. This reduces the transient recovery time on lines 10 and 11. As can be seen in Figure 1, M2 biases Q5 and M4 biases Q6. In the above description, all of IREF is routed through interconnect line 10 when IN is high and IN/ is low. When IN is low and IN/ is high all of IREF is routed through interconnect line 11. When this occurs, 16 starts to increase and 15 remains equal to 12. Similar to the previous description, node 4 and the internal nodes of the receiver, nodes 3 and 1, adjust until the delta ^) of Q6 and Q5 is such that the equation, deltaC -jJ between Q6 and Q5 = [(VT) x In(I6/I5)] is true. Node 4 (the emitter of Q6) tries to approach a voltage potential equal to [(VT) x In(I6/I5)] below node 2 (the emitter of Q5). However, due to the movement of nodes 1 and 3, node 4 never reaches that potential. Thus, the peak-to-peak voltage of interconnect line 11 is clamped to a voltage potential less than [(VT) x In(I6/I5)], (i.e., less than the 60 mV at 25 degrees Celsius for an NPN cascode pair clamp). Since IREF is flowing through interconnect line 11, OUT is equal to VDD - (R4 x IREF + 14) and OUT/ is equal to VDD - (R3 x 12). Since IREF is much greater than 12, OUT is low and OUT/ is high. Figure 2 shows another embodiment of the present invention. In this embodiment multiple current mode drivers are coupled to a pair of interconnect lines and a single current mode receiver. Referring to Figure 2, it should be noted that current mode drivers 1 and 2 are shown in close proximity, however they may be located anywhere within the IC. In addition, more than two drivers may be coupled to interconnect lines 10 and 11. Current mode driver 1 includes NPN transistors Ql and Q2 and current mode driver 2 includes Q8 and Q9. NMOS device Ml is biased to function as a current source by VREF. Ml supplies IREF to either of the drivers depending on control signals SI and S2. Select transistors Q7 and Q10 are controlled by signals SI and S2. Control signals SI and S2 determine which current mode driver transmits its corresponding data to the current mode receiver. For example when SI is high and S2 is low, IREF flows through Q7 and current mode driver 1. When this occurs, the data on the input of current mode driver 1, i.e., INI and INI/, is transmitted to the current mode receiver in the form of a current mode signal. Current mode driver 2 has no effect on lines 10 and 11 since Q10 is off and no current flows through Q8 or Q9. Similarly, when SI is low and S2 is high, IREF flows through Q10 and current mode driver 2. When this occurs, the data on the input of current mode driver 2, i.e. IN2 and IN2/, is transmitted to the current mode receiver in the form of a current mode signal. Current mode driver 1 has no effect on lines 10 and 11 since Q7 is off and no current flows through Ql or Q2. The current mode receiver converts the current mode signal from the selected driver into a differential voltage mode signal. The current mode receiver in Figure 2 includes cascode clamp transistors Q5 and Q6 and their corresponding NMOS biasing current sources M2 and M4. M2 and M4 are biased by VREF and are sized so as to provide a selected biasing current. Devices M2 and M4 function to bias Q5 and Q6 in their low resistance regions to ensure quick recovery from transients. The cascode clamp portion of the receiver includes matched load resistors R5 and R6. These resistors are the loads of the feedback amplifier which help reduce the voltage excursion at nodes 2 and 3. Under certain circumstances during the switching between the drivers, the total current injection into the transmission lines is greater than IREF. This may result in saturating the cascode amplifier. Therefore, the output is not taken from the collectors of the cascode amplifier, but rather at the collectors of the feedback amplifier Q3 and Q4. R7 and R8 are added to increase the gain to produce the required swing. The current mode receiver in Figure 2 functions in the same manner as the previously described current mode receiver shown in Figure 1. Thus, similar to the embodiment shown in Figure 1, smaller voltage swings are seen on the interconnect lines (nodes 2 and 4) while relatively larger voltage swing occur on internal nodes 1 and 3 of the receiver. Consequently, transmission delays are reduced since the peak-to-peak voltage swing on the interconnect lines is reduced. In addition, in contrast to prior art current mode receivers in which peak-to-peak swings are limited to 60 mV (or slightly higher depending on temperature and current densities), the range of output swing of the present invention's receiver is more versatile. Although the present invention has been described in conjunction with certain embodiments, it is appreciated that the invention may be implemented in a variety of other ways. By way of example, the concept of the present invention is not strictly limited to a BiCMOS circuit; it can be implemented with just bipolar devices. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.

Claims: I Claim: 1. An apparatus for reducing transmission delays of a first differential signal comprising: a transmitting means for converting said first differential signal into an intermediate differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said first differential signal, said transmitting means coupling said intermediate differential signal on first and second interconnect lines; a receiving means for converting said intermediate differential signal into an output differential signal having a peak-to-peak voltage greater than said peak-to-peak voltage of said intermediate differential signal in response to said intermediate differential signal, said receiving means loading said first and second interconnect lines such that said peak-to-peak voltage of said intermediate differential signal is driven to a specific magnitude; said receiving means also including a feedback means for clamping said peak-to-peak voltage of said intermediate differential signal to a magnitude less than said specific magnitude, said feedback means being coupled to said first and second interconnect lines. 2. The apparatus as described in claim 1 wherein said feedback means comprises a differential amplifier responsive to differential current in said intermediate differential signal. 3. The apparatus as described in claim 2 wherein said receiving means comprises a pair of transistors responsive to said differential current changes, each of the bases of said pair of transistors being coupled to said feedback means and each of the emitters of said pair of transistors being coupled to one of said first and second interconnect lines, said feedback means adjusting the base-to-emitter voltage potentials of each of said pair of transistors such that said peak-to-peak voltage of said intermediate differential signal is clamped to said magnitude less than said specific magnitude. 4. The apparatus as described in claim 3 wherein said peak-to-peak voltage of said output differential signal is greater than about 60 mV and said clamped magnitude of said peak-to-peak voltage of said intermediate differential signal is less than about 60 mV. 5. The apparatus as described in claim 3 wherein said clamped magnitude is approximately equal to 20 mV. 6. The apparatus as described in claim 3 wherein said peak-to-peak voltage of said output differential signal is compatible with emitter coupled logic (ECL) levels. 7. An apparatus for reducing transmission delays of a first voltage mode differential signal comprising: a transmitting means for converting said first voltage mode differential signal into a current mode differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said first voltage mode differential signal, said transmitting means coupling said current mode differential signal onto first and second interconnect lines; a receiving means for converting said current mode differential signal into a second voltage mode differential signal in response to differential current changes in said current mode differential signal, said receiving means including a first pair of transistors having each of their emitters coupled to one of said first and second interconnect lines, said first pair of transistors loading said first and second interconnect lines such that said peak-to-peak voltage of said current mode differential signal is driven towards a specific magnitude; said receiving means including a differential amplifier being coupled to the bases of said first pair of transistors, said differential amplifier including a second pair of emitter-coupled transistors having each of their bases coupled to said one of said first and second interconnect lines and their emitters coupled to a first current source, said differential amplifier clamping said peak-to-peak voltage of said current mode differential signal to a magnitude less than said specific magnitude. 8. The apparatus as described in claim 7 wherein said each of said emitters of said first pair of transistors is coupled to one of a pair of current sources, said pair of current sources biasing said first pair of transistors in their low resistance region. 9. The apparatus as described in claim 8 wherein said first current source and said pair of current sources are n-type metal oxide silicon devices each having their gates coupled to a reference voltage, and their sources coupled to a first working potential. 10. The apparatus as described in claim 9 wherein said first and second pairs of transistors are NPN bipolar transistors. 11. The apparatus as described in claim 10 wherein said receiving means further includes a first pair of matched resistive loads each coupled between one of the collectors of said first pair of transistors and a second working potential, said differential output signal being output by said collectors of said first pair of transistors. 12. The apparatus as described in claim 11 wherein said differential amplifier further includes a second pair of matched resistive loads, each of said second pair of matched resistive loads being coupled between one of said collectors of said second pair of emitter-coupled transistors and said second working potential. 13. The apparatus as described in claim 12 wherein said transmitting means comprises a third pair of emitter-coupled transistors having their emitters coupled to a second current source and each of their collectors coupled to said one of said first and second interconnect lines, and their bases coupled to said first voltage mode differential signal. 14. The apparatus as described in claim 13 wherein said peak-to peak voltage of said second voltage mode signal is greater than 60 mV and said peak-to-peak voltage of said current mode differential signal is less than 60 mV. 15. The apparatus as described in claim 13 wherein said peak-to peak voltage of said current mode differential signal is approximately equal to 20 mV. 16. The apparatus as described in Claim 13 wherein said peak-to-peak voltage of said second voltage mode differential signal is compatible with emitter coupled logic (ECL) levels. 17. An apparatus for reducing transmission delays of at least one differential signal comprising: means for transmitting said at least one differential signal within said integrated circuit, said at least one transmitting means converting said at least one differential signal into a corresponding intermediate differential signal having a peak-to-peak voltage less than the peak-to-peak voltage of said at least one differential signal, said transmitting means coupling said intermediate differential signal onto first and second interconnect lines; means for selecting said transmitting means responsive to a select signal; receiving means for converting said intermediate differential signal into an output differential signal having a peak-to-peak voltage greater than said peak-to-peak voltage of said intermediate differential signal, said receiving means loading said .first and second interconnect lines such that said peak-to-peak voltage of said intermediate differential signal is driven to a specific magnitude; said receiving means also including a feedback means for clamping said peak-to-peak voltage of said intermediate differential signal to a magnitude less than said specific magnitude, said feedback means being coupled to said first and second interconnect lines. 18. The apparatus as described in claim 17 wherein said feedback means comprises a differential amplifier responsive to differential current changes in said intermediate differential signal, said differential amplifier including a first pair of emitter-coupled transistors having their emitters coupled to a first current source and each of their collectors coupled to one of a first pair of matched resistive loads, said output differential signal being taken across said collectors of said first pair of emitter-coupled transistors. 19. The apparatus as described in claim 18 wherein said receiving means comprises a second pair of transistors being responsive to said differential current changes, each of the bases of said second pair of transistors being coupled to said feedback means and each of the emitters of said second pair of transistors being coupled to one of said first and second interconnect lines, said feedback means adjusting the base-to-emitter voltage potentials of each of said second pair of transistors such that said peak-to-peak voltage of said intermediate differential signal is clamped to said magnitude less than said specific magnitude. 20. The apparatus as described in claim 19 wherein said each of the emitters of said second pair of transistors is coupled to one of a pair of current sources, said pair of current sources biasing said second pair of transistors in their low resistance region. 21. The apparatus as described in claim 20 wherein said receiving means further includes a second pair of matched resistive loads each being coupled between one of said bases of said second pair of transistors and a first working potential. 22. The apparatus as described in claim 21 wherein said transmitting means includes a third pair of emitter-coupled transistors having their emitters coupled to said selecting means, each of their collectors coupled to said one of said first and second interconnect lines, and their bases coupled to said at least one differential signal, said select means determining whether a second current source is coupled to said emitters of said third pair of emitter-coupled transistors in response to said select signal. 23. The apparatus as described in claim 22 wherein said first, said second, and said pair of current sources are n-type metal oxide silicon devices each having their gates coupled to a reference voltage, and their sources coupled to a second working potential. 24. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said output differential signal is greater than 60 mV and said peak-to-peak voltage of said intermediate differential signal is less than 60 mV. 25. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said intermediate differential signal is approximately equal to 20 mV. 26. The apparatus as described in Claim 23 wherein said peak-to-peak voltage of said output differential signal is compatible with emitter coupled logic (ECL) levels.

Inventors: WONG BAN PAK, WONG, BAN, PAK
Applicants: MICROUNITY SYSTEMS ENG, MICROUNITY SYSTEMS ENGINEERING, INC.
Application year: 1994
Main classification: H03K19
IPC codes: H03K19