Charge pump circuit

Abstract: A charge pump circuit (1) including a number of pull-up stages (2) connected in parallel with one another between a reference potential line (3) and an output line (4). Each stage (2) includes a capacitor (5) having a first terminal connected to a charging and discharging node (7), and a second terminal connected to a pull-up node (6) for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node (7) is connected to the supply line (3) via a charging transistor (9) having a control terminal connected to a high-voltage bias node (11) formed by the adjacent stage in the opposite operating phase, for charging the capacitor (5) substantially up to the supply voltage.

Description: The present invention relates to a charge pump circuit. As is known, charge pump circuits provide for generating a voltage (known as boost voltage) greater than the supply voltage, for catering to the requirements of certain applications. For example, present nonvolatile flash memories at times present a particularly low supply voltage, as low as 3 V, whereas a higher gate voltage is required for reading the cells. For this purpose, charge pump circuits are based on the principle of alternating two phases, the first of which comprises charging a capacitor, and the second of which comprises pulling up one terminal of the capacitor and connecting the other terminal to an output via controlled switches, to achieve an output voltage greater than supply. US Patent US-A-5,191,232, filed by Silicon Storage Technology, relates to a voltage boost circuit (charge pump) for EEPROM memories, comprising a number of cascade-connected stages of the above type, each of which increases the voltage generated in the previous stage, so that the output voltage of the circuit, roughly speaking, equals the supply voltage multiplied by the number of stages. The stages are so timed that each at a given phase is followed by another at the opposite phase, which timing is achieved by means of a number of inverters, one for each stage of the charge pump, cascade-connected in a loop so that the output of the last inverter is connected to the input of the first. As stated, the above known charge pump provides for boosting the input voltage (supply) when a high input to output voltage ratio is required, but is unsuitable for applications requiring a lower ratio (e.g. an output voltage equal to twice the input voltage) but high power. In fact, for achieving a low boost ratio, a correspondingly small number of stages must be provided, only one of which is connected directly to the output line. In this case, a very high oscillation frequency, due to the propagation time of the timing pulse in the inverter loop, would be produced, and such as to prevent full charging of the capacitor. Such a situation would in fact result in conflicting requirements: on the one hand, high power capacitors are required for high power charge transfer; on the other, an increase in the capacitance of the capacitors results in a reduction in the charge of the capacitors at each cycle and hence in output power. Moreover, the efficiency of the known circuit is extremely poor in the presence of low supply voltages, e.g. 3 V. The capacitor of the known circuit, in fact, can only be charged to the input value less the threshold voltage of the diode interposed between the capacitor itself and the previous stage; and, similarly, fails to transfer the full charge, due to the voltage drop of the diode between itself and the next stage (or output). US-A-4,656,369 discloses a charge pump circuit according to the preamble of the attached claim 1 and includes a plurality of parallel connected charge pump stages for producing a negative bias voltage on an output line. Each stage comprises a capacitor element (13) connected to the control terminal of a diode-connected charging transistor (15) and to the control terminal of a switching element (16) of a subsequent stage, which switching element is interposed between the charging and discharging node (14) of the subsequent stage and the output. It is an object of the present invention to provide a charge pump circuit designed to overcome the drawbacks presented by known circuits, and which in particular provides for supplying high power, especially in the presence of a low input to output voltage ratio or low supply voltage. According to the present invention, there is provided a charge pump circuit as claimed in Claim 1. A number of preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figures 1-4 show four embodiments of the charge pump circuit according to the present invention; Figure 5 shows a graph of a number of signals in the Figure 1 circuit; Figures 6 and 7 respectively show the circuit arrangement and logic equivalent of a variation of a detail in the Figure 1-4 circuits. Number 1 in Figure 1 indicates a charge pump circuit comprising a number of stages 2 1 , 2 2 , 2 3 , ..., 2 n connected parallel with one another between a reference potential line (supply line 3 at potential V DD ) and an output (or boost) line 4. For the sake of simplicity, the stages and component parts of the stages in the following description are indicated using subscripts to show the location (from left to right) and distinguish between the stages when necessary, and without subscripts when no distinction is required. Stages 2 in fact are substantially identical with the exception of the last stage 2 n , as explained later on. Each stage 2 comprises a bootstrap capacitor 5 with terminals defining a first and second node 6 and 7; an output diode 8 interposed between second node 7 and output line 4; a charge transistor 9 interposed between supply line 3 and second node 7; an idle bias diode 10 interposed between supply line 3 and a node 11 formed by the gate terminal of charge transistor 9; and an inverter 12 interposed between nodes 6 of two adjacent stages 2, with the exception of the last stage 2 n on the right, the inverter of which is formed by the branch closing the timing loop, as described below. In detail, output diode 8 of each stage 2 comprises a native (i.e. low-threshold) N-channel MOS transistor with the drain and gate terminals short-circuited and connected to node 7 of its own stage 2, and the source terminal connected to output line 4; each transistor 9 comprises a native N-channel MOS transistor with the drain and gate terminals connected to supply line 3, and the source terminal connected to node 7 of its own stage 2; and each diode 10 comprises a native N-channel MOS transistor with the drain and gate terminals short-circuited and connected to supply line 3, and the source terminal connected to node 11 of its own stage 2. Node 11 of each stage 2 i is connected directly to node 7 i-1 of the previous stage 2 i-1 , and node 11 1 of the first stage 2 1 on the left is connected by line 13 to node 7 n of the last stage 2 n on the right to form a loop of stages. The input of inverter 12 i of each stage 2 i is connected to the output of inverter 12 i-1 of the previous stage; and the output of inverter 12 n-1 of the last but one stage 2 n-1 on the right (node 6 n-1 ) is connected to a first input of an AND circuit 15, the second input of which is supplied with an external enabling signal EN. The output of AND circuit 15 is connected to a first input of a NOR circuit 16, the second input of which is supplied with a synchronizing signal SYNC; and the output of NOR circuit 16 (supplying signal SS) is connected to node 6 1 of the first stage 2 1 on the left. In practice, NOR circuit 16 constitutes the inverter of stage 2 n , and together inverters 12 1 -12 n-1 and NOR circuit 16 (as well as AND circuit 15) form an oscillating loop 18 comprising an odd number of inversions. A capacitor 20 is connected between line 4 and ground, and acts as a level memory (flywheel element). The Figure 1 circuit operates as follows (refer also to the Figure 5 diagram showing the logic signal at the inputs of inverters 12 of the first four stages). In idle mode, with enabling signal EN and the SYNC signal low, signal SS is high and the circuit is in idle bias mode. In this condition, the input nodes 6 i of inverters 12 i of odd-position (and odd-subscript) stages 2 i , where i=2k-1 and k is a whole number, are high; and the input nodes 6 j of inverters 12 j of even stages 2 j , where j=2k , are low, as shown in Figure 5 in which V 2 , V 3 and V 4 respectively indicate the logic level of nodes 6 2 , 6 3 and 6 4 . Consequently, the even stages are biased to supply by turned-on diodes 10 (capacitors 5 charged to V DD -2V T , where V T is the voltage drop across diodes 10 and between the source and gate terminals of transistors 9), whereas the odd stages are not supplied. Upon the EN signal switching to high, the charge pump is turned on (instant t 0 in Figure 5); and, after a delay caused by the switching of NOR circuit 16, signal SS switches to low, so as to ground node 6 1 of the first stage 2 1 (instant t 1 ); and diode 10 1 and transistor 9 1 of first stage 2 1 are turned on, thus enabling capacitor 5 1 to be charged to V DD -2V T . After a delay caused by the output of inverter 12 1 switching to high (instant t 2 ), signal V 2 at node 6 2 switches to roughly V DD ; node 7 2 of the same stage 2 2 switches to roughly 2V DD -2V T , thus turning off diode 10 2 and transistor 9 2 and turning on diode 8 2 of second stage 2 2 ; and capacitor 5 2 is connected to output line 4 and, despite being only partly charged and not yet fully efficient, transfers the charge. At the same time, pull-up of node 7 2 of second stage 2 2 pulls up node 11 3 of third stage 2 3 to the same value 2V DD -2V T ; and, upon signal V 3 at the output of inverter 12 2 switching to low (with a certain delay with respect to switching of inverter 12 1 - instant t 3 ), capacitor 5 3 of third stage 2 3 begins charging. In this case, the capacitor is charged to the full supply voltage V DD value in that, as stated, the gate terminal of transistor 9 3 of third stage 2 3 (node 11 3 ) is at a higher potential than V DD , thus enabling node 7 3 to be connected to supply via charge transistor 9 3 which presents a negligible voltage drop between the drain and source terminals. Upon signal V 4 at the output of inverter 12 3 of third stage 2 3 switching to high (instant t 4 ), diode 10 4 of fourth stage 2 4 is turned off, and, as in stage 2 2 , capacitor 5 4 begins transferring the charge. Operation as described above is repeated for the following stages as the switch edge travels along inverters 12, with the even stages transferring the accumulated charge to line 4, and the odd stages charging fully, until the switching edge of the inverters 12 reaches the last stage 2 n (instant t 5 in Figure 5). When signal V n at the output of inverter 12 n-1 of the last but one stage switches to low, this switches AND circuit 15 which generates a low output signal; OR circuit 16 and signal SS switch to high (instant t 6 ); and the switch edge again travels along inverters 12. In this phase, as inverters 12 are switched, the odd stages 2 1 , 2 3 , ... switch to charge transfer mode, and the even stages to charge mode; and operation of pump 1 is practically regular, in that, with the exception of the first, the odd stages are fully charged. Nodes 7 3 , 7 5 , ... of the odd stages therefore switch successively to 2V DD and, taking into account the voltage drop V T of diodes 8 3 , 8 5 , ..., are capable of bringing line 4 up to 2V DD -V T . In this phase, the even stages are also charged fully. Upon this switch edge reaching the last but one stage 2 n-1 (instant t 7 ), signal V n at node 6 n switches to high, thus switching circuits 15 and 16; and a new switch edge begins traveling along inverters 12. In this phase, in which the odd stages 2 1 , 2 3 , ... are charged and the even stages 2 2 , 2 4 , ... transfer the accumulated charge, even the first node can be fully charged. Thanks to line 13, in fact, node 11 1 is at the potential 2V DD as node 7 n of the last charge transferring stage, so that, upon signal SS switching (instant t 8 ), transistor 9 1 is turned on and connects node 7 1 to supply line 3 at V DD . Operation as described above is repeated cyclically as long as enabling signal EN is high and the SYNC signal is low. If the SYNC signal switches to low, however, when the SS signal is low, upon the switch edge reaching the last stage, oscillation is interrupted until the SYNC signal again switches to low. Conversely, if SS is high, switching of the SYNC signal immediately switches SS to low, and oscillation (asynchronous with respect to the previously oscillations) is recommenced, and is interrupted upon the switch edge reaching the last stage and the pump is stopped. In both cases, therefore, the SYNC signal is valuable for temporarily stopping pump 1 - e.g. when address reading, in the event the circuit is used in a memory - without disabling the entire circuit. Charge pump 1 as described therefore provides for effectively boosting voltage even in case of a low input to output voltage ratio. Providing a large number of parallel stages, in fact, permits a parallel contribution by various stages at each charge transfer phase, as well as allows for allowing sufficient time for the oscillation to travel along inverters 12 and so ensures that, when the same inverter is switched again, it has safely reached the voltage level corresponding to the high or low state. As a result, the capacitors of each stage are also in the best possible condition, and are allowed enough time to be fully charged and to transfer the charge to output line 4. Moreover, biasing each stage by means of the previous one (and the first stage by the last via line 13) ensures the capacitors are charged, with no losses, up to the supply voltage, and also provides for accelerating the transient state to the steady state condition, thus enhancing the efficiency of the circuit. The pump according to the present invention also operates at high frequency. As the pump described is substantially a loop oscillator in which supply current is proportional to frequency, to the capacitance of the charge elements (capacitors) and to operating voltage (supply voltage V DD ), for a given current and, hence, efficiency, the high frequency of the pump provides for reducing the size of the capacitors and, despite featuring a large number of parallel stages, for greatly reducing the size of the pump as a whole. The efficiency of the Figure 1 circuit is further enhanced by the fact that, at each instant, there are always some stages transferring a charge to output line 4, with no ineffective half cycles in which the stages are charged and no charge is transferred, as would be the case if only one stage were connected to the output line. Figure 2 shows a further embodiment of the pump, indicated 25, which provides for achieving a higher input to output voltage ratio. In this case also, pump 25 comprises a number of stages 26 i connected in parallel with one another between supply line 3 and output line 4; and an oscillating loop 18 formed by a number of inverters 27 i and circuits 15, 16. (Here, too, unless required for operating description purposes, stages 26 are generally indicated without subscripts). A branch 29 is provided for biasing first stage 26 1 which extends between lines 3 and 4 and presents the same structure as part of stages 26, as described below. Each inverter 27 i defines an input node 28 i , and an output node 28 i+1 connected to the input of inverter 27 i+1 of the next stage. Each stage 26 i comprises a first capacitor 32 i having a first terminal connected to node 28 i , and the other terminal of which defines a node 34 i ; and a second capacitor 35 i having a first terminal connected to node 28 i+1 , and the other terminal of which defines a node 37. A first charge transfer diode 38 is connected between nodes 34 and 37; a second charge transfer diode 39 is connected between each node 37 and output line 4; a first idle bias diode 43 connects the anode of charge transfer diode 38 and node 34 to supply line 3; a second idle bias diode 44 connects the anode of charge transfer diode 39 and node 37 to supply line 3; and a transistor 45 1 presents its drain and source terminals connected respectively to supply line 3 and node 34 i , and its gate terminal connected to node 34 i-1 of the previous stage. Branch 29 comprises a capacitor 31 identical to capacitors 32; and a transistor 30 identical to transistors 45 of stages 26. More specifically, capacitor 31 presents a first terminal connected to a node 41 formed by the output of inverter 27 n of the last stage 26 n ; and a second terminal defining a node 40 and connected to the source terminal of transistor 30 which presents the gate terminal connected to node 34 n , and the drain terminal connected to line 3. Node 40 is connected by line 13 to the gate terminal of transistor 45 1 of first stage 26 1 ; and node 41 is connected to one input of AND circuit 15. Each diode 38, 39, 43 and 44 comprises a native N-channel MOS transistor with short-circuited drain and gate terminals; and each transistor 45 i and 30 comprises a native NMOS transistor. The Figure 2 circuit operates in the same way as the Figure 1 circuit, except that it provides for bringing the output line up to a voltage of 3V DD -2V T . In fact, in steady state mode, upon node 28 n of the last stage 26 n switching to low (0 V), capacitor 32 n begins charging, and its terminal 34 n switches to V DD together with the gate terminal of transistor 30; and, upon switching of the output of inverter 27 n , node 41 switches to high, thus enabling capacitor 35 n to transfer its charge to output line 4. In this phase, node 40 switches to 2V DD together with the gate terminal of transistor 45 1 , so that, as the switch edge advances and node 28 1 switches to low to commence charging capacitor 32 1 , this can be charged to the full supply voltage V DD ; and second capacitor 35 1 transfers its charge to output line 4. As the switch edge goes on along inverters 27, first capacitor 32 2 of the second stage switches to transfer its charge to second capacitor 35 2 which in turn switches to the charge phase; first capacitor 32 3 of the third stage switches to the charge phase up to V DD , and so on. In the next half cycle, following propagation of the switch edge along oscillating loop 18, first capacitors 32 1 , 32 3 , etc., which were formerly charging, transfer the charge to respective second capacitors 35 1 , 35 3 , etc. As said first capacitors were charged to the full supply voltage V DD , when nodes 28 1 , 28 3 , etc. switch to high, nodes 34 1 , 34 3 , ... present voltage 2V DD , and respective second capacitors 35 1 , 35 3 , ... can be charged to 2V DD -V T , where V T is the voltage drop of diodes 38. In the same half cycle, first capacitors 32 2 , 32 4 , etc. switch to the charge phase, and second capacitors 35 2 , 35 4 , etc. switch to transfer the charge to output 4. More specifically, in this phase, second capacitors 35 2 , 35 4 , etc., which were formerly charged to 2V DD -V T , are capable of bringing output line 4 up to 3V DD -2V T , taking into account the voltage drop of diodes 39. Like the Figure 1 circuit, therefore, stages 26 switch one after the other; signal EN provides for enabling and disabling the circuit, and the SYNC signal for temporarily interrupting operation; and each stage is biased, in steady state mode, by the previous stage to ensure full charging of capacitors 32 to V DD with minimum losses. Like circuit 25 in Figure 2, circuit 50 in Figure 3 comprises a number of parallel stages 51, each for supplying an output voltage of 3V DD -2V T . Stages 51 are similar to stages 2 in Figure 1, except that, as opposed to each stage 51 being connected to node 34 of the previous stage, the gate terminals of transistors 45 are all connected to one node 53, and each stage 51 comprises two inverters 48, 49. More specifically, for each stage, the output of inverter 48 defining node 33 is connected to the input of inverter 49, the output of which defines node 36; and first capacitors 32 are connected between nodes 33 and 34, and second capacitors 35 between nodes 36 and 37. In all but the first stage on the left, the input of first inverter 48 is connected to node 36 of the previous stage. In the first stage on the left, the input of inverter 48 (supplied with signal SS) defines a node 52 connected to the output of NOR circuit 16. Node 36 of the last stage on the right is connected to one input of NAND circuit 15. Common bias node 53 is formed by one terminal of a capacitor 54, the other terminal of which is connected to input 52 of inverter 48 of first stage 51. Node 53 is also connected to supply line 3 via a diode 55. Circuit 50 in Figure 3 operates in the same way as circuit 30 in Figure 2, except that, as the switch edge advances, first capacitors 32 all switch to the same condition - charge or charge transfer - as do second capacitors 35, so that all the stages operate in time with one another. Consequently, in the Figure 3 circuit, the propagation delay of each stage equals the total delay generated by inverters 48 and 49. What is more, in this case, capacitor 54 is charged in one half cycle to voltage V DD -V T , and, in the opposite half cycle, brings node 53 up to voltage 2V DD -V T and appropriately biases stages 51 as soon as they switch to the charge phase. Circuit 60 in Figure 4 is similar to that of Figure 2, except that, in steady state mode, each stage 61 is not biased by the previous stage, but presents its own biasing means similar to bias components 53-55 of stages 51 in Figure 3. Consequently, in addition to components 32, 35, 38, 39, 43-45, 48, 49, each stage 61 in Figure 4 also comprises a diode 62 interposed between supply line 3 and the gate terminal of transistor 45 (node 63); and a third capacitor 64 having one terminal connected to node 63, and the other terminal (node 65) connected to the input of inverter 48 and, for all but the first stage on the left, to the output of an inverter 66, the input of which is connected to output 36 of inverter 49 of the previous stage. Input node 65 of inverter 48 of the first stage is connected to the output of NOR circuit 16, the input of which is connected to AND circuit 15 as in circuits 1, 25 and 50 in Figures 1-3. Circuit 60 in Figure 4 operates in the same way as described for circuits 25 and 50. In the first phase, capacitor 64 is charged to voltage V DD -V T , where V T is the voltage drop across diode 62; and, in the meantime, capacitor 32 transfers its charge to capacitor 35 which is charged to 2V DD -V T . In the next phase, node 63 is brought up to voltage 2V DD -V T , so that capacitor 32 is charged fully to supply voltage V DD via transistor 45; and capacitor 35 transfers its charge to output line 4 to bring it up to voltage 3V DD -2V T . Figures 6 and 7 show a different embodiment of inverters 12, 27, 48, 49 and 66 in the Figure 1-4 circuits, which allows consumption of the circuits to be reduced by reducing the operating frequency. As shown in Figure 6, each inverter is formed by a pair of opposite-channel MOS transistors, one of which is divided into two unbalanced parts, of which one is switchable by an external signal, for controlling the current through the transistor and, hence, the switching time of the inverter. More specifically, each inverter (e.g. inverter 12 i in Figure 1) comprises a P-channel transistor 70 and an N-channel transistor 71, the gate terminals of which are connected together and to the input node 6 i of inverter 12 i . Transistor 70 presents the source terminal connected to supply V DD , and the drain terminal (node 6 i+1 ) connected to the drain terminal of transistor 71, the source terminal of which is grounded. The gate and drain terminals of transistor 71 (of minimum size) are connected respectively to the gate and drain terminals of an N-channel transistor 72; and the source terminal of transistor 72, which has a much larger width than transistor 71 to enable it to conduct far more current, is grounded via a switch 74. Switch 74 comprises an N-channel MOS transistor, is the same size as transistor 72, and is supplied at the gate terminal with a control signal SB, e.g. relative to the operating mode of the device featuring the charge pump circuit according to the present invention. Figure 7 shows the logic equivalent of one of the Figure 6 inverters, which comprises a two-input NAND circuit 76 with one input connected directly to input node 6 i , and the other connected to the output of a two-input OR circuit 77, one input of which is connected directly to input node 6 i , and the other input of which is supplied with signal SB. When signal SB of the Figure 6-7 inverters is high, transistors 71 and 72 operate in parallel with each other, so that, when node 6 i switches to high, they are turned on and provide jointly for discharging node 6 i+1 . Conversely, when signal SB is low, transistor 72 is turned off, and transistor 71 alone provides for discharging the current from node 6 i+1 to ground. Since transistor 71 is much smaller than transistor 72, it conducts much less current and therefore takes longer to discharge node 6 i+1 , so that inverter 12 takes longer to switch alongside a reduction in consumption and operating frequency of the charge pump circuit. Clearly, changes may be made to the circuits described and illustrated herein without, however, departing from the scope of the present invention. In particular, the number of stages may vary, providing the oscillating cycle is long enough to switch the inverters, charge and discharge the capacitors, and so ensure correct operation of the circuit; each stage may provide for a different input to output voltage ratio as required; provision may be made for modifying operating frequency, as described above, or for modifying the number of active stages in predetermined operating phases of the device featuring the charge pump; and, finally, bipolar switch elements may also be employed.

Claims: A charge pump circuit (1; 25; 50; 60) comprising a number of stages (2; 26; 51; 61) connected in parallel with one another between a reference potential line (3) and an output line (4), each stage comprising a first capacitor element (5; 32) having a first terminal connected to a charging and discharging node (7; 34) and a second terminal connected to a pull-up node (6; 28; 33) for switching between a first charging operating phase wherein the first capacitor element is charged and a second charge transfer operating phase, wherein the first capacitor element is discharged to the output line, and wherein the one of two adjacent stages is in the charging operating phase and the other of said two adjacent stages is in the charge transfer operating phase said charging and discharging node (7; 34) being connected to said reference potential line (3) via a first switching element (9; 45) comprising a charging transistor (9; 45) having a first and second terminal connected respectively to said reference potential line and said charging and discharging node, and a control terminal, characterized in that said stages (2; 26; 51; 61) are pull-up stages, for charging said first capacitor element (5; 32) to substantially the potential (VDD) of said reference potential line and in that said control terminal of said charging transistor (9; 45) is not directly connected to said second terminal of the same charging transistor (9; 45) and is directly connected to a high-voltage bias node formed by the charging and discharging node (7i-1; 34i-1) of an adjacent stage (2i-1; 26i-1) in the charging operating phase. A circuit as claimed in Claim 1, characterized in that each said pull-up stage (2 i ; 26 i ) presents the control terminal of its charging transistor (9 i ; 45 i ) connected to the charging and discharging node (11 i-1 ; 34 i-1 ) of a first adjacent stage (2 i-1 ; 26 i-1 ), and its charging and discharging node (11 i ; 34 i ) connected to the control terminal of the charging transistor (9 i+1 ; 45 i+1 ) of a second adjacent pull-up stage (2 i+1 ; 26 i+1 ) differing from the first adjacent pull-up stage. A circuit as claimed in Claim 1, characterized in that it comprises a common bias branch (53-55) presenting a first capacitive element (54) having a first terminal (53) connected to said reference potential line (3) via a first switching element (55), and a second terminal connected to its own pull-up node (52), said first terminal of said first capacitive element defining a common bias node (53); and by the fact that the control terminals of said charging transistors (45) of all the pull-up stages (51) are connected to said common bias node (53). A circuit as claimed in Claim 1, characterized in that each pull-up stage (61) comprises a bias branch (62-65) including a second capacitive element (64) having a first terminal (63) connected to said reference potential line (3) via a second switching element (62), and a second terminal connected to its pull-up node (65); and by the fact that the control terminal of each charging transistor (45) is connected to said first terminal (63) of said second capacitive element in the same stage. A circuit as claimed in any one of Claims 1-4, characterized in that it comprises an idle bias element (10; 43) interposed between said reference potential line (3) and said control terminal of said charging transistor (9; 45). A circuit as claimed in any one of the foregoing Claims, characterized in that said pull-up nodes (6; 28; 33, 36; 65) are connected to respective inputs of a number of cascade-connected inverting elements (12; 27; 48, 49; 66). A circuit as claimed in Claim 6, characterized in that said inverting elements (12; 27; 48, 49; 66) are closed-loop connected and perform an odd number of invertions, and form an oscillating loop (18). A circuit as claimed in Claim 7, characterized in that it comprises enabling and disabling means (15; 16) along said oscillating loop (18). A circuit as claimed in Claim 7 or 8, characterized in that said inverting elements (12) comprise control means (74) for varying the switching delay of the inverting elements. A circuit as claimed in Claim 9, wherein each said inverting element (12) comprises a pair of transistors (70, 71) of opposite type; at least one transistor (71) in said pair having a control terminal and a current supply terminal respectively in common with a control terminal and current supply terminal of an auxiliary transistor (72) controlled by a switch signal (SB). A circuit as claimed in any one of the foregoing Claims, characterized in that said charging and discharging node (7) is connected to said output line (4) via a single third switch element (8). A circuit as claimed in any one of the foregoing Claims, characterized in that each said pull-up stage (26; 31; 51; 61) comprises second charge storing means (35) having a first terminal (37) connected to said charging and discharging node (34) via a second switching element (38), and a second terminal connected to a respective pull-up node (28; 36); said second charge storing means operating in push-pull manner with respect to said first charge storing means (32) in the same pull-up stage. A circuit as claimed in Claim 12, characterized in that said first terminal (37) of said second charge storing means (35) is connected to said output line (4) via a fourth switch element (39). A circuit as claimed in Claim 12 or 13, characterized in that said first terminal (37) of said second charge storing means (35) is connected to said reference potential line (3) via a respective bias element (44).

Inventors: MACCARRONE MARCO, PADOAN SILVIA, PASCUCCI LUIGI, MACCARRONE, MARCO, PADOAN, SILVIA, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G11C5
IPC codes: G11C16, H02M3, G11C5, G11C17