Method for manufacturing a high-frequency lateral PNP transistor

Abstract: A high-frequency lateral PNP transistor presenting a base region (63') laterally delimited by P type emitter (68) and collector (69) regions, and at the top by a surface portion (67) of the N type semiconductor body (63) housing the active area of the transistor. The surface portion (67) delimiting the base region (63') presents no formations of insulating material grown across the surface, so that the width (W B ) of the base region (63') is reduced and ensures optimum dynamic characteristics of the transistor. The base contact (80, 82) may be located directly over the surface portion facing the base region (63'), to reduce the extrinsic base resistance and overall size of the device, or it may be located remotely and connected to the base region by a buried layer (62) and sinker region (88) to further reduce the base width.

Description: The present invention relates to a process for manufacturing a high-frequency lateral PNP transistor. As is known, NPN transistors are the components most commonly used in both analog and digital bipolar integrated circuits, and, for them to also operate at high switching frequency, sophisticated fabrication techniques have been devised, such as: dielectric or trench isolation; using one or more polycrystalline silicon (polysilicon) layers; self-alignment by means of silicon oxide spacers or composite materials; rapid thermal processes (RTP); and using silicides and/or polycides (i.e. double layers formed of a layer of polysilicon and a layer of silicide). A rundown of the problems involved in fabricating high-frequency NPN transistors is to be found in the article entitled: "Bipolar Device Design for High Density, High Performance Applications", by P.C. Hunt, presented at IEDM 89, 1989 IEEE, p. 791-794. An NPN transistor structure developed by the present Applicant is shown in Figure 1 and described below. Figure 1 shows a cross section of a wafer of semiconductor material 1 including a P - type substrate 2; an N + type buried layer 3; and an N - type epitaxial layer 4. A trench isolation region 5 peripherally defines the area (active area) in which the NPN transistor is formed, and comprises a nondoped polysilicon region 6 extending vertically from surface 35 of wafer 1, through epitaxial layer 4 and buried layer 3 to substrate 2; a nitride layer 7 surrounding polysilicon region 6 on all sides (except that facing surface 35 of wafer 1); and a thermal oxide layer 8 surrounding nitride layer 7. Field oxide regions 10, 11 extend across surface 35, the first over isolation region 5, and the second in an intermediate portion of the active area, so as to define two surface regions 12, 13 with no oxide covering. An N + type sinker region 14 extends through epitaxial layer 4 from window 12 of surface 35 to buried layer 3; an N + doped polysilicon layer 15 is formed over window 12, in electrical contact with sinker region 14; and a metal collector contact 16 is formed over layer 15. In epitaxial layer 4, two P + type regions 18, 19 are formed facing window 13 and connected to each other by a P type base region 20; two P + doped polysilicon layers 22, 23 are formed over regions 18, 19, layer 23 of which also extends over field oxide region 11 presenting base contact 24; and oxide regions 25 cover regions 22, 23, 15 and field oxide regions 10, 11, with the exception of the areas in which collector and base contacts 16 and 24 are formed. The facing lateral edges of regions 22, 23 and of overlying oxide regions 25 are covered with two symmetrical L-shaped thermal oxide portions 26, the horizontal arms of which cover part of surface 35 of wafer 1, and which are in turn covered by two L-shaped silicon nitride regions 27. A substantially U-shaped polysilicon layer 28, doped to present N + type conductivity, fills the gap between the horizontal arms of the L's contacting surface 35 of wafer 1, laterally covers nitride regions 27, and presents two horizontal end portions partially covering oxide regions 25. Polysilicon layer 28, which forms an emitter region, generates a thin N + type layer 29 inside base region 20 which has a width equal to the distance between L-shaped regions 26. A metal region 30 over polysilicon layer 28 forms the emitter contact of the transistor. The above structure provides for cutoff frequencies of over 20 GHz, propagation times of about 40 ps, and power-speed products of about 40 fJ. Though, as stated, NPN transistors are the ones most commonly used in integrated circuits, situations exist in which PNP transistors are also desirable, e.g. for integrating complex logic or analog functions. Figure 2 shows one lateral PNP transistor structure proposed in an article by Yamaguchi et al. published in March 1994 in IEEE Transactions on Electron Devices, vol. 41, n. 3, p. 321-329. This known solution comprises a P - type substrate 40; an N + type buried layer 41; an N type epitaxial layer 42; P + type emitter and collector regions 43, 44 in epitaxial layer 42; and an N + type sinker region 45 extending from the surface of the device to buried layer 41. A first oxide spacer region 48 separates emitter region 43 from collector region 44; and a second oxide spacer region 49 separates collector region 44 from sinker region 45; spacer regions 48, 49 are grown in the form of thermal oxide across the surface of the wafer. Polysilicon regions 50-52, doped similarly to regions 43-45, are deposited over the surface of the wafer at regions 43-45; and the emitter, collector and base contacts 53, 54, 55 are formed over regions 50-52. In the Figure 2 transistor, current flows parallel to the surface; the P + doped polysilicon regions 50 and 51 provide for contacting emitter region 43 and collector region 44; and the base region is formed by the portion 42' of epitaxial layer 42 extending between regions 43 and 44. Portion 42' is accessed by the low-resistivity path including polysilicon region 52, sinker region 45, and buried layer 41. The above known structure, however, fails to provide for good static characteristics (in particular, it presents low h fe values), and dynamic performance is also unsatisfactory. In fact, the base width - indicated W B in Figure 2 and which determines the gain of the transistor - cannot be reduced to less than 2-2.5 µm on account of the alignment tolerances of the various layers, and the limits posed by the growth of spacer region 48 and by the presence of "bird beaks" growing beneath the oxidation mask, at the edges of the oxide region. The impossibility of accurately controlling the size of the "bird beaks" is also a major source of imprecision in the sizing of the base width. Patent Abstracts of Japan, vol. 12, no 281 (E-641), August 2, 1988, & JP-A-63 058 870 describes a lateral PNP transistor having first contact regions 14 of polysilicon contacting respective semiconductor regions 32 of P type conductivity in the substrate. A second contact region 21 of polysilicon is formed between the first contact regions 14, separated therefrom by symmetrical L-shaped insulating material spacers and contacting a respective semiconductor region 31 of N type conductivity in the substrate. The first contact regions 14 are formed by a very expensive and not controllable process, including etching below the first contact regions 14 and filling the corresponding space with a polysilicon layer to contact the first contact regions 14. EP-A-0 526 374 describes a lateral bipolar transistor having a remote base contact connected to the base region through a low-resistive path. IBM Technical Disclosure Bulletin, vol. 25, no. 8, January 1983, pp. 4171-4173 describes a further lateral bipolar transistor with remote base contact. It is an object of the present invention to provide a process for manufacturing a PNP transistor of superior performance as compared with known solutions, and which, preferably, may be formed using the same technology as the NPN component in Figure 1, with only minor alterations to the fabrication process, for permitting PNP and NPN transistors to be fabricated simultaneously in the same integrated device. According to the present invention, there is provided a process for manufacturing a high-frequency lateral PNP transistor as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a cross section of a silicon wafer incorporating a known NPN transistor; Figure 2 shows a cross section of a silicon wafer incorporating a known PNP transistor; Figure 3 shows a cross section of a silicon wafer incorporating a PNP transistor made in accordance with the present invention. Figure 4 shows a variation of the Figure 3 transistor that does not belong to the invention. Number 60 in Figure 3 indicates a silicon wafer comprising a P - type substrate 61, an N + type buried layer 62 and an N - type epitaxial layer 63, similar to layers 2-4 in Figure 1. A trench isolation region 64, identical to region 5 in Figure 1 and therefore not described further, isolates the region in which the PNP transistor is formed from the adjacent regions in which other components are integrated. A field oxide region 66 extends across the surface 67 of the wafer, over isolation region 64, so as to peripherally define the active area of the PNP transistor. In epitaxial layer 63, two spaced P + type emitter and collector regions 68, 69 are formed facing surface 67; and, over emitter and collector regions 68, 69, there are formed two P + doped polysilicon contact regions 70, 71 presenting a portion directly contacting surface 67 (and hence regions 68, 69), and a portion extending over field oxide region 66 where respective emitter and collector contacts 74 and 75 are formed. An oxide layer 76 covers regions 70, 71 and field oxide layers 66, with the exception of the areas in which emitter and collector contacts 74 and 75 are formed. The facing lateral edges of regions 70, 71 and of overlying oxide layer 76 are covered with two symmetrical L-shaped portions of thermal oxide 77, the horizontal side of which covers part of surface 67 of wafer 60, and which are in turn covered with two symmetrical L-shaped silicon nitride regions 78. A substantially U-shaped polysilicon layer 80, doped to present N + type conductivity, fills the gap between the horizontal arms of the L's contacting surface 67 of wafer 60, laterally covers nitride regions 78, and presents two horizontal end portions partially covering oxide layer 76. Polysilicon layer 80, which forms a base contact region, generates a thin N + type layer 81 inside epitaxial layer 63. A metal region 82 over polysilicon layer 80 forms the base contact of the transistor. In the Figure 3 transistor, the base region is formed by portion 63' of the epitaxial layer, the width (base width W B ) of which is defined by the distance between regions 68 and 69, and therefore substantially (with the exception of the lateral diffusion of regions 68, 69) by the distance between the facing edges of polysilicon regions 70 and 71. This distance is determined by a plasma etching photolithographic step, which technique provides for achieving smaller minimum dimensions and, though depending on the equipment used, far greater precision as compared with the thermal oxidation (planox) process used for growing oxide region 48 of the Figure 2 transistor. More specifically, the technique used by the Applicant provides for achieving a base width W B of about 0.8 µm. In the Figure 3 transistor, the polysilicon layer 80 between regions 70 and 71 provides for minimizing the extrinsic base resistance r bb , of the transistor, as well as for dispensing with the sinker region normally provided between the base contact and the epitaxial layer (region 14 in Figure 1 and 45 in Figure 2), thus greatly reducing the size of the transistor and hence the parasitic capacitances associated with it. As in Figure 1, the Figure 3 transistor also provides for improving gain by permitting the use of a less heavily doped epitaxial layer 63 as compared with the known Figure 2 solution. As such, the Figure 3 transistor presents superior dynamic and static characteristics ensuring reliable operation even at high frequency. As can be seen, the Figure 3 transistor presents the same structure as in Figure 1, and may therefore be formed using the same technology and simultaneously with the Figure 1 transistor. More specifically, regions 70 and 71 may be formed simultaneously with regions 22, 23 in Figure 1, and, like regions 22, 23 for regions 18, 19, constitute diffusion sources for emitter and collector regions 68 and 69, which are thus formed by dope diffusion from regions 70 and 71, with no need for specific implant or diffusion steps. Similarly, spacer regions 77, 78 and N + doped polysilicon region 80 may be formed simultaneously with corresponding spacer regions 26, 27 and polysilicon region 28 in Figure 1, by appropriately modifying the mask. A special mask must be provided, however, to prevent the base implant for forming region 20 in Figure 1 from penetrating the base region of the Figure 3 transistor. In the Figure 3 transistor, the minimum base width is determined by the need to prevent the two horizontal arms of the L's from touching during the successive steps for defining spacer regions 77 and 78; which condition therefore imposes a minimum distance between polysilicon emitter and collector regions 70, 71, and hence a minimum base width W B . Figure 4 shows a structure that does not form part of the invention and wherein the base contact is no longer formed between the emitter and collector regions, and the base region is accessed via a buried layer and a sinker region. In the Figure 4 transistor, the distance between polysilicon emitter and collector regions 70 and 71 is so selected that the two horizontal arms of the two L-shaped spacer regions 77 in Figure 3 are no more separated, and are joined to form a single U-shaped oxide spacer region 85. Similarly, nitride regions 78 are joined to form a single U-shaped nitride region 86; and a field oxide region 87 is formed across the surface of the wafer to divide the active area into two parts: one integrating emitter and collector regions 68, 69 and the base region (portion 63" of the epitaxial layer), and a part in which is formed an N + type sinker region 88 extending from surface 67 to buried layer 62. On surface 67, at sinker region 88, an N + doped polysilicon layer 89 is formed with a base contact 90 on top. Unlike the Figure 3 transistor, the N + doped silicon layer for forming region 89 of the Figure 4 transistor is easily removable from surface 67 at base region 63". In the transistor of Figure 3, in fact, region 80 cannot be removed, due to the risk of over-etching down to the epitaxial layer and so damaging the base region; whereas, in the example in Figure 4, the N + polysilicon layer may safely be removed by virtue of epitaxial layer 63 at base region 63" being protected by oxide and nitride regions 85, 86. In the Figure 4 example, metal line 74 forming the emitter contact is extended over base region 63" to prevent the formation of inverted surface layers between the emitter and collector. Except for a different layout and special mask design, the Figure 4 example involves no changes to the fabrication process of the Figure 1 NPN transistor. The advantages of the transistor made in accordance with the present invention are as follows. In particular, eliminating the field oxide layer across the surface over the base region greatly reduces the base width and hence increases the gain of the transistor; and reducing the size and defectiveness of the transistor provides for improved dynamic performance, as well as for permitting use of the transistor in high-frequency applications. Clearly, changes may be made to the process for manufacturing as described and illustrated herein without, however, departing from the scope of the present invention as defined by the appended claims.

Claims: A process for manufacturing a high-frequency lateral PNP transistor, characterized by the steps of: forming insulating regions (66) across a surface (67) of a semiconductor body (63) of N-type conductivity, said insulating regions laterally bounding an active area of the transistor, said active area including a first, a second and a third portions of said surface (67), said second surface portion being spaced from said first surface portion and delimiting therewith said third surface portion and said third surface portion having a base region (63') of the transistor formed therein; depositing a layer of conductive material on said insulating regions (66) and said first, second and third surface portions; shaping said layer of conductive material to form a single layer emitter contact region (70) and a single layer collector contact region (71) of conductive material, said emitter contact region (70) having a first emitter contact portion on said first surface portion and a second emitter contact portion on one of said insulating regions (66) and said collector contact region (71) having a first collector contact portion on said second surface portion and a second collector contact portion on another one of said insulating regions (66); forming an emitter region (68) of P-type conductivity in said first surface portion and a collector region (69) of P-type conductivity in said second surface portion by diffusion from said emitter contact region (70) and said collector contact region (71), respectively; forming an emitter metal contact (74) in direct electrical contact with said second emitter contact portion of said emitter contact region (70); forming a collector metal contact (75) in direct electrical contact with said second collector contact portion of said collector contact region (71); forming two L-shaped spacer regions (77, 78) of insulating material symmetrically with respect to each other and having each a first portion in direct contact with said third surface portion, a second portion of one of the L-shaped spacer regions directly contacting said first emitter contact portion (70) and a second portion of the other of the L-shaped spacer regions directly contacting said first collector contact portion (71) and forming a base contact region (80) extending at least partially between said spacer regions of insulating material (77, 78), and in direct electrical contact with said base region (63') via said third surface portion. A process according to claim 1, characterized in that said emitter (70) and collector (71) contact regions are made of semiconductor material. A process according to any one of claims 1-2, characterized in that said step of forming a base contact region (80) comprises forming a substantially U-shaped base contact region of semiconductor material (80) having its base over and directly contacting said third surface portion, and with its arms adjacent to said spacer regions of insulating material (77, 78); the process being further characterised by the step of forming a metal region (82) on said base contact region of semiconductor material (80). A process according to any one of claims 1-3, characterized by the step of forming trench isolation formations (64) surrounding said active area in said semiconductor body (63).

Inventors: FALLICO GIUSEPPE, ZAMBRANO RAFFAELE, FALLICO, GIUSEPPE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLAMICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1994
Main classification: H01L21
IPC codes: H01L29