Sensor signal processing unit

Abstract: A peak hold circuit 11 holds a peak value of an output signal from a rotating angle sensor 6. A bottom hold circuit 12 holds a bottom value of the output signal from the rotating angle sensor 6. A threshold value is set from the peak value by the peak hold circuit 11 and the bottom value by the bottom hold circuit 12 by resistors 24 to 27, analog switches 28 and 29 and a NOT circuit 31. A comparator 10 compares the output signal of the rotating angle sensor 6 with the set value thus set, and outputs a binary signal (digitized signal) in accordance with the comparison result.

Description: The present invention relates to a sensor signal processing unit according to the preamble of claim 1. A sensor signal processing unit corresponding to the preamble of claim 1 is, e.g., known in the art front JP-A-61 091 770, JP-A-04 069 986 and US-A-4 665 318. For example, the sensor signal processing unit disclosed in JP-A-61 091 770 comprises a peak hold means for holding a peak value of an output signal of a sensor and a bottom hold means for holding a bottom value of the output signal of the sensor; furtheron, there is provided a threshold value setting circuit for setting a threshold value from the respective peak value and the respective bottom value. The respective output signal of the sensor is compared with the respective threshold value set by the setting circuit so as to output a binary signal in accordance with the comparison result. The processing unit of JP-A-61 091 770 is provided for a sensor which, basically, is delivering a signal in the form of square-wave, i.e. a bi-level or binary signal. If the respective sensor, however, delivers an output signal which is rather a continuously varying signal, such as a sine wave or a triangular wave, the known circuit will provide an output signal the binary information of which most probably will not correspond to the binary information of the sensor signal. For example, the known signal processing unit will not be able to produce a correct binary signal from a sensor signal having the waveform as shown under "IN" in Fig.2 of the present invention. The same disadvantage holds true with the signal processing units known US-A-4 665 318. The signal processing unit known from JP-A-04 069 986 is provided for the detection of the revolution of a rotary member by using a magnetoresistance element (MRE) (for example a ferromagnetic thin film resistor). When a gear-like rotary member rotates, the direction of a magnetic flux passing through the MRE changes, so that the output of the MRE also changes. The revolution of the rotary member is detected by digitizing the output change and effecting an appropriate signal processing. In order to convert the wave-like output from the MRE to a digital output, or in other words, to digitize the output, the reference described above employs the following method to determine a threshold value. Namely, the method sets in advance the threshold values (an upper limit value S1 and a lower threshold value S2) of a binary pulse-forming comparator as digitization means, and always corrects the output of the MRE in such a manner that the output of the MRE crosses the threshold value, that is, in such a manner that digitization and detection can be carried out even when the output of the MRE changes. To correct the output, a comparator for setting the upper limit and another comparator for setting the lower limit are provided, and when the output of the MRE exceeds the upper or lower limit value, a count value of an up/down counter is counted down or up using an oscillator to change the count value. This count value is used as an offset input, and offset adjustment is carried out so that the output of the MRE is between the upper limit value and the lower limit value. However, the output of the MRE includes an offset voltage and changes with the passage of time. Therefore, output correction must be always carried out so that the output of the MRE is within the range of the set values as described above. In other words, the output correction circuit must be always kept operating. This means that the oscillator of the output correction circuit is always operating and an oscillation spike noise always occurs. If this spike noise occurs at the same timing as the switching operation of the binary pulse forming comparator for digitizing the output of the MRE, the timing of switching deviates somewhat, and this deviation results in an error in angle accuracy. This term "angle accuracy" means the level of reproducibility which represents at which level of the output waveform of the MRE sensor the digitization output is switched from 1 to 0 and vice versa. Accordingly, if the spike noise occurs, a very small deviation of the edge occurs when the binary pulse-forming comparator effects its comparison operation, and this deviation results in an error in angle accuracy. In the case of a crank angle/cam angle sensor used for controlling an engine of a vehicle, for example, absolute angle accuracy of ±0.1° and repeatability of 0.02° are necessary. Accordingly, external noises such as switching noise must also be cut off as much as possible. It is the object of the present invention to improve a processing unit according to the preamble of claim 1 in such a way that even continuously varying output signals of a sensor can be correctly processed. This object, according to the present invention, is solved by the advantageous measures indicated in the characterizing part of claim 1. By this advantageous circuit structure it is possible to correctly process even such sensor signals which have a continuously varying waveform. Further advantageous developments of the present invention are the subject-matter of the dependent claims. The subject-matter of subclaim 2, i.e. the circuit structure of a peak hold means or a bottom hold means, is basically known from JP-A-63 213 199. Furtheron, WO-A-8 400 452 discloses a circuit which is used to transform an analog input signal into a binary signal and which comprises a peak hold means and a bottom hold means similar to that disclosed in JP-A-63 213 199. In the following, the present invention will be described in more detail by way of several embodiments thereof with reference to the drawings, in which: Fig. 1 is a circuit diagram of a sensor signal processing unit according to an embodiment of the present invention; Fig. 2 is a timechart showing various waveforms; Fig. 3 is also a timechart showing various waveforms; Fig. 4 is a structural view of a peak hold circuit; Fig. 5 is a structural view of a bottom hold circuit; Fig. 6 is a structural view of a peak hold circuit for comparison; Fig. 7 is a structural view of a bottom hold circuit for comparison; Fig. 8 is a structural view of a peak hold circuit of an application example; Fig. 9 is a structural view of a bottom hold circuit of an application example; Fig. 10 is a timechart showing various waveforms; Fig. 11 is a structural view of a circuit for error signal judgement of an application example; Fig. 12 is a timechart showing various waveforms; Fig. 13 is a circuit diagram showing a part of a single processing circuit of an angular sensor; Fig. 14 is a block diagram showing an example of a digitizing circuit; Fig. 15(A) is a diagram showing input/output of a comparator; and Fig. 15(B) is a diagram showing an input/output timechart of the comparator. Fig. 1 is a circuit diagram of a sensor signal processing unit according to an embodiment of the present invention. This sensor signal processing unit is an apparatus for detecting a rotation position of an engine. As depicted in Fig. 1, a disc-like rotary member 2 is fixedly fitted to a shaft 1 which rotates with the revolution of the engine at a rotating speed of 1/2. The rotary member 2 comprises a magnet holding portion 3 made of a non-magnetic material (e.g., austenite type stainless steel) and a ferrite magnet 4 having an annular shape and fixed around the magnet holding member 3. A magnetization plane 5, wherein magnetic poles having different polarities are alternately and equidistantly magnetized, is disposed on an outer peripheral surface of the ferrite magnet 4. A reference position 5a at which magnetization is removed and which has a wide pitch is disposed at a part of the magnetization plane 5. A rotating angle sensor 6 includes a pair of MREs (magnetoresistance elements) 7A and 7B so disposed on the magnetization plane 5 of the rotary member 2 as to oppose each other. A power supply is connected in series with these MREs 7A, 7B. An amplifier 9 is connected to the junction 8 between the MREs 7A and 7B. The resistance value of each MREs 7A, 7B changes in accordance with the magnetic field intensity in the circumferential direction with the rotation of the rotary member 2. As a result, the voltage at the junction 8 between the MREs 7A and 7B changes, and a voltage signal is output from the rotating angle sensor 6. The signal waveform at this junction 8 is represented by V8 in Fig. 2, and the signal waveform at the output portion of the amplifier 9 is represented by IN in Figs. 2 and 3. The output terminal of the amplifier 9 is connected to an inverting input terminal of a comparator 10. The output terminal of the amplifier 9 is further connected to a peak hold circuit 11 and to a bottom hold circuit 12. Fig. 4 shows a definite structural example of the peak hold circuit 11 and Fig. 5 shows a definite structural example of the bottom hold circuit 12. In Fig. 4, the input terminal is connected to a non-inverting input terminal of a CMOS operational amplifier 14 through an analog switch 13. An MOS hold capacitor 15 is connected to the non-inverting input terminal of the CMOS operational amplifier 14. Negative feedback is applied to the output terminal of the CMOS operational amplifier 14, and this output terminal is connected to the inverting input terminal of a CMOS comparator 16. The output terminal of this CMOS comparator 16 is connected to an OR gate 18, and the output terminal of the OR gate 18 is connected to a control terminal of an analog switch 13. A NOT circuit 19 is interposed between both control terminals of the analog switch 13. A 5V power supply is connected to a non-inverting input terminal of the CMOS operational amplifier 14 through another analog switch 20. In the bottom hold circuit shown in Fig. 5, the circuit construction is substantially the same as that of the peak hold circuit 11 shown in Fig. 4, but the connection of the two input terminals of the CMOS comparator 16 are reversed and the non-inverting input terminal of the CMOS operational amplifier 14 is grounded through the analog switch 20. As is obvious from the definite example given above, the sensor signal processing unit according to the present invention comprises the peak hold means for holding the peak value of the output signals from the sensor, the bottom hold means for holding the bottom value of the output signals from the sensor, the threshold value setting means for setting the threshold value from the peak value from the peak hold means and the bottom value from the bottom hold means, and the comparison means for comparing the output signal of the sensor with the threshold value set by the threshold setting means and outputting a binary signal in accordance with their difference. In the sensor signal processing unit according to the present invention described above, the peak hold means or the bottom hold means includes the operational amplifier, the analog switch is disposed at one of the input terminals of this operational amplifier so as to input the output signal of the sensor and the output of the operational amplifier to the CMOS comparator, and the output terminal of this CMOS comparator is connected to the control terminal of the analog switch. In this way, charging of the capacitor is controlled by controlling the analog switch so as to effect holding of the peak value or the bottom value. When the construction described above is added to the sensor signal processing unit, the output signal of the sensor and the output of the operational amplifier are input to the CMOS comparator, and when the analog switch is controlled by the output of the CMOS comparator, charge to the capacitor is controlled and peak holding or bottom holding is effected. As a result, it is possible to obtain the effect that the potential of the capacitor can be held by controlling the analog switch, and the output level does not change. In the sensor signal processing unit according to the present invention as described above, on the other hand, it is preferred to forcedly deviate the comparator input by a predetermined potential in order to eliminate any mistake in holding due to offset of the CMOS comparator. It is also preferred that the peak value of the peak hold means and the bottom value of the bottom hold means be forcedly set to mutually different values at the turn-on time of the power supply. When such a construction is employed, the CMOS comparator input is forcedly deviated by a predetermined potential and a mistake in holding due to offset of the CMOS comparator can be eliminated. Further, the peak value of the peak hold means and the bottom value of the bottom hold means can be forcedly set to the mutually different values at turn-on time of the power supply, so that chattering of the output can be prevented. The sensor signal processing unit according to the present invention can be applied to a moving body having equidistant portions, at which magnetic substances are equidistantly disposed, and a reference position portion, for converting the equidistant portions and the reference position portion to electric signals. In such a case, a construction is preferably employed so that, when one of the peak value hold means and the bottom value hold means holds the respective hold value, this holding operation is inhibited unless the peak value or the bottom value exceeds a predetermined voltage. According to this construction, the peak value hold means or the bottom value hold means is inhibited from holding the peak value or the bottom value unless the difference between the peak value and the bottom value exceeds a predetermined voltage during the holding operation of the respective means. As a result, the reference position portion can be stably detected by changing setting of the difference voltage between the peak hold value and the bottom hold value in accordance with a ratio of the signal of the equidistant portions to the signal of the reference position portion after confirming the amplitude of the error signal output of the reference position portion of the sensor. The processing unit can be made compact through full LSI into a CMOS chip. Next, the characterizing features of the peak hold circuit 11 shown in Fig. 4 and the bottom hold circuit shown in Fig. 5 will be explained. A typical peak hold circuit according to the prior art is shown in Fig. 6, and a typical bottom hold circuit is shown in Fig. 7. The peak hold circuit (shown in Fig. 6) has been accomplished in the past by utilizing the characteristic feature that a current is caused to flow in only one direction through a diode 21. According to this system, however, only a voltage which is lower by a forward voltage drop Vp of the diode than the actual peak voltage, can be held because such a voltage drop Vp exists in the diode 21. To incorporate such a peak hold circuit into a CMOS LSI, it is essentially necessary to fabricate a BiCMOS structure and to assemble a pure diode devoid of a parasitic effect, inside the LSI. However, this embodiment can avoid such a problem because the analog switch 13 and the CMOS comparator 16 are used in place of the diode 21. Here, the operation of the peak hold circuit (Fig. 4) will be explained. The CMOS comparator 16 compares the peak hold output voltage with the input voltage. When the input voltage is higher than the output voltage, the output of the CMOS comparator 16 is "1", the analog switch 13 is turned on, and charging of the MOS hold capacitor 15 begins. When the potential of the MOS hold capacitor 15 rises, the output voltage similarly rises. Charging continues until the input voltage is equal to the output voltage, at which time the CMOS comparator 16 outputs "0" and the analog switch 13 is turned off. Even when the input voltage drops thereafter, the analog switch 13 is turned off, because the MOS hold capacitor 15 holds the potential, so the output level does not change and the peak value of the input voltage is continuously held. Since this operation also holds true of the bottom hold circuit (Fig. 5), its explanation will be omitted. However, the only difference is that the voltage to be held is the bottom value in the case of the bottom hold circuit. Incidentally, in order to let the peak hold circuit 11 shown in Fig. 4 and the bottom hold circuit 12 shown in Fig. 5 operate stably, the output must reliably become "0" when the non-inverting input terminal and the inverting input terminal in the CMOS comparator 16 reach exactly the same value. Otherwise, the analog switch 13 cannot be turned off even when the input voltage goes over the peak value and starts decreasing, and there is a possibility that the peak voltage cannot be held. Another embodiment of the present invention is directed to solving such a problem. In other words, an application example of the peak value hold circuit 11 shown in Fig. 4 and the bottom hold circuit 12 shown in Fig. 5 is shown in Figs. 8 (peak hold circuit) and 9 (bottom hold circuit 12). To cope with the problem described above, forced offset is provided to the input of the CMOS comparator 16 as shown in Figs. 8 (peak hold circuit) and 9 (bottom hold circuit 12). In other words, in Fig. 8, a current mirror circuit 22 is connected to the non-inverting input terminal of the CMOS comparator 16, and a resistor 23 is interposed between the input terminal and the non-inverting input terminal of the CMOS comparator 16. The potential at the non-inverting input terminal of the CMOS comparator 16 is set to be lower by 20 mV as a potential corresponding to the offset voltage, and to a noise component, by a constant current and the resistor 23. According to this circuit construction, since peak detection can be stably made, peak hold is possible to a low frequency as low as 0.1 Hz. In other words, peak hold can be made to a lower frequency by slightly raising the output voltage of the CMOS operational amplifier 14 during the delay time of the CMOS comparator 16. By the way, when such a circuit (the current mirror circuit 22 and the resistor 23) is not provided, the lowest operation limit is 40 Hz. The similar situation as explained above, can be applicable to the bottom hold circuit shown in Fig. 9, and accordingly, a voltage which is higher than the output by 20 mV, as an offset voltage and a noise component, is set by connecting a current mirror circuit 22 and the resistor 23 to the inverting input terminal of the CMOS comparator 16. Turning back again to Fig. 1, on the other hand, four resistors 24, 25, 26 and 27 are connected in series between the output terminal of the peak hold circuit 11 and the output terminal of the bottom hold circuit 12. Analog switches 28 and 29 are interposed in series between the junction a of the resistors 24 and 25 and the junction b of the resistors 26 and 27. The junction 30 between both analog switches 28, 29 is connected to the non-inverting input terminal of the comparator 10. The output terminal of the comparator 10 is connected to the control terminal of the analog switch 29. Further, the output terminal of the comparator 10 is connected to the control terminal of the analog switch 28 through the NOT circuit 31. An edge detection circuit 32 is connected to the output terminal of the comparator 10, and includes a rising edge detection portion 32a and a falling edge detection portion 32b. The rising edge detection circuit 32a detects the rising edge of the output signal of the comparator 10, and outputs a bottom reset signal to the bottom hold circuit 12. The falling edge detection circuit 32b detects a falling edge of the output signal of the comparator 10 and outputs a peak reset signal to the peak hold circuit 11. In Figs. 2 and 3, the waveform of the output signal of the peak hold circuit 11 is represented by PH and the waveform of the output signal of the bottom hold circuit 12, by BH. Further, the waveform of the signal at the junction 30 between the analog switches 28 and 29 is represented by TH. In Fig. 2, the bottom reset signal from the rise detection portion 32a of the edge detection circuit 32 is represented by BR, and the peak reset signal from the fall detection portion 32b, by PR. Further, in Fig. 2, the output signal of the comparator 10 is represented by OUT. The operation of the circuit having the circuit construction so far explained will be described next. The processing unit includes the peak hold circuit 11 and the bottom hold circuit 12, and a voltage between the peak hold value and the bottom hold value is generated by the resistor voltage division by the resistors 24 to 27, and this voltage is provided as the non-inverting input terminal voltage of the comparator 10. As soon as the comparator 10 changes from the H level to the L level (timings t3 and t5 in Figs. 2 and 3) or vice versa (timings t2 and t4 in Figs. 2 and 3), the peak value or the bottom value is reset so as to greatly change the potential at the non-inverting input terminal of the comparator 10 and to thus greatly deviate the threshold value to prevent incorrect operation. In other words, the potential at the non-inverting input terminal of the comparator 10 is switched to (1/4)·(PH - BH) and(3/4)·(PH - BH) in accordance with the H or L level of the output of the comparator 10. Here, symbols PH and BH represent the peak hold value and the bottom hold value, respectively. Accordingly, the processing unit stably operates not only for the sensor output of a triangular wave or a sine wave but also for a sensor output waveform which is nearly flat at the center of the waveform amplitude. The voltage at the non-inverting input terminal of the comparator is derived by resistor voltage division at a value between the peak hold value and the bottom hold value. Consequently, even when the peak and bottom values of the waveform change in accordance with each peak and valley, angle accuracy of the edge of the OUT waveform can be retained correctly because the threshold value is given by the amplitude ratio. By the way, the lowest operation frequency is determined by the peak hold time and the bottom hold time, and it can be confirmed through experiments that stable operation can be obtained to 0.1 Hz by the use of a hold capacitor of 100 PF. This is a sufficient value for normal use. In Fig. 1, the output terminal of the peak hold circuit 11 is connected to the non-inverting input terminal of the operational amplifier 34 through the resistor 33. The output terminal of the bottom hold circuit 12 is connected to the inverting input terminal of the operational amplifier 34 through the resistor 35. The non-inverting input terminal of the operational amplifier 34 is grounded through the resistor 36. The output terminal of the operational amplifier 34 receives negative feedback through the resistor 37. The output terminal of the operational amplifier 34 is connected to the inverting input terminal of the comparator 38, and the reference power supply 39 is connected to the non-inverting input terminal of the comparator 38. The output terminal of the comparator 38 is connected to one of the input terminals of each of two AND gates 41 and 42. The other input terminal of the AND gate 41 is connected to the output terminal of the comparator 10, and the other input terminal of the AND gate 42 is connected to the output terminal 10 of the comparator 10 through a NOT circuit 17. The output terminal of the AND gate 41 is connected to the peak hold circuit 11 by a peak value pull-up line. The output terminal of the AND gate 42 is connected to the bottom hold circuit 12 through a bottom value pull-down line. In Fig. 2, the output waveform of the operational amplifier 34 is represented by (P - B). The output waveform of the comparator 38 is represented by S1, the output waveform of the AND gate 41, by S3, and the output waveform of the AND gate 42, by S4. The operation of the circuit which has been so far described will be explained next. The operational amplifier 34 computes the difference between the peak hold value (PH) and the bottom hold value (BH). When this difference is smaller than the value of the reference voltage V ref1 of the reference power supply 39, the comparator 38 outputs "1". Then, the analog switch 20 shown in Fig. 4 or the analog switch 20 shown in Fig. 5 is closed (turned on), and the peak value or the bottom value is pulled towards 5V or 0V. When the difference PH - BH becomes greater than the reference voltage V ref1 of the reference power supply 39, the output of the comparator 38 becomes "0", and the analog switch 20 shown in Fig. 4 or the analog switch 20 shown in Fig. 5 is opened (turned off), so that PH - BH is fixed to a value equal to the reference voltage V ref1 . When the circuit operates at the time of turn-on of the power supply (at the timing t1 in Figs. 2 and 3), whether or not the difference PH - BH is smaller than the reference voltage V ref1 is immediately judged, and the peak hold value (PH) is pulled away from the bottom hold value (BH). Normally, the input signal is constant when the power supply is turned on. Accordingly, the peak hold value (PH) and the bottom hold value (BH) are equal to each other. When the circuit of this embodiment is used, however, the peak hold value (PH) can be pulled away from the bottom hold value (BH) simultaneously with turn-on of the power supply, and the CMOS comparator 10 shown in Fig. 1 can be prevented from effecting incorrect judgement due to very small noise of the power supply, so that chattering of the output can be prevented. On the other hand, the inverting input terminal of the comparator is shown connected to the junction 43 between the operational amplifier 34 and the comparator 38 in Fig. 1. The non-inverting input terminal of the comparator 44 is connected to a reference power supply 45 (V ref2 ). The output terminal of the comparator 44 is connected to one of the input terminals of each of the two AND gates 46 and 47. The other input terminal of the AND gate 47 is connected to the output terminal of the comparator 10, and the other input terminal of the AND gate 46 is connected to the output terminal of the comparator 10 through the NOT circuit 48. The output terminal of the AND gate 46 is connected to the OR gate 18 shown in Fig. 4 by a peak hold inhibition line. The output terminal of the AND gate 47 is connected to the OR gate 18 shown in Fig. 5 through a bottom hold inhibition line. In Fig. 2, the output waveform of the comparator 44 is represented by S2, the output waveform of the output terminal of the AND gate 46, by PH1, and the output waveform of the output terminal of the AND gate 47, by BH1. The operation of the circuit having the construction which has been so far explained will be described next. When the bottom value does not deviate by a predetermined voltage during the peak holding operation, the bottom hold inhibition signal (BHI) is generated and bottom hold is inhibited. Accordingly, the threshold value always becomes greater than the MRE output waveform and the output is fixed at the H level, so that the reference position of the rotary member 2 can be detected. The reverse is also true. In other words, so long as the peak value does not deviate by a predetermined voltage during the bottom hold operation, the peak hold inhibition signal (PHI) is output, and peak hold is inhibited. Accordingly, the threshold value is always smaller than MRE output waveform, and the output is kept fixed at the L level. The reference voltage is made variable by the output amplitude ratio at the portions having a narrow magnetization pitch and the reference position devoid of magnetization. Accordingly, the reference position devoid of magnetization can be stably detected by merely updating the set voltage of the difference of the PH - BH value in accordance with the ratio of the output amplitude at the portions having a narrow magnetization pitch and the output amplitude at the reference position devoid of magnetization. In comparison with the prior art system, one of the characterizing features of the sensor signal processing unit according to the present invention described above resides in that the threshold value is set on the basis of the peak value (or the bottom value) immediately after the passage of the peak or bottom of the output signal of the sensor. The present invention can drastically improve angle accuracy of binary pulses on the basis of the technical concept described above. More definitely, in Fig. 3, IN represents the sensor output waveform, PH is the peak hold (peak value) waveform, BH is the bottom hold (bottom value) waveform, and TH is the threshold value waveform set on the basis of the peak value and the bottom value. This TH is given by 3/4 × (PH - BH) during the period of t1 to t2 and the period of t3 to t4, and is given by 1/4 × (PH - BH) during the period of t2 to t3 and the period of t4 to t5. Since the threshold value TH is given by the proportional relationship between the peak value and the bottom value (1/4 and 3/4 in this case), angle accuracy can be maintained even when the peak value and the bottom value change. In this case, the threshold value TH is set after passing by the peak or the bottom of the waveform and outputs the pulse edge (the instant that the sensor output waveform IN passes by TH). Accordingly, the pulse is output on the peak value and the bottom value appearing immediately before, and angle accuracy is high. In other words, the threshold value is set in accordance with the proportional relationship immediately after the waveform passes by the peak and the bottom, and the pulse output is generated. For the reason described above, digitization (binary output) can be effected with high angle accuracy even for a sensor output waveform the height of the peak and bottom of which change for each pulse output. In other words, as can be understood from the waveforms shown in Fig. 15(B), the generation of the threshold value and digitization (pulse forming) are effected after passing by each peak or bottom. Accordingly, angle accuracy is high. Further, high angel accuracy can be secured by effecting resetting and digitization after each peak in addition to the storage of the peak and the bottom. Hysteresis can also be added to a comparison voltage by resetting the peak (or the bottom). When such hysteresis is added, the occurrence of chattering can be prevented when the voltage level of the input signal is close to the threshold value. The sensor signal processing unit of this embodiment is fully constituted into a CMOS chip by LSI. As described above, the digitization apparatus of this embodiment comprises the peak hold circuit 11 (peak hold means) for holding the peak value of the output signal from the rotating angle sensor 6, the bottom hold circuit 12 (bottom hold means) for holding the bottom value of the output signal of the rotating angle sensor 6, the resistors 24 to 27, the analog switches 28, 29 and the NOT circuit 31 (threshold value setting means) for setting the threshold value from the peak value from the peak hold circuit 11 and the bottom value from the bottom hold circuit 12, and the comparator 10 (comparison means) for comparing the threshold value set by the resistors 24 to 27, the analog switches 28, 29 and the NOT circuit 31 (threshold setting means) with the output signal of the rotating angle sensor 6, and outputting the binary signal in accordance with the comparison result. In the afore-mentioned patent publication (Japanese Unexamined Patent Publication (Kokai) No. 4-77671), an amplifier having a large amplification ratio and an amplifier having a small amplification ratio must be provided. However, the present invention does not require the two amplifiers but uses only one amplifier 9. Accordingly, the circuit of the present invention can be simplified. Each of the peak hold circuit 11 and the bottom hold circuit 12 shown in Figs. 4 and 5 includes the CMOS operational amplifier 14 and employs the circuit construction wherein the analog switch 13 is provided at one of the input terminals of this operational amplifier 14, the sensor output signal and the output of the CMOS operational amplifier 14 are applied to the CMOS comparator 16, and the output terminal of the CMOS comparator 16 and the control terminal of the analog switch 13 are connected to control the analog switch 13 so that charging of the MOS hold capacitor 15 can be controlled by controlling the analog switch 13 to execute peak hold or bottom hold operation. As a result, the potential of the MOS hold capacitor 15 can be held by controlling the analog switch 13, and the output level does not change. Here, since the input of the CMOS comparator 16 is forcedly deviated by a predetermined potential as shown in Figs. 8 and 9, the hold error due to offset of the CMOS comparator 16 can be eliminated. When the power supply is turned on, the peak value by the peak hold circuit 11 and the bottom value by the bottom hold circuit 12 are forcedly set to mutually different values. As a result, chattering of the output at the turn-on time of the power supply can be prevented. The rotating angle sensor 6 converts the equidistant portions and the reference position portions into electrical signals for the moving member having such equidistant portions and reference position portions, and the peak hold circuit 11 or the bottom hold circuit 12 inhibits holding of the peak value or the bottom value unless the peak value or the bottom value reaches at least a predetermined voltage during its holding operation. As a result, the reference position portions which output an error signal having a smaller amplitude than that of the signals of the equidistant portions of the sensor can be correctly detected. The sensor signal processing unit in this embodiment is completely converted to the CMOS chip by a LSI configuration, and therefore its size can be reduced. By the way, an error signal having a small amplitude can be discriminated not only by comparison with a predetermined voltage as is made in this embodiment, but also by a ratio of the difference voltage of the peak and bottom values, i.e., PH - BH, as shown in the circuit construction of Fig. 11 and the timing chart of Fig. 12. Next, another method and apparatus for controlling the output of the sensor signal in the sensor signal processing unit according to the present invention will be explained with reference to Figs. 13 to 15(A), 15(B). In addition to the construction of the above embodiment, the sensor signal processing unit of this embodiment includes signal amplification means for adding an offset signal to an output signal of a magnetism detection sensor for sensing magnetism, converting it to an electrical signal and outputting the signal, and amplifying the electrical signal; signal judgement means for outputting an offset adjustment start signal when the output signal of the signal amplification means exceeds a desired upper limit value or the lower limit value; cycle signal generation means for outputting a cycle signal by the offset adjustment start signal; count means for changing a count value by the cycle signal; and output correction means comprising offset signal output means for outputting an offset signal corresponding to the count value. In the sensor signal processing unit having the construction described above, the peak value and the bottom value of the output of the magnetism sensor are held when the output signal of the magnetism detection sensor is digitized, and a digitization threshold value is set by these values. Accordingly, once the output of the magnetism detection sensor is corrected by the output correction circuit, the digitization threshold value can thereafter be set by the peak/bottom hold means, and the correction operation of the output correction circuit is not necessary. In other words, the cycle signal for correction need not be oscillated for correction during the normal operation after the output correction, and a drop in angle accuracy caused by the oscillation spike noise can be prevented. Hereinafter, the construction of this embodiment will be explained with reference to the drawings. Fig. 13 shows a gear 51, an MRE bridge circuit 52, an output correction circuit 53 and a digitization circuit 54. First, the digitization circuit 54 will be explained with reference to Fig. 14. This circuit comprises a binary pulse forming comparator 61 which receives the output signal A corrected and amplified by the MRE bridge circuit 52 as a reversal input, a peak hold circuit 62a and a bottom hold circuit 62b that hold the peak value and the bottom value of the output signal A, respectively, a reset circuit 63 for resetting the hold operations of these hold circuits, and a threshold setting circuit 64 for setting a threshold value as a non-inverting input to the comparator 61 from the hold values. The circuit operation shown in Fig. 14 will be explained next with reference to a simple time chart shown in Figs. 15(A) and 15(B). Fig. 15(A) shows the comparator 61 and Fig. 15(B) shows the time chart. The inverting input of the comparator 61, that is, the MRE output signal A, is represented by symbol IN and indicated by a solid line, the non-inverting input, that is, the threshold value, is represented by TH and indicated by a dotted line, and the output is represented by OUT. When the IN value becomes smaller than the TH value, the output of the comparator 61, i.e., OUT, becomes "High", and when the IN value becomes greater than the TH value, the output OUT becomes "Low". The peak value is the value of the peak of the MRE output signal A and the bottom value is the value of the valley. The bottom hold value is reset when the IN waveform becomes smaller than the TH waveform, that is, when OUT becomes "High", and the peak hold value is reset when the IN waveform becomes greater than the TH waveform, that is, when OUT becomes "Low". The threshold value is set by the voltage dividing resistors, for example, so that it exists between the output value of the peak hold circuit and the output value of the bottom hold circuit (hereinafter called "PH - BH"). In this embodiment, the threshold value is determined by an analog switch, etc., (not shown) which is turned on and off in accordance with the value of OUT, so that the threshold value is (1/4)·(PH - BH) when OUT is "High", and is (3/4)·(PH - BH) when OUT is "Low". As described above, in the digitization circuit 54 according to this embodiment, the threshold value for digitization is not a fixed threshold value, but is continuously determined in accordance with the peak and bottom values of the MRE output signal A. In other words, even when the output changes, the threshold value corresponding to this output is always set, so that the detection error due to the output fluctuation can be prevented. Accordingly, once the offset adjustment is made after supplying the power, the offset adjustment can be stopped, that is, the oscillator of the output correction circuit can be stopped. Since adverse influence of the oscillation spike noise can thus be eliminated, high angle accuracy can be obtained. Next, the output correction circuit 3, which is so constituted as to stop the oscillator once offset is adjusted, will be explained with reference to Fig. 13. The + input of a differential amplifier 55 receives the output of the bridge circuit 52, and the - input receives a regulation voltage generated by a D/A converter 60. The output of the differential amplifier 55 is supplied to the + input of a comparator 56a for setting the upper limit value and the - input of a comparator 56b for setting the lower limit value, and is also input to a digitization circuit 54. Any one of voltages ref1 to ref4 derived and set by dividing the power supply voltage by resistors into four stages for setting the upper and lower limit values, is supplied to the + input and the - input of the comparators 56a and 56b. In this embodiment, ref1 or ref2 is input to the - input of the comparator 56a, and ref3 or ref4 is input to the + input of the comparator 56b. The outputs of the comparators 56a and 56b are input to an OR circuit 57. The output of the OR circuit 57 is input as an oscillation start signal to an oscillator 58, and the output of the oscillator 58 is input to an up/down counter 59. An up/down FLAG which decides to which side the up/down counter 59 should operate in accordance with the output of the comparator 56 is input to the up/down counter 59. In other words, the up/down counter 59 effects count-down when the output of the comparator 56a is "High", and effects count-up when this output is "Low". The output of the counter 59 is input to the D/A converter. Next, the operation of a circuit block shown in Fig. 13 will be explained. It will be assumed here that the gain of the differential amplifier (operational amplifier) 55 is set so that the output of this amplifier 55 is not higher than the set voltage ref1 and not lower than the set voltage ref4 when the signal of the MRE bridge circuit 52 is amplified. The value of ref1 is below the upper limit value of the output voltage range of the operational amplifier and the value of ref4 is above the lower limit value of the output voltage. The values ref2 and ref3 are set to values to which a hysteresis width is added, in order to achieve stable operation at the set values. First, when the power supply voltage is applied, each circuit block is set to the initial state. When the gear 1 starts rotating, the balance of the MRE bridge circuit 2 is disrupted and the output voltage changes. At this time, if the output of the operational amplifier 5 is greater than the set voltage ref1 (which means that the offset voltage occurs in the + direction), the output of the comparator 56a becomes "High" and the output of the OR circuit 57 becomes "High", so that the oscillator 58 starts oscillating. Then, the up/down FLAG becomes "High" and hence, the up/down counter 59 starts to count down due to the oscillation of the oscillator 58. Since the D/A convertor 60 is so wired as to output the analog voltage set by the data of this up/down counter 59, the output voltage of the D/A convertor 60 decreases. Accordingly, the output voltage of the operational amplifier 55 gradually decreases. This operation continues until the output voltage of the operational amplifier 55 drops below the value ref2. When the output voltage of the operational amplifier 55 becomes below ref2, the oscillating operation of the oscillator 58 stops, and the output voltage of the D/A convertor is fixed. In this state, the range of the output voltage of the operational amplifier 55 is not higher than ref2 and not lower than ref4, and this is the voltage range in which the digitization circuit 4 of the post-stage of the operational amplifier stably operates. Next, when the output voltage of the operational amplifier 5 is lower than ref4, the output of the comparator 56b becomes "High" and the output of the OR circuit 59 becomes "High", so that the oscillator 38 starts oscillating. Then, since the output of the comparator 56a is "Low" at this time, the up/down FLAG becomes "Low", so that the up/down counter 59 starts to count up due to the oscillation of the oscillator 58. In consequence, the output voltage of the D/A convertor 60 gradually increases. This operation continues until the output voltage of the operational amplifier 55 rises above ref3. When the output voltage of the operational amplifier becomes higher than ref3, the oscillating operation of the oscillator 59 stops, and the output range of the operational amplifier is fixed to a range not higher than ref1 and not lower than ref3. This is the voltage range in which the digitization circuit 54 of the post-stage of the operational amplifier 54 stably operates. As described above, according to this embodiment, the oscillating operation of the oscillator is started when the amplification signal of the MRE bridge output exceeds the set voltage ref1 or ref4 which is set in advance, and is stopped when the output voltage of the operational amplifier enters the range described above. Accordingly, the oscillator does not oscillate during the normal operation and consequently, the influence of the oscillation spike noise can be eliminated. In other words, angle detection can be stably made with a high level of accuracy such as an absolute angle accuracy of ±0.1 and repeatability of 0.02. Digitization of the output waveform is effected by the digitization circuit 54 comprising the binary pulse forming comparator 61 and the peak/bottom hold circuit 62. The peak/bottom hold circuit 62 stores at each sampling time the peak and bottom voltages of the output waveform of the operational amplifier 55 in a suitable memory, sets the threshold value in accordance with these voltages, and inputs it to the binary pulse forming comparator 61. The binary pulse forming comparator 61 digitizes the output waveform of the operational amplifier 55 in accordance with the threshold value set by the peak/bottom hold circuits 62a and 62b. According to this construction, the binary pulse edge can be output with high angle accuracy for the output waveform A having a suitable amplitude within a broad range of ref1 to ref4. Thereafter, the binary pulse is processed by a signal processing circuit not shown in the drawings.

Claims: Sensor signal processing unit, comprising: [a] a peak hold means (11) for holding a peak value of an output signal of a sensor (6;52); [b] a bottom hold means (12) for holding a bottom value of said output signal of said sensor (6;52); [c] a threshold value setting means (24-29) for setting a threshold value from the respective peak value held by said peak hold means (11) and the respective bottom value held by said bottom hold means (12); and [d] a comparison means (10) for comparing the respective output signal of said sensor (6;52) with the respective threshold value set by said setting means (24-29) and for outputting a binary output signal in accordance with the comparison result; characterized in that [e] an edge detection means (32) is provided which is detecting the raising and falling edge of said binary output signal of said comparison means (10), in response to the detected rising edge outputs a bottom reset signal (BR) to said bottom hold means (12) and in response to the detected falling edge outputs a peak reset signal (PR) to said peak hold means (11), and [c1] said threshold value setting means (24-29) is updating said threshold value (TH) at each level conversion of said binary output signal of said comparison means (10). Sensor signal processing unit according to claim 1, characterized in that said peak hold means (11) or said bottom hold means (12) is comprised of [a] an operational amplifier (14); [b] a hold capacitor (15) which is connected to one input terminal (+) of said operational amplifier (14); [c] an analog switch (13) whose output terminal is connected to said one input terminal (+) of said operational amplifier (14) and whose input terminal receives the output signal of said sensor (6;52); and [d] a CMOS comparator (16) whose one input terminal is connected to the output terminal of said operational amplifier (14), whose other input terminal receives the output signal of said sensor (6;52) and is forcedly deviated by a predetermined potential so as to eliminate a hold error due to an offset of said CMOS comparator (16), and whose output terminal is connected to the control terminal of said analog switch (13) so that the charging of said hold capacitor (15) can be controlled. Sensor signal processing unit according to claim 1 or 2, characterized by a peak value setting means (41) and a bottom value setting means (42) for forcedly setting the output signals of said peak hold means (11) and said bottom hold means (12), respectively, to reference signal levels (5V, 0V) if the difference of the respective output signal of said peak hold means (11) and said bottom hold means (12) is lower than the value of a reference power supply (39). Sensor signal processing unit according to one of claims 1 through 3, characterized by a hold inhibiting means (46, 47) which inhibits the holding action of said peak hold means (11) and/or of said bottom hold means (12) unless the respective holding value thereof exceeds a predetermined voltage while said peak hold means (11) and said bottom hold means (12), respectively, are holding a voltage. Sensor signal processing unit according to one of claims 1 through 4, wherein said sensor is a magnetism detection sensor (52) for sensing magnetism, characterized by: [a] a signal amplification means (55) for amplifying an output signal of said sensor (52) offset by an offset signal; [b] a cyclic signal generation means for outputting a cyclic signal when the output signal of said signal amplification means (55) exceeds a predetermined upper or lower limit value; [c] a counting means (59) for counting cycles of said cyclic signal; and [d] an offset signal outputting means (60) for outputting said offset signal in accordance with a counting number of said counting means (59); [e] wherein said peak hold means (11), said bottom hold means (12) and said comparison means (10) receive as input signal the output signal of said signal amplification means (55). Sensor signal processing unit according to claim 5, characterized in that said cyclic signal generation means includes: [a] a first signal comparison means (56a) for comparing the output signal of said signal amplification means (55) with the predetermined upper limit value; [b] a second signal comparison means (56b) for comparing the output signal of said signal amplification means (55) with the predetermined lower limit value; and [c] a cyclic signal outputting means (57) for outputting a cyclic signal when said first signal comparison means (56a) determines that the output signal of said signal amplification means (55) is higher than the predetermined upper limit value and when said second signal comparison means (56b) determines that the output signal of said signal amplification means (55) is lower than the predetermined lower limit value. Sensor signal processing unit according to claim 6, characterized in that said counting means (59) is counting in a count-up direction or in a count-down direction in accordance with the output of said first signal comparison means (56a) and said second signal comparison means (56b). Sensor signal processing unit according to claim 6 or 7, characterized in that at least two values are set between the predetermined upper or lower limit values.

Inventors: AOYAMA SEIKI, IZAWA ICHIROU, KUROYANAGI SUSUMU, MAKINO TOMOATU, MAKINO YASUAKI, AOYAMA, SEIKI, IZAWA, ICHIROU, KUROYANAGI, SUSUMU, MAKINO, TOMOATU, MAKINO, YASUAKI, IZAWA, ICHIROU SASAME-SHATAKU 242, 83-9, KUROYANAGI, SUSUMU 39, ICHIBAYASHIKI,, MAKINO, TOMOATU 46, RYOMACHI 2-CHOME,
Applicants: DENSO CORP, DENSO CORPORATION
Application year: 1994
Main classification: G01D5
IPC codes: G01D5, H03K5, G01D1