SRAM memory structure and manufacturing method thereof

Abstract: The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors (Q 3 , Q 4 ), a pair of driver transistors (Q 1 , Q 2 ), and a pair of load transistors Q 5 , Q 6 . The gate insulating film of access transistor (Q 3 , Q 4 ) is formed of a single layer of silicon oxide film (27c), while the gate insulating film of driver transistor (Q 1 , Q 2 ) is formed of a stacked layer formed of a silicon oxide film (27a) and a silicon nitride film (27b). The pair of load transistors (Q 5 , Q 6 ) are formed of two layers of polycrystalline silicon layers (41, 42) stacked upon each other with an insulating film therebetween. A source region (41b, 42b) and a drain region (41a, 42a) are formed in each of polycrystalline silicon layers (41, 42) with each channel region (41c, 42c) therebetween. One drain region (41a) forms a gate opposite to the other channel region (42c), while the other drain region (42a) forms a gate opposite to the one channel region (41c).

Description: The present invention relates to a semiconductor memory device and to a manufacturing method thereof. Conventionally, SRAM is known as one kind of semiconductor memory device. Fig. 18 is an equivalent circuit diagram showing one memory cell of a conventional SRAM. Referring to Fig. 18, the memory cell uses a p type MOS (Metal Oxide Semiconductor) as a load, and is formed of six transistors. More specifically, a pair of driver transistors (for driving) Q 1 and Q 2 (n type MOS transistors) and a pair of load transistors Q 5 and Q 6 (p type MOS transistors) are connected with each other to constitute a flip-flop circuit. The source regions 110 and 111 of the pair of load transistors Q 5 and Q 6 are connected to a power supply V cc . The source regions of driver transistors Q 1 and Q 2 are connected to GNDs 112 and 113. A pair of access transistors Q 3 and Q 4 (n type MOS transistors) are connected to storage nodes 114 and 115, respectively. A bit line 107 is connected to one of the source/drain regions of access transistor Q 3 . A bit line 108 is connected to one of the source/drain regions of access transistor Q 4 . The gate electrodes of access transistors Q 3 and Q 4 are connected to a word line 109. Now, a conventional SRAM memory cell structure will be described by way of illustrating a document (International Electron Device Meeting 1991 Technical Digest pp. 481 - 484). Figs. 19A and 19B are plan views showing a conventional SRAM memory cell structure divided into two stages from the bottom layer. More specifically, Fig. 19A illustrates driver transistors Q1 and Q2 and access transistors Q 3 and Q 4 formed on a substrate, while Fig. 19B illustrates thin film transistors (TFT) Q 5 and Q 6 . Fig. 20 is a schematic sectional view taken along line G-G in Figs. 19A and 19B. Referring to Figs. 19A, 19B, and 20, in the conventional memory cell, a pair of driver transistors Q 1 and Q 2 and a pair of access transistor Q 3 and Q 4 are formed at a main surface of a p type well 120. Driver transistor Q 1 has a drain region 125a and a source region 125b opposing to each other with a channel region 125c therebetween, and a gate electrode 124. Driver transistor Q 2 has a drain region 126a and a source region 126b opposing to each other with a channel region 126c therebetween, and a gate electrode 123. Access transistor Q 3 has a pair of source/drain regions 125d opposing to each other with a channel region 125e therebetween, and a gate electrode 121. Access transistor Q 4 has a pair of source/drain regions 126d opposing to each other with a channel region 126e therebetween, and a gate electrode 122. These transistors are formed of n type MOS transistors having source/drain regions formed on the main surface of p type well 120. The gate electrode 123 of driver transistor Q 2 is connected to the source/drain region 125d of access transistor Q 3 and the drain region 125a of driver transistor Q 1 through a contact portion 123a. The gate electrode 124 of driver transistor Q 1 is connected to the source/drain region 126d of access transistor Q 4 and the drain region 126a of driver transistor Q 2 through a contact portion 124a. The drain region 143a of load transistor Q 5 and the gate electrode 142 of load transistor Q 6 are connected to the gate electrode 124 of driver transistor Q 1 through a contact portion 143d. The drain region 144a of load transistor Q 6 and the gate electrode 141 of load transistor Q 5 are connected to the gate electrode 123 of driver transistor Q 2 through a contact portion 144d. A tungsten silicide layer 135 to be a GND line is formed at the position of an intermediate layer between driver transistor Q 1 , Q 2 and access transistor Q 3 , Q 4 , and load transistors Q 5 , Q 6 . A bit line 139 is connected to the source/drain region 125d of access transistor Q 3 with a plug layer 137 therebetween. The other bit line (not shown) is connected to the source/drain region 126d of access transistor Q 4 with a plug layer therebetween as in the case of bit line 139. Load transistors Q 5 and Q 6 each formed of a thin film transistor have gate electrodes 141 and 142 lying under channel regions 143c and 144c, respectively, and each constitutes a so-called bottom gate type transistor. Fig. 21 is a sectional view showing a typical cross section of a thin film transistor used for load transistors Q 5 and Q 6 . Referring to Fig. 21, the thin film transistor includes channel region 144c, drain region 144a, and source region 144b formed in a semiconductor layer such as of polycrystalline silicon. Gate electrode 142 is formed at a position opposing to channel region 144c with an insulating layer therebetween. Fig. 22 is a graphic representation showing the current characteristic of the above-described thin film transistor. In Fig. 22, Vd represents drain voltage, Vg gate voltage, and Id drain current. In such an SRAM, in order to increase the integration density of memory cells, an area occupied by each memory cell on plane must be reduced. More specifically, the area on plane occupied by driver transistors Q 1 , Q 2 , access transistors Q 3 , Q 4 , and load transistors Q 5 , Q 6 must be reduced. The above-described conventional memory cell is however encountered with the following two disadvantages in increasing integration density. The first disadvantage is instability in operation at the time of reading. Now, this disadvantage will be described in more detail. Figs. 23A and 23B are diagrams showing an equivalent circuit of the memory cell shown in Fig. 18 by dividing it into two inverter circuits related to reading operation. Referring to Figs. 23A and 23B, load transistors Q 5 and Q 6 are not illustrated, because current flowing across them is significantly small. The reading characteristic of the memory cell is produced from voltage change at the storage node thereof, with a bit line and a word line fixed to Vcc, while changing the gate voltage of a driver transistor (voltage at the storage node of the other side). Fig. 24 is a graphic representation showing the reading characteristic of the above-described SRAM. Referring to Fig. 24, the abscissa represents the voltage of storage node 115, while the ordinate represents the voltage of storage node 114. Curve α 1 represents the voltage change characteristic of storage node 114 when the voltage of storage node 115 is changed. Curve γ 1 represents the voltage change characteristic of storage node 115 when the voltage of storage node 114 is changed. Curves α 1 and γ 1 cross at three points P 1 , P 2 , and P 3 . Point P 3 corresponds to storage node 114 storing "High" data, while point P 1 corresponds to storage node 115 storing "High" data. Point P 2 is an unstable point, and voltage does not stop at point P 2 at the time of reading. In the figure, a region defined by circle h 1 is a so-called "memory cell eye". Generally, the larger the memory cell eye is, the more stable will be the reading operation. The memory cell eye is discussed in Evert Seevinck et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-22, No. 5, October 1987 pp. 748 - 754, and H. Shinohara et al., VLSI '82, pp. 106 - 107. There are several ways of enlarging a memory cell eye, and two approaches will be described in the following. The first method is to enlarge the driving capability ratio β of driver transistor and access transistor (in other words driving capability of driver transistor/driving capability of access transistor). Fig. 25 is a graphic representation showing the reading characteristic when the driving capability ratio β is increased with respect to the case shown in Fig. 24. Referring to Fig. 25, the memory cell eye is enlarged from circle h 1 to circle h 2 . The second approach is to reduce threshold voltage V th of access transistor. Vcc- 1 (distance between Vcc and  1 ) and Vcc- 2 (distance between Vcc and  2 ) in Fig. 24 correspond to the threshold voltages V th of access transistors Q 3 and Q 4 , respectively. It is noted that  1 and  2 are High level voltages of the outputs of the respective inverters. Fig. 26 is a graphic representation showing the characteristic when the threshold voltage V th of access transistor is reduced with respect to the case of Fig. 24. Referring to Fig. 26, if the threshold voltages V th of access transistors Q 3 and Q 4 are reduced to Vcc- 3 and Vcc- 4 , respectively, the memory cell eye is enlarged from circle h 1 to circle h 3 . Referring to Fig. 19A, a conventional approach for enlarging a memory cell eye is to increase the gate widths W D of driver transistors Q 1 and Q 2 , or to reduce the gate widths W A of access transistors Q 3 and Q 4 . This is because the driving capability of a transistor is substantially proportional to its gate width. To increase the gate width W D of a driver transistor however hinders the memory cell from being reduced in size, and therefore is not preferable in view of high intensity integration. Meanwhile, to reduce the gate width W A of an access transistor gives rise to increase in the threshold voltage V th of the access transistor due to the narrow channel effect. Therefore, the memory cell eye is reduced conversely as described above, resulting in unstable reading operation. As described above, such a conventional SRAM memory cell structure can not provide increase in integration density while maintaining operation stability. The second disadvantage is due to the limits of manufacture by photolithography techniques. Now, the limits will be described in more detail. Load transistors Q 5 and Q 6 employed in the conventional SRAM memory cell structure shown in Figs. 19A and 19B are both bottom gate type thin film transistors. Referring to Fig. 19B in particular, the gates 141 and 142 of load transistors Q 5 and Q 6 are formed of one layer. More specifically, when load transistors Q 5 and Q 6 are formed, a conductive layer is formed first, and then gate electrodes 141 and 142 are formed from the conductive layer by patterning utilizing a photolithography technique or the like. In the present state of the art, a minimum manufacturing size in patterning by means of photolithography is about 0.35µm and therefore the size of each portion of gate electrodes 141 and 142 patterned by means of photolithography (L 3 and L 4 , for example) can not be smaller than 0.35µm. The source/drain regions of load transistor Q 5 , Q 6 and layers 143, 144 to be channel regions are both also formed of one layer. Accordingly, the size of each portion of layers 143 and 144 (L 5 for example) can not be smaller than 0.35µm either. As described above, with the limits in the manufacture utilizing photolithography techniques, it is difficult to reduce the occupied area of load transistors Q 5 and Q 6 on plane, and the conventional SRAM memory cell structure is not statable for high density integration in this regard as well. The structure of load transistors Q 5 , Q 6 which is less susceptible to the limits in the manufacture by photolithography techniques as described above is disclosed in Japanese Patent Laying-Open No. 3-34569. Meanwhile, Fig. 27 is a plan view schematically showing the structure of a load transistor in Japanese Patent Laying-Open No. 3-34569. Referring to Fig. 27, the pair of load transistors are formed of two polycrystalline silicon layers 301 and 303 piled upon each other with an insulating film (not shown) therebetween. A drain region 301a and a source region 301b are formed with a channel region 301c therebetween in polycrystalline silicon layer 301. A drain region 303a and a source region 303b are formed with a channel region 303c therebetween in polycrystalline silicon layer 303. A drain region 303a to be a gate electrode is present on the underlying channel region 301c with an insulating film therebetween. Drain region 301a to be a gate electrode is present under the overlying channel region 303c with the insulating film therebetween. Thus, in the structure of the pair of load transistors, one constitutes a bottom gate type transistor and the other a top gate type transistor. The drain region of one transistor uses the gate electrode of the other transistor. Therefore, the limits in the manufacture by photolithography described above are reduced. The load transistor structure is therefore suitable for high density integration. The drain region 301a of the underlying polycrystalline silicon film 301 is not covered with overlying polycrystalline silicon film 303. Accordingly, an impurity can be implanted into drain region 301a in a self-aligned manner. In the load transistor structure, however, channel regions 301c and 303c both has an approximately L-shape. If, for example, misregistration of a mask at the time of patterning polycrystalline silicon thin film 303 causes the overlying polycrystalline silicon thin film 303 to be shifted with respect to the underlying polycrystalline silicon thin film 301 in the direction indicated by arrow J or K, the sizes L 6 , L 7 , W 1 , and W 2 of the portions of channel regions 301c and 303c can easily be changed. Fig. 28 is a plan view schematically showing how the dimension of a channel region is changed by misregistration of a mask. Referring to Fig. 28, the load transistor pair structure shown in Fig. 27 has its channel region dimension easily changed. Accordingly, a load transistor having a desired characteristic can not be obtained. It is also difficult to provide stable operation. As described above, in load transistors employed for a conventional SRAM memory cell structure, it was not possible to provide a structure suitable for high intensity integration while maintaining stable operation. A further semiconductor memory device and a method of its fabrication are known from EP-A-0 522 689. It is an object of the invention to provide a SRAM memory cell structure suitable for high density integration. This object is achieved by a semiconductor memory device according to claim 1 and a method according to claim 5, respectively. Further developments of the invention are given in the subclaims. The foregoing and other features and advantages of the present invention will become more apparent from the following detailed description of an embodiment of the present invention in conjunction with the accompanying drawings, of which : Fig. 1 is a sectional view schematically showing an SRAM memory cell structure according to a first embodiment of the invention in a cross section corresponding to Fig. 44; Fig. 2A is a schematic sectional view showing the structure of an access transistor in region A in Fig. 1 being enlarged; Fig. 2B is a schematic sectional view showing a driver transistor taken along line B-B in Fig. 1; Figs. 3A-8A and Figs. 3B-8B are cross sectional views schematically showing in the order of steps methods of manufacturing an access transistor and a driver transistor employed for the SRAM memory cell structure according to the first embodiment of the invention; Figs. 9A and 9B are sectional views showing manufacturing methods of the access transistor and driver transistor employed for the SRAM memory cell structure according to the first embodiment of the invention when the material of the gate insulating films are changed; Figs. 10A and 10B are sectional views schematically showing the structure of the access transistor and driver transistor corresponding to Figs. 9A and 9B; Figs. 11A and 11B are sectional views schematically showing the access transistor and driver transistor employed for the SRAM memory cell structure according to the first embodiment of the invention when the materials of the gate insulating films are changed; Figs. 12A-14A and Figs. 12B-14B are sectional views schematically showing in the order of steps methods of manufacturing the access transistor and driver transistor corresponding to Figs. 11A and 11B; Figs. 15A and 15B are sectional views schematically showing the structure of an access transistor and a driver transistor each having a gate insulating film formed of a single layer; Figs. 16A and 16B are sectional views showing manufacturing methods of the access transistor and driver transistor employed for the SRAM memory cell structure according to the first embodiment of the invention when the materials of the gate insulating films are changed; Figs. 17A and 17B are sectional views schematically showing the structure of the access transistor and driver transistor corresponding to Figs. 16A and 16B; Fig. 18 is an equivalent circuit diagram showing a general SRAM; Figs. 19A and 19B are plan views schematically showing a driver transistor, an access transistor, and a load transistor employed for a conventional SRAM memory cell structure; Fig. 20 is a sectional view taken along line G-G in Figs. 19A and 19B; Fig. 21 is a sectional view showing a thin film transistor forming a conventional load transistor; Fig. 22 is a representation showing the characteristic of the thin film transistor forming the conventional load transistor shown in Fig. 21; Figs. 23A and 23B are equivalent circuit diagrams for use in illustration of reading operation from a conventional SRAM memory cell; Fig. 24 is a representation showing characteristic curves in reading of data from a conventional memory cell; Fig. 25 is a representation showing characteristic curves in reading data showing the state of memory cell eyes when the driving capability ratio is increased; Fig. 26 is a representation showing characteristic curves in reading data showing the state of memory cell eyes when the threshold voltage V th of an access transistor is reduced; Fig. 27 is a plan view schematically showing the structure of a load transistor disclosed in a published document; and Fig. 28 is a representation for use in illustration of a disadvantage when mask misregistration is generated in the load transistor shown in Fig. 27. Now, the preferred embodiment of the invention will be described in conjunction with the accompanying drawings. Embodiment 1 Fig. 1 is a schematic cross sectional view showing in a cross section a memory cell structure for an SRAM according to a first embodiment of the invention corresponding to Fig. 20. Fig. 2A is an enlarged cross sectional view showing the structure of an access transistor indicated by region A in Fig. 1, while Fig. 2B is a schematic cross sectional view showing a driver transistor taken along line B-B in Fig. 1. Referring to Figs. 1, 2A and 2B, a pair of driver transistors Q 1 , Q 2 , and a pair of access transistors Q 3 , Q 4 are formed on a main surface of a p well 20. Driver Q 1 has a drain region 25a and a source region 25b, and a gate electrode 23. Driver transistor Q 2 has a drain region 26a, a source region 26b, and a gate electrode 23. Driver transistors Q 1 and Q 2 have a gate insulating film formed of a silicon oxide film 27a and a silicon nitride film 27b piled thereon. Access transistor Q 3 has a pair of source/drain regions 25d and a gate electrode 21. Access transistor Q 4 has a pair of source/drain regions 26d and a gate electrode 22. Access transistors Q 3 and Q 4 have a gate insulating film of a single layer silicon oxide film 27c. The memory cell structure of the SRAM according to the first embodiment of the invention is substantially identical to the memory structure of the conventional SRAM shown in Figs. 19A, 19B, and 20 except for the structure of the above-described driver transistors Q 1 , Q 2 , and access transistors Q 3 , Q 4 , and therefore description thereof is omitted. In the memory cell structure of the SRAM according to the embodiment, materials having different dielectric constants are used for the gate insulating films of driver transistors Q 1 , Q 2 , and the gate insulating film of access transistors Q 3 , Q 4 . Therefore, the driving capability ratio β of driver transistor to access transistor can advantageously be increased. Hereinafter, this will be described by referring to Mitsumasa Koyanagi, SUBMICRON DEVICE I Maruzen Kabushiki Kaisha, pp. 4 - 8. The driving capability of a transistor is given as follows: W L · µ eff · C IN where W represents the gate width of a transistor, L the gate length, µ eff the effective degree of movement of electrons on the surface, and C IN the capacitance of the gate insulating film per unit area. C IN is given by the following expression: C IN = ε IN · ε 0 t IN where ε 0 is a vacuum dielectric constant, ε IN is the relative dielectric constant of the gate insulating film, t IN is the thickness of the gate insulating film. As described, the driving capability ratio β is represented as "driving capability of driver transistor"/"driving capability of access transistor". Accordingly, one method of increasing the driving capability ratio β is to reduce the driving capability of an access transistor relative to the driving capability of a driver transistor. Reducing the relative dielectric constant of the gate insulating film of access transistors Q 3 , Q 4 would reduce the driving capability of the access transistor from expressions (1) and (2). From expressions (1) and (2), as the relative dielectric constant ε IN of a gate insulating film is increased, the driving capability of the transistor is increased, while the relative dielectric constant ε IN of a gate insulating film is reduced, the driving capability of the transistor is reduced. Accordingly, if a material having a smaller dielectric constant than the gate insulating film of driver transistors Q 1 and Q 2 is used for the gate insulating film of access transistors Q 3 and Q 4 , the driving capability of access transistors Q 3 , Q 4 relative to driver transistors Q 1 , Q 2 can be reduced. As a result, the driving capability ratio β can be increased. In contrast, from the above-described expressions (1) and (2), as another approach the same material is used for the gate insulating film of driver transistors Q 1 , Q 2 , and the gate insulating film of access transistors Q 3 , Q 4 , only their film thicknesses t IN are made different, and then the driving capability ratio β would be increased as a result. This approach is disclosed in Japanese Patent Laying-Open No. 63-211751. In this prior art document, only silicon oxide films are used for the gate insulating films of both of access transistors Q 3 , Q 4 and driver transistors Q 1 , Q 2 . The thickness t IN1 of the gate oxide film of access transistors Q 3 , Q 4 is formed larger than the thickness t IN2 of the gate oxide film of driver transistors Q 1 , Q 2 , and therefore a larger driving capability ratio β is obtained. According to the approach disclosed in the above-described prior art document, however, the larger the driving capability ratio β is to be, the larger will be difference in the thicknesses (t IN1 -t IN2 ) of the gate oxide films of driver transistors Q 1 , Q 2 and access transistors Q 3 , Q 4 . Accordingly, difference in potential between the gate electrodes of driver transistors Q 1 , Q 2 and access transistors Q 3 , Q 4 is large. Therefore, failures in a pattern shape are encountered in patterning the upper layer of the gate electrodes by means of photolithography. In this embodiment, by arbitrarily selecting materials having different dielectric constants for the gate insulating films, the film thickness of the gate insulating films of access transistors Q 3 , Q 4 , and driver transistors Q 1 , Q 2 can be set to desired values. Accordingly, the film thicknesses of the gate insulating films of access transistors Q 3 , Q 4 , and driver transistors Q 1 , Q 2 can be set identical. In such a case, failures in patterns on the upper layer of the gate electrodes by photolithography will hardly be encountered. More specifically, as illustrated in Figs. 1, 2A and 2B, the gate insulating film of access transistors Q 3 , Q 4 remains to be silicon oxide film 27c, and a stacked structure of silicon oxide film 27a and silicon nitride film 27b is used for the gate insulating film of driver transistors Q 1 , Q 2 . In this case, the relative dielectric constant of the silicon oxide film ε OX ≒3.8-3.85, while the relative dielectric constant of the silicon nitride film e N ≒7 which is about twice as large as that of the silicon oxide film. The gate insulating film for driver transistors Q 1 , Q 2 has a higher dielectric constant than access transistors Q 3 , Q 4 . As described above, in this embodiment, the driving capability ratio β can effectively be increased by controlling the material and thickness of the insulating film. Now, a manufacturing method will be described by way of illustrating driver transistor Q 2 and, access transistor Q 3 in Figs. 1, 2A and 2B. Figs. 3A-8A and Figs. 3B-8B are cross sectional views schematically showing, in the order of process, steps in a method of manufacturing an access transistor and a driver transistor used in the SRAM memory cell structure according to the first embodiment of the invention. Figs. 3A-8A show the access transistor, while Figs. 3B-8B show the driver transistor. Referring to Figs. 3A and 3B, a channel dope implantation is performed to p type well 20. A threshold voltage V th for the access transistor is determined by this implantation. Referring to Figs. 4A and 4B, photoresist 51a is formed on substrate 20 in an access transistor region (Fig. 4A), and then a channel dope implantation is performed to a driver transistor region (Fig. 4B) in well 20. These two channel dope implantations determine a threshold voltage for the driver transistor. Then, photoresist 51a is removed away. In the process shown in Figs. 3A and 3B, if an impurity is implanted to p type well 20 only into the access transistor region (Fig. 3A) covering only the driver transistor region (Fig. 3B) with resist for example and then implantation is performed to the driver transistor region (Fig. 4B) in p type well 20 by covering only the surface of access transistor region (Fig. 4A) with resist 51a in the process shown in Figs. 4A and 4B, the threshold voltage for the driver transistor can be determined by a single channel dope implantation. Referring to Figs. 5A and 5B, a thermal oxidation treatment is performed on the entire surface of the wafer, and a silicon oxide film 27a is formed on the surface of the wafer. A silicon nitride film 27b is formed on the entire surface of silicon oxide film 27a. Then, photoresist 51b is formed only on silicon nitride film 27b in the driver transistor region (Fig. 5B). Silicon nitride film 27b and silicon oxide film 27a in the access transistor region (Fig. 5A) are sequentially subjected to wet or dry etching utilizing photoresist 51b as mask. Then, photoresist 51b is removed away. Referring to Figs. 6A and 6B, the above-described etching exposes the surface of p type well 20 in the access transistor region (Fig. 6A.) Referring to Figs. 7A and 7B, a silicon oxide film 27c is formed on p type well 20 in the access transistor region (Fig. 7A) by a thermal oxidation treatment. In the thermal oxidation treatment, silicon nitride film 27b in the driver transistor region (Fig. 7B) is little oxidized. Accordingly, silicon oxide film 27c is formed only in the access transistor region (Fig. 7A). Referring to Figs. 8A and 8B, a polycrystalline silicon film is formed on the entire surface of the wafer 20. The polycrystalline silicon film, silicon nitride film 27b, and silicon oxide films 27c, 27a are sequentially etched away by means of photolithography and etching, and gate electrodes 21, 23, and gate insulating films 27c, 27a, 27b are formed. Then, an impurity is implanted using gate electrodes 21, 23, and an isolation oxide film (not shown) as mask. Thus, source/drain regions 25d, 26a, 26b as illustrated in Fig. 2 are formed. Assuming that the thickness of silicon oxide film 27c is t OX2 , the thickness of silicon oxide film 27a t OX1 , and the thickness of silicon nitride film 27b t N , the driving capability ratio β can be increased provided that silicon oxide films 27a, 27c, and silicon nitride film 27b are formed satisfying the following expression: ε OX t OX2 < 1 t OX1 ε OX + t N ε N It is noted that in the above-described embodiment, silicon nitride film 27b is used as a material having a different dielectric constant, but any other insulating film may be used. In this case, not only silicon oxide film 27c is formed on substrate 20 in the access transistor region (Fig. 9A) as shown in Figs. 9A and 9B but also silicon oxide film 27d is formed on the surface of insulating film 27ba by a thermal oxidation treatment in the process as illustrated in Figs. 6A and 6B. Then, post-treatment as described above is performed to form access transistor Q 3 and driver transistor Q 2 shown in Figs. 10A and 10B. At the time, assuming that the thickness of insulating film 27ba is t a , dielectric constant ε a , and the thickness of silicon oxide film 27d t OX3 , each gate insulating film needs only be formed satisfying the following expression: ε OX t OX2 < 1 t OX1 ε OX + t a ε a + t OX3 ε OX Though in Figs. 2B and 10B the gate insulating film of the driver transistor is formed of a plurality of layers, it may be simply formed of a single insulating film layer having a dielectric constant different from the silicon oxide film. Furthermore, the device may be arranged so that the gate insulating film of the access transistor is formed of a plurality of layers, while the gate insulating film of the driver transistor is formed of a single layer. Referring to Figs. 11A and 11B, a stacked layer of a silicon oxide film 27e and a silicon nitride film 27f, for example, may be used for the gate insulating film of access transistor Q 3 , while a single layer of silicon oxide film 27g may be used for the gate insulating film of driver transistor Q 4 . A manufacturing method when access transistor Q 3 and driver transistor Q 4 are thus structured will be described. Figs. 12A-14A and Figs. 12B-14B are cross sectional views schematically showing in the order of the process a manufacturing method of the access transistor and driver transistor shown in Figs. 11A and 11B. Referring to Figs. 12A and 12B, a channel dope implantation is performed to p type well 20 in order to determine a threshold voltage for each transistor. This channel dope implantation is substantially identical to the process illustrated in conjunction with Figs. 3A and 3B, and Figs. 4A and 4B, and therefore the description thereof is omitted. After the channel dope implantation, a silicon oxide film 27e and a silicon nitride film 27f are sequentially stack upon each other on the entire surface of p type well 20. Photoresist 51c is formed on the surface of silicon nitride film 27f in an access transistor region (Fig. 12A). Silicon nitride film 27f and silicon oxide film 27e in a driver transistor region (Fig. 12B) are sequentially etched away using photoresist 51c as mask. Referring to Figs. 13A and 13B, this step of etching away exposes the surface of p type well 20 in the driver transistor region (Fig. 13B). Referring to Figs. 14A and 14B, a silicon oxide film 27g is formed on p type well 20 in the driver transistor region (Fig. 14B) by a thermal oxidation treatment. It is noted that since silicon nitride film 27f is hardly oxidized at the time, and little silicon oxide film is formed on silicon nitride film 27f in the access transistor region (Fig. 14A). Then, a polycrystalline silicon film is formed on the entire surface of the silicon substrate. The polycrystalline silicon film is patterned into a desired form, and then an impurity is implanted to form access transistor Q 3 and driver transistor Q 2 as illustrated in Figs. 11A and 11B. In the structure shown in Figs. 11A and 11B, assuming that the thickness of silicon oxide film 27e is t OX1 , the thickness of silicon nitride film 27f is t N , and the thickness of silicon oxide film 27g is t OX2 , each gate insulating film is formed satisfying the following expression: 1 t OX1 ε OX + t N ε N < ε OX t OX2 Also in Figs. 2A and 2B and Figs. 10A and 10B, the gate insulating film of a driver transistor is formed of a plurality of layers, it may simply be formed of a single layer of insulating film having a dielectric constant different from the silicon oxide film. Referring to Fig. 15, for example, gate insulating film 27k for access transistors Q 3 , Q 4 may be formed of a single layer of silicon oxide film and gate insulating film 27j for driver transistors Q 1 , Q 2 may be formed of a single layer of silicon nitride film. In this case, when the thickness t IN1 of silicon nitride film 27j and the thickness t IN2 of oxide film 27k are each 100Å, the dielectric constants of the silicon nitride film and the silicon oxide film are ε N ≒7 and ε OX ≒3.8, respectively, and the driving capability ratio β will be 7/3.8≒1.84 (times) as large. If another material having a dielectric constant different from the silicon oxide film is used in place of silicon nitride film 27f, the state shown in Figs. 16A and 16B is attained by a thermal oxidation treatment in the process shown in Figs. 13A and 13B. More specifically, silicon oxide film 27g is formed on p type well 20 in the driver transistor region (Fig. 15B) by thermal oxidation treatment, while silicon oxide film 27h is formed on the surface of an insulating film 27fa in the access transistor region. Then, post-treatment the same as described above is performed to form access transistor Q 3 and driver transistor Q 2 shown in Figs. 16A and 16B. In the structure as illustrated in Figs. 17A and 17B, assuming that the thickness of insulating film 27fa is t a , relative dielectric constant is ε a , and the thickness of silicon oxide film 27h is t OX3 , each gate insulating film is expected to be formed satisfying the following expression: 1 t OX1 ε OX + t a ε a + t OX3 ε OX < ε OX t OX2 In the above-described embodiment, silicon oxide films and silicon nitride films are mainly employed for the gate insulating film, and a film having an insulating characteristic and a different dielectric constant can be used for the gate insulating film. Also in the above-described embodiment, although access transistor Q 3 and driver transistor Q 2 are described by way of illustration, the above-structure can be employed for access transistor Q 4 and driver transistor Q 1 . A ferroelectric film or a paraelectric film may be used for each gate insulating film. Such a ferroelectric film includes a PT (relative dielectric constant = from 200 to 400), a PZT (relative dielectric constant = from 300 to 2000) and a PLZT (relative dielectric constant = from 300 to 1500). The paraelectric film includes (Ba, Sr) TiO 3 (relative dielectric constant = from 250 to 500), SrTiO 3 (relative dielectric constant = from 200 to 250), and Ta 2 O 5 (relative dielectric constant = 22).

Claims: A semiconductor memory device, including a static memory cell having a pair of driver transistors (Q 1 , Q 2 ) of first type conductivity and a pair of load transistors of second type conductivity (Q 5 , Q 6 ) constituting a flip-flop circuit, and a pair of access transistors (Q 3 , Q 4 ), comprising: a semiconductor substrate (20) having a main surface; a first field effect transistor forming each of said driver transistors (Q 1 , Q 2 ) formed on the main surface of said semiconductor substrate; and a second field effect transistor forming each of said access transistors (Q 3 , Q 4 ) formed on the main surface of said semiconductor substrate, wherein said first field effect transistor includes, a first gate insulating film (27a, 27b; 27a, 27ba, 27d; 27g; 27j) formed on the main surface of said semiconductor substrate and having a first dielectric constant, and a first gate electrode (23, 24) formed on said first gate insulating film, and said second field effect transistor includes, a second gate insulating film (27c; 27e, 27f; 27e, 27fa, 27h; 27k) formed on the main surface of said semiconductor substrate and having a second dielectric constant, and a second gate electrode formed on said second gate insulating film, said first gate insulating film has a first thickness and said second gate insulating film has a second thickness, the ratio of the first dielectric constant to the first thickness is greater than the ratio of the second dielectric constant to the second thickness, one gate insulating film of said first and second gate insulating films includes a first insulating film (27c; 27g) and the other one of said first and second gate insulating films includes a second and a third insulating film (27a, 27b; 27a, 27ba; 27e, 27f; 27e, 27fa), the dielectric constant of said second insulating film being different from that of said third insulating film. A semiconductor memory device as recited in claim 1, wherein said first and said second insulating film (27c, 27a ; 27g, 27e) each include a silicon oxide film, and said third insulating film (27b) includes a silicon nitride film. A semiconductor memory device as recited in claim 1, wherein said other one gate insulating film includes said second insulating film (27a, 27e), said third insulating film (27ba, 27fa) having a dielectric constant different from said second insulating film, and a fourth insulating film (27d, 27h) having a dielectric constant different from said third insulating film. A semiconductor memory device as recited in claim 3, wherein said first, second and fourth insulating films (27c, 27g; 27a, 27e; 27d, 27h) each include a silicon oxide film. A method of manufacturing a semiconductor memory device including a static memory cell having a pair of driver transistors of first type conductivity (Q 1 , Q 2 ) and a pair of load transistors of second type conductivity (Q 5 , Q 6 ) constituting a flipflop circuit, and a pair of access transistors (Q 3 , Q 4 ) comprising the steps of: forming a first gate insulating film (27a, 27b; 27a, 27ba, 27d; 27g; 27j;) having a first dielectric constant on a main surface of a semiconductor substrate (20); forming a second gate insulating film (27c; 27e, 27f; 27e, 27fa, 27h; 27k) having a second dielectric constant smaller than the first dielectric constant on said main surface of said semiconductor substrate; forming a first gate electrode (23, 24) on said first gate insulating film; and forming a second gate electrode (21, 22) on said second gate insulating film, a first field effect transistor forming each of the driver transistors thus being formed to include said first gate insulating film and said first gate electrode, and a second field effect transistor forming each of said access transistors being formed to include said second gate insulating film and said second gate electrode, characterized in that said first gate insulating film is formed with a first thickness and said second gate insulating film is formed with a second thickness such that the ratio of the first dielectric constant to the first thickness is greater than the ratio of the second dielectric constant to the second thickness, and one gate insulating film of said first and second gate insulating films is formed such that it includes a first insulating film (27c; 27g) and the other one of said first and second gate insulating films is formed such that it includes a second and a third insulating film (27a, 27b; 27a, 27ba; 27e, 27f; 27e, 27fa), the dielectric constant of said second insulating film being different from that of said third insulating film.

Inventors: KOHNO YOSHIO, KURIYAMA HIROTADA, MAKI YUKIO, KOHNO, YOSHIO, KURIYAMA, HIROTADA, MAKI, YUKIO, KOHNO, YOSHIO, C/O MITSUBISHI DENKI K.K., KURIYAMA, HIROTADA, C/O MITSUBISHI DENKI K.K., MAKI, YUKIO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21, H01L23