Synchronization circuit for subcarrier signal

Abstract: A synchronization adder circuit for digital data communication is provided. This circuit includes an A/D converter, a waveform-shaping circuit, a square circuit, a low-pass filter, and an adder. The A/D converter samples at given sampling points in time per sampling cycle a received signal transmitted through a plurality of subcarriers to digitize sampled values to provide digital signals. The waveform-shaping circuit then waveform-shapes the digital signals from said A/D converter without decomposing them with respect to each subcarrier. The square circuit squares the output signals from the waveform-shaping circuit. The low-pass filter removes a given high-frequency component from output signals from the square circuit. The adder adds values of output signals from the low-pass filter at each sampling point for preselected sampling cycles to determine the samples suitable for reproduction of original data.

Description: BACKGROUND OF THE INVENTION 1 Technical Field of the Invention The present invention relates generally to a synchronization adder circuit which may be employed in a receiver of a digital communication system to synchronously add the power of sampled received signals, and more particularly to such a synchronization adder circuit having an improved compact structure. 2 Background Art In a known digital communication system, a receiver samples signal levels of a received signal at time intervals corresponding to transmission intervals at which a transmitter transmits symbols (1, 0), and compares them with a threshold value to reproduce original symbols. For transmission of digital data in a narrow band, the Nyquist characteristic is generally used. The same filter having the root Nyquist properties is usually employed both in transmitter and receiver. In such digital transmission, the sampling timing where a symbol is sampled from a received signal can be determined based on a maximum point of the envelope of the received signal unless a limiter amplifier is used as a receiver amplifier. The receiver digitizes the received signal at a sampling frequency that is an integral multiple (N) of a symbol-clock frequency, synchronously adds a square mean of samples at Nth sample points in time, and then identifies the samples at the Nth sample points having a maximum square means as indicating transmitted symbols. In order to enhancing the communication efficiency, known digital communication usually uses a plurality of subcarriers whose carrier frequencies are gradually shifted from the center frequency for transmitting a great deal of data. It is possible to improve the detection ability of symbol-timing (i.e., the symbol-clock frequency) by using the sum of the envelopes of the subcarriers. Fig. 5 shows a conventional synchronization adder circuit which includes generally A/D converters 21 and 22, frequency converters 31, 32, 33, and 34, waveform-shaping filters 51, 52, 53, 54, 55, 56, 57, and 58, square circuits 71, 72, 73, 74, 75, 76, 77, and 78, an adder 81, an adder circuit 82, a memory 83, and a discrimination point detecting circuit 84. The A/D converter 21 digitizes the same phase component 11 (I signal) of a received signal on each subcarrier at a sampling frequency of N times a symbol-clock frequency. The A/D converter 22 digitizes at the same sampling frequency an orthogonal component 12 (Q signal) of the received signal on each subcarrier. The frequency converters 31 to 34 frequency-convert the digital signals 23 and 24 on each subcarrier outputted from the A/D converters 21 and 22 to have their central frequencies agree with one another. The waveform-shaping filters 51 to 58 waveform-shape with the same filtering properties the I and Q signals on each subcarrier whose center frequencies have agreed with each other. The square circuits 71 to 78 square the waveform-shaped signals 61 to 68, respectively. The adder 81 forms the sum of outputs from the square circuits 71 to 78. The adder circuit 82 adds an output value from the adder 81 to the sum of the outputs from the square circuits 71 to 78 derived at a previous corresponding sampling point which, in turn, is stored in a given location, one for each sampling point, of the memory 83. Note that the synchronization adder circuit shown in Fig. 4 receives data transmitted on four subcarriers and an A/D conversion is made seven times (N = 7) per sampling cycle. In operation, data transmitted on four subcarriers is separated into the I and Q signals by means of orthogonal detection which are, in turn, inputted into the A/D converters 21 and 22 wherein they are digitized at a sampling frequency of seven times the symbol-clock frequency. Subsequently, the digitized I and Q signals are inputted into the frequency converters 31 to 34. The four subcarriers have carrier frequencies which are shifted from the center frequency by -3Δω, -Δω, Δω, and 3Δω, respectively. Each frequency converter 31 to 34 is thus arranged to frequency-converts the I and Q signals to have the center frequencies thereof coincide with one another (0Hz) for taking a corresponding subcarrier out of the I and Q signals. Figs. 6(a) and 6(b) show the frequency conversion in the frequency converters. For example, a central frequency offset by Δω, as shown in Fig. 6(a), is shifted by +Δω into a central frequency of zero shown in Fig. 6(b). The signals 41 to 48 processed by the frequency converters 31 to 34 are inputted into the waveform-shaping circuits 51 to 58. These waveform-shaping circuits are designed to extract, as shown in Fig. 6(c), a signal in a frequency range defined by the same width across the center frequency. The outputs from the waveform-shaping circuits 51 to 58 are squared in the square circuits 71 to 78 to derive the envelopes thereof. The outputs of the square circuits 71 to 78 are then added in the adder 81 to form the sum of the envelopes of the four subcarriers. A value provided by the adder 81 is added in the adder circuit 82 to a value already stored in a corresponding memory location of the memory 83. The memory 83 has seven memory locations each storing a total value of samples derived at corresponding sampling points in past sampling cycles. For example, when an instantaneous value of the adder 81 is derived at the second sampling point, the sum of samples obtained at the second sampling points in previous sampling cycles is first read out of the second memory location of the memory 83 and then is added to the value currently derived by the adder 81 which, in turn, is stored in the second memory location of the memory 82 again. The discrimination point detecting circuit 84 detects in the memory 83 a maximum total value of the samples extracted at individual sampling points for given sampling cycles, and identifies the samples having the maximum total value as optimum samples for reproduction of symbols. The above prior art synchronization adder circuit, however, encounters the drawback in that in order to derive the envelopes of four subcarriers, it is necessary to perform frequency-conversion four times and filtering process eight times, as discussed above. In other words, the frequency conversions of a number corresponding to the number of subcarriers and the filtering processes of twice the number of subcarriers are required. This results in bulky hardware of the circuit. Alternatively, in the case where the above variety of operations are executed in software, it becomes difficult to perform such operations in real time. Document JP-A-61 45658 discloses a timing phase control system in which two low-pass filtered orthogonal components of a received signal obtained from respective low-pass filters are subjected to synchronizing detection, In particular, band pass filters are used to extract a timing component from the filtered outputs of the low-pass filters. Furthermore, an adder circuit is provided for obtaining sums of the squared timing components to be subtracted in a subtractor, wherein the timing is extracted by shifting a sample point of a received signal on the basis of the obtained difference between two subsequent sampling values, Thus, synchronization is based on a shift of a sample point at the input side and not on an addition of subsequent samples of an envelope signal. It is an object of the present invention to provide a synchronization adder circuit having a reduced complexity. This object is achieved by a synchronization adder circuit as claimed in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given hereinbelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiment but are for explanation and understanding only. In the drawings: Fig. 1 is a circuit diagram which shows a synchronisation adder circuit according to the present invention; Fig. 2(a) shows frequency characteristics of four subcarriers before they are inputted to frequency converters; Fig. 2(b) shows frequency characteristics of four subcarriers after they have passed through waveform-shaping circuits; Fig. 2(c) shows frequency characteristics of output signals after they have passed through an adder; Fig. 2(d) shows frequency characteristics of a signal processed by a low-pass filter; Fig. 3 is a circuit diagram which shows a structure of a synthetic waveform-shaping filter employed in a synchronization adder circuit of the invention; Figs. 4(a), 4(b), and 4(c) are illustrations which show frequency characteristics when determining filter coefficients of a synthetic waveform-shaping filter of the invention; Fig. 5 is a circuit diagram which shows a conventional synchronization adder circuit; Figs. 6(a) shows frequency characteristics of four subcarriers before they are inputted to frequency converters; Fig. 6(b) shows frequency characteristics of four subcarriers after having been modulated in frequency through frequency converters; and Fig. 6(c) show frequency characteristics derived by a waveform-shaping circuits. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, particularly to Fig. 1, there is shown a synchronization adder circuit 100 according to the present invention. The adder circuit 100 includes generally A/D converters 21 and 22, synthetic waveform-shaping filters 35 and 36, square circuits 37 and 38, an adder 39, a low-pass filter (LPF) 50, an adder circuit 82, a memory 83, and a discrimination point detecting circuit 84. The A/D converter 21 digitizes the same phase component 11 (I signal) of a received signal on each subcarrier at a sampling frequency of several times a symbol-clock frequency. The A/D converter 22 digitizes at the same sampling frequency an orthogonal component 12 (Q signal) of the received signal of each subcarrier. The synthetic waveform-shaping filters 35 and 36 are designed to waveform-shape the I and Q signals 11 and 12 without modifying in frequency the subcarriers. The square circuits 37 and 38 square the outputs from the synthetic waveform-shaping filters 35 and 36, respectively. The adder 39 forms the sum of the outputs of the square circuits 37 and 38. The LPF 50 removes high-frequency components from the squared signal outputted from the adder 39. The adder circuit 82 adds an output value from the LFP 50 to a corresponding total value stored in the memory 83, as discussed in the introductory part of this specification. The memory 83 has memory locations each storing therein a total value of samples derived at corresponding sampling points in time. The discrimination point detecting circuit 84 looks up a maximum value of the total values stored in the memory 83 to determine samples to be reproduced as original symbols. To the A/D converters 21 and 22, the same phase components 11 and the orthogonal components 12 of received signals carried by four subcarriers, as shown in Fig. 2(a), are inputted. The A/D converters 21 and 22 then digitize the input signals at a sampling rate that is an integral multiple (N) of a symbol-clock rate (i.e., symbol-clock frequency) to provide digital signals 23 and 24, respectively. The synthetic waveform-shaping filters 35 and 36 each have a function of combining respective filtering effects, as shown by squares in Fig. 2(a), of typical baseband waveform-shaping filters each frequency-converting the digital signals 23 and 24 according to a frequency shift from a center frequency of each subcarrier, and are designed to waveform-shape the subcarriers without decomposing them to provide a signal as shown in Fig. 2(b). Each of the synthetic waveform-shaping filter 35 and 36, as shown in Fig. 3, includes delay elements 90 to 93, multipliers 94 to 98 having filter coefficients α(1) to α(5), and an adder 99, and is provided by setting a filter coefficient of a low-pass wave filter in the following manner. A filter coefficient α(k) (k = 1, 2, ······ N) of a low-pass wave filter shown in Fig. 4(a) is first modified according to a relation below to establish a filter shown in Fig. 4(b) having a filter coefficient α 1 (k). α 1 (k) = α(k) cos(ω · T · k) where T denotes a time interval of the delay element, ω is the central frequency, and k is a constant corresponding to each of the suffixes of the filter coefficients α 1 to α 5 of the multipliers 94 to 98. Next, the filter coefficient α 1 (k) of the filter shown in Fig. 4(b) is further modified according to an equation below to derive a filter coefficient α 2 (k) which provides filtering properties shown in Fig. 4(c). α 2 (k) = α 1 (k) cos(2ω · T · k) In the above manner, the synthetic waveform-shaping filter 35 and 36 are each designed to have passbands whose central frequencies correspond to the central frequencies of the subcarriers, receptively. Usually, the selection of a filter coefficient and the number of taps (i.e., the number of delay elements and multipliers) determine the performance of a filter. The output signals from the synthetic waveform-shaping filters 35 and 36 are squared by the square circuits 37 and 38 which are, in turn, added in the adder 39. The square operations of the square circuits 37 and 38 cause an output signal from the adder 39, as shown in Fig. 2(c), to include, in addition to an envelope component, unwanted components twice, four times, and six times the envelope component. These components are then removed by a filtering function, as shown by a square in Fig. 2(c), of the low-pass filter 50, so that only a signal having the envelope shown in Fig. 2(d) is inputted to the adder circuit 82. The adder circuits 82 then adds the output from the low-pass filter 50 to a corresponding total value, derived in previous sampling cycles, stored in the memory 83. The discrimination point detecting circuit 84 looks up a maximum value of the total values stored in the memory 83 which are derived at individual sampling points over past sampling cycles. The samples showing the maximum value are identified as optimum samples for reproduction of original symbols. The operation of the synchronization adder circuit until the envelope signal is obtained, will be discussed below with reference to mathematical equations. An input signal A to the synchronization adder circuit transmitted by four subcarriers can be expressed according to the equation (1) below. The suffixes "1, 2, 3, 4" indicate the numbers of subcarriers 1, 2, 3, 4 respectively. The equation (1) is derived based on the relations (2), (3), (4), and (5) below. A = a 1 e j1 e -j3Δωt + a 2 e j2 e -jΔωt + a 3 e j3 e jΔωt + a 4 e j4 e j3Δωt i 1 + jq 1 = a 1 e j1 i 2 + jq 2 = a 2 e j2 i 3 + jq 3 = a 3 e j3 i 24 +jq 4 = a 4 e j4 Taking into consideration the frequency offset ω off of the input signal to the synchronization adder circuit, the input signal may also be presented by the following equation. A' = A × e jωofft The above signal A' is waveform-shaped in the synthetic waveform-shaping filters 35 and 36, squared by the square circuits 37 and 38, and then inputted to the adder 39. The output from the adder 39 can be expressed by |A' 2 | = A' × A'* = A e jωofft × A*e -jωofft = (a 1 e j1 e -j3Δωt + a 2 e j2 e -jΔωt + a 3 e j3 e jΔωt + a 4 e j4 e j3Δωt ) × (a 1 e -j1 e j3Δωt + a 2 e -j2 e jΔωt + a 3 e -j3 e -jΔωt + a 4 e -j4 e -j3Δωt ) = a 1 2 + a 2 2 + a 3 2 + a 4 2 + a 1 a 2 e -j2Δωt e j(1-2) + a 1 a 3 e -j4Δωt e j(1-3) + a 1 a 4 e -j6Δωt e j(1-4) + a 2 a 1 e j2Δωt e j(2-1) + a 2 a 3 e -j2Δωt e j(2-3) + a 2 a 4 e -j4Δωt e j(2-4) + a 3 a 1 e j4Δωt e j(3-1) + a 3 a 2 e j2Δωt e j(3-2) + a 3 a 4 e -j2Δωt e j(3-4) + a 4 a 1 e j6Δωt e j(4-1) + a 4 a 2 e j4Δωt e j(4-2) + a 4 a 3 e j2Δωt e j(4-3) = (i 1 2 + q 1 2 ) + (i 2 2 + q 2 2 ) + (i 3 2 + q 3 2 ) + (i 4 2 + q 4 2 ) + {(i 1 i 2 + q 1 q 2 ) + (i 2 i 3 + q 2 q 3 ) + (i 3 i 4 + q 3 q 4 )}cos(2Δωt) + {(i 1 i 3 + q 1 q 3 ) + (i 2 i 4 + q 2 q 4 )}cos(4Δωt) + (i 1 i 4 + q 1 q 4 )}cos(6Δωt) As apparent from the above equation (7), the output from the adder 39 includes a component of the envelope "(i 1 2 + q 1 2 ) + (i 2 2 + q 2 2 ) + (i 3 2 + q 3 2 ) + (i 4 2 + q 4 2 ) and high-frequency components of twice, four time, and six times the envelope component. These high-frequency components are removed by the low-pass filter 50. Only envelope data, as defined by the following equation (8), is thus provided to the adder circuit 82. (i 1 2 + q 1 2 ) + (i 2 2 + q 2 2 ) + (i 3 2 + q 3 2 ) + (i 4 2 + q 4 2 ) In this manner, the envelope data is derived in the synchronization adder circuit of the invention using the two synthetic waveform-shaping filters, the square circuits squaring the outputs from the synthetic waveform-shaping filters, and the low-pass filter removing the high-frequency components produced through the square operation of the square circuits. While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding thereof, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modification to the shown embodiments which can be embodied without departing from the principle of the invention as set forth in the appended claims. A synchronization adder circuit for digital data communication is provided. This circuit includes an A/D converter, a waveform-shaping circuit, a square circuit, a low-pass filter, and an adder. The A/D converter samples at given sampling points in time per sampling cycle a received signal transmitted through a plurality of subcarriers to digitize sampled values to provide digital signals. The waveform-shaping circuit then waveform-shapes the digital signals from said A/D converter without decomposing them with respect to each subcarrier. The square circuit squares the output signals from the waveform-shaping circuit. The low-pass filter removes a given high-frequency component from output signals from the square circuit. The adder adds values of output signals from the low-pass filter at each sampling point for preselected sampling cycles to determine the samples suitable for reproduction of original data.

Claims: A synchronization adder circuit comprising: a) A/D converter means (21, 22) for digitizing at given sampling points in time per sampling cycle an in-phase component (I) and a quadrature-phase component (Q) of a received signal transmitted on each of a plurality of subcarriers; b) waveform-shaping filter means (35, 36) for waveform-shaping the digitized in-phase component and quadrature-phase component of the received signal from said A/D converter means (21, 22) without decomposing it for every subcarrier, by combining respective filtering effects; c) square means (37, 38) for squaring the waveform-shaped in-phase component and quadrature-phase component from said waveform-shaping circuit means (35, 36) ; d) an adder circuit (39) for forming the sum of the squared in-phase component and quadrature-phase component; e) a low-pass filter (50) for removing a given frequency component from the sum of the squared in-phase component and quadrature-phase component to obtain an envelope signal; f) adder means (82) for adding values of the envelope signal from said low-pass filter (50) at each sampling point over preselected sampling cycles to determine respective total values at the sampling points; and g) a detecting circuit (84) for detecting a maximum value of said total values to identify the output signal values from said low-pass filter (50) at a specified sampling point representing said maximum value as samples for reproduction of data transmitted on the subcarriers. A synchronization adder circuit according to claim 1, wherein said waveform-shaping filter means includes a waveform-shaping filter (35, 36) having passbands whose central frequencies correspond to central frequencies of the subcarriers, respectively. A synchronization adder circuit according to claim 1, wherein: said A/D converter means comprises a first A/D converter (11) for digitizing the in-phase component (I) of the received signal transmitted on each subcarrier and a second A/D converter (22) for digitizing the quadrature-phase component (Q) of the received signal transmitted on each subcarrier; said waveform-shaping filter means comprises a first waveform-shaping filter (35) for waveform-shaping the digitized signal component from said first A/D converter means (21) and a second waveform-shaping filter (36) for waveform-shaping the digitized signal component from said second A/D converter means (22) ; said square means comprises a first square circuit (37) for squaring the waveform-shaped signal component from said first waveform-shaping filter (35) and a second square circuit (38) for squaring the waveform-shaped signal component from said second waveform-shaping filter (36) ; and said adder circuit (39) being arranged to form the sum of the squared signal components from said first and second square circuits (37, 38) and to supply the sum as said squared signal to said low-pass filter (50) . A synchronization adder circuit according to claim 3, wherein said first and second waveform-shaping filters (35, 36) each have passbands whose central frequencies correspond to central frequencies of the subcarriers, respectively.

Inventors: HIRAMATSU KATSUHIKO, INOGAI KAZUNORI, ISHIKAWA KIMIHIKO, HIRAMATSU, KATSUHIKO, INOGAI, KAZUNORI, ISHIKAWA, KIMIHIKO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: H04L5
IPC codes: H04L5, H04L7, H04J1, H04L27