Method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device

Abstract: A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.

Description: The present invention relates to a method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device, and to a row redundancy integrated circuitry actuating such method. Semiconductor memory devices are generally organized in a bidimensional array (memory matrix) wherein the single memory elements are located at the intersection of rows ("word lines") and columns ("bit lines") of the matrix: to access a given memory element, it is necessary to select the word line and the bit line at the intersection of which said memory element is located; to this purpose, the memory address bus is divided into row and column address signals, which are decoded independently. It is known that in the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that tile manufacturing process characteristics are usually pushed to limits. In order to avoid that the presence of a limited number of defective memory elements on many millions forces the rejection of the entire chip, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number of additional memory elements, commonly called "redundancy memory elements", to be used as a replacement of those elements that, during testing of the memory device, prove defective; the selection circuits, with which the integrated component must necessarily be provided, and which allow the above mentioned functional replacement of a defective memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry", while the set of redundancy memory elements and circuitry is defined for short as "redundancy". The redundancy circuitry comprises programmable non-volatile memory registers (redundancy registers) suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply. In practical implementations of redundancy in memory devices, both word lines and bit lines of redundancy memory elements are generally provided in the memory matrix; each redundancy word line or bit line is associated with a respective row or column redundancy register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected. As far as word lines are concerned, it has been recognized that the most frequent defect consists in short-circuits between adjacent word lines: this situation is easily detected during testing because when the selection of one of two short-circuited word lines is attempted, the potential of such word line cannot rise to the designed value, being linked by the short-circuit to the potential of the adjacent non-selected word line. When therefore during testing a defective word line is found, it is assumed that such word line is short-circuited with the adjacent word line (the one which, in the scanning sequence, follows the defective word line), and both said word lines are replaced by two respective redundancy word lines; from then on, the two defective word lines will never be selected. Since defective word lines always come in pairs, it is known to design the row redundancy registers in such a way as to store each a pair of row addresses, and to be each one associated with a respective pair of redundancy word lines: into each row redundancy register can therefore be programmed the addresses of two adjacent short-circuited word lines. Each row redundancy register comprises programmable non-volatile memory cells wherein the addresses of two adjacent defective word lines can be programmed; each one of such memory cells must comprise at least one programmable non-volatile memory element, such as a fuse or a floating-gate MOSFET, a load circuit for reading the information stored therein, and a program load circuit for the programming of the memory element according to the logic state of a respective address bit in the row address signal set (row address bus). In memory devices the association between the word lines in the memory matrix and the respective selection signals generated by the row address decoding and selection circuitry is generally such that adjacent word lines have addresses which only differ in one bit; since however such bit can be anyone of the bits constituting the row address signal set, it follows that in order to always be able to replace any two adjacent short-circuited word lines, each row redundancy register should store two full row addresses: this means that each row redundancy register must comprise a number of memory cells equal to twice the number of row address bits. Since each memory cell occupies a significant chip area, this would lead to an excessive increase in the overall chip size, so that the overall process yield is decreased instead of increased. This is why a compromise is generally reached between the repairability rate for defective word line pairs and the increase in chip size; in practice, designers give up the possibility to replace any two adjacent short-circuited word lines, limiting such replacement to adjacent word lines whose addresses only differ in one (or more) bit belonging to a given subset of the whole row address signal set: if for example the row address signal set comprises m address bits, it can be thought of as being the sum of two subsets n and q such that n contains the most significant row address bits, while q contains the least significant row address bits; limiting the replacement of defective word line pairs to take place for adjacent word lines having addresses differing in one (or more) bits of the subset q, it is sufficient to store in a given row redundancy register the full row address m for one of the pair of adjacent word lines, and the subset q for the other word line of the pair. This means that each row redundancy register must be made up of (m+q) memory cells, instead of 2m; the impact on the repairability rate can be appreciated by considering that the probability of having a short-circuit defect between two adjacent word lines with addresses differing in one (or more) bit in the subset n is 1/2 q . In the European Patent No. EP A-0 655 743 a program load circuit for the programming of a memory cell in a non-volatile memory register (such as a row redundancy register) is described thanks to which the datum to be programmed into the memory element of the memory cell can be directly supplied by one of the address signal lines already present in the memory device and supplying the decoding circuitry, without the need of generating additional signals. In view of the state of the art described, the main object of the present invention is to provide a method for programming redundancy registers in a row redundancy integrated circuitry, which makes use as far as possible of signal lines already existent in the memory device for different purposes, without the need of generating on-chip dedicated signals and thus minimizing the memory device chip size. Another object of the present invention is to realize a row redundancy integrated circuitry actuating the abovementioned method. According to the present invention, as defined in the independent claims such main object is attained by means of a method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of a matrix of memory elements, the row redundancy circuitry comprising a plurality of non-volatile memory registers each one associated with a respective pair of redundancy row of redundancy memory elements and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows, characterized in that each non-volatile memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals, and in that it provides for: a) applying to said row address signals the address of a first defective row of said pair of adjacent defective rows; b) activating one of said selection signals for selecting the non-volatile register which is to be programmed; c) applying to a further signal of the set of column address signals a first logic level to select for programming, in the selected non-volatile memory register, a first subset of the two subsets of memory cells; d) enabling the programming of the address of the first defective row of the pair of adjacent defective rows into said first subset of memory cells; e) applying to at least a subset of said row address signals the address of a second defective row of said pair of adjacent defective rows; f) applying to said further signal of the set of column address signals a second, opposite logic level to select for programming, in the selected non-volatile memory register, at least a group of memory cells of the second subset of the two subsets of memory cells; g) enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset of memory cells. According to the present invention, the other object is attained by means of a row redundancy integrated circuitry for a semiconductor memory device, characterized in that it comprises first means for supplying each non-volatile memory register with row address signals which when one of the non-volatile memory register is to be programmed carry the address of the defective rows, and second means for supplying each non-volatile memory register with one respective column address signal which is activated to select the respective associated non-volatile memory register for programming, and in that it further comprises circuit means supplied with a further column address signal for activating, according to the logic state of said further column address signal, either one or the other of two control signals supplied to the non-volatile memory registers for selecting the subset of memory cells of the selected non-volatile memory register into which the data carried by the row address signals are to be programmed. Thanks to the present invention, programming of the row redundancy registers can be carried out by using already existing signals, i.e. address signals normally used to address the memory elements when reading the memory device. The features of the present invention will be made more evident by the following detailed description of a particular embodiment, illustrated as a non-limiting example in the annexed drawings, wherein: Figure 1 is a schematic electrical diagram of a row redundancy circuitry according to the present invention; Figure 2 is a schematic electrical diagram of a redundancy register for said row redundancy circuitry; Figure 3 is a schematic electrical diagram of a programmable non-volatile memory cell of the redundancy register of Figure 2; Figure 4 is a schematic electrical diagram of a circuit for generating control signals for the redundancy circuitry; Figure 5 is a schematic electrical diagram of another embodiment of the circuit of Figure 4; Figure 6 is a schematic electrical diagram of a part of a matrix of memory elements of a semiconductor memory device showing a pair of defective word lines and a pair of redundancy word lines; Figure 7 is a schematic electrical diagram of a memory matrix architecture. As already told, semiconductor memory devices comprise a matrix of memory elements M (Fig.s 6 and 7) located at the intersection of rows (word lines) WL1-WLn and columns (bit lines) BL1-BLm, and are further provided with redundancy rows RWL0-RWL7 of redundancy memory elements RM. As shown in Figure 1, a row redundancy integrated circuitry according to the invention comprises a plurality of redundancy registers RR1-RR4 (four in the shown example), each one associated with a respective pair of redundancy word lines RWL0,RWL1-RWL6,RWL7 (Fig. 7). In the following, the memory device is initially supposed to have a memory matrix architecture of the type comprising only one of the blocks indicated by HM1 or HM2 in Figure 7; accordingly, the signal HMSS in dash-and-dot line should not be considered. In the last part of the specification, a memory matrix architecture of the type comprising both the blocks HM1 and HM2 in Figure 7 is taken into account. As further shown in Figure 2, each redundancy register RR1-RR4 comprises a first group 1 of programmable non-volatile memory cells MC4-MC9 (six in the shown example) and two second groups 2 and 2' of programmable non-volatile memory cells MC0-MC3 (four in the example). The memory cells MC4-MC9 of the first group 1 of each redundancy register RR1-RR4 are each one supplied with a respective row address signal R4-R9 taken from a bus RABUS' containing the signals corresponding to the most significant row address bits; the signals of the bus RABUS' are a first subset of a set of row address signals grouped together to form a row address bus RABUS which is generated in a per-se known way by a row address input buffer circuitry RABUF and also supplies in a per-se known way a row decoding circuitry RADEC for the selection of the word lines WL1-WLn of the memory matrix (Figs. 1 and 7). Each memory cell MC4-MC9 has an output signal MCS4-MCS9, representing the memory cell status, which is supplied, together with the respective row address signal R4-R9, to a respective comparator 3 whose output signal CMP4-CMP9 is activated only when the memory cell status coincides with the current state of the respective row address signal; since the comparator 3 deals with digital signals, it can be simply represented by an AND gate. All the signals CMP4-CMP9 supply a first-level redundancy word line selection circuit 4 which, when all the signals CMP4-CMP9 are activated (i.e. when the current state of the most significant row address signals R4-R9 coincides with the logic state stored in the memory cells MC4-MC9 of the first group 1) activates a respective first-level redundancy word line selection signal FLRS. Depending on the logic level which corresponds to the activated state of the signals CMP4-CMP9 and of the signal FLRS, the circuit 4 can be represented by an AND gate (CMP4-CMP9="1" and FLRS="1" when activated), by an OR gate (CMP4-CMP9="0" and FLRS="0" when activated), by a NAND gate (CMP4-CMP9="1" and FLRS="0" when activated) or by a NOR gate (CMP4-CMP9="0" and FLRS="1" when activated); further, as it is known to anyone skilled in the art, the circuit 4 can be represented by a tree of few-input logic gates instead of a single six-input logic gate, to increase switching speed. Each memory cell MC0-MC3 in the two second groups 2 and 2' is supplied with a respective row address signal R0-R3 taken from a bus RABUS"; the signals of the bus RABUS" are a second subset of the set of row address signals of the bus RABUS and represent the signals corresponding to the least significant row address bits; similarly to the memory cells MC4-MC9 in the first group 1, each memory cell MC0-MC3 in the groups 2 and 2' has an output signal MCS0-MCS3, representing the memory cell status, which is supplied, together with the respective row address signal R0-R3, to a respective comparator 3 whose output signal CMP0-CMP3 is activated only when the memory cell status coincides with the current state of the respective row address signal. Each one of the two groups of signals CMP0-CMP3 supplies a respective second-level redundancy word line selection circuit 5 and 5' which, when all the signals CMP0-CMP3 of the respective group are activated (i.e. when the current state of the least significant row address signals R0-R3 coincides with the logic state stored in the memory cells MC0-MC3 of the respective second group 2 and 2') activates a respective second-level redundancy word line selection signal SLRS and SLRS'. Practical implementation considerations analogous to those made for the circuit 4 hold for the two circuits 5 and 5'. Each one of the two second-level selection signals SLRS and SLRS' is supplied, together with the first-level selection signal FLRS, to a respective redundancy word line selection circuit 6 and 6' whose output RSODD and RSEVEN is activated when both the first-level selection signal FLRS and the respective second-level selection signal SLRS and SLRS' are activated. The signals RSEVEN and RSODD are connected through a respective switch S1-S4 and S1'-S4' to a respective redundancy word line selection signal RWL0S,RWL2S,RWL4S,RWL6S and RWL1S,RWL3S,RWL5S,RWL7S for the selection of the redundancy word lines (said switches S1-S4 and S1'-S4' are controlled by a control signal CNT, for example activated by an internal control circuitry of the memory device in certain test conditions: the activation of the signal CNT determines the switches to connect the redundancy word line selection signals RWL0S-RWL7S to a single signal line EXT, for example directly connected to a data input/output pad of the memory device, to simultaneously activate all the redundancy word lines). The activation of the signal RSEVEN in one of the redundancy registers RR1-RR4 determines the selection of the even-indexed redundancy word line RWL0,RWL2,RWL4,RWL6 of the associated pair RWL0,RWL1-RWL6,RWL7, while the activation of the signal RSODD determines the selection of the odd-indexed redundancy word line RWL1,RWL3,RWL5,RWL7. Further, the activation of the signal RSEVEN or RSODD prevents the defective word line whose address is stored in the memory cells of the first group 1 and of the second group 2 or 2' of memory cells of the respective redundancy register from being selected. As described in the European Patent No. EP-A-0 657 814, it is necessary to prevent ambiguous word line selection to occur: since in fact even non-programmed redundancy registers, associated with unused pairs of redundancy word lines, store a particular logic state which belongs to the set of all the possible states for the row address signals R0-R9, when a row address is supplied to the memory device which coincides with said particular logic state the pairs of redundancy word lines associated with all the non-programmed redundancy registers would be simultaneously selected. This is clearly unacceptable, and the selection of the redundancy word lines must be inhibited whenever a row address is supplied to the memory device which coincides with said particular logic state (which is well known, since it corresponds to the non-programmed or virgin condition of the memory cells MC0-MC9). To this purpose, a combinatorial circuit 7 (Fig. 1) is supplied with the row address bus RABUS to recognize if the current state of the row address signals R0-R9 coincides with said particular logic state, and if this occurs, the circuit 7 activates an inhibition signal DIS which is supplied to the first-level redundancy word line selection circuits 4 in all the redundancy registers RR1-RR4 (Fig. 2). This prevents the first-level selection signals FLRS from being activated even if one or more redundancy registers RR1-RR4 exist which has not been programmed, and which therefore stores in the memory cells MC0-MC9 said particular logic state. The combinatorial circuit 7 can be an element of the row address decoding circuitry RADEC. As described in the European Patent No. EP-A-0 655 743, and as shown in Figure 5, each programmable non-volatile memory cell MC0-MC9 comprises a programmable non-volatile memory element, for example a floating gate MOSFET M1 with source connected to a ground voltage GND and control gate connected to a supply voltage VG which can be switched by a control circuitry (not shown) internal to the memory device from a reading voltage value (typically of 5 V) to a programming high-voltage value (of about 12 V); the drain of M1 is connected to a reading load circuit LC whose output is represented by the signal MCS0-MCS9; the drain of M1 is also connected to a programming load circuit substantially represented by a MOSFET M2 whose drain is connected to a programming data line PDL. In each redundancy register RR1-RR4, the programming data lines PDL of the memory cells MC4-MC9 of the first group 1 are each connected to a respective one of the most significant row address signals R4-R9, while the programming data lines PDL of the memory cells MC0-MC3 of the two second groups 2 and 2' are each connected to a respective one of the least significant row address signals R0-R3. In each redundancy register RR1-RR4, the gate of the MOSFET M2 in the memory cells MC4-MC9 of the first group 1 and in the memory cells MC0-MC3 of the group 2 is connected to an output signal PEVEN of a first ground/high-voltage switch 8 (Figure 2), while the gate of the MOSFET M2 in the memory cells MC0-MC3 of the group 2' is connected to an output signal PODD of a second ground/high-voltage switch 8'. A first control signal EVEN commonly supplies all the switches 8, while a second control signal ODD commonly supplies all the switches 8'; further, the switches 8 and 8' in each redundancy register RR1-RR4 are commonly supplied with a respective column address signal C0-C3 taken from a bus CABUS' which contains a subset of a set of column address signals grouped together in a column address bus CABUS; said column address bus CABUS is generated in a per-se known way by a column address input buffer circuitry CABUF and also supplies, in a per-se known way, a column address decoding circuitry CADEC for the selection of bit lines of the memory matrix (Figs. 1 and 7). An example of circuit for generating the two control signals EVEN and ODD is shown in Figure 3, and comprises a first NOR gate 9 supplied with a control signal RRPGEN activated by the control circuitry internal to the memory device, and with a further column address signal C4 taken from the bus CABUS'; an output of the NOR gate 9 represents the control signal EVEN, and is supplied to a second NOR gate 10 which is also supplied with the signal RRPGEN, and whose output represents the control signal ODD; in this example, it is assumed that the activated state for the two control signals EVEN and ODD corresponds to the "1" logic state, while the signal RRPGEN is activated by driving it to the "0" logic state; the column address signal C4 is used to selectively activate either the signal EVEN or the signal ODD when RRPGEN is activated (C4="0" activates the signal EVEN, while C4="1" activates the signal ODD). Other embodiments are obviously possible, depending on the logic level corresponding to the activated state of the signal RRPGEN; the essential requirement is that when the signal RRPGEN is not activated, both of the control signals EVEN and ODD are also not activated, independently from the logic state of the column address signals C4, while when RRPGEN is activated, either EVEN or ODD is activated depending on the logic state of C4. During the memory device testing, different word lines WL1-WLn (Fig. 7) of the memory matrix are addressed sequentially, starting for example from the word line WL1. Let's suppose that a word line WLi (Fig. 6) proves defective: as previously described, it is assumed that a defect D exists such that the word line WLi is short-circuited with the adjacent word line WLi+1 which, in the testing scanning sequence, follows WLi; this means that not only WLi, but also WLi+1 is defective, and the word line pair WLi,WLi+1 must be replaced by a pair of redundancy word lines, for example by the pair RWL2,RWL3. To this purpose, the addresses of the word lines WLi and WLi+1 must be programmed into the redundancy register RR2 which is associated with RWL2 and RWL3. According to the method of the present invention, the memory device is supplied with a row address corresponding to that of the defective word line WLi, so that the row address bus RABUS carries one of the two addresses to be programmed into the redundancy register RR2; the memory device is further supplied with a column address such that the column address signals C0 and C2 to C4 are logic "0"s, while C1 is a logic "1", to selectively program RR2 among all the redundancy registers RR1-RR4. When the internal control circuitry drives the signal RRPGEN to the "0" logic state, since C4="0", the signal EVEN is activated (i.e. driven to "1"), while the signal ODD is kept to "0". Since in RR2 the switch 8 has both the inputs EVEN and C1 in the "1" logic state, its output PEVEN is driven to the programming high-voltage value, while the switch 8', having just one input (C1) in the "1" logic state and the other input (ODD) in the "0" logic state, keeps its output PODD at the ground voltage level. The signal PEVEN turns on the MOSFET M2 in the memory cells MC4-MC9 of the group 1 and in the memory cells MC0-MC3 of the group 2 of the redundancy register RR2; simultaneously to the activation of RRPGEN, the internal control circuitry switches the gate voltage VG of the floating-gate MOSFET M1 of all the memory cells to the programming high-voltage value. In the memory cells wherein the MOSFET M2 is on, the floating-gate transistor M1 will therefore have a programming high-voltage value applied to its gate, and a drain voltage depending on the logic state of the respective programming data line PDL: if PDL is a logic "1", electrons will be injected into the floating gate of M1, causing a threshold voltage shift, while if PDL is a logic "0", no injection of electrons takes place, and no threshold voltage shift affects M1. The load circuit LC is designed to detect such threshold voltage shifts. In all the memory cells wherein M2 is off, the drain of M1 is left floating, and no electron injection takes place; M1 will therefore not change its programming state. The most significant row address signals R4-R9 of the address of WLi are thus programmed into the memory cells MC4-MC9 of the group 1 of RR2, and the least significant row address signals R0-R3 are programmed into the memory cells MC0-MC3 of the group 2 of RR2; this means that the defective word line WLi is redunded by the redundancy word line RWL2. After this step, the signal RRPGEN is deactivated, and the row address supplied to the memory device is changed into the address of the defective word line WLi+1. Since WLi+1 is adjacent to WLi, its address will differ from the address of WLi only in the least significant bits. For this reason, in order to replace WLi+1 with RWL3 it is not necessary to have the full address of WLi+1 stored in the redundancy register RR2, being sufficient to store only the least significant bits of such address. To this purpose, the memory device is supplied with a row address such that the row address signals R0-R3 carry the least significant part of the address of WLi+1; further, the column address supplied to the memory device is changed so that C4 is now a logic "1" (C0, C2 and C3 are still logic "0"s). When the signal RRPGEN is re-activated, the control signal ODD is driven to a logic "1", while the signal EVEN is kept to "0"; in this way the switch 8' drives its output PODD to the programming high-voltage, and the logic value of the row address signals R0-R3 is thus programmed into the memory cells MC0-MC3 of the group 2' of RR2. When the memory device is operated in reading condition, and the row address supplied to it coincides with the address of WLi, the memory cell status signals MCS4-MCS9 in RR2 coincide with the respective row address signals R4-R9, and the signals CMP4-CMP9 are activated; the same happens for the memory cells MC0-MC3 of the group 2 of RR2; since the first- and second-level redundancy row selection signals FLRS and SLRS in RR2 are activated, the signal RSEVEN is also activated, so that the redundancy word line RWL2 is selected instead of WLi. When differently the row address supplied to the memory device coincides with the address of WLi+1, in which the logic state of the most significant bits is identical to that of the address of WLi, the signals FLRS and SLRS' are activated, so that the redundancy word line RWL3 is selected instead of WLi+1. The pair of defective word lines WLi,WLi+1 is therefore functionally replaced by the pair of redundancy word lines RWL2,RWL3. It should be noted that the pair of adjacent short-circuited word lines WLi,WLi+1 can be replaced by the redundancy word line pair RWL2,RWL3 only if the addresses of WLi and WLi+1 differs in one or more bits belonging to their least significant part, represented by the row address signals R0-R3; this is due to the fact that each redundancy register RR1-RR4 comprises a unique group (the first group 1) of memory cells MC4-MC9, to store the most significant bits of the row address of a pair of word lines. Pairs of adjacent defective word lines with addresses differing in one or more bits belonging to their most significant part, represented by the row address signals R4-R9, cannot therefore be replaced by redundancy word line pairs. The impact on the repairability rate can be appreciated by considering that the probability of having a defect between two adjacent word lines with addresses differing in one or more bits in their most significant part is 1/16. Such a compromise allows to limit the number of memory cells required in each redundancy register to 6+4+4. It is obviously possible to increase the repairability rate, by decreasing the number of memory cells in the common first group 1, and increasing the number of memory cells in the two second groups 2 and 2', at the expense of an increase in the overall number of memory cells, and thus in the chip size: if for example the first group 1 of memory cells is made to comprise five memory cells, and each of the two second groups 2 and 2' five memory cells, the probability of having a non-repairable defect lower to 1/32, but the number of memory cells required for each redundancy register increases of one unity (5+5+5), which, given the four redundancy registers RR1-RR4 existent, means an overall increase of four memory cells. Figure 7 shows a particular memory matrix architecture which is sometimes used in memory devices: such architecture provides for splitting the memory matrix into two half-matrices HM1 and HM2. Each half-matrix is made up of an equal number of memory elements M located at the intersection of word lines WL1-WLn and bit lines BL1-BLm. Each logic configuration of row address signals determines the selection of a respective word line in each half-matrix; an extra address bit is required to select between the two half-matrices. Each half-matrix is further provided with a plurality of redundancy word line pairs RWL0,RWL1-RWL6,RWL7. Defective word line pairs in one half-matrix are replaced by redundancy word line pairs of the same half-matrix. A row redundancy circuitry for a memory device with such a memory matrix architecture is composed by two identical circuit parts, substantially identical to the row redundancy circuitry previously described. One of said two circuit parts is again shown in Figures 1 and 2, taking into account the signal HMSS in dash-and-dot line: such a signal represents a half-matrix selection signal, and can be regarded as an extra address signal used to select one or the other of the two half-matrices; the second part of the redundancy circuitry is not shown but is exactly identical to the first part, except from the fact that the signal HMSS is replaced by its logic complement. The row redundancy circuitry mentioned above allows to increase the repairability rate, since the replacement of a defective word line pair in a given half-matrix does not cause such replacement to occur also for the word line pair in the other half-matrix but having the same address. To this purpose, the signal HMSS supplies all the redundancy registers RR1-RR4; inside each redundancy register RR1-RR4, HMSS supplies the first-level redundancy word line selection circuit 4. When the signal HMSS is not activated, i.e. when the other half-matrix is addressed, the activation of the first-level selection signals FLRS is inhibited. This prevents that, if in the two half-matrixes two pairs of defective word lines with the same addresses exist, addressing the memory device with such defective row address causes the simultaneous selection of two redundancy word lines. Further, the generation of the two control signals EVEN and ODD in each part of the redundancy circuitry is submitted to the activation of the respective half-matrix selection signal. An example of circuit for the generation of the control signals EVEN and ODD for this embodiment is shown in Figure 4. Differently from the circuit of Figure 3 for the previous embodiment, the output signal of the NOR gate 9 is supplied, together with the signal HMSS, to a first NAND gate 11 whose output constitutes the control signal EVEN; similarly, the output of the NOR gate 10 is supplied, together with the signal HMSS, to a second NAND gate 12, whose output constitutes the signal ODD. A similar circuit will be provided in the other part of the redundancy circuitry, the signal HMSS being replaced by its logic complement. In this way, the activation of either one of the two control signals EVEN or ODD is submitted to the activation of the half-matrix selection signal HMSS. This is necessary during programming of the redundancy registers to select one out of two redundancy registers belonging to different parts of the row redundancy circuitry but supplied with the same column address signal C0-C3.

Claims: Method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of a matrix of memory elements, the row redundancy circuitry comprising a plurality of non-volatile memory registers (RR1-RR4) each one associated with a respective pair of redundancy row of redundancy memory elements and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows, characterized in that each of said plurality of non-volatile memory registers (RR1-RR4) is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS), and in that it provides for: a) applying to said row address signals (R0-R9) the address of a first defective row of said pair of adjacent defective rows; b) activating one of said selection signals (C0-C3) for selecting the non-volatile register (RR1-RR4) which is to be programmed; c) applying to a further signal (C4) of the set of column address signals (CABUS) a first logic level to select for programming, in the selected non-volatile memory register (RR1-RR4), a first subset (1,2) of the two subsets (1,2;1,2') of memory cells (MC0-MC9); d) enabling the programming of the address of the first defective row of the pair of adjacent defective rows into said first subset (1,2) of memory cells; e) applying to at least a subset (R0-R3) of said row address signals (R0-R9) the address of a second defective row of said pair of adjacent defective rows; f) applying to said further signal (C4) of the set of column address signals (CABUS) a second, opposite logic level to select for programming, in the selected non-volatile memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; g) enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells. Row redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of a matrix of memory elements, the row redundancy circuitry comprising a plurality of non-volatile memory registers (RR1-RR4) each one associated with a respective pair of redundancy rows of redundancy memory elements and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows, characterized in that it comprises first means (RABUS',RABUS") for supplying each of said plurality of non-volatile memory registers (RR1-RR4) with row address signals (R0-R9) which when one of the said plurality of non-volatile memory registers (RR1-RR4) is to be programmed carry the address of the defective rows, and second means (CABUS') for supplying each non-volatile memory register (RR1-RR4) with one respective column address signal (C0-C3) which is activated to select the respective associated non-volatile memory register (RR1-RR4) for programming, and in that it further comprises circuit means (9,10) supplied with a further column address signal (C4) for activating, according to the logic state of said further column address signal (C4), either one or the other of two control signals (EVEN,ODD) supplied to the non-volatile memory registers (RR1-RR4) for selecting the subset of memory cells (1,2;1,2') of the selected non-volatile memory register (RR1-RR4) into which the data carried by the row address signals (R0-R9) are to be programmed. Row redundancy integrated circuitry according to claim 2, further characterized in that each subset (1,2;1,2') of memory cells (MC0-MC9) is composed by a first group (1) of memory cells (MC4-MC9), supplied with a first subset (R4-R9) of the row address signals (R0-R9) containing the most significant row address signals, and by a second group (2,2') of memory cells (MC0-MC3), supplied with a second subset (R0-R3) of the row address signals (R0-R9) containing the least significant row address signals. Row redundancy integrated circuitry according to claim 3, further characterized in that the first group (1) of memory cells (MC4-MC9) of one subset (1,2) coincides with the first group (1) of memory cells of the other subset (1,2'). Row redundancy integrated circuitry according to claim 4, further characterized in that each memory cell (MC0-MC9) comprises at least one programmable non-volatile memory element (M1), a load circuit (LC) for reading the information stored in said non-volatile memory element (M1), and a programming load circuit (M2) for electrically connecting said non-volatile memory element (M1) to a respective row address signal (R0-R9). Row redundancy integrated circuitry according to claim 5, further characterized in that said programming load circuit comprises a transistor (M2) which is connected between said respective row address signal (R0-R9) and a supply electrode of the non-volatile memory element (M1), and is controlled by a program enable signal (PEVEN,PODD). Row redundancy integrated circuitry according to claim 6, further characterized in that each non-volatile memory register (RR1-RR4) comprises first program selection means (8) supplied with one (EVEN) of said two control signals (EVEN,ODD) and with said respective column address signal (C0-C3) and supplying the memory cells (MC4-MC9) of the first group (1) of memory cells of the two subsets (1,2;1,2') of memory cells and the memory cells (MC0-MC3) of the second group (2) of the first subset (1,2) of memory cells with a first program enable signal (PEVEN), and second program selection means (8') supplied with the other (ODD) of said two control signals (EVEN,ODD) and with said respective column address signal (C0-C3) and supplying the second group (2') of memory cells (MC0-MC3) of the second subset (1,2') of memory cells with a second program enable signal (PODD).

Inventors: GOLLA CARLA MARIA, MACCARRONE MARCO, GOLLA, CARLA MARIA, MACCARRONE, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1994
Main classification: G06F11
IPC codes: G11C29