Interface for devices controlled by microcontrollers and/or microprocessors

Abstract: An interface device for actuator devices (RA) controlled by microprocessors comprises a hold capacitor (C) which can maintain the control signals of the microprocessor such that the microprocessor can detect the current flowing through the actuator device (RA) using the same communication line (IN) used for sending the control signals by means of a feedback connection (R2). The interface device according to the invention thus permits the control and auto-diagnosis of the actuator devices (RA) whilst being very inexpensive.

Description: The present invention relates in general to interfaces for devices controlled by microprocessors and/or microcontrollers and more specifically it relates to interfaces of this type which can actuate diagnosis functions of the devices controlled. Recently, as is known, devices comprising microprocessors and/or microcontrollers for automatically controlling devices and apparatus of all types have become extremely widespread in all areas of technology. These microprocessors perform their functions by sending control signals to actuator devices, for example, power semiconductors or relays. It is clear that, for many applications, it is useful to be able to control the state and functionality of these actuator devices. In fact, in various fields, such as, for example, the motor-vehicle field, there are apparatus the functioning of which is important or even essential, for example, antilock braking systems for which the possibility of being able to diagnose possible breakdowns is extremely useful. Normally, the interfaces used for connections between the microprocessors and the actuator devices have no diagnostic functions or are provided therewith by additional communication lines (I/O), that is, dedicated particularly to the diagnostic functions. This manner of performing the diagnosis is evidently expensive and, furthermore, increases complexity of the electronic system. EP-A-0 418 665 exemplifies that prior art. The object of the present invention is to provide an interface which enables all of the above problems to be overcome satisfactorily. According to the present invention, this object is achieved by virtue of an interface having the characteristics given in the claims following the present description. Further advantages and characteristics of the present invention will become clear from the following detailed description given with reference to the appended drawings, provided by way of non-limiting example, in which: Figure 1 is a schematic circuit diagram of an embodiment of an interface according to the present invention; and Figures 2, 3 and 4 are schematic circuit diagrams of alternative embodiments of the interface according to the present invention. The specific embodiments described here refer to semiconductor actuator devices since they constitute the great majority of the actuator devices connected to microcontrollers and microprocessors and are generally used for controlling other electrical devices such as motors, relays, etc. The interface according to the present invention has three operating states which are known in the following as ON, OFF and TEST MODE. As already stated, the circuit of the interface, shown in Figure 1, comprises a semiconductor device T, for example, a FET or MOSFET-type transistor or a CMOS or HCMOS logic gate. This can be simple, for example, a transistor or complex, for example, a logic gate (inverting or not) which controls a transistor. This semiconductor device T naturally has a control terminal which is normally connected by a resistor R1 to a communication terminal, or line, IN connected to a microprocessor. The semiconductor device T controls a device or charge RA (represented by a resistor) which is connected to a voltage source VBAT. The circuit further comprises a feedback resistor R2 connected between the communication line IN and the terminal of the transistor T connected to the charge resistor RA, and a capacitor C which connects the control terminal of the transistor T to earth GND. In the operating state ON, a high voltage level (ON) which is subsequently maintained as such by the capacity of the capacitor C for a period of time determined by the time constant of the discharge of the capacitor C, is forced to the control terminal of the transistor T by the line IN. In the operating state OFF, a low voltage level (OFF) which is subsequently maintained as such by the capacity of the capacitor C for a period of time determined by the time constant of the charge of the capacitor C, is forced to the control terminal of the transistor T by the line IN. The time constant, for charging and/or discharging, of the capacitor C can possibly be determined by a resistor R3, connected in parallel with the capacitor C and having corresponding size. This alternative embodiment is shown in Figure 2 in which an uncoupling diode D disposed between the line IN and the control terminal of the transistor T is also provided instead of the resistor R1. In the operating state TEST MODE, the capacitor C maintains the command previously imposed on the line IN connected to the microprocessor for these predetermined periods of time. The capacitor C thus "memorises" the command emitted by the microprocessor and maintains it at the control terminal of the transistor T so as to "free" the line IN. This line IN, previously used as an output of the microprocessor for transmitting the command, is then used subsequently as an input, thus enabling the microprocessor to detect the voltage level present at the terminal of the transistor T connected to the charge RA. The microprocessor can thus check that the voltage level detected at this point is appropriate for the correct voltage level in this situation. It will be appreciated that the microprocessor must be arranged and/or programmed such that it can perform these detecting operations. Since the programming and/or arranging of microprocessors and microprocessor systems are within the ability of a person skilled in the art, these operations will not be explained in detail in the present document. If it is wished to extend the operating state TEST MODE using the permanent short-circuit protection function, it is necessary to provide a resistor (not shown) disposed in series with the transistor T, that is, connected between the transistor T and earth GND, in order to restrict the maximum destructive peak current. The interface according to the present invention can advantageously function both with inverting devices and with non-inverting devices, which may be simple, such as, for example, a transistor or more complex, for example, composed of an active component such as a logic gate plus a transistor. Figures 3 and 4 show, for example, two alternative circuits, corresponding to the circuits of Figures 1 and 2 respectively, in which the transistor T is not controlled directly by the communication line IN but by means of an inverting gate of the NOT type. Using devices of the non-inverting type, the circuit is more efficient owing to the intrinsic protection in the event of short-circuits by virtue of the circuit feedback which always restricts the current to a predetermined limit and by virtue of the ability to maintain the operating state (ON or OFF) initially imposed. This state can be memorised for a longer amount of time for example by a bistable circuit, during which the line IN connected to the microprocessor, used as the input, can control the output of the semiconductor device T, for example, according to the process known as polling. In an advantageous alternative embodiment, the interface according to the invention can also be used to perform a closed-loop control of the current flowing through the pulse width modulating (PWM) charge RA without requiring a communication line dedicated to detecting the current itself. In an alternative embodiment, the interface according to the invention does not require a capacitor C for memorising the control signals, since this function is performed by the stray capacitance at the input of the transistor T. This capacity, indicated C' in Figures 1 and 2 (connected by dotted lines), can thus replace the capacitor C where possible. As regards the embodiment shown in Figures 3 and 4, in which an inverting gate NOT is interposed between the transistor T and the line IN, it is possible to use the stray capacitance C' only in the case in which the transistor T and the inverting gate NOT are together in a single integrated semiconductor device comprising the transistor T and the gate NOT. In this case, in fact, the integrated semiconductor device comprises the transistor T and the gate NOT also has a stray capacitance C' at the input which can be used in the manner described above. For this reason, a stray capacitance C' is also shown at the input of the inverting gate NOT in Figures 3 and 4.

Claims: An interface device which can allow processing means to control actuator means (RA), by means of a communication line (IN); and comprising semiconductor means (T) driven by these processing means and which can control the passage of electric current through the actuator means (RA), characterized in that it further comprises: means for storing electric charge (C, C'), operationally connected to the communication line (IN) and to the semiconductor means (T), which can memorise and maintain a control signal sent by the processing means to the semiconductor means (T); detector means (R2), operationally connected to the communication line (IN) and to the actuator means (RA), which can allow these processing means to detect a signal indicating the passage of electric current through the actuator means (RA). A device according to Claim 1, in which the voltage of the semiconductor means (T) is controlled and the control signal is a voltage signal, characterized in that the charge storage means (C, C') are brought to the voltage of the control signal and maintain it for a time interval of predetermined duration in order to control the semiconductor means (T). A device according to Claim 2, characterized in that the charge storage means comprise a capacitance (C, C'). A device according to Claim 3, characterized in that the capacitance consists of a capacitance (C') input to the semiconductor means (T). A device according to Claim 4, characterized in that the capacitance (C') input to the semiconductor means (T) is a stray capacitance. A device according to Claim 3, characterized in that the charge storage means (C, C') comprise a capacitor (C). Device according to any one of Claims 4 to 6, characterized in that the detector means comprise resistor means (R2) connecting the actuator means (RA) to the communication line (IN), such that the processing means detect a voltage at the actuator means (RA) by the resistor means (R2) and the communication line (IN) in the time intervals in which the semiconductor means (T) are controlled by the charge storage means (C, C'). A device according to Claim 7, characterized in that the resistor means comprise a resistor (R2). A device according to Claim 8, characterized in that a resistor (R1) is interposed between the communication line (IN) and the semiconductor means (T). A device according to Claim 8, characterized in that an uncoupling diode (D) is interposed between the communication line (IN) and the semiconductor means (T). A device according to any one of Claims 8 to 10, characterized in that it comprises a resistor (R3) connected in parallel with the capacitor (C) in order to determine the duration of the time intervals. A device according to any one of the preceding claims, in which the semiconductor means comprise a transistor (T), characterized in that it further comprises a restrictor resistor connected in series with the transistor (T). A device according to any one of the preceding claims, characterized in that it comprises logic means (NOT) interposed between the communication line (IN) and the transistor (T). A device according to Claim 13, characterized in that the logic means comprise a logic gate (NOT). A device according to Claim 14, characterized in that the logic gate is an inverting logic gate (NOT). A process for controlling actuator means (RA) in a system comprising processing means and an interface device according to any one of Claims 1 to 15, interposed between the processing means and the actuator means (RA), characterized in that the processing means are configured to perform the following stages: sending a control signal to the interface device by means of the communication line (IN) in a first predetermined time period; and detecting the functioning of the actuator means (RA) by means of the communication line (IN) and the interface device in a second predetermined period of time. A process according to Claim 16, characterized in that the stage for detecting the functioning of the actuator means (RA) comprises the stage of detecting a voltage at the actuator means (RA) by the communication line (IN) and the interface device. A process according to Claim 17, characterized in that it further comprises the stage of controlling a passage of current through the actuator means (RA) according to a predetermined development. A process according to Claim 18, characterized in that the stage for controlling the passage of current through the actuator means (RA) comprises the stage of periodically detecting the voltage at the actuator means (RA), this voltage being indicative of the passage of current. A process according to Claim 19, characterized in that the passage of current through the actuator means (RA) is controlled by pulse width modulation.

Inventors: FERRARI SILVIO, FERRARI, SILVIO
Applicants: MAGNETI MARELLI SPA, MAGNETI MARELLI S.p.A.
Application year: 1994
Main classification: G05B19
IPC codes: G05B19