METHODS FOR FABRICATING FLAT PANEL DISPLAY SYSTEMS AND COMPONENTS

Abstract: A method is provided for fabricating a display cathode which includes forming a conductive line adjacent a face of a substrate. A region of amorphic diamond is formed adjacent a selected portion of the conductive line. The figure is an enlarged exploded cross-sectional view of a diode display unit (10) which includes two primary components: cathode plate (12) and anode plate (14). A vacuum is maintained between the plates by a seal (16). Regularly spaced pillars (26) separate cathode plate (12) and anode plate (14). A plurality of low effective work-function emitter areas (24) are formed by respective layers of amorphic diamond along conductive lines (20) disposed on substrate (18). A layer (34) of photo-emitting material is formed along transparent conductive lines (30) which are disposed upon substrate (28). Enlarge pads or leads (32) allow connection to an external signal source.

Description: METHODS FOR FABRICATING FLAT PANEL DISPLAY SYSTEMS AND COMPONENTS TECHNICAL FIELD OF THE INVENTION The present invention relates in general to flat panel displays and in particular to methods for fabricating flat panel display systems and components. CROSS-REFERENCE TO RELATED APPLICATIONS The following copending and coassigned United States patent applications contain related material and are incorporated herein by reference: United States Patent Application Serial Number 07/851,701, Attorney Docket Number M0050-P01US, entitled "Flat Panel Display Based On Diamond Thin Films," and filed March 16, 1992; and United States Patent Application Serial Number 08/071,157, Attorney Docket Number M0050-P03US, entitled "Amorphic Diamond Film Flat Field Emission Cathode," and filed June 2, 1993. BACKGROUND OF THE INVENTION Field emitters are useful in various applications such as flat panel displays and vacuum microelectronics. Field emission based displays in particular have substantial advantages over other available flat panel displays, including lower power consumption, higher intensity, and generally lower cost. Currently available field emission based flat panel displays however disadvantageously rely on micro- fabricated metal tips which are difficult to fabricate. The complexity of the metal tip fabrication processes, and the resulting low yield, lead to increased costs which disadvantageously impact on overall display system costs. Field emission is a phenomenon which occurs when an electric field proximate the surface of an emission material narrows a width of a potential barrier existing at the surface of the emission material. This narrowing of the potential barrier allows a quantum tunnelling effect to occur, whereby electrons cross through the potential barrier and are emitted from the material. The quantum mechanical phenomenon of field emission is distinguished from the classical phenomenon of thermionic emission in which thermal energy within an emission material is sufficient to eject electrons from the material. The field strength required to initiate field emission of electrons from the surface of a particular material depends upon that material's effective "work function." Many materials have a positive work function and thus require a relatively intense electric field to bring about field emission. Other materials such as cesium, tantalum nitride and trichromium monosilicide, can have low work functions, and do not require intense fields for emission to occur. An extreme case of such a material is one with negative electron affinity, whereby the effective work function is very close to zero (<0.8eV). It is this second group of materials which may be deposited as a thin film onto a conductor, to form a cathode with a relatively low threshold voltage to induce electron emissions. In prior art devices, the field emission of electrons was enhanced by providing a cathode geometry which increases local electric field at a single, relatively sharp point at the tip of a cone (e.g., a micro-tip cathode) . For example, U.S. Patent No. 4,857,799, which issued on August 15, 1989, to Spindt et al., is directed to a matrix-addressed flat panel display using field emission cathodes. The cathodes are incorporated into the display backing structure, and energize corresponding cathodoluminescent areas on an opposing face plate. Spindt et al. employ a plurality of micro-tip field emission cathodes in a matrix arrangement, the tips of the cathodes aligned with apertures in an extraction grid over the cathodes. With the addition of an anode over the extraction grid, the display described in Spindt et al. is a triode (three terminal) display. Micro-tip cathodes are difficult to manufacture since the micro-tips have fine geometries. Unless the micro-tips have a consistent geometry throughout the display, variations in emission from tip to tip will occur, resulting in uneven illumination of the display. Furthermore, since manufacturing tolerances are relatively tight, such micro-tip displays are expensive to make. Thus, to this point in time, substantial efforts have been made in an attempt to design cathodes which can be mass produced with consistent close tolerances. In addition to the efforts to solve the problems associated with manufacturing tolerances, efforts have been made to select and use emission materials with relatively low effective work functions in order to minimize extraction field strength. One such effort is documented in U.S. Patent No. 3,947,716, which issued on March 30, 1976, to Fraser, Jr. et al., directed to a field emission tip on which a metal adsorbent has been selectively deposited. Further, the coated tip is selectively faceted with the emitting planar surface having a reduced work function and the non-emitting planar surface as having an increased work function. While micro-tips fabricated in this manner have improved emission characteristics, they are expensive to manufacture due to the required fine geometries. The need for fine geometries also makes emission consistency between micro-tips difficult to maintain. Such disadvantages become intolerable when large arrays of micro-tips, such as in flat display applications, are required. Additional efforts have been directed to finding suitable geometries for cathodes employing negative electron affinity substances as a coating for the cathode. For instance, U.S. Patent No. 3,970,887, which issued on July 20, 1976, to Smith et al., is directed to a microminiature field emission electron source and method of manufacturing the same. In this case, a plurality of single crystal semiconductor raised field emitter tips are formed at desired field emission cathode sites, integral with a single crystal semiconductor substrate. The field emission source according to Smith et al. requires the sharply tipped cathodes found in Fraser, Jr. et al. and is therefore also subject to the disadvantages discussed above. U.S. Patent No. 4,307,507, issued December 29, 1981 to Gray et al. and U.S. Patent No. 4,685,996 to Busta et al. describe methods of fabricating field emitter structures. Gray et al. in particular is directed to a method of manufacturing a field-emitter array cathode structure in which a substrate of single crystal material is selectively masked such that the unmasked areas define islands on the underlying substrate. The single crystal material under the unmasked areas is orientation-dependent etched to form an array of holes whose sides intersect at a crystallographically sharp point. Busta et al. is also directed to a method of making a field emitter which includes anisotropically etching a single crystal silicon substrate to form at least one funnel-shaped protrusion on the substrate. Busta et al. further provides for the fabrication of a sharp-tipped cathode. Sharp-tipped cathodes are further described in U.S. Patent No. 4,885,636, which issued on August 8, 1989, to Busta et al. and U.S. Patent No. 4,964,946, which issued on October 23, 1990, to Gray et al. Gray et al. in particular discloses a process for fabricating soft-aligned field emitter arrays using a soft-leveling planarization technique, (e.g., a spin-on process) . While the use of low effective work-function materials improves emission, the sharp tipped cathodes referenced above are still subject to the disadvantages inherent with the required fine geometries: sharp- tipped cathodes are expensive to manufacture and are difficult to fabricate such that consistent emission is achieved across an array. Flat cathodes help minimize these disadvantages. Flat cathodes are much less expensive and less difficult to produce in large numbers (such as in an array) because the microtip geometry is eliminated. In Serial No. 07/851,701, which was filed on March 16, 1992, and entitled "Flat Panel Display Based on Diamond Thin Films," an alternative cathode structure was first disclosed. Serial No. 07/851,701 discloses a cathode having a relatively flat emission surface as opposed to the aforementioned micro-tip configuration. The cathode, in its preferred embodiment, employs a field emission material having a relatively low effective work function. The material is deposited over a conductive layer and forms a plurality of emission sites, each of which can field-emit electrons in the presence of a relatively low intensity electric field. A relatively recent development in the field of materials science has been the discovery of amorphic diamond. The structure and characteristics of amorphic diamond are discussed at length in "Thin-Film Diamond, " published in the Texas Journal of Science, vol. 41, no. 4, 1989, by C. Collins et al. Collins et al. describe a method of producing amorphic diamond film by a laser deposition technique. As described therein, amorphic diamond comprises a plurality of micro-crystallites, each of which has a particular structure dependent upon the method of preparation of the film. The manner in which these micro-crystallites are formed and their particular properties are not entirely understood. Diamond has a negative election affinity. That is, only a relatively low electric field is required to narrow the potential barrier present at the surface of diamond. Thus, diamond is a very desirable material for use in conjunction with field emission cathodes. For example, in "Enhanced Cold-Cathode Emission Using Composite Resin-Carbon Coatings," published by S. Bajic and R.V. Latham from the Department of Electronic Engineering and Applied Physics, Aston University, Aston Triangle, Burmingham B4 7ET, United Kingdom, received May 29, 1987, a new type of composite resin- carbon field-emitting cathode is described which is found to switch on at applied fields as low as approximately 1.5 MV m "1 , and subsequently has a reversible I-V characteristic with stable emission currents of greater than or equal to 1 mA at moderate applied fields of typically greater than or equal to 8 MV m "1 . A direct electron emission imaging technique has shown that the total externally recorded current stems from a high density of individual emission sites randomly distributed over the cathode surface. The observed characteristics have been qualitatively explained by a new hot-electron emission mechanism involving a two-stage switch-on process associated with a metal-insulator-metal-insulator-vacuum (MIMIV) emitting regime. However, the mixing of the graphite powder into a resin compound results in larger grains, which results in fewer emission sites since the number of particles per unit area is small. It is preferred that a larger amount of sites be produced to produce a more uniform brightness from a low voltage source. Similarly, in "Cold Field Emission From CVD Diamond Films Observed In Emission Electron Microscopy," published by C. Wang, A. Garcia, D.C. Ingram, M. Lake and M.E. Kordesch from the Department of Physics and Astronomy and the Condensed Matter and Surface Science Program at Ohio University, Athens, Ohio on June 10, 1991, there is described thick chemical vapor deposited "CVD" polycrystalline diamond films having been observed to emit electrons with an intensity sufficient to form an image in the accelerating field of an emission microscope without external excitation. The individual crystallites are of the order of 1-10 microns. The CVD process requires 800oc for the depositing of the diamond film. Such a temperature would melt a glass substrate used in flat panel displays. In sum the prior art has failed to: (1) take advantage of the unique properties of amorphic diamond; (2) provide for field emission cathodes having a more diffused area from which field emission can occur; and (3) provide for a high enough concentration of emission sites (i.e., smaller particles or crystallites) to produce a more uniform electron emission from each cathode site, yet require a low voltage source in order to produce the required field for the electron emissions. SUMMARY OF THE INVENTION According to one embodiment of the present invention, a method is provided for fabricating a display cathode which includes the steps of forming a conductive line adjacent a face of a substrate and forming a region of amorphic diamond adjacent a selected portion of the conductive line. According to another embodiment of the present invention, a method is provided for fabricating a cathode plate for use in a diode display unit which includes the step of forming a first layer of conductive material adjacent a face of a substrate. The first layer of conductive material is patterned and etched to define a plurality of cathode stripes spaced by regions of the substrate. A second layer of conductive material is formed adjacent the cathode stripes and the spacing regions of the substrate. Next, a mask is formed adjacent the second layer of conductive material, the mask including a plurality of apertures defining locations for the formation of a plurality of spacers. The spacers are then formed by introducing a selected material into the apertures. Portions of the second layer of conductive material are selectively removed to expose areas of surfaces of the cathode stripes. Finally, a plurality of amorphic diamond emitter regions are formed in selected portions of the surfaces of the cathode stripes. According to an additional embodiment of the present invention, a method is provided for fabricating a pixel of a triode display cathode which includes the steps of forming a conductive stripe at a face of a substrate. A layer of insulator is formed adjacent the conductive stripe. A layer of conductor is next formed adjacent the insulator layer and patterned and etched along with the layer of conductor to form a plurality of apertures exposing portions of the conductive stripe. An etch is performed through the apertures to undercut portions of the layer of insulator forming a portion of a sidewall of each of the apertures. Finally, regions of amorphic diamond are formed at the exposed portions of the conductive stripe. According to a further embodiment of the present invention a method is provided for fabricating a triode display cathode plate which includes the step of forming a plurality of spaced apart conductive stripes at a face of a substrate. A layer of insulator is formed adjacent the conductive stripes followed by the formation of a layer of conductor adjacent the insulator layer. The layer of insulator and the layer of conductor are patterned and etched to form a plurality of apertures exposing portions of the conductive stripes. An etch is performed through the apertures to undercut portions of the layer of insulator forming a portion of a sidewall of each of the apertures. Finally, regions of amorphic diamond are formed at the exposed portions of the conductive stripes. The embodiments of the present invention have substantial advantages over prior art flat panel display components. The embodiments of the present invention advantageously take advantage of the unique properties of amorphic diamond. Further, the embodiments of the present invention provide for field emission cathodes having a more diffused area from which field emission can occur. Additionally, the embodiments of the present invention provide for a high enough concentration of emission sites that advantageously produces a more uniform electron emission from each cathode site, yet which require a low voltage source in order to produce the required field for the electron emissions. The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGURE la is an enlarged exploded cross-sectional view of a field emission (diode) display unit constructed according to the principles of the present invention; FIGURE lb is a top plan view of the display unit shown in FIGURE la as mounted on a supporting structure; FIGURE lc is a plan view of the face of the cathode plate shown in FIGURE la; FIGURE Id is a plan view of the face of the anode plate shown in FIGURE la; FIGURES 2a-21 are a series of enlarged cross- sectional views of a workpiece sequentially depicting the fabrication of the cathode plate of FIGURE la; FIGURES 3a-3k are a series of enlarged cross- sectional views of a workpiece sequentially depicting the fabrication of the anode plate of FIGURE la; FIGURE 4a is an enlarged plan view of a cathode/extraction grid for use in a field emission (triode) display unit constructed in accordance with the principles of the present invention; FIGURE 4b is a magnified cross-sectional view of a selected pixel in the cathode/extraction grid of FIGURE 4a; FIGURE 4c is an enlarged exploded cross-sectional view of a field emission (triode) display unit embodying the cathode/extraction grid of FIGURE 4a; FIGURES 5a-5k are a series of enlarged cross- sectional views of a workpiece sequentially depicting the fabrication of the cathode/extraction grid of FIGURE 4a; FIGURE 6 depicts an alternate embodiment of the cathode plate shown in FIGURE la in which the microfabricated spacers have been replaced by glass beads; FIGURE 7 depicts an additional embodiment of the cathode plate shown in FIGURE la in which layers of high resistivity material has been fabricated between the metal cathode lines and the amorphic diamond films; and FIGURES 8a and 8b depict a further embodiment using both the high resistivity material shown in FIGURE 7 and patterned metal cathode lines. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiments of present invention are best understood by referencing FIGURES 1-5 of the drawings in which like numerals designate like parts. FIGURE la is an enlarged exploded cross-sectional view of a field emission (diode) display unit 10 constructed in accordance with the principles of the present invention. A corresponding top plan view of display unit 10 mounted on a supporting structure (printed circuit board) 11 is provided in FIGURE lb. Display unit 10 includes a sandwich of two primary components: a cathode plate 12 and an anode plate 14. A vacuum is maintained between cathode plate 12 and anode plate 14 by a seal 16. Separate plan views of the opposing faces of cathode plate 12 and anode plate 14 are provided in FIGURES lc and Id respectively (the view of FIGURE la substantially corresponds to line la-la of FIGURES lb, lc, and Id) . Cathode plate 12, the fabrication of which is discussed in detail below, includes a glass (or other light transmitting material) substrate or plate 18 upon which are disposed a plurality of spaced apart conductive lines (stripes) 20. Each conductive line 20 includes an enlarged lead or pad 22 allowing connection of a given line 20 to external signal source (not shown) (in FIGURE lb display unit pads 22 are shown coupled to the wider printed circuit board leads 23) . Disposed along each line 20 are a plurality of low effective work-function emitters areas 24, spaced apart by a preselected distance. In the illustrated embodiment, low effective work-function emitter areas are formed by respective layers of amorphic diamond. A plurality of regularly spaced apart pillars 26 are provided across cathode plate 12, which in the complete assembly of display 10 provide the requisite separation between cathode plate 12 and anode plate 14. Anode plate 14, the fabrication of which is also discussed in detail below, similarly includes a glass substrate or plate 28 upon which are disposed a plurality of spaced apart transparent conductive lines (stripes) 30, e.g., ITO (Indium doped Tin Oxide). Each conductive line 30 is associated with a enlarge pad or lead 32, allowing connection to an external signal source (not shown) (in FIGURE lb display unit pads 32 are shown coupled to the wider printed circuit board leads 33) . A layer 34 of a phosphor or other photo-emitting material is formed along the substantial length of each conductive line 30. In display unit 10, cathode plate 12 and anode plate 14 are disposed such that lines 20 and 30 are substantially orthogonal to each other. Each emitter area 24 is proximately disposed at the intersection of the corresponding line 20 on cathode plate 12 and line 30 on anode plate 14. An emission from a selected emitter area 24 is induced by the creation of a voltage potential between the corresponding cathode line 20 and anode line 30. The electrons emitted from the selected emitter area 24 strike the phosphor layer 34 on the corresponding anode line 30 thereby producing light which is visible through anode glass layer 28. For a more complete description of the operation of display 10, reference is now made to copending and coassigned U.S. Patent Application Serial Number 08/071,157, Attorney's Docket Number M0050-P03US. The fabrication of diode display cathode plate 12 according the principles of the present invention can now be described by reference to illustrated embodiment of FIGURES 2a-21. In FIGURE 2a, a layer 20 of conductive material has been formed across a selected face of glass plate 18. In the illustrated embodiment, glass plate 18 comprises a 1.1 mm thick soda lime glass plate which has been chemically cleaned by a conventional process prior to the formation of conductive layer 20. Conductive layer 20 in the illustrated embodiment comprises a 1400 angstroms thick layer of chromium. It should be noted that alternate materials and processes may be used for the formation of conductive layer 20. For example, conductive layer 20 may alternatively be a layer of copper, aluminum, molybdenum, tantalum, titanium, or a combination thereof. As an alternative to sputtering, evaporation or laser ablation techniques may be used to form conductive layer 20. Referring next to FIGURE 2b, a layer of photoresist 38 has been spun across the face of conductive layer 20. The photoresist may be for example, a 1.5 mm layer of Shipley 1813 photoresist. Next, as is depicted in FIGURE 2c, photoresist 38 has been exposed and developed to form a mask defining the boundaries and locations of cathode lines 20. Then, in FIGURE 2d, following a descum step (which may be accomplished for example using dry etch techniques) , conductive layer 20 is etched, the remaining portions of layer 20 becoming the desired lines 20. In the preferred embodiment, the etch step depicted in FIGURE 2d is a wet etch 38. In FIGURE 2e, the remaining portions of photoresist 36 are stripped away, using for example, a suitable wet etching technique. In FIGURE 2f a second layer of conductor 40 has been formed across the face of the workpiece. In the illustrated embodiment conductive layer 40 is formed by successively sputtering a 500 angstroms layer of titanium, a 2500 angstroms layer of copper, and a second 500 angstroms layer of titanium. In alternate embodiments, metals such as chromium - copper - titanium may be used as well as layer formation techniques such as evaporation. Next, as shown in FIGURE 2g, a layer 42 of photoresist is spun across the face of conductive layer 40, exposed, and developed to form a mask defining the boundaries and locations of pillars (spacers) 26 and pads (leads) 22. Photoresist 42 may be for example a 13 μm thick layer of AZP 4620 photoresist. Following descum (which again may be performed using dry etch techniques), as shown in FIGURE 2h, regions 44 are formed in the openings in photoresist 42. In the illustrated embodiment regions 44 are formed by the electrolytic plating of 25 μm of copper or nickel after etching away titanium in the opening. Following the plating step, photoresist 42 is stripped away, using for example WAYCOAT 2001 at a temperature of 80oc, as shown in FIGURE 2i. Conductor layer 40 is then selectively etched as shown in FIGURE 2j . In the illustrated embodiment, a non-HF wet etch is used to remove the copper/titanium layer 40 to leave pillars 26 and pads 22 which comprise a stack of copper layer 44 over a titanium/copper/titanium layer 40. In FIGURE 2k, a metal mask 46 made form copper, molybdenum or preferably magnetic materials such as nickel or Kovar defining the boundaries of emitter areas 24 is placed on top of the cathode plate and is aligned properly to the spacers and lines. Emitter areas 24 are then fabricated in the areas exposed through the mask by the formation of amorphic diamond films comprising a plurality of diamond micro-crystallites in an overall amorphic structure. In the embodiment illustrated in FIGURE 2k, the amorphic diamond is formed through the openings in metal mask 46 using laser ablation. The present invention however is not limited to the technique of laser ablation. For example, emitter areas 24 having micro-crystallites in an overall amorphic structure may be formed using laser plasma deposition, chemical vapor deposition, ion beam deposition, sputtering, low temperature deposition (less than 500°C) , evaporation, cathodic arc evaporation, magnetically separated cathodic arc evaporation, laser acoustic wave deposition, similar techniques, or a combination thereof. One such process is described in "Laser Plasma Source of Amorphic Diamond, " published by American Institute of Physics, January 1989, by Collins et. al. In general the micro-crystallites form with certain atomic structures which depend on environmental conditions during layer formation and somewhat by chance. At a given environmental pressure and temperature, a certain percentage of crystals will emerge in an SP2 (two-dimensional bonding of carbon atoms) while a somewhat smaller percentage will emerge in an SP3 configuration (three-dimensional bonding of carbon atoms) . The electron affinity for diamond micro-crystallites in the SP3 configuration is less than that of the micro-crystallites in the SP2 configuration. Those micro-crystallites in the SP3 configuration therefore become the "emission sites" in emission areas 24. For a full appreciation of the advantages of amorphic diamond, reference is now made to copending and coassigned U.S. Patent Application Serial Number 08/071,157, Attorney's Docket Number M0050-P03US. Finally, in FIGURE 21, ion beam milling, or a similar technique, is used to remove leakage paths between paths between lines 20. In addition other conventional cleaning methods (commonly used in microfabrication technology) may be used to remove large carbon (or graphite) particles generated during amorphic diamond deposition. Following conventional clean-up and trimming away of the excess glass plate 18 around the boundaries, cathode plate 12 is ready for assembly with anode plate 14. The fabrication of the anode plate 14 according to the principles of the present invention can now be described using the illustrative embodiment of FIGURES 3a -3k. In FIGURE 3a, a layer 30 of conductive material has been formed across a selected face of glass plate 28. In the illustrated embodiment, glass plate 28 comprises a 1.1 mm thick layer of soda lime glass which has been previously chemically cleaned by a conventional process. Transparent conductive layer 30 in the illustrated embodiment comprises a 2000 A thick layer of Indium doped Tin Oxide formed by sputtering. Referring next to FIGURE 3b, a layer of photoresist 50 has been spun across the face of conductive layer 30. The photoresist may be for example a 1.5 μm layer of Shipley 1813 photoresist. Next, as is depicted in FIGURE 3c, photoresist 50 has been exposed and developed to form a mask defining the boundaries and locations of anode lines 30. Then, in FIGURE 3d following a conventional descum step, conductive layer 30 is etched, the remaining portions of layer 30 becoming the desired lines 30. In FIGURE 3e, the remaining portions of photoresist 50 are stripped away. In FIGURE 3f a second layer of conductor 52 has been formed across the face of the workpiece. In the illustrated embodiment conductive layer 52 is formed by successively sputtering a 500 A layer of titanium, a 2500 A layer of copper, and a second 500 A layer of titanium. In alternate embodiments, other metals and fabrication processes may be used at this step, as previously discussed in regards to the analogous step shown in FIGURE 2f. Next, as depicted in FIGURE 3g, a layer 54 of photoresist is spun across the face of conductive layer 52, exposed, and developed to form a mask defining the boundaries and locations of pads (leads) 32. Following descum, pads (leads) 32 are completed by forming plugs of conductive material 56 in the openings in photoresist 54 as depicted in FIGURE 3h. In the illustrated embodiment, pads 32 are formed by the electrolytic plating of 10 μm of copper. Following the plating step, photoresist 54 is stripped away, using for example WAYCOAT 2001 at a temperature of 80oC, as shown in FIGURE 3i. The exposed portions of conductor layer 52 are then etched as shown in FIGURE 2j . In FIGURE 3j, a non-HF wet etch is used to remove exposed portions of titanium/copper/titanium layer 52 to leave pads 32 which comprise a stack of corresponding portions of conductive stripes 30, the remaining portions of titanium/copper/titanium layer 52 and the conductive plugs 56. The use of a non-HF etchant avoids possible damage to underlying glass 28. After cleaning and removing excess glass 28 around the boundaries, phosphor layer 34 is selectively formed across substantial portions of lines anode lines 30 as shown in FIGURE 3k. Phosphor layer, in the illustrated embodiment a layer of powdered zinc oxide (ZnO) , may be formed for example using a conventional electroplating method such as electrophoresis. Display unit 10 depicted in FIGURES la and Id can then be assembled from a cathode plate 12 and anode plate 14 as described above. As shown, the respective plates are disposed face to face and sealed in a vacuum of IO "7 torr using seal which extends along the complete perimeter of unit 10. In the illustrated embodiment, seal 16 comprises a glass frit seal, however, in alternate embodiments, seal 16 may be fabricated using laser sealing or by an epoxy, such as TORR-SEAL (Trademark) epoxy. Reference is now made to FIGURE 4a, which depicts the cathode/grid assembly 60 of a triode display unit 62 (FIGURE 4c) . Cathode/grid assembly 60 includes a plurality of parallel cathode lines (stripes) 64 and a plurality of overlying extraction grid lines or stripes 66. At each intersection of a given cathode stripe 64 and extraction line 66 is disposed a "pixel" 68. A further magnified cross-sectional view of a typical "pixel" 68 is given in FIGURE 4b as taken substantially along line 4b-4b of FIGURE 4a. A further magnified exploded cross-sectional view of the selected pixel 68 in the context of a triode display unit 62, with the corresponding anode plate 70 in place and taken substantially along line 4c-4c of FIGURE 4a is given in FIGURE 4c. Spacers 69 separate anode plate 70 and cathode/grid assembly 60. The cathode/grid assembly 60 is formed across the face of a glass layer or substrate 72. At a given pixel 68, a plurality of low work function emitter regions 76 are disposed adjacent the corresponding conductive cathode line 64. Spacers 78 separate the cathode lines 64 from the intersecting extraction grid lines 66. At each pixel 68, a plurality of apertures 80 are disposed through the grid line 66 and aligned with the emitter regions 76 on the corresponding cathode line 64. The anode plate 70 includes a glass substrate 82 over which are disposed a plurality of parallel transparent anode stripes or lines 84. A layer of phosphor 86 is disposed on the exposed surface of each anode line, at least in the area of each pixel 68. For monochrome display, only an unpatterned phosphor such as ZnO is required. However, if a color display is required, each region on anode plate 70 corresponding to a pixel will have three different color phosphors. Fabrication of anode plate 70 is substantially the same as described above with the exception that the conductive anode lines 84 are patterned and etched to be disposed substantially parallel to cathode lines 64 in the assembled triode display unit 62. The fabrication of a cathode/grid assembly 60 according to the principles of the present invention can now be described by reference to the embodiment illustrated in FIGURES 5a-5k. In FIGURE 5a, a layer 64 of conductive material has been formed across a selected face of glass plate 72. In the illustrated embodiment, glass plate 72 comprises a 1.1 mm thick soda lime glass which has been chemically cleaned by a conventional process prior to formation of conductive layer 64. Conductive layer 64 in the illustrated embodiment comprises a 1400 angstroms thick layer of chromium. It should be noted that alternate materials and fabrication processes can be used to form conductive layer, as discussed above in regards to conductive layer 20 of FIGURE 2a and conductive layer 30 of FIGURE 3a. Referring next to FIGURE 5b, a layer of photoresist 92 has been spun across the face of conductive layer 64. The photoresist may be for example a 1.5 μm layer of Shipley 1813 photoresist. Next, as is depicted in FIGURE 5c, photoresist 92 has been exposed and developed to form a mask defining the boundaries and locations of cathode lines 64. Then, in FIGURE 5d following a conventional descum (for example, performed by a dry etch process) , conductive layer 64 is etched leaving the desired lines 64. In FIGURE 5e, the remaining portions of photoresist 92 are stripped away. Next, as shown in FIGURE 5f, a insulator layer 94 is formed across the face of the workpiece. In the illustrated embodiment, insulator layer 94 comprises a 2 μm thick layer of silicon dioxide (Si02) which is sputtered across the face of the workpiece. A metal layer 66 is then formed across insulator layer 94. In the illustrated embodiment, metal layer comprises a 500-0 A thick layer of titanium-tungsten (Ti-W) (90%-10%) formed across the workpiece by sputtering. In alternate embodiments, other metals and fabrications may be used . FIGURE 5g is a further magnified cross-sectional view of a portion of FIGURE 5f focusing on a single pixel 68. In FIGURE 5g, a layer 98 of photoresist, which may for example be a 1.5 μm thick layer of Shipley 1813 resist, is spun on metal layer 96. Photoresist 98 is then exposed and developed to define the location and boundaries of extraction grid lines 66 and the apertures 80 therethrough. Following descum, metal layer 66 (TI-W in the illustrated embodiment) and insulator layer 94 (in the illustrated embodiment Si02) are etched as shown in FIGURE 5h leaving spacers 78. Preferably, a reactive ion etch process is used for this etch step to insure that the sidewalls 100 are substantially vertical. In FIGURE 5i, the remaining portions of photoresist layer 98 is removed, using for example WAYCOAT 2001 at a temperature of 80oc. After photoresist removal, a wet etch is performed which undercuts insulator layer 94, as shown in FIGURE 5j further defining spacers 78. In other words, the sidewalls of the wet etch may be accomplished for example using a buffer-HF solution. The cathode/grid structure 62 is essentially completed with the formation of the emitter areas 76. In FIGURE 5k, a metal mask 102 is formed defining the boundaries and locations of emitter areas 76. Emitter areas 76 are then fabricated by the formation of amorphic diamond films comprising a plurality of diamond micro-crystallites in an overall amorphic structure. In the embodiment illustrated in FIGURE 5j , the amorphic diamond is formed through the openings in metal mask 102 using laser ablation. Again, the present invention however is not limited to the technique of laser ablation. For example, emitter areas 76 having micro-crystallites in an overall amorphic structure may be formed using laser plasma deposition, chemical vapor deposition, ion beam deposition, sputtering, low temperature deposition (less than 500°C) , evaporation, cathodic arc evaporation, magnetically separated cathodic arc evaporation, laser acoustic wave deposition, similar techniques, or a combination thereof. The advantages of such amorphic diamond emitter areas 76 have been previously described during the above discussion of diode display unit 10 and in the cross-references incorporated herein. FIGURE 6 shows an alternative embodiment of cathode plate 12. In this case, the fabrication of spacers 44 shown in steps 2f-2j is not required. Thereafter, small glass, sapphire, polymer or metal beads or fibers, such as the depicted 25 micron diameter glass beads 104, are used as spacers, as seen in FIGURE 6. Glass beads 104 may be attached to the substrate by laser welding, evaporated indium or glue. Alternatively, glass beads 104 may be held in place by subsequent assembly of the anode and cathode plates. FIGURE 7 shows a further embodiment of cathode plate 12. In this case, a thin layer 106 of a high resistivity material such as amorphous silicon has been deposited between the metal line 20 and the amorphic diamond film regions 24. Layer 106 helps in the self- current limiting of individual emission sites in a given pixel and enhances pixel uniformity. Also as shown in FIGURE 7, each diamond layer 24 is broken into smaller portions. The embodiment as shown in FIGURE 7 can be fabricated for example by depositing the high resistivity material through metal mask 46 during the fabrication step shown in FIGURE 2k (prior to formation of amorphic diamond regions 24) using laser ablation, e-beam deposition or thermal evaporation. The amorphic diamond is then deposited on top of the high resistivity layer 106. In order to create layers 24 which are broken into smaller regions as shown in FIGURE 7, the amorphic diamond film can be directed through a wire mesh (not shown) intervening between metal mask 46 and the surface of layer 106. In a preferred embodiment, the wire mesh has apertures therethrough on the order of 20 - 40 μm, although larger or smaller apertures can be used depending on the desired pixel size. In FIGURES 8a and 8b an additional embodiment of cathode plate 12 having patterned metal lines 20 is depicted. In this case, an aperture 108 has been opened through the metal line 20 and a high resistivity layer 106 such as that discussed above formed therethrough. The amorphic diamond thin films 24 are then disposed adjacent the high resistivity material 106. In the embodiment shown in FIGURES 8a and 8b, diamond amorphic films 24 have been patterned as described above. It should be noted that in any of the embodiments disclosed herein, the amorphic diamond films may be fabricated using random morphology. Several fabrication methods such as ion beam etching, sputtering, anodization, sputter deposition and ion- assisted implantation which produce very fine random features of sub-micron size without the use of photolithography. One such method is described in co- pending and co-assigned patent application Serial No. ' 08/052,958 entitled "Method of Making A Field Emitter Device Using Randomly Located Nuclei As An Etch Mask", Attorney's Docket No. DMS-43/A, a combination of random features which enhance the local electric field on the cathode and low effective work function produces even lower electron extraction fields. It should be recognized that the principles of the embodiments shown in FIGURES 6-8 for cathode plate 12 can also be applied to the fabrication of cathode/grid assembly 60 of triode display unit 62 (FIGURE 4c) . It should also be noted that while the spacers herein have been illustrated as disposed on the cathode plate, the spacers may also be disposed on the anode plate, or disposed and aligned on the cathode and anode plates in accordance with the present invention. Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A method for fabricating a display cathode comprising the steps of: forming a conductive line adjacent a face of a substrate; and forming a region of amorphic diamond adjacent a selected portion of the conductive line. 2. The method of claim 1 wherein said step of forming a conductive line comprises the substeps of: forming a layer of conductor adjacent said face; forming a layer of photoresist adjacent said layer of conductor; exposing and developing said layer of photoresist to form a mask defining boundaries of said conductive line; and etching said layer of conductor through said mask to form said conductive line. 3. A method of fabricating a cathode plate for use in a diode display unit comprising the steps of: forming a first layer of conductive material adjacent a face of a substrate; patterning and etching the first layer of conductive material to define a plurality of cathode stripes spaced by regions of the substrate; forming a second layer of conductive material adjacent the cathode stripes and the regions of the substrate therebetween; forming a mask adjacent the second layer of conductive material having a plurality of apertures defining locations for the formation of a plurality of spacers; forming said plurality of spacers by introducing a selected material into the apertures; selectively removing portions of the second layer of conductive material to expose surface areas of the cathode stripes; and selectively forming a plurality of amorphic diamond emitter regions in selected portions of the surface areas of the cathode stripes. 4. A method of fabricating a cathode plate comprising the steps of: forming a layer of conductor adjacent a face of a substrate; patterning and etching the layer of conductor to define a plurality of cathode stripes spaced by interleaved regions of the substrate; and selectively forming a plurality of amorphic diamond emitter regions in selected surface areas of the cathode stripes. 5. The method of Claim 4 wherein said step of forming a region of amorphic diamond comprises the step of forming a region of amorphic diamond by laser ablation. 6. A method of fabricating a pixel of a triode pixel display cathode comprising the steps of: forming a conductive stripe at a face of a substrate; forming a layer of insulator adjacent the conductive stripe; forming a layer of conductor adjacent the insulator layer; patterning and etching the layer of insulator and the layer of conductor to form a plurality of apertures exposing portions of the conductive stripe; etching through the apertures to undercut portions of the layer of insulator forming a portion of a sidewall of each of the apertures; and forming regions of amorphic diamond at the exposed portions of the conductive stripe. 7. The method of Claim 6 wherein said step of forming regions of amorphic diamond comprises the step of forming regions of amorphic diamond by laser ablation. 8. A method of fabricating a triode display cathode plate comprising the steps of: forming a plurality of spaced apart conductive stripes at a face of a substrate; forming a layer of insulator adjacent the conductive stripes; forming a layer of conductor adjacent the insulator layer; patterning and etching the layer of insulator and the layer of conductor to form a plurality of apertures exposing portions of the conductive stripes; etching through the apertures to undercut portions of the layer of insulator forming a portion of a sidewall of each of the apertures; and forming regions of amorphic diamond at the exposed portions of the conductive stripes. 9. The method of Claim 8 wherein said step of forming regions of amorphic diamond comprises a step of forming regions of amorphic diamond by laser ablation. 10. A method of fabricating a cathode plate comprising the steps of: forming a layer of conductor adjacent a face of a substrate; patterning and etching the layer of conductor to define a plurality of cathode stripes spaced between interleaved regions of the substrate; forming a plurality of spacers disposed within said interleaved regions of the substrate; and selectively forming a plurality of amorphic diamond emitter regions in selected areas of the cathode stripes. 11. A method of fabricating a cathode plate comprising the steps of: forming a layer of conductor adjacent a face of a substrate; patterning and etching the layer of conductor to define a plurality of cathode stripes spaced by interleaved regions of the substrate; selectively forming regions of high resistivity material adjacent portions of the cathode stripes; and selectively forming a plurality of amorphic diamond emitter regions in selected areas of the regions of high resistivity material. 12. The method of Claim 11 wherein said step of forming a plurality of amorphic diamond regions comprises the step of forming a plurality of amorphic diamond regions using random morphology. 13. A method of fabricating a cathode plate comprising the steps of: forming a layer of conductor adjacent a face of a substrate; patterning and etching the layer of conductor to define a plurality of cathode stripes spaced by interleaved regions of the substrate, the plurality of cathode stripes including a plurality of apertures therethrough exposing underlying regions of the substrate; selectively forming regions of high resistivity material within the apertures through the cathode stripes; and selectively forming a plurality of amorphic diamond emitter regions in selected areas of the regions of high resistivity material. 14. The method of Claim 13 wherein said step of forming a plurality of amorphic diamond emitter regions in selected areas of the regions of high resistivity material comprises the step of forming amorphic diamond regions using random morphology.

Inventors: KUMAR NALIN, XIE CHENGGANG, KUMAR, NALIN, XIE, CHENGGANG
Applicants: MICROELECTRONICS & COMPUTER, MICROELECTRONICS AND COMPUTER TECHNOLOGY CORPORATI
Application year: 1994
Main classification: G03C5
IPC codes: H01J9, H01J17, H01J19, H01J29, H01J31, H04N1