Data recording method

Abstract: A pilot signal is superposed and recorded on data at the beginning of each track. The beginning part of the track is constituted by using only codewords of which disparity in every 10 bits is +2, 0 or -2. The beginning part of track is also constituted so that the cumulative value of the disparities of every 10 bits may increase or decrease in the period of the pilot signal to be superposed. Therefore, the frequency spectrum in the beginning part of the track has a peak at the frequency of pilot signal, and using this peak as pilot signal, tracking is controlled in reproduction.

Description: The present invention relates to a recording method in high density magnetic recording apparatus such as a digital recording video cassette recorder (digital VCR). Presently is promoted the study on the digital VCR for recording sound and picture by digital signals of 0 and 1 for the purpose of higher picture quality and higher sound quality. In particular, video signals contain plenty of information, and to record them for a long time, high density recording for recording plenty of information on a tape is indispensable. Two methods are attempted at present for high density recording. A first method is to shorten a length necessary for recording one bit,which is a method of enhancing a so-called line density. A second method is to narrow a track width. To enhance the line density, hitherto, improvement was promoted from a viewpoint of recording material and signal processing, and about 0.25 µm of the line density is realized for recording one bit. On the other hand, the tracking width is said to be limited around 10 µm in a VCR from a viewpoint of mechanical precision in recording and reproducing, and tracking control for obtaining a stable reproduced output. In an 8 mm VCR, a pilot signal is superposed and recorded in video signals and audio signals for the purpose of tracking control. In the case of the digital VCR for recording video signals and audio signals by digital signals, a quantity of information to be recorded is very large as compared with that of an analog VCR. That is, the technology of high density recording is more required than that of the analog VCR. In the digital VCR, a recording signal band is much wider than in the analog VCR, and it is difficult to assign a frequency for pilot signals in other frequency band than a signal to be recorded as in the 8 mm VCR. It is thus required to assign a pilot signal frequency within the frequency band of signal to be recorded. Besides, to realize a narrow track width, it is needed to raise a ratio of a amplification level of the pilot signal to a noise level of the pilot signal. However, when the amplification level of the pilot signal is increased, an amplitude of other signal than an original signal to be recorded is also increased, and the pilot signal disturbs when reproducing, and an error rate of judging each bit whether 1 or 0 becomes higher. Accordingly, if attempted to superpose other signal than a signal to be recorded as the pilot signal, an amplitude of the pilot signal cannot be increased. If the amplitude of the pilot signal cannot be increased, a ratio of signal to noise (S/N) of the pilot signal in a reproduced signal becomes poor, and the tracking precision is worsened. Therefore, in a system for superposing other signal than the signal to be recorded as a pilot signal, it is difficult to realize a system with a narrow track width. EP-A-0 339 724 discloses an arrangement where the pilot signal is generated by converting 8-bit information words to 10-bit channel words such that each channel word is selected from at least three channel words of different disparity, positive, negative or zero, in such a way that the average value of the recorded signal can vary substantially in conformity with the variation of the pilot signal wave. The conversion is realized by using a predetermined conversion table or by using a precoder. It is hence a primary object ofthe present invention to present a method for superposing a pilot signal for tracking at the time of reproduction so as not to disturb judgement of 1 or 0 in reproduction, in a high density magnetic recording apparatus. The present invention provides a data recording method for recording digital data on a plurality of parallel tracks formed on a recording medium, each of said tracks having an insert information recording region provided at the beginning of the track and audio and video data recording regions, said method comprising the steps of: recording at least one of audio data and video data on said audio and video recording regions of a track on the recording medium; generating a plurality of ID codewords such that the cumulative value of the disparity which is defined as a difference in the number of 1's and O's in every n bits varies periodically to generate a pilot signal which will be used for tracking control; recording the generated ID codewords into the insert information recording region of the track on the recording medium, characterized in that the step of generating the plurality of ID codewords includes the step of: converting an m-bit data block into a 2m-bit data block by once repeating each bit of the m-bit data block, 2T pre-coding the m-bit data block with an initial bit value of 01 or 10 to obtain a (2m+2)-bit data block beginning with said initial bit value, and adding k dummy bits to the (2m+2)-bit data block to obtain an ID codeword having 2m+2+k bits, wherein the k dummy bits have a disparity between a total number of 1 bits and a total number of 0 bits which is +i, 0, or -i. A data row recorded in such data recording method is recorded so that the cumulative value of disparities of every n bits may vary in the period of the pilot signal. Increase or decrease of the cumulative value of disparities is the pilot signal. Since the data row to be recorded itself generates the pilot signal, the error rate is not raised if recorded by enlarging the increase or decrease of disparity so that the amplitude of the pilot signal may be larger. In the data recording method of the present invention, the amplitude of the pilot signal used for tracking at the time of reproduction can be increased at the time of recording without worsening the error rate in reproduction, so that a system of narrow track width can be realized. In order that the present invention be more readily understood an embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig. 1 is a block diagram of an insert information generating circuit showing an embodiment of the present invention. Fig. 2 is a block diagram of an insert information generating circuit showing other embodiment of the present invention. Fig. 3 is a structural diagram of track patterns according to the embodiment of the present invention. Fig. 4 is a block diagram of a recording apparatus showing the embodiment of the present invention. Fig. 5 is a diagram showing a frequency spectrum of data row recorded in the embodiment of the present invention. Fig. 6 is a configuration diagram of three different patterns on a tape to be recorded in the embodiment of the present invention. Fig. 7 is a diagram showing a disparity of every 10 bits of data row. Fig. 8 is a diagram showing increase or decrease of cumulative value of disparities of every 10 bits of data row at frequency F1. Fig. 9 is a recording pattern showing a first example of selection order of three kinds of run-up data in region G1. Fig. 10 is a recording pattern showing a second example of selection order of three kinds of run-up data in region G1. Fig. 11 is a recording pattern showing a third example of selection order of three kinds of run-up data in region G1. Fig. 12 is a diagram showing configuration of sync block in region ITI. Fig. 13 is a bit pattern showing a first example of synchronization codeword of ITI. Fig. 14 is a bit pattern showing a second example of synchronization codeword of ITI. Fig. 15 is a diagram showing configuration of ID code-word-L and an example of dummy part. Fig. 16 is a diagram for explaining a coding method of block number part of ID codeword-L and ID codeword-U of ITI. Fig. 17 is a diagram showing an example of selection order of each codeword in region ITI. Fig. 18 is a block diagram of 2T- pre-code. Fig. 19 is a diagram for explaining configuration of sync block when recording the block number first from MSB in ITI. Fig. 20 is a diagram showing another disparity of every 10 bits of data row. Fig. 3 shows a configuration of a track patterns in an embodiment of the present invention. Two track patterns (A) and (B) are shown in Fig. 3. Regions A and V are audio and video data recording regions. INDEX is a region for recording time code and other information. G2 to G4 are regions provided for inserting and recording regions INDEX, A and V individually. A recording amplifier is turned on or off in these regions. G5 is provided to prevent the old data from being left over when overwritten. G1 and ITI are regions for recording insert information for insert recording to replace the data in at least one region out of the regions A, V and INDEX. Fig. 4 shows an example of recording apparatus for recording the track pattern in Fig. 3. A video signal 401 is fed into a video signal processing circuit 403. An audio signal 402 is fed into an audio signal processing circuit 404. The video signal processing circuit 403 processes an input video signal by error correction coding or the like, and sends out to a switch circuit 408. The audio signal processing circuit 404 processes an input audio signal by error correction coding or the like, and sends out to the switch circuit 408. An INDEX generating circuit 405 generates additional information such as time code and sends out to the switch circuit 408. An insert information generating circuit 406 generates insert information, and sends out to the switch circuit 408. An output signal from the insert information generating circuit 406 is recorded in the regions G1 and ITI in the track patterns in Fig. 3. A GAP data generating circuit 407 generates the data to be recorded in regions G2, G3, G4 and G5 in Fig. 3, and sends out to the switch circuit 408. The switch circuit 408 receives a control signal from a control circuit 409, and changes over output signals from the video signal processing circuit 403, audio signal processing circuit 404, INDEX generating circuit 405, and insert information generating circuit 406, and sends out to a recording amplifier 410. The control circuit 409 sends out a control signal to the switch circuit 408 so that an output signal of the switch circuit 408 may be recorded on the tape in the track patterns shown in Fig. 3. The recording amplifier 410 amplifies the output signal of the switch circuit 408, and sends out to a recording head 411. The recording head 411 records an output signal from the recording amplifier 410 in a magnetic tape 412. Referring now to an example of track pattern (B) in Fig. 3, an operation of the recording apparatus in Fig. 4 for recording this track pattern is described. At the beginning of each track, the insert information generating circuit 406 sends out the data to be recorded in region G1 in Fig. 3. The control circuit 409 sends out a control signal to the switch circuit 408 so that the switch circuit 408 may select the output signal of the insert information generating circuit 406. The switch circuit 408 selects the output signal of the insert information generating circuit 406, and sends out to the recording amplifier 410. The insert information generating circuit 406 sends out data to be recorded in the region ITI. The control circuit 409 issues a control signal so that the switch circuit 408 may consecutively selects the output signal of the insert information generating circuit 406. The switch circuit 408 selects the output signal of the insert information generating circuit 406 consecutively according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. Consequently, the GAP data generating circuit 407 generates the data to be recorded in the region G2, and sends out to the switch circuit 408. The control circuit 409 sends out a control signal to the switch circuit 408 so as to select the output signal of the GAP data generating circuit 407 upon reaching the time for recording region G2. The switch circuit 408 selects the output signal of the GAP data generating circuit 407 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. The audio signal processing circuit 404 sends out the data to be recorded in region A. The control circuit 409, upon reaching the time for recording region A, sends out a control signal to the switch circuit 408 so as to select the output signal of the audio signal processing circuit 404. The switch circuit 408 selects the output signal of the audio signal processing circuit 404 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. In consequence, the GAP data generating circuit 407 generates the data to be recorded in region G3, and sends out to the switch circuit 408. The control circuit 409, upon reaching the time for recording region G3, sends out a control signal to the switch circuit 408 so as to select the output signal of the GAP data generating circuit 407. The switch circuit 408 selects the output signal of the GAP data generating circuit 407 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. Consequently, the video signal processing circuit 403 sends out the data to be recorded in the region V. The control circuit 409, upon reaching the time for the region V, sends out a control signal to the switch circuit 408 so as to select an output signal of the video signal processing circuit 403. The switch circuit 408 selects the output signal of the video signal processing circuit 403 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. Successively, the GAP data generating circuit 407 generates data to be recorded in the region G4, and sends out to the switch circuit 408. The control circuit 409, upon reaching the time for the region G4, sends out a control signal to the switch circuit 408 so as to select the output signal of the GAP data generating circuit 407. The switch circuit 408 selects the output signal of the GAP data generating circuit 407 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. Next, the INDEX generating circuit 405 sends out the data to be recorded in the region INDEX. The control circuit 409, upon reaching the time for recording the region INDEX, sends out a control signal to the switch circuit 408 so as to select an output signal of the INDEX generating circuit 405. The switch circuit 408 selects the output signal of the INDEX generating circuit 405 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. The GAP data generating circuit 407 generates data to be recorded in the region G5, and sends out to the switch circuit 408. The control circuit 409, upon reaching the time for the region G5, sends out a control signal to the switch circuit 408 so as to select the output signal of the GAP data generating circuit 407. The switch circuit 408 selects the output signal of the GAP data generating circuit 407 according to the control signal from the control circuit 409, and sends out to the recording amplifier 410. The recording amplifier 410 sends out the output signal of the switch circuit 408 to the recording head 411, and the recording head 411 records in the magnetic tape 412. Thus, the recording apparatus in Fig. 4 is capable of recording the track pattern (B) shown in Fig. 3 on a magnetic tape. In the tape recorded by such recording apparatus, by reproducing the insert information recorded in the regions G1 and ITI in Fig. 3, tracking is controlled so that the head can trace accurately on the track, and insert recording of rewriting accurately at least one of the regions INDEX, A and V can be realized. A method of tracking by reproducing the regions G1 and ITI is described below. Fig. 5 shows a frequency spectrum of data row recorded in the regions G1 and ITI. As shown in Fig. 5, the frequency spectrum of the regions G1 and ITI is available in three types, F0, F1 and F2. A peak level at frequency f1 in the type F0 is much smaller than that in the type F1, and a peak level at frequency f2 in the type F0 is much smaller than that in the type F2. The type F1 possesses a peak at the frequency f1, and the peak level at the frequency f2 in the type F1 is much smaller than that in the type F2. The type F2 possesses a peak at the frequency f2, and the peak level at the frequency f, in the type F2 is much smaller than that in the type F1. Frequencies f1 and f2 in the embodiment are respectively 1/90 and 1/60 of the recording frequency. These patterns are disposed on the tape as shown in Fig. 6. In tracks before and after the track having the spectrum of the type F0, tracks of the types F1 and F2 are disposed. When the recording head is on the track of the type F0, by nature, since the spectrum of the type F0 does not possess peak at frequencies f1 and f2, peak would not be detected at frequencies f1 and f2 of the reproduced signal of the track of the type F0, but peaks are formed at frequencies f1 and f2 also in the reproduced signal of the type F0 by crosstalk from the adjacent tracks of the types F1 and F2. When the head is deviated in the direction of track of the type F1, the fl frequency component of the reproduced signal of the type F0 increases, and the f2 component decreases at the same time. To the contrary, when the head is deviated in the direction of the type F2, the frequency fl component decreases, and the frequency f2 component increases. Thus, by reproducing the track of the type F0, it is possible to detect how much the head is deviated in which direction to the track, and tracking is controlled by adjusting the tape feed speed so as to compensate for the deviation. A pilot signal is generated by recording the regions G1 and ITI as follows. The insert information to be recorded in the regions G1 and ITI is composed only of 10-bit codewords of which disparity in every 10 bits is +2, -2 and 0, and by regularly arranging the 10-bit codewords of which disparity in every 10 bits is +2, -2 and 0, the data row of each pattern is created. Fig. 7 shows an example of arrangement of codewords of which disparity in every 10 bits is ±2 and 0. The type F0 records only with 10-bit codewords of which disparity is 0. The types F1 and F2 repeat 10-bit codewords of +2, -2 and 0 in the period of pilot signal. Fig. 8 shows a change of cumulative value of disparity of recording patterns. The data of the type F1 repeats increase and decrease of the cumulative value of disparity in a period of 90 bits as shown in Fig. 8. By repeating increase and decrease in a period of 1/90 of recording frequency which is the period of the pilot signal, the pilot signal can be generated at a frequency of 1/90 of the recording frequency. This is because the disparity is a mean of codewords, and when the increase or decrease is periodic, the spectrum of the frequency corresponding to the period is enlarged, and this frequency component becomes a pilot signal. The recording pattern of the type F2 also generates a pilot signal at a frequency of 1/60 of the recording frequency because the cumulative value of disparity repeats increase and decrease in a period of 1/60 of the recording frequency similarly. Besides, by raising the absolute value of the disparity in every 10 bits, the amplitude of the pilot signal can be enlarged. The apparatus for reproducing digital signals is provided with a circuit (hereinafter called PLL) for generating usually a synchronization signal (clock) more stably than reproduced signal. In this embodiment, the region G1 not only generates a pilot signal, but also records run-up data for operating the PLL stably in order to accurately reproduce the data recorded behind the region G1 when reproducing. The region G1 is composed of three kinds of run-up data of which disparity is +2, 0 and -2. Fig. 9 shows a first example of the type F1 pattern in the region G1. The region G1 is composed of three kinds of run-up data, that is, run-up pattern A as run-up data with disparity of +2, run-up pattern B as run-up data with 0, and run-up pattern C with run-up data -2. By arranging three types of the run-up data as shown in Fig. 9, the cumulative value of disparity of every 10 bits increases or decreases as shown in Fig. 8, and therefore a pilot signal is generated at frequency f1. In the case of pattern of the type F0 or pattern of F2, the disparity in every 10 bits disposes three kinds of the run-up data as shown in Fig. 7. Fig. 10 and Fig. 11 show other examples of recording pattern of the type F1 in the region G1. In this embodiment, the region ITI not only generates a pilot signal, but also records position information of the regions A, V and INDEX on the tape in the track pattern in Fig. 3. In the case of insert recording of video signal or after-recording of audio signal, to replace the data of prerecorded regions A, V and INDEX, it is necessary to identify the data recorded positions correctly. In the region ITI, 64 sync blocks comprising synchronization codeword and ID codeword are recorded. In a specific sync block from the beginning of the region ITI, the number of that sync block is recorded, and this number is continuously recorded from the beginning sync block of the region ITI. By the number of the sync block detected from the reproduced signal, it is known at which position on the track the head is present. Accordingly, it is possible to determine when to record the data of the regions A, V and INDEX, so that the data can be rewritten at accurate positions. Hence, the regions G2 to G4 can be set shorter, and more audio and video data can be recorded. By detecting the region ITI, moreover, the recording positions of the regions A, V and INDEX are recognized in each track, so that insert or after-recording can be conducted if the entire track is largely deviated from the reference position. The region ITI is composed of 64 sync blocks comprising 30 bits each. Of the 64 sync blocks, the block number from the beginning is recorded in the specific sync block. Fig. 12 shows the configuration of sync blocks in the region ITI. This diagram shows a case in which the block number to be coded in the sync block is coded first from the LSB. A sync block is composed of synchronization codeword of 10 bits, an ID codeword-L of 10 bits, and an ID codeword-U of 10 bits. Fig. 13 shows an example of bit pattern of synchronization codeword of the region ITI. There are three types of synchronization codeword, that is SYNC-A with disparity +2, SYNC-B with 0, and SYNC-C with -2. When recording, there are three synchronization codewords, which are SYNC-A, SYNC-B and SYNC-C, but when detected by partial response 4, the beginning two bits are unstable, and the final eight bits are identical in all three types as shown in Fig. 8. From SYNC-A, SYNC-B and SYNC-C, a pilot signal is generated, and it is selected so that the cumulative value of the disparity may increase or decrease in the period of the pilot signal, and a synchronization codeword is obtained. Fig. 14 shows other example of bit pattern of synchronization codeword of the region ITI. The ID codeword-L is, same as the synchronization codeword, available in three types, that is, ID-L-A with disparity of +2, ID-L-B with disparity of 0, and IDL-C with disparity of -2. The ID codeword-L is divided into 8 bits of block number part and 2 bits of dummy part. In the block number part, lower three bits of the sync block number expressed in 6 bits are coded and recorded. Fig. 16 shows the coding method of the block number part of the ID code-word-L and the ID codeword-U of the region ITI. In Fig. 16, lower three bits of the block number are 6. As shown in Fig. 16, by repeating once each bit of the lower three bits of the block number, a six-bit code is obtained. ID-L-A and ID-L-B are pre-coded by 2T with the initial value of "01". ID-L-C is pre-coded by 2T with the initial value of "10". Adding two bits as initial value to the beginning of the 2T pre-coded 6 bits, an 8-bit code is obtained, and the disparity of the 8-bit code is 0 in block number in all three types. Since the disparity of 8 bits of the block number part is always 0, the disparity of the ID codeword-L is determined in the dummy part. The dummy part of ID-L-A of which disparity is +2 is "11", the dummy part of ID-L-B of which disparity is 0 is "01", and the dummy part ID-L-C of which disparity is -2 is "00". The ID code -L is selected so that the cumulative value of disparities may be increased or decreased in the period of pilot in order to generate a pilot signal from three types of ID-L-A, ID-L-B, and ID-L-C. The ID codeword-U is available in three types, same as the ID codeword-L, that is, ID-U-A with disparity of +2, ID-U-B with disparity of 0, and ID-U-C with disparity of -2. The ID codeword-U is, like the ID codeword-L shown in Fig. 15, divided into 8 bits of block number part and 2 bits of dummy part. In the block number part of these three types of the ID codeword-U, upper three bits of the sync block number expressed in 6 bits are coded and recorded. As shown in Fig. 16, each bit of upper three bits of the block number is repeated once, and a 6-bit codeword is obtained. ID-U-A and ID-U-B are pre-coded by 2T with the initial value of "01". ID-U-C is pre-coded by 2T with the initial value of "10". Adding two bits as initial value to the beginning of the 2T pre-coded 6 bits, an 8-bit codeword is obtained, and the disparity of the 8-bit codeword is 0 in the block number in all three types. Therefore, the dummy part also determines the disparity of the ID codeword-U. The dummy part of ID-U-A of which disparity is +2 is "11", the dummy part of ID-U-B of which disparity is 0 is "01", and the dummy part ID-U-C of which disparity is -2 is "00". The ID codeword-U is selected so that the cumulative value of disparities may increase or decrease in the period of pilot signal in order to generate a pilot signal from the three types above. Fig. 17 shows the sequence of selection of the synchronization codeword, ID codeword-L, and ID codeword-U in the region ITI. By composing the region ITI in this sequence. the cumulative value of disparities in every 10 bits is increased or decreased in the pilot period, so that a pilot signal can be generated. In the boundary of the regions G1 and ITI, too, by recording so that the increase or decrease of cumulative value of every 10 bits may be continuous, pilot signals continuous between the region G1 and the region ITI can be generated. Fig. 18 shows a block diagram of 2T pre-coding used in coding of ID codeword-L and ID codeword-U. Pre-coding of 2T is effected prior to recording in order to judge whether 1 or 0 in partial response 4 from the reproduced signal. In this embodiment, 2T pre-coding is effected on the 6-bit codeword obtained by repeating once each bit of the lower or upper three bits of the block number, and in D-FF circuit 1802 and D-FF circuit 1803 in Fig. 18, the values of 1, 0 or 0, 1 are respectively loaded as initial values. The initial values of the D-FF circuit 1802 and D-FF circuit 1803 are respectively 0 and 1 when the disparity of the ID codeword -L and ID codeword-U to be coded is +2 or 0, and 1 and 0 when the disparity is -2. Each bit of the input 6-bit codeword is calculated with the output of the D-FF circuit 1802 which is an output value from the 2T pre-coding circuit two bits before, by exclusive OR in an EOR circuit 1801, and the result is issued. In this way, the block number parts of the ID codeword-L and ID codeword-U can be detected by partial response 4. The above explanation relates to an example of coding and recording first from the LSB of each block number in region ITI, but it is also possible to code and record first from the MSB. Fig. 19 shows the constitution of sync block in such a case. In this case, the synchronization codeword is followed by ID codeword-U, which is followed by ID code-word-L. In upper 3 bits and lower 3 bits of block number coded in each ID codeword, upper bits are first coded. In the method of coding, same as in Fig. 15 for recording first from the LSB, each bit is repeated once to obtain a 6-bit codeword, and this 6-bit codeword is pre-coded by 2-T. In this case, however, upper bits are first pre-coded by 2-T. In this case, in the synchronization codeword, the same pattern as when recording the block number first from the LSB is used. In ID codeword-L, as shown in Fig. 16, since each bit of lower three bits of a block number is repeatedly recorded, a same value is reproduced twice, if there is no error, in the lower three bits of the block number to be reproduced. Therefore, whether the lower three bits of the two block numbers being reproduced are the same value or not may be utilized as the criterion for judging presence or absence of error. In the case of ID codeword-U, quite similarly, whether the upper three bits of two block numbers being reproduced are same or not may be utilized as the criterion for judging presence or absence of error. Fig. 1 shows an insert information generating circuit of the embodiment. A run-up pattern A generating circuit 101, a run-up pattern B generating circuit 102, and a run-up pattern C generating circuit 103 are circuits for generating run-up pattern A, run-up pattern B, and run-up pattern C, respectively. A SYNC-A generating circuit 104, a SYNC-B generating circuit 105, and a SYNC-C generating circuit 106 are respectively circuits for generating SYNC-A, SYNC-B, and SYNC-C. A block number generating circuit 113 is a circuit for generating a block number to be recorded in each sync block. An ID-L-A generating circuit 107, an ID-L-B generating circuit 108, and an ID-L-C generating circuit 109 respectively generate ID-L-A, ID-L-B, and ID-L-C by receiving lower 3 bits of the block number issued from the block number generating circuit 113. An ID-U-A generating circuit 110, an ID-U-B generating circuit 111, and an ID-U-C generating circuit 112 respectively generate ID-U-A, ID-U-B, and ID-U-C by receiving upper 3 bits of the block number issued from the block number generating circuit 113. A period generating circuit 114 issues a 2-bit control signal. This 2-bit control signal 0 in the first 40 bits when the pilot signal is 1/90 of the recording frequency as in the case of the type F1 pattern, and 1 in the next 10 bits, and 2 in the next 40 bits. In the F2 pattern, repeating 0 and 2 in every 30 bits, and it is always 1 in the F0 pattern. A period generating circuit 114 repeatedly issues the 2-bit control signal while recording the regions G1 and ITI. A switch circuit 115 selects the output of the run-up pattern A generating circuit 101 when the output of the period generating circuit 114 is 0, selects the output of the run-up pattern B generating circuit 102 when 1, and selects the output of the run-up pattern C generating circuit 103 when 2. A switch circuit 116 selects the output of the SYNC-A generating circuit 104 when the output of the period generating circuit 114 is 0, selects the output of the SYNC-B generating circuit 105 when the output of the period generating circuit 114 is 1, and selects the output of the SYNC-C generating circuit 106 when the output of the period generating circuit 114 is 2. A switch circuit 117 selects the output of the ID-L-A generating circuit 107 when the output of the period generating circuit 114 is 0, selects the output of the ID-L-B when the output of the period generating circuit 114 is 1, and selects the output of the ID-L-C generating circuit 109 when the output of the period generating circuit 114 is 2. A switch circuit 118 selects the output of the ID-U-A generating circuit 110 when the output of the period generating circuit 114 is 0, selects the output of the ID-U-B generating circuit 111 when the output of the period generating circuit 114 is 1, and selects the output of the ID-U-C generating circuit 112 when the output of the period generating circuit 114 is 2. A data change-over control circuit 120 issues a 2-bit control signal, and this control signal is 0 when recording the region G1, 1 when recording the synchronization codeword in the region ITI, 2 when recording the ID codeword-L of the region ITI, and 3 when recording the ID codeword-U of the region ITI. A switch circuit 119 selects the output of the switch circuit 115 when the control signal entered from the data changeover control circuit is 0. When the control signal from the data changeover control circuit is 1, the output of the switch circuit 116 is selected, when the control signal from the data changeover control circuit is 2, the output of the switch circuit 117 is selected, and when the control signal from the data changeover control circuit is 3, the output of the switch circuit 118 is selected. In this way, data of the region G1 to ITI can be issued from the switch circuit 119. The insert information generating circuit may be also realized in a circuit configuration shown in Fig. 2. The bit rows recorded in the regions G1 and ITI are predetermined bit rows. Therefore, by storing the bit rows recorded in the regions G1 and ITI in a memory device, the bit rows stored in the memory device are put out when recording. A memory 1 in Fig. 2 is a memory circuit, and bit rows to be recorded in the regions G1 and G2 are stored preliminarily. A memory 201 issues the stored bit rows according to the address signal of an address generating circuit 202. The address generating circuit 202 issues an address signal to the memory 201 so that the bit rows of G1 and ITI may be delivered from the memory 201. The memory 201 may be also realized by combining logic elements, instead of using memory device. In the foregoing embodiment, frequencies f1 and f2 of the pilot signals are 1/90 and 1/60 of the recording frequency, respectively. When frequencies f1 and f2 of the pilot signals are 1/60 and 1/40 of the recording frequency, respectively, by arranging the disparities of every 10 bits of bit rows of the regions G1 and ITI as shown in Fig. 20, the pilot signals can be generated at frequencies f1 and f2. By disposing 10-bit codewords in this way, in the case of the type F0 pattern, the cumulative value of disparities in every 10 bits is always 0, and the cumulative value of disparities in every bits of the type F1 pattern increases or decreases in a period of 60 bits. Besides, the cumulative value of disparities of every 10 bits of the type F2 pattern increases or decreases in a period of 40 bits. Thus, there are peaks at frequency f1 of the type F1 pattern and frequency f2 of the type F2 pattern. Meanwhile, the peak levels of frequency f1 and frequency f2 of the type F0 pattern are sufficiently smaller than the peak levels of frequency f1 of the type F1 pattern and frequency f2 of the type F2 pattern. The run-up patterns (run-up pattern A, run-up pattern B, run-up pattern C) for composing the region G1 in the case of the frequencies f1 and f2 at 1/60 and 1/40 of the recording frequency respectively, synchronization codewords (SYNC-A, SYNC-B, SYNC-C) for composing the region ITI, the ID codeword-U (ID-U-A, ID-U-B, ID-U-C), and the ID codeword-L (ID-L-A, ID-L-B, ID-L-C) can use exactly the same codewords as in the case of frequencies f1 and f2 at 1/90 and 1/60 of the recording frequency respectively. Meanwhile, the insert information generating circuit for generating data to be recorded in the regions G1 and ITI may be realized by the circuits shown in Fig. 1 and Fig. 2, same as at the case of the frequencies f1 and f2 of 1/90 and 1/60 of the recording frequency, respectively. The operation is described below in the case of the frequencies f1 and f2 of the period generating circuit 114 in Fig. 1 at 1/60 and 1/40, respectively. In the case of type F0, the period generating circuit 114 always issues 1, in the case of the type F1, 0 and 2 are issued alternately in every 30 bits, and in the case of the type F2, 0 and 2 are issued alternately in every 20 bits. A switch circuit 115 selects the output of the run-up pattern A generating circuit 101 when the output of the period generating circuit 114 is 0, selects the output of the run-up pattern B generating circuit 102 when the output of the period generating circuit 114 is 1, and selects the output of the run-up pattern C generating circuit 103 when the output of the period generating circuit 114 is 2. A switch circuit 116 selects the output of SYNC-A generating circuit 104 when the output of the period generating circuit 114 is 0, selects the output of the SYNC-B generating circuit 105 when the output of the period generating circuit 114 is 1, and selects the output of the SYNC-C generating circuit 106 when the output of the period generating circuit 114 is 2. A switch circuit 117 selects the output of the ID-L-A generating circuit 107 when the output of the period generating circuit 114 is 0, selects the output of the ID-L-B generating circuit 108 when the output of the period generating circuit 114 is 1, and selects the output of the ID-L-C generating circuit 109 when the output of the period generating circuit 114 is 2. A switch circuit 118 selects the output of the ID-U-A generating circuit 110 when the output of the period generating circuit 114 is 0, selects the output of the ID-U-B generating circuit 111 when the output of the period generating circuit 114 is 1, and selects the output of the ID-U-C generating circuit 112 when the output of the period generating circuit 114 is 2. The other blocks in Fig. 1 operate same as in the case of the frequencies f1 and f2 at 1/90 and 1/60, respectively. Explained next is the operation in the case of the pilot frequencies f1 and f2 of the period generating circuit 114 in Fig. 2 at 1/60 and 1/40, respectively. By preliminarily storing the data rows of the regions G1 and ITI when the frequencies f1 and f2 are 1/60 and 1/40 of the recording frequency respectively in a memory 201, the data rows stored at the time of recording are issued out. An address generating circuit 202 sends an address signal to a memory 201 so that the data rows in the regions G1 and ITI may be issued from the memory 201. Incidentally, the memory 201 may be realized also by combining logic elements, instead of memory elements.

Claims: A data recording method for recording digital data on a plurality of parallel tracks formed on a recording medium (412), each of said tracks having an insert information recording region provided at the beginning of the track and audio and video data recording regions, said method comprising the steps of: recording (411) at least one of audio data and video data on said audio and video recording regions of a track on the recording medium (412); generating (406) a plurality of ID codewords such that the cumulative value of the disparity which is defined as a difference in the number of 1's and 0's in every n bits varies periodically to generate a pilot signal which will be used for tracking control; recording (411) the generated ID codewords into the insert information recording region of the track on the recording medium, characterized in that the step of generating the plurality of ID codewords includes the step of: converting an m-bit data block into a 2m-bit data block by once repeating each bit of the m-bit data block, 2T pre-coding the m-bit data block with an initial bit value of 01 or 10 to obtain a (2m+2)-bit data block beginning with said initial bit value, and adding k dummy bits to the (2m+2)-bit data block to obtain an ID codeword having 2m+2+k bits, wherein the k dummy bits have a disparity between a total number of 1 bits and a total number of 0 bits which is +i, 0, or -i. A data recording method as claimed in claim 1, wherein a cumulative value of the disparity of each 2m+2+k; bits of the insert information varies from zero to a peak value and back to zero in a period which corresponds to a period of the pilot signal. A data recording method as claimed in claim 1 or 2, wherein a frequency of the pilot signal is 1/90, 1/60 or 1/40 of a recording frequency of the audio data and the video data. A data recording method as claimed in any of claims 1 to 3, wherein 2m+2+k equals 10, and wherein the period of the cumulative value of the disparities of the insert information is 90 bits, 60 bits or 40 bits.

Inventors: GOTO MAKOTO, ICHIKAWA KEI, IKETANI AKIRA, ISAKA HARUO, KAWAKAMI YASUNORI, GOTO, MAKOTO, ICHIKAWA, KEI, IKETANI, AKIRA, ISAKA, HARUO, KAWAKAMI, YASUNORI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: G11B15
IPC codes: G11B27, G11B15, G11B20