Integrated circuit and method with centralized control of edge transition detection pulse duration

Abstract: Circuitry for producing a transition detection signal of adequate and optimized duration is disclosed. A transition detection circuit is associated with each of the input terminals from which transitions are to initiate an operating cycle, such as precharge and equilibration in a memory access cycle. Each transition detection circuit produces, responsive to a logic transition at its associated terminal, a transition detection pulse. Those transition detection circuits which produce only brief transition detection pulses are coupled to a centralized summing circuit. The summing circuit generates the transition detection circuit from the logical combination of the transition detection circuits, and includes a delay circuit to lengthen the brief incoming transition detection pulse to the desired duration. In this way, a single placement of the summing circuit can be used to optimize the transition detection pulse duration for initiation of the operating cycle of the integrated circuit.

Description: This invention is in the field of integrated circuits, and more specifically is in the field of timing control of such circuits. Many modern integrated circuits utilize the detection of transitions at their input terminals to initiate an operating cycle. One type of integrated circuit that especially benefits from this technique are static memories, including both static random-access memories (SRAMs) and also read-only memories (ROMs) of both the programmable and mask-programmed variety. As is known in the art, such memories may either be implemented as stand-alone integrated circuit memory chips, or embedded within microprocessor or other VLSI or ULSI logic devices. These conventional static memories are generally operated in an asynchronous fashion, with memory access initiated upon receipt of an address value and an enable signal, and without requiring a clock signal to be presented thereto. While many static memories are "fully" static, in that peripheral circuitry such as address decoders, sense amplifiers, and input/output circuitry are maintained as fully operational, modern static memories now utilize internal dynamic clocking for low power and fast access operation. Since these internally clocked static memories do not receive an external clock signal from which internal clock signals may be generated, the technique of edge transition detection (ETD) is useful in producing a timing pulse from which the internal clock signals can be generated. Examples of memories including ETD (also referred to as "address transition detection" or "ATD") are described in Okuyama et al., "A 7.5-ns 32K X 8 CMOS SRAM," IEEE J. Solid State Circuits , Vol. 23, No. 5 (October 1988), pp. 1054-1059, Kohno et al., "A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization," IEEE J. Solid State Circuits , Vol. 23, No. 5 (October 1988), pp. 1060-1066, and Williams et al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE J. Solid State Circuits , Vol. 23, No. 5 (October 1988), pp, 1085-1094. An example of the use of ETD in input buffers, and an example of an ETD circuit, are described in my U.S. Patent No. 5,124,584, assigned to SGS-Thomson Microelectronics, Inc. US Patent No. 4,744,063 discloses a static memory having an address transition detector, an input data transition detector and a pulse signal generator. The pulse signal generator generates a pulse having a leading edge corresponding to detection by either the address transition detector or the data transition detector of a transition on the address or data signal lines. The duration of such pulse is determined by the pulse signal generator. US Patent No. 4,636,991 discloses a memory circuit using address transition detector to equilibrate bit-lines. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic states to generate a summation address signal for the row address. Similarly, outputs of transitions detectors for column address signals are summed in at least two logic stages to generate the summation address signal for a column address. US Patent No. 5,264,737 discloses a semiconductor memory integrated circuit with a circuit for producing a pulse in response to a transition at an address input, comprising a plurality of transition detection circuits, each associated with an input terminal, and a summing circuit comprising logic circuitry, a delay circuit and output circuitry, for generating a summed transition detection pulse having a lengthened, centrally controlled duration. Those in the art will appreciate that the generation of internal clock signals from edge transition detection makes the ETD pulse a critical timing parameter in static memories. On one hand, the ETD pulse must remain active long enough to be communicated to clocked circuits distributed around the chip, so as to successfully accomplish precharge and equilibration functions. On the other hand, the duration of the ETD pulse should not be maintained so long as to delay access. Referring now to Figure 1, an exemplary conventional integrated circuit memory chip 1 is illustrated in plan view, showing an example of the layout location of input pads 2 and their edge transition detection (ETD) circuits 4. As is known in the art, the number of inputs that are to be monitored for edge transition can be substantial in modern SRAMs, as high as fifty or greater in modern memories (i.e., twenty or more addresses, thirty-two or more data input terminals, and associated control signal inputs). The number of such input pads 2 and ETD circuits 4 shown in Figure 1 is much reduced from this, for purposes of clarity of description. In addition, pads other than input pads 2 are also present in integrated circuit 1 that will either not be subject to transition (e.g., power supply and ground pads) or are not to be monitored for this purpose (e.g., dedicated output pads). According to this example, each input pad 2 is associated with an ETD circuit 4, which detects transitions at input pad 2 and generates a pulsed signal responsive thereto. Conventionally, as shown in Figure 1, ETD circuits 4 are located on the chip near their associated input pad 2. Since the integrated circuit generates its internal clock signals for a memory cycle responsive to the detection of a transition at any one of the input pads 2, the output of each ETD circuit 4 is bussed to a summing circuit 6 (schematically illustrated as an OR function in Figure 1), which generates a signal ETD* from which the internal clock signals for an operating cycle of circuit 1 may be generated. Alternatively, some or all of the outputs of ETD circuits 4 may be combined in a wired-OR arrangement. Referring now to Figure 2a, ETD circuit 4 i associated with an input pad 2 i and according to a conventional design is illustrated and will now be described; of course, other types and designs of ETD circuits are also used in conventional circuit 1. The signal at input pad 2 i , after buffering by inverting input buffer 3 i , is communicated to ETD circuit 4 i as well as to the remainder of integrated circuit 1 (at node IN i ). As described in the U.S. Patent No. 5,124,584, ETD circuit 4 includes two legs 8a, 8b, each leg terminating at a corresponding NAND gate 12a, 12b. The outputs of NAND gates 12a and 12b are connected to inputs of NAND gate 10, the output of which drives line ETD i . Line ETD i is communicated to summing circuit 6 as shown in Figure 1. In addition, as described in the U.S. Patent No. 5,124,584, line ETD i may be used to control the latching of the input signal on node IN i for protection against spurious input pulses. First leg 8a and second leg 8b of ETD circuit 4 i each include a series of delay stages 14 implemented in the form of AND functions; for example, as shown in Figure 2b, each of delay stages 14 may be implemented as NAND gate 14a with its inputs connected to one another, followed by inverter 14b. In first leg 8a, node IN i is connected directly to one input of NAND gate 12a, and to both inputs of the first delay stage 14 in first leg 8a; the second input of NAND gate 12a receives the inverted output from the last delay stage 14 in first leg 8a. Similarly, in second leg 8b, the inverted state of node IN i is presented to a first input of NAND gate 12b and to both inputs of the first delay stage in leg 8b; the other input of NAND gate 12b receives the inverted output of the last delay stage 14 in second leg. As such, first and second legs 8a, 8b are substantially identical, except that complementary states are provided to their inputs. In operation, ETD circuit 4 i generates a high logic level pulse at the output of NAND gate 10, at line ETD i responsive to the receipt of a logic transition at input pad 2 i . For example, if input pad 2 i is initially high and node IN i is initially low, the output of NAND gates 12a and 12b will both be high, causing a low logic level to be driven by NAND gate 10 at line ETD i . Upon a high-to-low transition at input pad 2 i resulting in a low-to-high transition of node IN i , a high level is presented to one input of NAND gate 12a (the other input already having a high logic level thereat), causing NAND gate 12a to change state and present a low logic level to NAND gate 10 in combination with the high level previously driven by NAND gate 12b (which does not change due to this transition). This causes line ETD i to go to a high logic level until such time as the high level at node IN i propagates through delay stages 14 in first leg 8a to the second input of NAND gate 12a (as a low logic level), causing the output of NAND gate 12a to return high to force a low logic level at node ETD i . Second leg 8b operates in a similar fashion to generate the pulse at line ETD i responsive to a low-to-high transition at pad 2 i . As a result of the construction of ETD circuit 4 i , the duration of the pulse at line ETD i is determined by the delay period through the delay stages 14 in first and second legs 8a, 8b (depending upon the polarity of the input transition), and thus by the number of delay stages 14 in each of first and second legs 8a, 8b. For example, Figure 2c illustrates the construction of ETD circuit 4 D , in which the first and second legs 8a, 8b, respectively, have only two delay stages 14. As a result, the width of the pulse produced by ETD circuit 4 D at line ETD D , responsive to a transition at input node IN D , is shorter than that produced at line ETD i of Figure 2a. By way of further background, ETD circuit 4 D conventionally is used in connection with data input transition detection, in contrast with ETD circuit 4 i being conventionally used in connection with address input transition detection. As noted above, the duration of the edge transition detection pulse is a critical parameter in modern integrated circuits. However, in many high-speed integrated circuit designs, the design and selection of the proper ETD pulse width cannot be optimized until actual circuits are built and functionally tested under all voltage and temperature conditions. Specifically, it has been found in some first-revision circuits that the ETD pulse may be too short in some conditions, necessitating a design change to lengthen the ETD pulse. As is evident from Figures 2a and 2c, lengthening of the ETD pulse would be effected by the adding more delay stages 14 into each of the first and second legs 8a, 8b of each of the ETD circuits 4 i , 4 D in integrated circuit 1. The provision of additional delay stages into each of the ETD circuits 4 i , 4 D is quite inefficient from a layout standpoint, given that the additional elements must be provided for each one of the ETD circuits 4 i , 4 D . Furthermore, layout constraints may actually prevent the addition of delay stages 14, as has been particularly observed for input data ETD circuits 4 D at those locations that lack the chip surface area for additional gates, for example as due to the space required for output buffer and driver circuitry thereat. In addition, the characterization of the effects of varying ETD pulse durations, using conventional techniques such as focused ion beam or special test modes, is made cumbersome by the multiple placements of ETD circuits 4. It is therefore an object of the present invention to provide an edge transition detection circuit that provides efficient optimization of the duration of the edge transition detection pulse. It is a further object of the present invention to provide such a circuit with centralized delay stage placement, thus achieving improvements in chip layout efficiency. It is a further object of the present invention to provide such a circuit which enables individual ETD circuits associated with inputs to be implemented in minimal chip area. It is a further object of the present invention to provide delay stages that allow for lengthening of the pulse duration by more than 100% of the input pulse duration. Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings. According to the present invention there is provided an integrated circuit, comprising: a first plurality of transition detection circuits, each associated with one of a first plurality of input terminals, and each for generating a pulse of a first predetermined duration at an output responsive to a logic transition at its associated input terminal; a second plurality of transition detection circuits, each associated with one of a second plurality of input terminals, each for generating a pulse of a second predetermined duration, longer than the first duration, responsive to a logic transition at its associated input terminal; a summing circuit, having a plurality of inputs, each connected to the output of one of said first and second pluralities of transition detection circuits, said summing circuit for presenting, responsive to a pulse at the output of one of said first plurality of transition detection circuits, a summed transition detection pulse (ETD*), said summing circuit comprising: first logic circuitry having a plurality of inputs, each input coupled to an output of one of said first plurality of transition detection circuits, for presenting a signal at its output (DT) responsive to receiving a pulse from any one of said first plurality of transition detection circuits; a delay circuit coupled to the output (DT) of said first logic circuitry, for generating at its output a delayed lengthened pulse (DTD), of a third duration longer than the first duration, responsive to the output (DT) of said first logic circuitry; second logic circuitry having a plurality of inputs, each input coupled to an output of one of said second plurality of transition detection circuits, for presenting a signal at its output (ACT) responsive to receiving a pulse from any one of said second plurality of transition detection circuits; and output circuitry, coupled to the outputs of said first logic circuitry, said second logic circuitry, and said delay circuit, for generating the summed transition detection pulse (ETD*) responsive to either the signal at the output of said first logic circuitry, the signal at the output (ACT) of said second logic circuitry, or to the delayed lengthened pulse (DTD) at the output of said delay circuit. The present invention also provides a method of initiating an operating cycle of an integrated circuit, comprising: monitoring a first plurality of input terminals, each of the first plurality of input terminals being associated with one of a first plurality of transition detection circuits; each of the first plurality of transition detection circuits on detecting a logic transition at its associated input terminal, generating a pulse of a first predetermined duration at an output; communicating the pulses of the first duration to a first logic circuit which is coupled to the output of each of said first plurality of transition detection circuits and providing a first signal (DT) at the output of the first logic circuit in response to receiving a pulse from any one of the first plurality of transition detection circuits; monitoring a second plurality of input terminals, each of the second plurality of input terminals being associated with one of a second plurality of transition detection circuits; each of said second plurality of transition detection circuits on detecting a logic transition at its associated input terminal, generating a pulse of a second predetermined duration at an output, said second duration being longer than the first duration; communicating the pulses of the second duration to a second logic circuit which is coupled to the output of each of the second plurality of transition detection circuits and providing a second signal (ACT) at the output of the second logic circuit in response to receiving a pulse from any one of the second plurality of transition detection circuits; generating, with a delay circuit, a delayed lengthened pulse responsive to the first signal from the first circuit, said delayed lengthened pulse having a third duration substantially longer than said first duration; generating a summed transition detection pulse (ETD*) in output circuitry coupled to the outputs of the first logic circuit, said second logic circuit and said delay circuit, said output circuitry being responsive to the first signal, the second signal or to the delayed lengthened pulse; and forwarding the summed transition detection pulse as a transition detection signal (ETD*). Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 is a plan view of a conventional integrated circuit illustrating the relative positions of edge transition detection circuits together with a summing circuit. Figure 2a is an electrical diagram, in schematic form, of an edge transition detection circuit according to the prior art. Figure 2b is an electrical diagram, in schematic form, of a delay stage as used in the conventional circuit of Figure 2a. Figure 2c is an electrical diagram, in schematic form, of an edge transition detection circuit according to the prior art, and which produces a shorter pulse than that of Figure 2a. Figure 3 is an electrical diagram, in schematic and block form, of an edge transition and summing circuit according to the preferred embodiment of the invention. Figure 4 is a plan view of an integrated circuit according to the preferred embodiment of the invention, illustrating the relative positions of the edge transition detection circuits together and the summing circuit of Figure 3. Figure 5 is an electrical diagram, in schematic form, of a delay stage in the summing circuit according to the preferred embodiment of the invention. Figure 6 is a timing diagram illustrating the operation of the circuit of Figure 5. Figure 7 is an electrical diagram, in schematic form, of a delay stage in the summing circuit according to an alternative embodiment of the invention. Figure 8 is a timing diagram illustrating the operation of the circuit of Figure 7. Referring now to Figure 3, edge transition detection circuitry according to the preferred embodiment of the invention will now be described in detail. As shown schematically in Figure 3, a number of input terminals or pads 22a, for receiving address signals, are each connected to an associated address ETD circuit 24a. Write enable terminal 22w and chip enable terminal 22e are similarly connected to control signal ETD circuits 24w, 24e, respectively; in this way, edge transitions at these control terminals can also initiate an operating cycle according to the present invention. According to this example of the preferred embodiment of the invention, ETD circuits 24a, 24w, 24e are each constructed similarly as ETD circuit 4 i described above relative to Figure 2a. Similarly, input data terminals or pads 22d each receive input data, and are connected to an associated ETD circuit 24d that is constructed similarly as ETD circuit 4 D described above relative to Figure 2c. Accordingly, in this example of the preferred embodiment of the invention, the duration of the ETD pulse generated by address ETD circuits 24a, in the event of a transition at an address terminal 22a, is longer than that of the pulse generated by input data ETD circuits 24d responsive to a transition at a data input terminal 22d. For example, the duration of the pulse generated by address ETD circuits 24a and control signal ETD circuits 24w, 24e may be on the order of 8 to 10 nsec, while the duration of the pulse generated by input data ETD circuits 24d may be on the order of 3 to 4 nsec. According to the preferred embodiment of the invention, the outputs of each of the ETD circuits 24a, 24d, 24w, 24e are communicated to summing circuit 20, despite the difference in the duration of the produced ETD pulses. For the example of integrated circuit 100 shown in Figure 4, summing circuit 20 has a single placement and receives signals from ETD circuits 24 located across and around integrated circuit 100. The output of summing circuit 20, on line ETD*, is a pulse indicating that a transition at one of the input terminals (address, control or input data) has been detected, and that an operating cycle of the integrated circuit 100 is to be initiated. In addition, as noted above, the pulse on line ETD* is also used as a basis for the generation of internal clock signals for the initiated operating cycle, and for effecting precharge and equilibration in memory integrated circuits. As will become apparent from the following description, summing circuit 20 lengthens the duration of the ETD pulses produced by input data ETD circuits 24d, by way of a single placement of additional delay elements, for consistency with ETD pulses produced by address ETD circuits 24a and control signal ETD circuits 24w, 24e. Summing circuit 20 includes NOR function 25 which receives, at its inputs, the outputs of write enable ETD circuit 24w and chip enable ETD circuit 24e. Inputs to NOR function 26 in summing circuit 26 receive the outputs of each address ETD circuit 24a. NOR functions 25, 26 may each be implemented as the combination of multiple NOR functions, or alternatively may be implemented in wired-NOR fashion. The outputs of NOR functions 25, 26 are connected to corresponding inputs of NAND function 28, which drives line ACT at its output. Line ACT thus presents an active high pulse responsive to any one of address ETD circuits 24a or control ETD circuits 24w, 24e presenting an active high pulse upon a transition at its associated input terminal 22a, 22w, 22e, respectively. Summing circuit 20 also includes NOR functions 27 for processing of the input data ETD pulses. The output of each input data ETD circuit 24d is connected to a corresponding input of one of NOR functions 27. Summing circuit 20 preferably includes multiple NOR functions 27, such that the outputs of input data ETD circuits 24d are arranged in groups. Each of NOR functions 27 presents its output to NAND function 29, which drives line DT at its output. Line DT thus presents an active high pulse responsive to any one of input data ETD circuits 24d presenting an active high pulse upon a transition at its associated input data terminal 22d. Line ACT at the output of NAND function 28, and line DT at the output of NAND function 29, are each connected to respective inputs of NOR function 32 in summing circuit 32. Line DT is also connected to delay circuit 30, which presents a delayed signal on line DTD to a third input of NOR function 32. According to the preferred embodiment of the invention, delay circuit 30 lengthens the duration of the pulse generated by input data ETD circuits 24d, as will be described hereinbelow. NOR function 32 drives line ETD*, after inversion by inverter 33, to present a pulse corresponding to the logical OR of lines ACT, DT and DTD. The pulse on line ETD* is used to initiate an operating cycle in circuit 100 responsive to the detection of a transition at any of address terminals 22a, control terminals 22w, 22e, and input data terminals 22d. In this example, the pulse on line ETD* is an active high pulse, since the pulses on lines ACT, DT, DTD are all active high pulses. Delay circuit 30 may be implemented by way of any conventional delay elements, such as one or more logic stages in sequence. However, certain circuit arrangements have been found to be preferable for lengthening the duration of the ETD pulses by a large amount, and will now be described in detail. Referring now to Figure 5, the construction of delay circuit 30 for presenting a pulse on line DTD that is longer in duration than that on line DT, according to a first embodiment of the invention, will be described in detail. Delay circuit 30 includes NAND function 40 that receives, at a first input, the state of line DT inverted by inverter 35. The output of inverter 35 is also connected to both inputs of delay stage 36. In this example, delay stages 36, 38, 40 are constructed similarly as described hereinabove relative to Figure 2b, and thus correspond to a logical AND function having a propagation delay. Of course, the number of delay stages in delay circuit 30 may vary from one to many, depending upon the desired pulse width. The output of delay stage 36 is connected to a second input of NAND function 40, and to both inputs of the succeeding delay stage 38. Similarly, the output of delay stage 38 is connected to another input of NAND function 40 and to both inputs of delay stage 42; the output of delay stage 42 is connected to an input of NAND function 40. This construction of delay circuit 30 thus produces a pulse on line DTD having a duration defined by the duration of the pulse at line DT and the propagation delay through delay stages 36, 38, 42. Referring now to Figure 6, the operation of delay circuit 30 will now be described in detail. Prior to detection of an input transition (i.e., in steady-state), line DT is at a low logic level. The output of inverter 35 (shown in Figure 6 as OUT 35 ) is thus at a high logic level, causing the outputs of delay stages 36, 38, 42 (shown in Figure 6 as lines OUT 36 , OUT 38 , OUT 42 , respectively) to also be high. With all four inputs to NAND function 40 high, line DTD is driven low. In this condition, referring back to Figure 3, with all three lines ACT, DT, DTD at a low logic level, line ETD* also remains at a low logic level. Referring back to Figure 3, upon detection of a transition at an input data terminal 22d, the associated input data ETD circuit 24d will generate an active high pulse at its output, of a duration defined by the delay of ETD circuit 24d. This active high pulse is communicated to summing circuit 20, and applied to an input of NOR function 27 which, in turn, presents a low logic level to NAND function 29. As a result, an active high pulse is presented on line DT which has a duration corresponding to the propagation delay of the input data ETD circuit 24d that detected the transition. As noted above, due to layout and design limitations, this pulse duration may not be adequate for generation of internal clock signals and other signals, such as precharge and equilibration, that are necessary for integrated circuit 100 to initiate and perform an operating cycle. Referring back to Figure 6, the active high pulse on line DT causes a low logic level to be driven by inverter 35 on line OUT 35 , delayed by the propagation delay δ 35 of inverter 35. This low logic level is presented to an input of NAND function 50, producing a high logic level on line DTD after the propagation delay δ 40 of NAND function 40. For proper operation of summing circuit 30, the pulse on line DTD must overlap the pulse on line DT, such that the resulting pulse on line ETD* is a single, longer, pulse than the pulse on line DT. Accordingly, the sum of propagation delays δ 35 and δ 40 must be less than the duration of the pulse on line DT. Also responsive to the low level pulse at the output of inverter 35, delay stage 36 produces a low logic level at its output (OUT 36 ), delayed by the propagation delay δ 36 . This low logic level at the output of delay stage 36 is presented to NAND function 40, maintaining line DTD high after such time as line DT returns high and after the output of inverter 35 returns high. In order to maintain a single extended high logic level at line DTD, it is therefore important that the delay time δ 36 be shorter than the duration of the pulse on line DT, so that the low logic level at the output of delay stage 36 overlaps the low logic level at the output of inverter 35. The low logic level pulse originating at the output of inverter 35 propagates in similar fashion through delay stages 38 and 42. As shown in Figure 6, the output of delay stage 38 (OUT 38 ) goes low responsive to the falling edge of OUT 36 , delayed by propagation delay δ 38 of delay stage 38; similarly, the output of delay stage 42 (OUT 42 ) is driven low responsive to the falling edge of OUT 38 , delayed by propagation delay δ 42 of delay stage 42. Each low level output OUT 38 , OUT 42 is forwarded to NAND function 40 so as to overlap the previously generated low logic level, and maintaining line DTD high. In each case, it is important that none of the propagation delays δ 38 , δ 42 exceed the duration of the pulse at line DT to ensure that the output at line DTD does not prematurely return to a low logic level. The pulse on line DTD returns low responsive to output OUT 42 returning high, which occurs as the high-to-low transition of line DT propagates through delay circuit 30 to appear (as a low-to-high transition) at the output of delay stage 42, and propagates through NAND function 40. As illustrated in Figure 6, the logical OR of lines DT and DTD (and thus the active high pulse on line ETD*) has a duration that is the sum of the pulse duration on line DT and the propagation delay δ 30 through delay circuit 30. The propagation delay δ 30 is the sum of the propagation delays δ35, δ 36 , δ 38 , δ 42 and δ 40 . For example, typical propagation delays for inverter 35 and NAND function 40 according to conventional technology are on the order of 1 nsec, while typical propagation delays for delay stages 36, 38, 42 are on the order of 2 nsec. For a 3 nsec active high pulse on line DT generated by an input data ETD circuit 24d, summing circuit 20 according to this embodiment of the invention would produce an active high signal on line ETD* of 11 nsec (i.e., 3 nsec plus 8 nsec). Summing circuit 20 is thus able to lengthen the duration of the ETD signal pulse by the provision of a centrally located single placement of delay circuit 30, and thus in a manner that avoids having to replicate delay stages for each input terminal, and that allows for full chip area utilization at the critical locations near input terminal pads. This centralized placement of delay circuit 30 also greatly facilitates the adjustment of the ETD pulse duration by way of conventional techniques such as mask revision, focused ion beam, fuse programming, and special test mode operation. According to this embodiment of the invention, the duration of the transition detection pulses produced by address ETD circuits 24a and control signal ETD circuits 24w, 24e is on the order of 10 nsec, and as such summing circuit 20 is not required to provide lengthening thereof. Referring now to Figure 7, delay circuit 30' according to a second embodiment of the invention will now be described in detail. Delay circuit 30' can be substituted for delay circuit 30 of Figure 5 in summing circuit 20 shown in Figure 3. Lines DT and ACT are connected to inputs of NOR function 32 for driving line ETD* via inverter 33, as before. Line DT is also connected to inverter 43 which in turn drives both inputs of AND delay stage 45, as well as one input of each of AND delay stages 47, 49 and NAND function 50. AND delay stages 45, 47, 49 correspond to logical AND functions, and may be constructed as a NAND followed by an inverter as described hereinabove relative to Figure 2b. The output of AND delay stage 45 is connected to the second input of AND delay stage 47, while the output of AND delay stage 47 is connected to the second input of AND delay stage 49. The output of AND delay stage 49 is connected to the second input of NAND function 50, which drives line DTD at its output. Line DTD is connected to an input of NOR function 32, as before. The operation of delay stage 30' will now be described in detail relative to Figure 8. As in the case of delay stage 30 described hereinabove, line DT is at a low logic level in the steady-state condition of summing circuit 20, prior to detection of a transition at an input data terminal 22d. This forces high logic levels at the outputs of inverter 43 and AND delay stages 45, 47, 49 (i.e., OUT 43 , OUT 45 , OUT 47 , OUT 49 , respectively). As a result, both inputs to NAND function 50 are high and thus line DTD is at a low logic level. As described hereinabove relative to Figures 3 and 5, upon detection of an edge transition at one of input data terminals 22d, the associated input data ETD circuit 24d communicates an active high pulse, of relatively short duration, to the input of NOR function 27 in summing circuit 20. By operation of NAND function 29, line DT then presents an active high pulse to NOR function 32 (initiating a high logic level on line ETD*) and to inverter 43. The output of inverter 43 (OUT 43 ) makes a high-to-low transition responsive to the leading edge of the active high pulse on line DT, delayed by propagation delay δ 43 . This low level at the output of inverter 43 is presented to NAND function 50, which in turn drives line DTD high after the propagation delay δ 50 of NAND function 50. The low level at the output of inverter 43 is also presented to one input of each of AND delay stages 45, 47, 49, causing their outputs to go low after their respective propagation delays δ 45 , δ 47 , δ 49 . At the end of the active high pulse on line DT and after the propagation delay δ 43 , the output of inverter 43 (OUT 43 ) returns high. As shown in Figure 8, however, at this time, each of AND delay stages 45, 47, 49 maintains its output at a low logic levels. The output of AND delay stage 45 (OUT 45 ) remains low until the high logic level at OUT 43 has propagated through AND delay stage 45, at which time its output (OUT 45 ) returns high. To ensure that a single pulse at line DTD is generated, it is important that each of the propagation delays δ 45 , δ 47 , δ 49 of AND delay stages 45, 47, 49 be shorter than the duration of the pulse at line DT, so that the outputs of AND delay stages 45, 47, 49 are all driven low prior to the output of inverter 43 (OUT 43 ) returning to a high logic level. The high logic level returning at the output of AND delay stage 45 (OUT 45 ) is in turn presented to AND delay stage 47 which, after propagation delay δ 47 , drives a high logic level at its output (OUT 47 ). The high logic level of OUT 47 then propagates through AND delay stage 49, appearing at its output (OUT 49 ) after the propagation delay δ 49 , at which time NAND function 50 has high logic levels at both of its inputs. Line DTD then returns to a low logic level after propagation delay δ 50 through NAND function 50. As illustrated in Figure 8, and similarly as discussed above relative to delay circuit 30, the logical OR of lines DT and DTD (and thus the active high pulse on line ETD*) has a duration that is the sum of the pulse duration on line DT and the propagation delay δ 30' through delay circuit 30'. The propagation delay δ 30' is the sum of the propagation delays δ 43 , δ 45 , δ 47 , δ 49 and δ 50 . For example, for propagation delays for inverter 43 and NAND function 50 are on the order of 1 nsec and propagation delays for AND delay stages 45, 47, 49 are on the order of 2 nsec, summing circuit 20 according to this embodiment of the invention would produce an active high signal on line ETD* of 11 nsec in duration on receipt of an active high pulse on line DT of 3 nsec in duration. Similarly as noted above, delay circuit 30' in summing circuit 20 lengthens the duration of the ETD signal pulse without requiring replication of delay stages for each input terminal. Layout and design efficiency, particularly at locations near input terminal pads, as well as ease of pulse duration adjustment, are thus improved. Of course, delay circuit 30 may be constructed according to other implementations. Care must be taken, however, when the incoming pulses are less than 50% of the duration of the desired lengthened pulse, to ensure that a single lengthened pulse is produced rather than merely a second delayed pulse of the same duration. The preferred embodiments of delay circuits 30, 30' described hereinabove are effective for lengthening the transition detection pulses well beyond 100% of the duration of the incoming pulse, as noted in the above description. The preferred embodiment of the invention described hereinabove contemplates that the duration of the ETD pulse from address ETD circuits 24a and control signal ETD circuits 24w, 24e is adequate, and thus no lengthening is provided therefor in summing circuit 20. Of course, it will be appreciated that some of the outputs of address ETD circuits 241 and control signal ETD circuits 24w, 24e may also be forwarded to delay circuit 30 or 30', if shorter ETD pulses are produced thereby. This would provide additional layout and design efficiency, as the number of delay elements in address ETD circuits 241 and control signal ETD circuits 24w, 24e could be reduced. Further in the alternative, summing circuit 20 may be implemented to have a larger programmable number of delay stages in its delay circuit 30, 30' than that shown hereinabove. This would allow for device characterization and testing to select the optimal ETD pulse duration, in which case laser programming or, alternatively, mask programming may be performed to select the desired number of delay stages to effect the desired ETD pulse duration. Still further in the alternative, multiple summing circuits 20 may also be provided according to the present invention, especially for extremely large integrated circuit chips. Multiple summing circuits may also provided within the integrated circuit, especially when dictated by chip size or by the need for different ETD pulse durations for different operating cycles. In any event, the present invention provides the important advantages of allowing ETD circuits associated with, and located near, the input terminal pads to present pulses of short duration, thus saving chip area from that required in prior circuits for multiple placements of delay elements. The central summing circuit ensures standardization of ETD pulse durations for transitions from all appropriate input terminals, and also enables the use of a single set of delay stages for multiple input terminals, further improving layout efficiency. The duration of the ETD pulse may also be easily adjusted at the central summing circuit through mask revision, focused ion beam, fuse programming, special test mode operation, and other similar techniques. While the invention has been described herein relative to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.

Claims: An integrated circuit, comprising: a first plurality of transition detection circuits (24d), each associated with one of a first plurality of input terminals (22d), and each for generating a pulse of a first predetermined duration at an output responsive to a logic transition at its associated input terminal (22d); a second plurality of transition detection circuits (24a,24w,24e), each associated with one of a second plurality of input terminals (22a,22w,22e), each for generating a pulse of a second predetermined duration, longer than the first duration, responsive to a logic transition at its associated input terminal (22a,22w,22e); a summing circuit (20), having a plurality of inputs, each connected to the output of one of said first and second pluralities of transition detection circuits (24d), said summing circuit (20) for presenting, responsive to a pulse at the output of one of said first plurality of transition detection circuits (24d), a summed transition detection pulse (ETD*), said summing circuit (20) comprising: first logic circuitry (27,29) having a plurality of inputs, each input coupled to an output of one of said first plurality of transition detection circuits (24d), for presenting a signal at its output (DT) responsive to receiving a pulse from any one of said first plurality of transition detection circuits (24d); a delay circuit (30) coupled to the output (DT) of said first logic circuitry (27,29), for generating at its output a delayed lengthened pulse (DTD), of a third duration longer than the first duration, responsive to the output (DT) of said first logic circuitry (27,29); second logic circuitry (25,26,28) having a plurality of inputs, each input coupled to an output of one of said second plurality of transition detection circuits (24a,24w,24e), for presenting a signal at its output (ACT) responsive to receiving a pulse from any one of said second plurality of transition detection circuits (24a,24w,24e); and output circuitry (32,33), coupled to the outputs of said first logic circuitry (27,29), said second logic circuitry (25,26,28), and said delay circuit (30), for generating the summed transition detection pulse (ETD*) responsive to either the signal at the output of said first logic circuitry (24d), the signal at the output (ACT) of said second logic circuitry (25,26,28), or to the delayed lengthened pulse (DTD) at the output of said delay circuit (30). The circuit of claim 1, wherein said delay circuit (30) comprises: a plurality of delay stages (36,38,42), each having an input and an output, a first (36) one of said plurality of delay stages (36,38,42) having its input coupled to the output of said first logic circuitry (27,29), and the remainder of said plurality of delay stages (38,42) having their input coupled to the output of a preceding one of said plurality of delay stages (36,38), so that the signal generated by the first logic circuitry (27,29) propagates through the plurality of delay stages (36,38,42); a combining circuit (40), having an input coupled to the output of each of said plurality of delay stages (36,38,42), and having an output coupled to said output circuitry (32,33), for generating the delayed lengthened pulse (DTD) responsive to any one of said delay stages (36,38,42) presenting the propagated signal at its output. The circuit of claim 1, wherein the delay circuit comprises: a series of delay stages (45,47,49,50), each having first and second inputs, a first (45) one of said series of delay stages (45,47,49,50) having its first and second inputs coupled to the output of the first logic circuitry (27,29), each of the remainder of said series of delay stages (47,49,50) having its first input coupled to the output of the preceding one (45,47,49) of said plurality of delay stages and having its second input coupled to the output of said first logic circuitry (27,29) and wherein the last (50) of said series of delay stages has its output coupled to said output circuitry (32,33), for presenting the delayed lengthened pulse (DTD) thereto. The integrated circuit of any preceding claim, wherein the first plurality of input terminals (22d) are disposed near a plurality of edges of the integrated circuit; and wherein each of said first plurality of transition detection circuits (24d) are located near their associated input terminal (22d). The integrated circuit of any preceding claim, wherein the summed transition detection signal (ETD*) is used to initiate an operating cycle of the integrated circuit. The integrated circuit of any preceding claim, wherein the integrated circuit comprises a memory; and wherein the summed transition detection signal (ETD*) is used to initiate an access of the memory. The circuit of claim 3, wherein the first plurality of input terminals (22d) comprise data terminals and the second plurality of input terminals (22a,22w,22e) comprise address terminals (22a) of the integrated circuit. A method of initiating an operating cycle of an integrated circuit, comprising: monitoring a first plurality of input terminals (22d), each of the first plurality of input terminals being associated with one of a first plurality of transition detection circuits (24d); each of the first plurality of transition detection circuits (24d) on detecting a logic transition at its associated input terminal (22d), generating a pulse of a first predetermined duration at an output; communicating the pulses of the first duration to a first logic circuit (27,29) which is coupled to the output of each of said first plurality of transition detection circuits (24d) and providing a first signal (DT) at the output of the first logic circuit (27,29) in response to receiving a pulse from any one of the first plurality of transition detection circuits (24d); monitoring a second plurality of input terminals (22a,22w,22e), each of the second plurality of input terminals being associated with one of a second plurality of transition detection circuits (24a,24w,24e); each of said second plurality of transition detection circuits (24a,24w,24e) on detecting a logic transition at its associated input terminal (22a,22w,22e), generating a pulse of a second predetermined duration at an output, said second duration being longer than the first duration; communicating the pulses of the second duration to a second logic circuit (25,26,28) which is coupled to the output of each of the second plurality of transition detection circuits (24a,24w,24e) and providing a second signal (ACT) at the output of the second logic circuit (25,26,28) in response to receiving a pulse from any one of the second plurality of transition detection circuits (24a,24w,24e); generating, with a delay circuit (30), a delayed lengthened pulse (DTD) responsive to the first signal from the first circuit, said delayed lengthened pulse having a third duration substantially longer than said first duration; generating a summed transition detection pulse (ETD*) in output circuitry (32,33) coupled to the outputs of the first logic circuit (27,29), said second logic circuit (25,26,28) and said delay circuit (30), said output circuitry being responsive to the first signal, the second signal or to the delayed lengthened pulse; and forwarding the summed transition detection pulse as a transition detection signal (ETD*). The method of claim 8, wherein the second plurality of input terminals (22a,22w,22e) correspond to address terminals (24a). The method of claim 9, wherein the integrated circuit comprises a memory. The method of claim 8, 9 or 10 wherein the first plurality of input terminals (22d) correspond to data terminals.

Inventors: MCCLURE DAVID CHARLES, MCCLURE, DAVID CHARLES
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1994
Main classification: H03K5
IPC codes: H03K5, G11C8