Driving apparatus for liquid crystal display

Abstract: A driving apparatus for a liquid crystal display of a type sandwiching a layer of liquid crystal material capable of responding to a voltage of an effective value applied between row and column electrodes. The apparatus includes an image data buffer memory for storing and outputting a digital image data of one frame, transferred from an external circuit, in the form of an image data matrix; a matrix generator for outputting data having a predetermined orthogonal matrix; a converter for converting the image data with the use of the orthogonal matrix into an converted data matrix and for outputting the converted data matrix; a converted data buffer memory for storing and outputting the converted data matrix; a driver for driving the liquid crystal display in synchronism with a row signal, which applies the orthogonal matrix to the row electrodes of the liquid crystal display, and also a column signal which applies the converted data matrix to the column electrodes of the liquid crystal display.

Description: The present invention relates to a driving apparatus for a liquid crystal display utilizing an addressing technique effective to permit a fast responding STN (Super Twisted Nematic) simple matrix type liquid crystal display to provide images of high contrast. The liquid crystal display is nowadays used as one type of flat panel displays, an exemplary type of which is a STN simple matrix type liquid crystal display. As shown in Fig. 1, this STN simple matrix type liquid crystal display is of a simple structure includes a plurality of transparent, stripe-shaped first electrodes formed on a first glass substrate so as to extend in one direction, a corresponding number of similarly transparent, stripe-shaped second electrodes formed on a second glass plate so as to extend in a transverse direction perpendicular to such one direction to thereby form a matrix of row and column electrodes together with the first electrodes, and a layer of liquid crystal material sealingly sandwiched between the first and second glass substrates. Due to this peculiar structure, the STN liquid crystal display has an advantage in that it is inexpensive to make. With the advent of a STN liquid crystal display having a fast responding characteristic and capable of displaying time-varying image of a video-rate, the field of application of this STN liquid crystal display is now expanding. However, It has been found that the fast responding STN simple matrix type liquid crystal display is susceptible to a considerable reduction in image contrast if it is driven by the use of the conventional driving technique in which a select voltage is applied at a time to one of the row electrodes during one frame period while information to be applied to pixels aligned with such one of the row electrodes is supplied through the column electrodes. To avoid this considerable reduction in image contrast, a new driving technique has been suggested to improve the image contrast exhibited by the STN simple matrix type liquid crystal display by selecting the plural row electrodes simultaneously at a time and selecting a number of times one of the row electrodes during one frame period. This recently suggested driving technique is shown in will be discussed with reference to Fig. 2. A voltage proportional to a data having a predetermined orthogonal matrix is applied as a row signal to the row electrodes of the STN simple matrix type liquid crystal display. The orthogonal matrix referred to above consists of a data of two binary digits of "1" and "-1" or a data of three binary digits of "1", "0" and "-1", in which the inner product of arbitrarily chosen two different ones of the row vectors forming parts of the matrix or arbitrarily chosen two different ones of the column vector forming parts of the matrix necessarily be zero. Of the data having this matrix, the binary digits "1", "0" and "-1" are taken as Low, Middle and High levels, respectively, and are used as row signals. In other words, a three-digit driver is used for a row driver. Also, with respect to a digital image data for each frame to be displayed by the liquid crystal display, a product of the digital image date times the orthogonal matrix to be used for driving the row electrodes is determined and is then converted into a converted data. A voltage proportional to the value of each element of the converted data is applied, as a column signal, to the column electrode of the STN simple matrix type liquid crystal display. If the image data is of a multistep gradation, the converted date correspondingly represents a multi-level data and, therefore, an analog driver is employed for a column driver. In addition, since the use of this driving technique results in an increase of the column voltage of the column signal, it is inevitably necessary to use the column driver having a high breakdown voltage. Thus, when the two signals are applied to the two sets of the electrodes of the liquid crystal display, an effective voltage proportional to each element of the image data is accumulated in the row and column electrodes during one frame period. Since respective portions of the liquid crystal layer aligned with the pixels permit passage of light therethrough in dependence on the effective voltage between the row and column electrodes, an image can be displayed on the liquid crystal display. This newly suggested driving technique is described by T.J. Scheffer and B. Clifton in "Active Addressing Method for High-Contrast Video-Rate STN Displays" [1992 SID Digest of Technical Papers XXIII, 228-231 (1992)]; by B. Clifton and D. Prince in "Hardware Architectures for Video-Rate, Active Addressed STN Displays" [Proceedings 12th International Display Research Conference, 503-506 (1992)]; and by A.R. Corner and T.J. Scheffer in "Pulse-Height Modulation (PHM) Gray Shading Methods for Passive Matrix LCDs." (Proceedings 12th International Display Research Conference, 69-72 (1992)]. According to the first listed paper, it is described that the Walsh function as the orthonormal function for the row selection is effective to lower the voltage of the column signal. However, when the Walsh function discussed in this first listed paper is employed, a problem arises in that no high speed computational algorithm for the Hadamard conversion can be used in an arithmetic circuit for computing the column signal. The second listed paper introduces a specific structure of an arithmetic circuit for computing the column voltage. This arithmetic circuit is of a structure wherein computation is effected for each bit of the digital data. With this arithmetic circuit, a digital data signifying "0" cannot be recognized "0" and no multiplication of it by any other data can be omitted, and therefore, redundancy tends to occur in circuit configuration and computational speed. The last listed paper discloses the pulse-height modulation which is a method of modulating the column signal for accomplishing a gray shading. Although this last listed paper introduces an equation for calculating the virtual information element, this equation includes a multiplication and a square root and, therefore, a substantial loss occurs in circuit configuration and computational speed if the arithmetic circuit is so structured as to merely perform the equation. Although not discussed in any one of those papers, some problems are involved in developing liquid crystal displays which operate according to the newly suggested driving technique. In the first place, when an image corresponding to two fields transmitted according to the interlaced scanning system is non-interlaced to provide a single picture, data for different timings are simultaneously displayed and, therefore, distortion may occur in an edge of a moving object. In the second place, with the signal processing device based on this newly suggested driving method, computation is carried out to the column vectors of the image date to determine one of the converted data. To describe it with reference to the matrix of the image date shown in Fig. 2, the sequence of reading of each of the image data will be as follows. a 11 → a 21 → a 31 → a 41 → a 12 → a 22 → ··· → a 44 On the other hand, the sequence of writing of the image data will be as follows since the image data is inputted by means of a raster scanning. a 11 → a 12 → a 13 → a 14 → a 21 → a 22 → ··· → a 44 In other words, the direction of image data reading and the direction of image data writing are such as shown in Figs. 3(a) and 3(b), respectively. Thus, since the image data reading direction and the image data writing direction are different from each other, two buffer memories each capable of holding the image data are required. These buffer memories are alternately operated for each frame period to receive the image data for each row and to output for each column the image data of the previous frame period, respectively. On the other hand, while each element of the converted data represents an inner product between the column vector of the image data and the row vector of the orthogonal matrix, the row vectors of the orthogonal matrix for each column vector of one of the image data are computed in the sequence from the first row to the last row of the orthogonal matrix and, therefore, the column vectors of the image data are prepared in the following sequence. b 11 → b 21 → b 31 → b 41 → b 12 → b 22 → ··· → b 44 The converted data so prepared are supplied in units of a single row to the row driver as shown in Fig. 2, and therefore, the sequence of reading is as follows. b 11 → b 12 → b 13 → b 14 → b 21 → b 22 → ··· → b 44 Accordingly, even in the case of the converted data, each of the buffer memories must have a capacity corresponding to twice the size of the data as is the case with the image data. Where a color image is desired to be displayed, the image data are supplied after having been decomposed into R (red), G (green) and B (blue) image components. The use of an dedicated arithmetic circuit for the image data of each color, R, G or B, necessarily increases the size of the circuit configuration and, therefore, it is necessary to reduce the circuit configuration by integrating these arithmetic circuits to a single system. Also, the STN simple matrix type liquid crystal display having a fast responding characteristic of about 150 ms cannot be effectively used as a display device for displaying a time-varying image and has a problem in that afterimages tend to be observed. From EP-A-0 507 061, a driving apparatus for a liquid crystal display is known for providing driving signals to row and column electrodes. The driving apparatus comprises an input buffer memory for receiving video signals, a row signal generator and a column signal generator which generate predetermined orthogonal matrix data. These signals are processed and delivered as row signals and column signals to a liquid crystal display matrix. It is an object of the present invention to provide a driving apparatus for a liquid crystal of the type referred to above, wherein the image data corresponding to one field transmitted according to an interlaced scheme is displayed during one field period by displaying the data for one row in two rows, thereby avoiding any possible distortion of the edge of a moving object. The driving apparatus for a liquid crystal display according to the invention is structured as defined in claim 1. In a preferred embodiment, as defined in claim 2, the computation is carried out by the use of a simplified circuit utilizing a table provided with values of virtual rows so that the arithmetic circuit can be reduced in size. In a further embodiment of the present invention, as defined in claim 3, without performing computation of the digital data for each bit, a multiplication by a digital data signifying "0" is dispensed with by taking all bits as a real number, thereby reducing the size of the necessary arithmetic circuit. Other features of the present invention will become clear from the following description taken in conjunction with preferred embodiments thereof with reference to the accompanying drawings, in which like parts are designated by like reference numerals and in which: Fig. 1 is a schematic perspective view of the STN simple matrix type liquid crystal display; Fig. 2 is a schematic diagram showing a concept of the driving method in which a plurality of rows are selected simultaneously; Figs. 3(a) and 3(b) are schematic diagrams showing respective directions of writing and reading image data, respectively, which take place during the practice of the driving method in which the plural rows are selected simultaneously; Fig. 4 is a circuit block diagram showing a first embodiment of the present invention; Fig. 5 is a circuit block diagram showing an inverter group employed in the first embodiment shown in Fig. 4; Fig. 6 is a circuit block diagram showing an adder network employed in the first embodiment shown in Fig. 4; Fig. 7 is a block diagram showing a concept of the driving method in which the plural rows are simultaneously selected when a row drive block is employed in the first embodiment shown in Fig. 4; Fig. 8 is a block diagram showing the details of a switch employed in the first embodiment shown in Fig. 4; Fig. 9 is a circuit block diagram showing a virtual row forming circuit 3 employed in the first embodiment shown in Fig. 4; Fig. 10(a) is a circuit block diagram showing the details of an image data buffer memory employed in the first embodiment shown in Fig. 4; Fig. 10(b) is a circuit block diagram showing the details of a converted data buffer memory employed in the first embodiment shown in Fig. 4; Fig. 11 is a diagram showing the lay-out of the image data within a two-dimensional buffer memory forming the image data buffer memory; and Fig. 12 is a diagram showing an operation of the image data buffer memory. A driving apparatus for the simple matrix type liquid crystal display according to the present invention will be described in connection with preferred embodiments thereof with reference to the accompanying drawings. Fig. 4 illustrates a circuit block diagram of the driving apparatus according to the first embodiment of the present invention. Referring now to Fig. 4, an image data buffer memory 1 temporarily stores, in the form of a matrix A 1 , an image data supplied from an external circuit and corresponding to one field (L rows and M columns. M represents a natural number and L represents a natural number smaller than N 1 .) and then sequentially outputs a column vector of the matrix A 1 . This image data is a digital data of D bits (D represents a natural number equal to or greater than 2.) in which a single data corresponds to a value from "1" to "-1". A column register 2 sequentially loads and then latches data of the column vectors of the matrix A 1 outputted from the image data buffer memory 1. A matrix memory 10 stores all data of an orthogonal matrix H 1 of N 1 rows and N 1 columns (N 1 representing a natural number) which take two digits of "1" and "-1". Specifically, the matrix memory 10 stores all data as a logic Low when they take the value of "1", but as a logic High when they take the value of "-1". An address generating circuit 11 reads out a data written at a specific address in the matrix memory 10 when such address is specified. A row register 12 temporarily stores a data of one row of the matrix H 1 read out from the matrix memory 10. In the description which follows, it is assumed that the row register 12 stores a data of the i-th row vector (i representing a natural number equal to or smaller than N 1 ) of the matrix H 1 while the column register 2 stores a data of the j-th column vector (j representing a natural number equal to or smaller than M) of the matrix A 1 . A virtual row forming circuit 3 calculates, for each column, a value necessary to adjust the sum of squares of the data for one column to a single constant for all columns and then add the virtual row to the last row of the matrix A 1 . An inverter group 4 comprises, as shown in Fig. 5, an XOR array 401 including D × L XOR gates and an adder group 402 including L adders and is operable to calculate a complemental number of 2 of the k-th digital data (k representing a natural number equal to or smaller than L) of D bits of the column register 2 only when the k-th data of the row register 12 is "-1", i.e., a logic High, and then to output it after having reversed the sign thereof. In other words, it corresponds to a calculation of the product between the k-th data of the row register 12 and the k-th data of the column register 2. An adder network 5 repeats (L - 1) times a computation, by which each neighboring data of the L D-bit data outputted from the inverter group 4 are summed together to provide a single data, until the single data is finally obtained and then outputs the total of output data outputted from the inverter group 4. Fig. 6 illustrates an example of the adder network 5 in which L is 8. Referring to Fig. 6, adders 501 to 504 constitute a D-bit + D-bit adder circuit; adders 505 and 506 constitute a (D + 1)-bit + (D + 1)-bit adder circuit; and an adder 506 constitutes a (D + 2)-bit + (D + 2)-bit adder circuit. If the data inputted is of D bits, the data outputted is (D + 3) bits. An adder 6 is operable to sum together the output data of the virtual row forming circuit 3 and the output data of the adder network 5. However, since the N 1 -th column data of the matrix H 1 is such that "1" and "-1" alternate with each other, outputting of the output data of the virtual row forming circuit 3 with its sign alternately reversed, corresponds to a virtual expansion of the matrix A 1 to a matrix having N 1 rows with information on the virtual row treated as the N 1 -th row data of the matrix A 1 . Also, the operation of the adder 6 corresponds to that, when N 1 is equal to or greater than L + 2, data from the (L + 1)-th row to the (N 1 - 1)-th row are regarded "0" and any computation of these "0"s with other data is omitted. Output data from the adder 6 are supplied to a converted data buffer memory 7 and stored temporarily therein in the form of a data of a matrix B 1 corresponding to the product between the matrix H 1 and the matrix A 1 . On the other hand, the simple matrix type liquid crystal display 16 is a simple matrix type liquid display having (2 × L) rows and M columns. A row voltage register 13 is a shift register having (2 × N 1 ) bits and is operable to load data for the i-th row of the matrix H 1 at a timing i which corresponds to one field period divided equally by N 1 , but to load the single output data of the matrix memory 10 two times since the operating speed thereof is twice the speed at which output data of the matrix memory 10 switches. In other words, the K-column data of the matrix H 1 is stored at the (2 × k - 1)-th and (2 × k)-th bits of the row voltage register 13. A switch 14 is, as shown in Fig. 7, comprised of (2 x L) switches which operate in response to a vertical synchronizing signal. More specifically, these switches forming the switch 14 are switched to a lower position, as viewed in Fig. 7, in response to a vertical synchronizing signal applied during an even-numbered field, but to an upper position as viewed in Fig. 7 in response to a vertical synchronizing signal applied during an odd-numbered field. In other words, during the odd-numbered field, a row driver 15 applies a voltage, corresponding to the data of the second bit to the (2 × L + 1)-th bit of the row voltage register 13, to the (2 × L) row electrodes of the simple matrix type liquid crystal display 16, but during the even-numbered field, the row driver 15 applies a voltage, corresponding to the first bit to the (2 × L)-th bit of the row voltage register 13 to the (2 × L) row electrodes of the simple matrix type liquid crystal display 16. A converted data buffer memory 7 is operable to supply to a digital-to-analog (D/A) converter 8 all data of the matrix B 1 in the order from an intersection between the first row and the first column to the intersection between the first row and the M-th column and then down to the N 1 -th row, which converter 8 subsequently converts the digital values, sequentially supplied from the converted data buffer memory 7, into corresponding analog values and then output those analog values. A column driver 9 is operable to apply to the M column electrodes of the simple matrix type liquid crystal display 16 voltages proportional to the analog values corresponding to the M data at the i-th row of the matrix B 1 which have been converted by the D/A converter 8 at a timing i. Of these various component parts, the column register 2, the inverter group 4, the adder network 5 and the adder 6 altogether constitute an arithmetic block 150 for performing a multiplication and a summation; the virtual row forming circuit 3 and the arithmetic block 150 altogether constitute a conversion block 100 for converting the matrix A 1 into the matrix E 1 ; the matrix memory 10, the address generating circuit 11 and the row register 12 altogether constitute a matrix generating block 200; the row voltage register 13, the switch 14 and the row driver 15 altogether constitute a row driving block 300 for driving the row electrodes of the simple matrix type liquid crystal display 16; and the D/A converter 8 and the column driver 9 altogether constitute a column driving block 400 for driving the column electrodes of the simple matrix type liquid crystal display 16. Fig. 8 illustrates a method of driving the STN simple matrix type liquid crystal display which can be employed when these component parts as discussed above are employed. The image data and the converted data both shown in Fig. 8 are those corresponding to one field. As shown in Fig. 8, although the neighboring row electrodes of the liquid crystal display are driven by the same row signal, the same row signal is applied to drive, during the even-numbered field, each neighboring row electrodes displaced every row with respect to those during the odd-numbered field. When an image corresponding to one frame is displayed by the simple matrix type liquid crystal display according to the driving method shown in Fig. 8, the resolution may be lowered since the data for one row is displayed over two rows, but no distortion of an edge of a moving object such as observed when the images corresponding to two fields transmitted according to the interlaced scheme are merged together is observed. The nature of the matrix H 1 will now be described. Supposing the circulant Hadamard matrix H 0 of N 1 orders which is an orthogonal matrix having data consisting of two digits "1" and "-1", the circulant Hadamard matrix H 0 may be considered a circulant matrix of (N 1 - 1) orders except for each of the first row and the first column which contain only "1". By reversing the sign of every other data of the matrix H 1 with respect to any of the direction of the rows and that of the columns, a new matrix is formed. By way of example, the circulant Hadamard matrix shown in the following equation (1) can result in a new matrix shown in the following equation (2). The matrix H 1 so obtained is still an orthogonal matrix in which, in a similar manner to the first row and the first column of the matrix H 0 , none of the rows and the columns of the matrix H 1 contain data of the same value, and therefore, the voltage of the column signal can be lowered. The virtual row forming circuit 3 performs a computation using the value of each virtual row, more specifically the following equation (3). If the computation is carried out as stipulated in the equation (3), the circuit configuration will become large and, therefore, the virtual row forming circuit 3 is so constructed as shown in Fig. 9 to simplify the computation. Referring now to Fig. 9, a multiplier circuit 301 calculates the square of one image data supplied from the image data buffer memory 1 while an accumulator circuit 302 accumulates an output data from the multiplier circuit 301 to calculate the sum of the squares of the image data for one row. A table memory 303 stores value of virtual rows corresponding to the sum of the squares of the image data for one row and the data from the table memory 303 is read out by the use of an output data from the accumulator circuit 302. Also, the respective operation of the image data buffer memory 1 and the converted data buffer memory 7 will now be described with reference to Figs. 10(a) and 10(b). Referring first to Fig. 10(a), the image data inputted to a selector 101 are transferred by raster scanning and, assuming that they have been separated into R, G and B data each having a matrix of three rows and four columns, the R, G and B data can be expressed by the following equations (4), (5) and (6), respectively. In the following description, the operation in which the data are transferred by means of an ordinary method such as a raster scanning technique will be referred to as a horizontal scanning while the operation in which the data are transferred with the vertical and horizontal directions reversed relative to those in the ordinary method will be referred to as a vertical scanning. A counter 108 outputs 0 to 3 repeatedly to the selector 101. Based on the output data from the counter 108, the selector 101 selects two-dimensional buffer memories 102, 103, 104 and 105 and then outputs the input data to the selected two-dimensional buffer memories. Each of the two-dimensional buffer memories 102 to 105 has a memory area of three rows and three columns and, before the data are written at a specified address, the data stored at such specified address are read out. An address generating circuit 107 generates an address necessary to permit the horizontal and vertical scannings to be repeated in the two-dimensional buffer memories for each field. A selector 106 operates, based on the output data from the counter 108, to select the two-dimensional buffer memories 102 to 105 and to cause output data to be outputted from the selected two-dimensional buffer memories. As a result, the three image data so inputted are inputted to the image data buffer memory 1 in the form of one image data expressed by the following equation (7) and are transferred to the two-dimensional buffer memories 102 to 105 in the form of respective data expressed by the following equations (8), (9), (10) and (11). In this example, while each of the two-dimensional buffer memories 102 to 105 performs a writing by means of the horizontal scanning, each of the two-dimensional buffer memories 102 to 105 performs the vertical scanning during the next succeeding field since it utilizes the address outputted from the address generating circuit 107. Also, since before the data writing, the reading of the data one field prior to the current field is carried out, the image data buffer memory 1 consequently outputs one column of data of the image data sequentially to the conversion block 100. Fig. 11 illustrates how the image data are arranged in the two-dimensional memories forming such image data buffer memory 1. As shown in Fig. 11, in a condition similar to the definition of the rows and the columns in the two-dimensional buffer memories which has been reversed for each field period, the image data are stored. Fig. 12 illustrates the operation of the entire image data buffer memory 1. Referring to Fig. 12, the image data inputted are sequentially distributed to the two-dimensional buffer memories forming the image data buffer memory 1 and, in each of the two-dimensional buffer memories, the direction of operation is switched for each frame period to accomplish data reading and data writing simultaneously. Hereinafter, the operation of the converted data buffer memory 7 will be described. Referring now to Fig. 10(b), a counter 708 outputs 0 to 3 repeatedly to a selector 701. Based on the output data from the counter 708, the selector 701 selects two-dimensional buffer memories 702, 703, 704 and 704 and then outputs the input data to the selected two-dimensional buffer memories. Each of the two-dimensional buffer memories 702 to 705 has a memory area of three rows and three columns and, before the data are written at a specified address, the data stored at such specified address are read out. An address generating circuit 707 generates an address necessary to permit the horizontal and vertical scannings to be repeated in the two-dimensional buffer memories for each field. A selector 706 operates, based on the output data from the counter 708, to select the two-dimensional buffer memories 702 to 705 and to cause output data to be outputted from the selected two-dimensional buffer memories. The converted data, shown by the equation (13) below, which have been outputted from the conversion block 100 are outputted by means of the vertical scanning in the sequence of tr11, tr21, tr31, tg11, tg21, tg31, ····· and are, therefore, outputted to the two-dimensional buffer memories 702 to 705 in the form of respective data expressed by the following equations (14), (15), (16) and (17). In this example, while each of the two-dimensional buffer memories 702 to 705 performs a writing by means of the vertical scanning, each of the two-dimensional buffer memories 702 to 705 performs the horizontal scanning during the next succeeding field since it utilizes the address outputted from the address generating circuit 707. Also, since before the data writing, the reading of the data one field prior to the current field then written at such address is carried out, the image data buffer memory 7 consequently outputs one row of data of the image data, represented by the equation (13) above, sequentially to the D/A converter 8. As hereinabove described, the image data buffer memory 1 even though it has a capacity equal to the size of the image data is possible to temporarily store the image data transferred by the horizontal scanning and then to read the image data out by the vertical scanning. The converted data buffer memory 7 even though it has a capacity equal to the size of the converted data is possible to temporarily store the converted data transferred by the vertical scanning and then to read the converted data out by the horizontal scanning. At the same time, the image data buffer memory 1 compiles the R, G and B image data into a single image data and, therefore, arithmetic circuits (conversion block 100) for processing the R, G and B image data, respectively, can easily be unified into a single system. It is to be noted that, if the data at the N 1 -th column of the matrix H 1 outputted from the row register 12 are inputted to the virtual row forming circuit 3 and the virtual row forming circuit 3 reverses the sign of information of the virtual row when the data are "-1" (logic High) and then outputs it, similar effects can be obtained. Also, in the adder network 5, even when L is not the power of 2, and if by suitably combining values of L and repeating a summation of the two values (L - 1) times, the total of the L data can be calculated and, therefore, similar effects can be obtained.

Claims: A driving apparatus for a liquid crystal display (16) of a type sandwiching a layer of liquid crystal material capable of responding to a voltage of an effective value applied between row and column electrodes, which apparatus comprises: an image data buffer memory (1) for storing and outputting a digital image data of one frame, transferred from an external circuit, in the form of an image data matrix; a matrix generating means (200) for outputting data having a predetermined orthogonal matrix; a conversion means (100) for converting the image data with the use of the orthogonal matrix into an converted data matrix and for outputting the converted data matrix; a converted data buffer memory (7) for storing and outputting the converted data matrix; and a row driving means (300; 13, 14, 15) for driving the liquid crystal display in synchronism with a row signal, which applies the orthogonal matrix to the row electrodes of the liquid crystal display, and a column driving means (400) which applies the converted data matrix to the column electrodes of the liquid crystal display (16); wherein in case of interlaced image data inputted from the external circuit, each of said image data buffer memory (1) and said converted data buffer memory (7) stores data corresponding to one field, and wherein said row driving means (300; 13, 14, 15) applies one signal of the row signal to the neighboring two row electrodes of the liquid crystal display (16) during an odd-numbered field period and, during an even-numbered field period, to the neighboring two row electrodes which have been shifted by a value corresponding to one row with respect to those during an odd-numbered field period. The driving apparatus as claimed in claim 1, wherein said conversion means (100) comprises a virtual row forming means (3) for calculating a value necessary to make constant for all columns the sum of the squares of data on one column of the image data matrix which comprises discrete values corresponding to real numbers of 1 to -1 and for adding the calculated value virtually to the last row of the image data matrix as information for a virtual row; and an arithmetic means (150) for calculating the product of the two matrixes; wherein said virtual row forming means (3) is operable to calculate the information for the virtual row by making reference to a predetermined table when all data for one column of the image data are to be transferred from the image data buffer memory (1) to the arithmetic means (150); and wherein said arithmetic means (150) calculates the products of the two matrixes while taking the discrete values corresponding to the real numbers of 1 to -1 forming the image data matrix as a single value. The driving apparatus as claimed in claim 2, wherein said arithmetic means (150) is operable, in the event that a length of the orthogonal matrix conforming to a direction of the rows differs from a length of the image data matrix conforming to a direction of the columns, to add to the image data matrix rows in which data are zero, to thereby adjust the length of the orthogonal matrix conforming to the direction of the rows to the length of the image data matrix conforming to the direction of the columns.

Inventors: FUKUI YASUHITO, MATSUMOTO TOKIKAZU, YUMINE MANABU, FUKUI, YASUHITO, MATSUMOTO, TOKIKAZU, YUMINE, MANABU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1994
Main classification: G09G3
IPC codes: G09G3