SYSTEM FOR DYNAMICALLY ALLOCATING MEMORY REGISTERS FOR FORMING PSEUDO QUEUES

Abstract: A queue system comprising a plurality of queues (20-23) where each is defined by a set of criteria, the queue system comprises a plurality of header registers (1-3) where each header register defines a queue in the queue system and a plurality of task registers where each task register can be associated with each queue (20-23) in the queue system. Each header register has a unique address and contains a previous field and a next field. Each previous field and said next field store the address of another register in a given queue such that each queue is formed in a double link structure. Control means is provided for dynamically assigning task registers to queues (20-23) by controlling the addresses in the previous and next fields in each header and task registers such that each of said task registers is always assigned to a queue in the queue system.

Description: SYSTEM FOR DYNAMICALLY ALLOCATING MEMORY REGISTERS FOR FORMING PSEUDO QUEUES A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any one of the patent documents or the patent disclosure as it appears in the United States Patent & Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. CROSS-REFERENCE TO RELATED APPLICATIONS The following copending U.S. patent application is assigned to the assignee of the present application, is related to the present application and its disclosures is incorporated herein by reference: (A) Ser. No. 08/006,457 filed January 21, 1993, by Stephen R. Cornaby and entitled SYSTEM FOR ALLOCATING TASKS BETWEEN TWO ACTUATORS SERVICING THE SAME MAGNETIC DISK MEDIA IN A SINGLE DISK DRIVE. BACKGROUND OF THE INVENTION Field of the Invention The invention relates to a system for establishing queues within a processing system and for the effective movement of data between the established queues. Description of the Related Art Many computer systems employ queues for managing the transferring of tasks and data within the computing system. Queues can be of many types, such as the first in first out queue (FIFO) where the entries stored in the queue are read from the queue in the sequence that the entries were stored in the queue. Another type of queue is the last in first out queue (LIFO) where the last entry stored in the queue is the first entry read out of the queue. This is to say the newest data stored in the queue will be the first data read out of the queue. Queues have been constructed from hardware registers and from dedicated portions of a memory, acting as a software register, where the queue is operated under the control of a program in the processor. A queue formed from a memory is described in the text Micro-processor Application Handbook. Editor-in-Chief David F. Stout, McGraw-Hill Book Company, 1982. The author discusses in Section 17.6, entitled "A Task-Scheduling Executive", the formation of a task queue using a forward linked structure. The forward link structure is formed by having each queue's entry contain a pointer to the address of the next queue entry. A queue formed by the forward link process will define the number and sequence of the registers in the queue at any given instant of time. Further, in many processing systems it is desired to move tasks that are defined as entries within the queue from one queue to another queue where each queue is used to specify a course of action to be taken with regard to the entries in that queue. Normally a task is removed from a queue and physically transferred into another queue. The movement of tasks between queues can be a time consuming process and subjects the task to errors generated during the transfer of the task, thereby requiring error recovery procedures to be invoked or attempt a retry transfer operation. SUMMARY OF THE INVENTION It is an object of the invention to provide a queue system for generating a plurality of queues where each queue can include any task registers in the system. Another object of the invention is that the queues within the queue system are not limited to a fixed length. It is another object of the invention to have a queue system which allows the queues within the system to be of various types of queues. It is another object of the invention to structure the queues in the queue system using a double-linked pointer structure where each register contains a pointer to the previous and next register in the queue in which the register resides at that instance in time. Briefly, this invention is directed to the formation of a plurality of queues from a dedicated set of memory registers within a random access memory unit. The memory registers are either header registers or task registers. Each queue has a specified header register and those task registers assigned to that queue. A task register is always assigned to a queue within the queue system. All registers contains at least two fields, a previous field and a next field. For any register used within the queue system, the previous field will contain the address of the preceding register in that queue and the next field containing the address of the following register in the queue. One queue is designated as an empty queue which will contain those task registers which are not presently being used in one of the active queues in the queue system. Task registers are effectively moved between queues by changing the contents of the next and previous fields of the register to be moved and the next and previous fields of the other registers in the queue which will be affected by the insertion or removal of the task register to be inserted or removed from the queue. The task registers are not physically moved between queues but are effectively moved by controlling the previous and next fields of the register, thereby allowing the formation of pseudo queues within the queue system where the length of each pseudo queue is defined by the number of task registers linked to the header register for that queue at any given instant of time. A control means is provided for performing procedures for inserting and removing task register from queues. Finally, the different type of queues may be included in a queue system. For example, one queue may be a first in first out queue, a second queue may be a last in first out queue, a third queue may be a queue ordered by address and a fourth queue may be a queue ordered by the contents of another field in the task register other than the next and previous fields associated with the task register. An advantage of the present invention is that the queue system can be customized without requiring alteration to the hardware in the system. Another advantage of the invention is that tasks can be transferred quickly from queue to queue without exposing task data to transfer errors. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with respect to the particular embodiments thereof and reference will be made to the drawings, in which: FIGURE 1 is a high level drawing showing the processing system embodying the queue system of the invention; FIGURE 2 is a representation of a queue system configuration employing four queues; FIGURES 3A through 3L are diagrams illustrating the movement of tasks between the queues represented in Figure 2 in accordance with the queue system. FIGURE 4 is a flow chart of routine A for removing a task register from a queue. FIGURE 5 is a flow chart of routine B for inserting a task register into a queue in an ordered sequence using the example of ordering by task register address. FIGURE 6 is a flow chart of routine C for inserting a task register into a queue such that the task register will be in the last position of that queue. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figure 1, the queue system is embodied within a processing system comprised in part by processor 10, read only memory ROM 11 and random access memory RAM 12. Processor 10 communicates with ROM 11 via lines 13 and with RAM 12 via line 14. This general configuration of a processor, read only memory and random access memory, is widely used throughout the industry. The processing system is generally incorporated within a larger computing system and is dedicated to handling specific types of functions within the overall system. For instance, such processing systems are included within disk drive file control units, I/O channel control units, as well as within the main processing unit itself. The processor is running under the control of a system program which was written to enable the processor to perform its designed functions. The queue system of this invention is controlled by processor 10 and uses RAM 12 for the actual formation of the pseudo queues. RAM 12 is structured to contain a plurality of storage addresses where each address includes a number of bits or bytes of data. The queue system requires that addresses within the random access memory be dedicated to the queue system for the formation of the pseudo queues within the RAM. Each of the addresses is considered to be a task register or a header register. Each header and task register includes at least two fields, a previous field and a next field. The previous field of a register stores the address of the preceding register in the queue and the next field stores the address of the following register in the queue. Each queue is comprised of at least a header register. When a queue has no task registers associated with the queue, the header register for that queue will have the header registers own address stored in the previous and next field of the header register for the queue. Therefore the previous and next fields have pointers pointing to the location of the header register for the queue. Each task register is assigned to a queue at all times. In the queue system one queue is designated as the empty queue whose function it is to contain the task registers that are presently not assigned to a task that is to be operated upon by the operating system. The queue system may have many different configurations and can be tailored to the needs of the designer. Figure 2 is a configuration consisting of four queues, 20, 21, 22 and 23, within the queue system for the purpose of explaining the preferred embodiment of the queue system. The configuration is comprised of queue D 23 which acts as the empty queue and which initially will contain all the task registers in the queue system. When processor 10 receives a task to be performed by using the queue system, the task is assigned to the task register having the lowest address in queue D 23. The queue is then removed from queue D 23 and inserted into queue A 20. While the task is in queue A 20 the system will perform various operations to determine what the task is and what resources and operations must be performed with regard to that task by the processing system. The processing system then makes a decision as to whether the task is to be processed in accordance with a first processing course associated with queue B 21 or a second processing course associated with queue C 22. The task register is then effectively moved by removing the task register from queue A 20 and inserting the task register in either queue B 21 or queue C 22. When the task is completed the task register is removed from queue B 21 or queue C 22 and inserted into queue D 23. The system has the further option that if the task need not be processed by the processing course associated with queue B 21 or queue C 22, the task register associated with the then completed task is removed from queue A 20 and inserted into queue D 23. Referenced copending patent application "System for Allocating Tasks Between Two Actuators Servicing the Same Magnetic Disk Drive in a Single Disk Drive", describes a dual actuator system servicing a single magnetic disk media. The queue system of this invention is employed within the microprocessor and RAM unit referred to therein. In Appendix A of this application and the cross-referenced application queue A 20 is the command queue, queue B 21 is the one channel queue where a task for retrieving or storing data onto the magnetic media will employ only one of the two actuators, queue C 22 is a two channel queue which uses both actuators in the performance of a command from the system with regard to the single magnetic media and, finally, queue D 23 is the empty queue. The routines for inserted and removing a task into queue B 21, the one channel queue, is set forth in detail in the cross-referenced copending application and will not be repeated herein. For simplicity in describing the queue system of this invention queue B 21 will be designated as a queue which is address ordered. It should be understood that the queue system of the invention is not limited to the configuration shown in Figure 2 and the designer of the queue system, in accordance with this invention, can have the queue system comprised of as many queues as the system designer wishes, where each of those queues can be ordered in accordance with the criteria set forth and controlled by the designer. Further, the addresses of the memory registers within the random access memory may be a single block of dedicated addresses or a plurality of blocks of dedicated addresses or addresses that are not consecutive. Again, which addresses and the distribution of those addresses within the random access memory is designer choice and the location of the addresses used in the memory is not critical to the queue system architecture. In review, for simplicity in describing the invention, the task register in queues A 20, B 21 and D 23 are address ordered within the queue and the task registers in queue C 23 are ordered in the sequence of insertion into the queue. If the tasks in queue C 23 are serviced by using the task register address stored in the next field of the header register for queue C 23, then queue C 23 effectively becomes a first in first out (FIFO) queue. If the tasks in queue C 23 are serviced by using the task register address stored in the previous field of the header register for queue C 23, then queue C 23 effectively becomes a last in first out (LIFO) queue. It can readily be seen that the character of the queue is determined by the system designer as to how he orders the queues within the queue system and how he removes tasks from the queue. Once again the classification of each of the queues into a type of queue is not critical within the system except that one queue must be dedicated as an empty queue to ensure that all task registers associated and used in the queue system are always placed within one of the queues of the queue system. Referring to Figure 4, routine A is a procedure for removing a task register from any queue within the queue system. During a move operation for moving a task register from one queue to another queue, the move operation first executes routine A, the removal of the task register, hereinafter referred to as the current register, from the queue. To perform this removal operation routine A performs the following sequence of steps. Step 1 makes the address stored in the next field of the previous register, whose address is stored in the previous field of the current register, equal to the address stored in the next field of the current register. Step 2 makes the address stored in the previous field of the next register, whose address is stored in the next field of the current register, equal to the address stored in the previous field of the current register. In this manner the linkage between the task registers in the queue has been reestablished after the removal of the current register from the queue. It should be noted that no action at this time is taken with regard to the next field and previous field of the current register being removed as this will be addressed during the insertion routine of the removed current register into another queue. Referring to Figure 5, routine B is a process for the insertion of a removed current register into a queue in an ordered sequence using the example where the task registers are ordered in ascending order of the addresses of the task registers in the queue. This would be the routine followed when a removed current register is inserted into queues A, B or D of the configuration as heretofore described with regard to Figure 2. In this operation it is required that the current register be inserted in the queue between the register having the next lowest address and the register having the next highest address than the address of the current register to be inserted in the queue. Attention must be paid to the circumstance that the header register may be one of the registers whose previous or next field will be changed by this procedure. Routine B performs this operation by executing the following sequence of steps. Step 1 selects the header register of the desired queue into which the current register is to be inserted. Step 2 determines if the address stored in the next field of the selected register, which in the first instance will be the header register, is equal to the address of the header register. If the address stored in the next field of the selected register is the address of the header register, the routine will branch to step 5. If the address stored in the next field of the selected register is not equal to the address of the header register, step 3 is performed which tests if the address of the current register is greater than the address stored in the next field of the selected register. If this inquiry is negative, the routine branches to step 5. If the inquiry of step 3 is affirmative, step 4 is performed to make the selected register the register whose address is stored in the next field of the presently selected register and will return to step 2. The loop of step 2, step 3 and step 4 will be repeated until the loop is exited either from step 2 or step 3. When the routine exits from either step 2 or step 3, step 5 is processed. Step 5 makes the address stored in the next field of the removed current register to be equal to the address stored in the next field of the selected register. Step 6 then makes the address stored in the previous field of the removed current register equal to the address of the selected register. Step 7 then makes the address stored in the previous field of the register whose address is stored in the next field of the selected register equal to the address of the removed current register. Finally, step 8 makes the address stored in the next field of the selected register equal to the address of the removed current register. It should be noted that steps 5, 6, 7 and 8 may be interchanged except that step 8 must always follow the completions of presently step 5 and step 7. At the completion of step 8 of routine B, the removed current register will have been inserted in the queue and all task registers within the queue will be order in ascending address order of the task registers in the queue. While Routine B has been described for the ordering of the task register in ascending task register address order, the ordering may be done by using data in an additional field in each header and task register in the queue system. When an additional field is used to determine the sequence of the task registers in the queue, Routine B would be modified in steps 1, 2 , 3 and 4 to determine the appropriate selected register in accordance with the data stored in that additional field being used for that purpose. Once the selected register has been determined then the current task register to be inserted is inserted by step 5, 6, 7 and 8 of Routine B. Referring to Figure 6, routine C is a procedure for the insertion of the removed current register into a queue where the removed current register will be inserted as the last task register in the queue. Effectively, the task registers are ordered within the queue in the sequence in which the task registers were inserted into the queue. Routine C performs this operation by executing the following sequence of steps. Step 1 selects the header register of the desired queue. In the queue configuration of Figure 2, routine C would be performed whenever a removed current register is to be inserted into queue C 23. Step 2 then makes the address stored in the next field of the removed current register equal to the address of the header register. This will ensure that the removed current register will be inserted in the queue as the last register in the queue. Step 3 then makes the address stored in the previous field of the removed current register equal to the address stored in the previous field of the header register. Step 4 then makes the address stored in the next field of the register whose address is indicated in the previous field of the header register equal to the address of the removed current register. Finally, step 5 makes the address stored in the previous field of the header register equal to the address of the removed current register. The registers in the queue are linked in a forward loop by the next fields in the registers and in a backward loop by the previous fields in the register. The use of the next field and previous field within each of the registers within each of the queues allows the system to proceed up and down a queue in an orderly fashion. The system may also access any register within the queue regardless of its position within the queue, according to the address of the register being sorted by the system. Again this allows maximum flexibility to the system designer who is designing the queue system to meet the needs of the system designer. If so desired, routines A, B and C may be permanently stored within the ROM 11 to be accessed by processor 10 whenever a move operation between queues is indicated by the operating system. The operation of the queue system will be discussed with regard to the examples shown in Figures 3A through 3L. The figures each show four header registers having addresses A, B, C and D respectively. Address A is the address of the header register for queue A 20, address B is the address of the header register for queue B 21, address C is the address of the header register for queue C 22, and address D is the address of the header register for queue D 23. Nine task registers are shown having addresses from 1 through 9. Again there is no significance to the addresses selected for use in these examples and the addresses may be selected for either the header registers or the task registers in accordance with the criteria specified and used by the system designer. Each of the header registers and task registers have a previous field PF and a next field NF associated with it. Once again the previous field PF will have the address of the previous register within the queue and the next field NF will have the address of the next register within the queue. With regard to the task registers two other columns are supplied, the column labeled TN is used to identify the task that is assigned to a task register and column labeled Q is used to indicate which of the queues a task register is presently assigned. Figure 3 shows the relationship of the task registers and header registers when all of the task registers are assigned to queue D 23. As can be seen, the header registers for queues A, B and C in addresses A, B and C have each of the address of their own associated header register stored in the previous fields and next fields of their associated register. When the previous field and next field both contain the address of the header register, that queue is empty. Therefore queues A, B and C are empty at this time and all registers are in the queue D 23. The next field of header register for queue D 23 contains the address of the first task register in the queue at address l and the previous field of the header register for queue D 23 contains the address of the last task register in the queue at address 9. Hereinafter the task register will be identified by the address of the task register, for example task register l is the task register located at address 1 in the RAM 13. In task register 1 the previous field contains address D, the address of the header register, and the next field contains address 2, the address of the following task register in queue D 23. In task register 9, the previous field contains address 8, the address of the preceding task register in the queue, and the next field contains address D, the address of the header register. By observation, task registers 2, 3, 4, 5, 6, 7 and 8 each have their previous field containing the address of the preceding task register in the queue and their next field containing the address of the following task register in the queue. The header register for queue D 23 and task registers 1 through 9 are therefore interlinked to form queue D 23. Assume that the operating system upon receiving a task will store that task in the task register whose address is stored in the next field of empty queue and then will move that register from queue D 23 to queue A 20. Assume that the operating system receives task Al for processing. To perform the above described operation, the operating system would first store task Al in task register 1 and then would execute routine A to remove task register 1 from queue D 23. Task register 1 will be the current register referred to in routine A and B. Routine B would next be executed to insert task register 1 into queue A 20 by sequentially executing steps 1, 2, 5, 6, 7 and 8. The results of the procedure are shown in Figure 3B where task register l, containing task Al, is in queue A 20 and all other task registers remained in queue D 23. It should be noted that the next field in queue D 23 now points to task register 2 rather than to task register 1. Referring to Figure 3C, assume that the system next receives task A2 which will now be stored in task register 2 in queue D 23 which will then be moved to queue A 20. After task A2 has been loaded into task register 2, task register 2 will be removed from queue D by routine A. Routine B will next insert register 2 into queue A 20 by executing steps 1, 2, 3, 4, 2, 5, 6, 7 and 8. The results of the procedure are shown in Figure 3C. Referring to Figure 3D, assume the system next receives task A3 which is stored in register 3 in queue D 23 and then register 3 is moved from queue D 23 to queue A 20. Routine A will be executed to remove register 3 from queue D 23. Then routine B will insert register 3 within queue A 20 by sequentially executing steps 1, 2, 3, 4, 2, 3, 4, 2, 5, 6, 7 and 8. The results of the procedure are shown in Figure 3D. In summary, at this time queue A 20 consists of header register A and task registers 1, 2 and 3, queue B 21 consists of header register B, queue C 22 consists of header register C, and queue D 23 consists of header register D and task registers 4, 5, 6, 7, 8 and 9. Referring to Figure 3E, assume that the system next determines that task Al should be moved from queue A 20 to queue B 21 for further processing. Since task Al is stored in task register 1, routine A is executed to remove task register 1 from queue A 20. Routine B is then executed to insert task register 1 into queue B 21 by executing sequentially steps 1, 2, 5, 6, 7 and 8. Referring to Figure 3F, assume the operating system next receives task A4 which is stored in task register 4 in queue D 23 which is then inserted into queue A 20. Routine A is executed to remove task register 4 from queue D 23. Routine B is executed to insert task register 4 into queue A 20 by executing sequentially steps 1, 2, 3, 4, 2, 3, 4, 2, 5, 6, 7 and 8. The results of this procedure are shown in Figure 3F. In summary, queue A 20 now contains header register A and task registers 2, 3 and 4, queue B 21 contains header register B and task register 1, queue C 22 contains header register C and queue D 23 consists of header register D and task registers 5, 6, 7, 8 and 9. Referring to Figure 3G, assume next that the operating system determines that task A3 should be moved from queue A 20 to queue C 22. Since task A3 is stored in task register 3, routine A will be executed to remove task register 3 from queue A 20. Routine C will then be executed to insert task register 3 into queue C 22 by sequentially executing steps 1, 2, 3, 4 and 5. The results of this procedure are shown in Figure 3G. Referring to Figure 3H, next assume that tasks A5, A6 and A7 are received in that order by the system to be processed by the system. These tasks will be inserted in task registers 5, 6 and 7. Task registers 5, 6 and 7 will then be moved from queue D 23 to queue A 20. Each of these operations will include the operation of executing routine A and then routine B for each of these tasks. The results of these procedures are shown in Figure 3H. In summary, at this time queue A 20 consists of header register A and task registers 2, 4, 5, 6 and 7, queue B 21 consists of header register B and task register 1, queue C 22 consists of header register C and task register 3, and queue D 23 consists of header register D and task registers 8 and 9. Referring to Figure 31, assume that the operating system determines that task A5 should be moved from queue A 20 to queue C 22. Since task A5 is in task register 5, routine A will be executed to remove task register 5 from queue A 20. Routine C will then be executed to insert task register 5 into queue C 22 by sequentially executing steps 1, 2, 3, 4 and 5. The results of this operation are shown in Figure 31. Referring to Figure 3J, next assume that the operating system determines that task A2 should be moved from queue A 20 to queue C 22 for processing. Since task A2 is located in task register 2, routine A is executed to remove task register 2 from queue A 20. Routine C is then executed to insert task register 5 into queue C 22 by sequentially executing steps 1, 2, 3, 4 and 5. The results of this procedure are shown in Figure 3J. In review, at this time queue A 20 consists of header register A and task registers 4, 6 and 7, queue B 21 consists of header register B and task register 1, queue C 22 consists of header register C and task registers 3, 5 and 2, and queue D 23 consists of header register D and task registers 8 and 9. Referring to Figure 3K, the system next having determined that task Al has been completed will return task register Al, storing task Al, from queue A 20 to queue D 23. Routine A will be executed to remove task register 1 from queue A 20. Routine B will then be executed to insert task register into queue D 23 by sequentially executing steps 1, 2, 3, 5, 6, 7 and 8. The results of this procedure are shown in Figure 3K. Referring to Figure 3L, assume that the operating system task 8 which is stored in task register 1 in queue D 23 which is then inserted into queue A 20. After task A8 is stored in task register 1, routine A is then executed to remove task register 1 from queue D 23. Routine B is then executed to insert task register 1 into queue A 20 by sequentially executing steps 1, 2, 3, 5, 6, 7 and 8. The results of this procedure are shown in Figure 3L. In summary, at this time queue A 20 contains header register A and task A8, A4, A6, A7 stored in task registers 1, 4, 6 and 7, respectively, queue B 21 consists of header register B, queue C 22 contains header register C and task A3, A5 and A2 stored in task registers 3, 5 and 2, respectively and queue D 23 consists of header register D and task registers 8 and 9. The foregoing discussion has exemplified the operation of the queue system and how the queue system can be customized by the designer to meet the designer's needs. While the queue system has been described as using memory locations within a random access memory, it should be understood that dedicated hardware registers could be used instead of the random access memory. It can readily be appreciated that the movement of the tasks between queues only necessitated the modifications of the previous and next fields of the registers being affected by the removal and insertion of a task register into a queue. At no time is it necessary to move the actual data associated with the task stored within the task register when the task register containing the task was effectively moved between queues. In the foregoing manner the queue system has allocated registers to form pseudo queues where each pseudo queue is comprised of a header register and one or more of the task registers and where each task register is always assigned to a queue in the queue system. The resulting queue system is one that is readily available to be customized by the designer and easy alteration and modification as the system requirements are changed. The routine set forth in Figures 4, 5 and 6 are implemented in microcode using known digital software implementation and were assembled using Motorolla 68C11 Assembler, Series 5.0. The microprograms are detailed in Appendix A and carry out the function of the routines of the flow charts as shown in Figures 4, 5 ( not by task register ordering but by additional field ordering) and 6. It should be understood that the method can be embodied in other microprograms using other programmable languages or can be stored in the read only memory within a computer system. The functions of processor 10 can be implemented by a hardware state machine dedicated to perform the functions necessary to carry out the routines described herein. While the invention has been particularly shown and described with reference to the preferred embodiments therefore, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention. Given the above disclosure of general concepts and specific embodiments, the scope of the protection sought is defined by the following claims. APPENDIX A Conner Peripherals, Inc. 1992 AUTHOR: Steve Cornaby DATE: 8 Aug 1990 HISTORY: AA9A QTOEMPTY: AA9A OF SEI ;Don't allow interrupts while we ; are a justmg pointers Irom current queue point X to previous entry get next of removed queue store in next of previous entry point X to next entry get previous of removed queue store in previous of next entry insert new C E into empty queue ; Get queue header ; point to last CQE in queue ; point next pointer to new CQE point prev pointer of new CQE to last entry Get queue header point previous to new CQE point next of new CQE to header ; Interrupts OKAY now ;Reιurn to post status and sense AAC1 QT02CHAN. AAC1 OF SEI ;Don't allow interrupts while we ; are adjustmg pointers ; remove this CQE from current queue SUBSTITUTE SHEET (RULE 26| point X to previous entry get next of removed queue store in next of previous entry point X to next entry get previous of removed queue store in previous ol next entry ; Get queue header point to last CQE in queue point next pointer to new CQE point prev pointer of new CQE to last entry Get queue header point previous to new CQE point next of new CQE to header ; Interrupts OKAY now ; eturn to post status and sense NAME QTOSTAT PURPOSE: Move the CQE (Command Queue Entry) to the status queue THEORY: Y points to the CQE to be moved. Since it is possible for the host to be connected to ine process to give status, QTOSTAT checks lor this condition and places the queue at the head if the host is alrea.y connected EXIT NONE AUTHOR: Steve Cornaby DATE: 8 Aug 1990 HISTORY QTOSTAT .Don't allow interrupts while we ; ■ "-"TEST"*** ; are adjust mg pointers rent queue point X io previ ous ent ry get next of removed queue store in next of previous entry point X to next ent get previous of removed queue store in previous of next entry Get queue header .See if we are currently connect eo request at head, if not. at tai l point to last CQE in queue QTOS05 point next pointer to new CQE point prev pointer of new CQE to last entry ;Get queue headei ; point previous to new CQE point next of new CQE to header SUBSTITUTE SHEET (RULE 26} AB15 15 08 20 BCLR H_PORTD,20h ; ««««» TEST"** * AB18 0E CLI ; Interrupts OKAY now AB19 39 RTS .Return to post status and sense NAME: QTOCNTH PURPOSE. Point to the CQE with a the continue queue entry at head THEORY: Y points to the CQE to be pointed to by the continue queue AccD points on entry to the continue address EXIT NONE AUTHOR Steve Cornaby DATE: 16 Aug 1990 HISTORY ;McLe sure no interrupts occur ; wr.ile CNTH or CNTT is being updated ;Stcre off continue a.-ress ; See if we jre currently connected request .: head, if not, a; tai l Get queue jointed to .y queue head point to last CCi in queue Adjust heao to point ;o new entry pcint to CQE that needs to continue Interrupts are OKay r.ow .Get queue pointed to :y queue tail paint to CQE that reeds to continue point to next CQE in queue ,Aθ'ust tail to point :o next jnused = ' " fy Irr.errupts .re Or*.ay * ow NAME QT01CHAN PURPOSE Move the CQE (Command Queue Entry) tc the lch -.nel queue II the command is directed, check if the chanr, THEORY Y points to the CQE to be moved 0 contains execution address when execution continues EXI T NONE AUTHOR Steve Cornaby DATE 8 Aug 1990 HISTORY QT01CHAN SEI ; Don't allow interrupts while we , are adjusting pointers STD <S EXCTADD, Y .Store continuing execution address ; remove this CQE from current queue LDX <S_PRV, Y .point X to previous entry LDD <S_NXT Y , get next of removed queue STD <S_NXT,X , store in next of previous entry , point X to next entry get previous of removed queue store in previous of next entry . insert new CQE into 1 channel queue LOX -V_1CKAN ; Get queue header LDX <S PRV.X , point to last CQE in queue STY <S~NXT,X , point next pointer to new CQE STX <S PRV, Y , point prev pointer of new CQE to last entr> LDX #V 1CKAN , Get queue header STY <S~PRV X , point previous to new CQE STX <S NXT, Y point next of new CQE to header CLI , Interrupts OKAY now RTS .Return to post status and sense NAME QT010RD PURPOSE Move the CQE (Command Queue Entry) to the Ichannel queue and order 11 THEORY Y points to the CQE to be moved D contains execution address when execution continues The Ichannel queue is traversed and the destination address compared against that of the new command When traversal is complete, X will be pointing to the CQE before which the current CQE is to be placed EXIT AUTHOR Steve Cornaby DATE 8 Aug 1990 HISTORY AB67 QT010RD AB67 OF SEI Don t allow interrupts while we are adjust mg pointers ," Set up continue address AB68 18 ED 09 STD <S EXCTADD, Y Store continuing execution address ; -* Remove this CQE from current queue point X to previous ent ry get next of r moved queue store in next ol previous entry point λ to next entry get previous ol removed queue store in previous of next entry AB7B OE C I , Al I ow inter rupt s now Check to see if lcban queue empty ; Get Ichannel queue pointer .Point to first entry , end if queue empty ;Branch if not empty , Set non-sequent la I flag BRA ORD100 ABSA 0RD05. ;" Command with which we are comparing may be directed II so, it doesn't count for the compare Continue with the next CQE AB8A IE OB 40 5F BRSET <S QSTAT.X, SB DRCTD, ORD50 .Branch if directed command AB8E AB8E 0RD10 ," Command not directed ;" Compare destination cylinder of new CQE against destination cylinder of Ichan CQE Branch to insert if new less than Ichan LDD <S_DCYL, X Get destination of Ichan CQE CPD <S DCYL Y subtract destination cylinder new CQE BLS 0RD1S branch if NEW command fits before or is on same cylinder as ICHAN command LDAA #01 Set non-sequential command BRA ORD100 , " New command is greater than Ichan CQE command Check to see if it Ichannel co manc is linked to the next command 0RD15. BRCLR <S CSTAT.X, SB CLNKED, ORD20 .Brancn if command not linked LDX <S~NXT X ~ , Get neit command to check it out CPX #V_1CHAN ; Check if at end BNE 0RD1S . branch if not LDAA .01 ,AccA '= 0 means non-sequential BRA ORDIO: Insert at end i I we are ABAE ORD20 Check if command can be coalesced First priority is to check if it is the same type ol ccnmand .Get op code check if matches candiαate CQE r ' ' -- • :; code: Command not linked Check ιl it is sequential to old command .Get 1st LBA past old command , compere against first LBA of new command , Branch i I not sequent i a I , High Oyte I < I ; Branch if not sequential Command was sequential Check il command is still active If so, link it to the following command ABBD OF SEI ;Dιsable interrupts until Ichan ; queue is updated ABBE 86 01 LDAA #01 ; Use AccA as a 1 lag SUBSTITUTE SHEET (RULE 2® LDAB <S_DSKSTAT, X .Get disk status BNE ORD35 , Not executing if status already posted BSET <S_CSTAT X S8 CLNKED Set I inked bit in old CQE BSE T <S CS1 AT Y SB BLNKE D and backward linked bit in new CQE , ** Check to see if command we are linking to is currently active BRCLR <S_CSTAT, X, SB_CDATIN, ORD35 , Not executing if data not in buffer BRSET <S QSTAT, X, SB_BCHAN, 0RD30 .Branch if executing on channel , " Setup linked CQE with same attributes as currently executing CQE , Set attributes for channel A BCLR <S QSTAT, Y, SB BCHAN , Not B channel LDD #0 , Get channe I A off et STD <S_CHAN0FF,Y , store in CQE channel offset BRA OR035 cont mue ORD30 .Set attributes for channel B BSET <S QSTAT, Y. SB_BCHAN Not β channel LDD -0020h , Get channel B offset STD <S CHANOFF, Y , store in CQE channel offset ORD35 LDX <S NXT.X Point to following CQE so new CQE , will be insert ed after old CQE BRA ORD100 Branch to insert CQE , •• new CQE is greater than or equal to Ichan CQE Move to the next Ichan CQE and try again ORD50 .Point to next ent ry , insert before end ol Ichan queue ORD10 , if pointing to last entry else branch for another compare ABF 4 OR0100 Insert new CQE before Ichannel CQE destination insert new CQE into 1 channel queue ABF4 3C PSHX Preserve CQE before which we will insert new CQE LDX <S_PRV X point to last CQE in queue STY <S_NXT,X point next pointer to new CQE STX <S PRV. Y point prev pointer of new CQE to last entry PULX .Point at CQE STY <S_PRV X po int previous t o new CQE STX <S NXT Y point next ol new CQE to header CLI Al I ow i nt er rupt s TSTA Set zero I lag RTS Return to post status and sense NAME CCHAN PURPOSE Check if there are more entries in the channel queue Since channel commands can be directed check the status byte to see which channel we are currently servicing and check for other directed commands to that channel If there are no directed commands for the channel, select the first CQE in the Ichannel queue and place it in the appropriate channel header Then clear the executing bit such that the kernal will start the new process THEORY Y points to the currently executing CQE The Ichannel queue is checked to see if it is empty If it is empty then the address field of the currently executing channel Is set to zero If the Ichannel queue is not empty, but there are no CQEs directed to the currently executing CQE, and no non-directed CQEs the address field of the currently executing channel is again set to zero The routine will search all Ichannel entries for directed commands, which are executed first This occurs because directed commands can be steps in the error recovery sequence, and the command may be partially complete In addition, read and write buffer commands are directed commands This routine is also the location of more complex algoor i thims lor CQE selection Since they are as yet undefined, the routine simply selects the first entry ••"•KOTE<—" This routine can be called only after the current operation has been removed from the Ichannel queue by calling QTOSTAT, etc EXIT NONE AUTHOR Steve Cornaby DATE 8 Sep 1990 HISTORY AC07 CCHAN " Since we mil be looking for directed commands the routine splits to a checker for chanA and chanB [01] if TWOACT AC07 18 IE OB 80 33 BRSET <S QSTAT, Y SB BCHAN CCH19 .Branch if channel B is ending [00] endi f ACOC CD EE 02 LDX <S NXT Y Point to CQE after current CQE ACOF 20 02 BRA CCH02 AC11 CCHOO , *- ChanA is ending Get next CQE, (if any) LDX <S_NXT X Point to next CQE CCH02 DO CPX IV lCi-AN make sure it isn t he.der BNE CCH05 branch to end if it i sn t , ** We are pointing to header We must skip the header and point to ine next CQE We are done when we are pointing to the CQE currently pointed to by ACHAN LDX < ~J>r X Ski header l it pc i i cς CCH05 BSET H_POPTD lOh • - •• -TEST---' CPX V AChA*. check if we are done BNE CCH10 Branch if we are not LDX .OOOCr, There are no other command, pending BRA CCH18 so clear channel and end CCH10 , ** We are pointing to next valid CQE , ** Make sure it is not already being executed on a channel BRSET <S_QSTAT.X SB_CHANLNK, CCHOO . branch if already linked BRSET <S_CSTAT, X, SB_BLNKED. CCHOO , or if backward coalesced BRCLR <S_QSTAT,X SB DSCTD,CCH15 .Branch if not a directed coirmand BRSET <S QSTAT, X, SB~DIRB, CCHOO .Branch if directed to other channel ; ** Command " directed to this channel Point to it and end AC3 CCH15 We are finishing an operation on B channel Point to CQE immediately after current CQE <S NXT, Y , Point to next CQE CCH22 ChanA is ending Get next CQE, (if any) <S NXT.X .Point to next CQE #V ICHAN make sure it isn't header CCH25 branch to end if it isn't ; ** We are pointing to header We must skip the header and point to the next CQE We are done when we are pointing ; to the CQE currently pointed to by ECHAN AC4B EE 02 .Skip header and point to next CQE AC4D CCH25 AC4D BC 11 63 , check if we are done AC50 26 05 , Branch if we are not AC52 CE 00 00 There are no other commands pending AC55 20 13 so clear channel and end AC57 CCH30 , ** We are pointing to next valid CQE ; ** Make sure it is not already being eiecuted on a channel AC57 IE OB 02 E9 BRSET <S QSTAT, X, SB_CHANLNK. CCH20 . .ranch if already linked AC5B IE OC 02 E5 BRSET <S CSTAT.X. SB_BLNKED CCH20 , or if backward coalesced ACSF IF OB 40 04 BRCLR <S_QSTAT,X, SB_DRCTD, CCH35 .Branch if not a directed command AC63 IF OB 20 DD BRCLR <S_QSTAT. X. B OIRB. CCH20 .Branch if directed to other channel , ** Command directed to this channel Point to it and end AC67 CCH35 AC67 IC OB 82 BSET <S_QSTAT.X, SB_BCHA<TSB_CHANLNK Set channel and channel linked bits AC6A CCH38 AC6A FF 11 63 STX V BCHAN .Update BCriAN AC6D CCH100 AC60 OF SEI Turn afl interrupts until done ** Clear out all entries from CNT quet. thai malch the CQE just t. _— i et t: AccY oints to C E we are just (misiing .See »r,at head is pointing al . Initialize AccO to zero Point back or,_ entry on initialization Look at val 10 entry , checi if at tail br.nch to end it checked all entries , Check if CQE matches that |ust written branch i f no match Load with zeroes if matches to invalidate Loop to look again , Al low interrupts again SUBSTITUTE SHEET (RULE 26 AC87 39 RTS and r e t u r n NAME: SCHAN PURPOSE: A non-directed command has just been placed in the Ichannel queue. The current status of the channels is unknown. Scan the channels to see if they are currently busy. If either is not busy, copy the CQE pointer into the channel command register. The kernal will detect an un-started command and start the channel command THEORY: Y points to the CQE just moved to the Ichannel queue. Channel A is checked to see if it is empty. The channel pointer will be zero if it is empty. If it is not empty. Channel B is checked If eitαer channel is empty, the contents of Y will be written to it. The channel in process is 0 as it is a new command. The kernal samples for a channel pointer != 0 and a Channel in process = 0 to know if it should begin a new command. EXIT: NONE AUTHOR: Steve Cornaby DATE: 11 Sep 1990 HISTORY: AC88 SCHAN AC88 SEI ; No interrupts while we mess with queue . i f TWOACT ACS9 LDX V ACHAN Chirk i f channel A free AC8C BNE SC05 branch if not ACSE STY V ACHAN Channel :s free, tell kernal to start ACS2 BSET <5 QSTAT,Y,SB_CHANLNK CC: is row linked to a Channel AC96 BRA SCEND .ranch to continue AC98 SCO5 AC98 LDX V BCHAN Ch:.k if channel A free AC9B BNE SCEND , branch i f not AC9D STY V BCHAN Ch.nnel .s free, tell kernal to start ACA1 BSET <5_QSTAT, Y,SB_CHANLNK , CC.: is r.ow linked to a Channel else LDX V ACHAN Chi.k i f channel A free BNE SCEND b'anch if not STY V ACHAN Cr.cnnel <s free, tell kernal to start BSET <_ QSTAT, Y, SB CHANLNK CC: is r.ow linked to a Channel ACA5 OE CLI lr,-.jrrup:s are okay now ACA6 39 RTS NAME: FREEZQ PURPOSE: An error condition occurred r_π the process. Freeze the Q so that no further operation: will occur on the channel until the host has a chance * .o do z command. Normally, the command would be a request ssnse command, but if the host instead chooses to do another command, Queue processing will proceed normal ly. THEORY: Y points to the currently executing CQE. The routine will place the Queue in the state that it would normally be If the queue were waiting for a command It requires a call to SCHAN to re-activate the channel. Such a call occurs on any command, including request sense. Thus, the channel is reactivated at the conclusion of the fol lowing command. EXIT: NONE AUTHOR: Steve Cornaby DATE: 28 Dec 1990 HISTORY: FREE2Q: SEI ;Turn off interrupts until done LDD #0 ; Initialize AccD with zeros BCLR <S_QSTAT.Y,SB_CHA IP ;No longer executing on this channel BRSET <S_QSTAT,Y, SB_BCHAN, FRZ10 ;Branch if channel B is ending STO V ACHAN ; ut A channel to sleep BRA FRZ20 ; and end FR210: STO V SCHAN ; Put B channel to sleep ; and end FRZ20: CL! ;Al low interrupts again RTS and return Eι\D INCLUDE S5DEFECT.ASM ; Rd defect list / reassign / format STTL S5DEFECT.ASM - Defect handling/reassign/format unit PAGE

Claims: CLAIMS What is claimed is: 1. A queue system comprising: a plurality of queues where said queues are comprised from: a plurality of header registers, each said header register being uniquely associated with one of said queues, each said header register having a unique address and contains a previous field and a next field; a plurality of task registers, each said task register having a unique address and contains a previous field and a next field; where each said previous field and said next field stores a header register address or a task register address; and control means for dynamically assigning said task registers to said queues by controlling the addresses stored in said previous field and next field in each of said header registers and task registers such that each of said task registers is always to one of said queues thereby effectively moving said task registers between queues without physically moving said task registers. 2. The queue system of Claim 1 wherein said next field and said previous field of said header register for a said queue will store the address of said header register for said queue when no said task registers are assigned to said queue by said control means. 3. The queue system of Claim 1 wherein said previous field of a said task register stores the address of the register immediately preceding said task register in said queue containing said task register and said next field of said task register contains the address of the register immediately following said task register in said queue containing said task register. 4. The queue system of Claim 3 wherein the sequence of addresses stored in the next field of the registers in each said queue forms a continuous loop in the direction from header register to last task register in the queue and the sequence of address stored in the previous field of the registers in said queue forms a continuous loop in the direction from the last task register to the header register in the queue. 5. The queue system of Claim 1 wherein said control means further comprises: a deletion means for removing a task register from a queue; and an insertion means for inserting a task register into a queue. 6. The queue system of Claim 5 wherein said insertion means includes a first means for inserting said task register in said queue as the last task register in said queue. 7. The queue system of Claim 5 wherein said insertion means includes a second means for inserting said task register in said queue as a function of the address of said task register being inserted into said queue. 8. The queue system of Claim 1 wherein one of said queues in said queue system is an empty queue and contains those task registers which are not placed in another queue within said queue system thereby insuring that, at all times, each task register will be placed in a queue in said queue system. 9. The queue system of Claim 1 wherein said control means effectively moves a task register between a first queue and a second queue within said queue system by first actuating said deletion means to remove said task register from said first queue and then actuating said first or second means of said insertion means for inserting said removed task register into said second queue.

Inventors: CORNABY STEPHEN R, CORNABY, STEPHEN, R.
Applicants: CONNER PERIPHERALS INC, CONNER PERIPHERALS, INC.
Application year: 1994
Main classification: G06F9
IPC codes: G06F5, G06F7, G06F9