Noise filter

Abstract: 1. A filter for filtering noise from a first signal on a SCSI bus as provided by an input buffer comprising: a schmitt trigger for receiving the first signal and providing a digital signal version of the first signal as a second signal; a first filter for filtering positive pulses having a pulse width less than 12 nanoseconds from the second signal and inverting the second signal to form a third signal; a second filter for filtering negative pulses having a pulse width less than 12 nanoseconds from the third signal and inverting the third signal to form a fourth signal; a third filter for filtering pulses having a pulse width less than 35 nanoseconds from the fourth signal and inverting the fourth signal to form a fifth signal; and an inverter for inverting the fifth signal to form a filter output.

Description: The present invention relates to a noise filter such as CMOS integrated circuitry for elimination or reduction of noise from signals received from a SCSI (Small Computer Systems Interface) Bus. More particularly, the present invention may relate to such noise reduction elimination circuitry for use on an input buffer of a SCSI bus controller integrated with other components onto a single integrated circuit chip. SCSI is a standard that allows users to easily add up to seven peripheral devices on a personal computer such as CD-ROM and high capacity disk drives. A SCSI adapter board in a personal computer provides a SCSI bus controller which provides digital address, data, and control signals to a SCSI bus on which peripheral devices reside. Fig. 1 illustrates the configuration of a SCSI bus with connecting devices. As shown, the SCSI bus 100 supports up to seven devices 101-107, with a potential one meter length of cable between the devices. Terminators 108 and 109 are provided at the ends of the SCSI bus cable. Device 1, labeled 101 is the host computer which includes an output buffer 120 and input buffer 130 connected to the SCSI bus line. The signal from the input buffer 130 is fed through a filter 140 to SCSI controller 150. Because of noise on SCSI bus signals, particularly switching noise and ground bounce created by output buffers such as 120, the input buffers can generate erroneous signals. Filters, such as filter 140 have, thus, been used between the input buffer and internal components of the device connected to the SCSI bus such as controller 150. Such a filter is disclosed in U.S. Patent No. 5,113,098 entitled "Glitch Remover Circuit For Transmission Links", to Sassan, incorporated herein by reference. More recent devices which operate on a SCSI bus can now generate significantly more noise. See, for example, U.S. Patent Application No. 08/186,050 entitled "Integrated SCSI and Ethernet Controller", by Chih-Siung Wu et al., filed January 24, 1994 (AMD961). By integrating a SCSI controller with an Ethernet Controller the transistor count of the device which connects to the SCSI bus increases from nearly 20,000 to over 100,000. By increasing the transistor count in this manner, particularly as integrated circuit processes move to a sub-micron levels, noise on the SCSI bus is increased to a level greater than current filtering can effectively eliminate. The larger devices on the SCSI bus introduce larger loading and generate additional ground bounce and current switching noise. Additional noise is also created by reflections of the noise created by the larger devices on the SCSI bus due to the long SCSI bus cable lengths. With such additional noise not eliminated by current filtering, input buffers receiving signals from the SCSI bus may once again generate erroneous signals. Circuitry which responds to such added switching, ground bounce, and reflection noise on a SCSI bus is therefore desired. Such circuitry is particularly desired to protect a SCSI controller logic against false input signal sensing without substantially complicating the SCSI controller design. The present invention provides a filter responsive to noise created from larger devices on a SCSI bus. The described embodiment filters out noise caused by ground bounce or current switching during the assertion of a signal, negation of a signal, or during transitions between the assertion and negation phase of a signal on the SCSI bus. The described embodiment also substantially eliminates reflection noise generated during the negation phase of SCSI bus signals. The present invention is a filter for filtering noise from a first signal on a SCSI bus as provided by an input buffer comprising: a schmitt trigger for receiving the first signal and providing a digital signal version of the first signal as a second signal; a first filter for filtering positive pulses having a pulse width less than 12 nanoseconds from the second signal and inverting the second signal to form a third signal; a second filter for filtering negative pulses having a pulse width less than 12 nanoseconds from the third signal and inverting the third signal to form a fourth signal; a third filter for filtering pulses having a pulse width less than 35 nanoseconds from the fourth signal and inverting the fourth signal to form a fifth signal; and an inverter for inverting the fifth signal to form a filter output. BRIEF DESCRIPTION OF THE DRAWINGS Further details of the present invention are explained with the help of the attached drawings in which: Fig. 1 illustrates the configuration of a SCSI bus with connecting devices; Fig. 2 shows a block diagram of the double filtering glitch eater in accordance with the present invention; Fig. 3A shows the input signal (IN) as received by the circuitry of Fig. 2 from an input buffer connected to a SCSI bus; Fig. 3B shows a signal obtained at point A in the circuitry of Fig. 2; Fig. 3C shows a signal obtained at point B in the circuitry of Fig. 2; Fig. 3D shows a signal obtained at point C in the circuitry of Fig. 2; Fig. 3E shows the output signal (OUT) of the circuitry of Fig. 2; Fig. 4 shows detailed circuitry for the Schmitt trigger of Fig. 2; Fig. 5 shows detailed circuitry for filter 1 and filter 2 of Fig. 2; and Fig. 6 shows detailed circuitry for filter 3 of Fig. 2. Fig. 2 shows a preferred embodiment of the present invention in the form of a block diagram of a double filtering glitch eater 200. The double filtering glitch eater includes four stages, the first stage being a Schmitt trigger 400, and the second through fourth stages being filters 500A, 500B and 600. Figs. 3A-3E show signals at particular points in the circuitry of Fig. 2. Fig. 3A shows the input signal (IN) as received by the circuitry of Fig. 2 from an input buffer connected to a SCSI bus. As shown, the signal IN includes noise, or oscillations on an assertion edge 302, on a negation edge 306, and in a portion of the signal 304 between the assertion and negation edge. Fig. 3B shows a signal obtained at point A at the output of Schmitt trigger 400. The Schmitt trigger 400 of the first stage, preferably has a transfer characteristic so that a signal received at the input IN of circuitry 200 shown by the curve in Fig. 3A is converted to a signal as shown in Fig. 3B. The Schmitt trigger transfer characteristic enables the Schmitt trigger to change to a HIGH state when a signal above a voltage level represented by VIH in Fig. 3A is received, and to change to a LOW state when a signal represented by VIL in Fig. 3A is received to create a signal as shown in Fig. 3B. As shown in Fig. 3B, ground bounce and switching noise without considering reflections are usually less than 10 nanoseconds and occurs on both the rising and falling edges of a signal pulse on the SCSI bus. All these noises, including noises 304 between 302 and 306 which have not been present in previous circuitry are eliminated by the first two filter circuits 500A and 500B in Fig. 2. Fig. 3C shows a signal obtained at point B at the output of filter 1, labeled 500A. As shown, filter 1 removes the noise signals of less than 12 nanosecond duration on the negation edge of the pulse and provides an inverted output signal at point B. Fig. 3D shows a signal obtained at point C at the output of filter 2, labeled 500B. As shown, filter 2 removes the noise signals of less than 12 nanosecond duration on the assertion edge of the pulse and provides an inverted output signal at point B. The noise eliminated by filter 2 is due to reflections on the long SCSI cable, hence causing the inversion of noise due to switching and ground bounce eliminated by filter 1. Fig. 3E shows the output signal (OUT) at the output of filter 3, labeled 600. Filter 3 eliminates conventional noise of less than a 35 nanosecond duration which is typically found on a SCSI bus. With noise on the order of 35 ns, significant reflections due to the lengths of the SCSI cables do not occur which require an additional filter to remove negative pulses. Note that with a 48 milliamp driver current called for by the SCSI bus specification, a delay of less than 5ns can be typically created by the pull down transistors of an output buffer of an active device. Pull up can be provided by the terminators on the SCSI bus as shown in Fig. 1, and the delay created by these devices is slower, typically on the order of 35 ns. Schmitt Trigger Fig. 4 shows detailed circuitry for the Schmitt trigger 400 of Fig. 2, along with a logic diagram 402 for the Schmitt trigger which includes a single inverter. The Schmitt trigger type buffer circuit 400 includes a plurality of N-channel transistors 412, 414, and 416, a plurality of P-channel transistors 422, 424, 426, an inverter gate 432 and output driver inverters 434 and 436. Also included in the circuitry of Fig. 2 are components utilized to prevent power flow from V CC to ground during power down. These components include a P-channel transistor 442, and an N-channel transistor 444 with gates driven by inverters 452 and 454. Note than in Figs. 4 as well as figures which follow, transistor sizes are indicated for the components shown. In the Schmitt trigger circuitry, the gates of transistors 412, 414, 422, and 424 are connected to the VIN input received from an input buffer as described with respect to Fig. 2. The common drains of transistors 414 and 424 are connected to the input of inverter gate 432. The output of inverter gate 432 is provided through the two driver inverters 434 and 436 as connected in series to provide the output VOUT of the Schmitt trigger. The transistor 422 series as a first load device with its drain connected to the source of transistor 424, and its source connected to a ground potential. Transistor 426 serving as a second load device has its drain connected to a supply potential V CC and its gate connected to the input of inverter 432. Transistor 414 has a source connected to the drain of transistor 412. The transistor 412, serving as a third load device has its source connected to the V CC supply through transistor 442. The transistor 416, serving as a fourth load device has its source connected to the input of inverter 432 and its drain connected to ground. When a signal having noise spikes is applied to the input terminal (IN) of the Schmitt trigger 400, the circuitry 400 will remove any noise spikes around the threshold point of its input on both the rising and falling edges of the input control signals. This is achieved by a hysteresis provided by transistors 422, 426, 412 and 416 as known to those skilled in the art. Consequently, the output voltage (VOUT) will appear as illustrated in Fig. 2B, with an input voltage (IN) applied as shown in Fig. 2A. For a sleep mode, a power down signal PWDWN is provided through the two inverters 452 and 454 to the gates of transistors 442 and 444. The source and drain of transistor 442 are coupled between the V DD power supply and the source of transistor 412 to prevent power from flowing from V DD when PWDWN is HIGH, indicating a sleep mode. The source and drain of transistor 442 are coupled from the input of inverter 442 to ground to allow a flow of power to ground when PWDWN is HIGH, indicating a sleep mode. Thus, the sleep mode circuitry of Schmitt trigger 400 prevents the flow of power from V CC to ground during a sleep mode, but otherwise allow the flow of power from VCC to ground. Filter Circuitry Fig. 5 shows detailed circuitry 500 for filter 1 and filter 2 of Fig. 2. The filter circuitry 500 includes an inverter 502, a NOR gate 504, a delay circuit 506 and an enabling circuit 508. The filter input labeled FIN provides a signal to inverter 502 which provides input signal buffering. The output of inverter 502 is provided directly to a V A input of NOR gate 504, and through delay circuitry 506 to an input V B of NOR gate 504. The output of inverter 504 is provided through enabling circuit 508 to form the output (FOUT) of filter circuitry 500. Delay circuitry 506 includes two inverters 510 and 512 connected in series between the output of inverter 502 and V B . A capacitive delay is provided between inverters 510 and 512 by P-channel transistors 514 and 516 and by capacitive elements 518 and 520. Transistor 514 has its drain and gate connected to V DD and its source connected to the drain of transistor 516. Transistor 516 has its gate connected to the output of inverter 502 and its source connected to the output of inverter 510. Transistors 514 and 516 coupled with inverters 510 and 512 provide a 12 ns delay. Capacitive elements 518 and 520 are coupled to the output of inverter 510 to increase the delay of delay circuitry 506. Signals T1 and T2 being HIGH enable the capacitive elements 518 and 520. Note that in the circuitry of Fig. 2, T1 and T2 are grounded because only a 12 ns delay is desired. Essentially, for the circuitry of filters 1 and 2 of Fig. 2, capacitive elements 518 and 520 can be removed. With one of the capacitive elements 518 and 520 turned on, the delay will increase to approximately 25 ns. With both 518 and 520 on, the delay will be approximately 35 ns. The circuitry for capacitive elements 518 and 520 is identical and will be described with respect to only capacitive element 518. Capacitive element 518 includes a transistor 520 with its source and drain connected to ground and its gate connected to the output of inverter 510 through transistors 522 and 524, the transistor 520 acting as a capacitor. N-channel transistor 522 has its drain connected to the source of P-channel transistor 524 and to the output of inverter 510. N-channel transistor 522 has its source connected to the drain of P-channel transistor 524 and to the gate of transistor 524. The gate of transistor 522 is connected directly to T1, while the gate of transistor 524 is connected to the gate of transistor 524 through inverter 526. As such, when T! is HIGH, current is provided through transistors 522 and 524 to transistor 520 which acts as a capacitor. With T1 LOW, transistors 522 and 524 cut off power to transistor 520. The circuitry for inverter 512 includes three P-channel transistors 531, 532 and 533 and three N-channel transistors connected in a Schmitt trigger configuration. Transistors 531, 532, 533, 541, 542, and 543 are connected similar to transistors 412, 414, 416, 422, 424, and 426 of the Schmitt trigger 400 with the input of inverter 512 formed by the input (IN) of Fig. 4 and the output of inverter 512 formed by the input to inverter 432 of Fig. 4. The enabling circuitry 508 includes two inverters 552 and 554, two N-channel transistors 555 and 556 and two P-channel transistors 557 and 558. Transistor 555 has a drain connected to receive the output of NOR gate 504 as well as to the source of transistor 557. The source of transistor 555 is connected to the drain of transistor 557 and to the input of output buffer 554. Transistor 556 has a drain connected to the FIN input signal as well as to the source of transistor 558. The source of transistor 556 is connected to the drain of transistor 558 and to the input of output buffer 554. The gates of transistors 555 and 558 are connected directly to receive the signal T0. The gates of transistors 557 and 556 receive the signal T0 through inverter 552. In operation, when T0 is HIGH, the filter 500 functions with the output of inverter 554 (FOUT) following the output of NOR gate 504. With T0 low, the filter is disconnected and the output of inverter 554 (FOUT) follows FIN. With signals T1 and T2 being LOW, disabling the capacitance provided by capacitance elements 518 and 520, the inverters 510 and 512 along with capacitive elements 514 and 516 introduce a delay of approximately 12 nanoseonds. With T1 or T2 provided HIGH, the delay of 506 is increased to either 35 ns or 35 ns as discussed above. Consequently, the delayed signal V B at the input of NAND gate 504 is the same as signal V A which is applied to the other input of NOR gate 504, but delayed by approximately 12 ns, assuming T1 and T2 are LOW. As discussed previously, a pulse of less than 12 ns is considered a glitch from the input buffer on a SCSI bus which is desired to be removed. With a pulse applied at the input of filter 500 (FIN), a LOW signal will arrive at V A while a LOW will arrive at input V B 12 ns later. The output of NAND gate 504 remains LOW until a LOW is received from both inputs V A and V B . Thus, with a pulse of less than 12 ns at the FIN input, V A and V B will never be LOW at the same time, and a corresponding change in the output signal FOUT indicative of the pulse will never be generated. With a pulse of greater than 12 ns at the FIN input, V A and V B will both go low after a delay of 12 ns, and a corresponding pulse will be delivered at FOUT delayed by approximately 12 ns. Filters 1 and 2 Filters 1 and 2 are provided with T0 connected to V cc and T1-2 connected to ground, thus enabling the filter 500 and creating a delay of 12 ns. Note that the filter circuitry 500 only responds to a FIN signal which transitions from LOW to HIGH to LOW. Thus, by utilizing filter circuitry 500 as filter 1 of Fig. 2, only such LOW-HIGH-LOW pulses can be eliminated. Note also that the logic diagram 501 for the circuitry 500 is an inverter. Thus, even though HIGH-LOW-HIGH pulses less than 12 ns are not eliminated, they are inverted. Thus by providing two filters, filter 1 and filter 2 of Fig. 200 in series, pulses less than 12 ns can be eliminated with LOW-HIGH-LOW transitions and with HIGH-LOW-HIGH transitions. Thus, noise due to large devices on the SCSI bus can be eliminated by filter 1, and reflections of such noise due to long cable lengths can be eliminated by filter 2. Filter 3 Fig. 6 shows the circuitry for filter 3. As shown, filter 3 includes the circuitry 500 of Fig. 5 followed by an additional inverter 600 to invert the signal inverted by the circuitry of Fig. 5. In the circuitry of Fig. 2, T0 is typically connected to V DD to activate the filter. Additionally, T1 and T2 are connected to V DD to provide a 35 ns delay. Thus, the circuitry of Fig. 3 filters noise pulses less than 35 ns typically found on a SCSI bus, while filters 1 and 2 are provided to remove noise due to pulses less than 12 ns which may be provided by, more recently developed circuitry which can generate additional noise. Although the invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many modifications will fall within the scope of the claim which follows.

Claims: A filter for filtering noise from a first signal on a SCSI bus as provided by an input buffer comprising: a schmitt trigger for receiving the first signal and providing a digital signal version of the first signal as a second signal; a first filter for filtering positive pulses having a pulse width less than 12 nanoseconds from the second signal and inverting the second signal to form a third signal; a second filter for filtering negative pulses having a pulse width less than 12 nanoseconds from the third signal and inverting the third signal to form a fourth signal; a third filter for filtering pulses having a pulse width less than 35 nanoseconds from the fourth signal and inverting the fourth signal to form a fifth signal; and an inverter for inverting the fifth signal to form a filter output.

Inventors: SZETO KINYUE, WU CHIH-SIUNG, SZETO, KINYUE, WU, CHIH-SIUNG
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1994
Main classification: H03K5
IPC codes: G06F13, G06F3, H03H17, H03K17, H03K5, H03K19