DIRECT-CURRENT IMPRESSING CIRCUIT

Abstract: Both ends of the primary winding of a transformer (T₃ or T₄) or a choke coil (L₂ or L₃) are connected to a current mirror circuit or a constant-voltage circuit. The AC component bypasses a transistor (Q₁ or Q₂) constituting a current mirror circuit or a constant-voltage circuit through a bypass circuit comprising a capacitor (C₂). The DC magnetization caused in the core or yoke of the transformer (T₃) or the choke coil (L₂) is canceled by DC currents made to flow through the primary winding of the transformer (T₃) or choke coil (L₂) in opposite directions. The DC magnetization caused in the core or yoke of the transformer (T₄) or the choke coil (L₃) is reduced to a very low extent when the DC currents made to flow through the primary winding of the transformer (T₄) or the choke coil (L₃) are suppressed. Therefore, the circuit including the transformer (T₃) can be miniaturized, and the characteristics of the circuit can be improved, because a gap is not needed in the magnetic circuit of this circuit.

Description: TECHNICAL FIELD The present invention relates to a DC application circuit for applying a direct current to a transformer or a choke coil for use in various transmission circuits. BACKGROUND ART In order to extract AC components from signals containing DC components and AC components, use has been hitherto made of a transformer, for example, as shown in Fig. 14. In this diagram, a choke coil L 1 is connected in parallel to the input side of a transformer T 1 via a direct current isolation capacitor C 1 . Therefore, when this circuit receives DC/AC superimposed signals, only the AC components are applied to the transformer T 1 . However, this configuration entails problems that the choke coil L 1 tends to be large-sized resulting in increased size of the entire circuit or that the use of the choke coil L 1 may lead to raised component costs. To solve such problems, use as a transformer may be made of a DC applicable transformer T 2 , for example, as shown in Fig. 15. The DC applicable-type transformer T 2 includes a large gap in its magnetic path to eliminate the influence of a DC magnetization, thereby allowing application of the DC components. Disadvantageously, the configuration as shown in Fig. 15 needs to have enlarged external dimensions due to the provision of the gap to eliminate the influence of the DC magnetization. For instance, the number of turns of the transformer T 2 is 1600 turns on both the primary side and the secondary side, with a core size of 35 mm (so-called EI-35). The use of such a large-sized transformer T 2 would result in an attenuation value as low as 3dB at 100 Hz as seen in Fig. 16. Japanese Patent No. JP-A-1,143,528 shows a circuit for combining an AC signal with a DC signal. A current mirror is used to apply a direct current to both the primary and secondary windings of a transformer. The currents applied to each winding flow in opposite directions with values selected so as to make the core biased magnetization of the transformer zero. Japanese Patent No. JP-A-58-25,755 shows a circuit including a hybrid transformer having three primary windings. A DC signal applied to the transformer is passed through an additional winding in the opposite direction to the main windings, thus the DC magnetic field is the iron core of the transformer is reduced. Both of these applications require additional windings to reduce DC magnetization of a magnetic member associated with the transformer. SUMMARY OF THE INVENTION The present invention was conceived to overcome the above problems. It is therefore an object of the present invention to enable a direct current to be applied to a winding of a transformer or a choke coil without increasing the size of a circuit configuration, as well as to improve the characteristics. In the embodiments of the present invention, DC magnetisation, which may be caused by the DC component of a DC/AC superimposed signal supplied to the winding, is reduced or eliminated by a DC magnetization prevention circuit. Thus, there is no need to provide a gap to compensate for influence of the DC magnetization, which will result in no increase in the external dimensions and no degradation in the characteristics. Additionally, upon the evaluation of the characteristics, the characteristics do not vary largely depending on whether the input is a DC/AC superimposed signal or only an AC signal, thus facilitating the evaluation and testing. The embodiments of the present invention may be widely applied to general transmission circuits. According to a first aspect of the present invention there is provided a circuit for applying a direct current to a winding comprising a winding for carrying a DC/AC superimposed signal consisting of a DC component and an AC component superimposed on each other, said winding including a centre tap, and a DC magnetization prevention circuit for preventing DC magnetization of a magnetic member associated with said winding due to the DC component flowing therethrough, characterised in that said centre tap is arranged to receive the DC/AC superimposed signal, and in that said DC magnetization prevention circuit controls the flow of the DC component through parts of said winding on opposite sides of said centre tap so that the DC component flows in opposite directions in the two parts. In the embodiments of this first aspect of the present invention, the DC component flows in opposite directions through the two parts of the winding from the boundary defined by the center tap, whereby the magnetization due to the DC component can be offset by the flow in each part of the winding, accomplishing a preferable prevention of the DC magnetization in the magnetic member. The embodiments of this aspect of the invention may be implemented by a current mirror circuit having a diode side circuit connected to one end of the winding and a transistor side circuit connected to the other end thereof, and a bypass circuit for bypassing said AC component in said winding around said diode side circuit of said current mirror circuit so that only the DC component is input to the current mirror circuit. Such implementation will allow the DC component of the DC/AC superimposed signal fed to the winding to be led into the current mirror circuit. Through the bypass circuit, the AC component is bypassed via a part of the winding to the exterior of the current mirror circuit. Accordingly, a part of the winding through which the AC component flows serves its original function for the transformer or the choke coil, while simultaneously the DC component separates from the center tap of the winding into two directions (into the diode side circuit and the transistor side circuit of the current mirror circuit), with the result that the magnetization due to the DC component is offset by the flow in each of the two parts of the winding. According to a second aspect of the present invention there is provided a circuit for applying a direct current to a winding comprising a winding for carrying a DC/AC superimposed signal consisting of a DC component and an AC component superimposed on each other, and a DC magnetization prevention circuit for preventing DC magnetization of a magnetic member associated with said winding due to the DC component flowing therethrough, said DC magnetization prevention circuit including a current mirror circuit having a diode side circuit and a transistor side circuit, and a bypass circuit providing an AC bypass for the diode side of said current mirror circuit, characterised by a shunt circuit for dividing the input current of the DC/AC superimposed signal into two flows and also for supplying one of them to the diode side circuit of said current mirror circuit and the other to the transistor side circuit thereof, in that said diode side circuit is connected to one end of said winding and said transistor side circuit is connected to the other end thereof, and in that said shunt circuit is arranged such that the direct current flowing to the diode side circuit of the current mirror circuit is sufficiently smaller in value than the direct current flowing to the transistor side circuit thereof such that the DC component to be input to said winding bypasses said winding, thereby reducing the DC component flowing through said winding to such a degree that it can be ignored. In the embodiments of this aspect of the invention, almost all of the DC component to be input to the winding is bypassed to the exterior of the winding by virtue of the DC magnetization prevention circuit. As a result, the DC component flowing through the winding is reduced to such a degree that it can be ignored, and hence little or no DC magnetization takes place. Thus, without providing the center tap on the winding, the same DC magnetization preventing function as the embodiments of the first aspect of the present invention can be realized. The DC component of the DC/AC superimposed signal is divided by the shunt circuit into the diode side circuit and the transistor side circuit of the current mirror circuit. At that time, the shunt circuit controls or regulates the flow of the direct current so that the direct current flowing into the diode side circuit of the current mirror circuit is sufficiently smaller in value than the direct current flowing into the transistor side circuit thereof. Therefore, the DC component flowing into the diode side circuit of the current mirror circuit and hence into the winding connected thereto becomes minute. The bypass circuit serves to bypass the diode side circuit of the current mirror circuit for an alternating current. This will allow the characteristics viewed from the input side to coincide with the characteristics of the winding. Moreover, the shunt circuit can be implemented by the resistors, and the appropriate setting of the values of the resistors will ensure a preferred implementation of the above function. Preferably, the shunt circuit includes a resistor connected to the diode side circuit and a resistor connected to the transistor side circuit of the current mirror circuit, the value of the resistor connected to the diode side circuit being sufficiently large for the value of the resistor connected to the transistor side circuit to be ignored. According to a third aspect of the present invention there is provided a circuit for applying a direct current to a winding comprising the winding for carrying a DC/AC superimposed signal consisting of a DC component and an AC component superimposed on each other, a DC magnetization prevention circuit for preventing DC magnetization of magnetic member associated with said winding due to the DC component flowing therethrough, characterised in that said DC magnetization prevention circuit includes a transistor connected in parallel to the winding and a biasing circuit connected in series to the winding for biasing said transistor, in that a bypass circuit provides an AC bypass for said biasing circuit, and in that said DC magnetization prevention circuit is arranged such that the DC component to be input to said winding bypasses said winding, thereby reducing the DC component flowing through said winding to such a degree that it can be ignored. The DC/AC superimposed signal input to the winding is supplied on one hand to the transistor and on the other hand to the winding. The bias circuit connected in series to the winding is alternatingly bypassed by the bypass circuit so that the AC impedance of the transistor has a large value. Furthermore, the value of the DC component flowing into the biasing circuit via the winding results in a value determined by the current amplification factor of the transistor, and hence in a sufficiently small value compared with the value of the DC component flowing into the transistor. Thus, in this configuration, the DC component flowing into the winding becomes very minute. Preferably, the implementation of the transistor by Darlington connection will ensure a circuit having a greater current driving ability. The bias circuit may be configured as a bleeder bias circuit consisting of a plurality of resistors connected in series for supplying a bias voltage from a connection point thereof. This will allow the transistor bias circuit to act as a voltage regulator, ensuring a regulated action. Further, by constituting a low-pass filter using the capacitors of the bypass circuit and the resistors of the bleeder biasing circuit, the leakage of the AC component into the transistor can be reduced. Use of this low-pass filter will allow the omission of some of the resistors and reduction in the generation of heat. In each of the embodiments of the present invention the winding is preferably a primary winding of a transformer or a choke coil. This means that the embodiments of the present invention are applicable to not only the case where the winding is the primary winding of a transformer but also to the case where the winding is a choke coil. In this manner, the embodiments of the present invention have a very wide range of applications. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a circuit diagram showing a configuration of a circuit according to the first embodiment of the present invention; Fig. 2 is a graphical representation showing characteristics of this embodiment; Fig. 3 is a circuit diagram showing a configuration of a circuit according to the second embodiment of the present invention; Fig. 4 is a circuit diagram showing a configuration of a circuit according to the third embodiment of the present invention; Fig. 5 is a circuit diagram showing a configuration of a circuit according to the fourth embodiment of the present invention; Fig. 6 is a circuit diagram showing a configuration of a circuit according to the fifth embodiment of the present invention; Fig. 7 is a circuit diagram showing a configuration of a circuit according to the sixth embodiment of the present invention; Fig. 8 is a circuit diagram showing a configuration of a circuit according to the seventh embodiment of the present invention; Fig. 9 is a circuit diagram showing a configuration of a circuit according to the eighth embodiment of the present invention; Fig. 10 is a circuit diagram showing a configuration of a circuit according to the ninth embodiment of the present invention; Fig. 11 is a circuit diagram showing a configuration of a circuit according to the tenth embodiment of the present invention; Fig. 12 is a circuit diagram showing a configuration of a circuit according to the eleventh embodiment of the present invention; Fig. 13 is a circuit diagram showing a configuration of a circuit according to the twelfth embodiment of the present invention; Fig. 14 is a circuit diagram showing a configuration of a circuit according to the first prior art example; Fig. 15 is a circuit diagram showing a configuration of a circuit according to the second prior art example; and Fig. 16 is a graphical representation showing characteristics of this prior art example. In the diagrams, T 3 and T 4 denote a transformer. A transistor is designated at Q 1 and Q 2 , and a capacitor is designated at C 2 to C 4 . L 2 and L 3 represent a choke coil, and Z represents a load impedance. It is to be noted in the diagrams that the same elements are indicated by the same reference numerals. BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of the present invention will now be described with reference to the accompanying drawings. Referring first to Fig. 1, there is shown a configuration of a circuit according to the first embodiment of the present invention. In the shown circuit, use is made of a transformer T 3 with an additional primary winding channel. A DC/AC superimposed signal is provided as an input to a center tap of the transformer T 3 . Through a resistor R 1 , one end of a primary winding of the transformer T 3 is connected to a collector of a transistor Q 1 . The other end of the primary winding is coupled to a collector of a transistor Q 2 . A short circuit is established between a base and the collector of the transistor Q 1 so that the transistor Q 1 functions as a diode. Emitters of the transistors Q 1 and Q 2 are connected to an input terminal via resistors R 2 and R 3 , respectively. Bases of the transistors Q 1 and Q 2 are coupled with each other so that a current mirror circuit is made up of the transistors Q 1 and Q 2 . In addition, the resistor R 1 is located between the one end of the winding and the transistor Q 1 , and a capacitor C 2 bypasses the resistor R 1 , transistor Q 1 and resistor R 2 . When the thus configured circuit receives the DC/AC superimposed signal, DC components thereof are led into a current mirror circuit through the primary winding of the transformer T 3 . More specifically, a direct current fed from the center tap is led via a part (upper side of the diagram) of the primary winding into the transistor Q 1 of the current mirror circuit, while simultaneously a direct current having the same value as the above (when a mirror ratio is 1) is led via the other part (lower side of the diagram) of the primary winding into the transistor Q 2 . In this case no AC components flow into the transistor Q 1 since it is bypassed by the bypass capacitor C 2 due to the presence of the resistor R 1 . As a result, DC magnetization of a core or a yoke (not shown) attendant on the supply of the DC components into the primary winding of the transformer T 3 will be canceled because flow of the DC components on one side of the center tap on the primary winding is opposite in direction to that on the other side. Thus, there is no need to provide a gap in the core or the yoke in consideration of the DC magnetization, thereby preventing the transformer T 3 from increasing in size. It is to be appreciated that the lower part in the diagram of the primary winding of the transformer T 3 (the part on the side of the transistor Q 2 of the current mirror circuit) does not function as an original primary winding of the transformer since no AC components flow therethrough. Allowed to function as the original primary winding of the transformer is the upper part in the diagram (the part on the side of the transistor Q 1 of the current mirror). In order to clarify the effect of this embodiment, comparisons will now be made between this embodiment and the above-described second prior art example according to EI-35 specification. In the case where this embodiment is used for the same application as the thus configured second prior art example, 800 turns in total on the primary side and 400 turns on the secondary side will be sufficient for the number of turns of the transformer T 3 , with a core size of 14 mm (so-called EI-14). Furthermore, this circuit can be constituted of general-purpose elements. By way of example, the transistor Q 1 and Q 2 can be transistors such as 2SC1815, manufactuered by the Toshiba Corporation, and the resistors R 1 , R 2 , and R 3 and the capacitor C 2 can be implemented by elements having general specifications and values such as 150 Ω and 100 µF, respectively. Moreover, this embodiment ensures remarkably improved characteristics compared with the second prior art example set forth hereinabove. As is seen in Fig. 2, an attenuation value at, for instance, 100Hz results in approximately -1 dB, and attenuation characteristics describe a substantially flat curve from lower frequencies to higher frequencies. In the characteristics of this circuit, there is very little difference between the case of inputting the DC/AC superimposed signal and the case of inputting only the AC components, which will facilitate the valuation and testing of the characteristics. Referring to Fig. 3, there is depicted a configuration of a circuit according to the second embodiment of the present invention. In the shown circuit, use is made of a transformer T 4 reduced in size compared with the conventional transformer, for reasons which will be described later. The DC/AC superimposed signal is input to the transformer T 4 having, for instance, an input impedance of 600 Ω and an output impedance of 600 Ω. Firstly, this embodiment differs from the first embodiment in the connection of the transformer to the current mirror circuit. More specifically, although the upper and lower terminals of the transformer T 3 were coupled to the diode side and the transistor side, respectively, of the current mirror circuit in the first embodiment, the lower and upper terminals of the transformer T 4 are coupled to the diode side and the transistor side, respectively, in this embodiment. Secondly, this embodiment differs from the first embodiment in that the transformer T 4 used is not provided with the center tap, and that the DC/AC superimposed signal is input to the upper terminal of the transformer T 4 . When the thus configured circuit receives the DC/AC superimposed signal, DC components I 0 thereof are divided into a direct current I 1 to the collector of the transistor Q 2 and DC components I 2 of a primary current to the transformer T 4 . The current I 2 is led into the current mirror circuit via the primary winding of the transformer T 4 . The current I 2 causes a DC voltage R 2 I 2 between ends of the resistor R 2 , allowing the same voltage to occur between ends of the resistor R 3 . A ratio of the current I 1 to the current I 2 is therefore determined by values of the resistors R 1 to R 3 . For instance, let the resistors R 1 and R 2 be 10 KΩ, and the resistor R 3 be 10 Ω. When a current of 100 mA flows through the resistor R 3 , a voltage of 100 mA x 10 Ω = 1V will appear between ends of the resistor R 3 . At that time, the ends of the resistor R 2 are also subjected to the same voltage of 1V, and hence the value of the current flowing through the resistor R 2 is 1V / 10 KΩ = 0.1 mA. In other words, when the circuit of this embodiment receives the DC/AC superimposed signal having DC components I 0 = 100 mA, an extremely large direct current (about 100 mA), compared with the direct current of 0.1 mA flowing through the resistor R 2 , will flow into the transistor Q 1 and the resistor R 3 . This means that almost all of the DC components I 0 of the input signal flow into the transistor Q 2 and the resistor R 3 , but a very minute DC current is allowed to flow through the primary winding of the transformer T 4 . As a result, the DC magnetization of the core or the yoke which might be otherwise caused by the supply of the DC components into the primary winding of the transformer T 4 can be ignored due to the extremely minute DC components flowing therethrough. This will result in no need to provide a gap in consideration of the DC magnetization, whereby it is possible to prevent the transformer T 4 from increasing in size. In addition, the AC components of the input DC/AC superimposed signal flow into the primary winding of the transformer T 4 since a collector-emitter impedance of the transistor Q 2 is infinite. These AC components are bypassed by the capacitor C 2 . Thus, between the input terminals of this circuit, there will appear characteristics of the transformer T 4 . In this embodiment, as long as the number of turns of the transformer t 4 is 400 turns on both the primary side and the secondary side, the core size may be 14 mm (so-called EI-14). Additionally, this circuit can be made up of general-purpose elements. It is to be appreciated that, for instance, the transistor Q 1 and Q 2 can be transistors such as 2SC1815, manufactured by the Toshiba Corporation, and the resistors R 1 , R 2 , and R 3 and the capacitor C 2 can be implemented by elements having general specifications and values. In the same manner as the first embodiment, this embodiment also ensures remarkably improved characteristics compared with the second prior art example. That is, the same characteristics as seen in Fig. 2 can be obtained. Also, like the first embodiment, the circuit characteristics hardly vary between the case of inputting the DC/AC superimposed signal and the case of inputting only the AC components. Referring to Fig. 4, there is illustrated a configuration of a circuit according to the third embodiment of the present invention. Also in the shown circuit, use is made of the same transformer T 4 as in the second embodiment. This embodiment differs from the second embodiment in that it includes a voltage regulator in place of the current mirror circuit. More specifically, with the elimination of the transistor Q 1 having the short-circuited base-collector, a bleeder biasing circuit for the transistor Q 2 is made up of the resistors R 1 and R 2 . The resistors R 1 and R 2 are bypassed by the capacitor C 2 in an alternating manner, and hence the biasing by the resistors R 1 and R 2 will result in a DC biasing. The transistor Q 2 and the biasing circuit (including the resistors R 1 and R 2 ) constitute the voltage regulator, whereby collector-emitter impedance of the transistor Q 2 results in an alternatingly high impedance. The transistor Q 2 can be 2SC3298, manufactured by the Toshiba Corporation, for instance. The DC components I 0 of the DC/AC superimposed signal are divided into the direct current I 1 to the collector of the transistor Q 2 and the DC component I 2 of the primary current of the transformer T 4 , the current I 2 being led via the primary winding of the transformer T 4 into the biasing circuit. The base of the transistor Q 2 is bleeder-biased by virtue of the current I 2 , whereby the base-emitter voltage of the transistor Q 2 results in a constant voltage, to allow the direct current I 1 having a value in accordance with this voltage to flow into the collector of the transistor Q 2 . The ratio of the current I 1 to the current I 2 depends on a current amplification factor of the transistor Q 2 and a design of the biasing circuit. Thus, the current I 1 results in an extremely large current compared with the current I 2 . Consequently, in the same manner as the second embodiment, the DC components I 0 of the input signal hardly flow into the primary winding of the transformer T 4 . Therefore, similarly, the need to provide a gap in consideration of the DC magnetization is eliminated and the transformer T 4 is prevented from increasing in size. This embodiment also realizes a transformer T 4 reduced in size to the same degree as the second embodiment, while ensuring characteristics equivalent thereto. In addition, the number of the transistors can be decreased by one, contributing to not only the simplification of the circuit configuration but also the curtailment of the production costs. Referring to Fig. 5, there is shown a configuration of a DC application circuit according to the fourth embodiment of the present invention. This embodiment differs from the third embodiment in that it employs Darlington connection including a couple of transistors (for instance, 2SD1162s, manufactured by NEC Corporation) as the transistor Q 2 . Correspondingly, a capaictor C 4 is provided in parallel with the primary winding of the transformer T 4 . A capacitor C 3 is further provided in parallel with the resistor R 2 . The Darlington connection of the transistor Q 2 will ensure its increased current drive ability. The addition of the capacitor C 3 allows a low-pass filter to be constituted of the resistor R 1 , and the capacitors C 2 and C 3 , thereby reducing a leak of the AC components to the transistor Q 2 side. Referring to Fig. 6, there is depicted a configuration of a DC application circuit according to the fifth embodiment of the present invention. This embodiment differs from the fourth embodiment in that the resistor R 2 is eliminated therefrom. The elimination of the resistor R 2 results in no generation of heat by the resistor R 2 , realizing a circuit generating less heat. Referring to Fig. 7, there is illustrated a configuration of a DC application circuit according to the sixth embodiment of the present invention. This embodiment differs from the third embodiment in that the capacitor C 3 is provided without the resistor R 2 . Elimination of the resistor R 2 realizes a circuit generating less heat, and the addition of the capacitor C 3 ensures a reduction in leak age of the AC components into the transistor Q 2 side. Referring finally to Figs. 8 to 13, there are shown configurations of DC application circuits, respectively, according to the seventh to twelfth embodiment of the present invention. The shown circuits differ from the first to sixth embodiment in that they are a circuit for applying direct current to a choke coil L 2 or L 3 . These embodiments also ensure the effects such as reduction in size. It is to be noted that in the above description the mirror ratio of the current mirror circuit was 1, which is associated with the fact the center tap halves the number of winding in the first and seventh embodiments. However, in the execution of the present invention, mirror ratios other than 1 may be designed. For instance, there may be employed the transistors Q 1 and Q 2 having proper emitter areas, in accordance with the setting of the position of the center tap for the first and seventh embodiments, and so as to allow a minute direct current to flow through the primary winding of the transistor T 4 for the second and eighth embodiments. However, in view of reducing the influence of the DC magnetization as well as providing an inexpensive configuration, it is most preferable to employ the mirror ratio of 1 in the first and seventh embodiments and to employ as large a mirror ratio as possible in the other embodiments using the current mirror circuit. Moreover, the value of the resistor R 1 may be set in accordance with the DC value. Also, the diode-connected transistor Q 1 may be replaced with a diode. INDUSTRIAL APPLICABILITY The present invention is applicable to a facsimile or various other transmission devices. More specifically, the present invention is widely applicable to transformers or inductors for use in a circuit processing a superimposed signal of a DC signal and an AC signal.

Claims: A circuit for applying a direct current to a winding, comprising: a winding for carrying a DC/AC superimposed signal consisting of a DC component and an AC component superimposed on each other, said winding including a centre tap; and a DC magnetization prevention circuit for preventing DC magnetization of a magnetic member associated with said winding due to the DC component flowing therethrough; characterised in that said centre tap is arranged to receive the DC/AC superimposed signal; and in that said DC magnetization prevention circuit controls the flow of the DC component through the parts of said winding on opposite sides of said centre tap so that the DC component flows in opposite directions in the two parts. A circuit for applying a direct current to a winding according to Claim 1, wherein said DC magnetization prevention circuit includes: a current mirror circuit having a diode side circuit (Q 1 ) connected to one end of said winding and a transistor side circuit (Q 2 ) connected to the other end thereof; and a bypass circuit (C 2 ) for bypassing said AC component in said winding around said diode side circuit of said current mirror circuit, so that only the DC component is input to the current mirror circuit. A circuit for applying a direct current to a winding, comprising: a winding for carrying a DC/AC superimposed signal (I 0 ) consisting of a DC component and an AC component superimposed on each other; and a DC magnetization prevention circuit for preventing DC magnetization of a magnetic member associated with said winding due to the DC component flowing therethrough, said DC magnetization prevention circuit including: a current mirror circuit having a diode side circuit (Q 1 ) and a transistor side circuit (Q 2 ); and a bypass circuit (C 2 ) providing an AC bypass for the diode side (Q 1 ) of said current mirror circuit; characterised by a shunt circuit for dividing the input current of the DC/AC superimposed signal into two flows (I 1 , I 2 ) and also for supplying one of them (I 2 ) to the diode side circuit (Q 1 ) of said current mirror circuit and the other (I 1 ) to the transistor side circuit (Q 2 ) thereof; in that said diode side circuit (Q 1 ) is connected to one end of said winding and said transistor side circuit (Q 2 ) is connected to the other end thereof; and in that said shunt circuit is arranged such that the direct current (I 2 ) flowing to the diode side circuit (Q 1 ) of the current mirror circuit is sufficiently smaller in value than the direct current (I 1 ) flowing to the transistor side circuit (Q 2 ) thereof such that the DC component to be input to said winding bypasses said winding, thereby reducing the DC component flowing through said winding to such a degree that it can be ignored. A circuit for applying a direct current to a winding, according to Claim 3, wherein said shunt circuit includes a resistor (R 2 ) connected to the diode side circuit (Q 1 ) and a resistor (R 3 ) connected to the transistor side circuit (Q 2 ) of said current mirror circuit, the value of said resistor (R 2 ) connected to the diode side circuit (Q 1 ) being sufficiently large for the value of said resistor (R 3 ) connected to the transistor side circuit (Q 2 ) to be ignored. A circuit for applying a direct current to a winding, comprising: the winding for carrying a DC/AC superimposed signal (I 0 ) consisting of a DC component and an AC component superimposed on each other; a DC magnetization prevention circuit for preventing DC magnetization of magnetic member associated with said winding due to the DC component flowing therethrough; characterised in that said DC magnetization prevention circuit includes: a transistor (Q 2 ) connected in parallel to the winding; and a biasing circuit (R 1 , R 2 ) connected in series to the winding for biasing said transistor (Q 2 ); in that a bypass circuit (C 2 ) provides an AC bypass for said biasing circuit (R 1 , R 2 ); and in that said DC magnetization prevention circuit is arranged such that the DC component to be input to said winding bypasses said winding, thereby reducing the DC component flowing through said winding to such a degree that it can be ignored; A circuit for applying a direct current to a winding, according to Claim 5, wherein said biasing circuit comprises a bleeder biasing circuit consisting of a plurality of resistors (R 1 , R 2 ) connected in series for supplying a bias voltage from a connection point thereof. A circuit for applying a direct current to a winding, according to Claim 6, wherein in co-operation with said resistors (R 1 , R 2 ) constituting said bleeder biasing circuit, said bypass circuit (C 2 ) constitutes a low-pass filter for reducing leakage of the AC component into the transistor (Q 2 ) connected in parallel to said winding. A circuit for applying a direct current to a winding, according to Claim 5, wherein said transistor (Q 2 ) connected in parallel to said winding is an equivalent transistor obtained by Darlington connection of a plurality of transistors. A circuit for applying a direct current to a winding according to Claim 5, wherein in co-operation with a capacitor (C 3 ) constituting said bypass circuit (C 2 ), said biasing circuit (R 1 , R 2 ) constitutes a low-pass filter for reducing leakage of the AC component into the transistor (Q 2 ) connected in parallel to said winding. A circuit for applying a direct current to a winding, according to any one of Claim 1, Claim 3 and Claim 5, wherein said winding is a primary winding of a transformer (T 3 , T 4 ) or a choke coil (L 2 , L 3 ).

Inventors: ICHIKAWA SYUZI, UMEDA KAZUHIRO, ICHIKAWA, SYUZI, UMEDA, KAZUHIRO
Applicants: TOKYO TSUKI CO LTD, TOKYO TSUKI CO., LTD.
Application year: 1994
Main classification: H04M19
IPC codes: H04M19, H01F27, H03H11, G05F1