Semiconductor nonvolatile memory device

Abstract: A semiconductor nonvolatile memory device which can adopt bit line system and can achieve an enhancement of speed of the read out time etc., which device adopting a differential type sensing system comprising a bit line BL and an inverted bit line BL_ connected in series to a sense amplifier SA f , wherein provision is made of a first memory cell MC 1 connected to a word line WL and the bit line BL; a second memory cell MC 2 connected to the word line WL which is common also for the first memory cell MC 1 , and, connected to the inverted bit line BL_; and a circuit BVA which retains the potential of either one of bit lines of the bit line BL and the inverted bit line BL_ at the first potential at the time of a read out operation, and, sets the potential of the other bit line at the second potential made to have a difference from the first potential for a predetermined time.

Description: BACKGROUND OF THE INVENTION 1. Field of the invention The present invention relates to a semiconductor nonvolatile memory device such as a flash EEPROM which can be electrically rewritten. 2. Description of the Related Art As a symmetrical arrangement of a bit line and an inverted bit line having a complementary level to this in a semiconductor memory device, for example, a dynamic random access memory (DRAM) circuit, there is a so-called differential type sensing circuit (including flip-flop type), wherein, to produce a reference level for a differential sense amplifier, a reference cell referred to as a dummy cell corresponding to a storage cell is arranged in the inverted bit line on the opposite side to the side for reading data. Conventionally, it has been impossible for a flash EEPROM, particularly a NAND type, to adopt the so-called folded bit line method which is advantageous for the enhancement of speed etc. and has been adopted in a DRAM circuit etc. Therefore, as shown in Fig. 1, there has been adopted an open bit line system (refer to for example Document 1: "A Quick Intelligent Program Architecture for 3V-only NAND EEPROMS"; Sympo. VLSI Cir. pp 20 - 21. 1992) in which data lines DLR and DLL which become symmetrical lines around a sense amplifier (SA) 1 are separated in terms of position, and memory cell arrays (MCAR) 11 and (MCAL) 6 are connected as the storage cells and dummy cells (DCLR) 14 and (DCLL) 2 to the respective data lines (DR) 2 and (DL) 15. In the above-mentioned open bit line system, however, even though lines are in a symmetrical arrangement, they are separated in terms of position, and therefore there is liable to be an imbalance in the electrical characteristics between the symmetrical lines. Further, it is not possible to completely equalize the noise voltage resulting from connection from another conductive body such as a peripheral circuit to the symmetrical lines. Therefore, the influence of the noise is larger than that of the folded bit line system and it is difficult to achieve an enhancement of sensitivity of the sense amplifier, resulting in a problem that the enhancement of speed was difficult. As a result, a NAND type cell has been considered as a low speed and large capacity memory, and the random access time becomes about 1 µs. Also, as shown in Fig. 2, to construct the folded bit line system, a divided bit line system having a divided bit line structure (document 2: "High Speed Page Mode Sensing Scheme for EPROM's and Flash EEPROM's using Divided Bit Line Architecture"; Sympo VLSI Cir. pp 97 - 98, 1990) has been proposed. Note that, in Fig. 2, SA denotes a sense amplifier 44; SRG denotes a storage cell 35; DCL denotes a dummy cell 25; WL denotes a word line 33; DWL denotes a dummy word line 23; BL denotes a bit line 21; BL_ denotes an inverted bit line 22; nt 1 to nt 4 denote n-channel MOS transistors 30, 27, 39, 41; and C B denotes a capacitor 26, 29, 37, 38; respectively. The folded bit line system is realized by dividing the bit line by turning on and off the transistors (nt 1 to nt 4 ) 30, 32, 39, 41 by the signals (SW1) 31 and (SW2) 40. In this divided bit line system, however, due to the necessity of sensing by connecting the divided bit line, the potential difference between the bit line BL and inverted bit line BL_ which were especially provided is reduced to a half potential difference. This disadvantage will be explained in further detail below referring to Fig. 2. Now assume that the signals (SW1) 31 and (SW2) 40 are at the low level, the transistors (nt 1 to nt 4 ) 30, 27, 39, 41 are in the OFF state, the storage cell (SRG) 35 and dummy cell (DCL) 25 pass a current, and the potentials of the bit line (BL) 21 or the inverted bit line (BL_) 22 become as follows: V BL 1 = 0 V V BL 2 = VPC - ΔV BL 2 V BL 1_ = VPC - ΔV BL 1_ V BL 2_ = 0 V where, VPC indicates a precharge level. Here, when assuming that the signal (SW1) 31 is made the high level and the transistors (nt 1 and nt 3 ) 30 and 39 are brought to the ON state, the following formulas stand: V BL = (1/2) (V BL 1 + V BL 2) = (1/2) (VPC - ΔV BL 2) V BL _ = (1/2) (V BL 1_ + V BL 2_) = (1/2) (VPC - ΔV BL 1_) Accordingly, it becomes: ΔV BL - BL_ = V BL - V BL _ = (1/2) (DV BL 1_ - DV BL 2) In this way, it ecomes the potential difference of 1/2. Prior art document EP-A-0 031 496 discloses a nonvolatile memory device in which memory cell blocks are connected to a bit line which forms an input to a differential sense amplifier which has its complementary input coupled to another memory cell block. The memory cell blocks are coupled to their respective bit lines through a pair of series-connected enhancement and depletion type transistors. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor nonvolatile memory device which can be made by a folded bit line structure, and improve an operation speed, such as a speed of the read-out time. To solve this object, the present invention provides a semiconductor nonvolatile memory device as specified in claim 1. Preferred embodiments of the invention are described in the subclaims. Specifically, the above-described memory cell may be a NOR type, or a NAND type. According to the present invention, in a structure having a plurality of memory cell blocks connected to the first and second bit lines, the state of connection of the respective blocks and bit lines is controlled by the selective gate comprising the two selective transistors connected in cascade. BRIEF DESCRIPTION OF THE DRAWINGS The above objects and features and other objects of the present invention will be more apparent from the following description with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an example of an open bit line system; Fig. 2 is a circuit diagram showing an example of a divided bit line system; Fig. 3 is a circuit diagram showing an embodiment of the semiconductor nonvolatile memory device according to the present invention; and Figs. 4A and 4B are vies showing an example of the structure of a memory cell array of Fig. 3. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 3 is a circuit diagram showing an embodiment of the semiconductor nonvolatile memory device according to the present invention. In the present circuit, in a NAND type flash memory, two upper selective transistors are provided, one being made to act as a depletion transistor, whereby it is possible to adopt the folded bit line system. A dummy cell is used as a reference cell. Also, this circuit has the same structure as that of the folded bit line of the well known DRAM circuit except the selective gate of each memory cell array is constituted by two stages. In Fig. 3, SA f denotes a flip-flop type sense amplifier 119 (The sense amplifier (SA f ) 119 is constituted by a flip-flop type sense amplifier which performs the cross connection of the input and output of two CMOS inverters); BL denotes a bit line 100; BL_ denotes an inverted bit line 101; MCA 1h and MCA 2h denotes the memory cell arrays 107 and 102 connected to the bit line (BL) 100; MCA 1 l and MCA 2 l are memory cell arrays 108 and 103 connected to the inverted bit line (BL_) 101; DCL h denotes a dummy cell 95 connected to the bit line (BL) 100; DCL l denotes a dummy cell 96 connected to the inverted bit line (BL_) 101; D denotes a data line 12; D_ denotes an inverted data line 125 taking a complementary level to that of the data line; and NT 11 to NT 16 denote nMOS transistors 93, 94, 116, 117, 123, and 124; respectively. Figure 4A and 4B are views showing an example of the structure of the memory cell array according to the present embodiment. As shown in Fig. 4A, each memory cell array is constituted by upper first and second selective transistors (SL 1 ) 133 and (SL 2 ) 135 connected in series; eight memory transistors (MT 0 to MT 7 ) 137, 139,..., 142 connected in series to the second selective transistor (SL 2 ) 135; and a lower selective transistor (SL 3 ) 144 connected in series between the memory transistor (MT 7 ) 142 and the ground. One of the first and second selective transistors (SL 1 ) 133 and (SL 2 ) 135 is constituted by a depletion transistor. In the memory cell array, the first selective transistor (SL 1 ) 133 is connected to the bit line (BL) 100 or the inverted bit line (BL_) 101. At this time, the first and -second selective transistors (SL 1 ) 133 and (SL 2 ) 135 of the memory cell array connected to the same bit line (BL) 100 or inverted bit line (BL_) 101 are alternately constituted by the depletion transistor in an order of connection from the side of the sense amplifier SA f . This is performed for taking the balance of the capacitance. Note that the structure of Fig. 4A is expressed by simplifying the same like Fig. 4B. An explanation will be made next of the operation by the above-described structure taking as an example a case where the data of the memory transistor connected to the selective gates indicated by (SG 11 ) 113 and (SG 21 ) 112 and connected to the word line WL j is read out. Note that, the explanation for the writing/erasing operation is omitted here. First, as the initial state, the signals PC (92), SAG (115), and Y i (122) are set at the low level (0 V). By this, the nMOS transistors (NT 11 to NT 16 ) 93, 94, 116, 117, 123, and 124 become the OFF state. Further, the signals DSG and SG are set at the low level and the word line WL j and dummy word line (DWL) 97 are set at the high level (5 V). Also, the VSAL (118) and VSAH (121) are set at the voltage V pc (91), and the data line (D) 126 and inverted data line (D_) 125 are set at (1/2) V CC level. In this state, the signals PC (92) and SAG (115) are set at the high level. By this, the nMOS transistors (NT 11 to NT 14 ) 93, 94, 116 and 117 become the ON state. As a result, the bit line (BL) 100 and inverted bit line (BL_) 101 are precharged to the voltage V pc (91). Next, the word line of the almost simultaneously selected cell is set at the low level, and the signal SG is set at the high level. The signal DSG of the dummy cell DMC connected to the inverted bit line (BL_) 101 is set at the high level and the dummy word line (DWL) 97 is set at the low level. In this case, the signals SG 2 (110) and DSG 1 (99) are set at the high level, and the word line (WL) 100 and dummy word line (DWL) 97 are set at the low level. When the precharge is ended, the signal PC (92) is set at the low level. By this, the nMOS transistors (NT 11 and NT 12 ) 93 and 94 become the OFF state, and the sensing is started. When the selected cell passes a current, the voltage V BL of the bit line (BL) 100 is lowered. This its not changed if it does not pass a current. On the other hand, since the dummy cell DMC is set so as to pass a current at an intermediate level, the voltage V BL of the inverted bit line (BL_) 101 is slightly lowered. Namely, when assuming that the selected cell passes a current, the voltage V BL of the bit line (BL) 100 is considerably lowered. When the potential difference between the bit line (BL) 100 and the inverted bit line (BL_) 101 becomes around -0.1 V, the signals SAG (115) and VSAL (118) are set to the low level and VSAH (121) is set to the high level. By this, looking the outputs SA and SA_ of the sense amplifier SA f , the voltage SA becomes the low level (0 V) and the voltage SA_ becomes the high level (5 V) due to the operation of the flip-flop-type sense amplifier SA f . Next, the signal Y i (122) is set to the high level. By this, the nMOS transistors (NT 15 and NT 16 ) 123 and 124 become the ON state and the voltages SA and SA_ are read out to the data line (D) 126 and the inverted data line (D_) 125. As explained above, according to the present embodiment, two selective transistors are used in each memory cell array and one selective transistor is made a depletion transistor, so it is possible to adopt a folded bit line system even in a NAND type flash memory. As a result, the layout is easy to set. Also, various noise act in exactly the same way on the bit line (BL) 100 and the inverted bit line (BL_) 101. Therefore, the influence of the noise can be suppressed to the lowest level. Accordingly, it is possible to raise the sensitivity of the sense amplifier and to achieve an enhancement of speed. Further, the cell size can be made smaller than a NOR type and the manufacturing process becomes simple as well. Also, with a 3 V single power source, it is possible to make the cell about 100 ns. Note that in the embodiment, NAND type flash memory was explained as an example, but the present invention may also be applied to NOR type flash memory. As explained above, according to this embodiment, it is possible to adopt a folded bit line system even in a flash memory of other semiconductor nonvolatile memory device. As a result, the layout becomes easy and, further, various noise act in exactly the same way on the first and second bit lines, so the influence of noise can be suppressed to the lowest level. Accordingly, the sensitivity of the sense amplifier can be raised, and the enhancement of speed can be achieved.

Claims: A semiconductor nonvolatile memory device which adopts a differential type sensing system comprising first (100) and second complementary bit lines (101) connected to a differential sense amplifier (119), comprising: first and second memory cell blocks (107, 108) respectively connected to said first and second bit lines through selection gates (111 - 114) each comprising two selection transistors connected in series to selectively connect a memory cell block to its respective bit line, one of the series connected selection transistors associated with each of the blocks being an enhancement type transistor while the other one is a depletion type transistor; characterized in that respective ones of the series-connected selection transistors of the blocks associated with the first and second bit lines are controlled by the same selection signals (110, 127) with those selection transistors of the blocks associated with the first and second bit lines which are of the same type being controlled by different ones of the selection signals. A semiconductor nonvolatile memory device as set forth in claim 1, wherein each said memory cell block is formed as a NOR type. A semiconductor nonvolatile memory device as set forth in claim 1, wherein each said memory cell block is formed as a NAND type.

Inventors: ARAKAWA HIDEKI, ARAKAWA, HIDEKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1994
Main classification: G11C16
IPC codes: G11C16