DC voltage offset compensation

Abstract: The object of the invention comprises a method and a device for compensating the DC offset (dU) of a D/A converter (2) particularly in the base frequency modulator of a mobile phone. The method and the device use an error correction register (5), whose value is changed on the basis of the DC offset, and which is added to each signal sample to be converted for compensating the DC offset. The value of the error correction register (5) is changed in the testing mode so that a preset control value is fed into the D/A converter (2), corresponding to the zero voltage of the output of an ideal D/A converter; the voltage values of the outputs of the differential output pair (2a, 2b) arranged in connection with the D/A converter (2) are compared to verify the polarity of the voltage difference (dU) of the outputs and the polarity, i.e. the sign, of the relative DC offset; and, on the basis of the polarity of the voltage difference (dU), the value of the error correction register (5) is either decreased or increased by one from the preset initial value which is preferably zero.

Description: The present invention relates to a method and apparatus for compensating the DC offset voltage of a D/A converter, in particular for a D/A Converter for a digital radio telephone. In digital radio telephones the modulation of a signal to be transmitted is carried out in the digital part of the modulator, after which the modulated digital signal is converted into an analog signal by a D/A converter. The analogue signal is then coupled to the radio frequency section of the radio telephone for transmission as a radio signal. A problem with D/A converters is that a low and generally slowly varying DC offset occurs in their output, generally resulting from the non-ideal characteristics of the manufactured circuit components, and which is not related to the digital signal to be converted. The DC offset causes undesirable carrier leakage in the transmission signal of the mobile phone which interferes with the transmission of the signal. It is thus desirable that the DC offset of the D/A converter is compensated. In a known method for compensating the DC offset of a D/A converter an error correction register is arranged in connection with the D/A converter, the value of the contents of the error correction register being modified in accordance with the measured DC offset and added to each signal to be converted. By obtaining a value for the error correction register which is opposite in polarity but the same magnitude as the DC offset of the D/A converter, the DC offset can be compensated. A problem with the above-described method for compensating the DC offset is that it does not take into account the variation in DC offset due to temperature changes. This temperature behaviour is neither predictable nor necessarily regular, and in addition, it is different for respective D/A converter component units. Since it is not economically feasible to measure the temperature behaviour of each D/A converter component and to tabulate it in a memory arranged in connection with the D/A converter, the compensation of the DC offset due to temperature has to be carried out in some other way that is economic. IEEE JOURNAL OF SOLID-STATE CIRCUITS, DEC. 1990, USA, VOL. 25, NR. 6, PAGE(S) 1318-1327, ISSN 0018-9200 Tan K-S et al 'Error correction techniques for high-performance differential A/D converters' discloses an A/D converter that adjusts the A/D converters DC offset by controlling the capacitive coupling of a known signal to a top plate of a capacitive array. EP 0 605 883, wich constitutes prior art under Article 54(3) EPC, discloses a DC offset adjuster that compares a signal processed by a D/A converter with a reference signal. In a first aspect the present invention provides a method for compensating for an offset in a signal of an electronic device having a differential pair output port, the method comprising the steps of: inputting a predetermined signal to the electronic device; deriving an error signal indicative of a difference between respective signals of a differential signal output from the differential output port. modifying a compensation value stored in a memory means in accordance with the error signal; and adding said value to a subsequent signal input to the electronic device. and in a second aspect the present invention provides apparatus for compensating for an offset in a signal of an electronic device having a differential pair output port, the apparatus comprising input means for inputting a predetermined signal to the electronic device; detecting means for detecting a difference between respective signals of a differential signal output from the differential output port. modifying means for modifying a compensation value stored in a memory means in accordance with the detected difference; and adding means for adding send value to a subsequent signal input to the electronic device. This has the advantage in that offsets can be compensated for even if they vary, without having to have complex look up tables. The invention enables the updating of compensation values during operation of equipment in which the apparatus is disposed, and take into account thermal drift or other such reasons for non ideal behaviour of the electronic device. In a preferred embodiment, the method can be repeated until the difference passes through a minimum value. This advantageously provides an initialisation of the compensation value during, for example, start up of equipment utilising the invention. Preferably, the method and the apparatus are arranged such that the predetermined signal is input to the electronic device only when the device is not being used for its normal purpose. This means that updating or modification of the compensation value can be performed without interrupting the normal operation of the electronic device. The invention is now described in detail, by way of example only, and with reference to the appended drawings in which: Fig. 1 shows a block diagram of a circuit arrangement for compensating the DC offset of a D/A converter; and Fig. 2 shows a block diagram of the GMSK modulator of a mobile phone with the parts relating to the compensation of the DC offset of the D/A converter shown. The circuit arrangement in Fig. 1 comprises data processing unit 1, D/A converter 2, RF modulator 3, and comparator 4. Data processing unit 1 is preferably a microprocessor-based circuit component comprising error correction register 5 and testing unit 6. Error correction register 5 can optionally be disposed outside of data processing unit 1 and in connection with the D/A converter. Data processing unit 1 and D/A converter 2 are linked together by data bus 1b. D/A converter 2 is a peripheral component of the microprocessor circuit which is generally implemented so that it comprises a number of registers for different purposes. D/A converter 2 is provided with at least one differential output pair 2a, 2b, output signals A +, A-obtained from the output pair being signals of opposite phases to one another but having equal values. Input terminals 4a, 4b of comparator 4 are connected to differential outputs 2a, 2b of D/A converter 2. Output 4c of comparator 4 is, in turn, connected to data processing unit 1. Outputs 2a, 2b of D/A converter 2 are also connected to RF modulator 3. Testing unit 6 is preferably implemented in a programmable way in connection with data processing unit 1. In the circuit arrangement in Fig. 1 a digital signal, which is for example a serial-signal comprising 8-bit words, is fed into data processing unit 1 via input 1a. One or more modulation signals are formed in data processing unit 1, depending on the modulation method used, and these signals are fed via bus 1b into D/A converter 2 in parallel form. Analogue signals A+, A- obtained from the differential output pair 2a, 2b of the D/A converter are fed into RF modulator 3. Signals A+, A- and local oscillator signals are combined in modulator 3 to form a high-frequency RF signal which is sent to the radio path. The apparatus for compensating the DC offset of the D/A converter comprises differential output pair 2a, 2b arranged in connection with D/A converter 2, comparator 4, data processing unit 1, error correction register 5 and testing unit 6. The checking and compensation of the DC offset is carried out whenever there is no signal intended to be sent to the radio path by data processing unit 1 and D/A converter 2. This phase is hereinafter called the testing mode. The compensation of the DC offset is implemented by apparatus in accordance with the invention as shown in Fig. 1 in the following way. Error correction register 5 contains a suitable initial value which is preferably zero. The modulator is switched on. The testing mode is started immediately after switching on, and a control value corresponding to a zero voltage from the output of an ideal D/A converter is fed from testing unit 6 of data processing unit 1 into D/A converter 2 via bus 1b. In this case, after a normal D/A conversion carried out by the D/A converter, each output 2a, 2b of the differential output pair should have a zero voltage, assuming that no DC offset occurs. Differential outputs 2a, 2b are independent of each other, whereby possible DC offsets in these outputs accordingly occur as independent voltage variations. If value UA+ of signal A+ present in output 2a is +0 m V and value UA- of signal A- present in output 2b is + 10 m V, the voltage difference dU = (UA+) - (UA-) = -10 m V between inputs 4a, 4b of the comparator. The polarity of difference dU of the output voltages of outputs 2a, 2b of D/A converter 2, i.e., whether the difference is positive or negative, is determined by comparator 4. In this example, where a negative voltage difference, i.e., dU = -10 m V is observed in the input terminals 4a, 4b, as a result of the comparison carried out by comparator 4, a positive signal is placed on output 4c of the comparator, i.e., the output is raised to a positive constant voltage. Data processing unit 1 examines the state of output 4c of comparator 4, and if it is high, modifies the contents of error correction register 5 by subtracting one from it, whereby the value of error correction register 5 is -1 in this example. The control value of testing unit 6, to which the value of the error correction register updated in connection with the testing phase has been added, is fed into D/A converter 2, and the testing phase begins again. Comparator 4 is again used to check the polarity of difference dU of the output voltages of outputs 2a, 2b of D/A converter 2, i.e., whether the difference is positive or negative, and if it is observed that offset voltage dU of signals A+, A- is still negative, the state of output 4c of comparator 4 is maintained up in the positive constant voltage. Data processing unit 1 is used to check the state of output 4c of comparator 4 and if it is high, the value of the contents of error correction register 5 is modified by subtracting one from it, whereby the value of error correction reg ster 5 is -2 in this example. The above-described testing phases are repeated in the testing mode until the polarity of difference dU of the output voltages of outputs 2a, 2b of D/A converter 2 is changed with respect to the previous testing phase. Consequently, it is observed in the above example that the sign of offset voltage dU of signals A+, A- is changed from negative to positive, whereby also the state of output 4c of comparator 4 is changed from the positive constant voltage to the negative constant voltage, i.e., the output is lowered. The change in state of output 4c of comparator 4 is observed by data processing unit 1 and thus it is known that voltage difference dU as well as the DC offset are as close to zero as possible in this configuration, resulting from the compensation of the value of error correction register 5. The testing mode is now brought to an end. Effectively initialization of the compensation of the DC offset has been carried out and the modulator is ready for normal operation. The testing mode is preferably activated in the above-described manner as soon as the modulator or the device in which it is included, is switched on. It is also desirable to repeat the testing mode at intervals during normal operation, such as between the transmitting times of the actual signals to be transmitted. The testing mode and the compensation of the DC offset is implemented as a single testing phase corresponding to the above-described first testing phase carried out after switching on the modulator. Thus, a control value corresponding to the zero voltage of an ideal D/A converter is fed into D/A converter 2. Comparator 4 is used to verify the polarity of the difference dU between the output voltages of outputs 2a, 2b of D/A converter 2. If the difference is positive, output 4c of comparator 4 is lowered (or remains low) and the value of error correction register 5 is increased by one and, conversely, if the difference is negative, output 4c of comparator 4 is raised (or remains high) and the value of error correction register 5 is decreased by one. The testing mode is ended and the procedure is not continued even though the voltage state of output 4c of comparator 4 is not changed from high to low or vice versa. This testing mode is repeated at suitable, regular intervals such as at intervals of one second or one minute depending on the application and the conditions. The rate of change of the DC offset is considered to be sufficiently low with respect to the repetition of the testing mode and to the repetition interval of the updating of the error correction register, consequently it is not necessary to repeat the testing phases at any more frequent intervals. Fig. 2 shows a GMSK modulator for a mobile phone. This modulator includes signal processor 7 serving as a data processing unit, D/A converter 8 and I/Q base frequency modulator 9 which are all connected in series to one another in the foregoing order. A bit stream such as speech data packed in time division frames is fed into digital signal processor 7 through input connector 7a. Digital signal processor 7 forms the modulation signals for the I and Q branches, from the data fed into it, which are further fed through data bus 7b in parallel form to D/A converter 8. D/A converter 8 contains two pairs of differential outputs 8a, 8b and 8c, 8d. First output pair 8a, 8b gives a first pair of analogue differential output signals Q+, Q- of the Q branch, and second output pair 8c, 8d gives a second pair of analogue differential output signals I+, I- of the I branch. These differential output signals Q+, Q-, I+, I- are fed to I/Q modulator 9 where the signals are converted into high-frequency signals using local signal LO and after this they may be mixed up to a higher frequency into a suitable radio signal (not shown in the figure) and transmitted to the radio path. Testing unit 14 is preferably implemented as a programmable unit within or in connection with signal processor 7. Signal processor 7 is used to check outputs 10c, 11c of comparator 10, 11 and to update error correction registers 12, 13. In outputs 8a, 8b and 8c, 8d of D/A converter 8 there occurs at least occasionally a DC offset which is mainly due to the voltage drift due to changes in temperature, as already discussed. The device includes, in order to compensate the DC offset of the D/A converter, two differential output pairs 8a, 8b and 8c, 8d arranged in connection with D/A converter 8 and, correspondingly, two comparators 10, 11 whose inputs 10a, 10b and 11a, 11b are connected to output pairs 8a, 8b; and 8c, 8d of D/A converter 8, digital signal processor 7 to which output 10c, 11c of the respective comparator 10, 11 is connected, two error correction registers 12, 13 and testing unit 14. Error correction registers 12, 13 and testing unit 14 are preferably in connection with digital signal processor 1. Possible DC offsets of D/A converter 8 are compensated in the following manner: The DC offset of D/A converter 8 is measured when the converter is not used for modulating time division bursts transmitted by the mobile phone. Thus, in the testing mode a preset digital control value, corresponding to the zero voltage of the output of an ideal D/A converter, is fed in parallel form from testing unit 14 to the outputs of D/A converter 8. In this case a zero voltage should occur in differential output pairs 8a, 8b and 8c, 8d of D/A converter 8, i.e., all the outputs should be in the zero potential. Voltage values UQ+, UQ- of the outputs of first output pair 8a, 8b of D/A converter 8 are compared in first comparator 10 and, correspondingly, voltage values UI+, UI- of the outputs of second differential output pair 8c, 8d are compared in second comparator 11. If voltage difference dU1 = (UQ+) - (UQ-) and/or dU2 = (UI+) - (UI-) of the outputs of output pair 8a, 8b and/or 8c, 8d of the D/A converter is positive, output 10c and/or 11c of comparator 10 and/or 11 is lowered, i.e., it is brought to the negative constant voltage which is verified by digital signal processor 7 and the value of the contents of error correction register 12 and/or 13 is increased by one on the basis of this. If voltage difference dU1 and/or dU2 of the outputs of differential output pair 8a, 8b and/or 8c, 8d of the D/A converter is negative, output 10c and/or 11c of comparator 10 and/or 11 is increased, i.e., it is brought to the positive constant voltage which is verified by digital signal processor 8 and the value of the contents of corresponding error correction registers 12 and/or 13 is decreased by one on the basis of this. Thus the value of each error correction register 12 and/or 13 depends on the DC offsets and in particular on the sign of the differences thereof occurring in output pair 8a, 8b and/or 8c, 8d of the D/A converter. The above-described testing phase is then repeated. The control value of testing unit 14, in which the value of error correction register 12 and/or 13 updated in connection with the previous testing phase is added, is fed into D/A converter 8. Comparators 10 and/or 11 are again used to verify the polarity of differences dU1 and/or dU2 of the output voltages of outputs 8a, 8b and/or 8c, 8d of D/A converter 8, i.e., whether the difference is positive or negative, and if observed that one or both of differences dU1 and/or dU2 of the output voltages are still positive, the state of outputs 10c and/or 11c of the corresponding or both comparators 10 and/or 11 is kept low in the negative constant voltage. Signal processor 7 is used to examine the states of outputs 10c and/or 11c of comparators 10 and/or 11, i.e., the state of one or both outputs is low, which results in changing the value of the contents of the corresponding or both error correction registers 12 and/or13 by increasing it by one. The above-described testing phases are repeated in the testing mode until the polarity of difference dU1 and/or dU2 of the output voltages of output pairs 8a, 8b and/or 8c, 8d of D/A converter 8 changes. In this case it is observed according to the above example that the sign of offset voltage dU1 and/or dU2 of signals UQ+, UQ- and/or UI +, UI- is changed from positive to negative, whereby also the state of output 10c and/or 11 c of comparator 10 and/or 11 is changed from a negative signal to a positive signal, i.e., the output is increased and it is in the positive constant voltage. Any change in state of outputs 10c, 11c of both comparators 10, 11 is verified separately by signal processor 7 and, consequently, it is known that offset voltages dU1, dU2 as well as the DC offsets are as close to the zero voltage as possible, due to carrying out the compensations of the values of the corresponding error correction registers 12 and/or 13 in question. The testing mode is brought to an end. The modulator is ready for normal operation. After this the values of error correction register 12 and 13 are added in each signal sample to be converted, and correspondingly in the output signal of the Q and I branches for compensating the DC offset. Signal processor 7 or a corresponding data processing unit preferably includes equipment such as logic unit 16, 17 for monitoring the voltage states of outputs 10c, 11c of each comparator 10, 11 and especially for monitoring a change thereof during the testing mode between two sequential testing phases. The testing mode is ended on the basis of the information provided by logic units 16, 17 when the voltage state of the output of the comparator is changed from positive to negative or vice versa. In this case the value of error correction register 12, 13 is kept unmodified. The testing mode is implemented in the above-described manner in several testing phases and the contents of error correction registers 12, 13 is checked several times in a row as soon as the mobile phone or a corresponding device is switched on. It is desirable to update the contents of error correction registers 12, 13 during the normal use of the mobile phone at suitable intervals such as when D/A converter 8 is free from processing the actual signals to be modulated. In this case the updating of error correction registers 12, 13 can be implemented in only a few or even one testing mode phase, in which a control value corresponding to the zero voltage is written from testing unit 14 to D/A converter 8, and if difference dU1 and/or dU2 of the voltages of output pair 8a, 8b and/or 8c, 8d is positive, the value of error correction register 12 and/or 13 is decreased by one and if difference dU1 and/or dU2 of the voltages is negative, the value of error correction register 12 and/or 13 is increased by one, as previously described. After this the testing mode is ended and no attention is paid to the change in state of outputs 10c, 11c of comparators 10, 11. The same procedure is implemented also in connection with the compensation of the DC offset and the modulator in Fig. 1. Due to the slow rate of change of the DC offset it is possible that only one testing phase need be carried out at each interval. Taking into account the testing mode implemented in connection with normal use of a mobile phone or a corresponding device, it is preferable to further include in the device for compensating the DC offset of the D/A converter equipment 15 (Fig. 2) for detecting time division bursts and/or for locating free time slots, whereby the contents of error correction registers 12, 13 can be updated during the testing mode. Equipment 15 can be placed in connection with digital signal processor 7 and implemented as a unit with programs, utilizing the existing structures. The data processing unit is used to process the digital signals fed into the modulator, to monitor the testing mode and the testing unit in particular, to examine the state of one or more comparators, and to place the value of the contents of one or more error correction registers. The data processing unit can be implemented, as already stated before, as a microcomputer-based device such as a digital signal processor or a logic circuit or a combination thereof. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention. In particular, the present invention may apply to any type of circuit or application in which a DC offset needs compensating.

Claims: A method for compensating for an offset in a signal of an electronic device (2; 8) having a differential pair output port, the method comprising the steps of: inputting a predetermined signal to the electronic device (2;8); deriving an error signal indicative of a difference between respective signals of a differential signal output from the differential output port; modifying a compensation value stored in a memory means (5; 12, 13) in accordance with the error signal; and adding said value to a subsequent signal input to the electronic device (2; 8). A method according to claim 1, further comprising repeating said steps with the subsequent signal being the predetermined signal until said difference passes through a minimum value. A method according to claim 1 wherein the electronic device (2; 8) is a D/A converter. A method according to any preceding claim, wherein the error signal is indicative of the polarity of the difference. A method according to any preceding claim, wherein the predetermined signal has substantially zero magnitude. A method according to claims 4 or 5, wherein the value stored in the memory means (5; 12, 13) is incremented if the said polarity is negative and decremented if the polarity is positive. A method according to any of claims 4 to 6 dependent on claim 2, wherein the passing of the difference through a minimum value is indicated by a change in the polarity of the difference. A method according to any preceding claim, wherein said steps are performed during periods of non-use of the electronic device. Apparatus for compensating for an offset in a signal of an electronic device (2; 8) having a differential pair output port, the apparatus comprising input means (1; 7) for inputting a predetermined signal to the electronic device (2; 8); detecting means (4; 10, 11) for detecting a difference between respective signals of a differential signal output from the differential output port; modifying means for modifying a compensation value stored in a memory means (5; 12, 13) in accordance with the detected difference; and adding means for adding said value to a subsequent signal input to the electronic device (2; 8) Apparatus according to claim 9, wherein the electronic device (2; 8) is a D/A converter. Apparatus according to claim 9 or claim 10, wherein the detecting means (4; 10, 11) is adapted to detect the polarity of the difference. Apparatus according to any of claims 9 to 11, wherein the input means (1; 7) is adapted to input a predetermined signal of substantially zero magnitude to the electronic device (2; 8). Apparatus according to any of claims 11 to 12, wherein the value stored in the memory means (5; 12, 13) is incremented if the said polarity is negative and decremented if the said polarity is positive. Apparatus according to claim 11 or any of claims 12 to 13, dependent on claim 13, wherein the passing of the difference through a minimum value is indicated by a change in the polarity of the difference. Apparatus according to any of claims 9 to 14, wherein the input means (1; 7) inputs a predetermined signal to the electronic device (2; 8) when it is not in use. Apparatus according to claim 15, comprising equipment (15) for detecting free time slots or non use of the electronic device (2; 8) when the value stored in the memory means (5; 12, 13) can be updated.

Inventors: LINTINEN MARKKU, MIKKOLA PEKKA, RANTA JUKKA, LINTINEN, MARKKU, MIKKOLA, PEKKA, RANTA, JUKKA
Applicants: NOKIA MOBILE PHONES LTD, NOKIA MOBILE PHONES LTD.
Application year: 1994
Main classification: H03M1
IPC codes: H03M1, H03C3