A SIGNAL PROCESSING CIRCUIT AND A METHOD OF DELAYING A BINARY PERIODIC INPUT SIGNAL

Abstract: The invention relates to a signal processing circuit for delaying a binary period input signal (S0). Three series-connected delay devices (D1-D3) produce output signals (S1-S3) which are delayed in relation to the input signal (S0). The delay of the delay devices (D1-D3) can be controlled to a very high degree of accuracy, in that the delay devices (D1-D3) include a plurality of mutually identical series-connected delay elements (20A-24A) which are manufactured at one and the same time by common process steps in one and the same semiconductor process. A control means (1) compares in a phase detector (2) the phase of the input signal (S0) with the phase of the output signal (S3) from the last delay device (D3), and on the basis thereof delivers control signals (V0-V4) to the delay devices. These control signals control the delay devices (D1-D3) in a manner such that an equal number of delay elements (20A-24A) will be activated in each of the delay devices (D1-D3), such that the delay devices will have mutually the same delay. The total delay between the input signal (S0) and the last output signal (S3) exceeds one-half but is less than one and a half periods of the input signal (S0) in a first regulating sequence, and the total delay reaches to one period of the input signal (S0) in a second regulating sequence.

Description: A SIGNAL PROCESSING CIRCUIT AND A METHOD OF DELAYING A BINARY PERIODIC INPUT SIGNAL TECHNICAL FIELD The present invention relates to a method of delaying a binary periodic input signal using at least two series-connected semiconductortype delay devices ofvariable delay, anddelay¬ ing the input signal successively in the series-connected delay devices, said delay devices being connected to a control means and each producing a respective output signal. The invention also relates to an arrangement for carrying out the method. BACKGROUND ART Periodic binary data signals are often used as clock signals, in which case very high demands are placed on a well-defined frequency. There is often a reason to multiply the frequency of a clock signal in order to obtain a new clock signal of higher frequency. A clock signal can be frequency multiplied by using delayed signals of an original clock signal and combining the delayed signals in a logic circuit in some suitable manner to provide a clock signal of higher frequency. One problem in this regard is that the delayed signals are not delayed accurately enough. When the delayed signals are used to extract desired signals, the deficiency in delay accuracy is propagated, thereby resulting in error in the multiplied clock signal, for instance in the form of an uneven pulse- pause-ratio. A resume of how delayed clock signals have earlier been obtained and how frequency multiplied circuits have been produced is given below. An article "Unsurpassed Flexibility Heralds Clock Generator" by Dave Bursky on pages 63-66 of the technical magazine Electronic Design, 12 November 1992, describes a circuit for generating clock frequencies. The circuit includes a phase- locked loop which comprises a phase detector, a filter, a voltage controlled oscillator, and a division circuit. The phase detector compares the respective phases of a reference signal and a feedback signal from the voltage controlled oscillator and delivers a control signal to the filter, which in turn delivers a control voltage to the oscillator. There is then produced on the oscillator output a signal which is received and divided by the division circuit, so that the divided signal obtains the same frequency as the reference signal. Thevoltage controlled oscillator is a ring oscillator which includes a plurality of series-connected delay elements of variable delay. Signals are tapped from the delay elements to a programmable matrix selector. The matrix selector can be programmed to provide signals whose frequencies are multiples of the reference signal frequency or signals which are delayed in relation to the reference signal. Patent Application G.B. 2,199,457 A teaches a circuit for doubling the frequency of an incoming binary data signal. The data signal is delayed in a variable delay device. The data signal and the delayed data signal are then combined logically in a circuit which therewith produces an output signal whose frequency is twice that of the input signal. The output signal and the input signal are used to adjust the delay of the delay device so as to obtain a 50/50 pulse-pause-ratio. Patent Application G.B. 2,130,825 A teaches a delay circuit which includes a plurality of series-connected transistors 2 constructed in so-called I L-technique. A phase comparator compares the phase of an input signal with the phase of a delayed input signal. The delay of each transistor is cor¬ rected on the basis of this phase comparison, so as to obtain the desired delay. Patent Specification G.B. 1,561,465 teaches a circuit for changing the frequency of an input signal. The input signal is first frequency-divided in a division circuit and then delayed in a delay circuit which comprises series-connected delay elements having several tappingpoints. The divided signal and the plurality of delayed signals are combined logically in a logic circuit, so as to obtain an output signal of desired frequency. IBM Technical Disclosure Bulletin, Vol. 34, No. 3, August 1991, teaches a circuit for doubling the frequency of an input signal. The input signal is delayed in a delay device whose delay can be adjusted with a control voltage. The input signal and the delayed signal are combined in a logic circuit, so as to obtain a signal whose frequency is twice that of the input signal frequency. This signal and the delayed input signal are converted in a circuit, which converts the pulse-pause-ratio of the signal to voltages. These two voltages are compared in a comparator which produces the control voltage that adjusts the delay of the delay device. JP 61-163715 (A) teaches series-connected delay elements 1 which are used to obtain so-called multi-phase blocks. The delay elements produce delayed signals and eachdelayed signal is combined logically with an inverted delayed signal in a two-input AND-gate. The output signals are then used for multi-phase clocks. Although the aforesaid publications present solutions to the problem of multiplying the frequency of a clock signal and of delaying a clock signal, the problem of generating the delayed signals that are used to extract the multiplied signal with sufficiently high accuracy still remains. DISCLOSURE OF THE INVENTION The object of the present invention is to provide a signal processing circuit for delaying a binaryperiodic input signal to a very high degree of accuracy in the time delay. The circuit includes at least two series-connected delay devices, each of which delivers an output signal which is delayed in relation to the binary input signal. Each of the delay devices includes a plurality of series-connected delay elements. A tapping facility through which the delay device output signal can be taken out is provided downstream of each delay element. The time delay of the delay device can be varied by control¬ ling from which tap the output signal shall be taken out. By also comparing the phase of the binary input signal with the phase of the output signal taken from one of the delay devices, it is possible to adjust the circuit so that the phase difference between the two compared signals will reach a predetermined number of half periods of the input signal, and so that each of the delay devices will obtain mutually the same time delay. All delay elements are produced simultaneous- ly in common process stages in one and the same semiconductor process, and consequently all of the delay elements will have mutually identical delay times. This results in a very high degree of delay accuracy. The resolution of the time delay, by which is meant the ratio between the delay time of one delay element and the delay time of one delay device, can be controlled by integrating differently-sized numbers of delay elements in each delay device. The greater the number of delay elements in the delay devices, the higher the resolution obtained. The signal processing circuit can be integrated on one and the same semiconductor chip and is well-suited for mass produc¬ tion. The construction is digital, which means that the phase detector will be very simple and therewith require only a small amount of space. The accuracy in the delayed signals is increased by the present invention. When the delayed signals are used to produce a multiplied clock signal, the quality of the mul¬ tiplied clock signal will also be enhanced. The invention is characterized by the characteristic features set forth in the accompanying Claims and will be described in more detail with reference to a preferred exemplifying embodiment thereof and alsowith reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simple block schematic illustrating a signal processing circuit which comprises a control device and three delay devices in accordance with the invention. Figure 2 shows the block schematic in Figure 1 in more detail. Figure 3 is a circuit diagram of a delay device included in the Figure 1 illustration. Figure 4 illustrates two clock diagrams for the phase detector illustrated in Figure 2. Figure 5 is a block schematic illustrating the state machine of Figure 2. Figure 6 is a block schematic illustrating an inventive arrangement for multiplying a clock signal, and an associated clock diagram. Figure 7 is a block schematic which also illustrates an arrangement for multiplying a clock signal, and an associated clock diagram. Figure 8 is a block schematic illustrating an arrangement for equalizing the pulse-pause-ratio of a clock signal with an uneven clock signal, and an associated clock diagram. BEST MODES OF CARRYING OUT THE INVENTION Figure 1 illustrates an inventive signal processing circuit and shows how this circuit operates in principle. A binary periodic input signal SO, which can assume the values 0 or 1, as shown in Figure 4, is delayed in three series-connected delay devices Dl, D2 and D3, each of which produces a respec¬ tive output signal SI, S2 and S3. The delay of the delay devices can be varied by applying control signals V0-V4 from a control device 1. The phase of the signal S3 from the third delay device D3 and the phase of the input signal SO are compared in the control device 1. There is then produced on the control outputs U0-U4 of the control device 1 control signals V0-V4, which are used to control the delay of the delay devices so that the output signal S3 from the third delay device D3 relative to the input signal SO will be delayed by one period of the input signal and so that each of the delay devices will have a mutually identical delay time. Thus, the output signals SI, S2 and S3 will be delayed one- third period therebetween. SI is thus delayed one-third of the period time in relation to SO and S2 is delayed two-thirds of the period time, whereas S3 is delayed one whole of the period time. Each of the delay devices Dl, D2 and D3 includes a large number of delay elements 20A-24A, resulting in veryhigh delay accuracy. This is shown and explained in more detail below. It is conceivable to connect a further delay device D5 to the series-connected delay devices D1-D3, as shown inbroken lines in Figure 1. In this case, the phase of the signal SI and the phase of the output signal S5 are conveniently compared in the control device 1. As in the earlier case, the result of this phase comparison is used to control the delay of the delay devices, although in this case so that the signal S5 will be delayed by one period in relation to the signal SI. Alter¬ natively, the signals SO and S3 can be delivered to the control device 1 and the signal S5 used solely as a delay signal. Figure 2 illustrates an embodiment of the signal processing circuit in Figure 1 in more detail. The control device 1 includes a phase detector 2 which receives the signal SO and the signal S3. The phase detector compares the phases of the two signals SO and S3 and delivers a phase signal T2, which is a logic zero when the signal S3 is delayed by more than one period of the input signal and a logic one when the signal S3 is delayed by a time which is shorter than one period of the input signal SO. The logic one or the logic zero is received by a state machine 3, which stores the signal for a number of clock periods, in this case eight clock periods. The state machine 3 then delivers a state signal T3 to a binary-type counter circuit 4 which therewith either counts up or down, depending on the value of the state signal T3. The construc- tion and operation of the state machine will be described in more detail with reference to Figure 5, while the operation of the phase detector will be described in more detail with reference to Figure 4. In turn, the counter circuit 4 delivers to a decoder 5 a counter signal T4 which contains information concerning the content of the circuit 4. The decoder 5 interprets the content of the counter signal T4 and activates one of its several control outputs, referenced U0-U4, these control outputs U0-U4 delivering the respective control sig¬ nals V0-V4. The Figure also shows the delay devices D1-D3. Each of the delay devices D1-D3 is comprised of a plurality of series-connected delay elements 20A-24A and each has control inputs L0-L4. The output signal can be tapped from the circuit after each delay element 20A-24A and passed directly to the input of the next following delay device, or to the phase detector 2 for phase comparison when the output signal is the output from the last delay device D3. The control output U0 of the decoder 5 is connected to the control input L0 of each of the delay devices D1-D3. Cor¬ respondingly, the remaining control outputs U1-U4 of the decoder are connected to the corresponding control inputs LI- L4 of each of the delay devices. The control signals V0-V4 which control the delay of the delay devices are produced on the control outputs U0-U4 of the decoder 5. The decoder 5 thus controls the delay of the delay devices D1-D3 simultaneously and in a manner such that the delay devices will each produce mutually the same delay, because an equally large number of delay elements are activated in each delay device D1-D3. The delay elements 20A-24Anamelyproducemutually the same delay, as will be explained in more detail with reference to Figure 3. The combined delay of all delay devices D1-D3 is equal to one period of the input signal, which is obtained with the aid of the adjustment achieved through the phase detector 2. Figure 3 illustrates inmore detail an exemplifying embodiment of the variable delay device Dl shown in Figure 1. The delay device includes the aforesaid series-connected delay elements 20A-24A, which in turn include series-connected delay buffers 20C-24C and buffer elements 20B-24Bwhich are connectedto the decoder 5 through control inputs L0-L4. The input signal SO can be delayed for different lengths of time, since it passes through different numbers of delay elements 20A-24A. After each delay buffer 20C-24C, the output signal SI can be tapped- off to the output of the delay device Dl via the buffer elements 20B-24B. For instance, the signal SO may pass through the delay buffer 20C and then be tapped-off via the buffer element 2OB. In this case, the signal has the smallest possible delay. The signal SO may also be permitted to pass through delay buffers 20C-24C and then be tapped-off through the buffer element 24B, in which case the signal has the longest possible delay. The time delay of the delay devices is thus stepwise variable. The decoder 5 delivers one of the control signals V0-V4 from a corresponding control output of its control outputs U0-U4 to a corresponding buffer element 20B-24B. For instance, the control signal V2 is delivered from the control output U2 to the buffer element 22B. The decoder thus determines through which buffer element the signal shall be tapped, thereby enabling the buffer element which provides the requisite delay to be activated. Corresponding buffer elements 20B-24B are activated simultaneously in each of the series-connected delay devices D1-D3. The decoder 5 will preferably be constructed so that when a switch is made from one buffer element to another buffer element, the buffer element to be activated will be activated before the buffer element to be deactivated is deactivated. For instance, when a switch is to be made from buffer element 22B to buffer element 23B, the buffer element 23B is activated prior to deactivating the buffer element 22B. This avoids the presence of voltage spikes that would otherwise occur on the outputs of the delay devices D1-D3 when switching between two buffer elements. Both the delay buffers 20C-24C and the buffer elements 20B-24B can each have the form of two series-con¬ nected inverters in C-MOS technique, for instance. In this case, each of the inverters is, in turn, loaded with an inverter so as to obtain a known load for the series-connected inverters. An inverter in C-MOS technique is described inmore detail in the book "Digital Teknik" by P.-E. Danielsson et al, chapter 4, page 85, published by Studentlitteratur 1977. An extremely high degree of accuracy in the time delay is achieved with this type of delay device, because all delay elements are manufactured simultaneously in accordance with the invention in a common process stage in the same semicon¬ ductor process, preferably on one and the same semiconductor chip. This means that the delay elements 20A-24A will obtain mutually identical delay times. It is thereby ensured that the delay devices D1-D3 will delay the input signal by equal magnitudes, since an equal number of delay elements are activated in each delay device. The manner of manufacture of the delay elements is known to the art and the inventive concept includes the use of these delay elements in a method and in a signal processing circuit according to the present invention. When the delay elements are integrated on one and the same chip, the spread between the time delay of respective delay elements 20A-24A will not be greater than some few thou¬ sandths. It has been discovered that the delay produced by the delay elements can differ substantially in the case of different delay elements that have not been produced at one and the same time, due to variations in process parameters such as tempera¬ ture and time, etc. When this is combined with variations in working temperature and operational voltage and also aging of the elements, the delay produced by the delay elements may differ by a factor of three (3) or more when the delay ele¬ ments have beenmanufactured on different occasions or are not integrated in one and the same chip. For the sake of simplicity, only five delay elements 20A-24A are shown in each delay device in Figure 3. In reality, the number will be much greater. For instance, each delay device D1-D3 may contain 128 delay elements. An increase in the number of delay elements will also result in an increase in the resolution of the time delay. In this respect, the word resolution relates to the ratio between the delay time of one delay element and the maximum delay time of a delay device. In practice, the accuracy of the circuit is restricted by the resolution. A delay device in which the delay elements are produced on one and the same chip is commercially available, as made evident in U.S. 5,095,233. A typical delay time of a delay element is 0.1-0.5 ns, although longer and shorter delay times can be achieved. When switching between two delay elements, i.e. either when the number of active delay elements 20A-24A is increased or when the number of active delay elements is decreased, there is a risk that voltage spikes will occur on the output. The output line, however, counteracts this phenomenon because its intrinsic capacity maintains the value on the line when voltage spikes occur. The self-capacitance of the output of the delay device Dl is symbolized in Figure 3 with the capaci¬ tance CI. A corresponding capacitance is found after all delay devices. Propagation of voltage spikes in the circuit can be further prevented by supplementing the self-capacitance of the line with an external capacitance. Since voltage spikes often occur when the counter circuit 4 counts up or down, the effect of voltage spikes can be further counteracted by using a counter circuit which uses a so-called Graycode. When counting up or down, a counter circuit of this kind will only change the content in one of its bits at a time, so that the smallest possible disturbances are propagated. Figure 4 is a clock diagram for the signals SO and S3 and for the signals Tl and T2 of the phase detector 2, all of said signals assuming the values 0 or 1. Also shown in Figure 4 is a time access which shows the time T. The signal SO is used as a binary clock signal of predetermined frequency. The signal S3 is also binary and has the same frequency as the signal SO, but is time-shifted. The phase detector 2 illustrated in Figure 2 is used to regulate the signal S3, so as to delay the signal by one period in relation to the input signal SO. This is achieved by controlling the delay produced by the delay devices D1-D3 by the phase detector 2 via the state machine 3, the counter circuit 4 and the decoder 5. The phase detector 2 has two inputs and one output and includes two series-connectedD flip-flops 41 and 42. Although the modus operandi of the D flip-flop will be well-known to the person skilled in this art, it will nevertheless be described briefly here. The D flip-flop has a clock input, a data input and a data output. It receives a binary clock signal of predetermined frequency on its clock input and a binary signal on its data input. The binary signal on the data input is read-out from the data output of the flip-flop at a positive clock flank, i.e. each time the clock signal changes from a low state to a high state. In the present case, the D flip-flops 41 and 42 receive the binary input signal SO as the clock signal. The phase detector 2 compares the phases of the signals SO and S3. The signal SO is applied to the clock input of both flip- flops, whereas the signal S3 is applied to the data input of the first D flip-flop 41. The data output of the first D flip- flop 41 produces a signal Tl and is connected to the data input of the second flip-flop 42. The second flip-flop 42 produces on its data output a phase signal T2 which is deliv¬ ered to the state machine 3. The upper part of the clock diagram in Figure 4 shows the signal S3 excessively delayed relative to the signal SO, i.e. delayed by more than one period. This delay error is il¬ lustrated by a line referenced Δr. The data output of the D flip-flop 41 reads-out a logic signal Tl = 0 at the positive flank of the input signal SO and at time point τl, this logic signal being received by the data input of the second flip- flop 42. The data output of the second flip-flop 42 reads-out the logic phase signal T2 = 0 at the next positive clock flank at time point τ2. The phase signal T2 from the output of the second flip-flop is delivered to an input of the state machine 3 according to Figure 2. The state machine 3 produces a state signal T3 which controls or steers the counter circuit 4 at uniform intervals, where the time between each state signal T3 to the counter circuit 4 is sufficiently great to enable the adjustment, either in the form of an increase or a decrease in the number of active delay elements, to be fed into the phase detector 2. In the case of the illustrated embodiment, this time interval corresponds to eight periods of the input signal SO. When the counter circuit 4 receives the state signal T3 = 0, the content of the counter circuit 4 is decreased and a counter signal T4 is delivered to the decoder 5, wherewith the delay in each of the delay devices D1-D3 is decreased by deac¬ tivating the last of the active delay elements and activating the preceding delay element. The lower part of the clock diagram illustrates the situation when the signal S3 has not been delayed sufficiently, i.e. has been delayed by less than one period in relation to the binary input signal SO. This delay error is indicated by the line ΔT. The data input of the first D flip-flop 41 receives a high signal S3 at time point rl when its clock input becomes high, wherein the high signal Tl = 1 appears on the output of the first D flip-flop 41. This signal is propagated to the data output of the second flip-flop 42 at the next positive clock flank of the signal SO at time point τ2. The counter circuit 4 then receives the state signal T3 = 1 via the state machine 3, informing the circuit to count-up, whereupon the counter circuit 4 produces the counter signal T4 and the delay time is increased in each of the delay devices D1-D3, by activating a further delay element of said delay elements 20A-24A and deactivating the earlier activated delay element, in accor¬ dance with the above descriptionmade with reference to Figure 3. In this way, it is possible to set the delay time of the delay devices D1-D3 so that the combined delay between the signals SO and S3 will reach one period of the input signal SO and so that each of the delay devices D1-D3 will have the same delay. It should be noted that since the construction is digital, a delay which equals exactly one period of the input signal is not often achieved and that the delay will deviate slightly from the desired delay. This deviation is due to the aforemen¬ tioned resolution of the delay devices. As a result of the limited resolution, the circuit may swing between two delay values of which one is slightly smaller than one period of the input signal SO and the other is slightly larger than one period. It is also conceivable to provide the phase detector with solely one D flip-flop. Aphase detector of this construction, however, will present a metastability problem, i.e. a certain period of time would lapse from the moment at which the clock signal switched from a low to a high value until the data output had a stable output signal. This problem is not manifested in the embodiment illustrated in Figure 2 which in- eludes a furtherD flip-flop, and consequentlythis embodiment is preferred. Figure 2 illustrates the state machine 3, the counter circuit 4 and the decoder 5. The decoder 5 includes an input and the control outputs U0-U4 and forms part of the control device 1. The signal T4 from the counter circuit 4 is received on the input of the decoder 5 and activates one of the decoder control outputs, of which only one at a time is high, and produces the corresponding control signal, be one of the control signals V0-V4. The decoder control unit that is chosen from the control units U0-U4 is determined by the current value of the counter circuit 4. Each of the decoder control outputs U0-U4 is connected to one of the control inputs L0-L4 of one of the buffer elements 20B-24B of each of the delay devices. For instance, the control output U0 is connected to the control input L0 of the delay device Dl and to a cor¬ responding control input of each of the remaining delay devices D2-D3. It lies within the scope of the present invention to provide the signal processing circuit with more or fewer series- connected delay devices D1-D3 than three, although the circuit will include at least two series-connected delay devices. The number of control outputs on the decoder 5 shall equal the number of control inputs on the delay devices D1-D3. If the number of delay devices is increased, then the number of branches from each of the decoder control outputs U0-U4 will also be increased, so that each of the decoder control outputs is connected to a corresponding control input L0-L4 on each of the delay devices. The decoder 5 thus controls the delays of the delay devices simultaneously and in a manner such as to activate the same number of delay elements 20A-24A in each of the delay devices D1-D3. The decoder 5 will preferably be of the kind which when a switch is made between two control signals on the control outputs, the value will be retained on the control output to be deactivated until the new control output has been ac¬ tivated. This time lapse is in the order of parts of a gate delay. This is achieved when the decoder switching time t for high to low control outputs is shorter than the decoder switching time t for low to high control outputs, i.e. when t , is < t „,,. This results in less disturbance when swit- pHL pLH ching between signals and therewith further counteracts the aforesaid problem of voltage spikes. Before it is possible to commence phase adjustment towards a full period delay as described with reference to Figure 4, it is necessary to set the delay of the delay devices so that the combined delaywill exceed one-half period but be shorter than one and a half periods, therewith tuningthe signal processing circuit to its regulating or control range. Otherwise the circuit will make the wrong adjustments. For instance, if the delay is less than one-half period the circuit may erroneously decrease the delay so that the phase difference between the signals SO and S3 moves towards zero. Correspondingly, if the delay exceeds one and a half periods the circuit may increase the delay so that the phase difference between the signals SO and S3 reaches two periods. The state machine is used to avoid this problem. Figure 5 illustrates one method of implementing the state machine 3. In the case of the illustrated embo- diment, the state machine includes a circuit 50 which is a combinatory network of logic gates, and a memory unit 51. The circuit 50 receives at determined input time points the phase signal T2, a resetting signal RESET and a control signal T8, and produces the state signal T3 and a control signal T7. The state signal T3 is fed into the counter circuit 4 at regular intervals, wherein the time between each signal input is such as to enable the control adjustment to propagate in the signal processing circuit. In the illustrated case, this time interval corresponds to eight periods of the input signal SO. The control signal T7 is fed back to the input of the circuit 50 and at the next input time point is received as the control signal T8. When the inventive signal processing circuit is to be started-up, the counter circuit 4 is set to zero, whereupon the delay devices D1-D3 will present the smallest possible delay. This means that the signals SO and S3 will be in phase, apart from a given smallest delay in the delay devices D1-D3, which causes the signal S3 to be delayed slightly in relation to the signal SO. The phase detector 2 will then produce the phase signal T2 = 0 which carries information to decrease the delay of the delay devices. Since the signal processing circuit is not in its regulating or adjustment range at this moment in time, the phase signal T2 = 0 will be erroneous. This is overcome because the state machine 3 receives the reset signal RESET in a first regulating or adjusting sequence during the start-up process. The circuit 50 builds its output signals T3, T7 as a function of its input signals T2, T8 and RESET and is constructed so that the circuit 50 will deliver a high state signal T3 * = 1 to the counter circuit 4 in the first regulating sequence. The counter circuit will therewith count-up and deliver a count signal T4 to the decoder 5 in accordancewith Figure 2 , wherewith the decoder 5 produces one of the control signals V0-V4 which increases the delay of the delay devices D1-D3. This continues until the phase detector 2 produces the phase signal T2 = 1 for the first time after starting-up the signal processing circuit. The signal processing circuit 3 has then increased the delay between the signal SO and the signal S3 to slightly more than one-half period, wherein the circuit is located in the regulating range and a second regulating sequence commences. The counter circuit 4 will preferably count-up through a further number of steps in order to ensure that the signal processing circuit is truly in its regulating range, i.e. to ensure that the delay between the input signal SO and the signal S3 truly exceeds one-half period but is shorter than one and a half periods. In the second regulating sequence, the state signal T3 is delivered to the counter circuit 4 at regular intervals, similar to the first regulating sequence. The counter circuit 4 therewith delivers a counter signal T4 to the decoder 5 and the decoder 5, in turn, produces one of the control signals V0-V4 which changes the delay of the delay devices so that the delay between the input signal SO and the signal S3 cor¬ responds to one period of the input signal, as described with reference to Figure 4. The values of the state signal T3 can be stored in the circuit 50 and used to calculate the values of the next arriving signal. For instance, the earlier values of the state signal T3 can be used to prevent overco pensation of the state machine 3. If three mutually sequential values of the state signal T3 from the state machine are considered, for instance a first value T3 = 1 and a second value T3 = 0, the state machine may be constructed so that a new high value T3 = 1 will not be produced as a third value. The earlier values of the state signal T3 are thus used to determine the value of the next arriving signal and to prevent overcompensation of the signal processing circuit when the phase signal T2 constantly alternates between the value 0 and the value 1. This results in greater accuracy in the event of external disturbances and interferences and therewith in more rapid adjustment of the signal processing circuit. The stored values of the state signal T3 may also be used by the state machine 3 to calculate the mean value of eight mutually sequential state signals T3 and then determine whether the state signal T3 shall be read¬ out as the value 1 or has the value 0 with the aid of a majority decision. Naturally, the number of state signals T3 used to form the mean value may be other than eight. According to a further modified embodiment of the invention, stored values of the state signal T3 can be used and processed in some way other than to form the mean value, whereafter the state signal T3 is delivered to the counter circuit 4. By way of an alternative embodiment, there can be used a state machine which sets the delay of the delay devices so that the delay between the input signal SO and the signal S3 in the second regulating sequence will reach a predetermined number of half periods of the input signal SO. For instance, the delay between the input signal SO and the signal S3 in the second regulating sequence may reach one and a half periods of the input signal SO or two periods of the input signal SO. In this case, the state machine 3 is constructed so that the signal processing circuit will switchto the second regulating sequence when the requisite delay has been obtained, i.e. when the delay lies within a regulating interval that has its centre at the predetermined number of half periods of the input signal SO, this regulating interval reaching to less than one period of the input signal SO. For instance, when using a signal processing circuit in which the delay between the input signal SO and the signal S3 shall reach one and a half periods in the second regulating se¬ quence, the signal processing circuit switches to the second regulating sequence when the delay between the input signal SO and the signal S3 exceeds one period but is less than two periods of the input signal SO, i.e. when the delay lies within one regulating interval which has its centre at one and one-half period of the input signal SO, this regulating interval reaching to less than one period of the input signal SO. In this case, the state machine is constructed to switch to the second regulating sequence after first having received a phase signal T2 = 1 and thereafter a phase signal T2 = 0, i.e. two mutually sequential switches of the phase signal T2. By switching of the phase signal T2 is meant that the phase signal changes its value, either from the value T2 = 1 to the value T2 = 0 or from the value T2 = 0 to the value T2 = 1. Each switch-over of the phase signal T2 corresponds to an increase in the delay between the input signal SO and the signal S3 by one-half period of the input signal SO. Correspondingly, the signal processing circuit switches to the second regulating sequence when the delay between the input signal SO and the signal S3 is intended to reach two periods when the state machine 3 has received three mutually sequential changes of the phase signal T2 switches in the first regulating sequence. If the delay between the input signal SO and the signal S3 is intended to attain a duration of one-half period in the second regulating sequence, the signal processing circuit will switch to the second regulating sequence immediately, without the phase signal T2 changing in the first regulating sequence. According to one alternative embodiment, the first regulating sequence is omitted and the state machine 3 loads a predeter¬ mined counter value into the counter circuit 4, when the circuit receives the reset signal RESET upon starting-up the signal processing circuit. The signal processing circuit will then pass directly to the second regulating sequence, after the requisite counter value has been loaded into the counter circuit 4. This counter value is chosen so that the delay between the input signal SO and the output signal S3 from the delay device D3 attains a delay value which deviates from a predetermined number of half periods of the input signal SO by less than one-half period of said input signal SO. Alter¬ natively, when starting-up the signal processing circuit, the counter circuit 4 can be loaded with a fixed counter value. for instance a counter value which corresponds to a delay of one-half period of the input signal 50, where in the first regulating sequence is not used. The state machine can also be implemented by several other methods. For instance, a state machine which has the proper¬ ties desired can be achieved with the aid of so-called HDL (Hardware Description Language) . In this case, the inputs and outputs of the state machine are defined and how the circuit shall behave in HDL, for instance verilog code. The verilog code is then translated to corresponding networks of logic gates with the aid of a program, for instance synopsis. This method will be well known to those skilled in this art; see for instance the handbook "HDLCompiler forVerilog, Reference Manual, Version 2.0" published by Synopsis, March 1991. Figure 6 illustrates how the delay signals S0-S2 can be used to multiply the frequency of the input signal SO. The three signals S0-S2 are combined logically in a logic gate 60, for instance a modulo-2-gate followed by an inverter, although other logic gates may be used as will be readily understood by the person skilled in this art. A frequency multiplied signal S7 will then appear on the output of the logic gate 60. Figure 6 also illustrates a clock diagram which shows how a multiplied clock signal is obtained. In the illustrated case, the logic gate output signal S7 has a frequency which is three times greater than the frequency of the original input signal SI. When the modulo-2-gate receives an odd number of high input signals (S0-S2) , the gate will produce a high signal on its output. The output signal is then inverted in an inverter on the output of the modulo-2-gate. In the case of this embodiment, it can be said generally that all odd factors n 1, 3, 5, 7, and so on, can be used as multiplying factors. The number of requisite delay devices D1-D3 will then be equal to n. For instance, three delay devices are needed to multiply the frequency of the input signal SI by three, and seven delay devices are required to multiply the frequency of the input signal SI by seven. Figure 7 illustrates an alternative method of utilizing the delayed signals to multiply a clock frequency. This method is able to produce clock signals that are multiplied by a factor m which is equal to a whole number half, i.e. 1/2, 1, 3/2, 2, 5/2, and so on. In this case, there is used a logic gate 70 which is of different design to the logic gate 60 used in the Figure 6 embodiment. The logic gate 70 can be implemented by activating a toggling D flip-flop 71 after each tap. By toggling D flip-flop is meant a D flip-flop which is provided with an inverter 72 between its data input and its data output. Figure 7 illustrates an example which includes the four series-connected delay devices D1-D4. The input signal SO is delivered to the first delay device Dl and then delayed incrementally in the series-connected delay devices D1-D4, which produce signals S1-S4. Each of the signals S0-S3 is then delivered to one of the toggling D flip-flops 71. The output signals of the D flip-flop 71 are then delivered to the EXOR- gate 73, wherewith the desired signal S6 is obtained on the output of the EXOR-gate 73. An EXOR-gate will produce a high output signal when one, and only one, of its input signals is high. The advantage afforded by this method is that the introduction of the toggling D flip-flops obviates the dependency on the negative clock flank of the input signal SO and therewith also the dependency on the pulse-pause-ratio of the input signal SO. This is achieved because each positive flank of the signals S0-S3 forms alternately a positive or a negative clock flank on the output signal S6, as illustrated in the as¬ sociated clock diagram. This latter implementation can also be used to smooth out the pulse-pause-ratio of a signal withwhich said ratio is uneven. In this case, there are used two series-connected delay devices Dl and D2 which produce the signals SI and S2 respec- tively, according to Figure 8. An input signal S8 which has an uneven pulse-pause-ratio is shown in the clock diagram. The output signal S6 from the EXOR-gate 73 has a 50/50 pulse- pause-ratio. Thus, the embodiment illustrated in Figure 6 enables a clock signal to be readily multiplied. In order to ensure a uniform pulse-pause-ratio, the multiplied clock signal may advan¬ tageously be applied to a circuit according to the Figure 8 embodiment. This circuit is a variant of the circuit il¬ lustrated in Figure 7, but has only two delay devices Dl and D2. The embodiment illustrated in Figure 6 can also be used to achieve a given phase-shift for a clock signal, for instance a phase shift of 90 degrees. According to a further variant, the delayed clock signals can be used to obtain several phase- shifted clock signals, so-called multi-phase clocks. Other multiplying factors than thosementioned above can be obtained with the aid of an external frequency divider. For instance, a clock signal can be first multiplied by two and then frequency-divided externally by three to obtain a multi- plication factor of 2/3. The embodiments illustrated in Figures 6, 7 and 8 utilize clock signals that have been obtained with the aid of the signal processing circuit according to the present invention. The quality of the multiplied clock signals is enhanced when practicing the invention, because the accuracy of the delayed clock signals has been increased. It will be understood that the invention is not restricted to the aforedescribed and illustrated exemplifying embodiments thereof and that modifications can be made within the scope of the following Claims.

Claims: CLAIMS 1. A method of delaying a binary periodic input signal (SO) in a digital signal processing circuit of the kind comprising delay devices (D1-D3) and a control means (1), wherein at least two of the delay devices (D1-D3) are connected in series and are of the semiconductor type having a variable delay, and in which method the input signal (SO) is delayed successively in the series-connected delay devices (D1-D3), said delay devices (D1-D3) being connected to the control means (1) and each delivering a delayed output signal (S1-S3) , charac¬ terized in that the method comprises the following steps: - each of the delay devices (D1-D3) is produced by connecting in series a plurality of delay elements (20A-24A) all of which are manufactured at one and the same time by a common process step in one and the same semiconductor process, so that the delay elements (20A-24A) will have mutually the same delay time; the phase of the binary periodic input signal (SO) is compared with the phase of the output signal (S3) of an indicated delay device (D3) , said phase comparison being carried out in a phase detector (2) in the control means (1) ; - control signals (V0-V4) are generated in the control means (1) in correspondence with the phase comparison; - the control signals (V0-V4) are delivered from the control outputs (U0-U4) of the control means (1) to each of the series-connected delay devices (D1-D3) ; - in a second regulating sequence, the control signals (V0- V4) from the control outputs (U0-U4) of the control means (1) activate a number of delay elements (20A-24A) such that the delay between the input signal (SO) and the output signal (S3) from the indicated delay device (D3) will reach a predeter¬ mined number of half periods of the input signal (SO) ; - the control signals (V0-V4) activate an equal number of delay elements (20A-24A) in each of the series-connected delay devices (D1-D3) . 2. A method according to Claim 1, characterized in that the second regulating sequence is preceded by a first regulating sequence in which the control signals (V0-V4) from the control outputs (U0-U4) of the control means (1) activate a number of delay elements (20A-24A) such that the delay between the input signal (SO) and the output signal (S3) from the indicated delay device (D3) will reach a delay value which differs from the predetermined number of half periods of the input signal (SO) by less than one-half period of the input signal (SO) . 3. A method according to Claim 2, in which the control means (1) includes a state machine (3) , a counter circuit (4) and a decoder (5) , characterized in that the control signals (V0-V4) in the first regulating sequence are generated by the fol¬ lowing steps: - the counter circuit (4) is set to zero; - - the state machine (3) receives a resetting signal (RESET) ; - the phase detector (2) delivers to the state machine (3) a phase signal (T2) which is contingent on the phase comparison and which can take each of a first value (T2=l) and a second value (T2=0) and the value of which changes in dependence on the delay of the output signal (S3) from the indicated delay device (D3) ; - the state machine (3) delivers to the counter circuit (4) a state signal (T3) which can take each of a first value (T3=l) and a second value (T3=0) in dependence on the number of changes of the phase signal (T2) ; the counter signal (4) delivers to the decoder (5) a counter signal (T4) corresponding to the value of the state signal (T3) ; - the decoder (5) decodes the counter signal (T4) and delivers the control signals (V0-V4) corresponding to the counter signal (T4) to the control outputs (U0-U4) of the control means (1) ; - the control signals (V0-V4) ccunt-up the delay of the delay devices (D1-D3) ; - the state machine (3) is readjusted so as to terminate the first regulating sequence when the delay between the input signal (SO) and the output signal (S3) from the indicated delay device (D3) reaches said delay value. 4. Amethod according to Claim 2, in which the control means (1) includes a state machine (3) , a counter circuit (4) and a decoder (5) , characterized in that in the first regulating sequence the control signals (V0-V4) activate the delay elements (20A-24A) by the following steps: - the state machine (3) receives a rest signal (RESET) ; - the state machine (3) delivers to the counter circuit (4) a state signal (T3) corresponding to the reset signal (RESET) , which loads the counter circuit with a predetermined counter value; - the counter circuit (4) delivers to the decoder (5) a counter signal (T4) which is dependent on the predetermined counter value; the decoder (5) decodes the counter signal (T4) and delivers the control signals (V0-V4) corresponding to the counter signal (T4) , via the outputs of the control means (l) ; - the control signals (V0-V4) activate delay elements (20A- 24A) in each of the delay devices (D1-D3) , wherein the number of delay elements activated is dependent on the predetermined counter value; - the state machine (3) is readjusted so that the first regulating sequence is terminated when the state machine (3) receives a phase signal (T2) from the phase detector (2) subsequent to the delay elements (20A-24A) being activated in dependence on the predetermined counter value. 5. A method according to Claim 1, 2, 3 or 4, in which the control means (1) includes a state machine (3) , a counter circuit (4) and a decoder (5) , characterized in that the control signals (V0-V4) are generated in the second regulating sequence by the following steps: - the phase detector (2) delivers to the state machine (3) a phase signal (T2) which is dependent on the phase comparison and which can take a first value (T2=l) and a second value (T2=0) , wherein the phase signal (T2) takes its first value (T2=l) when the output signal (S3) from the indicated delay device (D3) is delayed by less than the predetermined number of half periods of the input signal (SO) , and wherein said phase signal (T2) takes its second value (T2-0) when the output signal (S3) from the indicated delay device (D3) is delayed by more than the predetermined number of half periods of the input signal (SO) ; - the state machine (3) delivers to the counter circuit (4) a state signal (T3) which can take a first value (T3=l) and a secondvalue (T3=0) , said state signal (T3) being generated in dependence on the value of the phase signal (T2) , wherein the content of the counter circuit (4) is increased when the state signal (T3) takes its first value (T3=l) and the content of said counter circuit (4) is decreased when the state signal (T3) takes its second value (T3=0) ; - the counter circuit (4) delivers to the decoder (5) a counter signal (T4) which corresponds to the content of the counter circuit; the decoder (5) decodes the counter signal (T4) and delivers the control signals (V0-V4) corresponding to the counter signal (T4) , via the outputs of the control means (1) . 6. A method according to Claim 3 or 5, characterized in that a number of the state signal values are stored in the state machine (3) ; in that the state machine (3) generates the first state signal value (T3=l) or the second state signal value (T3=0) depending on the values of the stored signals; and in that the generated value is delivered to the counter circuit (4). 7. A method according to any one of Claims 1-6, charac¬ terized in that a change in the delay of the delay devices (D1-D3) includes the following steps: - the control signals (V0-V4) activate at a first predeter- mined time point one delay element (20A-24A) in each of the delay devices (D1-D3) in dependence on the phase comparison, said delay element (20A-24A) determining the delay of the delay devices; - the control signals (V0-V4) activate a new delay element (20A-24A) in each of the delay devices (D1-D3) at a next following predetermined time point, wherein the first activated delay element (20A-24A) is deactivated subsequent to activation of the later delay element (20A-24A) . 8. A method according to Claim 3, 5, 6 or 7, characterized in that the phase detector (2) delivers the phase signal (T2) to the state machine (3) at time points which correspond to each positive flank of the binary periodic input signal (SO) . 9. A method according to any one of Claims 1-8, charac¬ terized in that the control means (1) controls the delay devices (D1-D3) so that the number of activated delay elements (20A-24A) in each of the delay devices (D1-D3) will either decrease or increase by one. 10. A digital signal processing circuit comprising delay devices (D1-D3) and a control means (1) for delaying a binary periodic input signal (SO) , wherein at least two of the delay devices (D1-D3) are connected in series and are of the semiconductor type with variable delay and are connected to the control means (1), each of said delay devices (D1-D3) having an input and an output, characterized in that - each of the delay devices (D1-D3) includes a plurality of series-connected delay elements (20A-24A) ; - the delay elements (20A-24A) in all delay devices (D1-D3) are manufactured at one and the same time by common process steps in one and the same semiconductor process, so that the delay elements (20A-24A) will have mutually the same delay time; - the control means (1) has a first input connected to the input of one of the delay devices (Dl) on which it receives an input signal (SO) to said one delay device, a second input connected to the output of an indicated delay device (D3) , on which second input the control means (1) receives an output signal (S3) from the indicated delay device (D3) , and control outputs (U0-U4) connected to control inputs (L0-L4) of each of the delay devices (D1-D3) ; - the control means (1) includes a phase detector (2) which is intended to make a phase comparison between the signals (SO,S3) arriving on both inputs of the control means (1) ; - the control means (1) is intended on the basis of the phase comparison to deliver control signals (V0-V4) which in a second regulating sequence activate delay elements (20A-24A) in a number such that the delay between the input signal (SO) and the output signal (S3) from the indicated delay device (D3) will reach a predetermined number of half periods of the input signal (SO) ; and in that the control means (1) is intended to deliver the control signals (V0-V4) in a manner such as to activate an equal number of delay elements (20A-24A) in each of the series-connected delay devices (D1-D3) . 11. A digital signal processing circuit according to Claim 10, characterized in that - on the basis of the phase comparison, the control means (1) is intended to deliver on its control outputs (U0-U4) the control signals (V0-V4) which, in a first regulating sequence preceding the second regulating sequence, activate a number of delay elements (20A-24A) such that the delay between the input signal (SO) and the output signal (S3) from the in¬ dicated delay device (D3) will reach a delay value that dif- fers from the predetermined number of half periods of the input signal (SO) by less than one-half period of the input signal (SO) . 12. A signal processing circuit according to Claim 11, in which the control means (1) includes a state machine (3), a counter circuit (4) and a decoder (5) , each of which has at least one input and at least one output, characterized in that in the first regulating sequence - the counter circuit is set to zero; - the state machine (3) is intended to receive a reset signal (RESET) ; - the output of the phase detector (2) is connected to the input of the state machine (3) , said phase detector (2) being intended to deliver from its output to the state machine (3) a phase signal (T2) which is dependent on the phase comparison and which can take a first value (T2=l) and a second value (T2=0) , and the phase signal (T2) changes value in dependence on the delay of the output signal (S3) from the indicated delay device (D3) ; the output of the state machine (3) is connected to the input of the counter circuit (4) , said state machine (3) being intended to deliver to the counter circuit (4) a state signal (T3) which can take each of a first value (T3=l) and a second value (T3=0) in dependence on the number of changes of the phase signal (T2) ; - the output of the counter circuit (4) is connected to the input of the decoder (5) , said counter circuit (4) being intended to deliver to the decoder (5) a counter signal (T4) which is dependent on the value of the state signal (T3) ; - the outputs of the decoder (5) are connected to the control outputs (U0-U4) of the control means (1), said decoder (5) being intended to decode the counter signal (T4) and deliver the corresponding control signals (V0-V4) which count-up the delay of the delay devices (D1-D3) ; and in that - the state machine (3) is intended to be readjusted so that the first regulating sequence will be terminated when the delay between the input signal (SO) and the output signal (S3) fromthe indicated delay device (D3) reaches said delay value. 13. A signal processing circuit according to Claim 11, in which the control means (1) includes a state machine (3), a counter circuit (4) and a decoder (5) , each of which has at least one input and at least one output, characterized in that in the first regulating sequence - the state machine (3) is intended to receive a reset signal (RESET) ; - the state machine output is connected to the counter circuit input, wherein said state machine (3) is intended to deliver to the counter circuit (4) a state signal (T3) which corresponds to the reset signal (RESET) and loads the counter circuit with a predetermined counter value; - the counter circuit output is connected to the decoder input, wherein the counter circuit (4) is intended to deliver to the decoder (5) the counter signal (T4) which is dependent on the predetermined counter value; and in that - the decoder outputs are connected to the control outputs (U0-U4) of the control means (1), wherein the decoder (5) is intended to decode the counter signal (T4) and deliver the control signals (V0-V4) which correspondto the counter signal (T4) , wherein the decoder (5) is also intended to deliver control signals (V0-V4) in a manner such as to activate delay elements (20A-24A) in each of the delay devices (D1-D3) in numbers which depend on the predetermined counter value, and wherein the state machine (3) is intended to be readjusted so that the first regulating sequence is terminated when the state machine (3) receives a phase signal (T2) from the phase detector (2) subsequent tohaving activated the delay elements (20A-24A) in dependence on said predetermined counter value. 14. A signal processing circuit according to Claim 10, 11, 12 or 13, in which the control means (1) includes a state machine (3) , a counter circuit (4) and a decoder (5) , each of which has at least one input and at least one output, characterized in that in the second regulating sequence, the phase detector output is connected to the state machine input, said phase detector being intended to deliver from its output to the state machine (3) a phase signal (T2) which is dependent on the phase comparison and which can take a first value (T2=l) and a second value (T2=0) , wherein the phase detector (2) is intended to deliver its first value (T2=l) when the output signal (S3) from the indicated delay device (D3) is delayed in relation to the input signal (SO) by less than the predeter¬ mined number of half periods of the input signal (SO) , and the phase detector (2) is intended to deliver its second value (T2=0) when the output signal (S3) from the indicated delay device (Dl) is delayed in relation to the input signal (SO) by more than the predetermined number of half periods of the input signal (SO) ; in that the outputs of the state machine (3) is connected to the input of the counter circuits (4), wherein the state machine (3) is intended to deliver to the counter circuit (4) a state signal (T3) in dependence on the value of the phase signal (T2) , wherein said state signal (T3) can take a first value (T3=l) and a second value (T3=0) , wherein the content of the counter circuit (4) is increased when the state signal (T3) takes its first value (T3=l) and is decreased when the state signal (T3) takes its second value (T3=0) ; in that the output of the counter circuit (4) is connected to the input of the decoder (5) , wherein the counter circuit (4) is intended to deliver to the decoder (5) a counter signal (T4) containing information relating to the content of the counter circuit (4) ; in that the inputs of the decoder (5) are connected to the control outputs (U0-U4) of the control means (1) , wherein the decoder (5) is intended to decode the counter signal (T4) and to deliver from its outputs control signals (V0-V4) which correspond to the counter signal (T4). 15. A signal processing circuit according to Claim 12 or 14, characterized in that the state machine (3) is constructed to store a plurality of state signals (T3) ; in that the state machine (3) is adapted to generate the first value (T3=l) or the second value (T3=0) of the state signal in dependence on the values of the stored signals; and in that the state machine (3) is adapted to deliver the generated value to the counter circuit (4) . 16. A signal processing circuit according to any one of Claims 10-15, characterized in that when a change occurs in the delay of the delay devices (D1-D3) , the control means (1) functions to deliver the control signals (V0-V4) in a manner such as to activate at a first predetermined time point one delay element (20A-24A) in each of the delay devices (D1-D3) in dependence on the phase comparison, said delay element (20A-24A) determining the delay of the delay devices; in that the control means (1) is adapted to deliver the control signals (V0-V4) in a manner such as to activate a new delay element (20A-24A) in each of the delay devices (D1-D3) at a next following predetermined time point, said control means (1) being adapted to deactivate the first activated delay element (20A-24A) subsequent to said control means (1) having activated the later delay element (20A-24A) . 17. A signal processing circuit according to Claim 12, 14, 15 or 16, characterized in that the phase detector (2) is adapted to deliver the phase signal (T2) to the state machine (3) at time points which correspond to each positive flank of the binary periodic input signal (SO) . 18. A signal processing circuit according to any one of Claims 10-17, characterized in that a capacitor (CI) is arranged at the output of each of the delay devices (D1-D3) . 19. A signal processing circuit according to any one of Claims 10-18, characterized in that the control means (1) is adapted to control the delay devices (D1-D3) in a manner such that the number of delay elements (20A-24A) activated in each of the delay devices (D1-D3) is either decreased or increased by one.

Inventors: LIEDBERG NILS PER AKE, LIEDBERG, NILS, PER, AKE
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON
Application year: 1994
Main classification: H03K5
IPC codes: H03K5