Driver for flat panel display with two power supply circuits

Abstract: A driver suitable for a panel display system of the type having at least two substrates (12,13) each having electrodes (14,15) on the surface thereof arranged closely so that the electrodes intersect and face mutually, a plurality of intersections formed between the electrodes constructing cells (10), a plurality of the cells being arranged in a matrix configuration to form a display panel (1), each of the cells (10) having a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell and also having capabilities of discharge and light emission, and the electrodes comprising n scan electrodes (15) which are independent of each other. The driver comprises: a plurality of driver circuits provided between a first power supply line (FVH) and a second power supply line (FLG), and individually connected to the scan electrodes (15); a first power supply circuit (72) for supplying a first electric power to the first and the second power supply lines (FVH, FLG) the first electric power being used to write display data; and a second power supply circuit (73) for supplying a second electric power to the first and the second power supply lines (FVH, FLG), the second electric power being used to cause discharges based on the display data.

Description: This invention relates to the field of a driver of a flat panel display, more particularly, to a driver for a flat panel display by which high speed line sequential scanning can be realised with a low power dissipation and a low cost. In recent years, there has been a greater demand for a flat matrix display such as a plasma display (PDP), a liquid crystal display (LCD), or an electroluminescent (EL) display because of its thin appearance rather than a CRT. Requests for, especially, a color display are frequent these days. Flat displays including a plasma display and an electroluminescent (EL) display are thin. Moreover, the flat displays also permit large display screens. The application range and production scale of the flat displays are therefore rapidly expanding. In general, a flat display utilises charges accumulated between electrodes and causes a discharge to emit light for display. For better understanding of the general principle of such displays, the structure and operation of, for example, a plasma display will be briefly described. Well-known conventional plasma displays (AC type PDP) are a dual-electrode type that uses two electrodes for selective discharge (addressing discharge) and sustaining discharge and a triple-electrode type that uses three electrodes for addressing discharge. In a plasma display (PDP) for a color display, ultraviolet rays resulting from discharges are used to excite phosphors formed in discharge cells. The phosphors are susceptible to the impact of ions or positive charges induced synchronously with discharge. The above dual-electrode type has a structure that the phosphors are directly hit by ions. This structure may reduce the service lives of phosphors. To avoid such deterioration, the color plasma display usually employs the triple-electrode structure based on surface discharge. The triple-electrode type uses an arrangement in which a third electrode is formed on the substrate on which first and second electrodes for sustaining discharge are arranged or an arrangement in which a third electrode is formed on another substrate opposed to the one on which first and second electrodes are arranged. In the arrangement in which three electrodes are formed on the same substrate, the third electrode may be placed on or under the two electrodes for sustaining discharge. Furthermore, visible light emitted from phosphors may be transmitted or reflected by the phosphors for observation. The foregoing plasma displays of different types have the same principle. Mention will therefore be made of a flat display in which first and second electrodes for sustaining discharge are formed on a first substrate and a third electrode is formed on a second substrate opposed to the first substrate, by presenting examples thereof. That is, Fig. 3 is a schematic plan view showing a prior art configuration of a flat panel display. Fig. 3 is a schematic plan view showing a configuration of the aforesaid triple-electrode type plasma display (PDP). Fig. 4 is a schematic sectional view of one of discharge cells 10 formed in the plasma display shown in Fig. 3. As apparent from Figs. 3 and 4, the plasma display comprises two glass substrates 12 and 13. The first substrate 13 has first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15. The first electrodes 14 and second electrodes 15 serve as sustaining electrodes, lie in parallel with one another, and are shielded with a dielectric layer 18. A coating 21 made of magnesium oxide (MgO) is formed as a protective coat over the discharge surface that is the dielectric layer 18. On the surface of the second substrate 12 opposed to the first glass substrate 13, electrodes 16 acting as third electrodes or address electrodes are formed to intersect the sustaining electrodes 14 and 15. On the address electrodes 16, phosphors 19 each having one of red, green, and blue light-emitting characteristics are placed in discharge spaces 20 each defined by walls 17 formed on the surface of the second substrate 12 on which the address electrodes are arranged. Discharge cells 10 in the plasma display are separated from one another by partitions (walls). In a plasma display of the aforesaid example, the first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15 are lying in parallel with one another and are paired. The second electrodes (Y electrodes) 15 are driven separately by respective separate Y electrode driver circuits 41, ..., 4n, while the first electrodes (X electrodes) 14 form a common electrode which is driven by a single driver circuit 5. Also, address electrodes 16-1, ..., 16-m are orthogonally disposed to both of the X electrodes 14 and the Y electrodes 15, and are connected to a suitable address driver circuit 6. In such a prior art flat panel display, each of the address electrodes 16 is separately connected to address driver 6, which applies address pulses to the respective address electrode during the address discharge period. The Y electrodes 15 are connected one by one to an Y-electrode scan driver 41 ~ 4n. The scan driver is connected to an Y electrode common driver 3. For addressing discharge, pulses are generated by the scan driver 41 ~ 4n. For sustaining discharge, pulses are generated by the Y electrode common driver 3, and then applied to the Y electrodes 15 via the Y-electrode scan driver 41 ~ 4n. The X electrodes 14 are connected in common with respect to all display lines on a panel of the flat display. An X-electrode common driver 5 generates a write pulse and a sustaining pulse, and applies these pulses to the X electrodes 14 concurrently. These drivers are controlled by a control circuit (not shown). The control circuit is controlled with a synchronizing signal which is fed by an external unit. The X-electrode common driver 5 and Y-electrode common driver 3 in this example are connected to a suitable driver control unit (not shown). The X-electrodes 14 and Y electrodes 15 are driven all together by reversing polarities of applied voltages alternately. Thus, the aforesaid sustaining discharge is executed. As mentioned above, the display panel 1 in the prior art flat panel display has m and n lines of the sustain discharge cell portions 10 arranged in horizontal and vertical directions respectively in matrix form, wherein Y side scanning driver circuit 41 drives the Y electrodes which are connected to m number of the sustain discharge cell portions 10, disposed at the top of the lines arranged in the vertical direction, and also arranged in the horizontal direction, and similarly, each of Y side scanning driver circuits 42-4n separately drives a corresponding scanning display line of the Y electrodes. On the other hand, the X side driver circuit 5 is arranged in parallel with all of the Y electrodes, and it comprises a common electrode so that all of the X electrodes are simultaneously driven by a single X electrode driver circuit 5. The method to drive the prior art flat panel display mentioned above is now described with referencing Fig. 5 and 6. That is, one frame of the display period S is divided into a scan address period S-1 and a sustain discharge period S-2 and thus the display operation is carried out by operating both periods, sequentially. And in the scan address period, a scan signal is provided from the Y electrode scan driver circuit 41 to the Y electrode 15-1, and a signal which corresponds to a display data of the first line formed by Y electrode 15-1, is provided, from the address driver 6 to the address electrodes 16-1 ~ 16-m using an address pulse AP, so that the cell portions 10 discharge temporally to enable a predetermined value of charge (wall charge) so that the cell can show a memory function deposited in this cell portion. Similarly, data to be displayed, is written into a defined cell portion by scanning the lines sequentially one by one, in order of Y side electrode-scanning driver 42, 43, ..., 4n up to the Y electrodes 15-2, ..., 15-n. When the scan address period S-1 is completed, the sustain discharge period S-2 starts whereby a defined voltage Ysus is simultaneously applied between the electrodes of the cell portion 10, which is formed at intersecting portions of the Y electrode 15-1, ..., 15-n and the X electrode 14, then the polarity of the voltage is inverted and a voltage Xsus is applied to the cell portion 10 by a similar operation, so that an alternating voltage is applied between the cell portions 10. Then, only the cell portions 10 which have the predetermined value of charges (wall charge) during the scan address period carry out a luminous discharge repeatedly for a defined number of times. Also, in the prior art flat panel display, for all of the cell portions 10, an initial operating period may be provided to eliminate the charges which is generated by the Y side driver circuits 3 and the X side common driver within the cell portions which conducted a luminous discharging operation in the previous sustain discharge period. In this case, during the initial operating period, a method for initializing display data of each display line sequentially, one by one, may be used, and a batch eliminating method may also be used. Also, an arrangement of the scan driver and sustain discharge circuit of the prior art flat panel display, is shown in Fig. 7, wherein n driver circuits 41, ..., 4n are provided, each of which has a push-pull type driver circuit 51 for driving the respective one of Y electrodes 15-1, ..., 15n, which constitute a display line. At same time, one end 0 of the push-pull type driver circuit 51, is connected to Vs, as a first voltage source via a suitable switch means SW1 (05), and the other end P is connected to GND, as a second voltage source, via a suitable switch means SW2 (O6). On the other hand, at the output of the push pull type driver circuit 51, there are provided diodes DU1, ..., Dun having a function to raise the voltage of the display line, diodes DD1, ..., DDn having a function to lower the voltage of the display line, and the driver 5 commonly driving the X electrodes comprises an output stage having a transistor TR3 and TR4. The method for driving the prior art flat panel display constituted as described above generates a sustain discharge wave in the Y electrode via diodes DU1, ... , DUn and DD1, ..., DDn by the Y side common driver circuit 3, whereby the output of the push-pull type driver circuit 51 is kept in high impedance state during the scan address period in which scan pulses are applied to the Y electrode by the push-pull type driver circuit 51 within the driver circuit for scanning the Y electrode side scan. Also, a sustain voltage wave is generated in the X electrode by X electrode side driver circuit 5. Next, another arrangement example of the prior art flat panel display will described with referencing Fig 8. That is, the flat panel display is generally called a floating system, wherein a power recovery circuit 60 is further provided to the driver circuit 3, for scanning. That is, as can be understandable from the block diagram shown in Fig. 8, in the prior art flat panel display, each of the driver circuit 41, ..., 4n for the Y electrode side scanning, includes a switch means 52 which has a transistor TR5 connected to a defined writing voltage Vsc via a resistor and a diode D030 connected in parallel with the transistor TR5, and a power recovery circuit 60 is also added. Also, the X electrode driver circuit 5 has an output stage known in the prior art, and a power recovery circuit 60 connected to said output stage at same time. Also, a connection between each of driver circuits 41, ..., 4n for the Y electrode side scanning and the power recovery circuit 60, is made wherein each of the driver circuits 41, ..., 4n for the Y electrode side scanning is arranged to be open-drain circuit. The power recovery circuit 60 has a display panel which is a capacitive load, so that it has an external capability of recovering charge to be transferred in the panel, when a voltage needed to a gas discharge in the panel, and it has a circuit construction to serially resonate by a panel capacitor Cp (C) and a coil 61. Operation of the flat panel display shown in Fig. 8, will now be explained, wherein a fall of the scanning pulse occurs, when the transistor TR5 in the push-pull type driver circuit 51, is turned on, and a rise of the pulse may be taken by a method in which a charge current flows from a resistor R1 to the panel capacitor, or from the sustain discharge circuit provided in Y side common electrode driver 3 to a diode D01, when the transistor TR5 is turned off. Meanwhile, the sustain discharge wave is generated by the driver circuit 5 for X electrode side and the common driver circuit for the X electrode side through the diode D01 or transistor TR5 consisted of FET. However, in the prior art flat panel display, as shown in Fig. 7, the withstand voltage of the driver circuit for scanning the Y electrode side is determined by approximately 200 volt which is the maximum voltage of the sustain discharge wave, but not approximately eighty (80) volt which is the voltage (Vsc) at scanning, therefore it is required to use a LSI having a large withstand voltage, so that the circuit arrangement become complicated as well as the manufacturing cost becomes very high. Also, in the flat panel display shown in Fig. 8, it is required to raise or fall the voltage only by a resistor. Therefore, the resistor is required to have a large value which tends to increase the time until a defined voltage is established, thus it can not be applicable to a high speed line scanning. Therefore, the resistor should have a small value, but when the value is decreased, a needless current flows through it so that the ON voltage of the driver circuit for scanning is required to be high, that is, the capacity thereof is required to be large. Also, if the resistor is not used, a method could be available wherein the potential is raised from the driver circuit common to the Y electrode. In that case, a problem has existed that the current loss became high since the scanning driver circuit was used both in the scan address period and the sustain discharge period. Another example of a prior art configuration of a flat panel display is provided by EP-A-0 549 275 which is an earlier application of the present applicant, and discloses the features of the preamble of claim 1. Therefore, it is an object of this invention to provide a flat panel display that improves the defects of the prior art, has a lower withstand voltage, can perform a fast line scanning and regenerate power and has a low power dissipation with a low cost. According to a first aspect of the present invention, there is provided a driver suitable for a panel display system of the type having at least two substrates each having electrodes on the surface thereof arranged closely so that said electrodes intersect and face mutually, a plurality of intersections formed between said electrodes constructing cells, a plurality of said cells being arranged in a matrix configuration to form a display panel, each of said cells having a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell and also having capabilities of discharge and light emission, said electrodes comprising n scan electrodes which are independent of each other; wherein said driver comprises a plurality of driver circuits provided between a first power supply line and a second power supply line, and individually connected to the scan electrodes; characterised by a first power supply circuit for supplying a first defined voltage to the first and the second power supply lines during a scan address period, said first defined voltage being used to write display data; and a second power supply circuit for supplying a second defined voltage to the first and the second power supply lines during a sustain discharge period, said second defined voltage being used to cause discharges based on the display data. In an embodiment of the invention, during the period wherein each of the Y electrodes, consisting of the display line, writes display data in the cell portion, a signal voltage for scanning is applied for example, during a scan address period and a sustain discharge voltage is applied during the period for discharging the cell portion to which the display data is written for a defined time, for example, the sustain discharge voltage is applied thereto during the sustain discharge period. Accordingly, since a different voltage is applied to a display line of Y electrodes during a different display operation period, the circuit construction is simplified and the driver can be used while completely eliminating the effect of the voltage, applied thereto during a different period, even though a different voltage is applied to the same electrode during a different period, and thus the withstand voltage of the respective circuit can be lowered since the voltage used will not become higher than the defined voltage. Also, the driver circuit for driving the Y electrodes is provided with two power supply lines (FVH and FLG), and two systems of power recovery circuit 60 connected to two power supply lines connecting the respective driver circuits so that a part of the power generated in the circuitry of the flat panel display can be used to make a power saving type flat panel display. Reference is made, by way of example, to the accompanying drawings in which: Fig.1 is a block diagram showing a circuit constitution of an embodiment of a flat-panel display according to this invention, Fig.2 is a view showing a detailed example of the driving voltage waveform when operating the drive unit of the flat-panel display shown in Fig.1, Fig. 3 is a plan view describing a constitution of the prior art flat-panel display, Fig. 4 is a sectional view describing a constitutional example of the cell portion used in the prior art flat-panel display, Fig. 5 is a view describing an example of the driving method of the prior art flat-panel display, Fig. 6 is a view showing a detailed example of the driving voltage wave form when operating the prior art flat-panel display, Fig. 7 is a block diagram of an example of the drive unit of the prior art flat-panel display,and Fig. 8 is a block diagram of another example of the drive unit of the prior art flat-panel display. An embodiment of a flat panel display in accordance with this invention will now be described in detail with reference to the drawings. Figure 1 is a block diagram showing an embodiment of an arrangement of the flat panel display in accordance with this invention, wherein at least two substrates (Fig. 4) on which electrodes 14, 15 are disposed, are adjacently positioned in such manner that the electrodes are facing each other; a suitable fluorescent substance (fig. 4) is, for example, inserted between the substrates 12 and 13; a plurality of orthogonal portions formed by the electrodes, orthogonally intersecting each other, form cell portions 10, each of which constitutes a pixel; and the cell portions 10 are arranged in a matrix form to form a display panel and have a memory function which is able to store a predetermined amount of charges, and a luminous discharge function; and wherein, in order to select cell portions for performing a write operation for writing suitable display data into cells, the sequence of display operation comprises: a period for scanning to select a line from plurality of display lines in line sequence method and writing the display data into the cell portions, for example, an address period (Fig. 2); and a period for illuminating the cell portions 10 into which the display data, is written, multiple times by discharging the cell portions, for example, a sustain discharge period; and wherein push-pull driver circuits 55 are provided in parallel, each of which having, for example, two transistors TR6 and TR7. The push-pull driver 55 is connected to each of two power supply lines FVH and FLG, connected, for example, to a driver circuit for driving one of the electrodes forming a plurality of display lines to be scanned, for example, a Y electrode 15; and is also provided with a power supply means 70 which applies a defined voltage, that is a voltage of a first power supply line, to at least one of the power supply lines, respectively connected to the driver circuits; and a switch means 80 which leaks a defined voltage applied to the respective power supply lines connecting the driver circuits. It is desirable that the display panel 1 in the flat display panel in accordance with this invention, comprises three electrodes including an X electrode 14, Y electrode 15 and address electrode 16 for driving and displaying an image, and for the display, it is desirable that display panel 1 is either the plasma display (PDP) or the electroluminescence (EL) type. That is, the driver of the flat-panel display embodying this invention is provided with a power supply circuit means 70 for supplying or cutting off the voltage (OFF voltage Vsc, when scanning operation is carried out) of the first voltage supply means, such as a scanning voltage, to the power supply line common to Y electrode scanning driver circuits 101, 102, ..., 10n and the Y electrode scanning driver circuits having the push-pull circuit 55, providing an ON voltage a switch means 80 for leaking current caused by the voltage used for scanning and applied to the respective power line of the scan driver circuits 101, 102, ..., 10n to force the voltage of the power supply line to be zero voltage or ground. Furthermore, it is desirable that the power supply circuit means 70 is provided with a first power supply means 71 which applies a defined voltage, e.g., Vsc to at least one of two power supply lines FVH and FLG, e.g., FVH1, ..., FVHn (the first power supply line) connecting the driver circuit during the scan address period (S-1) wherein the display data is written into the cell portion, and a second power supply means 90 which applies a defined voltage to the power supply lines FVH1, ..., FVHn during the sustain discharge period (S-2) wherein the cell portion, into which the display data is written, is allowed to discharge for a defined period. Furthermore, it is desirable that the first power supply means 71 is provided with a first voltage generating means 72 for generating a high voltage supply, e.g., Vsc, a second voltage generating means 73 for generating a low voltage supply, e.g., ground level of voltage, wherein the first voltage generating means 72 is connected to one connecting wire, e.g., FVH (the first power supply line) of two power supply lines (FVH, FLG), and the second voltage generating means 73 is connected to one connecting wire, e.g., FLG (the second power supply line) of the other of two power supply lines (FVH, FLG). It is desirable that the above mentioned voltage generating means 72, 73 used with this invention are respectively provided with switch means 74, 75, which supply a defined voltage to any one (e.g. FVH1, ..., FVHn) of two power supply lines (FVHl ~ FVHn and FLG - FLGn) connected to the driver circuits, in response to a predetermined control signal supplied externally to the switching means. It is also desirable that the switch means 74, 75 include MOSFETs (TR8, TR9) respectively. It is also desirable that a diode D04 or a resistor R, or both are provided between the first voltage generating means 72 of the first power supply means 71 and one, e.g., FVH (the first power supply line) of two power supply lines connected to the driver circuit, used with the driver of the flat panel display of this invention. On the other hand, in the driver of the flat panel display of this embodiment, the second power supply means 90, in the power supply circuit 70, used with the driver of the flat panel display of this invention, has voltage generating means 91, 92 which generate two different potentials, respectively, and which are respectively connected to the power supply line and the display line (FVH, FLG) connecting the driver circuit. In this embodiment, the first voltage generating means 91 for supplying GND potential is connected to the power supply line FVH, for example, one of two power supply lines connecting the driver circuit, and the second voltage generating means 92, generating high voltage Vs, is connected to the other power supply line FLG (the second power supply line) of the two power supply lines connecting the driver circuit. Furthermore, each of the voltage generating means 91, 92 comprising the second power circuit 90 in accordance with this embodiment, is provided with switching means 93, 94, respectively and is arranged to supply a defined voltage to any one (e.g., FVH or FLG) of the power supply lines connecting the driver circuit by a defined control signal supplied externally. Furthermore, the switch means 93, 94 are provided with MOSFETs (TR11, TR12) respectively. Note that diodes D021, D022 may be connected in parallel to the MOSFETs (TR11, TR12) which constitute the switching means 93, 94, provided in the voltage generating means 91, 92 in the second power means 90 described above. On the other hand, it is desirable that diodes D02, D03 are connected in parallel to the transistors TR6, TR7 of the push-pull type driver circuit 55, used for the scanning driver circuit 101 of the Y electrode side. Also, the power supply lines connected to each of the driver circuits of the Y electrode side used with this invention have two power supply lines (FVH, FLG) between which the push-pull type of driver circuit 55 is connected in parallel. It should be noted that the other electrode, i.e., X electrode is a common electrode. Also, the above mentioned leak current control circuit 80 used with this embodiment may have a switch 81 which is constituted by, for example, a MOSFET (TR10), and which is connected to the power supply line (FVH) to which the first voltage generating means 72 is connected. Next, it is desirable that, in the flat panel display according the invention, a power recovery circuit 60 is connected to each of the power supply lines (FVH, FLG) which constitute two power supply lines connecting the driver circuit. It is desirable that the power recovery circuit 60 is constituted by a resonant circuit which includes capacitors provided by the display panel 1, and coils 62, 63 connected through diodes, e.g., D02 and D03, respectively. In this embodiment inductance values of each of the coils 62 and 63 in the resonant circuit 60 having the panel capacitors and the coils connected through diodes,are set at respective values which are different from each other. That is, the power recovery circuit 60 has two systems of L-C resonant circuit with diodes and MOSFETs which are connected to the resonant circuit. And the power recovery circuit 60 is able to clamp the voltage from a peak voltage generated during the resonance to a defined voltage (Vs or GND), whereby part of the power is stored in a capacitor described hereunder to be used during the next scanning period. The above mentioned second power supply circuit 90 has a switch function for supplying a current during the sustain discharge period wherein an illumination for display is repeated. Note that the detailed circuit configuration of the power recovery circuit 60 is not specifically limited. Therefore any recovery circuit known in the prior art may be used, so that the recovery circuit formed by diodes D013, D014, D015, D016, D017, D018, D019, D020, and MOSFET (TR13, TR14) other than coil 62, 63, and further a capacitor C2, arranged in the configuration as shown in Fig. 1 can be used. Each of these diodes used for the power recovery circuit 60 has a function for eliminating parasitic inductance components generated within a circuit in relation to the coil 62, 63. Note that the driver circuit used for the prior art flat-panel display shown in Fig. 8 may be used for the common driver circuit of the X electrode side. Also, the first voltage generating means 91 in the second power supply circuit 90 may be eliminated when the switch means 80 is used in the drive unit of the flat panel display. In another embodiment of the present invention, a suitable resistor is provided between the leakage current control switch 80 and one of the two power source lines connected to the driver circuit, for example, FVH, so as to dull a rising pulse wave from of the scanning pulses. As an alternate embodiment in accordance with this invention, a suitable driving operation is performed on the assumption of the constitution mentioned above, however, the essential constitution of the driving method for a flat-panel display comprises; a push-pull type driver circuit comprising two transistors provided for respective electrodes forming an electrode pair of the electrodes for discharging, which form the cell, and a first power supply means for supplying a defined voltage to each of the electrodes during a period wherein display data is written into the cell portion, and a second power supply means for supplying a defined voltage to each of the electrodes during a period wherein the cell to which the display data is written discharges for a defined time, and a leakage current control switch means for leaking the defined voltage applied to each of the drivers. The driving method comprises the steps of operating the first power supply means to apply a defined voltage to the electrodes before writing display data to the cell portions; disenabling the operation of the first power supply means to enable the leakage current control switch means so that a voltage difference between the power supply lines of the electrode is eliminated, immediately before completing the period wherein the display data is written into the cell portion; and operating the second power supply means to apply an alternating voltage to the electrode during the period wherein the cell portions discharge for a defined time. Also, an alternate embodiment of the driving method of the flat-panel display in accordance with this invention may be provided wherein the voltage difference of both ends of the push-pull type driver circuit 101 during the period when the cell portions discharge for a defined time, that is a the sustain discharge period S-2, is kept at zero to carry out a display process. Furthermore, diodes D02 and D03 are connected in parallel to the transistors TR2 and TR7, respectively, of the push-pull type driver circuit 101, and thereby the sustain discharge voltage during the sustain discharge period S-2 may be applied from the second power means 90 to the display panel through only the diodes D02 and D03. An example of the driving method of the driver of the flat panel display will now be described with reference to Fig. 2. Note that the address electrode is eliminated in Fig. 2. In the driving method of the driver in the prior art, scanning pulses are supplied to the Y electrode side for selecting each of the Y electrodes in a line sequential manner one by one, and Vsc is output to one line as the scan voltage and the other line is grounded during that time, whereby the voltage Vsc is applied between the lines for scanning. In this method, in contrast to the prior art scanning method, a zero voltage is applied to each of the electrodes to be scanned as an OFF voltage for scanning. The reason for adapting such a method, is that, in the flat panel display, both of the voltage wave Vsc (approximately 80 volts) for scanning to be used during the scan address period S-1 wherein a display data is written into the cell, and the sustain discharge voltage wave (e.g. approximately 200 volts) used during sustain discharge period S-2 wherein the cell portion to which the display data is written is discharged for a defined period, are applied to two power supply lines FVH and FLG which are connected to the driver circuit for driving the respective Y electrode, i.e., scanning electrode. Therefore, if the voltage used during the scan address period remains on the power supply lines FVH and FLG, the sustain discharge voltage used during the sustain discharge period, is added to that voltage, so that a high voltage such as 280 volts will be applied to the electrode that requires the withstand voltage to be raised. Therefore, in this method, a novel technical feature is employed wherein each of the power supply lines connected to a driver circuit for driving the scanning electrode mentioned above is commonly used in the scan address period S-1 and in the sustain discharge voltage S-2. And in order to avoid the problem for the withstand voltage, the voltage applied to power supply lines during a specified period is eliminated once to thereby change voltage of the power source line, to 0 volt, and then a defined voltage, which is to be used during the other operation period, is newly applied thereto. That is, immediately before the Y electrode 15 enters in the scan address period S-1 as shown in Fig. 2, the MOSFET transistor TR6, which comprises the scan driver circuit 101 of the Y electrode is set to an ON condition. And at the same time, the MOSFET transistor TR8, which constitutes the first voltage generating means 72 in the second power supply means 71 is set to an ON condition. Also, the MOSFET transistor TR9 is turned ON, simultaneously. During this period, the MOSFET transistor A which constitutes the common driver 5 for the X electrodes, is set to an ON condition, and thus the voltage between power supply lines FVL and FLG is connected to the driver circuit for driving the Y electrode 15, and simultaneously the voltage Vs is applied to the X electrode. As a result, each of the Y electrodes (15-1, ..., 15-n) is charged up to the voltage Vsc through a rapid charging period (T1), and holds a defined voltage Vsc substantially to the end of the scan address period S-1. On the other hand, each of the Y electrodes (15-1, ..., 15-n) is charged up to the voltage Vsc, and the first transistor TR7 of the pull (PULL) side, which is connected to one of the power supply lines (FLG1), connected to driver circuit 101, is turned ON, for driving the first line of Y electrode (15-1), and the transistor TR6 of the push (PUSH) side is turned to an OFF state, whereby the Y electrode is grounded. And at the time t1, an address output, which corresponds to the display data which is related to the power supply line FVH connected to the driver circuit for driving the Y electrode 15-1, and corresponds to the Y electrode 15-1, is applied to the address driver 6 to write the data. In the write operation of the data, the cell portion 10 connected to the Y electrode selected by the address data, discharges to produce a defined charge in the cell portion 10, and afterwards the cell portion 10 which discharges ceases the discharge, due to the charge (wall charge) of the cell 10 itself. Note that during that period, the transistor TR6 of the push (PUSH) side in the driver circuit 101 for driving each of the Y electrodes 15-2, ..., 15-n, i.e., the other electrodes, is set to an ON state. Such a scanning is performed for each of the Y electrodes 15-2, ..., 15-n, and at time t2 immediately before the end of the scan address period S-1, a MOSFET transistor TR8 constituting the first voltage generating means, is set to an OFF condition, and at time t3 after a defined period of time has elapsed, a MOSFET transistor TR10 of the leakage current control switch means 80 is set to an ON condition. In this state, the MOSFET transistor TR9 constituting the second voltage generating means 73, is turned ON, so that at the time T4 a high voltage, i.e., Vsc, which charges the power supply lines FVH and FLG connected to the driver circuit for driving the Y electrode, is applied via the MOSFET transistor TR10 to ground, so that the voltage between the power supply line FVH and FLG becomes zero. Note that the MOSFET transistor TR9 constituting the second voltage generating means 73 is turned OFF at the time T4. At the same time, the MOSFET transistor A constituting the common driver 5 of the X electrode is set to an OFF condition at the time T4, whereby the scan address period S-1 ends. That is, the potential of the X electrode is set at zero; at the same time, the voltage of all Y electrodes is set at zero volts via the diode D02 of the scan driver 101 for scanning, and set at zero volts at the point between the power supply lines FVH and FLG and thus the scan period is completed. Then, the voltage Vs is applied to the X electrode so that the discharge will not extend in the vertical direction. Next, during the sustain discharge period S-2, the discharged cell portion 10 during the address period mentioned above still holds the charge (wall charge) in the cell portion 10 to be displayed, so that an alternate voltage is applied only to the cell portion wherein the charge (wall charge) remains for repeating the discharge to enable display. Note that if a sustained discharge is to be performed, the same alternating voltage is applied to all Y electrodes at the same time. At first, during the initial sustain discharge period, the defined voltage Vs is applied to the Y electrode, and at the time T5 the transistor B in the X electrode side is turned ON so that X electrode holds zero voltage. Then, at the time T6, the transistor TR14 provided in the power recovery circuit 60, is turned to ON, so that part of the power stored in a capacitor C2 charges the power supply line FLG to raise the potential of one FLG of the power supply lines connected to the driver circuit for driving the Y electrode. If the charge on the capacitor C2 is sufficient, the voltage of the power supply line FLG connected to the driver circuit for driving the Y electrode is increased up to the defined voltage Vs, but generally it is not possible for the voltage to be increased up to Vs. At time T7 the transistor TR14 is turned OFF, and at the same time, the MOSFET (TR12), which is the switch means 94 provided in the second voltage generating means 92 which is provided in the second power supply 90, is turned ON to raise the voltage Vs of the power supply line FLG. Of course, if the power recovery circuit 60 is not used, the voltage of the power supply line FLG is raised up to the defined voltage Vs by the second voltage generating means 92 provided in the second power supply 90. The voltage mentioned above is applied to the cell portion of the display panel via the diode D03. At the time T8, the second voltage generating means 92 provided in the second power supply 90 is turned OFF, and at same time the transistor B in the driver circuit 5 of the X electrode enters an OFF condition. Next, at the time T9, the transistor TR13 provided in the power recovery circuit 60 is turned ON, and part of the voltage Vs charging the line connection FVH charges the capacitor 2 to store the charge, which is used for discharging operation of the Y electrode, in the next step. The voltage of the power supply line FVH is rapidly decreased by the scanning, and at the time T10 the transistor TR13 is turned OFF and simultaneously the MOSFET (TR11), which is the switch means 93 provided in the first voltage generating means 91 which is provided in the second power supply 90, is turned ON to drop the voltage of the wiring connection FVH completely to zero volts. With this operation, the first sustain discharge operation of the Y electrode is completed, and the sustain discharge operation of the X electrode is then performed. On the X electrode side, at the time T11, the MOSFET transistor (TR11) is in an ON condition so that the potential of the X electrode is raised, and the time T12, the MOSFET transistor C is turned OFF, and simultaneously the transistor A is turned ON so that the potential of the X electrode is raised to the defined voltage Vs. During this period, the voltage on the Y electrode side of the cell portion is kept at zero volts since the ground potential voltage is supplied through the diode D02 and D03 to the electrode. Next, at the time T13, both MOSFET transistors, TR11 and A are simultaneously turned OFF, but at the time T14 both the transistors D and B are turned ON, so that the voltage of the X electrode falls to zero volts and part of the charge stored in the cell portion 10 charges the capacitor C3 to conclude the first sustain discharge operation of the X electrode side. Then, the discharge operations on the Y and X electrode sides are alternately repeated for a defined number of times so as to illuminate the defined cell portion 10 of the display panel with a defined brightness. Note that the brightness level at the cell portion 10 is decided by the given number of times of the application of the alternating voltage. Furthermore, referring to the operation of the power recovery circuit 60 in the above embodiment, all Y electrodes are charged to Vs by the external voltage supply Vp set to a defined potential, for example to an intermediate voltage between the voltage Vs and GND through the series LC resonant path of the transistor TR14, diode D016, coil 63, diode D03 of the serial resonant LC circuit, and the transistor TR11 is turned ON approximately at the peak voltage of the LC resonant circuit to apply the voltage Vs. At this moment, the cell portion wherein more than a certain level of the wall charge remains, produces the sustained discharge since the sum of an applied voltage Vs and the quantity of the residual wall charge exceeds the discharge starting voltage of the rare gas. After ceasing the discharge by moving the wall charge itself, the Y electrode is grounded, then the charge Cp stored in the display panel is transferred to the external power supply Vp. Then, all of the Y electrodes discharge from the display panel capacitor Cp to ground via the series resonant path of the diode D02, coil 62, diode 15, and transistor TR13, but part of the charge is stored in the capacitor C2 for further use in the next sustain discharge operation, and at approximately the peak of the LC resonant voltage, the transistor TR11 is set to an on state, whereby the potential of the Y electrode is kept at ground level which terminates the generation of the sustain discharge wave. Similarly, the sustain discharge wave is produced at the next cycle, and by repeating this operation, a sequence of the sustain discharge periods is formed. When the display operation mentioned above is completed, the wall charges in all of the cell portions 10 are eliminated by an initialization operation to perform the next frame operation. The drive unit of the flat panel display in accordance with this embodiment employs the technical architecture as described above whereby the withstand voltage in the scanning side driver circuit can be restrained to a low level. That is, the withstand voltage of the drive unit of the flat panel display in accordance with this embodiment can be restricted to Vsc, since the output voltage difference is zero volts between the two power supply lines FVH and FLG connected to the driver circuit for driving the sustain discharge type Y electrode during the sustain discharge period. Also, in the drive unit of the flat panel display in accordance with this embodiment, a push-pull type driver can be used, which enables high speed line sequential scanning. Power recovery is also possible by connecting two LC resonance circuit lines to the drive unit, so that a power saving type drive unit for a flat-panel display can be realized. Further the circuit arrangement of the drive unit can be simplified by forming the driver circuit as a LSI, so as to provide an economical driver for a flat-panel display.

Claims: A driver suitable for a panel display system of the type having at least two substrates (12, 13) each having electrodes (14, 15, 16) on the surface thereof arranged closely so that said electrodes intersect and face mutually, a plurality of intersections formed between said electrodes constructing cells (10), a plurality of said cells being arranged in a matrix configuration to form a display panel, each of said cells having a capability of a memory for storing a given amount of charge according to a voltage applied to an electrode in the cell and also having capabilities of discharge and light emission, said electrodes comprising n scan electrodes (15-1, 15-2,...,15-n), which are independent of each other; wherein said driver comprises: a plurality of driver circuits (101, 102, ...,10-n) provided between a first power supply line (FVH) and a second power supply line (FLG), and individually connected to the scan electrodes; characterised by : a first power supply circuit (71),for supplying a first defined voltage to the first and the second power supply lines during a scan address period, said first defined voltage being used to write display data; and a second power supply circuit (90) for supplying a second defined voltage to the first and the second power supply lines during a sustain discharge period, said second defined voltage being used to cause discharges based on the display data. A driver according to claim 1, said first power supply circuit (71) including: a first voltage generator (72), connected to the first power supply line (FVH), for generating a higher potential power supply voltage, and a second voltage generator (73), connected to the second power supply line (FLG), for generating a lower potential power supply voltage; and said second power supply circuit (90) including: a third voltage generator (91), connected to the first power supply line (FVH), for generating a lower potential power supply voltage, and a fourth voltage generator (92), connected to the second power supply line (FLG), for generating a higher potential power supply voltage (Vs). A driver according to claim 1, wherein each of the driver circuits includes a plurality of transistors (TR6, TR7) serially connected between the first and the second power supply lines (FVH, FLG). A driver according to claim 3, wherein each of the driver circuits further includes diodes (D02, D03) connected in parallel to the transistors (TR6, TR7). A driver according to claim 2, said first, second, third and fourth voltage generators (72, 73, 91, 92) being individually provided with switches (74, 75, 93, 94) for applying predetermined voltages to the first and second power supply lines (FVH, FLG) connected thereto in response to control signals applied thereto. A driver according to claim 1, said first and second power supply lines (FVH, FLG) being connected to the driver circuits in common.

Inventors: HIROSE TADATSUGU, KAMEYAMA SHIGEKI, KISHI TOMOKATSU, OTSUKA AKIRA, YOSHIKAWA KAZUO, HIROSE, TADATSUGU, KAMEYAMA, SHIGEKI, KISHI, TOMOKATSU, OTSUKA, AKIRA, YOSHIKAWA, KAZUO, HIROSE, TADATSUGU, C/O FUJITSU LIMITED, KAMEYAMA, SHIGEKI, C/O FUJITSU LIMITED, KISHI, TOMOKATSU, C/O FUJITSU LIMITED, OTSUKA, AKIRA, C/O FUJITSU LIMITED, YOSHIKAWA, KAZUO, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1994
Main classification: G09G3
IPC codes: G09G3