Phase synchronization circuit having a short pull-in time and a low jitter

Abstract: In a phase synchronization circuit including a digital phase comparator 1, a synchronism discrimination circuit 2, a charge pump circuit 3, a loop filter 11, a voltage controlled oscillator 14, and a frequency-division circuit 6, the charge pump circuit 3 is composed of a level comparator 15 comparing the output voltage of the loop filter 11 with a predetermined reference voltage, for outputting a level discrimination signal, an AND circuit 4 for outputting a logical product of an output UP of the phase comparator 1 and the level discrimination signal, an inverter 5 for outputting an inverted signal of an output DOWN of the phase comparator 1, an AND circuit 6 for outputting a logical product of an output signal of the inverter 5 and the level discrimination signal, a PMOS transistor 8 having its source connected to a voltage supply through a constant current source 7, its gate applied with an output signal of the AND circuit 4, and its drain connected to an input of the loop filter 11, and an NMOS transistor 9 having its drain connected to the input of the loop filter 11, its gate applied with an output signal of the AND circuit 6, and its source connected to ground through a constant current source 10.

Description: Background of the Invention Field of the invention The present invention relates to a phase synchronization circuit. Description of related art Conventionally, various types of phase synchronization circuits have been proposed. In order to realize a high-speed pull-in operation and a low jitter in a circuit configured to multiplying a frequency of an input signal, measures are taken to change a constant of a loop filter by means of a synchronism discrimination circuit (for example, Japanese Patent Application Laid-Open Publication No. JP-A-2-211718 and No.JP-A-4-241520). One example of such conventional ones is shown in Figure 1, which is composed of a phase comparator 1; a synchronism discrimination circuit 2; a charge pump circuit 3 comprising a constant current source 7 of a flow-out type (current value : I 1 ), a constant current source 10 of a flow-in type (current value : I 2 ), a PMOS transistor 8, an NMOS transistor 9 and an inverter 35; a loop filter comprising a resistor 12 and a capacitor 13; a voltage controlled oscillator 14; and a frequency-division circuit 16, which are connected as shown. As the phase comparator 1 of Figure 1, a circuit shown in Figure 2 is well known, which is composed of NAND circuits 21, 22, 23, 24, 25, 26, 27, 28, and 29, which are connected as shown. In Figure 2, an output UP and an output DOWN are ordinarily at a high level in response to an input R receiving a predetermined input signal and an input V receiving a frequency-divided output signal from the frequency-division circuit 16. When a trailing edge of the input R is in advance of a trailing edge of the input V, the output UP is brought to a low level during that period in which die trailing edge of the input R is in advance of the trailing edge of the input V. On the contrary, when the trailing edge of the input R is delayed from the trailing edge of the input V, the output DOWN is brought to a low level during that period in which the trailing edge of the input R is delayed from the trailing edge of the input V. The loop filter 11, is a circuit for removing a noise generated in the phase comparator 1, and is generally constituted of a low pass filter. The voltage controlled oscillator 14 is controlled by an output voltage of the loop filter 11 so that an oscillation frequency of the voltage controlled oscillator 14 is controlled in accordance with the output voltage of the loop filter 11, so as to generate an oscillation signal having a frequency corresponding to the output voltage of the loop filter 11. The frequency-division circuit 16 frequency-divides the oscillation frequency of the voltage controlled oscillator 14 so as to output a frequency-divided signal to the phase comparator 1, and is often constituted of a synchronizing counter. In addition, the synchronism discrimination circuit 2 is composed of a well known circuit shown in Figure 3, which is composed of a NAND circuit 17, a resistor 18, a capacitor 19 and an inverter 20, which are connected as shown. If the output UP or the output DOWN of the phase comparator 1 shown in Figure 1 is at a low level for a long period of time, it is judged that a synchronization is not attained in the phase synchronization circuit. Operation of the phase synchronization circuit will now be explained. In Figure 1, if the trailing edge of the input R of the phase comparator 1 is in advance of the trailing edge of the input V of the phase comparator 1 so that the output UP of the phase comparator 1 is brought to the low level and the output DOWN is at the high level, the PMOS transistor 8 turns ON and the NMOS transistor 10 turns OFF. As a result, the capacitor 13 is charged through the constant current source 7 and the PMOS transistor 8, and a potential V B of a connecting node B rises up, which increases the oscillation frequency of the voltage controlled oscillator 14. On the contrary, if the trailing edge of the input R of the phase comparator 1 becomes delayed from the trailing edge of the input V of the phase comparator 1 so that the output UP of the phase comparator 1 is at a high level and the output DOWN is brought to a low level, the PMOS transistor 8 turns OFF and the NMOS transistor 10 turns ON. Accordingly, the capacitor 13 is discharged through the constant current source 10 and the NMOS transistor 9, and the potential V B of the connecting node B falls down, which lowers die oscillation frequency of the voltage controlled oscillator 14. If the output UP or the output DOWN of the phase comparator 1 is at a low level for a long period of time, it is discriminated in the synchronism discrimination circuit 2, that the synchronization is not attained in the synchronization circuit. In this case, by means of the control signal generated by the synchronism discrimination circuit 2, the current values of the constant current source 7 and the constant current source 10 are made large, so that a synchronization is quickly attained Thereafter, if the phase synchronization circuit becomes in a synchronized condition so that the time period of the low level of the output UP or the output DOWN of the phase comparator 1 becomes short, or else both of the output UP and the output DOWN are always at a high level, the current values of the constant current source 7 and the constant current source 10 is decreased under control of the control signal outputted from the synchronism discrimination circuit 2, whereby a low jitter control can be realized in the phase synchronization circuit. The constant current source 7 and the constant current source 10 are designed to have the same current value so that they have the same amount of phase adjustment. In this case, if it is assumed that the same current value is I (I 1 = I 2 = I), a capacitance value of the capacitor 13 is C 13 , an inherent angular frequency of the phase synchronization circuit is ω n , a damping coefficient is ζ, a gain of the voltage controlled oscillator 14 is K, a frequency-division ratio of the frequency-division circuit 16 is N, and a resistance value of the resistor 12 of the loop filter 11 is R 12 , I and R can be represented as follows: I = ω n 2 • N • C 13 /K R 12 = 2 ζ / (ω n • C 13 ) In addition, an input voltage V IN of the voltage controlled oscillator 14 is exactly the same as a voltage V B on the node B which has been generated by the fact that an electric charge is charged into the capacitor 13 during a period of time required for the current value I to be detected in the phase comparator 1. The oscillation frequency f of the voltage controlled oscillator 14 corresponding to this input voltage V IN is represented by the following equation: f = V IN • K By using above mentioned equations (1), (2) and (3) on the condition that N = 512 (input frequency of 8 KHz, output frequency 4.096 MHz), C13 = 60 pF, K = 2.0 MHz/V, R = 25 MΩ, the current value I of the constant current source in the synchronized condition is equal to 40 nA, the current value I of the constant current source in the non-synchronized condition is equal to 400 nA, ω n = 2π × 256 rad/s, ζ=1,2, the change in time of the oscillation frequency f of the voltage controlled oscillator 14 is calculated, and the characteristic curve 101 shown in Figure 5 is obtained. Given the time t r which elapses before the oscillation frequency f becomcs constant is a pull-in time, t r = 7ns. The phase synchronization circuit is generally used in various applications. For example, when it is used for PCM CODEC, that is to say in the system required to have a constant frequency all the time, the voltage level of the output voltage V B of the loop filter 11 is maintained, in a synchronized condition, at the same level as that of a voltage V 0 which is shown in the characteristics of the voltage controlled oscillator shown in Figure 4. However in the conventional phase synchronization circuits, the charging/discharging operation of the capacitor 13 during a pull-in process for synchronization is conducted only when the output UP or the output DOWN of the phase comparator 2 is at a low level. Therefore, there is a disadvantage that when both the output UP and the output DOWN of the phase comparator 1 are at a high level, the capacitor 13 is neither charged nor discharged even under the condition that there is a large difference in voltage level between the voltage V B and the V 0 . Consequently, the pull-in time for the phase synchronization becomes long. Summary of the Invention Accordingly, it is an object of the present invention to provide a phase synchronization circuit which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a phase synchronization circuit having a charge pump circuit, which is capable of shortening a phase synchronization pull-in time, without damaging the jitter characteristics after the phase synchronization has been attained. The above and other objects of the present invention are achieved in accordance with the present invention by a phase synchronization circuit which includes: a digital phase comparator, a synchronism discrimination circuit receiving an output of the phase comparator, for discriminating a phase synchronization condition so as to output a control signal , a charge pump circuit receiving the output of the phase comparator, and controlled by the control signal, for outputting a phase differential signal, a loop filter receiving the phase differential signal of the charge pump circuit, for limiting a frequency band of the phase differential signal, a voltage controlled oscillator frequency-controlled by an output voltage of the loop filter, and a, frequency-division circuit receiving an output signal of the voltage controlled oscillator, for frequency-dividing the output signal of the voltage controlled oscillator and for feeding back a frequency-divided output signal to the phase comparator, wherein the charge pump comprises: a level comparator receiving the output voltage of the loop filter for comparing it with a predetermined reference voltage so as to output a predetermined level discrimination signal, a first AND circuit receiving a first output signal of the phase comparator and the level discrimination signal, for outputting a logical product signal, an inverter receiving a second output signal of the phase comparator for outputting an inverted signal of the second output signal, a second AND circuit receiving the inverted signal outputted from the inverter and the level discrimination signal, for outputting a logical product signal, a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of the first AND circuit, and its drain connected to an input of the loop filter, and an NMOS transistor having its drain connected to the input of the loop filter, its gate connected to receive an output signal of the second AND circuit, and its source connected to ground through a second constant current source, a current value of the first constant current source being controlled by the control signal outputted form the synchronism discrimination circuit and the level discrimination signal, and a current value of the second constant current source being controlled by the control signal outputted form the synchronism discrimination circuit. According to a second aspect of the second invention, there is provided a phase synchronization circuit which includes: a digital phase comparator, a synchronism discrimination circuit receiving an output of the phase comparator, for discriminating d phase synchronization condition so as to output a control signal , a charge pump circuit receiving the output of the phase comparator, and controlled by the control signal, for outputting a phase differential signal, a loop filter receiving the phase differential signal of the charge pump circuit, for limiting a frequency band of the phase differential signal, a voltage controlled oscillator frequency-controlled by an output voltage of the loop filter, and a frequency-division circuit receiving an output signal of the voltage, controlled oscillator, for frequency-dividing the output signal of the voltage controlled oscillator and for feeding back a frequency-divided output signal to the phase comparator, wherein the charge pump comprises: a first level comparator receiving the output voltage of the loop filter for comparing it with a first predetermined reference voltage so as to output a first predetermined level discrimination signal, a second level comparator receiving the output voltage of the loop filter for comparing it with a second predetermined reference voltage so as to output a second predetermined level discrimination signal, an AND circuit receiving a first output signal of the phase comparator and the first level discrimination signal, for outputting a logical product signal, a first OR circuit receiving an output signal of the AND circuit and the second level discrimination signal, for outputting a logical sum signal, an inverter receiving a second output signal of the phase comparator for outputting an inverted signal of the second output signal, a second OR circuit receiving an output signal of the inverter and the second level discrimination signal, for outputting a logical sum signal, a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of the first OR circuit, and its drain connected to an input of the loop filter, and an NMOS transistor having its drain connected to the input of the loop filter, its gate connected to receive an output signal of the second OR circuit, and its source connected to ground through a second constant current source, a current value of the first constant current source being controlled by the control signal outputted form the synchronism discrimination circuit and the first level discrimination signal, and a current value of the second constant current source being controlled by the control signal outputted form the synchronism discrimination circuit and the second level discrimination signal. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram showing a conventional example; Figure 2 a circuit diagram showing one example of the phase comparator used in the first embodiment; Figure 3 is a circuit diagram showing one example of the phase synchronism discrimination circuit used in the first embodiment; Figure 4 is a graph showing the oscillation frequency characteristics of the voltage controlled oscillator; Figure 5 is a graph showing the synchronization pull-in characteristics of the phase synchronizing circuit; Figure 6 is a block diagram of the first embodiment of the phase synchronization circuit in accordance with the present invention; and Figure 7 is a block diagram of the second embodiment of the phase synchronization circuit in accordance with the present invention; Description of the Preferred embodiments The present invention will now be described with reference to the the accompanying drawings. Figure 6 shows a block diagrams of a first embodiment of the phase synchronization circuit in accordance with the present invention. In Figure 6, elements similar to those shown in Figure 1 are given the same Reference Numerals. As shown in Figure 6, this embodiment includes a phase comparator 1 having an input R receiving a predetermined input signal and an input V receiving a frequency-divided output signal, and also having an output UP and an output DOWN, which are connected to a synchronism discrimination circuit 2 and a charge pump circuit 3. This charge pump circuit 3 comprises an AND circuit 4 having a first input connected to the output UP of the phase comparator 1, an inverter 5 having an input connected to the output DOWN of the phase comparator 1, and an AND circuit 6 having a first input connected to an output of the inverter 5. The charge pump circuit 3 also includes a PMOS transistor (P-channel MOS (metal-oxide-semiconductor field effect transistor)) 8 having its source connected to a voltage supply V DD through a first constant current source 7 of the flow-out type, its gate connected to receive an output signal of the AND circuit 4, and its drain connected to a node A, and an NMOS transistor (N-channel MOS (metal-oxide-semiconductor field effect transistor)) 9 having its drain connected to the node A, its gate connected to receive an output signal of the AND circuit 6, and its source connected to ground through a second constant current source 10 of the flow-in type. The constant current source 7 is controlled by an output of the synchronism discriminator 2 and a level comparator 15, so that the amount of current flowing through the constant current source 7 is adjusted to become large or small. Similarly, the constant current source 10 by the output of the synchronism discriminator 2, so that the amount of current flowing through the constant current source 10 is adjusted to become large or small. An output of the charge pump circuit 3, namely, the node A is connected to a loop filter 11, which comprises a resistor 12 connected at its one end to the node A and at its other end to another node B, and a capacitor 13 having one end connected to the node B and the other end connected to ground. An output of this loop filter 11, namely, the node B is connected to a non-inverting input of the level comparator 15, which has its inverting input connected to a reference voltage V 1 explained hereinafter. The node B is also connected to an input of a voltage controlled oscillator 14, which has an output connected to an output OUT and an input of a frequency-division circuit 16. An output of the frequency-division circuit 16 is connected to the input V of the phase comparator 1. As clearly seen from comparison between Figures 1 and 6, the first embodiment is different from the conventional example in the construction of the charge pump circuit which is one of the components of the phase synchronization circuit. Namely, the charge pump circuit of the conventional example is composed of the constant current sources 7 and 10, the PMOS transistor 8, the NMOS transistor 9, and the inverter 35. In this embodiment, on the contrary, the charge pump circuit 3 of the first embodiment comprises, as stated above, the AND circuits 4 and 6, the inverter 5, the constant current sources 7 and 10, the PMOS transistor 8, the NMOS transistor 9 and the comparator 15. In Figure 6, the non-inverting input of the comparator 15 is applied with the output of the loop filter 11, that is, a potential V B at the connecting node B connected to the input of the voltage controlled oscillator 14. The inverting input of the comparator 15 is applied with the reference voltage V 1 , which has a level lower than that of the voltage V 0 shown in Figure 4. If the phase synchronization circuit is not in the synchronized condition and the level of the potential V B of the connecting node B gradually falls down to a level lower than the reference voltage V 1 , the output level of the comparator 15 is brought to a low level, which is applied to the AND circuits 4 and 6, as well as to the constant current source 7 as a control signal for shifting its current value to a large current in this case. Furthermore, in the situation that the phase synchronization circuit is not in the synchronized condition and the level of the potential V B of the connecting node B falls down to a level lower than the reference voltage V 1 by action of the discharge of the capacitor 13, respectively input paths from the output UP and the output DOWN of the phase comparator 1 to the PMOS transistor 8 and the NMOS transistor 9, are shut down by means of a gate function of the AND circuits 4 and 6, so that the low level signal is applied to the gate of each of the POMS transistor 8 and the NMOS transistor 9. In this case, the PMOS transistor 8 turns ON and the NMOS transistor 9 turns OFF, regardless of the output of the phase comparator 1, so that the loop filter 11 and the voltage controlled oscillator 14 of the phase synchronization circuit are brought into a phase synchronizing pull-in operation. Because of this, the capacitor 13 is charged with a large current I 1 through the constant current source 7 and the PMOS transistor 8, which increases the potential V B of the connecting node B so that it will exceed the reference voltage V 1 . As a result, the oscillation frequency of the voltage controlled oscillator 14 is shifted to a high frequency, which is then applied to the input V of the phase comparator 1 through the frequency-division circuit 16. In this way, when the output DOWN of the phase comparator 1 stays at a low level, the phase synchronization circuit is forced to restore the phase pull-in condition by action of a level comparing function of the comparator 15. Accordingly, the time required to attain the synchronized condition is shortened. On the other hand, when the level of the potential V B of the connecting node B exceeds the reference voltage V 1 applied to the inverting input of the comparator 15, the output level of the comparator 15 is brought to a high level, which is applied to the AND circuits 4 and 6 as well as to the constant current source 7 so as to limit the current of the constant current source 7. Furthermore, when the potential V B of the connecting node B exceeds the level of the reference voltage V 1 , the output UP and the output DOWN of the phase comparator 1 are applied normally to the gate of PMOS transistor 8 and the NMOS transistor 9 by the gate function of the AND circuits 4 and 6, respectively. Accordingly, a normal working condition of the phase synchronization circuit is restored. In this case, the operation of the phase synchronization circuit is carried out by means of the output UP and the output DOWN of the phase comparator 1, and when the output UP or the output DOWN stays at a low level for long time of period, the synchronism discrimination circuit 2 discriminates that the synchronization is not attained in the phase synchronization circuit, and carries out the control operation for making the current values of the constant current source 7 and the constant current value 10 large. On the other hand, if the output UP and the output DOWN stays at a low level only for a short period of time, the synchronism discrimination circuit 2 concludes that the synchronization is attained in the phase synchronization circuit, and carries out the control operation for making the current values of the constant current source 7 and the constant current source 10 small. In the synchronism discrimination circuit 2, furthermore, as a condition or standard for discriminating the phase synchronization, it is determined whether the phase difference detected by the phase comparator 1 was caused by a jitter which occurred after the synchronization has been attained in the phase synchronization circuit or it was detected because the synchronization has not yet been attained. For this purpose, the discrimination of synchronization/non-synchronization is performed by using, as a criterion, a value slightly bigger than the width of a jitter occurred in the phase synchronization circuit. Figure 7 shows a block diagram of the second embodiment of the phase synchronization circuit in accordance with the present invention. In Figure 7, elements similar to those shown in Figure 6 are given the same Reference Numerals, and explanation of the construction thereof will be omitted. As clearly seen from the comparison between Figures 6 and 7, this second embodiment is different from the first embodiment in the construction of the charge pump circuit which is one of the components of the phase synchronization circuit. Namely, the charge pump circuit 3 of the second embodiment is composed of an AND circuit 30 having a first input connected to the output UP of the phase comparator 1 and a second input connected to the output of the level comparator 15, an OR circuit 31 having a first input connected to an output of the AND circuit 30. The charge pump circuit 3 also comprises an inverter 32 having an input connected to the output DOWN of the phase comparator 1, an AND circuit 36 having a first input connected to an output of the inverter 32 and a second input connected to the output of the level comparator 15, and an OR circuit 33 having a first input connected to an output of the AND circuit 6. An output of the OR circuit 31 is connected to the gate of the PMOS transistor 8, and an output of the OR circuit 33 is connected to the gate of the NMOS transistor 9. In addition, the output of the loop filter 11, namely, the node B, is connected not only the level comparator 15 but also a non-inverting input of another level comparator 34, which has its inverting input connected to another reference voltage V 2 which will be explained hereinafter. An output of this level comparator 34 is connected to a second input of each of the OR circuits 31 and 33. Furthermore, the current source 10 is controlled by not only the output of the synchronism discriminator 2 and the output of the level comparator 34. In Figure 7, similarly to the first embodiment, the non-inverting input of the comparator 15 is applied with the output of the loop filter 11, that is, the potential V B of the connecting node B connected to the input side of the voltage controlled oscillator 14. The inverting input of the comparator 15 is applied with the reference voltage V 1 having a level lower than the voltage V 0 shown in Figure 4. The non-inverting input of the comparator 34 is applied with the potential V B of the connecting node B, and the inverting input of the comparator 34 is applied with a reference voltage V 2 , which has a level higher than that of a voltage V 0 shown in Figure 4. The comparator 15 operates in the same manner as the first embodiment. Namely, when the potential V B of the connection node B gradually falls down to a level lower than the reference voltage V 1 , the output level of the comparator 15 is brought to a low level, which is then applied to the AND circuits 30 and 36, as well as to the constant current source 7 as a control signal for shifting its current value to a large current. In this situation, the output signal of the comparator 34 is also at a low level. Accordingly, the PMOS transistor 8 turns to ON regardless of the level of the output UP of the phase comparator 1, so that the loop filter 11 and the voltage controlled oscillator 14 of the phase synchronization circuit are brought into the phase pull-in operation condition. As a result, the capacitor 13 is charged with a large current I 1 through the constant current source 7 and the PMOS transistor 8, which increases the potential V B of the connecting node B so that it will exceed the reference voltage V 1 . Then, the oscillation frequency of the voltage controlled oscillator 14 is caused to shift to a high frequency, which is then applied to the input V of the phase comparator 1 through the frequency-division circuit 16. In this way, when V B < V 1 , the phase synchronization circuit is forced to restore the phase pull-in operation condition by means of a level comparing function of the comparators 15 and 34. Accordingly, the time required to attain the synchronized condition is shortened. On the other hand, if the level of the potential V B of the connecting node B gradually rises up, and then, exceeds the level of the reference voltage V 2 , the output level of the comparator 34 is then brought to a high level, which is in turn applied to the OR circuit 31 and the OR circuit 33, as well as to the constant current source 10 as a control signal for shifting its current value to a large current. Under this situation, the output signal of the comparator 15 is also at a high level. As a result, the NMOS transistor 9 turns ON regardless of the level of the output DOWN of the phase comparator 1, and the loop filter 11 and the voltage controlled oscillator 14 of the phase synchronization circuit are brought under the phase pull-in operation condition. Namely, the capacitor 13 is discharged will, the large current 12 through the constant current source 10 and the NMOS transistor 9, so that the potential V B of the connecting node B is caused to drop to a level lower than that of the reference voltage V 2 . Accordingly, an oscillation frequency of the voltage controlled oscillator 14 is caused to shift to a low frequency, which is then applied into the input V of the phase comparator 1 through the frequency-division circuit 16. In this way, in response to the situation where the output UP of the phase comparator 1 stays at a low level, the phase synchronization circuit is forced to restore the phase pull-in condition by action of a level comparing function of the comparators 15 and 34. Therefore, the time required to attain the synchronized condition is shortened. If, as the result of the above mentioned operations, the potential V B of the connecting node B, namely the input voltage of the voltage controlled oscillator 14 is brought to a voltage level between V 1 and V 2 , the outputs of the comparator 15 and the comparator 34 are brought to a high level and a low level, respectively. There is thus formed a path starting from the output UP of the phase comparator 1 to pass through the AND circuit 30 and the OR circuit 31 and to reach the gate of the PMOS transistor 8. There is also formed a path starting from the output DOWN of the phase comparator 1 to pass through the inverter 32 and via the OR circuit 33 and to reach to the gate of the NMOS transistor 9. Accordingly, the phase synchronizing circuit of the second embodiment assumes the circuit connection construction exactly identical to that of a proper phase synchronization circuit, and the synchronized condition is attained in a short period of time when the potential V B at the connecting node B is close to V 0 . For the above mentioned first and second embodiments, a calculation is conducted by using the above mentioned equations (1), (2) and (3) and under the numerical condition that N = 512 (input frequency : 8 KHz, output frequency : 4.096 MHz), C = 60 pF, K = 2.0 MHz/V, R = 25 MHz, a current value I of the constant current source in a synchronized condition is 40 nA, a current value I of the constant current source in a non-synchronized condition is 400 nA, an inherent angular frequency ω n = 2π × 256 rad/s, a damping coefficient ζ = 1.2. If the change in time of the oscillation frequency f of the voltage controlled oscillator 14 is calculated, the oscillation frequency characteristics shown by the line 102 in Figure 5 is obtained. The synchronization pull-in time t r which elapses before the oscillation frequency becomes constant, is represented as t r = 4ns. This synchronization pull-in time t r is not larger than 60 % of the value of the above mentioned conventional example. As explained above, when the voltage level outputted form the charge pump circuit and then applied to the input of the voltage controlled oscillator is greatly different front that of the predetermined voltage level corresponding to the phase synchronized condition, the synchronization pull-in takes a long time. To deal with this situation, the present invention advantageously makes it possible to shorten the synchronization pull-in time by controlling the discharge current in comparison with the capacitance of the loop filter, and while keeping a low jittering characteristics after the synchronization pull-in operation has been completed. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A phase synchronization circuit which includes a digital phase comparator (1), a synchronism discrimination circuit (2) receiving an output of said phase comparator (1), for discriminating a phase synchronization condition so as to output a control signal, a charge pump circuit (3) receiving the output of said phase comparator (1), and controlled by said control signal, for outputting a phase differential signal, a loop filter (11) receiving said phase differential signal of said charge pump circuit (3), for limiting the frequency band of said phase differential signal, a voltage controlled oscillator (14) frequency-controlled by the output voltage of said loop filter, a frequency-division circuit (16) receiving the output signal of said voltage controlled oscillator (14) for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to said phase comparator (1), an inverter (5) receiving a second output signal of said phase comparator for outputting the inverted signal of said second output signal, the charge pump circuit (3) comprising a PMOS transistor (8) having its source connected to a voltage supply through a first constant current source (7), and its drain connected to an input of said loop filter (11), an NMOS transistor (9) having its drain connected to said input of said loop filter (11) and its source connected to ground through a second constant current source (10), the current value of said first constant current source (7) being controlled by said control signal outputted from said synchronism discrimination circuit (2), and the current value of said second constant current source (10) being controlled by said control signal outputted from said synchronism discrimination circuit (2), characterized in that said charge pump further comprises: a level comparator (15) receiving said output voltage of said loop filter (11) for comparing it with a predetermined reference voltage (V 1 ) so as to output a predetermined level discrimination signal, the current value of said first constant current source (7) being further controlled by said level discrimination signal, a first AND circuit (4) receiving a first output signal of said phase comparator and said level discrimination signal, for outputting a logical product signal, a second AND circuit (6) receiving said inverted signal outputted from said inverter and said level discrimination signal, for outputting a logical product signal, the gate of said PMOS transistor (8) being connected to receive the output signal of said first AND circuit, and the gate of said NMOS transistor (9) being connected to receive the output signal of said second AND circuit. A phase synchronization circuit which includes a digital phase comparator (1), a synchronism discrimination circuit (2) receiving an output of said phase comparator (1), for discriminating a phase synchronization condition so as to output a control signal, a charge pump circuit (3) recieving the output of said phase comparator (1), and controlled by said control signal, for outputting a phase differential signal, a loop filter (11) receiving said phase differential signal of said charge pump circuit (3), for limiting the frequency band of said phase differential signal, a voltage controlled oscillator (14) frequency-controlled by an output voltage of said loop filter, a frequency-division circuit (16) receiving the output signal of said voltage controlled oscillator (14) for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to said phase comparator (1), an inverter (5) receiving a second output signal of said phase comparator for outputting the inverted signal of said second output signal, the charge pump circuit comprising a PMOS transistor (8) having its source connected to a voltage supply through a first constant current source (7), and its drain connected to an input of said loop filter (11), an NMOS transistor (9) having its drain connected to said input of said loop filter (11) and its source connected to ground through a second constant current source (10), the current value of said first constant current source (7) being controlled by said control signal outputted from said synchronism discrimination circuit (2), and the current value of said second constant current source (10) being controlled by said control signal outputted from said synchronism discrimination circuit (2), characterized in that said charge pump further comprises: a first level comparator (15) receiving said output voltage of said loop filter (11) for comparing it with a first predetermined reference voltage (V 1 ) so as to output a first predetermined level discrimination signal, the current value of said first constant current source (7) being further controlled by said first level discrimination signal, a second level comparator (34) receiving said output voltage of said loop filter for comparing it with a second predetermined reference voltage (V 2 ) so as to output a second predetermined level discrimination signal, the current value of said second constant current source (10) being further controlled by said second level discrimination signal, an AND circuit (30) receiving a first output signal of said phase comparator (1) and said first level discrimination signal, for outputting a logical product signal, a first OR circuit (31) receiving the output signal of said AND circuit and said second level discrimination signal, for outputting a logical sum signal, a second OR circuit (33) receiving an output signal of said inverter and said second level discrimination signal, for outputting a logical sum signal, the gate of said PMOS transistor (8) being connected to receive the output signal of said first OR circuit (31), and the gate of said NMOS transistor (9) being connected to receive the output signal of said second OR circuit (33). A phase synchronization circuit claimed in claim 2 wherein said charge pump (3) further comprises a second AND circuit (36) receiving said output signal of said inverter (32) and said first level discrimination signal, for outputting a logical product signal, which is supplied to said second OR circuit (33) as said output signal of said inverter.

Inventors: MASUDA KAZUAKI, MASUDA, KAZUAKI, MASUDA, KAZUAKI, C/O NEC IC MICROCOMPUTER SYSTEM
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H03L7
IPC codes: H03L7