Floating point multiplier

Abstract: A floating point multiplier includes an exponential part adder (105) performing adding process by inputting exponential parts of preliminarily separated floating point multiplied value and multiplying value for outputting an exponential addition result (111), a binary multiplier (210) performing multiplying process by inputting mantissa of the mutually separated floating point multiplied and the for outputting the result of multiplication, an OR gate (212) outputting an OR signal by inputting predetermined digits of lower bits (211) to output as the sticky bit (213), rounding process and normalization process circuit (116) for inputting the predetermined digit of upper bits (214) of said multiplication result and said sticky signal (213), performing rounding process and the normalizing process for the upper bits (214) of the multiplication result on the basis of the sticky bit (213), and coupling the result of normalization with the addition result (111) of the exponential parts to output the final multiplication result (117), and selection circuit (220) inputting the final multiplication result (117) and the lower bits (211) of the multiplication result of the binary multiplier for selectively outputting.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a floating point multiplier composed of integrated circuits. More specifically, the invention relates to a floating point multiplier which can be easily tested after production. Description of the Related Art When floating point multiplication, an adding process for exponential parts of a multiplied value and multiplying value, a multiplying process for mantissa, a rounding process for the product of multiplication of the mantissa and normalizing process are performed to finally obtain the result of multiplication. In the floating point multiplication, the mantissa is obtained from upper half bits of the product of multiplication of the mantissa of two inputs and a total sum of truncated lower bits. Concerning such floating point multiplication method have been described in IEEE 754, "IEEE Standard for Binary Floating-Point Arithmetic". In the conventional floating point multiplier, exponential parts of floating point multiplied value and multiplying value separated through preceding process step are added by an exponential part adder. On the other hand, mantissa of the floating point multiplied value and multiplying values are multiplied by a binary multiplier. When the mantissa is n bits, multiplication is performed by inputting p bits (p ≧ n) of mantissa to the binary multiplier. From the binary multiplier, 2p-1 bits of a product of multiplication is output. Among the produce of multiplication of the mantissa in the binary multiplier, a sticky bit of lower m bits is derived. On the other hand, on the basis of the sticky bit, rounding process and normalizing process for the upper q bits (q > n) are performed so that a final product of multiplication can be output by combining the results of the rounding process and the normalizing process with the mantissa processed through adding process. The binary multiplier inputs two binary values of bit length p (p ≧ n) assuming the let length of the mantissa of floating point is n bits and then outputs two vi¥binary values of bit length (2p-1). The output to be input to the rounding process and the normalizing process are upper q bits and a sticky bit of truncated lower (2p-1-q=m) bits. As set forth above, in the conventional floating point multiplier, lower m bits of the mantissa of the product of the binary multiplication is aggregated as sticky bit. Therefore, even when there is a faulty gate in the binary multiplier, it is difficult to detect failure of the gate on the basis of the output. Concerning the gate corresponding to the upper bit of the binary multiplier, test can be performed by monitoring the external output since the upper bits are externally output the final result of multiplication. Therefore, there should not be risen the problems as those raised in testing the lower bits. In order to detect failure of 1 bit in the lower output in question, it becomes necessary to apply a test pattern with such multiplied values and multiplying values to set all other lower output to "0" other than the bit in question and vary the bit in question between "0" and "1". Accordingly, for testing failure of all bits of the lower output, a large number of test patterns set forth above are to be prepared for each digit of the lower bits for performing testing by inputting each test pattern in one by one basis to make testing very cumbersome. Also, as the sticky bit of OR gate is an internal signal instead of an externally output signal, testing becomes further cumbersome. The following is an example of the test pattern: Assuming that the lower m bits of the output of the binary multiplier is 5 bits, in order to detect failure of the gate for the second least significant bit, for example, "10101" and "11010" are input as the multiplied value and the multiplying values. When these two values are multiplied, if failure is not caused in the gate of the binary multiplier, the following calculation will be performed: From this, "1000100010", in which among the lower 5 bits, the second least significant bit in question is "1" and all other bits are "0" is output. If the gate corresponding to the second least significant bit is in failure, the second bit becomes "0" so that the sticky bit of the lower 5 bits becomes "0". Thus, failure of the gate can be detected. Assuming that the lower m bits of the output of the binary multiplier is 5 bits, in order to detect failure of the gate for the fourth lower bit, for example, "10111" and "11000" are input as the multiplied value and the multiplying values. When these two values are multiplied, if failure is not caused in the gate of the binary multiplier, the following calculation will be performed: From this, "1000101000", in which among the lower 5 bits, the fourth lower bit in question is "1" and all other bits are "0" is output. If the gate corresponding to the second least significant bit is in failure, the fourth lower bit becomes "0" so that the sticky bit of the lower 5 bits becomes "0". Thus, failure of the gate can be detected. As set forth above, since failure of the gate is detected from the result of multiplication of a large number of test patterns which are preliminarily prepared, the testing is very labor and time intensive work. From 1990 IEEE INT'L CONFERENCE ON COMPUTER DESIGN: VLSI In Computers & Processors, 17-19 Sept. 1990, Cambridge, USA, A. KATSUNO ET AL.: 'A 64-bit Floating Point Processing Unit with a Horisontal Instruction Code for Parallel Operations' teaches a binary multiplier with a normalization function. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a floating point multiplier which can easily perform a failure detection test for gates of a binary multiplier on the basis of lower bits of a result of multiplication performed by a binary multiplier which performs multiplication of the mantissa. In order to accomplish the above-mentioned and other objects, a floating point multiplier, according to one aspect of the invention, comprises: exponential part adder means for inputting exponential parts of floating point multiplied value and multiplying value of the floating point indications which are separated from each other and effecting the process of addition for outputting the result of addition of the exponential parts; binary multiplier means for inputting mantissa of the multiplied value and the multiplying value of the floating point indication which are separated from each other; an OR gate outputting an OR signal by inputting predetermined digits of lower bits to output as the sticky bit; rounding process and normalization process means for inputting the predetermined digit of upper bits of the multiplication result and the sticky signal, performing rounding process and the normalizing process for the upper bits of the multiplication result on the basis of the sticky bit, and coupling the result of normalization with the addition result of the exponential parts to output the final multiplication result; and selection means for inputting the final multiplication result and the lower bits of the multiplication result of the binary multiplier for selectively outputting either of them in response to an input test selection signal. According to another aspect of the invention, a floating point multiplier comprises: exponential part adder means for inputting exponential parts of floating point multiplied value and multiplying value of the floating point indications which are separated from each other and effecting the process of addition for outputting the result of addition of the exponential parts; binary multiplier means inputting mantissa of the multiplied value and the multiplying value of the floating point indication which are separated from each other; normalization process means for inputting the predetermined digit of upper bits of the multiplication result and the exponential part addition result, performing the normalizing process for the upper bits of the multiplication result signal, and coupling the result of normalization with the addition result of the exponential parts to output the final multiplication result; and selection means inputting the final multiplication result and a predetermined digit of lower bits of the multiplication result of the binary multiplier for selectively outputting in response to an input test selection signal. In the preferred construction, the select means inputs an externally provided selection signal for outputting the final multiplication result while the selection signal is absent and the lower bits of the multiplication results of the binary multiplier only when the selection signal is input. Preferably, the selection means comprises a multiplexer. The binary multiplier may input n bits mantissa as p (p ≧ n) and output the multiplication result of (2p-1) bits; and the select means may input the final multiplication result and the lower (2p-1-q) bits of the multiplication result of the binary multiplier. Also, the OR gate may input the lower (2p-1-q) bits (q > n) for deriving an OR and output one bit sticky bit, and the rounding process and normalizing process means may input the upper q bits of the multiplication result of the binary multiplier, the addition result and the sticky bit. Other objects, feature and advantages of the present invention will become apparent from the detailed description given herebelow. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description of the invention and the accompanying drawings of the preferred embodiment, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only. In the drawings: Fig. 1 is a block diagram showing a construction of the first embodiment of a floating point multiplier according to the present invention; and Fig. 2 is a block diagram showing a construction of the second embodiment of a floating point multiplier according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiments of the present invention will be discussed hereinafter with reference to the accompanying drawings. Fig. 1 shows the first embodiment of a floating point multiplier according to the present invention. In Fig. 1, the first embodiment of the floating point multiplier comprises a exponential part adder 105 for adding process of exponential parts of a multiplied value and a multiplying value, a binary multiplier 210 for inputting and multiplying mantissa of the multiplied value and the multiplying value, a rounding process and normalizing process circuit 116 for performing rounding process and normalizing process for the product of multiplication by the binary multiplier 210, an OR gate for deriving a logical sum (OR) of lower m bits of the product of multiplication by the binary multiplier 210, and a select circuit 220 for selectively outputting the product of multiplication of the multiplied value and the multiplying value or data for testing. To the exponential part adder 105, exponential parts 101 and 102 of the multiplied value and the multiplying value, which are separated through the preceding process step, are input. These inputs are processed by addition and then output as an addition result 111. In the binary multiplier 210, two data derived by converting the mantissa (n bits: n is a positive integer) with the bit length p (p ≧ n) of the multiplied value and the multiplying value of floating point indication separated through the preceding process step, are input as input data 103 and 104. The binary multiplier 210 performs multiplying process for the input data 103 and 104 for outputting product of multiplication of (2p-1) bits. Among the (2p-1) bits of the product of multiplication output from the binary multiplier 210, lower m bits ( m ≦ n : m = 2p - 1 - q) 211 excluding upper q bits (q > n) are input to the OR gate 2121. In the OR gate 212, OR of the lower m bits 211 is derived and output as one bit sticky bit 213. The rounding process and normalizing process circuit 116 takes the sticky bit 213 output from the OR gate 212 as control signal to output the multiplication product 117 from the result of addition 111 of the exponential parts in the exponential part adder 105 and upper q bits 214 of the multiplication result of the binary multiplier 210. The rounding process to be performed by the rounding process and normalizing process circuit 116 is a process for rounding up (outputting by adding "1") the digit lower than the significant digit greater than equal to 0.5 and rounding down the digit smaller than 0.5 (outputting upper q bits as is). In concrete, judgement is made on the basis of the sticky bit 213 and the upper q bits of the multiplication result of the binary multiplier 210 to selectively output a rounded up value derived by adding "1" to the upper q bits of the multiplication result of the binary multiplier 210 or a rounded down value which is the upper q bits per se (by rounding down the digit lower than the significant digit). The normalization process in the rounding process and normalizing process circuit 116 is a process for inputting the rounded up value or rounded down value through the rounding process and for effecting left shifting so that the upper 2 bits becomes greater than or equal to 1 and smaller than 2. On the other hand, in the rounding process and normalizing process circuit 116, coupling of the value of the normalized mantissa and the exponential part adding result output from the exponential part adder 105 is effected to output as the product of multiplication 117. The select circuit 222 comprises a multiplexer, for example. To this selection circuit 220, according to an input test selection signal, the product of multiplication 117 and the lower m bits of the multiplication result output from the binary multiplier 210 are selectively output. The select circuit 220 outputs the product of multiplication 117 while the test selection signal 221 is not input (normal multiplication mode). Only when the test selection signal 221 is input, the selection circuit 220 outputs the lower m bits of the multiplication result of the binary multiplier 210. Accordingly, by the test selection signal 221, the floating point multiplier can be switched between the multiplication mode and test mode. In the shown embodiment of the floating point multiplier, in addition to the original floating point multiplication, it is provided with an instruction for providing the test selection signal 221 for selectively outputting the lower bits of the output of the binary multiplier 210. Therefore, by outputting the lower bits of the output of the binary multiplier depending upon necessity, the lower bits of the binary multiplier can be externally monitored. Accordingly, it becomes possible to easily perform testing for detecting failure of the internal gate of the binary multiplier, which is otherwise cause substantial difficulty as in the prior art. Namely, conventionally, since the presence of faulty gate of the binary multiplier 210 need to be judged on the basis of the sticky bit of the lower bit of the binary multiplier 210, a large number of test patterns should be preliminarily provided. Also, the sticky bit of the OR gate 212 is the internal signal instead of the signal externally output from the floating point multiplier, the testing has been cumbersome work in the prior art. In contrast to this, since the shown embodiment permits selectively outputting of the lower bits of the binary multiplier externally, it becomes possible to monitor the overall output of the binary multiplier 210. As a result, number of test pattern required for testing can be significantly reduced so as to significantly reduce the work load and working time. it should be appreciated that, concerning the gates corresponding to the upper bits of the binary multiplier, since the upper bits are externally output as the final result of multiplication, the test can be performed by simply monitoring the external output. Therefore, no inconvenience as experienced in the lower bit will never arisen. Fig. 2 shows the second embodiment of a floating point multiplier according to the present invention. The shown floating point multiplier has a construction, in which the rounding process in the first embodiment is neglected. Accordingly, in place of the rounding process and normalizing process circuit 116, a normalizing process circuit 300 which performs normalization only for the upper bits of the binary multiplier 210. On the other hand, the OR gate for deriving the stocky bit is not provided. In the normalization circuit 300. The upper bits of the normalized output of the binary multiplier 210 and the exponential part adding result of the exponential part adder 105 are combined to output the final product of the multiplication to a selection circuit 320 (for instance, it may comprise a multiplexer). In this kind of floating point multiplier, the lower bits of the output of the binary multiplier is normally truncated or rounding down so as not to be output externally. Therefore, in order to monitor the lower bits of the output of the multiplier 210, it is required to monitor the lower bit of the output of the binary multiplier incorporated in the floating pint multiplier. This makes the test labor and time intensive work. Accordingly, even in the shown second embodiment, since the lower bit of the multiplication result of the binary multiplier can be externally output as the output of the floating point multiplier 210, it becomes possible to monitor the lower bit of the binary multiplier. Thus, it becomes possible to easily perform the test for detection of the faulty gate of the binary multiplier 210. Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above.

Claims: A floating point multiplier characterized in that it comprises: exponential part adder means (105) for inputting exponential parts (101, 102) of floating point multiplied value and multiplying value of the floating point indications which are separated from each other and effecting the process of addition for outputting the result of addition of the exponential parts; binary multiplier means (210) for inputting mantissa of the multiplied value and the multiplying value of the floating point indication which are separated from each other; an OR gate (212) outputting an OR signal by inputting predetermined digits of lower bits (211) to output as the sticky bit (213); rounding process and normalization process means (116) for inputting the predetermined digit of upper bits (214) of said multiplication result and said sticky bit signal, performing rounding process and the normalizing process for the upper bits of the multiplication result on the basis of the sticky bit (213), and coupling the result of normalization with the addition result of the exponential parts to output the final multiplication result (117); and selection means (220) for inputting the final multiplication result (117) and the lower bits (211) of the multiplication result of the binary multiplier for selectively outputting either of them in response to an input test selection signal. A floating point multiplier as set forth in claim 1, wherein said select means inputs an externally provided selection signal (221) for outputting the final multiplication result while said selection signal (221) is absent and the lower bits of the multiplication results of the binary multiplier (210) only when said selection signal is input. A floating point multiplier as set forth in claim 1, wherein said selection means comprises a multiplexer. A floating point multiplier as set forth in claim 1, wherein said binary multiplier (210) inputs n bits mantissa as p (p ≧ n) and outputs the multiplication result (214) of (2p-1) bits; said OR gate (212) inputs the lower (2p-1-q ;q > n) bits (211) for deriving an OR and outputs one bit sticky bit (213); said rounding process and normalizing process means (116) inputs the upper q bits of the multiplication result (214) of the binary multiplier (210), the addition result (111) and the sticky bit (213); and said select means (220) inputs the final multiplication result (117) and the lower (2p-1-q) bits (211) of the multiplication result of the binary multiplier (210). A floating point multiplier characterized in that it comprises: exponential part adder means (105) for inputting exponential parts (101, 102) of floating point multiplied value and multiplying value of the floating point indications which are separated from each other and effecting the process of addition for outputting the result of addition of the exponential parts; binary multiplier means (210) for inputting mantissa of the multiplied value and the multiplying value of the floating point indication which are separated from each other; normalization process means (300) for inputting the predetermined digit of upper bits (214) of said multiplication result and said exponential part addition result (111), performing the normalizing process for the upper bits of the multiplication result signal, and coupling the result of normalization with the addition result of the exponential parts to output the final multiplication result (117); and selection means (320) for inputting the final multiplication result (117) and a predetermined digit of lower bits (211) of the multiplication result of the binary multiplier for selectively outputting either of them in response to an input test selection signal. A floating point multiplier as set forth in claim 5, wherein said select means (320) inputs an externally provided selection signal (321) for outputting the final multiplication result (117) while said selection signal (321) is absent and the lower bits (211) of the multiplication results of the binary multiplier (210) only when said selection signal (321) is input. A floating point multiplier as set forth in claim 5, wherein said selection means comprises a multiplexer. A floating point multiplier as set forth in claim 1, wherein said binary multiplier (210) inputs n bits mantissa as p (p ≧ n) and outputs the multiplication result of (2p-1) bits; and said select means (320) inputs the final multiplication result (117) and the lower (2p-1-q) bits (211) of the multiplication result of the binary multiplier (210).

Inventors: HAGIHARA YASUHIKO, HAGIHARA, YASUHIKO, HAGIHARA, YASUHIKO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: G06F11
IPC codes: G01R31, G06F11