Automatic control circuit for a power amplifier

Abstract: In a power amplifier (5) circuit, deformed rises and overshoots in the waveform of an RF output signal (6) in the burst transmission mode are prevented by short-circuiting both ends of a capacitor (21) of a low-pass filter (10) with a switch (18) having a control terminal, before the start of transmission.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an automatic control circuit for a power amplifier for use in mobile digital cellular telephone systems and portable telephones. Description of the Prior Art FIG. 6 is a diagram of an automatic control circuit for a power amplifier of the prior art which is used for burst transmission in mobile digital cellular telephone systems and portable telephones which is similar to that disclosed in EP-A-509 733. In FIG. 6, reference numeral 1 represents a baseband signal, 2 an oscillator for generating a carrier wave, 3 a modulator for modulating the carrier wave 2 with the baseband signal 1, 4 a radio frequency signal output from the modulator 3, and 5 a power amplifier for amplifying the radio frequency signal 4 and having a gain control terminal 5a. Reference numeral 6 represents a radio frequency output signal (referred to as an "RF output signal" hereinafter) amplified by the power amplifier 5, 7 a detector for detecting the envelope waveform of the RF output signal, 8 a reference signal voltage generator for generating the waveform of a reference signal voltage 31, 9 a comparator for detecting the difference between the waveform detected by the detector 7 and the waveform of the reference signal voltage 31, and 10 a low-pass filter for filtering an error signal 32 output from the comparator 9 and supplying the error signal 32 to the gain control terminal 5a of the power amplifier 5. The reference signal voltage generator 8 comprises a D/A converter 12 for converting digital data into analog data to output the reference signal voltage 31, a waveform generating ROM 13 for storing data 33 to be supplied to the D/A converter 12, a counter 14 for specifying an address in the ROM 13, and a RAMP controller 15 for outputting a signal for controlling a transmission waveform at the start and end of a burst transmission to the counter 14. Reference numeral 16 represents a transmission control signal for controlling the counter 14 and the ROM 13, and 17 a power level control signal for controlling the ROM 13. A description is subsequently given of the operation of the prior art control device. The baseband signal 1 is modulated by the modulator 3 together with the carrier wave from the oscillator 2 to generate the the radio frequency output signal 6 (referred to as the "RF output signal" hereinafter). This RF output signal 6 is amplified by the power amplifier 5 and transmitted through an isolator, a duplexer and an antenna. For the purpose of effecting an optimal and stable transmission, the waveform of the RF output signal 6 amplified by the power amplifier 5 is detected by the detector 7, and this detection output and the reference signal voltage 31 from the reference signal voltage generator 8 are compared by the comparator 9 to output an error signal voltage 32 which is then fed back to the gain control terminal 5a of the power amplifier 5 through the lowpass filter 10. Furthermore, the reference signal voltage generator 8 operates in such a manner that the waveform generating ROM 13 and the counter 14 are activated by the transmission control signal 16 at the start of transmission and a CLK signal is then input into the counter 14 so that the counter 14 begins to count and specifies the address of the waveform data 33 stored previously in the waveform generating ROM 13. The waveform-generating ROM 13 stores waveform data 33 for each transmission power level and switches data in response to a power level control signal 17. When an address in the waveform-generating ROM 13 has been specified, the waveform data 33 at the specified address is input into the D/A converter 12 to output the waveform of the reference signal voltage 31. For the purpose of preventing the expansion of a spectrum caused by drastic changes in the waveform of the RF output signal 6, such as steep rises and falls that occur in the burst transmission mode, the counter 14 is controlled by the RAMP controller 15 upon input of the CLK signal at the start and end of transmission to generate the reference signal voltage 31 by means of which rises and falls in the waveform of the RF output signal 6 can be smoothened. Since there is an offset voltage in the comparator 9 used in the automatic control circuit for a transmission power amplifier of the prior art, undesirable charges are accumulated in the capacitor of the low-pass filter 10 at the time of non-transmission in the burst transmission mode. Such undesirable charges are accumulated in the capacitor especially when the automatic control circuit for a power amplifier is turned off at the time of non-transmission for the purpose of power saving. If transmission starts in this state, the gain control of the power amplifier 5 cannot be performed precisely as the response of the low-pass filter 10 is unstable, resulting in the occurrence of undesirable changes in the waveform of the RF output signal 6 such as deformed rises and overshoots. EP-A-261 967 discloses a partial solution to this problem, based on using, in place of the filter, an intergrator connected so as to memorise the last value of the gain control parameter between bursts.This solution may be satifactory if the next burst is transmitted at the same power level as the current burst. Summary of the Invention The present invention is intended to solve the above problem, and it is therefore an object of the invention to provide an automatic control circuit for a power amplifier which can effect an optimal and stable control of the transmission output even if an offset voltage or the like is generated in the comparator. According to a first aspect of the present invention, there is provided an automatic control circuit for a power amplifier which comprises means (initializing means 37) for initializing a low-pass filter (low-pass filter 10). According to a second aspect of the present invention, there is provided an automatic control circuit for a power amplifier wherein means for initializing a low-pass filter (low-pass filter 10) comprise a circuit for connecting a DC voltage source (DC voltage source 19) supplying an initial value to both ends of a capacitor (capacitor 21) constituting the low-pass filter (low-pass filter 10). According to a third aspect of the present invention, there is provided an automatic control circuit for a power amplifier wherein a low-pass filter (low-pass filter 10) comprises a capacitor (capacitor 21) located between the negative input terminal and the output terminal of a comparator (comparator 9) and initializing means (initializing means 37) comprise a switch (analog switch 35) for discharging the capacitor (capacitor 21). According to a fourth aspect of the invention, there is provided an automatic control circuit for a power amplifier which uses a digital filter (digital filter 26) as a low-pass filter for processing a digital signal in a CPU (CPU 24) and which comprises means (initializing means 37) for initializing the digital filter immediately before the start of transmission. In the first aspect of the invention, the low-pass filter (low-pass filter 10) is initialized immediately before the start of transmission. In the second aspect of the invention, the DC voltage source (DC voltage source 19) corresponding to an initial value is connected to both ends of the capacitor (capacitor 21) immediately before the start of transmission in order to initialize the low-pass filter (low-pass filter 10). In the third aspect of the invention, the low-pass filter (low-pass filter 10) comprises the capacitor (capacitor 21) located between the negative input terminal and the output terminal of the comparator (comparator 9) and is initialized by short-circuiting the capacitor (capacitor 21) with the switch (analog switch 35) immediately before the start of transmission. In the fourth aspect of the invention, the digital filter (digital filter 26) for processing a digital signal in the CPU (CPU 24) is used as a low-pass filter and initialized immediately before the start of transmission. The above and other objects, features and advantages of the invention will become more apparent from the following description of preferred embodiments when taken in conjunction with the accompanying drawings. Brief Description of the Drawings FIG. 1 is a diagram of an automatic control circuit for a power amplifier according to Embodiment 1 of the invention; FIG. 2 is a timing chart showing the switching control signal of Embodiment 1; FIG. 3 is a diagram of an automatic control circuit for a power amplifier according to Embodiment 2 of the invention; FIG. 4 is a diagram of an automatic control circuit for a power amplifier according to Embodiment 3 of the invention; FIG. 5 is a flow chart showing the signal processing of Embodiment 3; and FIG. 6 is a diagram of an automatic control circuit for a power amplifier of the prior art. Description of the Preferred Embodiments Embodiment 1 FIG. 1 shows an automatic control circuit for a power amplifier according to a first embodiment of the present invention. Reference numerals 1 to 17 and 31 to 33 designate the same components as in the prior art shown in FIG. 6, and, accordingly, their description is omitted. Reference numeral 18 represents a switch having a control terminal for selecting the formation of a low-pass filter or the connection of a capacitor 21 with a DC voltage source 19. Reference numeral 20 represents a switching control signal, and 34 is a resistor, the one end of which is connected to the switch 18 and the other end of which is connected to the comparator 9. Numeral 37 represents means for initializing the low-pass filter 10 which comprises the switch 18 for connecting the DC voltage source 19 supplying an initial value to both ends of the capacitor 21 which constitutes the low-pass filter 10. In the low-pass filter 10 structured as described above, the switch 18 is connected to the DC voltage source 19 for the purpose of preventing undesirable charges from being accumulated in the capacitor 21 by the offset voltage of the comparator 9 at the time of non-transmission, and the low-pass filter 10 is reset to an initial state during the non-transmission transmission period. Immediately before the start of the switch 18 is shifted reversely to the resistor 34 in the feedback route of the error voltage 32 of the automatic control circuit for a power amplifier so as to form the low-pass filter 10. The switch 18 is shifted in response to the switching control signal 20. FIG. 2 is a timing chart showing the relationships among burst operation, the switching control signal 20 and the state of the capacitor 21 of the low-pass filter 10. In the burst operation, the voltage of the capacitor 21 begins to rise gradually immediately after the change from transmission to non-transmission. However, as the switch 18 is connected to the DC voltage source 19 in response to the switching control signal 20, the charges of the capacitor 21 are discharged quickly. At the time of any further transmission, the switch 18 is switched and connected to the side for constructing the low-pass filter 10 in response to the switching control signal 20 and the low-pass filter 10 is in the initial state again. The same operation is performed repeatedly. Embodiment 2 FIG. 3 shows another embodiment of the invention wherein the low-pass filter 10 is connected to the comparator 9. Reference numeral 35 represents an analog switch which is inserted into the low-pass filter 10 parallel to the capacitor 21 and controlled by a discharge control signal 22. A resistor 36 is connected to both ends of the capacitor 21 and the low-pass filter 10 comprises the capacitor 21 located between the negative input terminal and the output terminal of the comparator 9. The initializing means 37 comprises the analog switch 35 which discharges any accumulated charges of the capacitor 21. The same components as those in the prior art have the same reference signs and their description is omitted. The following is a description of the operation of this second embodiment. When the automatic control circuit for a power amplifier is turned off at the time of non-transmission for the purpose of saving energy, electric charges are accumulated in the capacitor 21 of the low-pass filter 10 connected to the comparator 9. Therefore, changes such as deformations and overshoots can arise in the waveform of the RF output signal 6 in a similar way as in the prior art. To cope with this situation during burst operation, the analog switch 35 is closed in response to the discharge control signal 22 immediately before the start of transmission in order to discharge any accumulated charges by short-circuiting both ends of the capacitor 21. Thereby rises in the RF output signal 6 can be optimized and stabilised. The charges of the capacitor 21 are discharged in response to the discharge control signal 22 and its timing is the same as that of the switching control signal 20 shown in FIG. 2. That is, when the signal becomes "HI", the switch 35 is closed, and when the signal becomes "LO", the switch 35 is opened. Embodiment 3 FIG. 4 shows an automatic control circuit for a power amplifier wherein a low-pass filter is not realized by hardware, rather a digital signal is processed by a digital signal processor (DSP) in order to achieve the same function as a low-pass filter. Reference numeral 23 represents an A/D converter which converts the waveform of the RF output signal 6 detected by the detector 7 into a digital value. Reference numeral 24 represents a CPU forming the digital signal processor (DSP) for digitally processing the output of the A/D converter 23 together with the reference signal voltage 31 and including a digital filter 26. Reference numeral 25 designates a D/A converter for converting the output of the CPU 24 into an analog value to be supplied to a terminal 5a of the power amplifier 5. The same components as those in the prior art have the same reference signs and their description is omitted. The following is a description of the operation of this third embodiment with reference to the flow chart of FIG. 5. In Step 1, the state variable of the digital filter 26 is first initialized by the CPU 24, and in Step 2 it is checked, whether the state is transmission or not. If it is transmission, the process goes to Step 3 wherein the detected waveform is taken in by the A/D converter 23. The detected waveform data is compared with the waveform data of the reference signal voltage 31 in Step 4, and the error signal output thereafter is filtered by the initialized digital filter 26 in Step 6. Then, the filtered signal is converted into an analog value again by the D/A converter 25 in Step 6 to be fed back to the power amplifier 5. In Step 7, the process returns to Step 3 if transmission is not over, or to Step 1 to initialize the digital filter 26 if transmission is over. Thereby, the unspecified variable of the digital filter 26 is initialized immediately before the start of transmission, thus making it possible to eliminate any unstable response of the filter and to effect an optimal and stable rise in the waveform of the RF output signal 6. As described above, according to the first aspect of the invention, since the low-pass filter is initialized before transmission, it is possible to eliminate the accumulation of undesirable charges in the capacitor of the low-pass filter at the time of non-transmission during burst operation. Furthermore, when the automatic control circuit for a power amplifier is turned off at the time of non-transmission for the purpose of saving energy, it is also possible to eliminate the accumulation of undesirable charges in the capacitor. For this reason, an accurate gain control of the power amplifier is possible, and undesirable changes in the waveform of the RF output signal 6 such as deformed rises and overshoots can be eliminated. Moreover, even if an offset voltage or the like is generated in the comparator 9, an optimal and stable control of transmission output is ensured. According to the second aspect of the invention, since means for initializing the low-pass filter 10 consist of a circuit for connecting a DC voltage source 19 supplying an initial value to both ends of the capacitor 21 which constitutes the low-pass filter, an optimal and stable control of the transmission output is achieved. According to the third aspect of the invention, since the low-pass filter 10 comprises the capacitor 21 located between the negative input terminal and the output terminal of the comparator 9 and is initialized by short-circuiting the capacitor 21 with the switch 35, the optimal and stable control of transmission output is obtained. According to the fourth aspect of the invention, since the digital filter 26 for processing a digital signal in the CPU 24 is used as a low-pass filter and initialized immediately before the start of transmission, an optimal and stable control of the transmission output is ensured also in this case.

Claims: An automatic control circuit for a power amplifier comprising a power amplifier (5) for amplifying a radio frequency, a detector (7) for detecting the envelope waveform of a radio frequency output signal (6) amplified by the power amplifier, a comparator (9) for detecting the difference between the detected waveform and the waveform of a reference signal voltage (31) from a reference signal voltage generator (8), and a low-pass filter (10) for filtering the output of the comparator (9) to be supplied to the gain control terminal (5a) of the power amplifier (5), characterized in that the circuit further comprises means (37; 18, 19; 23-25) for initializing the low-pass filter (10). The control circuit according to claim 1, wherein the means (37) for initializing the low-pass filter (10) comprise a circuit (18, 19) for connecting a DC voltage source (19) supplying an initial value to both ends of a capacitor (21) which constitutes the low-pass filter (10). The control circuit according to claim 1, wherein the low-pass filter (10) comprises a capacitor (21) located between the negative input terminal and the output terminal of the comparator (9) and the means (37) for initializing the low-pass filter (10) comprise a switch (35) for discharging the capacitor (21). The control circuit according to claim 1, wherein the low-pass filter (10) comprises a capacitor (21) located between the negative input terminal and the output terminal of the comparator (9) and an analog switch (35) for discharging charges in the capacitor (21). An automatic control circuit for a power amplifier, comprising a power amplifier (5) and a detector (7) for detecting the envelope waveform of a radio frequency output signal (6) amplified by the power amplifier (5), such that the output signal of the detector (7) is processed as a digital signal through an A/D converter (23), a CPU and a D/A converter (25) and is fed back as a digital signal to the gain control terminal (5a) of the power amplifier (5), characterised in that the circuit uses a digital filter (26) as a low-pass filter for processing a digital signal in the CPU (24) and comprises means for initializing the digital filter (26) immediately before the start of transmission. The control circuit according to any of claims 1 to 4, wherein the reference signal voltage generator (8) comprises a D/A converter (12) for converting digital data into analog data in order to output a reference signal voltage (31), a ROM (33) for storing data to be supplied to the D/A converter (12), a counter (14) for specifying an address in the ROM (33), and a controller (15) for outputting a signal for controlling a transmission waveform at the start and end of a burst transmission to the counter (14).

Inventors: NAGANO HIROAKI, NAGANO, HIROAKI, NAGANO, HIROAKI, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H03G3
IPC codes: H04B1, H04B7, H03G3