Rotation register for orthogonal data transformation

Abstract: This invention is a rotation register (208) in a data processing apparatus (71). The data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. In the preferred embodiment the set of registers is dual ported and can be read from or written to via two data processor buses (103, 105, 107). The register selection circuit also permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers (200) are connected together in a loop (208). The most significant bit of each data register connected to the least significant bit of a sequential data register, with the last data register is connected to the first data register. In a register rotation mode the register selection circuit rotates bits in each data register in around the loop. In the preferred embodiment this rotation is by one bit upon each execution of a register rotation instruction. In the preferred embodiment of this invention, the rotation register (208) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.

Description: CROSS REFERENCE TO RELATED APPLICATIONS This application relates to improvements in the inventions disclosed in the following copending U.S. patent applications, all of which are assigned to Texas Instruments: U.S. Patent Application Serial No. 07/437,858 filed November 17, 1989, now U.S. Patent No. 5,212,777 issued May 18, 1993, and entitled "MULTI-PROCESSOR RECONFIGURABLE IN SINGLE INSTRUCTION MULTIPLE DATA (SIMD) AND MULTIPLE INSTRUCTION MULTIPLE DATA (MIMD) MODES AND METHOD OF OPERATION". U.S. Patent Application Serial No. 07/437,946 filed November 17, 1989, now U.S. Patent No. 5,197,140 issued March 23, 1993 and entitled "SLICED ADDRESSING MULTI-PROCESSOR AND METHOD OF OPERATION". U.S. Patent Application Serial No. 07/437,857 filed November 17, 1989, now U.S. Patent No. 5,339,447 issued August 16, 1994 and entitled "ONES COUNTING CIRCUIT, UTILIZING A MATRIX OF INTERCONNECTED HALF-ADDERS, FOR COUNTING THE NUMBER OF ONES IN A BINARY STRING OF IMAGE DATA". U.S. Patent Application Serial No. 07/437,851 filed November 17, 1989, now U.S. Patent No. 5,239,654 issued August 24, 1993 and entitled "DUAL MODE SIMD/MIMD PROCESSOR PROVIDING REUSE OF MIND INSTRUCTION MEMORIES AS DATA MEMORIES WHEN OPERATING IN SIMD MODE". U.S. Patent Application Serial No. 07/437,875 filed November 17, 1989, now U.S. Patent No. 5,226,125 issued July 6, 1993 and entitled "SWITCH MATRIX HAVING INTEGRATED CROSSPOINT LOGIC AND METHOD OF OPERATION". TECHNICAL FIELD OF THE INVENTION The technical field of this invention is the field of digital data processing and more particularly microprocessor circuits, architecture and method for digital data processing especially digital image/graphics processing. BACKGROUND OF THE INVENTION This invention relates to the field of computer graphics and in particular to bit mapped graphics. In bit mapped graphics computer memory stores data for each individual picture element or pixel of an image at memory locations that correspond to the location of that pixel within the image. This image may be an image to be displayed or a captured image to be manipulated, stored, displayed or retransmitted. The field of bit mapped computer graphics has benefited greatly from the lowered cost and increased capacity of dynamic random access memory (DRAM) and the lowered cost and increased processing power of microprocessors. These advantageous changes in the cost and performance of component parts enable larger and more complex computer image systems to be economically feasible. The field of bit mapped graphics has undergone several stages in evolution of the types of processing used for image data manipulation. Initially a computer system supporting bit mapped graphics employed the system processor for all bit mapped operations. This type of system suffered several drawbacks. First, the computer system processor was not particularly designed for handling bit mapped graphics. Design choices that are very reasonable for general purpose computing are unsuitable for bit mapped graphics systems. Consequently some routine graphics tasks operated slowly. In addition, it was quickly discovered that the processing needed for image manipulation of bit mapped graphics was so loading the computational capacity of the system processor that other operations were also slowed. The next step in the evolution of bit mapped graphics processing was dedicated hardware graphics controllers. These devices can draw simple figures, such as lines, ellipses and circles, under the control of the system processor. Many of these devices can also do pixel block transfers (PixBlt). A pixel block transfer is a memory move operation of image data from one portion of memory to another. A pixel block transfer is useful for rendering standard image elements, such as alphanumeric characters in a particular type font, within a display by transfer from nondisplayed memory to bit mapped display memory. This function can also be used for tiling by transferring the same small image to the whole of bit mapped display memory. The built-in algorithms for performing some of the most frequently used graphics functions provide a way of improving system performance. However, a useful graphics computer system often requires many functions besides those few that are implemented in such a hardware graphics controller. These additional functions must be implemented in software by the system processor. Typically these hardware graphics controllers allow the system processor only limited access to the bit map memory, thereby limiting the degree to which system software can augment the fixed set of functions of the hardware graphics controller. The graphics system processor represents yet a further step in the evolution of bit mapped graphics processing. A graphics system processor is a programmable device that has all the attributes of a microprocessor and also includes special functions for bit mapped graphics. The TMS34010 and TMS34020 graphics system processors manufactured by Texas Instruments Incorporated represent this class of devices. These graphics system processors respond to a stored program in the same manner as a microprocessor and include the capability of data manipulation via an arithmetic logic unit, data storage in register files and control of both program flow and external data memory. In addition, these devices include special purpose graphics manipulation hardware that operate under program control. Additional instructions within the instruction set of these graphics system processors controls the special purpose graphics hardware. These instructions and the hardware that supports them are selected to perform base level graphics functions that are useful in many contexts. Thus a graphics system processor can be programmed for many differing graphics applications using algorithms selected for the particular problem. This provides an increase in usefulness similar to that provided by changing from hardware controllers to programmed microprocessors. Because such graphics system processors are programmable devices in the same manner as microprocessors, they can operate as stand alone graphics processors, graphics co-processors slaved to a system processor or tightly coupled graphics controllers. New applications are driving the desire to provide more powerful graphics functions. Several fields require more cost effective graphics operations to be economically feasible. These include video conferencing, multi-media computing with full motion video, high definition television, color facsimile and digital photography. Each of these fields presents unique problems, but image data compression and decompression are common themes. The amount of transmission bandwidth and the amount of storage capacity required for images and particular full motion video is enormous. Without efficient video compression and decompression that result in acceptable final image quality, these applications will be limited by the costs associated with transmission bandwidth and storage capacity. There is also a need in the art for a single system that can support both image processing functions such as image recognition and graphics functions such as display control. In U.S. Patent No. 3,588,483, a data processor having a plurality of register stages which may be selectively interconnected to effect a plurality of operations is disclosed. In one disclosed operation, data can be rotated through the register stages in either direction. In one embodiment, data may be loaded into the data processor either as serial data bits shifted into the data processor from either end or as a parallel data word. SUMMARY OF THE INVENTION This invention is a rotation register in a data processing apparatus. The data processing apparatus includes a data processor bus, the rotation register and a register selection circuit. The rotation register is embodied by a plurality of data registers each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. In the preferred embodiment the set of registers is dual ported and can be read from or written to via two data processor buses. The register selection circuit also permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers may be connected together in a loop. The most significant bit of each data register may be connected to the least significant bit of a sequential data register. The most significant bit of the last data register may be connected to the least significant bit of the first data register. In a register rotation mode the register selection circuit may rotate bits in each data register in around the loop. In the preferred embodiment this rotation is by one bit upon each execution of a register rotation instruction. The data processing apparatus preferably operates from a source of instructions. An instruction decode logic connected to the source of instructions controls the register selection circuit. This control includes: entering the normal register read mode and selecting an instruction specified data register in response to a normal register read mode instruction; entering the normal register write mode and selecting an instruction specified data register in response to a normal register write mode instruction; entering the rotation register read mode and selecting the noncontiguous bits in response to a rotation register read mode instruction; entering the rotation register write mode and selecting the noncontiguous bits in response to a rotation register write mode instruction; and entering the register rotation mode and rotating the bits in each data register in the loop in response to a register rotation instruction. In the preferred embodiment the plural data registers include 32 bit registers having 4 sections of 8 bits each. In the preferred embodiment of this invention, the rotation register is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing. BRIEF DESCRIPTION OF THE FIGURES These and other aspects of the present invention are described below together with the Figures, in which: Figure 1 illustrates the system architecture of an image processing system such as would employ this invention; Figure 2 illustrates the architecture of a single integrated circuit multiprocessor that forms the preferred embodiment of this invention; Figure 3 illustrates in block diagram form one of the digital image/graphics processors illustrated in Figure 2; Figure 4 illustrates in schematic form the pipeline stages of operation of the digital image/graphics processor illustrated in Figure 2; Figure 5 illustrates in block diagram form the data unit of the digital image/graphics processors illustrated in Figure 3; Figure 6 illustrates in schematic form field definitions of the status register of the data unit illustrated in Figure 5; Figure 7 illustrates in block diagram form the manner of splitting the arithmetic logic unit of the data unit illustrated in Figure 5; Figure 8 illustrates in block diagram form the manner of addressing the data register of the data unit illustrated in Figure 5 as a rotation register; Figure 9 illustrates in schematic form the field definitions of the first data register of the data unit illustrated in Figure 5; Figure 10 illustrates in block diagram form the construction of one bit circuit of the arithmetic logic unit of the data unit illustrated in Figure 5; Figure 11 illustrates in schematic form the construction of the resultant logic and carry out logic of the bit circuit illustrated in Figure 10; Figure 12 illustrates in schematic form the construction of the Boolean function generator of the bit circuit illustrated in Figure 10; Figure 13 illustrates in block diagram form the function signal selector of the function signal generator of the data unit illustrated in Figure 5; Figure 14 illustrates in block diagram form the function signal modifier portion of the function signal generator of the data unit illustrated in Figure 5; Figure 15 illustrates in block diagram form the bit 0 carry-in generator of the data unit illustrated in Figure 5; Figure 16 illustrates in block diagram form a conceptual view of the arithmetic logic unit illustrated in Figures 10 and 11; Figure 17 illustrates in block diagram form a conceptual view of an alternative embodiment of the arithmetic logic unit; Figure 18 illustrates in schematic form the instruction word controlling the operation of the digital image/graphics processor illustrated in Figure 3; and Figure 19 illustrates in schematic form the multiprocessor integrated circuit of this invention having a single digital image/graphics processor in color facsimile system. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 is a block diagram of an image data processing system including a multiprocessor integrated circuit constructed for image and graphics processing according to this invention. This data processing system includes a host processing system 1. Host processing system 1 provides the data processing for the host system of data processing system of Figure 1. Included in the host processing system 1 are a processor, at least one input device, a long term storage device, a read only memory, a random access memory and at least one host peripheral 2 coupled to a host system bus. Arrangement and operation of the host processing system are considered conventional. Because of its processing functions, the host processing system 1 controls the function of the image data processing system. Multiprocessor integrated circuit 100 provides most of the data processing including data manipulation and computation for image operations of the image data processing system of Figure 1. Multiprocessor integrated circuit 100 is bi-directionally coupled to an image system bus and communicates with host processing system 1 by way of this image system bus. In the arrangement of Figure 1, multiprocessor integrated circuit 100 operates independently from the host processing system 1. The multiprocessor integrated circuit 100, however, is responsive to host processing system 1. Figure 1 illustrates two image systems. Imaging device 3 represents a document scanner, charge coupled device scanner or video camera that serves as an image input device. Imagine device 3 supplies this image to image capture controller 4, which serves to digitize the image and form it into raster scan frames. This frame capture process is controlled by signals from multiprocessor integrated circuit 100. The thus formed image frames are stored in video random access memory 5. Video random access memory 5 may be accessed via the image system bus permitting data transfer for image processing by multiprocessor integrated circuit 100. The second image system drives a video display. Multiprocessor integrated circuit 100 communicates with video random access memory 6 for specification of a displayed image via a pixel map. Multiprocessor integrated circuit 100 controls the image data stored in video random access memory 6 via the image system bus. Data corresponding to this image is recalled from video random access memory 6 and supplied to video palette 7. Video palette 7 may transform this recalled data into another color space, expand the number of bits per pixel and the like. This conversion may be accomplished through a look-up table. Video palette 7 also generates the proper video signals to drive video display 8. If these video signals are analog signals, then video palette 7 includes suitable digital to analog conversion. The video level signal output from the video palette 7 may include color, saturation, and brightness information. Multiprocessor integrated circuit 100 controls data stored within the video palette 7, thus controlling the data transformation process and the timing of image frames. Multiprocessor integrated circuit 100 can control the line length and the number of lines per frame of the video display image, the synchronization, retrace, and blanking signals through control of video palette 7. Significantly, multiprocessor integrated circuit 100 determines and controls where graphic display information is stored in the video random access memory 6. Subsequently, during readout from the video random access memory 6, multiprocessor integrated circuit 100 determines the readout sequence from the video random access memory 6, the addresses to be accessed, and control information needed to produce the desired graphic image on video display 8. Video display 8 produces the specified video display for viewing by the user. There are two widely used techniques. The first technique specifies video data in terms of color, hue, brightness, and saturation for each pixel. For the second technique, color levels of red, blue and green are specified for each pixel. Video palette 7 the video display 8 is designed and fabricated to be compatible with the selected technique. Figure 1 illustrates an addition memory 9 coupled to the image system bus. This additional memory may include additional video random access memory, dynamic random access memory, static random access memory or read only memory. Multiprocessor integrated circuit 100 may be controlled either in wholly or partially by a program stored in the memory 9. This memory 9 may also store various types of graphic image data. In addition, multiprocessor integrated circuit 100 preferably includes memory interface circuits for video random access memory, dynamic random access memory and static random access memory. Thus a system could be constructed using multiprocessor integrated circuit 100 without any video random access memory 5 or 6. Figure 1 illustrates transceiver 16. Transceiver 16 provides translation and bidirectional communication between the image system bus and a communications channel. One example of a system employing transceiver 16 is video conferencing. The image data processing system illustrated in Figure 1 employs imaging device 3 and image capture controller 4 to form a video image of persons at a first location. Multiprocessor integrated circuit 100 provides video compression and transmits the compressed video signal to a similar image data processing system at another location via transceiver 16 and the communications channel. Transceiver 16 receives a similarly compressed video signal from the remote image data processing system via the communications channel. Multiprocessor integrated circuit 100 decompresses this received signal and controls video random access memory 6 and video palette 7 to display the corresponding decompressed video signal on video display 8. Note this is not the only example where the image data processing system employs transceiver 16. Also note that the bidirectional communications need not be the same type signals. For example, in an interactive cable television signal the cable system head in would transmit compressed video signals to the image data processing system via the communications channel. The image data processing system could transmit control and data signals back to the cable system head in via transceiver 16 and the communications channel. Figure 1 illustrates multiprocessor integrated circuit 100 embodied in a system including host processing system 1. Those skilled in the art would realize from the following disclosure of the invention that multiprocessor integrated circuit 100 may be employed as the only processor of a useful system. In such a system multiprocessor integrated circuit 100 is programmed to perform all the functions of the system. This invention is particularly useful in a processor used for image processing. According to the preferred embodiment, this invention is embodied in multiprocessor integrated circuit 100. This preferred embodiment includes plural identical processors that embody this invention. Each of these processors will be called a digital image/graphics processor. This description is a matter of convenience only. The processor embodying this invention can be a processor separately fabricated on a single integrated circuit or a plurality of integrated circuits. If embodied on a single integrated circuit, this single integrated circuit may optionally also include read only memory and random access memory used by the digital image/graphics processor. Figure 2 illustrates the architecture of the multiprocessor integrated circuit 100 of the preferred embodiment of this invention. Multiprocessor integrated circuit 100 includes: two random access memories 10 and 20, each of which is divided into plural sections; crossbar 50; master processor 60; digital image/graphics processors 71, 72, 73 and 74; transfer controller 80, which mediates access to system memory; and frame controller 90, which can control access to independent first and second image memories. Multiprocessor integrated circuit 100 provides a high degree of operation parallelism, which will be useful in image processing and graphics operations, such as in the multi-media computing. Multiprocessor integrated circuit 100 includes two random access memories. Random access memory 10 is primarily devoted to master processor 60. It includes two instruction cache memories 11 and 12, two data cache memories 13 and 14 and a parameter memory 15. These memory sections can be physically identical, but connected and used differently. Random access memory 20 may be accessed by master processor 60 and each of the digital image/graphics processors 71, 72, 73 and 74. Each digital image/graphics processor 71, 72, 73 and 74 has five corresponding memory sections. These include an instruction cache memory, three data memories and one parameter memory. Thus digital image/graphics processor 71 has corresponding instruction cache memory 21, data memories 22, 23, 24 and parameter memory 25; digital image/graphics processor 72 has corresponding instruction cache memory 26, data memories 27, 28, 29 and parameter memory 30; digital image/graphics processor 73 has corresponding instruction cache memory 31, data memories 32, 33, 34 and parameter memory 35; and digital image/graphics processor 74 has corresponding instruction cache memory 36, data memories 37, 38, 39 and parameter memory 40. Like the sections of random access memory 10, these memory sections can be physically identical but connected and used differently. Each of these memory sections of memories 10 and 20 preferably includes 2 K bytes, with a total memory within multiprocessor integrated circuit 100 of 50 K bytes. Multiprocessor integrated circuit 100 is constructed to provide a high rate of data transfer between processors and memory using plural independent parallel data transfers. Crossbar 50 enables these data transfers. Each digital image/graphics processor 71, 72, 73 and 74 has three memory ports that may operate simultaneously each cycle. An instruction port (I) may fetch 64 bit data words from the corresponding instruction cache. A local data port (L) may read a 32 bit data word from or write a 32 bit data word into the data memories or the parameter memory corresponding to that digital image/graphics processor. A global data port (G) may read a 32 bit data word from or write a 32 bit data word into any of the data memories or the parameter memories or random access memory 20. Master Processor 60 includes two memory ports. An instruction port (I) may fetch a 32 bit instruction word from either of the instruction caches 11 and 12. A data port (C) may read a 32 bit data word from or write a 32 bit data word into data caches 13 or 14, parameter memory 15 of random access memory 10 or any of the data memories or parameter memories of random access memory 20. Transfer controller 80 can access any of the sections of random access memory 10 or 20 via data port (C). Thus fifteen parallel memory accesses may be requested at any single memory cycle. Random access memories 10 and 20 are divided into 25 memories in order to support so many parallel accesses. Crossbar 50 controls the connections of master processor 60, digital image/graphics processors 71, 72, 73 and 74, and transfer controller 80 with memories 10 and 20. Crossbar 50 includes a plurality of crosspoints 51 disposed in rows and columns. Each column of crosspoints 51 corresponds to a single memory section and a corresponding range of addresses. A processor requests access to one of the memory sections through the most significant bits of an address output by that processor. This address output by the processor travels along a row. The crosspoint 51 corresponding to the memory section having that address responds either by granting or denying access to the memory section. If no other processor has requested access to that memory section during the current memory cycle, then the crosspoint 51 grants access by coupling the row and column. This supplies the address to the memory section. The memory section responds by permitting data access at that address. This data access may be either a data read operation or a data write operation. If more than one processor requests access to the same memory section simultaneously, then crossbar 50 grants access to only one of the requesting processors. The crosspoints 51 in each column of crossbar 50 communicate and grant access based upon a priority hierarchy. If two requests for access having the same rank occur simultaneously, then crossbar 50 grants access on a round robin basis, with the processor last granted access having the lowest priority. Each granted access lasts as long as needed to service the request. The processors may change their addresses every memory cycle, so crossbar 50 can change the interconnection between the processors and the memory sections on a cycle by cycle basis. Master processor 60 preferably performs the major control functions for multiprocessor integrated circuit 100. Master processor 60 is preferably a 32 bit reduced instruction set computer (RISC) processor including a hardware floating point calculation unit. According to the RISC architecture, all accesses to memory are performed with load and store instructions and most integer and logical operations are performed on registers in a single cycle. The floating point calculation unit, however, will generally take several cycles to perform operations when employing the same register file as used by the integer and logical unit. A register score board ensures that correct register access sequences are maintained. The RISC architecture is suitable for control functions in image processing. The floating point calculation unit permits rapid computation of image rotation functions, which may be important to image processing. Master processor 60 fetches instruction words from instruction cache memory 11 or instruction cache memory 12. Likewise, master processor 60 fetches data from either data cache 13 or data cache 14. Since each memory section includes 2 K bytes of memory, there is 4 K bytes of instruction cache and 4 K bytes of data cache. Cache control is an integral function of master processor 60. As previously mentioned, master processor 60 may also access other memory sections via crossbar 50. The four digital image/graphics processors 71, 72, 73 and 74 each have a highly parallel digital signal processor (DSP) architecture. Figure 3 illustrates an overview of exemplary digital image/graphics processor 71, which is identical to digital image/graphics processors 72, 73 and 74. Digital image/graphics processor 71 achieves a high degree of parallelism of operation employing three separate units: data unit 110; address unit 120; and program flow control unit 130. These three units operate simultaneously on different instructions in an instruction pipeline. In addition each of these units contains internal parallelism. The digital image/graphics processors 71, 72, 73 and 74 can execute independent instruction streams in the multiple instruction multiple data mode (MIMD). In the MIMD mode, each digital image/graphics processor executes an individual program from its corresponding instruction cache, which may be independent or cooperative. In the latter case crossbar 50 enables inter-processor communication in combination with the shared memory. Digital image/graphics processors 71, 72, 73 and 74 may also operate in a synchronized MIMD mode. In the synchronized MIMD mode, the program control flow unit 130 of each digital image/graphics processor inhibits fetching the next instruction until all synchronized processors are ready to proceed. This synchronized MIMD mode allows the separate programs of the digital image/graphics processors to be executed in lock step in a closely coupled operation. Digital image/graphics processors 71, 72, 73 and 74 can execute identical instructions on differing data in the single instruction multiple data mode (SIMD). In this mode a single instruction stream for the four digital image/graphics processors comes from instruction cache memory 21. Digital image/graphics processor 71 controls the fetching and branching operations and crossbar 50 supplies the same instruction to the other digital image/graphics processors 72, 73 and 74. Since digital image/graphics processor 71 controls instruction fetch for all the digital image/graphics processors 71, 72, 73 and 74, the digital image/graphics processors are inherently synchronized in the SIMD mode. Transfer controller 80 is a combined direct memory access (DMA) machine and memory interface for multiprocessor integrated circuit 100. Transfer controller 80 intelligently queues, sets priorities and services the data requests and cache misses of the five programmable processors. Master processor 60 and digital image/graphics processors 71, 72, 73 and 74 all access memory and systems external to multiprocessor integrated circuit 100 via transfer controller 80. Data cache or instruction cache misses are automatically handled by transfer controller 80. The cache service (S) port transmits such cache misses to transfer controller 80. Cache service port (S) reads information from the processors and not from memory. Master processor 60 and digital image/graphics processors 71, 72, 73 and 74 may request data transfers from transfer controller 80 as linked list packet requests. These linked list packet requests allow multi-dimensional blocks of information to be transferred between source and destination memory addresses, which can be within multiprocessor integrated circuit 100 or external to multiprocessor integrated circuit 100. Transfer controller 80 preferably also includes a refresh controller for dynamic random access memory (DRAM) which require periodic refresh to retain their data. Frame controller 90 is the interface between multiprocessor integrated circuit 100 and external image capture and display systems. Frame controller 90 provides control over capture and display devices, and manages the movement of data between these devices and memory automatically. To this end, frame controller 90 provides simultaneous control over two independent image systems. These would typically include a first image system for image capture and a second image system for image display, although the application of frame controller 90 is controlled by the user. These image systems would ordinarily include independent frame memories used for either frame grabber or frame buffer storage. Frame controlled 90 preferably operates to control video dynamic random access memory (VRAM) through refresh and shift register control. Multiprocessor integrated circuit 100 is designed for large scale image processing. Master processor 60 provides embedded control, orchestrating the activities of the digital image/graphics processors 71, 72, 73 and 74, and interpreting the results that they produce. Digital image/graphics processors 71, 72, 73 and 74 are well suited to pixel analysis and manipulation. If pixels are thought of as high in data but low in information, then in a typical application digital image/graphics processors 71, 72, 73 and 74 might well examine the pixels and turn the raw data into information. This information can then be analyzed either by the digital image/graphics processors 71, 72, 73 and 74 or by master processor 60. Crossbar 50 mediates inter-processor communication. Crossbar 50 allows multiprocessor integrated circuit 100 to be implemented as a shared memory system. Message passing need not be a primary form of communication in this architecture. However, messages can be passed via the shared memories. Each digital image/graphics processor, the corresponding section of crossbar 50 and the corresponding sections of memory 20 have the same width. This permits architecture flexibility by accommodating the addition or removal of digital image/graphics processors and corresponding memory modularly while maintaining the same pin out. In the preferred embodiment all parts of multiprocessor integrated circuit 100 are disposed on a single integrated circuit. In the preferred embodiment, multiprocessor integrated circuit 100 is formed in complementary metal oxide semiconductor (CMOS) using feature sizes of 0.6 µm. Multiprocessor integrated circuit 100 is preferably constructed in a pin grid array package having 256 pins. The inputs and outputs are preferably compatible with transistor-transistor logic (TTL) logic voltages. Multiprocessor integrated circuit 100 preferably includes about 3 million transistors and employs a clock rate of 50M Hz. Figure 3 illustrates an overview of exemplary digital image/graphics processor 71, which is virtually identical to digital image/graphics processors 72, 73 and 74. Digital image/graphics processor 71 includes: data unit 110; address unit 120; and program flow control unit 130. Data unit 110 performs the logical or arithmetic data operations. Data unit 110 includes eight data registers D7-D0, a status register 210 and a multiple flags register 211. Address unit 120 controls generation of load/store addresses for the local data port and the global data port. As will be further described below, address unit 120 includes two virtually identical addressing units, one for local addressing and one for global addressing. Each of these addressing units includes an all "0" read only register enabling absolute addressing in a relative address mode, a stack pointer, five address registers and three index registers. The addressing units share a global bit multiplex control register used when forming a merging address from both address units. Program flow control unit 130 controls the program flow for the digital image/graphics processor 71 including generation of addresses for instruction fetch via the instruction port. Program flow control unit 130 includes; a program counter PC 701; an instruction pointer-address stage IRA 702 that holds the address of the instruction currently in the address pipeline stage; an instruction pointer-execute stage IRE 703 that holds the address of the instruction currently in the execute pipeline stage; an instruction pointer-return from subroutine IPRS 704 holding the address for returns from subroutines; a set of registers controlling zero overhead loops; four cache tag registers TAG3-TAG0 collectively called 708 that hold the most significant bits of four blocks of instruction words in the corresponding instruction cache memory. Digital image/graphics processor 71 operates on a three stage pipeline as illustrated in Figure 4. Data unit 110, address unit 120 and program flow control unit 130 operate simultaneously on different instructions in an instruction pipeline. The three stages in chronological order are fetch, address and execute. Thus at any time, digital image/graphics processor 71 will be operating on differing functions of three instructions. The phrase pipeline stage is used instead of referring to clock cycles, to indicate that specific events occur when the pipeline advances, and not during stall conditions. Program flow control unit 130 performs all the operations that occur during the fetch pipeline stage. Program flow control unit 130 includes a program counter, loop logic, interrupt logic and pipeline control logic. During the fetch pipeline stage, the next instruction word is fetched from memory. The address contained in the program counter is compared with cache tag registers to determine if the next instruction word is stored in instruction cache memory 21. Program flow control unit 130 supplies the address in the program counter to the instruction port address bus 131 to fetch this next instruction word from instruction cache memory 21 if present. Crossbar 50 transmits this address to the corresponding instruction cache, here instruction cache memory 21, which returns the instruction word on the instruction bus 132. Otherwise, a cache miss occurs and transfer controller 80 accesses external memory to obtain the next instruction word. The program counter is updated. If the following instruction word is at the next sequential address, program control flow unit 130 post increments the program counter. Otherwise, program control flow unit 130 loads the address of the next instruction word according to the loop logic or software branch. If the synchronized MIMD mode is active, then the instruction fetch waits until all the specified digital image/graphics processors are synchronized, as indicated by sync bits in a communications register. Address unit 120 performs all the address calculations of the address pipeline stage. Address unit 120 includes two independent address units, one for the global port and one for the local port. If the instruction calls for one or two memory accesses, then address unit 120 generates the address(es) during the address pipeline stage. The address(es) are supplied to crossbar 50 via the respective global port address bus 121 and local port address bus 122 for contention detection/prioritization. If there is no contention, then the accessed memory prepares to allow the requested access, but the memory access occurs during the following execute pipeline stage. Data unit 110 performs all of the logical and arithmetic operations during the execute pipeline stage. All logical and arithmetic operations and all data movements to or from memory occur during the execute pipeline stage. The global data port and the local data port complete any memory accesses, which are begun during the address pipeline stage, during the execute pipeline stage. The global data port and the local data port perform all data alignment needed by memory stores, and any data extraction and sign extension needed by memory loads. If the program counter is specified as a data destination during any operation of the execute pipeline stage, then a delay of two instructions is experienced before any branch takes effect. The pipelined operation requires this delay, since the next two instructions following such a branch instruction have already been fetched. According to the practice in RISC processors, other useful instructions may be placed in the two delay slot positions. Digital image/graphics processor 71 includes three internal 32 bit data busses. These are local port data bus Lbus 103, global port source data bus Gsrc 105 and global port destination data bus Gdst 107. These three buses interconnect data unit 110, address unit 120 and program flow control unit 130. These three buses are also connected to a data port unit 140 having a local port 141 and global port 145. Data port unit 140 is coupled to crossbar 50 providing memory access. Local data port 141 has a buffer 142 for data stores to memory. A multiplexer/buffer circuit 143 loads data onto Lbus 103 from local port data bus 144 from memory via crossbar 50, from a local port address bus 122 or from global port data bus 148. Local port data bus Lbus 103 thus carries 32 bit data that is either register sourced (stores) or memory sourced (loads). Advantageously, arithmetic results in address unit 120 can be supplied via local port address bus 122, multiplexer buffer 143 to local port data bus Lbus 103 to supplement the arithmetic operations of data unit 110. This will be further described below. Buffer 142 and multiplexer buffer 143 perform alignment and extraction of data. Local port data bus Lbus 103 connects to data registers in data unit 110. A local bus temporary holding register LTD 104 is also connected to local port data Lbus 103. Global port source data bus Gsrc 105 and global port destination data bus Gdst 107 mediate global data transfers. These global data transfers may be either memory accesses, register to register moves or command word transfers between processors. Global port source data bus Gsrc 105 carries 32 bit source information of a global port data transfer. The data source can be any of the registers of digital image/graphics processor 71 or any data or parameter memory corresponding to any of the digital image/graphics processors 71, 72, 73 or 74. The data is stored to memory via the global port 145. Multiplexer buffer 146 selects lines from local port data Lbus 103 or global port source data bus Gsrc 105, and performs data alignment. Multiplexer buffer 146 writes this data onto global port data bus 148 for application to memory via crossbar 50. Global port source data bus Gsrc 105 also supplies data to data unit 110, allowing the data of global port source data bus Gsrc 105 to be used as one of the arithmetic logic unit sources. This latter connection allows any register of digital image/graphics processor 71 to be a source for an arithmetic logic unit operation. Global port destination data bus Gdst 107 carries 32 bit destination data of a global bus data transfer. The destination is any register of digital image/graphics processor 71. Buffer 147 in global port 145 sources the data of global port destination data bus Gdst 107. Buffer 147 performs any needed data extraction and sign extension operations. This buffer 147 operates if the data source is memory, and a load is thus being performed. The arithmetic logic unit result serves as an alternative data source for global port destination data bus Gdst 107. This allows any register of digital image/graphics processor 71 to be the destination of an arithmetic logic unit operation. A global bus temporary holding register GTD 108 is also connected to global port destination data bus Gdst 107. Circuitry including multiplexer buffers 143 and 146 connect between global port source data bus Gsrc 105 and global port destination data bus Gdst 107 to provide register to register moves. This allows a read from any register of digital image/graphics processor 71 onto global port source data bus Gsrc 105 to be written to any register of digital image/graphics processor 71 via global port destination data bus Gdst 107. Note that it is advantageously possible to perform a load of any register of digital image/graphics processor 71 from memory via global port destination data bus Gdst 107, while simultaneously sourcing the arithmetic logic unit in data unit 110 from any register via global port source data bus Gsrc 105. Similarly, it is advantageously possible to store the data in any register of digital image/graphics processor 71 to memory via global port source data bus Gsrc 105, while saving the result of an arithmetic logic unit operation to any register of digital image/graphics processor 71 via global port destination data bus Gdst 107. The usefulness of these data transfers will be further detailed below. Program flow control unit 130 receives the instruction words fetched from instruction cache memory 21 via instruction bus 132. This fetched instruction word is advantageously stored in two 64 bit instruction registers designated instruction register-address stage IRA 751 and instruction register-execute stage IRE 752. Each of the instruction registers IRA and IRE have their contents decoded and distributed. Digital image/graphics processor 71 includes opcode bus 133 that carries decoded or partially decoded instruction contents to data unit 110 and address unit 120. As will be later described, an instruction word may include a 32 bit, a 15 bit or a 3 bit immediate field. Program flow control unit 130 routes such an immediate field to global port source data bus Gsrc 105 for supply to its destination. Digital image/graphics processor 71 includes three address buses 121, 122 and 131. Address unit 120 generates addresses on global port address bus 121 and local port address bus 122. As will be further detailed below, address unit 120 includes separate global and local address units, which provide the addresses on global port address bus 121 and local port address bus 122, respectively. Note that local address unit 620 may access memory other than the data memory corresponding to that digital image/graphics processor. In that event the local address unit access is via global port address bus 121. Program flow control unit 130 sources the instruction address on instruction port address bus 131 from a combination of address bits from a program counter and cache control logic. These address buses 121, 122 and 131 each carry address, byte strobe and read/write information. Figure 5 illustrates details of data unit 110. It should be understood that Figure 5 does not illustrate all of the connections of data unit 110. In particular various control lines and the like have been omitted for the sake of clarity. Therefore Figure 5 should be read with the following description for a complete understanding of the operation of data unit 110. Data unit 110 includes a number of parts advantageously operating in parallel. Data unit 110 includes eight 32 bit data registers 200 designated D7-D0. Data register D0 may be used as a general purpose register but in addition has special functions when used with certain instructions. Data registers 200 include multiple read and write ports connected to data unit buses 201 to 206 and to local port data bus Lbus 103, global port source data bus Gsrc 105 and global port destination data bus Gdst 107. Data registers 200 may also be read "sideways" in a manner described as a rotation register that will be further described below. Data unit 110 further includes a status register 210 and a multiple flags register 211, which stores arithmetic logic unit resultant status for use in certain instructions. Data unit 110 includes as its major computational components a hardware multiplier 220 and a three input arithmetic logic unit 230. Lastly, data unit 110 includes: multiplier first input bus 201, multiplier second input bus 202, multiplier destination bus 203, arithmetic logic unit destination bus 204, arithmetic logic unit first input bus 205, arithmetic logic unit second input bus 206; buffers 104, 106, 108 and 236; multiplexers Rmux 221, Imux 222, MSmux 225, Bmux 227, Amux 232, Smux 231, Cmux 233 and Mmux 234; and product left shifter 224, adder 226, barrel rotator 235, LMO/RMO/LMBC/RMBC circuit 237, expand circuit 238, mask generator 239, input A bus 241, input B bus 242, input C bus 243, rotate bus 244, function signal generator 245, bit 0 carry-in generator 246, and instruction decode logic 250, all of which will be further described below. The following description of data unit 110 as well as further descriptions of the use of each digital image/graphics processor 71, 72, 73 and 74 employ several symbols for ease of expression. Many of these symbols are standard mathematical operations that need no explanation. Some are logical operations that will be familiar to one skilled in the art, but whose symbols may be unfamiliar. Lastly, some symbols refer to operations unique to this invention. Table 1 lists some of these symbols and their corresponding operation. Symbol Operation ∼ bit wise NOT & bit wise AND | bit wise OR ^ bit wise exclusive OR @ multiple flags register expand % mask generation %! modified mask generation \\ rotate left << shift left >>u shift right zero extend >>s shift right sign extend >> shift right sign extend default case ∥ parallel operation *(A±X) memory contents at address base register A ± index register X or offset X &*(A±X) address unit arithmetic address base register A ± index register X or offset X *(A±[X]) memory contents at address base register A ± scaled index register X or offset X The implications of the operations listed above in Table 1 may not be immediately apparent. These will be explained in detail below. Figure 6 illustrates the field definitions for status register 210. Status register 210 may be read from via global port source data bus Gsrc 105 or written into via global port destination data bus Gdst bus 107. In addition, status register 210 may write to or load from a specified one of data registers 200. Status register 210 is employed in control of operations within data unit 110. Status register 210 stores four arithmetic logic unit result status bits "N", "C", "V" and "Z". These are individually described below, but collectively their setting behavior is as follows. Note that the instruction types listed here will be fully described below. For instruction words including a 32 bit immediate fields, if the condition code field is "unconditional" then all four status bits are set according to the result of arithmetic logic unit 230. If the condition code field specifies a condition other than "unconditional", then no status bits are set, whether or not the condition is true. For instruction words not including a 32 bit immediate field operations and not including conditional operations fields, all status bits are set according to the result of arithmetic logic unit 230. For instruction words not including a 32 bit immediate field that permit conditional operations, if the condition field is "unconditional", or not "unconditional" and the condition is true, instruction word bits 28-25 indicate which status bits should be protected. All unprotected bits are set according to the result of arithmetic logic unit 230. For instruction words not including a 32 bit immediate field, which allow conditional operations, if the condition field is not "unconditional" and the condition is false, no status bits are set. There is no difference in the status setting behavior for Boolean operations and arithmetic operations. As will be further explained below, this behavior, allows the conditional instructions and source selection to perform operations that would normally require a branch. The arithmetic logic unit result bits of status register 210 are as follows. The "N" bit (bit 31) stores an indication of a negative result. The "N" bit is set to "1" if the result of the last operation of arithmetic logic unit 230 was negative. This bit is loaded with bit 31 of the result. In a multiple arithmetic logic unit operation, which will be explained below, the "N" bit is set to the AND of the zero compares of the plural sections of arithmetic logic unit 230. In a bit detection operation performed by LMO/RMO/LMBC/RMBC circuit 237, the "N" bit is set to the AND of the zero compares of the plural sections of arithmetic logic unit 230. Writing to this bit in software overrides the normal arithmetic logic unit result writing logic. The "C" bit (bit 30) stores an indication of a carry result. The "C" bit is set to "1" if the result of the last operation of arithmetic logic unit 230 caused a carry-out from bit 31 of the arithmetic logic unit. During multiple arithmetic and bit detection, the "C" bit is set to the OR of the carry outs of the plural sections of arithmetic logic unit 230. Thus the "C" bit is set to "1" if at least one of the sections has a carry out. Writing to this bit in software overrides the normal arithmetic logic unit result writing logic. The "V" bit (bit 29) stores an indication of an overflow result. The "V" bit is set to "1" if the result of the last operation of arithmetic logic unit 230 created an overflow condition. This bit is loaded with the exclusive OR of the carry-in and carry-out of bit 31 of the arithmetic logic unit 230. During multiple arithmetic logic unit operation the "V" bit is the AND of the carry outs of the plural sections of arithmetic logic unit 230. For left most one and right most one bit detection, the "V" bit is set to "1" if there were no "1's" in the input word, otherwise the "V" bit is set to "0". For left most bit change and right most bit change bit detection, the "V" bit is set to "1" is all the bits of the input are the same, or else the "V" bit is set to "0". Writing to this bit in software overrides the normal arithmetic logic unit result writing logic. The "Z" bit (bit 28) stores and indication of a "0" result. The "Z" bit is set to "1" if the result of the last operation of arithmetic logic unit 230 produces a "0" result. This "Z" bit is controlled for both arithmetic operations and logical operations. In multiple arithmetic and bit detection operations, the "Z" bit is set to the OR of the zero compares of the plural sections of arithmetic logic unit 230. Writing to this bit in software overrides the normal arithmetic logic unit result writing logic circuitry. The "R" bit (bit 6) controls bits used by expand circuit 238 and rotation of multiple flags register 211 during instructions that use expand circuit 238 to expand portions of multiple flags register 211. If the "R" bit is "1", then the bits used in an expansion of multiple flags register 211 via expand circuit 238 are the most significant bits. For an operation involving expansion of multiple flags register 211 where the arithmetic logic unit function modifier does not specify multiple flags register rotation, then multiple flags register 211 is "post-rotated left" according to the "Msize" field. If the arithmetic logic unit function modifier does specify multiple flags register rotation, then multiple flags register 211 is rotated according to the "Asize" field. If the "R" bit is "0", then expand circuit 238 employs the least significant bits of multiple flags register 211. No rotation takes place according to the "Msize" field. However, the arithmetic logic unit function modifier may specify rotation by the "Asize" field. The "Msize" field (bits 5-3) indicates the data size employed in certain instruction classes that supply mask data from multiple flags register 211 to the C-port of arithmetic logic unit 230. The "Msize" field determines how many bits of multiple flags register 211 uses to create the mask information. When the instruction does not specify rotation corresponding to the "Asize" field and the "R" bit is "1", then multiple flags register 211 is automatically "post-rotated left" by an amount set by the "Msize" field. Codings for these bits are shown in Table 2. Msize Field Data Size bits Multiple Flags Register 5 4 3 Rotate amount No. of bits used Bit (s) R=1 used R=0 0 0 0 0 64 64 - - 0 0 1 1 32 32 31-0 31-0 0 1 0 2 16 16 31-16 15-0 0 1 1 4 8 8 31-24 7-0 1 0 0 8 4 4 31-28 3-0 1 0 1 16 2 2 31-30 1-0 1 1 0 32 1 1 31 0 1 1 1 64 0 0 - - As noted above, the preferred embodiment supports "Msize" fields of "100", "101" and "110" corresponding to data sizes of 8, 16 and 32 bits, respectively. Note that rotation for an "Msize" field of "001" results in no change in data output. "Msize" fields of "001", "010" and "011" are possible useful alternatives. "Msize" fields of "000" and "111" are meaningless but may be used in an extension of multiple flags register 211 to 64 bits. The "Asize" field (bits 2-0) indicate the data size for multiple operations performed by arithmetic logic unit 230. Arithmetic logic unit 230 preferably includes 32 parallel bits. During certain instructions arithmetic logic unit 230 splits into multiple independent sections. This is called a multiple arithmetic logic unit operation. This splitting of arithmetic logic unit 230 permits parallel operation on pixels of less than 32 bits that are packed into 32 bit data words. In the preferred embodiment arithmetic logic unit 230 supports: a single 32 bit operation; two sections of 16 bit operations; and four sections of 8 bit operations. These options are called word, half-word and byte operations. The "Asize" field indicates: the number of multiple sections of arithmetic logic unit 230; the number of bits of multiple flags register bits 211 set during the arithmetic logic unit operation, which is equal in number to the number of sections of arithmetic logic unit 230; and the number of bits the multiple flags register should "post-rotate left" after output during multiple arithmetic logic unit operation. The rotation amount specified by the "Asize" field dominates over the rotation amount specified by the "Msize" field and the "R" bit when the arithmetic logic unit function modifier indicates multiple arithmetic with rotation. Codings for these bits are shown in Table 3. Note that while the current preferred embodiment of the invention supports multiple arithmetic of one 32 bit section, two 16 bit sections and four 8 bit sections the coding of the "Asize" field supports specification of eight sections of 4 bits each, sixteen sections of 2 bits each and thirty-two sections of 1 bit each. Each of these additional section divisions of arithmetic logic unit 230 are feasible. Note also that the coding of the "Asize" field further supports specification of a 64 bit data size for possible extension of multiple flags register 211 to 64 bits. Asize Field Data Size bits Multiple Flags Register 2 1 0 Rotate amount No. of bits set Bit(s) set 0 0 0 0 64 64 - 0 0 1 1 32 32 31-0 0 1 0 2 16 16 15-0 0 1 1 4 8 8 7-0 1 0 0 8 4 4 3-0 1 0 1 16 2 2 1-0 1 1 0 32 1 1 0 1 1 1 64 0 0 - The "Msize" and "Asize" fields of status register 210 control different operations. When using the multiple flags register 211 as a source for producing a mask applied to the C-port of arithmetic logic unit 230, the "Msize" field controls the number of bits used and the rotate amount. In such a case the "R" bit determines whether the most significant bits or least significant bits are employed. When using the multiple flags register 211 as a destination for the status bits corresponding to sections of arithmetic logic unit 230, then the "Asize" field controls the number and identity of the bits loaded and the optional rotate amount. If a multiple arithmetic logic unit operation with "Asize" field specified rotation is specified with an instruction that supplies mask data to the C-port derived from multiple flags register 211, then the rotate amount of the "Asize" field dominates over the rotate amount of the combination of the "R" bit and the "Msize" field. The multiple flags register 211 is a 32 bit register that provides mask information to the C-port of arithmetic logic unit 230 for certain instructions. Global port destination data bus Gdst bus 107 may write to multiple flags register 211. Global port source bus Gsrc may read data from multiple flags register 211. In addition multiple arithmetic logic unit operations may write to multiple flags register 211. In this case multiple flags register 211 records either the carry or zero status information of the independent sections of arithmetic logic unit 230. The instruction executed controls whether the carry or zero is stored. The "Msize" field of status register 210 controls the number of least significant bits used from multiple flags register 211. This number is given in Table 2 above. The "R" bit of status register 210 controls whether multiple flags register 211 is pre-rotated left prior to supply of these bits. The value of the "Msize" field determines the amount of rotation if the "R" bit is "1". The selected data supplies expand circuit 238, which generates a 32 bit mask as detailed below. The "Asize" field of status register 210 controls the data stored in multiple flags register 211 during multiple arithmetic logic unit operations. As previously described, in the preferred embodiment arithmetic logic unit 230 may be used in one, two or four separate sections employing data of 32 bits, 16 bits and 8 bits, respectively. Upon execution of a multiple arithmetic logic unit operation, the "Asize" field indicates through the defined data size the number of bits of multiple flags register 211 used to record the status information of each separate result of the arithmetic logic unit. The bit setting of multiple flags register 211 is summarized in Table 4. Data Size bits ALU carry-out bits setting MF bits ALU result bits equal to zero setting MF bits 3 2 1 0 3 2 1 0 8 31 23 15 7 31-24 23-16 15-8 7-0 16 - - 31 15 - - 31-16 15-0 32 - - - 31 - - - 31-0 Note that Table 4 covers only the cases for data sizes of 8, 16 and 32 bits. Those skilled in the art would easily realize how to extend Table 4 to cover the cases of data sizes of 64 bits, 4 bits, 2 bits and 1 bit. Also note that the previous discussion referred to storing either carry or zero status in multiple flags register 211. It is also feasible to store other status bits such as negative and overflow. Multiple flags register 211 may be rotated left a number of bit positions upon execution of each arithmetic logic unit operation. The rotate amount is given above. When performing multiple arithmetic logic unit operations, the result status bit setting dominates over the rotate for those bits that are being set. When performing multiple arithmetic logic unit operations, an alternative to rotation is to clear all the bits of multiple flags register 211 not being set by the result status. This clearing is after generation of the mask data if mask data is used in that instruction. If multiple flags register 211 is written by software at the same time as recording an arithmetic logic unit result, then the preferred operation is for the software write to load all the bits. Software writes thus dominate over rotation and clearing of multiple flags register 211. Figure 7 illustrates the splitting of arithmetic logic unit 230 into multiple sections. As illustrated in Figure 7, the 32 bits of arithmetic logic unit 230 are separated into four sections of eight bits each. Section 301 includes arithmetic logic unit bits 7-0, section 302 includes bits 15-8, section 303 includes bits 23-16 and section 304 includes bits 31-24. Note that Figure 7 does not illustrate the inputs or outputs of these sections, which are conventional, for the sake of clarity. The carry paths within each of the sections 301, 302, 303 and 303 are according to the known art. Multiplexers 311, 312 and 313 control the carry path between sections 301, 302, 303 and 304. Each of these multiplexers is controlled to select one of three inputs. The first input is a carry look ahead path from the output of the previous multiplexer, or in the case of the first multiplexer 311 from bit 0 carry-in generator 246. Such carry look ahead paths and their use are known in the art and will not be further described here. The second selection is the carry-out from the last bit of the corresponding section of arithmetic logic unit 230. The final selection is the carry-in signal from bit 0 carry-in generator 246. Multiplexer 314 controls the output carry path for arithmetic logic unit 230. Multiplexer 314 selects either the carry look ahead path from the carry-out selected by multiplexer 313 or the carry-out signal for bit 31 from section 304. Multiplexers 311, 312, 313 and 314 are controlled based upon the selected data size. In the normal case arithmetic logic unit 230 operates on 32 bit data words. This is indicated by an "Asize" field of status register 210 equal to "110". In this case multiplexer 311 selects the carry-out from bit 7, multiplexer 312 selects the carry-out from bit 15, multiplexer 313 selects the carry-out from bit 23 and multiplexer 314 selects the carry-out from bit 31. Thus the four sections 301, 302, 303 and 304 are connected together into a single 32 bit arithmetic logic unit. If status register 210 selected a half-word via an "Asize" field of "101", then multiplexer 311 selects the carry-out from bit 7, multiplexer 312 selects the carry-in from bit 0 carry-in generator 246, multiplexer 313 selects the carry-out from bit 23 and multiplexer 314 selects the Carry-out from bit 31. Sections 301 and 302 are connected into a 16 bit unit and sections 303 and 304 are connected into a 16 bit unit. Note that multiplexer 312 selects the bit 0 carry-in signal for bit 16 just like bit 0, because bit 16 is the first bit in a 16 bit half-word. If status register 210 selected a byte via an "Asize" field of "100", then multiplexers 311, 312 and 313 select the carry-in from bit 0 carry-in generator 246. Sections 301, 302, 303 and 304 are split into four independent 8 bit units. Note that selection of the bit 0 carry-in signal at each multiplexer is proper because bits 8, 16 and 24 are each the first bit in an 8 bit byte. Figure 7 further illustrates zero resultant detection. Each 8 bit zero detect circuit 321, 322, 323 and 324 generates a "1" output if the resultant from the corresponding 8 bit section is all zeros "00000000". AND gate 331 is connected to 8 bit zero detect circuits 321 and 322, thus generating a "1" when all sixteen bits 15-0 are "0". AND gate 332 is similarly connected to 8 bit zero detect circuits 321 and 322 for generating a "1" when all sixteen bits 31-16 are "0". Lastly, AND gate 341 is connected to AND gates 331 and 332, and generates a "1" when all 32 bits 31-0 are "0". During multiple arithmetic logic unit operations multiple flags register 211 may store either carry-outs or the zero comparison, depending on the instruction. These stored resultants control masks to the C-port during later operations. Table 4 shows the source for the status bits stored. In the case in which multiple flags register 211 stores the carry-out signal(s), the "Asize" field of status register 210 determines the identity and number of carry-out signals stored. If the "Asize" field specifies word operations, then multiple flags register 211 stores a single bit equal to the carry-out signal of bit 31. If the "Asize" field specifies half-word operations, then multiple flags register 211 stores two bits equal to the carry-out signals of bits 31 and 15, respectfully. If the "Asize" field specifies byte operations, then multiple flags register 211 stores four bits equal to the carry-out signals of bits 31, 23, 15 and 7, respectively. The "Asize" field similarly controls the number and identity of zero resultants stored in multiple flags register 211 when storage of zero resultants is selected. If the "Asize" field specifies word operations, then multiple flags register 211 stores a single bit equal to output of AND gate 341 indicating if bits 31-0 are "0". If the "Asize" field specifies half-word operations, then multiple flags register 211 stores two bits equal to the outputs of AND gates 331 and 332, respectfully. If the "Asize" field specifies byte operations, then multiple flags register 211 stores four bits equal to the outputs of 8 bit zero detect circuits 321, 322, 323 and 324, respectively. It is technically feasible and within the scope of this invention to allow further multiple operations of arithmetic logic unit 230 such as: eight sections of 4 bit operations; sixteen sections 2 bit operations; and thirty-two sections single bit operations. Note that both the "Msize" and the "Asize" fields of status register 210 include coding to support such additional multiple operation types. Those skilled in the art can easily modify and extend the circuits illustrated in Figure 7 using additional multiplexers and AND gates. These latter feasible options are not supported in the preferred embodiment due to the added complexity in construction of arithmetic logic unit 230. Note also that this technique can be extended to a data processing apparatus employing 64 bit data and that the same teachings enable such an extension. Data registers 200, designated data registers D7-D0 are connected to local port data bus Lbus 103, global port source data bus Gsrc 105 and global port destination data bus Gdst 107. Arrows within the rectangle representing data registers 200 indicate the directions of data access. A left pointing arrow indicates data recalled from data registers 200. A right pointing arrow indicates data written into data registers 200. Local port data bus Lbus 103 is bidirectionally coupled to data registers 200 as a data source or data destination. Global port destination data bus Gdst 107 is connected to data registers 200 as a data source for data written into data registers 200. Global port source data bus Gsrc 107 is connected to data registers 200 as a data destination for data recalled from data registers 200 in both a normal data register mode and in a rotation register feature described below. Status register 210 and multiple flags register 211 may be read from via global port source data bus Gsrc 106 and written into via global port destination data bus Gdst 107. Data registers 200 supply data to multiplier first input bus 201, multiplier second input bus 202, arithmetic logic unit first input bus 205 and arithmetic logic unit second input bus 206. Data registers 200 are connected to receive input data from multiplier destination bus 203 and arithmetic logic unit destination bus 204. Data registers 200, designated registers D7-D0, are connected to form a 256 bit rotate register as illustrated in Figure 8. This rotate register is collectively designated rotation (ROT) register ROT 208. This forms a 256 bit register comprising eight 32 bit rotation registers ROT0, ROT1, ... ROT7. Figure 8 illustrates in part the definitions of the rotation registers ROT0, ROT1, ... ROT7. These rotation registers are defined sideways with respect to data registers D7-D0. The rotation register 208 may be rotated by a non-arithmetic logic unit instruction DROT, as described below. During this rotation the least significant bit of data register D7 rotates into the most significant bit of data register D6, etc. The least significant bit of data register D0 is connected back to the most significant bit of data register D7. ROT register 208 may be read in four 8 bit bytes at a time. The four 8 bit bytes are respective octets of bits having the same bit number in each of data registers 200 as shown below in Table 5 and illustrated in Figure 8. Rotation Register bits Octet of bits from each D7-D0 Bit 31-24 24 23-16 16 15-8 8 7-0 0 When a DROT instruction is executed the 256 bit rotation register 208 is rotated right one bit place. The least significant bit 0 of each byte A, B, C, D of each register such as D7 is mapped as shown to a particular bit number of the ROT register output onto the global port source data bus Gsrc 105. ROT register 208 is read only in the preferred embodiment, but can be writable in other embodiments. ROT register 208 is useful in image rotations, orthogonal transforms and mirror transforms. Performing 32 bit stores to memory from the rotation register 208 in parallel with eight DROT instructions rotates four 8 by 8 bit patches of data clockwise ninety degrees. The rotated data is stored in the target memory locations. Various combinations of register loading, memory address storing, and data size alteration, can enable a variety of clockwise and counter-clockwise rotations of 8 by 8 bit patches to be performed. Rotation of larger areas can then be performed by moving whole bytes. This remarkable orthogonal structure that provides register file access to registers D7-D0 in one mode, and rotation register access in the DROT operation, is only slightly more complex than a register file alone. The data register D0 has a dual function. It may be used as a normal data register in the same manner as the other data registers D7-D1. Data register D0 may also define certain special functions when executing some instructions. Some of the bits of the most significant half-word of data register D0 specifies the operation of all types of extended arithmetic logic unit operations. Some of the bits of the least significant half-word of data register D0 specifies multiplier options during a multiple multiply operation. The 5 least significant bits of data register D0 specify a default barrel rotate amount used by certain instruction classes. Figure 9 illustrates the contents of data register D0 when specifying data unit 110 operation. The "FMOD" field (bits 31-28) of data register D0 allow modification of the basic operation of arithmetic logic unit 230 when executing an instruction calling for an extended arithmetic logic unit (EALU) operation. Table 6 illustrates these modifier options. Note, as indicated in Table 6, certain instruction word bits in some instruction formats are decoded as function modifiers in the same fashion. These will be further discussed below. The modified operations listed in Table 6 are explained below. If the "FMOD" field is "0000", the normal, unmodified operation results. The modification "cain" causes the carry-in to bit 0 of arithmetic logic unit 230 to be the "C" bit of status register 210. This allows add with carry, subtract with borrow and negate with borrow operations. The modification "%!" works with mask generation. When the "%!" modification is active mask generator 239 effectively generates all "1's" for a zero rotate amount rather than all "0's". This function can be implemented by changing the mask generated by mask generator 239 or by modifying the function of arithmetic logic unit 230 so that mask of all "0's" supplied to the C-port operates as if all "1's" were supplied. This modification is useful in some rotate operations. The modifications "LMO", "RMO", "LMBC" and "RMBC" designate controls of the LMO/RMO/LMBC/RMBC circuit 237. The modification "LMO" finds the left most "1" of the second arithmetic input. The modification "RMO" finds the right most "1". The modification "LMBC" finds the left most bit that differs from the sign bit (bit 31). The "RMBC" modification finds the right most bit that differs from the first bit (bit 0). Note that these modifications are only relevant if the C-port of arithmetic logic unit 230 does not receive a mask from mask generator 239. The modification "A-port=0" indicates that the input to the A-port of arithmetic logic unit 230 is effectively zeroed. This may take place via multiplexer Amux 232 providing a zero output, or the operation of arithmetic logic unit 230 may be altered in a manner having the same effect. An "A-port=0" modification is used in certain negation, absolute value and shift right operations. A "multiple arithmetic logic unit operation" modification indicates that one or more of the carry paths of arithmetic logic unit 230 are severed, forming in effect two or more independent arithmetic logic units operating in parallel. The "Asize" field of status register 210 controls the number of such multiple arithmetic logic unit sections. The multiple flags register 211 stores a number of status bits equal to the number of sections of the multiple arithmetic logic unit operations. In the "carry-out(s) --> multiple flags" modification, the carry-out bit or bits are stored in multiple flags register 211. In the "zero result(s) --> multiple flags" modification, an indication of the zero resultant for the corresponding arithmetic logic unit section is stored in multiple flags register 211. This process is described above together with the description of multiple flags register 211. During this storing operation, bits within multiple flags register 211 may be rotated in response to the "rotate" modification or cleared in response to the "clear" modification. These options are discussed above together with the description of multiple flags register 211. The "A" bit (bit 27) of data register D0 controls whether arithmetic logic unit 230 performs an arithmetic or Boolean logic operation during an extended arithmetic logic unit operation. This bit is called the arithmetic enable bit. If the "A" bit is "1", then an arithmetic operation is performed. If the "A" bit is "0", then a logic operation is performed. If the "A" bit is "0", then the carry-in from bit 0 carry-in generator 246 into bit 0 of the arithmetic logic unit 230 is generally "0". As will be further explained below certain extended arithmetic logic unit operations may have a carry-in bit of "1" even when the "A" bit is "0" indicating a logic operation. The "EALU" field (bits 19-26 of data register D0 defines an extended arithmetic logic unit operation. The eight bits of the "EALU" field specify the arithmetic logic unit function control bits used in all types of extended arithmetic logic unit operations. These bits become the control signals to arithmetic logic unit 230. They may be passed to arithmetic logic unit 230 directly, or modified according to the "FMOD" field. In some instructions the bits of the "EALU" field are inverted, leading to an "EALUF" or extended arithmetic logic unit false operation. In this case the eight control bits supplied to arithmetic logic unit 230 are inverted. The "C" bit (bit 18) of data register D0 designates the carry-in to bit 0 of arithmetic logic unit 230 during extended arithmetic logic unit operations. The carry-in value into bit 0 of the arithmetic logic unit during extended arithmetic logic unit operations is given by this "C" bit. This allows the carry-in value to be specified directly, rather than by a formula as for non-EALU operations. The "I" bit (bit 17) of data register D0 is designated the invert carry-in bit. The "I" bit, together with the "C" bit and the "S" bit (defined below), determines whether or not to invert the carry-in into bit 0 of arithmetic logic unit 230 when the function code of an arithmetic logic unit operation are inverted. This will be further detailed below. The "S" bit (bit 16) of data register D0 indicates selection of sign extend. The "S" bit is used when executing extended arithmetic logic unit operations ("A" bit=1). If the "S" bit is "1", then arithmetic logic unit control signals F3-F0 (produced from bits 22-19) should be inverted if the sign bit (bit 31) of the data first arithmetic logic unit input bus 206 is "0", and not inverted if this sign bit is "1". The effect of conditionally inverting arithmetic logic unit control signals F3-F0 will be explained below. Such an inversion is useful to sign extend a rotated input in certain arithmetic operations. If the extended arithmetic logic unit operation is Boolean ("A" bit=0), then the "S" bit is ignored and the arithmetic logic unit control signals F3-F0 are unchanged. Table 7 illustrates the interaction of the "C", "I" and "S" bits of data register D0. Note that an "X" entry for either the "I" bit or the first input sign indicates that bit does not control the outcome, i.e. a "don't care" condition. S I First Input Sign Invert C? Invert F3-F0 0 X X no no 1 0 0 no no 1 0 1 no yes 1 1 0 no no 1 1 1 yes yes If the "S" bit equals "1" and the sign bit of the first input destined for the B-port of arithmetic logic unit 230 equals "0", then the value of the carry-in to bit 0 of arithmetic logic unit 230 set by the "C" bit value can optionally be inverted according to the value of the "I" bit. This allows the carry-in to be optionally inverted or not, based on the sign of the input. Note also that arithmetic logic unit control signals F3-F0 are optionally inverted based on the sign of the input, if the "S" bit is "1". This selection of inversion of arithmetic logic unit control signals F3-F0 may be overridden by the "FMOD" field. If the "FMOD" field specifies "Carry-in = Status Register's Carry bit", then the carry-in equals the "C" bit of status register 210 whatever the value of the "S" and "I" bits. Note also that the carry-in for bit 0 of arithmetic logic unit 230 may be set to "1" via the "C" bit for extended arithmetic logic unit operations even if the "A" bit is "0" indicating a Boolean operation. The "N" bit (bit 15) of data register D0 is used when executing a split or multiple section arithmetic logic unit operation. This "N" bit is called the non-multiple mask bit. For some extended arithmetic logic unit operations that specify multiple operation via the "FMOD" field, the instruction specifies a mask to be passed to the C-port of arithmetic logic unit 230 via mask generator 239. This "N" bit determines whether or not the mask is split into the same number of sections as arithmetic logic unit 230. Recall that the number of such multiple sections is set by the "Asize" field of status register 210. If the "N" bit is "0", then the mask is split into multiple masks. If the "N" bit is "1", then mask generator 239 produces a single 32 bit mask. The "E" bit (bit 14) designates an explicit multiple carry-in. This bit permits the carry-in to be specified at run time by the input to the C-port of arithmetic logic unit 230. If both the "A" bit and the "E" bit are "1" and the "FMOD" field does not designate the cain function, then the effects of the "S", "I" and "C" bits are annulled. The carry input to each section during multiple arithmetic is taken as the exclusive OR of the least significant bit of the corresponding section input to the C-port and the function signal F0. If multiple arithmetic is not selected the single carry-in to bit 0 of arithmetic logic unit 230 is the exclusive OR of the least significant bit (bit 0) the input to the C-port and the function signal F0. This is particularly useful for performing multiple arithmetic in which differing functions are performed in different sections. One extended arithmetic logic unit operation corresponds to (A^B)&C | (A^∼B)&C. Using a mask for the C-port input, a section with all "0's" produces addition with the proper carry-in of "0" and a section of all "1's" produces subtraction with the proper carry-in of "1". The "DMS" field (bits 12-8) of data register D0 defines the shift following the multiplier. This shift takes place in product left shifter 224 prior to saving the result or passing the result to rounding logic. During this left shift the most significant bits shifted out are discarded and zeroes are shifted into the least significant bits. The "DMS" field is effective during any multiply/extended arithmetic logic unit operation. In the preferred embodiment data register D0 bits 9-8 select 0, 1, 2 or 3 place left shifting. Table 8 illustrates the decoding. DMS field Left shift amount 9 8 0 0 0 0 1 1 1 0 2 1 1 3 The "DMS" field includes 5 bits that can designate left shift amounts from 0 to 31 places. In the preferred embodiment product left shifter 224 is limited to shifts from 0 to 3 places for reasons of size and complexity. Thus bits 12-10 of data register D0 are ignored in setting the left shift amount. However, it is feasible to provide a left shift amount within the full range from 0 to 31 places from the "DMS" field if desired. The "M" bit (bit 7) of data register D0 indicates a multiple multiply operation. Multiplier 220 can multiply two 16 bit numbers to generate a 32 bit result or of simultaneously multiplying two pair of 8 bit numbers to generate a pair of 16 bit resultants. This "M" bit selects either a single 16 by 16 multiply if "M" = "0", or two 8 by 8 multiplies if "M" = "1". This operation is similar to multiple arithmetic logic unit operations and will be further described below. The "R" bit (bit 6) of data register D0 specifies whether a rounding operation takes place on the resultant from multiplier 220. If the "R" bit is "1", the a rounding operation, explained below together with the operation of multiplier 220, takes place. If the "R" bit is "0", then no rounding takes place and the 32 bit resultant form multiplier 220 is written into the destination register. Note that use of a predetermined bit in data register D0 is merely a preferred embodiment for triggering this mode. It is equally feasible to enable the rounding mode via a predetermined instruction word bit. The "DBR" field (bits 4-0) of data register D0 specifies a default barrel rotate amount used barrel rotator 235 during certain instructions. The "DBR" field specifies the number of bit positions that barrel rotator 235 rotates left. These 5 bits can specify a left rotate of 0 to 31 places. The value of the "DBR" field may also be supplied to mask generator 239 via multiplexer Mmux 234. Mask generator 239 forms a mask supplied to the C-port of arithmetic logic unit 230. The operation of mask generator 239 will be discussed below. Multiplier 220 is a hardware single cycle multiplier. As described above, multiplier 220 operates to multiply a pair of 16 bit numbers to obtain a 32 bit resultant or to multiply two pairs of 8 bit numbers to obtain two 16 bit resultants in the same 32 bit data word. Arithmetic logic unit 230 performs arithmetic and logic operations within data unit 110. Arithmetic logic unit 230 advantageously includes three input ports for performing three input arithmetic and logic operations. Numerous buses and auxiliary hardware supply the three inputs. Input A bus 241 supplies data to an A-port of arithmetic logic unit 230. Multiplexer Amux 232 supplies data to input A bus 241 from either multiplier second input bus 202 or arithmetic logic unit first input bus 205 depending on the instruction. Data on multiplier second input bus 202 may be from a specified one of data registers 200 or from an immediate field of the instruction via multiplexer Imux 222 and buffer 223. Data on arithmetic logic unit first input bus 205 may be from a specified one of data registers 200 or from global port source data bus Gsrc bus 105 via buffer 106. Thus the data supplied to the A-port of arithmetic logic unit 230 may be from one of the data registers 200, from an immediate field of the instruction word or a long distance source from another register of digital image/graphics processor 71 via global source data bus Gsrc 105 and buffer 106. Input B bus 242 supplies data to the B-port of arithmetic logic unit 230. Barrel rotator 235 supplies data to input B bus 242. Thus barrel rotator 235 controls the input to the B-port of arithmetic logic unit 230. Barrel rotator 235 receives data from arithmetic logic unit second input bus 206. Arithmetic logic unit second input bus 206 supplies data from a specified one of data registers 200, data from global port source data bus Gsrc bus 105 via buffer 104 or a special data word from buffer 236. Buffer 236 supplies a 32 bit data constant of "00000000000000000000000000000001" (also called Hex "1") to arithmetic logic unit second input bus 206 if enabled. Note hereinafter data or addresses preceded by "Hex" are expressed in hexadecimal. Data from global port source data bus Gsrc 105 may be supplied to barrel rotator 235 as a long distance source as previously described. When buffer 236 is enabled, barrel rotator 235 enables generation on input B bus 242 of any constant of the form 2 N , where N is the barrel rotate amount. Constants of this form are useful in operations to control only a single bit of a 32 bit data word. The data supplied to arithmetic logic unit second input bus 206 and barrel rotator 235 depends upon the instruction. Barrel rotator 235 is a 32 bit rotator that may rotate its received data from 0 to 31 positions. It is a left rotator, however, a right rotate of n bits may be obtained by left rotating 32-n bits. A five bit input from rotate bus 244 controls the amount of rotation provided by barrel rotator 235. Note that the rotation is circular and no bits are lost. Bits rotated out the left of barrel rotator 235 wrap back into the right. Multiplexer Smux 231 supplies rotate bus 244. Multiplexer Smux 231 has several inputs. These inputs include: the five least significant bits of multiplier first input bus 201; the five least significant bits of multiplier second input bus 202; five bits from the "DBR" field of data register D0; and a five bit zero constant "00000". Note that because multiplier second input bus 202 may receive immediate data via multiplexer Imux 222 and buffer 223, the instruction word can supply an immediate rotate amount to barrel rotator 235. Multiplexer Smux 231 selects one of these inputs to determine the amount of rotation in barrel rotator 235 depending on the instruction. Each of these rotate quantities is five bits and thus can set a left rotate in the range from 0 to 31 bits. Barrel rotator 235 also supplies data to multiplexer Bmux 227. This permits the rotated data from barrel rotator 235 to be stored in one of the data registers 200 via multiplier destination bus 203 in parallel with an operation of arithmetic logic unit 230. Barrel rotator 235 shares multiplier destination bus 203 with multiplexer Rmux 221 via multiplexer Bmux 227. Thus the rotated data cannot be saved if a multiply operation takes place. In the preferred embodiment this write back method is particularly supported by extended arithmetic logic unit operations, and can be disabled by specifying the same register destination for barrel rotator 235 result as for arithmetic logic unit 230 result. In this case only the result of arithmetic logic unit 230 appearing on arithmetic logic unit destination bus 204 is saved. Although the above description refers to barrel rotator 235, those skilled in the art would realize that substantial utility can be achieved using a shifter which does not wrap around data. Particularly for shift and mask operations where not all of the bits to the B-port of arithmetic logic unit 230 are used, a shifter controlled by rotate bus 244 provides the needed functionality. In this event an additional bit, such as the most significant bit on the rotate bus 244, preferably indicates whether to form a right shift or a left shift. Five bits on rotate bus 244 are still required to designate the magnitude of the shift. Therefore it should be understood in the description below that a shifter may be substituted for barrel rotator 235 in many instances. Input C bus 243 supplies data to the C-port of arithmetic logic unit 230. Multiplexer Cmux 233 supplies data to input C bus 243. Multiplexer Cmux 233 receives data from four sources. These are LMO/RMO/LMBC/RMBC circuit 237, expand circuit 238, multiplier second input bus 202 and mask generator 239. LMO/RMO/LMBC/RMBC circuit 237 is a dedicated hardware circuit that determines either the left most "1", the right most "1", the left most bit change or the right most bit change of the data on arithmetic logic unit second input bus 206 depending on the instruction or the "FMOD" field of data register D0. LMO/RMO/LMBC/RMBC circuit 237 supplies to multiplexer Cmux 233 a 32 bit number having a value corresponding to the detected quantity. The left most bit change is defined as the position of the left most bit that is different from the sign bit 32. The right most bit change is defined as the position of the right most bit that is different from bit 0. The resultant is a binary number corresponding to the detected bit position as listed below in Table 9. The values are effectively the big endian bit number of the detected bit position, where the result is 31-(bit position). bit position result 0 31 1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 11 20 12 19 13 18 14 17 15 16 16 15 17 14 18 13 19 12 20 11 21 10 22 9 23 8 24 7 25 6 26 5 27 4 28 3 29 2 30 1 31 0 This determination is useful for normalization and for image compression to find a left most or right most "1" or changed bit as an edge of an image. The LMO/RMO/LMBC/RMBC circuit 237 is a potential speed path, therefore the source coupled to arithmetic logic unit second input bus 206 is preferably limited to one of the data registers 200. For the left most "1" and the right most "1" operations, the "V" bit indicating overflow of status register 210 is set to "1" if there were no "1's" in the source, and "0" if there were. For the left most bit change and the right most bit change operations, the "V" bit is set to "1" if all bits in the source were equal, and "0" if a change was detected. If the "V" bit is set to "1" by any of these operations, the LMO/RMO/LMBC/RMBC result is effectively 32. Further details regarding the operation of status register 210 appear above. Expand circuit 238 receives inputs from multiple flags register 211 and status register 210. Based upon the "Msize" field of status register 210 described above, expand circuit 238 duplicates some of the least significant bits stored in multiple flags register 211 to fill 32 bits. Expand circuit 238 may expand the least significant bit 32 times, expand the two least significant bits 16 times or expand the four least significant bits 8 times. The "Asize" field of status register 210 controls processes in which the 32 bit arithmetic logic unit 230 is split into independent sections for independent data operations. This is useful for operation on pixels sizes less than the 32 bit width of arithmetic logic unit 230. This process, as well as examples of its use, will be further described below. Mask generator 239 generates 32 bit masks that may be supplied to the input C bus 243 via multiplexer Cmux 233. The mask generated depends on a 5 bit input from multiplexer Mmux 234. Multiplexer Mmux 234 selects either the 5 least significant bits of multiplier second input bus 202, or the "DBR" field from data register D0. In the preferred embodiment, an input of value N causes mask generator 239 to generate a mask generated that has N "1's" in the least significant bits, and 32-N "0's" in the most significant bits. This forms an output having N right justified "1's". This is only one of four possible methods of operation of mask generator 239. In a second embodiment, mask generator 239 generates the mask having N right justified "0's", that is N "0's" in the least significant bits and N-32 "1's" in the most significant bits. It is equally feasible for mask generator 239 to generate the mask having N left justified "1's" or N left justified "0's". Table 10 illustrates the operation of mask generator 239 in accordance with the preferred embodiment when multiple arithmetic is not selected. Mask Generator Input Mask - Nonmultiple Operation 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 1 0000 0000 0000 0000 0000 0000 0000 0001 0 0 0 1 0 0000 0000 0000 0000 0000 0000 0000 0011 0 0 0 1 1 0000 0000 0000 0000 0000 0000 0000 0111 0 0 1 0 0 0000 0000 0000 0000 0000 0000 0000 1111 0 0 1 0 1 0000 0000 0000 0000 0000 0000 0001 1111 0 0 1 1 0 0000 0000 0000 0000 0000 0000 0011 1111 0 0 1 1 1 0000 0000 0000 0000 0000 0000 0111 1111 0 1 0 0 0 0000 0000 0000 0000 0000 0000 1111 1111 0 1 0 0 1 0000 0000 0000 0000 0000 0001 1111 1111 0 1 0 1 0 0000 0000 0000 0000 0000 0011 1111 1111 0 1 0 1 1 0000 0000 0000 0000 0000 0111 1111 1111 0 1 1 0 0 0000 0000 0000 0000 0000 1111 1111 1111 0 1 1 0 1 0000 0000 0000 0000 0001 1111 1111 1111 0 1 1 1 0 0000 0000 0000 0000 0011 1111 1111 1111 0 1 1 1 1 0000 0000 0000 0000 0111 1111 1111 1111 1 0 0 0 0 0000 0000 0000 0000 1111 1111 1111 1111 1 0 0 0 1 0000 0000 0000 0001 1111 1111 1111 1111 1 0 0 1 0 0000 0000 0000 0011 1111 1111 1111 1111 1 0 0 1 1 0000 0000 0000 0111 1111 1111 1111 1111 1 0 1 0 0 0000 0000 0000 1111 1111 1111 1111 1111 1 0 1 0 1 0000 0000 0001 1111 1111 1111 1111 1111 1 0 1 1 0 0000 0000 0011 1111 1111 1111 1111 1111 1 0 1 1 1 0000 0000 0111 1111 1111 1111 1111 1111 1 1 0 0 0 0000 0000 1111 1111 1111 1111 1111 1111 1 1 0 0 1 0000 0001 1111 1111 1111 1111 1111 1111 1 1 0 1 0 0000 0011 1111 1111 1111 1111 1111 1111 1 1 0 1 1 0000 0111 1111 1111 1111 1111 1111 1111 1 1 1 0 0 0000 1111 1111 1111 1111 1111 1111 1111 1 1 1 0 1 0001 1111 1111 1111 1111 1111 1111 1111 1 1 1 1 0 0011 1111 1111 1111 1111 1111 1111 1111 1 1 1 1 1 0111 1111 1111 1111 1111 1111 1111 1111 A value N of "0" thus generates 32 "0's". In some situations however it is preferable that a value of "0" generates 32 "1's". This function is selected by the "%!" modification specified in the "FMOD" field of status register 210 or in bits 52, 54, 56 and 58 of the instruction when executing an extended arithmetic logic unit operation. This function can be implemented by changing the mask generated by mask generator 239 or by modifying the function of arithmetic logic unit 230 so that mask of all "0's" supplied to the C-port operates as if all "1's" were supplied. Note that similar modifications of the other feasible mask functions are possible. Thus the "%!" modification can change a mask generator 239 which generates a mask having N right justified "0's" to all "0's" for N=0. Similarly, the "%!" modification can change a mask generator 239 which generates N left justified "1's" to all "1's" for N=0, or change a mask generator 239 which generates N left justified "0's" to all "0's" for N=0. Selection of multiple arithmetic modifies the operation of mask generator 239. When the "Asize" field of status register is "110", this selects a data size of 32 bits and the operation of mask generator 239 is unchanged from that shown in Table 10. When the "Asize" field of status register is "101", this selects a data size of 16 bits and mask generator 239 forms two independent 16 bit masks. This is shown in Table 11. Note that in this case the most significant bit of the input to mask generator 239 is ignored. Table 11 shows this bit as a don't care "X". Mask Generator Input Mask - Half Word Operation X 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 X 0 0 0 1 0000 0000 0000 0001 0000 0000 0000 0001 X 0 0 1 0 0000 0000 0000 0011 0000 0000 0000 0011 X 0 0 1 1 0000 0000 0000 0111 0000 0000 0000 0111 X 0 1 0 0 0000 0000 0000 1111 0000 0000 0000 1111 X 0 1 0 1 0000 0000 0001 1111 0000 0000 0001 1111 X 0 1 1 0 0000 0000 0011 1111 0000 0000 0011 1111 X 0 1 1 1 0000 0000 0111 1111 0000 0000 0111 1111 X 1 0 0 0 0000 0000 1111 1111 0000 0000 1111 1111 X 1 0 0 1 0000 0001 1111 1111 0000 0001 1111 1111 X 1 0 1 0 0000 0011 1111 1111 0000 0011 1111 1111 X 1 0 1 1 0000 0111 1111 1111 0000 0111 1111 1111 X 1 1 0 0 0000 1111 1111 1111 0000 1111 1111 1111 X 1 1 0 1 0001 1111 1111 1111 0001 1111 1111 1111 X 1 1 1 0 0011 1111 1111 1111 0011 1111 1111 1111 X 1 1 1 1 0111 1111 1111 1111 0111 1111 1111 1111 The function of mask generator 239 is similarly modified for a selection of byte data via an "Asize" field of "100". Mask generator 239 forms four independent masks using only the three least significant bits of its input. This is shown in Table 12. Mask Generator Input Mask - Byte Operation X X 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 X X 0 0 1 0000 0001 0000 0001 0000 0001 0000 0001 X X 0 1 0 0000 0011 0000 0011 0000 0011 0000 0011 X X 0 1 1 0000 0111 0000 0111 0000 0111 0000 0111 X X 1 0 0 0000 1111 0000 1111 0000 1111 0000 1111 X X 1 0 1 0001 1111 0001 1111 0001 1111 0001 1111 X X 1 1 0 0011 1111 0011 1111 0011 1111 0011 1111 X X 1 1 1 0111 1111 0111 1111 0111 1111 0111 1111 As noted above, it is feasible to support multiple operations of 8 sections of 4 bits each, 16 sections of 2 bits each and 32 single bit sections. Those skilled in the art would realize that these other data sizes require similar modification to the operation of mask generator 239 as shown above in Tables 10, 11, and 12. Data unit 110 includes a three input arithmetic logic unit 230. Arithmetic logic unit 230 includes three input busses: input A bus 241 supplies an input to an A-port; input B bus 242 supplies an input to a B-port; and input C bus 243 supplies an input to a C-port. Arithmetic logic unit 230 supplies a resultant to arithmetic logic unit destination bus 204. This resultant may be stored in one of the data registers of data registers 200. Alternatively the resultant may be stored in another register within digital image/graphics processor 71 via buffer 108 and global port destination data bus Gdst 107. This function is called a long distance operation. The instruction specifies the destination of the resultant. Function signals supplied to arithmetic logic unit 230 from function signal generator 245 determine the particular three input function executed by arithmetic logic unit 230 for a particular cycle. Bit 0 carry-in generator 246 forms a carry-in signal supplied to bit 0, the first bit of arithmetic logic unit 230. As previously described, during multiple arithmetic operations bit 0 carry-in generator 246 supplies the carry-in signal to the least significant bit of each of the multiple sections. Figure 10 illustrates in block diagram form the construction of an exemplary bit circuit 400 of arithmetic logic unit 230. Arithmetic logic unit 230 preferably operates on data words of 32 bits and thus consists of 32 bit circuits 400 in parallel. Each bit circuit 400 of arithmetic logic unit 230 receives: the corresponding bits of the three inputs A i , B i and C i ; a zero carry-in signal designated c in0 from the previous bit circuit 400; a one carry-in signal designated c in1 from the previous bit circuit 400; an arithmetic enable signal A en ; an inverse kill signal K i-1 from the previous bit circuit; a carry sense select signal for selection of carry-in signal cin0 or cin1; and eight inverse function signals F 7 - F 0 . The carry-in signals c in0 and c in1 for the first bit (bit 0) are identical and are generated by a special circuit that will be described below. Note that the input signals A i , B i and C i are formed for each bit of arithmetic logic unit 230 and may differ. The arithmetic enable signal A en and the inverted function signals F 7 - F 0 are the same for G11 of the 32 bit circuits 400. Each bit circuit 400 of arithmetic logic unit 230 generates: a corresponding one bit resultant S i ; an early zero signal Z i ; a zero carry-out signal designated c out0 that forms the zero carry-in signal c in0 for the next bit circuit; a one carry-out signal designated c out1 that forms the one carry-in signal c in1 for the next bit circuit; and an inverse kill signal K i that forms the inverse kill signal K i-1 for the next bit circuit. A selected one of the zero carry-out signal c out0 or the one carry-out signal c out1 of the last bit in the 32 bit arithmetic logic unit 230 is stored in status register 210, unless the "C" bit is protected from change for that instruction. In addition during multiple arithmetic the instruction may specify that carry-out signals from separate arithmetic logic unit sections be stored in multiple flags register 211. In this event the selected zero carry-out signal c out0 or the one carry-out signal c out1 will be stored in multiple flags register 211. Bit circuit 400 includes resultant generator 401, carry out logic 402 and Boolean function generator 403. Boolean function generator 403 forms a Boolean combination of the respective bits inputs A i , B i and C i according to the inverse function signals F 7 - F 0 . Boolean function generator produces a corresponding propagate signal P i , a generate signal G i and a kill signal K i . Resultant logic 401 combines the propagate signal P i with one of the carry-in signal c in0 or carry-in signal c in1 from a prior bit circuit 400 as selected by the carry sense select signal and forms the bit resultant S i and an early zero signal Z i . Carry out logic 402 receives the propagate signal P i , the generate signal G i , the kill signal K i , the two carry-in signals c in0 and c in1 and an arithmetic enable signal A en . Carry out logic 402 produces two carry-out signals c out0 and c out1 that are supplied to the next bit circuit 400. Figures 11 and 12 together illustrate an exemplary bit circuit 400 of arithmetic logic unit 230. Figure 11 illustrates the details of a resultant logic 401 and carry out logic 402 of each bit circuit 400 of arithmetic logic unit 230. Figure 12 illustrates the details of the corresponding Boolean function generator 403 of each bit circuit 400 of arithmetic logic unit 230. Each resultant logic 401 generates a corresponding resultant signal S i and an early zero signal Z i . Resultant logic 420 forms these signals from the two carry-in signals, an inverse propagate signal P i , an inverse kill signal K i-1 from the previous bit circuit and a carry sense select signal. The carry out logic 402 forms two carry-out signals and an inverse kill signal K i . These signals are formed from the two carry-in signals, an inverse propagate signal P i , an inverse generate signal G i and a kill signal K i for that bit circuit 400. Each propagate signal indicates whether a "1" carry-in signal propagates through the bit circuit 400 to the next bit circuit 400 or is absorbed. The generate signal indicates whether the inputs to the bit circuit 400 generate a "1" carry-out signal to the next bit circuit 400. The kill signal indicates whether the input to the bit circuit 400 generate a "0" carry-out signal to the next bit circuit. Note that the propagate signal P i , the generate signal G i and the kill signal K i are mutually exclusive. Only one of these signals is generated for each combination of inputs. Each bit circuit 400 of arithmetic logic unit 230 employs a technique to reduce the carry ripple time through the 32 bits. Arithmetic logic unit 230 is divided into carry sections, preferably 4 sections of 8 bits each. The least significant bit circuit 400 of each such section has its zero carry-in signal c in0 hardwired to "0" and its one carry-in signal c in1 hardwired to "1". Each bit circuit 400 forms two resultants and two carry-out signals to the next bit circuit. Once the carry ripple through each section is complete, the actual carry output from the most significant bit of the previous carry section forms the carry sense select signal. This carry select signal permits selection of the actual resultant generated by the bits of a section via a multiplexer. The first carry section receives its carry select signal from bit 0 carry-in generator 246 described in detail below. This technique permits the carry ripple through the carry sections to take place simultaneously. This reduces the length of time required to generate the resultant at the cost of some additional hardware for the redundant carry lines and the carry sense selection. Carry out logic 402 controls transformation of the carry-in signals into the carry-out signals. Carry out logic 402 includes identical circuit operating on the two carry-in signals c in0 and c in1 . The inverse propagate signal P i and its inverse, the propagate signal P i formed by invertor 412, control pass gates 413 and 423. If the propagate signal P i is "1", then one carry-in line 410 is connected to one carry-out line 411 via pass gate 413 and zero carry-in line 420 is connected to zero carry-out line 421 via pass gate 423. Thus the carry-in signal is propagated to the carry-out. If the propagate signal P i is "0", then one carry-in line 410 is isolated from one carry-out line 411 and zero carry-in line 420 is isolated from carry-out line 421. If the generate signal G i is "1", that is if the inverse generate signal G i is "0", then P-channel MOSFET (metal oxide semiconductor field effect transistor) 414 is turned on to couple the supply voltage to carry-out line 411 and P-channel MOSFET 424 is turned on to couple the supply voltage to carry-out line 421. If the generate signal G i is "0", that is if the inverse generate signal G i is "1", then the P-channel MOSFETs 414 and 424 are cut off and do not affect the carry-out lines 411 and 421. If the kill signal K i is "1", then N-channel MOSFET 415 couples ground to carry-out line 411 and N-channel MOSFET 425 couples ground to carry-out line 421. If the kill signal K i is "0", then the N-channel MOSFETs 415 and 425 are cut off and do not affect the carry-out lines 411 and 421. Invertor 422 generates the inverse kill signal K i supplied to the next bit circuit. Exclusive OR circuits 431 and 433 form the two resultants of resultant logic 401. Exclusive OR circuits 431 and 433 each receive the propagate signal P i from invertor 427 on an inverting input and the inverse propagate signal P i from invertor 428 on a noninverting input. Exclusive OR circuit 431 receives the inverse zero carry-in signal c in0 from invertor 426 on a noninverting input and forms the resultant for the case of a "0" carry-in to the least significant bit of the current carry section. Likewise, exclusive OR circuit 433 receives the inverse one carry-in signal c in1 from invertor 416 on a noninverting input and forms the resultant for the case of a "1" carry-in to the least significant bit of the current carry section. Invertors 432 and 434 supply inputs to multiplexer 435. Multiplexer 435 selects one of these signals based upon the carry sense select signal. This carry sense select signal corresponds to the actual carry-out signal from the most significant bit of the previous carry section. The inverted output of multiplexer 435 from invertor 436 is the desired bit resultant S i . Resultant logic 401 also forms an early zero signal Z i for that bit circuit. This early zero signal Z i gives an early indication that the resultant S i of that bit circuit 400 is going to be "0". Exclusive OR circuit 437 receives the propagate signal P i from invertor 427 on an inverting input and the inverse propagate signal P i from invertor 428 on a noninverting input. Exclusive OR circuit 437 also receives the inverse kill signal K i-1 from the previous bit circuit 400 on a noninverting input. Exclusive OR circuit 437 forms early zero signal Z i for the case in which the previous bit kill signal K i-1 generates a "0" carry-out signal and the propagate signal P i is also "0". Note that if K i-1 is "0", then both the zero carry-out signal c out0 and the one carry-out signal c out1 are "0" whatever the state of the carry-in signals c in0 and c in1 . Note that this early zero signal Z i is available before the carry can ripple through the carry section. This early zero signal Z i may thus speed the determination of a zero output from arithmetic logic unit 230. Boolean function generator 403 of each bit circuit 400 of arithmetic logic unit 230 illustrated in Figure 12 generates the propagate signal P i , the generate signal G i and the kill signal K i for bit circuit 400. Boolean function generator 403 consists of four levels. The first level includes pass gates 451, 452, 453, 454, 455, 456, 457 and 458. Pass gates 451, 453, 455 and 457 are controlled in a first sense by input C i and inverse input C i from invertor 459. Pass gates 452, 454, 456 and 458 are controlled in an opposite sense by input C i and inverse input C i . Depending on the state of input C i , either pass gates 451, 453, 455 and 457 are conductive or pass gates 452, 454, 456 and 458 are conductive. The second level includes pass gates 461, 462, 463 and 464. Pass gates 461 and 463 are controlled in a first sense by input B i and inverse input B i from invertor 465. Pass gates 462 and 464 are controlled in the opposite sense. Depending on the state of input B i , either pass gates 461 and 463 are conductive or pass gates 462 and 464 are conductive. The third level includes pass gates 471, 472 and 473. Pass gates 471 is controlled in a first sense by input A i and inverse input A i from invertor 473. Pass gates 472 and 473 are controlled in the opposite sense. Depending on the state of input A i , either pass gates 471 is conductive or pass gates 472 and 473 are conductive. The first level includes invertors 441, 442, 443, 444, 445, 446, 447 and 448 that are coupled to corresponding inverted function signals F 7 - F 0 . Invertors 441, 442, 443, 444, 445, 446, 447 and 448 provide input drive to Boolean function generator 403 and determine the logic function performed by arithmetic logic unit 230. Boolean function generator 403 forms the propagate signal P i based upon the corresponding input signals A i , B i and C i and the function selected by the state of the inverted function signals F 7 - F 0 The propagate signal P i at the input to invertor 476 is "1" if any path through pass gates 451, 452, 453, 454, 455, 456, 457, 458, 461, 462, 463, 464, 471 or 472 couples a "1" from one of the invertors 441, 442, 443, 444, 445, 446, 447 or 448. In all other cases this propagate signal P i is "0". Invertor 476 forms the inverse propagate signal P i , which is connected to resultant logic 401 illustrated in Figure 11. Each pass gate 451, 452, 453, 454, 455, 456, 457, 458, 461, 462, 463, 464, 471, 472 and 473 consists of an N-channel MOSFET and a P-channel MOSFET disposed in parallel. The gate of the N-channel MOSFET receives a control signal. This field effect transistor is conductive if its gate input is above the switching threshold voltage. The gate of the P-channel MOSFET is driven by the inverse of the control signal via one of the invertors 459, 465 or 474. This field effect transistor is conductive if its gate input is below a switching threshold. Because the P-channel MOSFET operates in inverse to the operation of N-channel MOSFET, the corresponding invertor 459, 467 or 474 assures that these two field effect transistors are either both conducting or both non-conducting. The parallel N-channel and P-channel field effect transistors insure conduction when desired whatever the polarity of the controlled input. Tri-state AND circuit 480 forms the generate signal G i and the kill signal K i . The generate signal G i , the kill signal K 1 and the propagate signal P i are mutually exclusive in the preferred embodiment. Therefore the propagate signal P i controls the output of tri-state AND circuit 480. If the propagate signal P i is "1", then tri-state AND circuit 480 is disabled and both the generate signal G i and the kill signal K i are "0". Thus neither the generate signal G i nor the kill signal K i change the carry signal. Pass gate 473 couples the output from part of Boolean function generator 403 to one input of tri-state AND circuit 480. The gate inputs of pass gate 473 are coupled to the first input bit A i in the first sense. An N-channel MOSFET 475 conditionally couples this input of tri-state AND circuit 480 to ground. The inverse of the first input bit A i supplies the gate input to N-channel MOSFET 475. Pass gate 473 and N-channel MOSFET 475 are coupled in a wired OR relationship, however no OR operation takes place because their gate inputs cause them to be conductive alternately. N-channel MOSFET 475 serves to force a "0" input into tri-state AND circuit 480 when A i = "0". An arithmetic enable signal supplies the second input to tri-state AND circuit 480. The tri-state AND gate 480 operates as follows. If the propagate signal P i is "1", then both P-channel MOSFET 481 and N-channel MOSFET 482 are conductive and pass gate 483 is non-conductive. This cuts off P-channel MOSFETs 414 and 424 and N-channel MOSFETs 415 and 425 so that none of these field effect transistor conducts. The output of tri-state AND circuit 480 thus is a high impedance state that does not change the signal on the carry-out lines 411 and 421. If the propagate signal P 1 is "0", then both P-channel MOSFET 481 and N-channel MOSFET 482 are non-conductive and pass gate 483 is conductive. The circuit then forms a logical AND of the two inputs. If either arithmetic enable or the signal at the junction of N-channel MOSFET 475 and pass gate 473 is "0" or both are "0", then at least one of P-channel MOSFET 484 or P-channel MOSFET 485 connects the supply voltage V+ (a logic "1") as the inverse generate signal G i to the gates of P-channel MOSFETs 414 and 424 of carry out logic 402. Thus P-channel MOSFETs 414 and 424 are non-conductive. At the same time pass gate 483 is conductive and supplies this "1" signal as kill signal K i to the gates of N-channel MOSFETs 415 and 425 of carry out logic 402. This actively pulls down the signal on zero carry-out line 421 forcing the zero carry-out signal c out0 to "0" and one carry-out line 411 forcing the one carry-out signal c out1 to "0". If both the inputs are "1", then the series combination of N-channel MOSFET 486 and N-channel MOSFET 487 supplies ground (a logic "0") to the gates of N-channel MOSFETs 415 and 425. N-channel MOSFETs 415 and 425 of carry out logic 402 are cut off and non-conductive. At the same time pass gate 483 couples this "0" to the gates of P-channel MOSFETs 414 and 424. Thus P-channel MOSFETs 414 and 424 of carry out logic 402 are conductive. This actively pulls up the signal on zero carry-out line 421 forcing the zero carry-out signal c out0 to "1" and one carry-out line 411 forcing the one carry-out signal c out1 to "1". The bit circuit construction illustrated in Figure 10 and 21 forms a propagate term, a generate term, a resultant term and two carry-out terms. Bit circuit 400 forms the propagate term P i as follows: P i = F0&(∼A i &∼B i &∼C i ) | F1&( A i &∼B i &∼C i ) | F2&(∼A i & B i &∼C i ) | F3&( A i & B i &∼C i ) | F4&(∼A i &∼B i & C i ) | F5&(A i &∼B i & C i ) | F6&(∼A i & B i & C i ) | F7&( A i & B i & C i ) Bit circuit 400 forms the generate term G i as follows: G i = A i &[ (F0&∼F1&∼B i &∼C i ) | ( F2&∼F3& B i &∼C i ) | (F4&∼F5&∼B i & C i ) | (F6&∼F7& B i & C i ) ] Bit circuit 400 forms the kill term K i as follows: K i = ∼G i & ∼P i Bit circuit 400 forms the resultant term S i as follows: S i = P i ^ ( c in0 & CSS | c in1 &∼CSS ) where: CSS is the carry sense select signal. Bit circuit 400 forms the two carry-out signals c out0 and c out1 as follows: c out0 = (P i & c in0 ) | (G i & A en ) | ∼(K i & A en ) c out1 = (P i & c in1 ) | (G i & A en ) | ∼(K i & A en ) Note that for any particular bit i the propagate signal P i , the generate signal G i and the kill signal K i are mutually exclusive. No two of these signals occurs simultaneously. The construction of each bit circuit 400 enables arithmetic logic unit 230 to perform any one of 256 possible 3 input Boolean functions or any one of 256 possible 3 input mixed Boolean and arithmetic functions depending upon the inverted function signals F 7 - F 0 . The nine inputs including the arithmetic enable signal and the inverted function signals F 7 - F 0 permit the selection of 512 functions. As will be further described below the data paths of data unit 110 enable advantageous use of three input arithmetic logic unit 230 to speed operations in many ways. Table 13 lists the simple Boolean logic functions of bit circuit 400 in response to single function signals F7-F0. Since these are Boolean logic functions and the arithmetic enable signal is "0", both the generate and kill functions are disabled. Note that for Boolean extended arithmetic logic unit operations it is possible to specify the carry-in signals c in0 and c in1 from bit 0 carry-in generator 246 as previously described, thus permitting a carry ripple. 8-bit ALU code field Function Signal Logical Operation 58 F7 A & B & C 57 F6 ∼A & B & C 56 F5 A & ∼B & C 55 F4 ∼A & ∼B & C 54 F3 A & B & ∼C 53 F2 ∼A & B & ∼C 52 F1 A & ∼B & ∼C 51 F0 ∼A & ∼B & ∼C These functions can be confirmed by inspecting Figures 11 and 12. For the example of F7 = "1" and F6-F0 all equal to "0", invertors 441, 442, 443, 444, 446, 447 and 448 each output a "0". Only invertor 445 produces a "1" output. The propagate signal is "1" only if C i = "1" turning on pass gate 455, B i = "1" turning on pass gate 463 and A i = "1" turning on pass gate 472. All other combinations result in a propagate signal of "0". Since this is a logical operation, both the zero carry-in signal c in0 and the one carry-in signal c in1 are "0". Thus S i = "1" because both exclusive OR circuits 431 and 433 return the propagate signal. The other entries on Table 13 may be similarly confirmed. A total of 256 Boolean logic functions of the three inputs A, B and C are enabled by proper selection of function signals F7-F0. Note that the state table of three inputs includes 8 places, thus there are 2 8 = 256 possible Boolean logic functions of three inputs. Two input functions are subset functions achieved by selection of function signals F7-F0 in pairs. Suppose that a Boolean function of B and C, without relation to input A, is desired. Selection of F7 = F6, F5 = F4, F3 = F2 and F1 = F0 assures independence from input A. Note that the branches of Boolean function generator 403 connected to pass gates 471 and 472 are identically driven. This ensures that the result is the same whether A 1 = "1" or A 1 = "0". Such a selection still provides 4 controllable function pairs permitting specification of all 16 Boolean logic functions of inputs B and C. Note that the state table of two inputs includes four places, thus there are 2 4 = 16 possible Boolean logic functions of three inputs. Similarly, selection of F7 = F5, F6 = F4, F3 = F1 and F2 = F0 ensures independence from input B and provides 4 controllable function pairs for specification of 16 Boolean logic functions of inputs A and C. Selection of F7 = F3, F6 = F2, F5 = F1 and F4 = F0 permits selection via 4 controllable function pairs of 16 Boolean logic functions of inputs A and B independent of input C. The instruction word determines the function performed by arithmetic logic unit 230 and whether this operation is arithmetic or Boolean logic. As noted in Table 13, the instruction word includes a field coded with the function signals for Boolean logic operations. This field, the "8 bit arithmetic logic unit" field (bits 58-51) of the instruction word, is directly coded with the function signals when the instruction specifies a Boolean logic operation for arithmetic logic unit 230. The "8 bit arithmetic logic unit" field is differently coded when the instruction specifies arithmetic operations. Study of the feasible arithmetic functions indicates that a subset of these arithmetic functions specify the most often used operations. If the set of function signals F7-F0 is expressed as a two place hexadecimal number, then these most often used functions are usually formed with only the digits a, 9, 6 and 5. In these sets of function signals F7 = ∼F6, F5 = ∼F4, F3 = ∼F2 and F1 = ∼F0. Bits 57, 55, 53 and 51 specify fifteen operations, with an "8 bit arithmetic logic unit" field of all zeros reserved for the special case of non-arithmetic logic unit operations. Non-arithmetic logic unit operations will be described below. When executing an arithmetic operation function signal F6 = bit 57, function signal F4 = bit 55, function signal F4 = bit 53 and function signal F2 = bit 51. The other function signals are set by F7 = ∼F6, F5 = ∼F4, F3 = ∼F2 and F1 = ∼F0. These operations and their corresponding function signals are shown in Table 14. Table 14 also shows the modifications to the default coding. 8-bit ALU code field Derived Description of operation 5 5 5 5 Function FFFFFFFF Signal 7 5 3 1 76543210 Hex 0 0 0 0 10101010 AA reserved for non-arithmetic 0 0 0 1 10101001 A9 logic unit operations A-B shift left "1" extend 0 0 1 0 10100110 A6 A+B shift left "0" extend 0 0 1 1 10100101 A5 A-C 0 1 0 0 10011010 9A A-B shift right "1" extend if sign=0 flips to 95 A-B shift right sign extend 0 1 0 1 10011001 99 A-B 0 1 1 0 10010110 96 A+B/A-B depending on C if ∼@MF flips to 99 A-B if sign=1 A+|B| 0 1 1 1 10010101 95 A-B shift right "0" extend 1 0 0 0 01101010 6A A+B shift right "0" extend 1 0 1 1 01101001 69 A-B/A+B if ∼@MF flips to 66 A+B if sign=1 A-|B| 1 0 1 0 01100110 66 A+B 1 0 1 1 01100101 65 A+B shift right "1" extend if sign=0 flips to 6A A+B shift right sign extend 1 1 0 0 01011010 5A A+C 1 1 0 1 01011001 59 A-B shift left "0" extend 1 1 1 0 01010110 56 A+B shift left "1" extend 1 1 1 1 01100000 60 (A&C)+(B&C), field A+B Several codings of instruction word bits 57, 55, 53 and 51 are executed in modified form as shown in Table 14. Note that the functions that list left or right shifts are employed in conjunction with barrel rotator 235 and mask generator 238. These operations will be explained in detail below. The "sign" referred to in this description is bit 31 of arithmetic logic unit second input bus 206, the bus driving barrel rotator 235. This is the sign bit of a signed number. A "0" in this sign bit indicates a positive number and a "1" in this sign bit indicates a negative (two's complement) number. A bit 57, 55, 53 and 51 state of "0100" results in a normal function of A-B with shift right "1" extend. If bit 31 of arithmetic logic unit second input bus 206 is "0", then the operation changes to A-B with shift right sign extend. A bit 57, 55, 53 and 51 state of "0110" results in a normal function of A-B or A+B depending on the bit wise state of C. If the instruction does not specify a multiple flags register mask operation (@MF) then the operation changes to A-B. If bit 31 of arithmetic logic unit second input bus 206 is "1", then the operation changes to A+|B| (A plus the absolute value of B). A bit 57, 55, 53 and 51 state of "1011" results in a normal function of A+B or A-B depending on the bit wise state of C. If the instruction does not specify a multiple flags register mask operation (∼@MF) then the operation changes to A+B. If bit 31 of arithmetic logic unit second input bus 206 is "1", then the operation changes to A-|B| (A minus the absolute value of B). A bit 57, 55, 53 and 51 state of "1001" results in a normal function of A+B with shift right "1" extend. If bit 31 of arithmetic logic unit second input bus 206 is "0", then the operation changes to A+B with shift right sign extend. Two codes are modified to provide more useful functions. A bit 57, 55, 53 and 51 state of "0000" results in a normal function of ∼A (not A), which is reserved to support non-arithmetic logic unit operations as described below. A bit 57, 55, 53 and 51 state of "1111" results in a normal function of A. This is modified to (A&C)+(B&C) or a field add of A and B controlled by the state of C. The base set of operations listed in Table 14 may be specified in arithmetic instructions. Note that instruction word bits 58, 56, 54 and 52 control modifications of these basic operations as set forth in Table 6. These modifications were explained above in conjunction with Table 6 and the description of status register 210. As further described below certain instructions specify extended arithmetic logic unit operations. It is still possible to specify each of the 256 arithmetic operations via an extended arithmetic logic unit (EALU) operation. For these instructions the "A" (bit 27) of data register D0 specifies either an arithmetic or Boolean logic operation, the "EALU" field (bits 26-19) specifies the function signals F7-F0 and the "FMOD" field (bits 31-28) specifies modifications of the basic function. Also note that the "C", "I", "S", "N" and "E" fields of data register D0 permit control of the carry-in to bit 0 of arithmetic logic unit 230 and to the least significant bit of each section if multiple arithmetic is enabled. There are four forms of extended arithmetic logic unit operations. Two of these specify parallel multiply operations using multiplier 220. In an extended arithmetic logic unit true (EALUT) operation, the function signals F7-F0 equal the corresponding bits of the "EALU" field of data register D0. In an extended arithmetic logic unit false (EALUF) operation, the individual bits of the "EALU" field of data register D0 are inverted to form the function signals F7-F0. The extended arithmetic logic unit false operation is useful because during some algorithms the inverted functions signals perform a useful related operation. Inverting all the function signals typically specifies an inverse function. Thus this related operation may be accessed via another instruction without reloading data register 208. In the other extended arithmetic logic unit operations the function signals F7-F0 equal the corresponding bits of the "EALU" field of data register D0, but differing data paths to arithmetic logic unit 230 are enabled. These options will be explained below. Data unit 110 operation is responsive to instruction words fetched by program flow control unit 130. Instruction decode logic 250 receives data corresponding to the instruction in the execute pipeline stage via opcode bus 133. Instruction decode logic 250 generates control signals for operation of multiplexers Fmux 221, Imux 222, MSmux 225, Bmux 227, Amux 232, Cmux 233, Mmux 234 and Smux 231 according to the received instruction word. Instruction decode logic 250 also controls operation of buffers 104, 106, 108, 223 and 236 according to the received instruction word. Control lines for these functions are omitted for the sake of clarity. The particular controlled functions of the multiplexers and buffers will be described below on description of the instruction word formats in conjunction with Figure 18. Instruction decode logic 250 also supplies partially decoded signals to function signal generator 245 and bit 0 carry-in generator 246 for control of arithmetic logic unit 230. Particular hardware for this partial decoding is not shown, however, one skilled in the art would be able to provide these functions from the description of the instruction word formats in conjunction with Figure 18. Instruction decode logic 250 further controls the optional multiple section operation of arithmetic logic unit 230 by control of multiplexers 311, 312, 313 and 314, previously described in conjunction with Figure 7. Figure 13 illustrates details of the function signal selector 245a. Function signal selector 245a forms a part of function signal generator 245 illustrated in Figure 5. For a full picture of function signal generation, Figure 13 should be considered with the function signal modifier 245b illustrated in Figure 14. Multiplexers are shown by rectangles having an arrow representing the flow of bits from inputs to outputs. Inputs are designated with lower case letters. Control lines are labeled with corresponding upper case letters drawn entering the multiplexer rectangle perpendicular to the arrow. When a control line designated with a particular upper case letter is active, then the input having the corresponding lower case letter is selected and connected to the output of the multiplexer. Input "a" of multiplexer Omux 500 receives an input in two parts. Bits 57, 55, 53 and 51 of the instruction word are connected to bit lines 6, 4, 2 and 0 of input "a", respectively. Invertor 501 inverts the respective instruction word bits and supplies them to bit lines 7, 5, 3 and 1 of input "a". Input "a" is selected if control line "A" goes active, and when selected the eight input bit lines are connected to their eight corresponding numbered output bit lines 7-4 and 3-0. Control line "A" is fed by AND gate 502. AND gate 503 receives a first input indicating execution of an instruction in any of the instruction classes 7-0. Instruction word bit 63 indicates this. These instruction classes will be further described below. AND gate 502 has a second input fed by bit 59 of the instruction word. As will be explained below, a bit 59 equal to "1" indicates an arithmetic operation. NAND gate 503 supplies a third input to AND gate 502. NAND gate 503 senses when any of the four instruction word bits 57, 55, 53 or 51 is low. Control input "A" is thus active when any of the instruction classes 7-0 is selected, and arithmetic bit 59 of the instruction word is "1" and instruction word bits 57, 55, 53 and 51 are not all "1'". Recall from Table 14 that a bit 57, 55, 53 and 51 state of "1111" results in the modified function signals Hex "60" rather than the natural function signals. Input "b" to multiplexer Omux 500 is a constant Hex "60". Multiplexer Omux 500 selects this input if AND gate 504 makes the control "B" active. AND gate 504 makes control "B" active if the instruction is within classes 7-0 as indicate by instruction word bit 63, the instruction word bit 59 is "1" indicating an arithmetic operation, and a bit 57, 55, 53 and 51 state of "1111". As previously described in conjunction with Table 14, under these conditions the function Hex "60" is substituted for the function signals indicated by the instruction. Input "c" to multiplexer Omux 500 receives all eight instruction word bits 58-51. Multiplexer Omux 500 selects this input if AND gate 505 makes control "C" active. AND gate 505 receives instruction word bit 59 inverted via invertor 506 and an indication of any of the instruction classes 7-0. Thus instruction word bits 58-51 are selected to perform any of the 256 Boolean operations in instruction classes 7-0. Instruction words for the operations relevant to control inputs "D", "E", "F", "G" and "H" have bits 63-61 equal to "011". If this condition is met, then bits 60-57 define the type of operation. Input "d" to multiplexer Omux 500 is a constant Hex "66". This input is selected for instructions that execute a parallel signed multiply and add (MPYS ∥ ADD) or a parallel unsigned multiply and add (MPYU ∥ ADD). These instructions are collectively referred to by the mnemonic MPYx ∥ ADD. Input "e" to multiplexer Omux 500 is a constant Hex "99". This input is selected for instructions that execute a parallel signed multiply and subtract (MPYS ∥ SUB) or a parallel unsigned multiply and subtract (MPYU ∥ SUB). These instructions are collectively referred to by the mnemonic MPYx ∥ SUB. Input "f" to multiplexer Omux 500 is a constant Hex "A6". This input is selected for the DIVI operation. The operation of this DIVI operation, which is employed in division, will be further described below. Input "g" to multiplexer Omux 500 is supplied from the "EALU" field (bits 26-19) of data register D0 according to an extended arithmetic logic unit function code from bits 26-19 therein. Control input "G" goes active to select this "EALU" field from data register D0 if OR gate 507 detects either a MPYx ∥ EALUT operation or and an EALU operation. As previously described, the T suffix in EALUT signifies EALU code true in contrast to the inverse (false) in EALUF. The EALU input is active to control input "G" when the "EALU" field of data register D0 indicates either EALU or EALU%. Invertor 508 inverts the individual bits of the "EALU" field of data register D0 for supply to input "h" of multiplexer Omux 500. Input "h" of multiplexer Omux 500 is selected in response to detection of a MPYx ∥ EALUF operation at control input "H". As previously described, the F suffix of EALUF indicates that the individual bits of the "EALU" field of register D0 are inverted for specification of function signals F7-F0. Multiplexer AEmux 510, which is also illustrated in Figure 13, generates the arithmetic enable signal. This arithmetic enable signal is supplied to tri-state AND gate 480 of every bit circuit 400. The "a" input to multiplexer AEmux 510 is the "A" bit (bit 27) of data register D0. OR gate 511 receives three inputs: MPYx ∥ EALUT, EALU, and MPYx ∥ EALUF. If the instruction selects any of these three operations, then control input "A" to multiplexer AEmux selects the "A" bit (bit 27) of data register D0. The "b" input to multiplexer AEmux 510 is the "ari" bit (bit 59) of the instruction word. As will be described below, this "ari" bit selects arithmetic operations for certain types of instructions. This input is selected if the instruction is any of the instruction classes 7-0. In this case the "ari" bit signifying an arithmetic operation ("ari"="1") or a Boolean operation ("ari"="0") is passed directly to the arithmetic logic unit 230. The "c" input of multiplexer AEmux 510 is a constant "1". The gate 512 selects this input if the instruction is neither an extended arithmetic logic unit instruction nor within instruction classes 7-0. Such instructions include the DIVI operation and the MPYx ∥ ADD and MPYx ∥ SUB operations. OR gate 513 provides an arithmetic or EALU signal when the instruction is either an arithmetic operation as indicated by the output of multiplexer AEmux 510 or an "any EALU" operation as indicated by OR gate 511. Figure 14 illustrates function signal modifier 245b. Function signal modifier 245b modifies the function signal set from function signal generator 245a according to the "FMOD" field of data register D0 or the instruction bits 58, 56, 54 and 52 depending on the instruction. Multiplexer Fmux 520 selects the function modifier code. The "a" input to multiplexer Fmux 520 is all "0's" (Hex "0"). NOR gate 521 supplies control line "A" of multiplexer Fmux 520. NOR gate 521 has a first input receiving the "any EALU" signal from OR gate 511 illustrated in Figure 13 and a second input connected to the output of AND gate 522. AND gate 522 receives a first input from the "ari" bit (bit 59) of the instruction word and a second input indicating the instruction is in instruction classes 7-0. Thus NOR gate 521 generates an active output that selects the Hex "0" input to Fmux 520 if the instruction is not any extended arithmetic logic unit operation and either the "ari" bit of the instruction word is "0" or the instruction is not within instruction classes class 7-0. The "b" input to multiplexer Fmux 520 receives bits 58, 56, 54 and 52 of the instruction word. The control input "B" receives the output of AND gate 522. Thus multiplexer Fmux 520 selects bits 58, 56, 54 and 52 of the instruction word when the instruction is in any instruction class 7-0 and the "ari" bit of the instruction is set. The "c" input of multiplexer Fmux 520 receives bits of the "FMOD" field (bits 31-28) of data register D0. The control input "C" receives the "any EALU" signal from OR gate 511. Multiplexer Fmux 520 selected the "FMOD" field of data register D0 if the instruction calls for any extended arithmetic logic unit operation. Multiplexer Fmux 520 selects the active function modification code. The active function modification code modifies the function signals supplied to arithmetic logic unit 230 as described below. The function modification code is decoded to control the operations specified in Table 6. As explained above, these modified operations include controlled splitting of arithmetic logic unit 230, setting one or more bits of multiple flags register 211 by zero(es) or carry-out(s) from arithmetic logic unit 230, rotating or clearing multiple flags register 211, operating LMO/RMO/LMBC/RMBC circuit 237 in one of its four modes, operating mask generation 239 and operating bit 0 carry-in generator 246. The operations performed in relation to a particular state of the function modification code are set forth in Table 6. Three circuit blocks within function modifier 245b may modify the function signals F7-F0 from multiplexer Omux 500 illustrated in Figure 13. Mmux block 530 may operate to effectively set the input to the C-port to all "1's". A-port block 540 may operate to effectively set the input to the A-port to all "0's". Sign extension block 550 is a sign extension unit that may flip function signals F3-F0. Mmux block 530 includes a multiplexer 531 that normally passes function signals F3-F0 without modification. To effectively set the input to the C-port of arithmetic logic unit 230 to "1's", multiplexer 531 replicates function signals F7-F4 onto function signals F3-F0. Multiplexer 531 is controlled by AND gate 533. AND gate 533 is active to effectively set the input to the C-port to all "1's" provided all three of the following conditions are present: 1) the function modifier code multiplexer Fmux 520 is any of the four codes "0010", "0011", "0110" or "0111" as detected by "0X1X" match detector 532 (X = don't care); 2) the instruction calls for a mask generation operation; and 3) the output from multiplexer Mmux 234 is "0". As previously described above, duplication of functions signals F7-F4 onto function signals F3-F0, that is selection of F7 = F3, F6 = F2, F5 = F1 and F4 = F0, enables selection of the 16 Boolean logic functions of inputs A and B independent of input C. Note from Table 6 that the four function modifier codes "0X1X" include the "%!" modification. According to Figure 14, the "%!" modification is achieved by changing the function signals sent to arithmetic logic unit 230 rather than by changing the mask generated by mask generator 239. A-port block 540 includes multiplexer 541 and connection circuit 542 that normally pass function signals F7-F0 without modification. To effectively set the input to the A-port of arithmetic logic unit 230 to all "0's", multiplexer 541 and connection circuit 541 replicates function signals F6, F4, F2 and F0 onto function signals F7, F5, F3 and F1, respectively. Multiplexer 541 and connection circuit 542 make this substitution when activated by OR gate 544. OR gate 544 has a first input connected to "010X" match detector 543, and a second input connected to AND gate 546. AND gate 546 has a first input connected to "011X" match detector 545. Both match detectors 543 and 545 determine whether the function modifier code matches their detection state. AND gate 546 has a second input that receives a signal indicating whether the instruction calls for a mask generation operation. The input to the A-port of arithmetic logic unit 230 is effectively zeroed by swapping function signals F6, F4, F2 and F0 for function signals F7, F5, F3 and F1, respectively. As previously described, this substitution makes the output of arithmetic logic unit 230 independent of the A input. This substitution takes place if: 1) the function modifier code finds a match in "010X" match detector 543; or 2) the instruction calls for a mask generation operation and the function modifier code find a match in "010X" match detector 545 and the instruction calls for a mask generation operation. Sign extension block 550 includes exclusive OR gate 551, which normally passes function signals F3-F0 unmodified. However, these function signals F3-F0 are inverted for arithmetic logic unit sign extension and absolute value purposes under certain conditions. Note that function signals F7-F4 from A-port block 540 are always passed unmodified by sign extension block 550. AND gate 552 controls whether exclusive OR gate 551 inverts function signals F3-F0. AND gate 552 has a first input receiving the arithmetic or extended arithmetic logic unit signal from OR gate 513 illustrated in Figure 13. The second input to AND gate 552 is from multiplexer 553. Multiplexer 553 is controlled by the "any EALU" signal from OR gate 511 of Figure 13. Multiplexer 553 selects a first signal from AND gate 554 when the "any EALU" signal is active and selects a second signal from compound AND/OR gate 556 when the "any EALU" signal is inactive. The output of AND gate 554 equals "1" when the data on arithmetic logic unit second input bus 206 is positive, as indicated by the sign bit (bit 31) as inverted by invertor 555, and the "S" bit (bit 16) of data register D0 is "1". The output of compound AND/OR gate 556 is active if: 1) the data on arithmetic logic unit second input bus 206 is positive, as indicated by the sign bit (bit 31) as inverted by invertor 555; 2) the instruction is within instruction classes 7-0; and 3) either a) instruction bits 57, 55, 53 and 51 find a match in "0100"/"1011" match detector 557 or b) AND gate 560 detects that instruction word bits 57, 55, 53 and 51 find a match in "1001"/"0110" match detector 558, and the instruction does not call for a multiple flags register mask operation (@MF) as indicated by invertor 559. Sign extension block 550 implements the exceptions noted in Table 14. An inactive "any EALU" signal, which indicates that the instruction specified an arithmetic operation, selects the second input to multiplexer 553. Compound AND/OR gate 556 determines that the instruction is within instruction classes 7-0 and that the sign bit is "0". Under these conditions, if instruction word bits 57, 55, 53 and 51 equal "0100" and then the function signal flips from Hex "9a" to Hex "95" by inverting function signal bits F3-F0. Similarly, if instruction word bits 57, 55, 53 and 51 equal "1011" and then the function signal flips from Hex "65" to Hex "6a" by inverting function signal bits F3-F0. If instruction word bits 57, 55, 53 and 51 equal "1001" and the instruction does not call for a multiple flags register mask operation as indicated by invertor 599, then the function signal flips from Hex "69" to Hex "66". This set of function signals causes arithmetic logic unit 230 to implement A-|B|, A minus the absolute value of B. If instruction word bits 57, 55, 53 and 51 equal "0110" and the instruction does not call for a multiple flags register mask operation, then the function signal flips from Hex "96" to Hex "99". This executes the function A+|B|, A plus the absolute value of B. Note that these flips of the function signals are based on the sign bit (bit 31) of the data on arithmetic logic unit second input bus 206. Figure 15 illustrates bit 0 carry-in generator 246. As previously described bit, 0 carry-in generator 246 produces the carry-in signal c in supplied to the first bit of arithmetic logic unit 230. In addition this carry-in signal c in from bit 0 carry-in generator 246 is generally supplied to the first bit of each of the multiple sections, if the instruction calls for a multiple arithmetic logic unit operation. Multiplexer Zmux 570 selects one of six possible sources for this bit 0 carry-in signal c in based upon six corresponding controls inputs from instruction decode logic 250. Input "a" of multiplexer Zmux 570 is supplied with bit 31 of multiple flags register 211. Multiplexer Zmux 570 selects this input as the bit 0 carry-in signal c in if the instruction calls for a DIVI operation. Inputs "b", "c" and "d" to multiplexer Zmux 570 are formed of compound logic functions. Input "b" of multiplexer Zmux 570 receives a signal that is a Boolean function of the function signals F6, F2 and F0. This Boolean expression, which is formed by circuit 571, is (F0 & ∼F6) | (F0 & ∼F2) | (∼F2 & ∼F6). Input "c" of multiplexer Zmux 570 is fed by exclusive OR gate 572, which has a first input supplied by exclusive OR gate 573 and a second input supplied by AND gate 574. The exclusive OR gate 573 has as a first input the "C" bit (bit 18) of data register D0, which indicates whether the prior operation of arithmetic logic unit 230 produced a carry-out signal c out at bit 31, the last bit. The second input of XOR gate 573 receives a signal indicating the instruction calls for a MPYx ∥ EALUF operation. AND gate 574 has a first input from invertor 575 inverting the sign bit (bit 31) present on arithmetic logic unit second input bus 206 for detecting a positive sign. AND gate 574 has a second input from the "I" bit (bit 17) of data register D0 and a third input from the "S" bit (bit 16) of data register D. As explained above, the "I" bit causes inversion of carry-in when the "S" bit indicates sign extend is enabled. This operation complements the sign extend operation of AND gate 554 and XOR gate 551 of the function modifier 246b illustrated in Figure 14. Input "d" of multiplexer Zmux 570 comes from XOR gate 576. XOR gate 576 has a first input supplied the function signal F0 and a second input supplied bit 0 of the data on input C bus 243. Input "b" of multiplexer Zmux 570 is selected when AND gate 581 sets control input "B" active. This occurs when the "arithmetic or EALU" from OR gate 513 is active, the instruction does not call for an extended arithmetic logic unit operation as indicated by invertor 582 and no other multiplexer Zmux 570 input is applicable as controlled by invertors 583, 584 and 585. Input "c" of multiplexer Zmux 570 is selected when AND gate 586 supplies an active output to control input "C". AND gate 586 is responsive to a signal indicating the instruction calls for "any EALU" operation. The rest of the inputs to AND gate 586 assure that AND gate 586 is not active if any of inputs "d", "e" or "f" are active via invertors 584, 585 and 595. Input "d" of multiplexer Zmux 570 is selected when control line "D" is from AND gate 587. AND gate 587 is active when the instruction is an arithmetic operation or an extended arithmetic logic unit operation, AND gate 589 is active and input "e" is not selected as indicated by invertor 585. AND gate 589 is active when the instruction specifies a multiple flags register mask operation (@MF) expansion and instruction word bits 57, 55, 53 and 51 find a match in "0110"/"1001" match circuit 588. These instruction word bits correspond to function signals Hex "69" and Hex "96", which cause addition or subtraction between ports A and B depending on the input to port C. No function signal flipping is involved since the instruction class involves multiple flags register expansion. Figure 7 illustrates providing this carry-in signal to plural sections of a split arithmetic logic unit in multiple mode. Input "e" of multiplexer Zmux 570 comes from the "C" bit (bit 30) of status register 210. As previously described, this "C" bit of status register 210 is set to "1" if the result of the last operation of arithmetic logic unit 230 caused a carry-out from bit 31. AND gate 594 supplies control input "E". AND gate 594 goes active when the instruction specifies an arithmetic operation or an extended arithmetic logic unit operation and the following logic is true: 1) the function modifier code finds a match in "0X01" match detector 591; or (OR gate 590) 2) the instruction calls for a mask generation operation and (AND gate 593) the function modifier code finds a match in "0X11" match detector 592. Input "f" of multiplexer Zmux 570 is supplied with a constant "0". Multiplexer Zmux 570 selects this input when the "arithmetic or EALU" signal from OR gate 513 indicates the instruction specifies a Boolean operation as inverted by invertor 595. The output of Zmux 570 normally passes through Ymux 580 unchanged and appears at the bit 0 carry-in output. In a multiple arithmetic operation in which data register D0 "A" bit (bit 27) and "E" bit (bit 14) are not both "1", Ymux produces plural identical carry-in signals. Selection of half word operation via "Asize" field of status register 210 causes Ymux to produce the supply the output of Zmux 570 to both the bit 0 carry-in output and the bit 16 carry-in output. Likewise, upon selection of byte operation Ymux 580 supplies the output of Zmux 570 to the bit 0 carry-in output, the bit 8 carry-in output, the bit 16 carry-in output and the bit 24 carry-in output. The operation of Ymux 580 differs when data register D0 "A" bit (bit 27) and "E" bit (bit 14) are both "1". AND gate 577 forms this condition and controls the operation of Ymux 580. This is the only case in which the carry-in signals supplied to different sections of arithmetic logic unit 230 during multiple arithmetic differ. If AND gate 577 detects this condition, then the carry-in signals are formed by the exclusive OR of function signal F0 and the least significant bit of the C input of the corresponding section of arithmetic logic unit 230. If the "Asize" field selects word operation, that is if arithmetic logic unit 230 forms a single 32 bit section, then the bit 0 carry-in output formed by Ymux 580 is the exclusive OR of function signal F0 and input C bus bit 0 formed by XOR gate 596. No other carry-in signals are formed. If the "Asize" field selects half word operation forming two 16 bit sections, then the bit 0 carry-in output formed by Ymux 580 is the output of XOR gate 596 and the carry-in to bit 16 is the exclusive OR of function signal F0 and input C bus bit 16 formed by XOR gate 598. Lastly, for byte multiple arithmetic the bit 0 carry-in output formed by Ymux 580 is the output of XOR gate 596, the bit 8 carry-in is formed by XOR gate 597, and the bit 16 carry-in is formed by XOR gate 598 and the bit 24 carry-in is formed by XOR gate 599. Figures 13, 14 and 15 not only represent specific blocks implementing the Tables but also illustrates the straightforward process by which the Tables and Figures compactly define logic circuitry to enable the skilled worker to construct the preferred embodiment even when a block diagram of particular circuitry may be absent for conciseness. Note that the circuits of Figures 13 and 14 do not cover control for the various multiplexers and special circuits via instruction decode logic 250 that are a part of data unit 110 illustrated in Figure 5. However, control of these circuits is straight forward and within the capability of one of ordinary skill in this art. Therefore these will not be further disclosed for the sake of brevity. Arithmetic logic unit 230 includes three 32 bit inputs having differing hardware functions preceding each input. This permits performance of many different functions using arithmetic logic unit 230 to combine results from the hardware feeding each input. Arithmetic logic unit 230 performs Boolean or bit by bit logical combinations, arithmetic combinations and mixed Boolean and arithmetic combinations of the 3 inputs. Mixed Boolean and arithmetic functions will hereafter be called arithmetic functions due to their similarity of execution. Arithmetic logic unit 230 has one control bit that selects either Boolean functions or arithmetic functions. Boolean functions generate no carries out of or between bit circuits 400 of arithmetic logic unit 230. Thus each bit circuit 400 of arithmetic logic unit 230 combines the 3 inputs to that bit circuit independently forming 32 individual bit wise results. During arithmetic functions, each bit circuit 400 may receive a carry-in from the adjacent lesser significant bit and may generate a carry-out to the next most significant bit location. An 8 bit control signal (function control signals F7-F0) control the function performed by arithmetic logic unit 230. This enables selection of one of 256 Boolean functions and one of 256 arithmetic functions. The function signal numbering of function signals F7-F0 is identical to that used in Microsoft® Windows. Bit 0 carry-in generator 246 supplies carry-in signals when in arithmetic mode. In arithmetic mode, arithmetic logic unit 230 may be split into either two independent 16 bit sections or four independent 8 bit sections to process in parallel multiple smaller data segments. Bit 0 carry-in generator 246 supplies either one, two or four carry-in signals when arithmetic logic unit 230 operates in one, two or four sections, respectively. In the preferred embodiment, an assembler for data unit 110 includes an expression evaluator that selects the proper set of function signals based upon an algebraic input syntax. The particular instruction being executed determines the function of arithmetic logic unit 230. As will be detailed below, in the preferred embodiment the instruction word includes a field that indicates either Boolean or arithmetic operations. Another instruction word field specifies the function signals supplied to arithmetic logic unit 230. Boolean instructions specify the 8 function signals F7-F0 directly. In arithmetic instructions a first subset of this instruction word field specifies a subset of the possible arithmetic logic unit operations according to Table 14. A second subset of this instruction word field specifies modifications of instruction function according to Table 6. All possible variations of the function signals and the function modifications for both Boolean and arithmetic instructions may be specified using an extended arithmetic logic unit (EALU) instruction. In this case the predefined fields within data register D0 illustrated in Figure 9 specify arithmetic logic unit 230 operation. Though arithmetic logic unit 230 can combine all three inputs, many useful functions don't involve some of the inputs. For example the expression A&B treats the C input as a don't care, and the expression A|C treats the B input as a don't care. Because different data path hardware precedes each input, the ability to use or ignore any the inputs supports the selection of data path hardware needed for the desired function. Table 15 shows examples of useful three input expressions where the C-input is treated as a mask or a merging control. Because data unit 110 includes expand circuit 238 and mask generator 239 in the data path of the C-input of arithmetic logic unit 230, it is natural to employ the C-input as a mask. Logical Function Typical use (A&C)|(B&∼C) Bit by bit multiplexing (merge) of A and B based on C. A chosen if corresponding bit in C is 1 (A&∼C)|(B&C) Bit by bit multiplexing (merge) of A and B based on C. B chosen if corresponding bit in C is 1 (A|B)&∼C Logic OR of A and B and then force to 0 everywhere that C is a 1 (A&B)&∼C Logic AND of A and B and then force to 0 everywhere C is a 1 A|(B&C) If C is 0 then force the B-input to 0 before logical ORing with A A|(B|∼C) If C is 0 then force the B-input to 1 before logical ORing with A The three input arithmetic logic unit 230 can perform mixed Boolean and arithmetic functions in a single pass through arithmetic logic unit 230. The mixed Boolean and arithmetic functions support performing Boolean functions prior to an arithmetic function. Various compound functions such as shift and add, shift and subtract or field masking prior to adding or subtracting can be performed by the appropriate arithmetic logic unit function in combination with other data path hardware. Note arithmetic logic unit 230 supports 256 different arithmetic functions, but only a subset of these will be needed for most programming. Additionally, further options such as carry-in and sign extension need to be controlled. Some examples expected to be commonly used are listed below in Table 16. Func Code Hex Function Default Carry-In Common Use 66 A+B 0 A+B ignore C 99 A-B 1 A-B ignore C 5A A+C 0 A+C ignore B A5 A-C 1 A-C ignore B 6A A+(B&C) 0 A+B shift right "0" extend C shift mask 95 A-(B&C) 1 A-B shift right "0" extend C shift mask 56 A+(B|C) 0 A+B shift left "0" extend C shift mask A9 A-(B|C) 1 A-B shift left "1" extend C shift mask A6 A+(B&∼C) 0 A+B shift left "0" extend C shift mask 59 A-(B&∼C) 1 A-B shift left "0" extend C shift mask 65 A+(B|∼C) 0 A+B shift right sign extend C shift mask 9A A-(B|∼C) 1 A-B shift right sign extend C shift mask 60 (A&C)+(B&C) 0 A+B mask by C 9F (A&C)-(B&C) 1 A-B mask by C 06 (A&∼C)+(B&∼C) 0 A+B mask by ∼C F9 (A&∼C)-(B&∼C) 1 A-B mask by ∼C 96 A+((-B&C)|(B&∼C)) LSB of C A+B or A-B based on ∼C 69 A+((B&C)|(-B&∼C)) LSB of ∼C A+B or A-B based on C CC B 0 B ignore A and C 33 -B 1 Negative B ignore A and C F0 C 0 C ignore A and B 0F -C 1 Negative C ignore A and B C0 (B&C) 0 B shift right "0" extend C shift mask 3F -(B&C) 1 Negative B shift right "0" extend C shift mask FC (B|C) 0 B shift left "1" extend C shift mask 03 -(B|C) 1 Negative B shift left "1" extend C shift mask 0C (B&∼C) 0 B shift left "0" extend C shift mask F3 -(B&∼C) 1 Negative B shift left "0" extend C shift mask CF (B|∼C) 0 B shift right sign extend C shift mask 30 -(B|∼C) 1 Negative B shift right sign extend C shift mask 3C (-B&C)|(B&∼C) LSB of C -B or B based on ∼C C3 (B&C)|(-B&∼C) LSB of ∼C B or -B based on C The most generally useful set of arithmetic functions combined with default carry-in control and sign extension options are available directly in the instruction set in a base set of operations. These are listed in Table 14. This base set include operations that modify the arithmetic logic unit's functional controls based on sign bits and that use default carry-in selection. Some examples of these are detailed below. All 256 arithmetic functions along with more explicit carry-in and sign extension control are available via the extended arithmetic logic unit (EALU) instruction. In extended arithmetic logic unit instructions the function control signals, the function modifier and the explicit carry-in and sign extension control are specified in data register D0. The coding of data register D0 during such extended arithmetic logic unit instructions is described above in relation to Figure 9. Binary numbers may be designated as signed or unsigned. Unsigned binary numbers are non-negative integers within the range of bits employed. An N bit unsigned binary number may be any integer between 0 and 2 N -1. Signed binary numbers carry an indication of sign in their most significant bit. If this most significant bit is "0" then the number is positive or zero. If the most significant bit is "1" then the number is negative or zero. An N bit signed binary number may be any integer from -2 N-1 -1 to 2 N-1 -1. Knowing how and why numbers produce a carry out or overflow is important in understanding operation of arithmetic logic unit 230. The sum of two unsigned numbers overflows if the sum can no longer be expressed in the number of bits used for the numbers. This state is recognized by the generation of a carry-out from the most significant bit. Note that arithmetic logic unit 230 may be configured to operation on numbers of 8 bits, 16 bits or 32 bits. Such carry-outs may be stored in Mflags register 211 and employed to maintain precision. The difference of two unsigned numbers underflows when the difference is less than zero. Note that negative numbers cannot be expressed in the unsigned number notation. The examples below show how carry-outs are generated during unsigned subtraction. The first example shows 7 "00000111" minus 5 "00000110". Arithmetic logic unit 230 performs subtraction by two's complement addition. The two's complement of an unsigned binary number can be generated by inverting the number and adding 1, thus -X = ∼X+1. Arithmetic logic unit 230 negates a number by logically inverting (or one's complementing) the number and injecting a carry-in of 1 into the least significant bit. First the 5 is bit wise inverted producing the one's complement "11111001". Arithmetic logic unit 230 adds this to 7 with a "1" injected into the carry-in input of the first bit. This produces the following result. Note that this produces a carry-out of "1" from the most significant bit. In two's complement subtraction, such a carry-out indicates a not-borrow. Thus there is no underflow during this subtraction. The next example shows 7-5. Note that the 8 bit one's complement of "00000111" is "11111000". In this case the carry-out of "0" indicates a borrow, thus the result is less than zero and an underflow has occurred. The last example of unsigned subtraction is 0-0. Note that the 8 bit one's complement of 0 is "11111111". The production of a carry-out of "1" indicates no underflow. The situation for signed numbers is more complex. An overflow on a signed add occurs if both operands are positive and the sign bit of the result is a 1 (i.e., negative) indicating that the result has rolled over from positive to negative. Overflow on an add also occurs if both operands are negative and the result has a 0 (i.e., positive) sign bit. Or in other words overflow on addition occurs if both of the sign bits of the operands are the same and the result has a different sign bit. Similarly a subtraction of can overflow if the operands have the same sign and the result has a different sign bit. When setting the carry bit in status register 210 or in the Mflags register 211, the bit or bits are always the "natural" carry outs generated by arithmetic logic unit 230 Most other microprocessors set "carry status" based upon the carry-out bit during addition but set it based upon not-carry-out (or borrow) during subtraction. These other microprocessors must re-invert the not-carry when performing subtract with borrow to get the proper carry-in to the arithmetic logic unit. This difference results in a slightly different set of conditional branch equations using this invention than other processors to get the same branch conditions. Leaving the sense of carries/not-borrows the same as those generated by arithmetic logic unit 230 simplifies many ways in which each digital image/graphics processor can utilize them. In the base set of arithmetic instructions, the default carry-in is "0" for addition and "1" for subtraction. The instruction set and the preferred embodiment of the assembler will automatically set the carry-in correctly for addition or subtraction in 32-bit arithmetic operations. The instruction set also supports carry-in based on the status registers carry-out to support multiple precision add-with-carry or subtract-with-borrow operations. As will be explained in more detail later, some functions arithmetic logic unit 230 support the C-port controlling whether the input to the B-port is added to or subtracted from the input to the A-port. Combining these arithmetic logic unit functions with multiple arithmetic permits the input to the C-port to control whether each section of arithmetic logic unit 230 adds or subtracts. The base set of operations controls the carry-in to each section of arithmetic logic unit 230 to supply a carry-in of "0" that section is performing addition and a carry-in of "1" if that section is performing subtraction. The hardware for supplying the carry-in to these sections is described above regarding Figure 15. The following details the full range of arithmetic functions possible using digital image/graphics processor 71 3-input arithmetic logic unit 230. For most algorithms, the subset of instructions listed above will be more than adequate. The more detailed description following is included for completeness. Included in the description below is information about how to derive the function code for arithmetic logic unit 230. Some observations about function code F7-F0 will be helpful in understanding how arithmetic logic unit 230 can be used for various operations and how to best use extended arithmetic logic unit instructions. The default carry-in is equal to F0, the least significant bit of the function code, except for the cases where the input to the C-port controls selection of addition or subtraction between A and B. Inverting all the function code bits changes the sign of the operation. For example the function codes Hex "66", which specifies A+B, and Hex "99", which specifies A-B, are bit wise inverses. Similarly, function code Hex "65" (A+(B|∼C)) and Hex "9A" (A-(B|∼C)) are bit wise inverses. Extended arithmetic logic unit instructions come in the pairs of extended arithmetic logic unit true (EALUT) and extended arithmetic logic unit false (EALUF). The extended arithmetic logic unit false instruction inverts the arithmetic logic unit control code stored in bits 26-19 of data register D0. As noted above, this inversion generally selects between addition and subtraction. Inverting the 4 least significant bits of the function code Hex "6A" for A+(B&C) yields gives Hex "65" that is the function A+(B|∼C). Similarly, inverting the 4 least significant bits of function code Hex "95" for A-(B&C) yields the function code Hex "9A" that is A-(B|∼C). The B&C operation zero's bits in B where C is "0" and the operation B|∼C forces bits in B to "1" where C is "0". This achieves the opposite masking function with respect to C. As will be explained below selectively inverting the 4 least significant bits of the function code based on a sign bit performs sign extension before addition or subtraction. All the 256 arithmetic functions available employing arithmetic logic unit 230 can be expressed as: S = A & F1(B,C) + F2(B,C) where: S is the arithmetic logic unit resultant; and F1(B,C) and F2(B,C) can be any of the 16 possible Boolean functions of B and C shown below in Table 17. F1 Code F2 Code Subfunction Common Use 00 00 0 Zeros term AA FF all 1's = -1 Sets term to all 1's 88 CC B B 22 33 -B-1 Negate B A0 F0 C C 0A 0F -C-1 Negate C 80 C0 B&C Force bits in B to 0 where C is 0 2A 3F -(B&C)-1 Force bits in B to 0 where C is 0 and negate A8 FC B|C Force bits in B to 1 where C is 1 02 03 -(B|C)-1 Force bits in B to 1 where C is 1 and negate 08 0C B&∼C Force bits in B to 0 where C is 1 A2 F3 -(B&∼C)-1 Force bits in B to 0 where C is 1 and negate 8A CF B|∼C Force bits in B to 1 where C is 0 20 30 -(B|∼C)-1 Force bits in B to 1 where C is 0 and negate 28 3C (B&∼C)|((-B-1)&C) Choose B if C=all 0's and -B if C=all 1's 82 C3 (B&C)|((-B-1)&∼C) Choose B is C=all 1's and -B if C=all 0's Figure 16 illustrates this view of arithmetic logic unit 230 in block diagram form. Arithmetic unit 491 forms the addition of the equation. Arithmetic unit 491 receives a carry input for bit 0 from bit 0 carry-in generator. The AND gate 492 forms A AND F1(B,C). Logic unit 493 forms the subfunction F1(B,C) from the function signals as listed in Table 17. Logic unit 494 forms the subfunction F2(B,C) from the function signals as listed in Table 17. This illustration of arithmetic logic unit 230 shows that during mixed Boolean and arithmetic operations the Boolean functions are performed before the arithmetic functions. A set of the bit circuits 400 illustrated in Figures 10, 11 and 12 together with the function generator illustrated in Figure 13, the function modifier illustrated in Figure 14 and the bit 0 carry-in generator illustrated in Figure 15 form the preferred embodiment of the arithmetic logic unit 230 illustrated in Figure 16. Those skilled in the art would recognize that there are many other feasible ways to implement arithmetic logic unit 230 illustrated in Figure 16. As clearly illustrated in Figure 16, the subfunctions F1(B,C) and F2(B,C) are independent and may be different subfunctions for a single operation of arithmetic logic unit 230. The subfunction F2(B,C) includes both the negative of B and the negative of C. Thus either B or C may be subtracted from A by adding its negative. The codes for the subfunctions F1(B,C) and F2(B,C) enable derivation of the function code F7-F0 for arithmetic logic unit 230 illustrated in Figures 11 and 12. The function code F7-F0 for arithmetic logic unit 230 is the exclusive OR of the codes for the corresponding subfunctions F1(B,C) and F2(B,C). Note the codes for the subfunctions have been selected to provide this result, thus these subfunctions do not have identical codes for the same operation. The subfunctions of Table 17 are listed with the most generally useful ways of expression. There are other ways to represent or factor each function. For example by applying DeMorgan's Law, the function B|∼C is equivalent to ∼(∼B&C). Because ∼X = -X-1, ∼(∼B&C) is equivalent -(∼B&C)-1 and B|∼C is equivalent to B|(-C-1). Note that the negative forms in Table 17 each have a trailing "-1" term. As explained above negative numbers are two's complements. These are equivalent to the bit wise logical inverse, which forms the 1's complement, minus 1. A carry-in of "1" may be injected into the least significant bit to cancel out the -1 and form the two's complement. In the most useful functions with a negative subfunction, only the F2(B,C) subfunction produces a negative. Often it will be convenient to think of the Boolean subfunctions in Table 17 as performing a masking operation. As noted in Table 17, the subfunction B&C can be interpreted as forcing the B input value to "0" where the corresponding bit in C is "0. The subfunction B|∼C can be interpreted as forcing the B input value to "1" for every bit where the C input is "0". Because mask generator 234 and expand circuit 238 feed the C-port of arithmetic logic unit 230 via multiplexer 233, in most cases the C-port will be used as a mask in subfunctions that involve both B and C terms. Table 17 has factored the expression of each subfunction in terms assuming that the input to the C-port is used as a mask. The equation above shows that the A-input cannot be negated in the arithmetic expression. Thus arithmetic logic unit 230 cannot subtract A from either B or C. On the other hand, either B or C can be subtracted from A because the subfunctions F1(B,C) and F2(B,C) support negation/inversion of B and C. The subfunctions of Table 17 when substituted into the above equation produces all of the 256 possible arithmetic functions that arithmetic logic unit 230 can perform. Occasionally, some further reduction in the expression of the resultant yields an expression that is equivalent to the original and easier to understand. When reducing such expressions, several tips can be helpful. The base instruction set defaults to a carry-in of "0" for addition and a carry-in of "1" when the subfunction F2(B,C) has a negative B or C term as expressed in Table 17. This carry-in injection has the effect of turning the one's complement (logical inversion) into a two's complement by effectively canceling the -1 on the right hand side of the expression of these subfunctions. The logic AND of A all "1's" equals A. Thus subfunction F1(B,C) may be set to yield all "1's" to get A on the left side of the equation. Note also that all "1's" equals two's complement signed binary number minus 1 (-1). The examples below show how to use the equation and the subfunctions of Table 17 to derive any of the possible arithmetic logic unit functions and their corresponding function codes. The arithmetic function A+B can be expressed as A&(all "1's")+B. This requires F1(B,C) = all "1's" and F2(B,C) = B. The F1 code for all "1's" is Hex "AA" and the F2 code for B is Hex "CC". Bit-wise XORing Hex "AA" and Hex "CC" gives Hex "66". Table 16 shows that Hex "66" is function code for A+B. The arithmetic function A-B can be expressed as A&(all "1's")+(-B-1)+1. This implies F1(B,C) = all "1's" (F1 code Hex "AA") and F2(B,C) = -B-1 (F2 code Hex "33") with a carry-in injection of "1". Recall that a carry-in of "1" is the default for subfunctions F2 that include negation. Bit-wise XORing the F1 code of Hex "AA" and with the F2 code of Hex "33" gives Hex "99". Table 16 shows that Hex "99" is the function code for A-B assuming a carry-in of "1". The arithmetic function A+C is derived similarly to A+B. Thus A+C = A&(all "1's")+C. This can be derived by choosing F1(B,C) = all "1's" and F2(B,C)=C. The exclusive OR of the F1 code of Hex "AA" and the F2 code of Hex "F0" produces Hex "5A" the function code for A+C. Likewise, A-C is the same as A&(all "1's")+(-C-1)+1. The exclusive OR of the F1 code of Hex "AA" and the F2 code of Hex "0F" produces Hex "A5" the function code for A-C. Three input arithmetic logic unit 230 provides a major benefit by providing masking and/or conditional functions between two of the inputs based on the third input. The data path of data unit 110 enables the C-port to be most useful as a mask using mask generator 234 or conditional control input using expand circuit 238. Arithmetic logic unit 230 always performs Boolean functions before arithmetic functions in any mixed Boolean and arithmetic function. Thus a carry could ripple out of unmasked bits into one or more bits that were zeroed or set by a Boolean function. The following examples are useful in masking and conditional operations. The function A+(B&C) can be expressed as A&(all "1's")+(B&C). Choosing F1(B,C) all "1's" (F1 code of Hex "AA") and F2(B,C)=B&C (F2 code of Hex "C0") gives A+(B&C). The bit-wise exclusive OR of HEX "AA" and Hex "C0" gives the arithmetic logic unit function code of Hex "6A" listed in Table 16. This function can strip off bits from unsigned numbers. As shown below, this function can be combined with barrel rotator 235 and mask generator 234 in performing right shift and add operations. In this case C acts as a bit mask that zeros bits of B everywhere C is "0". Since mask generator 234 can generate a mask with right justified ones, selection of mask generator 234 via multiplexer Cmux 233 permits this function to zero some of the most significant bits in B before adding to A. Another use of this function is conditional addition of B to A. Selection of expand circuit 238 via multiplexer Cmux 233 enables control of whether B is added to A based upon bits in Mflags register 211. During multiple arithmetic, bits in Mflags register 211 can control corresponding sections of arithmetic logic unit 230. The function A+(B|∼C) can be expressed as A&(all '1'S")+(B|∼C). Choosing F1(B,C) all "1's" (F1 code of Hex "AA") and F2(B/C) = B|∼C (F2 code of "CF") yields this expression. The bit-wise exclusive OR of Hex "AA" and Hex "C0" obtains the function code of Hex "65" as listed in Table 16. The function A-(B&C) can be expressed as A&(all "1's")+(-(B&-C)-l)+l. Choosing F1(B,C) = all "1's" (F1 code Hex "AA") and F2(B,C) = -(B&C)-1 (F2 code Hex "3F") with a carry-in injection of "1" yields this expression. The bit-wise exclusive OR of Hex "AA" and Hex "3F" yields the function code Hex "95" as listed in Table 16. This function can strip off or mask bits in the B input by the C input before subtracting from A. There are 16 possible functions where the subfunction F1(B,C)=0. These functions are commonly used with other hardware to perform negation, absolute value, bit masking, and/or sign extension of the B-input by the C-input. When subfunction F1(B,C)=0 then the arithmetic logic unit function is given by subfunction F2(B,C). The function - (B&C) may be expressed as (A&"0") + (-(B&C)). This expression can be formed by choosing F1(B,C) = 0 (F1 code Hex "00") and F2(B,C) = -(B&C)-1 (F2 code Hex "3F") with a carry-in injection of "1". The exclusive OR of Hex "00" and Hex "3F" yields the function code Hex "3F" as shown in Table 16. This function masks bits in B by a mask C and then negates the quantity. This function can be used as part of a shift right and negate operation. Several functions support masking both terms of the sum in the equation above in a useful manner. The function (A&C)+(B&C) can be achieved by choosing F1(B,C) = C (F1 code Hex "A0") and F2(B,C) = B&C (F2 code Hex "C0"). The exclusive OR of Hex "A0" and Hex "F0" yields the function code Hex "60" as shown in Table 16. This function will effectively zero the corresponding bits of the A and B inputs where C is "0" before adding. It should be noted that the Boolean function is applied before the addition and that one or more carries can ripple into the bits that have been zeroed. When using multiple arithmetic such carries do not cross the boundaries between the split sections of arithmetic logic unit 230. A common use for this function is to sum multiple smaller quantities held in one register. The B-port receives a rotated version of the number going to the A-port and the C-port provides a mask for the bits that overlap. Four 8 bit numbers can be summed into two 16 bit numbers or two 16 bit numbers summed into one 32 bit number in a single instruction. The similar function (A&C)-(B&C) is achieved by choosing F1(B,C) = C (F1 code Hex A0") and F2(B,C) -(B&C)-1 and injecting a carry-in of "1". The exclusive OR of Hex "A0" and Hex "3F" yields the function code Hex "9F" as shown in Table 16. This function can produce negative sums with the C-port value acting as a mask of the A and B inputs. The function (A&B)+B is achieved by choosing F1(B,C) = C (F1 code Hex "A0") and F2(B,C) = B (F2 code Hex "CC"). The exclusive OR of Hex "A0" and Hex "CC" yields the function code Hex "6C". This function can conditionally double B based on whether A is all "1's" or all "0's". Figure 17 illustrates in block diagram form an alternative embodiment of arithmetic logic unit 230. The arithmetic logic unit 230 of Figure 17 forms the equation: S = F3(A,B,C) + F4(A,B,C) where: S is the arithmetic logic unit resultant; and F3(A,B,C) and F4(A,B,C) can be any of the 256 possible Boolean functions of A, B and C. Adder 495 forms the addition of this equation and includes an input for a least significant bit carry input from bit 0 carry-in generator 246. Boolean function generator 496 forms the function F3(A,B,C) as controlled by input function signals. Boolean function generator 497 similarly forms the function F4(A,B,C) as controlled by input function signals. Note that Boolean function generators 496 and 497 independently form selected Boolean combinations of A, B and C from a set of the 256 possible Boolean combinations of three inputs. Note that it is clear from this construction that arithmetic logic unit 230 forms the Boolean combinations before forming the arithmetic combination. The circuit in Figure 12 can be modified to achieve this result. The generate/kill function illustrated in Figure 12 employs a part of the logic tree used in the propagate function. This consists of pass gates 451, 452, 453, 454, 461 and 462. Providing a separate logic tree for this function that duplicates pass gates 451, 452, 453, 454, 461 and 462 and eliminating the NOT A gate 475 results in a structure embodying Figure 17. Note in this construction one of the generate or kill terms may occur simultaneously with the propagate term. This construction provides even greater flexibility than that illustrated in Figure 16. The three input arithmetic logic unit 230, the auxiliary data path hardware and knowledge of the binary number system can be used to form many useful elementary functions. The instruction set of the digital image/graphics processors makes more of the hardware accessible to the programmer than typical in microprocessors. Making hardware more accessible to the programmer exposes some aspects of architecture that are hidden on most other processors. This instruction set supports forming custom operations using the elemental functions as building blocks. This makes greater functionality accessible to the programmer beyond the hardware functions commonly found within other processors, the digital image/graphics processors have hardware functions that can be very useful for image, graphics, and other processing. This combination of hardware capability and flexibility allows programmers to perform in one instruction what could require many instructions on most other architectures. The following describes some key elemental functions and how two or more of them can be combined to produce a more complex operation. The previous sections described the individual workings of each functional block of data unit 110. This section will discuss how these functions can be used in combination to perform more complex operations. Barrel rotator 235, mask generator 239 and 3-input arithmetic logic unit 230 can work together to perform shift left, unsigned shift right, and signed shift right either alone or combination with addition or subtraction in a single arithmetic logic unit instruction cycle. An assembler produces program code for digital image/graphics processors 71, 72, 73 and 74. This assembler preferably supports the symbols ">>u" for unsigned (logical) right shift, ">>" or ">>s" for arithmetic (signed) right shift, and "<<" for a left shift. These shift notations are in effect macro functions that select the appropriate explicit functions in terms of rotates, mask generation, and arithmetic logic unit function. The assembler also preferably supports explicitly specifying barrel rotation ("\\"), mask generation ("%" and "%!"), and the arithmetic logic unit function. The explicit notation will generally be used only when specifying a custom function not expressible by the shift notation. Data unit 110 performs left shift operations in a single arithmetic logic unit cycle. Such a left shift operation includes barrel rotator via barrel rotator 235 by the number of bits of the left shift. As noted above during such rotation, bits that rotate out the left wrap around into the right and thus need to be stripped off to perform a left shift. The rotated output is sent to the B-port of arithmetic logic unit 230. Mask generator 239 receives the shift amount and forms a mask with a number of right justified ones equal to the shift amount. Note that the same shift amount supplies the rotate control input of barrel rotator 235 from second input bus 202 via multiplexer Smux 231 and mask generator 239 from second input bus 202 via multiplexer Mmux 234. Mask generator 239 supplies the C-port of arithmetic logic unit 230. Arithmetic logic unit 230 combines the rotated output with the mask with the Boolean function B&∼C. Left shifts are expressed in the assembler below: Left_Shift = Input<<Shift_Amount This operation is equivalent to the explicit notation: Left_Shift = (Input\\Shift_Amount)&∼%Shift_Amount The following example shows of a left shift of Hex "53FFFFA7" by 4 bits. While shown in several steps, data unit 110 performs this in a single pass arithmetic logic unit cycle The original number in binary notation is: 0101 0011 1111 1111 1111 1111 1010 0111 Rotation by 4 places in barrel rotator 235 yields: 0011 1111 1111 1111 1111 1010 0111 0101 Mask generator 239 forms the following mask: 0000 0000 0000 0000 0000 0000 0000 1111 Arithmetic logic unit 230 forms the logical combination B&∼C. This masks bits in the rotated amount causing them to be "0" and retains the other bits. This yields the left shift result: 0011 1111 1111 1111 1111 1010 0111 0000 The left shift of the above example results in an arithmetic overflow, because some bits have "overflowed". During a shift left, arithmetic overflow occurs for unsigned numbers if any bits are shifted out. Arithmetic overflow may also occur for signed numbers if the resulting sign bit differs from the original sign bit. Arithmetic logic unit 230 of this invention does not automatically detect arithmetic overflow on left shifts. Left shift overflow can be detected by subtracting the left-most-bit-change amount of the original number generated by LMO/RMO/LMBC/RMBC circuit 237 from the left shift amount. If the difference is less than or equal to zero, then no bits will overflow during the shift. If the difference is greater than zero, this difference is the number of bits that overflow. The assembler further controls data unit 110 to perform left shift and add operations and left shift and subtract operations. The assembler translates the A+(B<<n) function into control of barrel rotator 235, mask generator 239, and arithmetic logic unit 230 to performed the desired operation. A shift left and add operation works identically to the above example of a simple shift except for the operation of arithmetic logic unit 230. Instead of performing the logical function B&∼C as in a simple shift, the arithmetic logic unit performs the mixed arithmetic and logical function A+(B&∼C). A left shift and add operation is expressed in the assembler notation as: LShift_Add = Input1 + Input2<<Shift_Amount This operation is equivalent to: LShift_Add = Input1 + [(Input2\\Shift_Amount)&∼%Shift_Amount] The following example shows a left shift of Hex "53FFFFA7" by 4 bits followed by addition of Hex "000000AA". Note that all these steps require only a single arithmetic logic unit cycle. The original Input2 in binary notation is: 0101 0011 1111 1111 1111 1111 1010 0111 Rotation by 4 places in barrel rotator 235 yields: 0011 1111 1111 1111 1111 1010 0111 0101 Mask generator 239 forms the mask: 0000 0000 0000 0000 0000 0000 0000 1111 Arithmetic logic unit 230 forms the logical combination B&∼C producing a left shift result: 0011 1111 1111 1111 1111 1010 0111 0000 The other operand Input1 in binary notation is: 0000 0000 0000 0000 0000 0000 1010 1010 Finally the sum is: 0011 1111 1111 1111 1111 1011 0001 1010 Note that arithmetic logic unit 230 forms the logical combination and the arithmetic combination in a single cycle and that the left shift result shown above is not available as an intermediate result. Note also that the sum may overflow even if the left shift does not produce an overflow. Overflow of the sum is detected by generation of a carry-out from the most significant bit of arithmetic logic unit 230. This condition is detected and stored in the "V" bit of status register 210. The shift left and subtract operation also breaks down into a set of functions performed by barrel rotator 235, mask generator 237, and arithmetic logic unit 230 in a single arithmetic logic unit cycle. The left shift and subtract operation differs from the previously described left shift operation and left shift and add operation only in the function of arithmetic logic unit 230. During left shift and subtract arithmetic logic unit 230 performs the mixed arithmetic and logical function A+(B|∼C)+1. Arithmetic logic unit 230 performs the "+1" operation by injection of a "1" into the carry input of the least significant bit. This injection of a carry-in takes place at bit 0 carry-in generator 246. Most subtraction operations with this invention take place using such a carry-in of "1" to the least significant bit. The assembler notation expresses left shift and subtract operations as follows: LShift_Sub = Input1 - Input2<<Shift_Amount This operation is equivalent to: LShift_Sub Input1-[(Input2\\Shift_Amount]&∼%Shift_Amount]+1 The following example shows a left shift of Hex "53FFFFA7" by 4 bits followed by subtraction of Hex "000000AA". Note that all these steps require only a single arithmetic logic unit cycle. The original Input2 in binary notation is: 0101 0011 1111 1111 1111 1111 1010 0111 Rotation by 4 places in barrel rotator 235 yields: 0011 1111 1111 1111 1111 1010 0111 0101 Mask generator 239 forms the mask: 0000 0000 0000 0000 0000 0000 0000 1111 The result of the logical combination ∼B|C is as follows: 1100 0000 0000 0000 0000 0101 1000 1111 The other operand Inputl in binary notation is: 0000 0000 0000 0000 0000 0000 1010 1010 The sum A+(∼B|C) is: 1100 0000 0000 0000 0000 0110 0011 1001 Finally the addition of the "1" injected into the least significant bit carry-in yields: 1100 0000 0000 0000 0000 0110 0011 1010 Note that arithmetic logic unit 230 forms the logical combination and the arithmetic combination in a single cycle and that neither the left shift result nor the partial sum shown above are available as intermediate results. The assembler of the preferred embodiment can control data unit 110 to perform an unsigned right shift with zeros shifted in from the left in a single arithmetic logic unit cycle. Since barrel rotator 235 performs a left rotate, at net right rotate may be formed with a rotate amount of 32-n, where n is the number of bits to rotate right. Note, only the 5 least significant bits of the data on second input bus 202 are used by barrel rotator 235 and mask generator 239. Therefore the amounts 32 and 0 are equivalent in terms of controlling the shift operation. The assembler will automatically make the 32-n computation for shifts with an immediate right shift amount. The assembler of the preferred embodiment requires the programmer form the quantity 32-n on register based shifts. Once the accommodation for right rotation is made, the unsigned shift right works the same as the shift left except that arithmetic logic unit 230 performs a different function. This operation includes rotation by the quantity 32-n via barrel rotator 235. The result of this net rotate right will to have bits wrapped around from the least significant to the most significant part of the word. The same quantity (32-n) controls mask generator 239, which will generate 32-n right justified ones. Mask generator 239 is controlled with the "!" option so that a shift amount of zero produces a mask of all "1's". In this case no bits are to be stripped off. Arithmetic logic unit 230 then forms a Boolean combination of the outputs of barrel rotator 235 and mask generator 239. An example of an unsigned right shift operation is shown below. The assembler notation for an unsigned right shift is: Unsigned_Right_Shift = Input>>u(32-Shift_Amount) The equivalent operation explicitly showing the functions performed is: Unsigned_Right_Shift = (Input\\(32-Shift_Amount))&%! (32-Shift_Amount) Note in the equation above the mask operator "%!" specifies that if the shift amount is zero, an all "1" mask will be generated. The example below show the unsigned shifting the number Hex "53FFFFA7" right by 4 bit positions. The original number in binary form is: 0101 0011 1111 1111 1111 1111 1010 0111 This number when left rotated by 32-4 = 28 places becomes: 0111 0101 0011 1111 1111 1111 1111 1010 Mask generator 239 forms a mask from the input 32-4 = 28, which is: 0000 1111 1111 1111 1111 1111 1111 1111 Lastly arithmetic logic unit 230 forms the Boolean combination B&C yielding the result: 0000 0101 0011 1111 1111 1111 1111 1010 Data unit 110 may perform either unsigned right shift and add or unsigned right shift and subtract operations. In the preferred embodiment the assembler translates the notation A+B>>u(n) into an instruction that controls barrel rotator 235, mask generator 239 and arithmetic logic unit 230 to performed an unsigned right shift and add operation. The unsigned shift right and add works identically to the previous example of a simple unsigned shift right except that arithmetic logic unit 230 performs the function A+(B&C). In the preferred embodiment the assembler translates the notation A-B>>u(n) into an instruction that controls barrel rotator 235, mask generator 239 and arithmetic logic unit 230 to performed an unsigned right shift and subtract operation . The unsigned shift right and subtract works similarly to the previous example of a simple unsigned shift right except that arithmetic logic unit 230 performs the function A-(∼B|C)+1. As with left shift and subtract the "+1" operation involves injection of a "1" carry-in into the least significant bit via bit 0 carry-in generator 246. The assembler of the preferred embodiment can control data unit 110 to perform a signed right shift with sign bits shifted in from the left in a single arithmetic logic unit cycle. The assembler will automatically make the 32-n computation for such shifts with an immediate right shift amount. Data unit 110 includes hardware that detects that state of the most significant bit, called the sign bit, of the input into barrel rotator 235. This sign bit may control the 4 least significant bits of the function code. When using this hardware, the 4 least significant bits of the function code are inverted if the sign bit is "0". Signed right shift operations use this sign detection hardware to control the function arithmetic logic unit 230 performs based on the sign of the input to barrel rotator 235. This operation can be explained using the following elemental functions. Barrel rotator 235 performs a net rotate right by rotating left by 32 minus the number of bits of the desired signed right shift (32-n). This shift amount (32-n) is supplied to mask generator 237, which will thus generate 32-n right justified "1's". The "1's" of this mask will select the desired bits of the number that is right shifted. The "0's" of this mask will generate sign bits equal to the of the most significant bit input to barrel rotator 235. Arithmetic logic unit 230 then combines the rotated number from barrel rotator 235 and the mask from mask generator 237. The Boolean function performed by arithmetic logic unit 230 depends upon the sign bit at the input to barrel rotator 235. If this sign bit is "0", then arithmetic logic unit 230 receives function signals to perform B&C. While selecting the rotated number unchanged, this forces "0" any bits that are "0" in the mask. Thus the most significant bits of the result are "0" indicating the same sign as the input to barrel rotator 235. If the sign bit is "1", then arithmetic logic unit 230 received function signal to perform B|∼C. This function selects the rotated amount unchanged while forcing to "1" any bits that are "0" in the mask. The change in function code involves inverting the 4 least significant bits if the detected sign bit is "0". Thus the most significant bits of the result are "1", the same sign indication as the input to barrel rotator 235. Two examples of the unsigned right shift operation are shown below. Signed right shift is the default assembler notation for right shifts. The two permitted assembler notations for a signed right shift are: Signed_Right_Shift = Input>>s(32-Shift_Amount) Signed_Right_Shift = Input»(32-Shift_Amount) Because this operation uses the sign detection hardware, there is no explicit way in the notation of the preferred embodiment of the assembler to specify this operation in terms of rotation and masking. In the preferred embodiment the sign of the input to barrel rotator 235 controls inversion of the function signals F3-F0. The first example shows a 4 place signed right shift of the negative number Hex "ECFFFFA7". The original number in binary notation is: 1110 1100 1111 1111 1111 1111 1010 0111 Left rotation by 28 (32-4) places yields: 0111 1110 1100 1111 1111 1111 1111 1010 Mask generator 237 forms this mask: 0000 1111 1111 1111 1111 1111 1111 1111 Because the most significant bit of the input to barrel rotator 235 is "1", arithmetic logic unit 230 forms the Boolean combination of B|∼C. This yields the result: 1111 1110 1100 1111 1111 1111 1111 1010 In this example "1's" are shifted into the most significant bits of the shifted result, matching the sign bit of the original number. The second example shows a 4 place signed right shift of the positive number Hex "5CFFFFA7". The original number in binary notation is: 0101 1100 1111 1111 1111 1111 1010 0111 Left rotation by 28 (32-4) places yields: 0111 0101 1100 1111 1111 1111 1111 1010 Mask generator 237 forms this mask: 0000 1111 1111 1111 1111 1111 1111 1111 Because the most significant bit of the input to barrel rotator 235 is "0", arithmetic logic unit 230 forms the Boolean combination of B&C by inversion of the four least significant bits of the function code. This yields the result: 0000 0101 1100 1111 1111 1111 1111 1010 Note that upon this right shift "0's" are shifted in the most significant bits, matching the sign bit of the original number. Data unit 110 may perform either signed right shift and add or signed right shift and subtract operations. In the preferred embodiment the assembler translates the notations A+B>>(n) or A+B>>s(n) into an instruction that controls barrel rotator 235, mask generator 239 and arithmetic logic unit 230 to perform a signed right shift and add operation. The signed shift right and add works identically to the previous example of the signed shift right except for the function performed by arithmetic logic unit 230. In the signed right shift and add operation arithmetic logic unit 230 performs the function A+(B&C) if the sign bit of the input to barrel rotator 235 is "0". If this sign bit is "1", then arithmetic logic unit 230 performs the function A+(B|∼C). In the preferred embodiment the assembler translates the notations A-B>>s(n) or A-B>>(n) into an instruction that controls barrel rotator 235, mask generator 239 and arithmetic logic unit 230 to perform a signed right shift and subtract operation. The signed shift right and subtract operation works similarly to the previous example of a simple signed shift right except for the function of arithmetic logic unit 230. When the sign bit is "1", arithmetic logic unit 230 performs the function A-(B&C)+1. When the sign bit is "0", arithmetic logic unit 230 performs the alternate function A-(B|∼C)+1. As in the case of left shift and subtract the "+1" operation involves injection of a "1" carry-in into the least significant bit via bit 0 carry-in generator 246. Barrel rotator 235, mask generator 237 and arithmetic logic unit 230 can perform field extraction in a single cycle. A field extraction takes a field of bits in a word starting at any arbitrary bit position, strips off the bits outside the field and right justifies the field. Such a field extraction is performed by rotating the word left the number of bits necessary to right justify the field and masking the result of the rotation by the number of bits in the size of the field. Unlike the cases for shifting, the rotation amount, which is based on the bit position, and the mask input, which is based on the field size, are not necessarily the same amount. The assembler of the preferred embodiment employs the following notation for field extraction: Field_Extract = (Value\\(32-starting_bit))&%!Field size The "%!" operator causes mask generator 237 to form a mask having a number of right justified "1's" equal to the field size, except for an input of zero. In that case all bits of the generated mask are "1" so that no bits are masked by the logical AND operation. This rotation and masking may produce wrapped around bits if the field size is greater than the starting bit position. These parameters specify an anomalous case in which the specified field extends beyond the end of the original word. Data unit 110 provides no hardware check to for this case. It is the responsibility of the programmer to prevent this result. The example below demonstrates field extraction of a 4-bit field starting at bit 24, which is the eight bit from the left, of the number Hex "5CFFFFA7". The number in binary form is: 0101 1100 1111 1111 1111 1111 1010 0111 The number must be rotated left by 32-24 or 8 bits to right justify the field. The output from barrel rotator 235 is: 1111 1111 1111 1111 1010 0111 0101 1100 Mask generator 237 forms the following mask from the field size of 4 bits: 0000 0000 0000 0000 0000 0000 0000 1111 Lastly, arithmetic logic unit 230 forms the Boolean combination B&C. This produces the extracted field as follows: 0000 0000 0000 0000 0000 0000 0000 1100 Mflags register 211 is useful in a variety of image and graphics processing operations. These operations fall into two classes. The first class of Mflags operations require a single pass through arithmetic logic unit 230. A number is loaded into Mflags register 211 and controls the operation of arithmetic logic unit 230 via expand circuit 238, multiplexer Cmux 233 and the C-port of arithmetic logic unit 230. Color expansion is an example of these single pass operations. The second class of Mflags operations require two passes through arithmetic logic unit 230. During a first pass certain bits are set within Mflags register 211 based upon the carry of zero results of arithmetic logic unit 230. During a second pass the contents of Mflags register 211 control the operation of arithmetic logic unit 230 via expand circuit 238, multiplexer Cmux 233 and the C-port of arithmetic logic unit 230. Such two pass Mflags operations are especially useful when using multiple arithmetic. Numerous match and compare, transparency, minimum, maximum and saturation operations fall into this second class. A basic graphics operation is the conversion of one bit per pixel shape descriptors into pixel size quantities. This is often called color expansion. In order to conserve memory space the shape of bit mapped text fonts are often stored as shapes of one bit per pixel. These shapes are then "expanded" into the desired color(s) when drawn into the display memory. Generally "1's" in the shape descriptor select a "one color" and "0's" in the shape descriptor select a "zero color". A commonly used alternative has "0's" in the shape descriptor serving as a place saver or transparent pixel. The following example converts 4 bits of such shape descriptor data into 8 bit pixels. In this example the data size of the multiple arithmetic operation is 8 bits. Thus arithmetic logic unit 230 operates in 4 independent 8 bit sections. The four bits of descriptor data "0110" are loaded into Mflags register 211: XXXXXXXX XXXXXXXX XXXXXXXX XXXX0110 The bits listed as "X" are don't care bits that are not involved in the color expansion operation. Expand circuit 238 expands these four bits in Mflags register 211 into blocks of 8 bit "1's" and "0's" as follows: 00000000 11111111 11111111 00000000 The one color is supplied to the A-port of arithmetic logic unit 230 repeated for each of the 4 pixels within the 32 bit data word: 11110000 11110000 11110000 11110000 The zero color is supplied to the B-port of arithmetic logic unit 230, also repeated for each of the 4 pixels: 10101010 10101010 10101010 10101010 Arithmetic logic unit 230 forms the Boolean combination (A&C)|(B&∼C) which yields: 10101010 11110000 11110000 10101010 Color expansion is commonly used with a PixBlt algorithm. To perform a complete PixBlt, the data will have to be rotated and merged with prior data to align the bits in the data to be expanded with the pixel alignment of the destination words. Barrel rotator 235 and arithmetic logic unit 230 can align words into Mflags register 211. This example assumed that the shape descriptor data was properly aligned to keep the example simple. Note also that Mflags register 211 has its own rotation capability upon setting bits and using bits. Thus a 32 bit word can be loaded into Mflags register 211 and the above instruction repeated 8 times to generate 32 expanded pixels. Simple color expansion as in the above example forces the result to be one of two solid colors. Often, particularly with kerned text letters whose rectangular boxes can overlap, it is desirable to expand "1's" in the shape descriptor to the one color but have "0's" serve as place saver or transparent pixels. The destination pixel value is unchanged when moving such a transparent color. Data unit 110 can perform a transparent color expand by simply using a register containing the original contents of the destination as the zero value input. An example of this appears below. Arithmetic logic unit 230 performs the same function as the previous color expansion example. The only difference is the original destination becomes one of the inputs to arithmetic logic unit 230. The four bits of descriptor data "0110" are loaded into Mflags register 211: XXXXXXXX XXXXXXXX XXXXXXXX XXXX0110 Expand circuit 238 expands these four bits in Mflags register 211 into blocks of 8 bit "1's" and "0's" as follows: 00000000 11111111 11111111 00000000 The one color is supplied to the A-port of arithmetic logic unit 230 repeated for each of the 4 pixels within the 32 bit data word: 11110000 11110000 11110000 11110000 The original destination data is supplied to the B-port of arithmetic logic unit 230, original destination data including 4 pixels: 11001100 10101010 11101110 11111111 Arithmetic logic unit 230 again forms the Boolean combination (A&C)|(B&∼C) which yields: 11001100 11110000 11110000 11111111 Note that the result includes the one color for pixels corresponding to a "1" in Mflags register 211 and the original pixel value for pixels corresponding to a "0" in Mflags register 211. Data unit 110 can generate a 1 bit per pixel mask based on an exact match of a series of 8 bit quantities to a fixed compare value. This is shown in the example below. The compare value is repeated four times within the 32 bit word. Arithmetic logic unit 230 subtracts the repeated compare value from a data word having four of the 8 bit quantities. During this subtraction, arithmetic logic unit 230 is split into 4 sections of 8 bits each. The zero detectors 321, 322, 323 and 324 illustrated in Figure 7 supply are data to be stored in Mflags register 211. This example includes two instructions in a row to demonstrate accumulating by rotating Mflags register 211. Initially Mflags register 211 stores don't care data: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX The first quantity for comparison is: 00000011 00001111 00000001 00000011 The compare value is "00000011". This is repeated four times in the 32 bit word as: 00000011 00000011 00000011 00000011 Arithmetic logic unit 230 subtracts the compare value from the first quantity. The resulting difference is: 00000000 00001100 11111110 00000000 This forms the following zero compares "1001" that are stored in Mflags register 211. In this example Mflags register 211 is pre-cleared before storing the zero results. Thus Mflags register 211 is: 00000000 00000000 00000000 00001001 The second quantity for comparison is: 00000111 11111100 00000011 00000000 The result of a second subtraction of the same compare value is: 00000100 11111001 00000000 11111101 This forms the new zero compares "0010" that are stored in Mflags register 211 following rotation of four places: 00000000 00000000 00000000 10010010 Additional compares may be made in the same fashion until Mflags register 211 stores 32 bits. Then the contents of Mflags register 211 may be moved to another register or written to memory. Threshold detection involves comparing pixel values to a fixed threshold. Threshold detection sets a 1 bit value for each pixel which signifies the pixel value was greater than or less than the fixed threshold. Depending on the particular application, the equal to case is grouped with either the greater than case or the less than case. Data unit 110 may be programmed to from the comparison result in a single arithmetic logic unit cycle. Arithmetic logic unit 230 forms the difference between the quantity to be tested and the fixed threshold. The carry-outs from each section of arithmetic logic unit 230 are saved in Mflags register 211. If the quantity to be tested I has the fixed threshold T subtracted from it, a carry out will occur only if I is greater than or equal to T. As stated above, arithmetic logic unit 230 performs subtraction by two's complement addition and under these circumstances a carry-out indicates a not-borrow. Below is an example of this process for four 8 bit quantities in which the threshold value is "00000111". Let four 8 bit quantities I to be tested be: 00001100 00000001 00000110 00000111 The threshold value T repeated four times within the 32 bit word is: 00000111 00000111 00000111 00000111 The difference is: 00000101 11111010 11111111 00000000 which produces the following carry-outs "1001". This results in a Mflags register 211 of: XXXXXXXX XXXXXXXX XXXXXXXX XXXX1001 As in the case of match detection, this single instruction can be repeated for new data with Mflags resister rotation until 32 bits are formed. When adding two unsigned numbers, a carry-out indicates that the result is greater than can be expressed in the number of bits of the result. This carry-out represents the most significant bit of precision of the result. Thus saving the carry-outs in Mflags register 211 can be used to maintain precision. These carry-out bits may be saved for later addition to maintain precision. Particularly when used with multiple arithmetic, limiting the precision to fewer bits often enables the same process to be performed in fewer arithmetic logic unit cycles. Mflags operations of the second type employ both setting bits within Mflags register 211 and employing bits stored in Mflags register 211 to control the operation of arithmetic logic unit 230. Multiple arithmetic can be used it in combination with expands of Mflags register 211 to perform multiple parallel byte or half-word operations. Additionally, the setting of bits in Mflags register 211 and expanding Mflags register 211 to arithmetic logic unit 230 are inverse space conversions that can be used in a multitude of different ways. The example below shows a combination of an 8 bit multiple arithmetic instruction followed by an instruction using expansion to perform a transparency function. Transparency is commonly used when performing rectangular PixBlts of shapes that are not rectangular. The transparent pixels are used as place saver pixels that will not affect the destination and thus are transparent so the original destination shows through. With transparency, only the pixels in the source that are not equal to the transparent code are replaced in the destination. In a first instruction the transparent color code is subtracted from the source and Mflags register 211 is set based on equal zero. If a given 8 bit quantity matches the transparent code, a corresponding "1" will be set in Mflags register 211. The second instruction uses expansion circuit 238 to expand Mflags register 211 to control selection on a pixel by pixel basis of the source or destination. Arithmetic logic unit 230 performs the function (A&C)|(B&∼C) to make this selection. While this Boolean function is performed bit by bit, Mflags register 211 has been expanded to the pixel size of 8 and thus it selects between pixels. The pixel source is: 00000011 01110011 00000011 00000001 The transparent code TC is "00000011". Repeated 4 times to fill the 32 bit word this becomes: 00000011 00000011 00000011 00000011 The difference SRC-TC is: 00000000 01110000 00000000 11111110 which produces the zero detection bits "1010". Thus Mflags register 211 stores: XXXXXXXX XXXXXXXX XXXXXXXX XXXX1010 In the second instruction, expand circuit 238 expands Mflags register 211 to: 11111111 00000000 11111111 00000000 The original destination DEST is: 11110001 00110011 01110111 11111111 The original source SRC forms a third input to arithmetic logic unit 230. Arithmetic logic unit 230 then forms the Boolean combination (DEST&@MF)|(SRC&∼@MF) which is: 11110001 00010011 01110111 00000001 Note that the resultant has the state of the source where the source was not transparent, otherwise it has the state of the destination. This is the transparency function. Data unit 110 can perform maximum and minimum functions using Mflags register 211 and two arithmetic logic unit cycles. The maximum function takes the greater of two unsigned pixel values as the result. The minimum function takes the lesser of two unsigned pixel values as the result. In these operations the first instruction performs multiple subtractions, setting Mflags register 211 based on carry-outs. Thus for status setting arithmetic logic unit 230 forms OP1-OP2. This first instruction only sets Mflags register 211 and the resulting difference is discarded. When performing the maximum function the second instruction, arithmetic logic unit 230 performs the operation (OP1&@MF)|(OP2&∼@MF). This forms the maximum of the individual pixels. Let the first operand OP1 be: 00000001 11111110 00000011 00000100 and the second operand OP2 be: 00000011 00000111 00000111 00000011 The difference OP1-OP2 is: 11111110 11110111 11111100 00000000 This produces carry-outs (not-borrows) "0101" setting Mflags register 211 as: XXXXXXXX XXXXXXXX XXXXXXXX XXXX0101 In the second instruction the four least significant bits in Mflags register 211 are expanded via expand circuit 238 producing: 00000000 11111111 00000000 11111111 Arithmetic logic unit 230 performs the Boolean function (OP1&@MF)|(OP2&∼@MF). This produces the result: 00000011 11111110 00000111 00000100 Note that each 8 bit section of the result has the state of the greater of the corresponding sections of OP1 and OP2. This is the maximum function. The minimum function operates similarly to the maximum function above except that in the second instruction arithmetic logic unit 230 performs the Boolean function (OP1&∼@MF)|(OP2&@MF). This Boolean function selects the lesser quantity rather than greater quantity for each 8 bit section. Data unit 110 may also perform an add-with-saturate function. The add-with-saturate function operates like a normal add unless an overflow occurs. In that event the add-with-saturate function clamps the result to all "1's". The add-with-saturate function is commonly used in graphics and image processing to keep small integer results from overflowing the highest number back to a low number. The example below shows forming the add-with-saturate function using multiple arithmetic on four 8 bit pixels in two instructions. First the addition takes place with the carry-outs stored in Mflags register 211. A carry-out of "1" indicates an overflow, thus that sum should be set to all "1's", which is the saturated value. Then expand circuit 238 expands Mflags register 211 to control selection of the sum or the saturated value. The first operand OP1 is: 00000001 11111001 00000011 00111111 The second operand OP2 is: 11111111 00001011 00000111 01111111 Arithmetic logic unit 230 forms the sum OP1+OP2 = RESULT resulting in: 00000000 00000100 00001010 10111110 with corresponding carry-outs of "1100". These are stored in Mflags register 211 as: XXXXXXXX XXXXXXXX XXXXXXXX XXXX1100 In the second instruction expand circuit 238 expands the four least significant bits of Mflags register 211 to: 11111111 11111111 00000000 00000000 Arithmetic logic unit 230 performs the Boolean function RESULT|@MF forming: 11111111 11111111 00001010 10111110 Note the result of the second instruction equals the sum when the sum did not overflow and equals "11111111" when the sum overflowed. Data unit 110 can similarly perform a subtract-with-saturate function. The subtract-with-saturate function operates like a normal subtract unless an underflow occurs. In that event the subtract-with-saturate function clamps the result to all "0's". The subtract-with-saturate function may also be commonly used in graphics and image processing. The data unit 110 performs the subtract-with-saturate function similarly to the add-with-saturate function shown above. First the subtraction takes place with the carry-outs stored in Mflags register 211. A carry-out of "0" indicates a borrow and thus an underflow. In that event the difference should be set to all "0's", which is the saturated value. Then expand circuit 238 expands Mflags register 211 to control selection of the difference or the saturated value. During this second instruction arithmetic logic unit 230 performs the Boolean function RESULT&@MF. This forces the combination to "0" if the corresponding carry-out was "0", thereby saturating the difference at all "0's". On the other hand if the corresponding carry-out was "1", then the Boolean combination is the same as RESULT. Figure 18 illustrates the format of the instruction word for digital image/graphics processors 71, 72, 73 and 74. The instruction word has 64 bits, which are generally divided into two parallel sections as illustrated in Figure 18. The most significant 25 bits of the instruction word (bits 63-39) specify the type of operation performed by data unit 110. The least significant 39 bits of the instruction word (bits 38-0) specify data transfers performed in parallel with the operation of data unit 110. There are five formats A, B, C, D and E for operation of data unit 110. There are ten types of data transfer formats 1 to 10. The instruction word may specify a 32 bit immediate value as an alternative to specifying data transfers. The instruction word is not divided into the two sections noted above when specifying a 32 bit immediate value, this being the exception to the general rule. Many instructions perform operations that do not use data unit 110. These instructions may allow parallel data transfer operations or parallel data transfer operations may be prohibited depending on the instruction. In other respects the operations specified for data unit 110 are independent of the operations specified for data transfer. The instruction word alternatives are summarized as follows. The operation of data unit 110 may be a single arithmetic logic unit operation or a single multiply operation, or one of each can be performed in parallel. All operations of data unit 110 may be made conditional based upon a field in the instruction word. The parallel data transfers are performed on local port 141 and global port 145 of data port unit 140 to and/or from memory. Two data transfer operations are independently specified within the instruction word. Twelve addressing modes are supported for each memory access, with a choice of register or offset index. An internal register to register transfer within data unit 110 can be specified in the instruction word instead of a memory access via global port 145. When an operation of data unit 110 uses a non-data unit register as a source or destination, then some of the parallel data transfer section of the instruction word specifies additional register information, and the global port source data bus Gsrc 105 and global port destination data bus Gdst 107 transfer the data to and from data unit 110. A part of the instruction word that normally specifies the local bus data transfer has an alternative use. This alternative use allows conditional data unit 110 operation and/or global memory access or a register to register move. Limited conditional source selection is supported in the operation of data unit 110. The result of data unit 110 can be conditionally saved or discarded, advantageously conditionally performing an operation without having to branch. Update of each individual bit of a status register can also be conditionally selected. Conditional stores to memory choose between two registers. Conditional loads from memory either load or discard the data. Conditional register to register moves either write to the destination, or discard the data. Description of the types of instruction words of Figure 18 and an explanation or glossary of various bits and fields of the five data unit operation formats follows. The bits and fields define not only the instruction words but also the circuitry that decodes the instruction words according to the specified logic relationships. This circuitry responds to a particular bit or field or logical combination of the instruction words to perform the particular operation or operations represented. Accordingly, in this art the specification of bits, fields, formats and operations defines important and advantageous features of the preferred embodiment and specifies corresponding logic circuitry to decode or implement the instruction words. This circuitry is straight forwardly implemented from this specification by the skilled worker in a programmable logic array (PLA) or in other circuit forms now known or hereafter devised. A description of the legal operation combinations follows the description of the instruction word format. Data unit format A is recognized by bit 63 = "1" and bit 44 = "0". Data unit format A specifies a basic arithmetic logic unit operation with a 5 bit immediate field. The "class" field (bits 62-60) designates the data routing within data unit 110 with respect to arithmetic logic unit 230. Table 18 shows the definition of the data routings corresponding to the "class" field for data unit formats A, B and C. Class field Input A Input B Input C maskgen rotate 6 6 6 2 1 0 0 0 0 src2/im src1 @MF - 0 0 0 1 dstc src1 src2/im - D0(4-0) 0 1 0 dstc src1 mask src2/im 0 0 1 1 dstc src1 mask src2/im src2/im 1 0 0 src2/im src1 mask DO(4-0) D0(4-0) 1 0 1 src2/im src1 @MF - D0(4-0) 1 1 0 dstc src1 src2/im - 0 1 1 1 src1 Hex "1" src2/im - src2/im In Table 18 "Input A" is the source selected by Amux 232 for input A bus 241. The source "src2/im" is either the five bit immediate value of "immed" field (bits 43-39) in data unit format A, the data register 200 designated by the "src2" field (bits 41-39) in data unit format B, or the 32 bit immediate value of the "32-bit immediate" field (bits 31-0) in data unit format C. The source "dstc" is a companion data register 200 to the destination of the arithmetic logic unit 230 result. This companion data register 200 has a register designation with the upper four bits equal to "0110", thereby specifying one of data registers 200, and a lower three bits specified by the "dst" field (bits 50-48). Companion registers are used with transfer formats 6 and 10 which use an "Adstbnk" field (bits 21-18) to specify the register bank of the destination and an "As1bank" (bits 9-6) to specify the register bank of Input B. This is known as a long distance destination, because the destination is not one of data registers 200. Thus one source and the destination may have different register banks with the same register numbers. Table 19 shows the companion registers to various other digital image/graphics processor registers based upon the register bank specified in the "Adstbnk" field. Note that with any other transfer formats this source register is the data register 200 having the register number specified by the "dst" field. Adstbnk D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 0 A0 A1 A2 A3 A4 -- A6 A7 0 0 0 1 A8 A9 A10 A11 A12 -- A14 A15 0 0 1 0 X0 X1 X2 -- -- -- -- -- 0 0 1 1 X8 X9 X10 -- -- -- -- -- 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 1 -- SR MF -- -- -- -- -- 0 1 1 1 CALL BR IPS IPRS INTEN INTFLG COMM LCTL 1 1 0 0 LC0 LC1 LC2 -- LR0 LR1 LR2 -- 1 1 0 1 LRSE0 LRSE1 LRSE2 -- LRS0 LRS1 LRS2 -- 1 1 1 0 LS0 LS1 LS2 -- LE0 LE1 LE2 -- 1 1 1 1 -- -- -- -- TAG0 TAG1 TAG2 TAG3 In Table 19 "--" indicates a reserved register. Note that Table 19 does not list register banks "0110, "1000", "1001", "1010" or "1011". All the registers in these banks are either reserved or assigned to emulation functions and would not ordinarily be used as long distance destinations. In Table 18 "Input B" is the source for barrel rotator 235 which supplies input B bus 242. The "Input B" source designated "src1" is the data register 200 indicated by the "src1" field (bits 47-45) in data unit formats A and B, or by the register bank of the "s1bank" field (bits 38-36) and the register number of the "src1" field (bits 48-45), which may be any of the 64 lower addressable registers within data unit 110, in data format C. The "Hex 1" source for "Input B" is the 32 bit constant equal to "1" from buffer 236. In Table 18 "Input C" is the source selected by Cmux 233 for input C bus 243. The "Input C" source "@MF" is one or more bits from multiple flags register 211 as expanded by expand circuit 238 in accordance with the "Msize" field (bits 5-3) of status register 210. See Table 2 for the definition of the "Msize" field of status register 210. The "src2/im" source has been previously described in conjunction with the "Input A" source. The "mask" source is the output of mask generator 239. In Table 18 "maskgen" is the source selected by Mmux 234 for mask generator 239. This source may be "src2/im" as previously described or "D0(4-0)", which is the default barrel rotate amount of the "DBR" field (bits 4-0) of data register D0. In Table 18 "rotate" is the source selected by Smux 231 for control of the rotate amount of barrel rotator 235. This source may be "0", which provides no rotate, "D0(4-0)", which is the default barrel rotate amount of the "DBR" field (bits 4-0) of data register D0, or "src2/im" as previously described. The "ari" bit (bit 59) designates whether arithmetic logic unit 230 of data unit 110 is used for an arithmetic operation or for a Boolean logic operation. If the "ari" bit is "1" then an arithmetic operation occurs, if "0" then a Boolean logic operation occurs. Data unit format A permits instruction word specification of the operation of arithmetic logic unit 230. The "8-bit ALU code" field (bits 58-51) designates the operation performed by arithmetic logic unit 230. This field designates an arithmetic operation if the "ari" bit is "1". If this is the case then "8-bit ALU code" bits 57, 55, 53 and 51 designate the arithmetic operation according to Table 14 as modified by the "FMOD" field consisting of "8-bit ALU code" bits 58, 56, 54 and 52 according to Table 6. If the "ari" bit is "0", then this is a Boolean operation and the "8-bit ALU code" field translates into function signals F7-F0 according to Table 13. The details of these encodings were described above in conjunction with the description of data unit 110. Data unit format A designates two sources and a destination for arithmetic logic unit 230. The "dst" field (bits 50-48) designates a register as the destination for arithmetic logic unit 230. The "dst" field may refer to one of data registers 200 by register number or the register number of the "dst" field may be used in conjunction with a register bank to specify a long distance register depending on the transfer format. The "src1" field (bits 47-45) designate a register as the first source for arithmetic logic unit 230. This may be one of data registers 200 or may be used in conjunction with a register bank to specify a long distance register depending on the transfer format. The "immed" field (bits 43-39) designates a 5 bit immediate value used as the second source for arithmetic logic unit 230. In use this 5 bit immediate value is zero extended to 32 bits. The use of register banks will be further discussed below in conjunction with description of the transfer formats. The storing of the resultant in the destination register occurs only if the condition noted in the "cond." field is true. The "cond." field (bits 35-32) designates the conditions for a conditional operation. Note that this "cond." field falls within the portion of the instruction word generally used for the transfer format. Transfer formats 7, 8, 9 and 10 include this field. Thus conditional storing of the resultant of arithmetic logic unit 230 occurs only when these transfer formats are used. In the preferred embodiment the "cond." field is decoded as shown below in Table 20. Condition field bits Mnemonic Condition Description Status bits Compared 3 3 3 3 5 4 3 2 0 0 0 0 u unconditional --- 0 0 0 1 p positive ∼N&∼Z 0 0 1 0 ls lower than ∼C|Z or same 0 0 1 1 hi higher than C&∼Z 0 1 0 0 lt less than (N&∼V)|(∼N&V) 0 1 0 1 le less than or equal to (N&∼V)|(∼N&V)|Z 0 1 1 0 ge greater than or equal to (N&V)|(∼N&∼V) 0 1 1 1 gt greater than (N&V&∼Z) | (∼N&∼V&∼Z) 1 0 0 0 hs, c lower than, carry C 1 0 0 1 lo, nc higher than or same, no carry ∼C 1 0 1 0 eq, z equal, zero Z 1 0 1 1 ne, nz not equal, not zero ∼Z 1 1 0 0 v overflow V 1 1 0 1 nv no overflow ∼V 1 1 1 0 n negative N 1 1 1 1 nn non-negative ∼N The conditions are detected with reference to status register 210. As previously described, status register 210 stores several bits related to the condition of the output of arithmetic logic unit 230. These conditions include negative, carry, overflow and zero. The conditional operation of arithmetic logic unit 230 related to status register 210 was detailed above in conjunction with the description of data unit 110. The data unit format B is recognized by bit 63 = "1", bit 44 = "0". Data unit format B specifies a basic arithmetic logic unit operation with a register specified for the second source of arithmetic logic unit 230. The "class" field designates the data routing within data unit 110 as previously described in conjunction with Table 18. The "ari" bit designates whether arithmetic logic unit 230 of data unit 110 is used for an arithmetic operation or for a Boolean logic operation. The "8 bit ALU code" field designates the operation performed by arithmetic logic unit 230 in the manner described above. The "src2" field (bits 41-39) designates one of the data registers 200 as the second source for arithmetic logic unit 230. In data unit format B the second source for arithmetic logic unit 230 is the data register designated in the "src2" field. Some data transfer formats permit designation of banks of registers for the first source and the destination of arithmetic logic unit 230. In other respects data unit format B is the same as data unit format A. The data unit format C is recognized by bit 63 = "1", bit 44 = "1" and bit 43 = "1". Data unit format C specifies a basic arithmetic logic unit operation with a 32 bit immediate field. The "class" field designates the data routing within data unit 110 as previously described in conjunction with Table 18. The "ari" bit designates whether arithmetic logic unit 230 of data unit 110 is used for an arithmetic operation or for a Boolean logic operation. The "8 bit ALU code" field designates the operation performed by arithmetic logic unit 230 as described above. The first source is the data register designated by the "src1" field. The second source is the 32 bit immediate value of the "32-bit imm." field (bits 31-0). This data unit format leaves no room to specify parallel data transfers, so none are permitted. The "dstbank" field (bits 42-39) designates a bank of registers within data unit 110. The "dstbank" field is employed with the "dst" field (bits 50-48) to designate any of 64 registers of data unit 110 as the destination for arithmetic logic unit 230. The "s1bnk" field (bits 38-36) designates a bank of registers within data unit 110. This designation is limited to a lower half of the registers of data unit 110 and is employed with the "src1" field to designate any of 64 lower half registers in data unit 110 as the first source for arithmetic logic unit 230. Operations can be made conditional based upon the "cond." field (bits 35-32) in a manner detailed below. Data unit format D has bit 63 = "1", bit 44 = "0", the "class" field is "000", bit 59 = "1" (which normally selects arithmetic as opposed to Boolean logic operation) and bits 57, 55, 53 and 51 of the "8 bit ALU code" are all "0". Data unit format D specifies non-arithmetic logic unit operations. The "operation" field (bits 43-39) designates a non-arithmetic logic unit operation. In the preferred embodiment this "operation" field is decoded as shown below in Table 21. Operation field Non-ALU Operation 4 4 4 4 3 3 2 1 0 9 0 0 0 0 0 no operation 0 0 0 0 1 idle 0 0 0 1 0 enable global interrupts 0 0 0 1 1 disable global interrupts 0 0 1 0 0 lock synchronization of instruction fetching 0 0 1 0 1 unlock synchronization of instruction fetching 0 0 1 1 0 reserved 0 0 1 1 1 rotate D registers right 1 0 1 0 0 0 null 0 1 0 0 1 halt. instruction execution 0 1 0 1 0 reserved 0 1 0 1 1 reserved 0 1 1 0 0 go to emulator interrupt 0 1 1 0 1 issue emulator interrupt 1 0 1 1 1 0 issue emulator interrupt 2 0 1 1 1 1 reserved 1 X X X X reserved The non-arithmetic logic unit instructions null, halt instruction execution, go to emulator interrupt, issue emulator interrupt 1 and issue emulator interrupt 2 prohibit parallel data transfers. Any parallel data transfers specified in the instruction word are ignored. The other non-arithmetic logic unit instructions permit parallel data transfers. Data unit format E is recognized by bits 63-61 being "011". Data unit format E specifies parallel arithmetic logic unit and multiply operations. These operations are referred to as "six operand operations" because of the six operands specified in this format. In the preferred embodiment the "operation" field (bits 60-57) specifies the operations shown below in Table 22. The symbol "∥" indicates that the listed operations occur in parallel within data unit 110. Note that only 11 of the 16 possible operations are defined. Operation field bits Six Operand Operations 6 5 5 5 0 9 8 7 0 0 0 0 MPYS ∥ ADD 0 0 0 1 MPYS ∥ SUB 0 0 1 0 MPYS ∥ EALUT 0 0 1 1 MPYS ∥ EALUF 0 1 0 0 MPYU ∥ ADD 0 1 0 1 MPYU ∥ SUB 0 1 1 0 MPYU ∥ EALUT 0 1 1 1 MPYU ∥ EALUF 1 0 0 0 EALU ∥ ROTATE 1 0 0 1 EALU% ∥ ROTATE 1 0 1 0 DIVI 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 | reserved The mnemonics for these operations were defined above. To review: MPYS ∥ ADD designates a parallel signed multiply and add; MPYS ∥ SUB designates a parallel signed multiply and subtract; MPYS ∥ EALUT designates a parallel signed multiply and extended arithmetic logic unit true operation; MPYS ∥ EALUF designates a parallel signed multiply and extended arithmetic logic unit false operation; MPYU ∥ ADD designates a parallel unsigned multiply and add; MPYU ∥ SUB designates a parallel unsigned multiply and subtract; MPYU ∥ EALUT designates a parallel unsigned multiply and extended arithmetic logic unit true operation; MPYU ∥ EALUF designates a parallel unsigned multiply and extended arithmetic logic unit false operation; EALU ∥ ROTATE designates an extended arithmetic logic unit operation with the output of barrel rotator 235 separately stored; EALU% ∥ ROTATE designates an extended arithmetic logic unit operation employing a mask generated by mask generator 239 with the output of barrel rotator 235 separately stored; and DIVI designates a divide iteration operation used in division. The arithmetic logic unit operation in an MPYx ∥ EALUT instruction is selected by the "EALU" field (bits 19-26) of data register D0, with the "A" bit (bit 27) selecting either an arithmetic operation or a logic operation as modified by the "FMOD" field (bits 31-28). The coding of these fields has been described above. The arithmetic logic unit operation in an MPYx ∥ EALUF instruction is similarly selected except that the sense of the "EALU" field bits is inverted. The arithmetic logic unit operations for the EALU and EALU% instructions are similarly selected. These operations employ part of the data register D0 of data unit 110 to specify the arithmetic logic unit operation. Data register D0 is pre-loaded with the desired extended arithmetic logic unit operation code. The DIVI operation will be further detailed below. Any data transfer format may be specified in parallel with the operation of data unit 110. Six operands are specified in data unit format E. There are four sources and two destinations. The "src3" field (bits 56-54) designates one of the data registers 200 as the third source. This is the first input for multiplier 220 if a multiply operation is specified, otherwise this is the barrel rotate amount of barrel rotator 235. The "dst2" field (bits 53-51) designates one of the data registers 200 as the second destination. If the instruction specifies a multiply operation, then "dst2" is the destination for multiplier 220. Otherwise "dst2" specifies the destination for the output of barrel rotator 235. The "dst1" field (bits 50-48) designates one of the data registers 200 as the destination for arithmetic logic unit 230. The "src1" field (bits 47-45) designates a register as the first input for arithmetic logic unit 230. If this instruction includes a transfer format 6 or 10, which include an "As1bank" field (bits 9-6), then this register source may be any register within data unit 110 with the "As1bank" field designating the register bank and the "src1" field designating the register number. In such a case this data cannot be rotated by barrel rotator 235. This is called a long distance arithmetic logic unit operation. For other transfer formats, the "src1" field specifies one of the data registers 200 by register number. Transfer formats 7, 8, 9 and 10 permit the register source to be conditionally selected from a pair of data registers 200 based on the "N" bit of status register 210. If the "N" bit (bit 31) of status register 211 is "1" then the designated data register is selected as the first source for arithmetic logic unit 230. If the "N" bit is "0" then the data register one less is selected. If this option is used, then the register number of the "src1" field must be odd. The "src2" field (bits 44-42) designates one of the data registers 200 as the second input for multiplier 220. The "src2" field (bits 41-39) designates one of the data registers 200 as the second input for multiplier 220. Table 23 shows the data path connections for some of the operations supported in data unit format E. Input C is the signal supplied to input C bus 243 selected by multiplexer Cmux 233. Maskgen is the signal supplied to mask generator 239 selected by multiplexer Mmux 234. Rotate is signal supplied to the control input of barrel rotator 235 selected by multiplexer Smux 231. Product left shift is the signal supplied to the control input of product left shifter 224 selected by multiply shift multiplexer MSmux 225. Note that the special case of the DIVI operation will be described later. Six Operand Operation Input C maskgen rotate product left shift MPYS ∥ ADD - - 0 0 MPYS ∥ SUB - - 0 0 MPYS ∥ EALUT mask D0(4-0) D0(4-0) D0(9-8) MPYS ∥ EALUF mask D0(4-0) D0(4-0) D0(9-8) MPYU ∥ ADD - - 0 0 MPYU ∥ SUB - - 0 0 MPYU ∥ EALUT mask D0(4-0) D0(4-0) D0(9-8) MPYU ∥ EALUF mask D0(4-0) D0(4-0) D0(9-8) EALU src4 - src3 - EALU% | mask | src4 | src1 | - For all the six operand instructions listed in Table 23, the first input to multiplier 220 on bus 201 is the register designated by the "src3" field (bits 56-54), the second input to multiplier 220 on bus 202 is the register designated by the "src4" field (bits 44-42), the input to barrel rotator 235 is the register designated by the "src1" field (bits 41-39) and the input to input A bus 241 is the register designated by the "src2" field (bits 47-45). Also note that multiplier 220 is not used in the EALU and EALU% instructions, instead the results of barrel rotator 235 are saved in the register designated by the "dst2" field (bits 53-51) via multiplexer Bmux 227. The DIVI operation uses arithmetic logic unit 230 and does not use multiplier 220. The DIVI operation may be used in an inner loop for unsigned division. Signed division may be implemented with additional set-up and clean-up instructions to handle the sign of the quotient. It is well known in the art that division is the most difficult of the four basic arithmetic operations (addition, subtraction, multiplication and division) to implement in computers. The DIVI instruction employs the hardware of data unit 110 to compute one digit of the desired quotient per execute pipeline stage, once properly set up. Note that the DIVI data unit instruction can only be used with a data transfer format that supports conditional data transfers (and consequently conditional data unit operations). These data transfer formats 7, 8, 9 and 10 will be fully described below. Multiplexer Amux 232 selects data from data register 200b designated by the "src2" field on arithmetic logic unit first input bus 205 for supply to arithmetic logic unit 230 via input A bus 241. Multiplexer Imux 222 selects the constant Hex "1" for supply to multiplier second input bus 202 and multiplexer Smux 231 selects this Hex "1" on multiplier second input bus 202 for supply to rotate bus 244. Data from one of the data registers 200 designated by the "src1" field supplies barrel rotator 235. This register can only be data register D7, D5, D3 or D1 and is a conditional register source selected by multiplexer 215 based upon the "N" bit (bit 31) of status register 210. If the "N" bit of status register 210 is "0", then data register 200a designated by the "src1" field is selected. This register selection preferably uses the same hardware used to provide conditional register selection in other instructions employing arithmetic logic unit 230, except with the opposite sense. This register selection may be achieved via a multiplexer or by substituting the inverse of the "N" bit of status register 210 for the least significant bit of the register field during specification of the register. If the "N" bit of status register 210 is "1", then data register 200c, which is one less than the register designated by the "src1" field, is selected. Barrel rotator 235 left rotates this data by one bit and supplies the resultant to arithmetic logic unit 230 via input B bus 241. The output of barrel rotator 235 is also saved to data register 200a via multiplexer Bmux 227, with bit 31 of multiple flags register 211 (before rotating) substituted for bit 0 of the output of barrel rotator 235. This destination register is the register designated by the "src1" field. Multiplexer Mmux 234 selects the constant Hex "1" on multiplier second input bus 202 for supply to mask generator 239. Multiplexer Cmux 233 selects the output from mask generator 239 for supply to arithmetic logic unit 230 via input C bus 243. Bit 0 carry-in generator 246 supplies bit 31 of multiple flags register 211 (before rotating) to the carry-in input of arithmetic logic unit 230. During the DIVI instruction arithmetic logic unit 230 receives a function code F7-F0 of Hex "A6". This causes arithmetic logic unit 230 to add the inputs upon input A bus 241 and input B bus 242 and left shift the result with zero extend. This left shift is by one bit due to the mask supplied by mask generator 239 in response to the Hex "1" input. This function is mnemonically A+B<0<. The resultant of arithmetic logic unit 230 is stored in data register 200c designated by the "dst1" field. Multiple flags register 211 is rotated by one bit, and the least significant bit (bit 0) of multiple flags register 211 is set according to the resultant produced by arithmetic logic unit 230. This same bit is stored in the "N" bit (bit 31) of status register 210. OR gate 247 forms this bit stored in multiple flags register 211 and status register 210 from c out of arithmetic logic unit 230 ORed with bit 31 of the input to barrel rotator 235. Note that other status register 210 bits "C", "V" and "Z" are set normally. If the data in data register 200a is X, the data in data register 200b is Y and the data in data register 200c is Z, then the DIVI instruction forms X = X<<1 and Z = X[n]Z+Y. The "n" mnemonic indicates register source selection based upon the "N" status register bit. The DIVI instruction operates to perform iterations of a conditional subtract and shift division algorithm. This instruction can be used for a 32 bit numerator divided by a 16 bit divisor to produce a 16 bit quotient and a 16 bit remainder or a 64 bit numerator divided by a 32 bit divisor to produce a 32 bit quotient and a 32 bit remainder. In the 64 bit numerator case the 32 most significant bits of the numerator are stored initially in data register 200a and the 32 least significant bits are initially stored in multiple flags register 211. Data register 200b stores the inverse of the divisor. For the first iteration of a division operation either the DIVI instruction is executed unconditionally or the "N" bit of status register 210 is set to "0". The rotated number from barrel rotator 235 is stored in data register 200a. Barrel rotator 235 and the rotation of multiple flags register 211 effectively shift the 64 bit numerator one place. Note that the most significant bit of multiple flags register 211 is the next most significant bit of the 64 bit numerator and is properly supplied to the carry-in input of arithmetic logic unit 230. The quantity stored in data register 200a is termed the numerator/running remainder. The result of the trial subtraction is stored in data register 200c. There are two cases for the result of the trial subtraction. If either the most significant bit of the initial numerator was "1" or if the addition of the negative divisor generates a carry, then the corresponding quotient bit is "1". This is stored in the first bit of multiple flags register 211 and in the "N" bit of status register 210. For the next trial subtraction, multiplexer 215 selects data register 200c for the B input for the next iteration by virtue of the "1" in the "N" bit of status register 210. Thus the next trial subtraction is taken from the prior result. If OR gate 247 generates a "0", then the corresponding quotient bit is "0". Thus the next trial subtraction is taken from the prior numerator/running remainder stored in data register 200a shifted left one place. This iteration continues for 32 cycles of DIVI, forming one bit of the quotient during each cycle. The 32 bit quotient is then fully formed in multiple flags register 211. The 32 bit remainder is found in either data register 200a or data register 200c depending upon the state of the "N" bit of status register 210. The process for a 32 bit by 16 bit division is similar. The negated divisor is left shifted 16 places before storing in data register 200b. The entire numerator is stored in data register 200a. The DIVI instruction is repeated only 16 times, whereupon the quotient is formed in the 16 least significant bits of multiple flags register 211 and the remainder in the 16 most significant bits of either data register 200a or data register 200c depending on the state of the "N" bit of status register 210. This technique employs hardware already available in data unit 100 to reduce the overhead of many microprocessor operations. The DIVI instruction essentially forms one bit of an unsigned division. Additional software can be employed to support signed division. Four divide subroutines may be written for the cases of unsigned half word (32 bit/16 bit) divide, unsigned word (64 bit/32 bit) divide, signed half word (32 bit/16 bit) divide, and signed word (64 bit/32 bit) divide. Each of the four subroutines includes three phases: divide preparation; divide iteration in a single instruction loop; and divide wrap-up. It is preferable to employ zero overhead looping and single 64 bit DIVI instruction within the loop kernel. The first part of each division subroutine is divide preparation. This first includes testing for a divisor of zero. If the divisor is "0", then the division subroutine is aborted and an error condition is noted. Next the sign bits are determined for the numerator and divisor. In the signed division subroutines the sign of the quotient is set as an OR of the sign bits of the numerator and divisor. Then in signed division, if either the numerator or divisor is negative they are negated to obtain a positive number. The numerator is spit between a selected odd data register and the multiple flags register 211. For a word division, the upper 32 bits of the numerator are stored in the selected data register and the lower 32 bits of the numerator are stored in multiple flags register 211. For a half word division all 32 bits of the numerator are stored in the selected data register. For the half word division, the unused lower bits of multiple flags register 211 are zero filled. For half word division the divisor is stored in the upper 16 bits of a data register with the lower bits being zero filled. The divisor should be negated so that arithmetic logic unit 230 can form subtraction by addition. The subroutines may compare the absolute values of the most significant bits of the numerator and denominator to determine if the quotient will overflow. The heart of each divide subroutine is a loop including a single DIVI instruction. It is very advantageous to write to one of the register addresses LSRE2-LSRE0 to initialize a zero overhead one instruction loop. Sixteen iterations are needed for half word quotients and 32 for word quotients. Since the loop logic 720 decrements to zero, the loop counter should be loaded with one less than the desired number of iterations. It is also possible to place up to two iterations of the DIVI instruction in the delay slots following loop logic initialization. The single instruction within this loop is the DIVI instruction, which has been fully described above. Each division subroutine is completed with divide wrap-up. Divide wrap-up includes the following steps. The quotient is moved from multiple flags register 211 to a data register. If the sign of the quotient is negative, then "1" is added to the quotient in the data register to convert from "1's" complement representation to twos complement representation. If the remainder is needed it is selected based upon the "N" bit of status register 210. A description of the data transfer formats and an explanation or glossary of various bits and fields of the parallel data transfer formats of instruction words of Figure 18 follows. As previously described above in conjunction with the glossary of bits and fields of the data unit formats these bits and fields define not only the instruction word but also the circuitry that enable execution of the instruction word. Transfer format 1 is recognized by bits 38-37 not being "00", bits 30-28 not being "000" and bits 16-15 not being "00". Transfer format 1 is called the double parallel data transfer format. Transfer format 1 permits two independent accesses of memory 20, a global access and a local access limited to the memory sections corresponding to the digital image/graphics processor. The "Lmode" field (bits 38-35) refers to a local transfer mode, which specifies how the local address unit of address unit 120 operates. This field is preferably decoded as shown in Table 24. Lmode field Expression Syntax Operation Description 3 3 3 3 8 7 6 5 0 0 X X no operation 0 1 0 0 *(An++=Xm) post-addition of index register with modify 0 1 0 1 *(An--=Xm) post-subtraction of index register with modify 0 1 1 0 *(An++=Imm) post-addition of offset with modify 0 1 1 1 *(An--=Imm) post-subtraction of offset with modify 1 0 0 0 *(An+Xm) pre-addition of index register 1 0 0 0 *(An-Xm) pre-subtraction of index register 1 0 1 0 *(An+Imm) pre-addition of offset 1 0 1 1 *(An-Imm) pre-subtraction of offset 1 1 0 0 *(An+=Xm) pre-addition of index register with modify 1 1 0 1 *(An-=Xm) pre-subtraction of index register with modify 1 1 1 0 *(An+=Imm) pre-addition of offset with modify 1 1 1 1 *(An-=Imm) pre-subtraction of offset with modify The "d" field (bits 34-32) designates one of the data registers D0-D7 to be the source or destination of a local bus transfer. The "e" bit (bit 31) if "1" designates sign extend, else if "0" designates zero extend for the local data transfer. This is operative in a memory to register transfer when the local "siz" field (bits 30-29) indicates less than a full 32 bit word size. This "e" bit is ignored if the data size is 32 bits. The combination of "e" (bit 31) = "1" and "L" (bit 21) = "0", which would otherwise be meaningless, indicates a local address unit arithmetic operation. The local "siz" field (bits 30-29) is preferably coded as shown in Table 25. Size field Data word size 3 2 0 9 0 0 byte 8 bits 0 1 half word 16 bits 1 0 whole word 32 bits 1 1 reserved The "s" bit (bit 28) sets the scaling mode that applies to local address index scaling. If the "s" bit is "1" the index in the address calculation, which may be recalled from an index register or an instruction specified offset, is scaled to the size indicated by the "siz" field. If the "s" bit is "0", then no scaling occurs. As previously described this index scaling takes place in index scaler 614. If the selected data size is 8 bits (byte), then no scaling takes place regardless of the status of the "s" bit. In this case only, the "s" bit may be used as an additional offset bit. If the "Lmode" field designates an offset then this "s" bit becomes the most significant bit of the offset and converts the 3 bit offset index of the "Lim/x" field to 4 bits. The "La" field (bits 27-25) designates an address register within local address unit 620 of address unit 120 for a local data transfer. The "L" bit (bit 21) indicates the local data transfer is a load transferring data form memory to register (L = "1") or a store transferring data from register to memory (L = "0") transfer. The "Lim/x" field (bits 2-0) specifies either the register number of an index register or a 3 bit offset depending on the coding of the "Lmode" field. The global data transfer operation is coded in a fashion similar to the coding of the local data transfer. The "L" bit (bit 17) is a global load/store select. This bit determines whether the global data transfer is a memory to register ("L" = "1") transfer, also known as a load, or a register to memory ("L" = "0") transfer, also known as a store. The "Gmode" field (bits 16-13) defines a global transfer mode in the same way the local transfer mode is defined by the "Lmode" field. This field is preferably decoded as shown in Table 26. Gmode field Expression Syntax Operation Description 1 1 1 1 6 5 4 3 0 0 X X no operation 0 1 0 0 *(An++=Xm) post-addition of index register with modify 0 1 0 1 *(An--=Xm) post-subtraction of index register with modify 0 1 1 0 *(An++=Imm) post-addition of offset with modify 0 1 1 1 *(An--=Imm) post-subtraction of offset with modify 1 0 0 0 *(An+Xm) pre-addition of index register 1 0 0 1 *(An-Xm) pre-subtraction of index register 1 0 1 0 *(An+Imm) pre-addition of offset 1 0 1 1 *(An-Imm) pre-subtraction of offset 1 1 0 0 *(An+=Xm) pre-addition of index register with modify 1 1 0 1 *(An-=Xm) pre-subtraction of index register with modify 1 1 1 0 *(An+=Imm) pre-addition of offset with modify 1 1 1 1 *(An-=Imm) pre-subtraction of offset with modify The "reg" field (bits 12-10) identifies a register. The "reg" field designates the number of the source register in the case of a store, or the number of the destination register in the case of a load. The "0bank" field (bits 20-18) contains three bits and identifies a bank of registers in the lower 64 registers. These registers have register bank numbers in the form "0XXX". The 3 bit "0bank" filed combines with the 3 bit "reg" field to designate any register in the lower 64 registers as the data source or destination for the global data transfer. The "e" bit (bit 9) if "1" designates sign extend, else if "0" designates zero extend for the global data transfer. This is operative in a memory to register transfer when the global "siz" field (bits 8-7) indicates less than a full 32 bit word size. This "e" bit is ignored if the data size is 32 bits. The combination of "e" (bit 9) = "1" and "L" (bit 17) = "0" indicates a global address unit arithmetic operation. The global "siz" field (bits 8-7) is preferably coded as shown in Table 27. Size field Data word size 8 7 0 0 byte 8 bits 0 1 half word 16 bits 1 0 whole word 32 bits 1 1 reserved The "s" bit (bit 6) sets the scaling mode that applies to global address index scaling. If the "s" bit is "1" the index in the address calculation, which may be recalled from an index register or an instruction specified offset, is scaled to the size indicated by the "siz" field. If the "s" bit is "0", then no scaling occurs. No scaling takes place regardless of the status of the "s" bit if the "siz" field designates a data size of 8 bits. If the "Gmode" field designates an offset then this "s" bit becomes the most significant bit of the offset and converts the 3 bit offset index of the "Gim/x" field to 4 bits. The "Ga" field (bits 5-3) designates an address register within global address unit 610 of address unit 120 for a local bus transfer. The "Gim/×" field (bits 24-22) specifies either the register number of an index register or a 3 bit offset depending on the coding of the "Gmode" field. The "Ga" field (bits 5-3) specifies the register number of the address register used in computing the memory address of the global data transfer. Data transfer format 2 is recognized by bits 38-37 not being "00", bits 30-28 being "000" and bits 16-15 not being "00". Data transfer format 2 is called the XY patch format. Data transfer format 2 permits addressing memory 20 in an XY patch manner multiplexing addresses from both the global and local address units of address unit 120. The "o" bit (bit 34) enables outside XY patch detection. When "o" bit is set to "1", the operations specified by the bits "a" and "n" are performed if the specified address is outside the XY patch. Otherwise, when "o" bit is "0", the operations are performed if address is inside the patch. The "a" bit (bit 33) specifies XY patch memory access mode. When the "a" bit is set to "1", the memory access is performed regardless of whether the address is inside or outside the XY patch. When the "a" bit is set to "0", the memory access is inhibited if the address is outside (if the "o" bit is "1") or inside (if the "o" bit is "0") the patch. The "n" bit (bit 32) specifies XY patch interrupt mode. When the "n" bit is set to "1", an interrupt flag register bit for XY patch is set to "1" if the address is outside (if "o" bit is "1") or inside (if "o" bit is "0") the patch. When "n" bit is set to "0", the XY patch interrupt request flag is not set. Other fields are defined in the same manner detailed above. The "Lmode" field specifies the local address calculation mode as shown in Table 28. This local address calculation includes a local address register designated by the "La" field and either a 3 bit unsigned offset or a local index register designated by the "Lim/x" field. The "Gmode" field specifies the global address calculation. A global unsigned 3 bit offset or a global index register indicated by the "Gim/X" field is combined with the address register specified by the "Ga" field to form the global address. The 4 bit "bank" field (bits 21-18) identifies a data register bank and is combined with the 3 bit "reg" field identifying a register number to designate any register as the data source or destination for an XY Patch access. The "L" bit is a load/store select. This bit determines whether an XY Patch access is a memory to register ("L" = "1") transfer, also know as a load, or register to memory ("L" = "0") transfer, also known as a store. The "e" bit if "1" designates sign extend, else if "0" designates zero extend. This is operative in a load operation (memory to register data transfer) when the "siz" field indicates less than a full 32 bit word size. This "e" bit is ignored if the data size is 32 bits. The combination of "e" = "1" with "L" = "0" indicates a patched address unit arithmetic operation. The "s" bit sets the scaling mode that applies to global address index scaling. If the "s" bit is "1" the data recalled from memory is scaled to the size indicated by the "siz" field. If the "s" bit is "0", then no scaling occurs. If the selected data size is 8 bits (byte), then no scaling takes place regardless of the status of the "s" bit. In this case only, the "s" bit is used as the most significant bit of the offset converting the 3 bit "Gim/x" offset index to 4 bits. Data transfer format 3 is recognized by bits 38-37 not being "00", bit 24 being "0" and bits 16-13 being "0000". Data transfer format 3 is called the move and local data transfer format. Data transfer format 3 permits a load or store of one of the data registers 200 via the local data port in parallel with a register to register move using global port source data bus Gsrc 105 and global port destination data bus Gdst 107. The local data port operation is defined by the fields "Lmode", "d", "e", "siz", "s", "La", "L" and "Lim/x" in the manner described above. The register to register move is from the register defined by the bank indicated by the "srcbank" field (bits 9-6) and the register number indicated by the "src" field (bits 12-10) to the register defined by the bank indicated by the "dstbank" field (bits 21-18) and the register number indicated by the "dst" field (bits 5-3). Data transfer format 3 supports digital image/graphics processor relative addressing. The "Lrm" field (bits 23-22) indicate the type of addressing operation. This is set forth in Table 28. Lrm field Addressing Mode 8 7 0 0 normal addressing 0 1 reserved 1 0 Data memory base address DBA 1 1 Parameter memory base address PBA Specification of DBA causes local address unit 620 to generate the base address of its corresponding memory. Likewise, specification of PBA causes local address generator 620 to generate the base address of the corresponding parameter memory. The base address generated in this manner may be combined with the index stored in an index register or an offset field in any of the address generation operations specified in the "Lmode" field shown in Table 24. This data transfer format also supports command word generation. If the destination of the register to register move is the zero value address register of the global address unit A15, then the instruction word decoding circuitry initiates a command word transfer to a designated processor. This command word is transmitted to crossbar 50 via the global data port accompanied by a special command word signal. This allows interprocessor communication so that, for example, any of digital image/graphics processors 71, 72, 73 and 74 may issue an interrupt to other processors. This process is detailed above. Data transfer format 4 is recognized by bits 38-37 not being "00", bit 24 being "0" and bits 16-13 being "0001". Data transfer format 4 is called the field move and local data transfer format. Data transfer format 4 permits a load or store of one of the data registers 200 via the local data port in parallel with a register to register field move using global port source data bus Gsrc 105 and global port destination data bus Gdst 107. The local data port operation is defined by the fields "Lmode", "d", "e" (bit31), "siz" (bits 30-29), "s", "La", "L" and "Lim/x" in the manner described above. The register to register field move is from the data register defined by the register number indicated by the "src" field (bits 12-10) to the register defined by the bank indicated by the "dstbank" field (bits 21-18) and the register number indicated by the "dst" field (bits 5-3). The "D" bit (bit 6) indicates if the field move is a field replicate move if "D" = "1", or a field extract move if "D" = "0". In a field replicate move the least significant 8 bits of the source register are repeated four times in the destination register if the "siz" field (bits 8-7) indicates a byte size, and the least significant 16 bits of the source register are duplicated in the destination register if the "siz" field (bits 8-7) indicates a half word size. If the "siz" field indicate a word size, then the whole 32 bits of the source register are transferred to the destination register without replication regardless of the state of the "D" bit. In a field extract move the "itm" field (bits 23-22) indicates the little endian item number to be extracted from the source register. The particular bits extracted also depends upon the "siz" field. When the data size of the "siz" field (bits 8-7) is byte, then "itm" may be 0, 1, 2 or 3 indicating the desired byte. When the data size of the "siz" field (bits 8-7) is half word, then "itm" may be 0 or 1 indicating the desired half word. The "itm" field is ignored if the "siz" field (bits 8-7) is word. The extracted field from the source register is sign extended if the "e" bit (bit 9) is "1" and zero extended if the "e" bit (bit 9) is "0". The "e" field is ignored during field replicate moves. Data transfer format 5 is recognized by bits 38-37 not being "00", bit 24 being "1" and bits 16-15 being "00". Data transfer format 5 is called local long offset data transfer. Data transfer format 5 permits a global port memory access using an address constructed in the local address unit because no global data transfer is possible. The local data port operation is defined by the fields "Lmode", "d", "e", "siz", "s", "La" and "L" in the manner described above. The register source or destination corresponds to the register number designated in the "reg" field (bits 34-32) in the bank of registers designated in the "bank" field (bits 21-18). The "Local Long Offset/x" field (bits 14-0) specifies a 15 bit local address offset or the three least significant bits specify an index register as set by the "Lmode" field. A programmer might want to use this data transfer format using an index register rather than the "Local long offset" field because data transfer format 5 permits any data unit register as the source for a store or as the destination for a load. The "Lmode" field indicates whether this field contains an offset value or an index register number. If the selected data size is 8 bits (byte), then no scaling takes place regardless of the status of the "s" bit. In this case only, the "s" bit becomes the most significant bit of the offset converting the 15 bit "Local long offset" field into 16 bits. The "Lrm" field (bits 23-22) specify a normal address operation, a data memory base address operation or a parameter memory base operation as listed above in Table 28. Data transfer format 6 is recognized by bits 38-37 being "00", bits 16-15 not being "00" and bit 2 being "0". Data transfer format 6 is called global long offset data transfer. Data transfer format 6 is similar to data transfer format 5 except that the address calculation occurs in the global address unit. The fields "bank", "L", "Gmode", "reg", "e", "siz", "s" and "Ga" are as defined above. The "Global Long Offset/x" field (bits 36-22) specifies a global offset address or an index register depending on the "Gmode" field. This is similar to the "Local Long Offset/x" field discussed above. The "Grm" field (bits 1-0) indicate the type of addressing operation. This is set forth in Table 29. Grm field Addressing Mode 1 0 0 0 normal addressing 0 1 reserved 1 0 Data memory base address DBA 1 1 Parameter memory base address PBA This operates in the same fashion as the "Lrm" field described above except that the address calculation takes place in global address unit 610. Data transfer format 7 is recognized by bits 38-37 not being "00", bit 24 being "0" and bits 16-14 being "001". Data transfer format 7 is called the non-data register data unit operation and local data transfer format. Data transfer format 7 permits a local port memory access in parallel with a data unit operation where the first source for arithmetic logic unit 230 and the destination for arithmetic logic unit 230 may be any register on digital image/graphics processor 71. The local data port operation is defined by the fields "Lmode", "d", "e", "siz", "s", "La", "Lrm", "L" and "Lim/x" in the manner described above. The "Adstbnk" field (bits 21-18) specifies a bank of registers for the arithmetic logic unit destination. This field specifies a register source in combination with the "dst" field in data unit formats A, B and C, and the "dst1" field in data unit format D. The "As1bank" field specifies a bank of registers for the first arithmetic logic unit source. This specifies a register source in combination with the "src1" field in data unit formats A, B, C and D. These data unit operations are called long distance arithmetic logic unit operations because the first source and the destination need not be the data registers 200 of data unit 110. Data transfer format 8 is recognized by bits 38-37 being "00", bit 24 being "0" and bits 16-13 being "0000". Data transfer format 8 is called the conditional data unit operation and conditional move transfer format. Data transfer format 8 permits conditional selection of the first source for arithmetic logic unit 230 and conditional storing of the resultant of arithmetic logic unit 230. The conditional arithmetic logic unit operations are defined by the fields "cond.", "c", "r", "g" and "N C V Z". The "cond." field (bits 35-32) defines an arithmetic logic unit operation from conditional register sources and conditional storage of the arithmetic logic unit resultant. This field is defined in Table 20. These conditions are evaluated based upon the "N", "C", "V" and "Z" bits of status register 210. The specified condition may determine a conditional register source, a conditional storage of the result of arithmetic logic unit 230 or a conditional register to register move. The "c" bit (bit 31) determines conditional source selection. If the "c" bit is "0", then the first source for arithmetic logic unit 230 is unconditionally selected based upon the "src1" field (bits 47-45) of the data unit format portion of the instruction word. If the "c" bit is "1", then the register source is selected between an odd and even register pair. Note that in this case the "src1" field must specify an odd numbered data register 200. If the condition is true, then the specified register is selected as the first source for arithmetic logic unit 230. If the condition is false, then the corresponding even data register one less than the specified data register is selected as the source. The preferred embodiment supports conditional source selection based upon the "N" bit of status register 210. If the "N" field of status register 210 is "1" then the designated data register is selected as the first source for arithmetic logic unit 230. If the "N" field of status register 210 is "0", then the data register one less is selected. This selection can be made by a multiplexer or by substitution of the "N" field of status register 210 for the least significant bit of the register number. While the preferred embodiment supports only conditional source selection based upon the "N" bit of status register 210, it is feasible to provide conditional source selection based upon the "C", "V" and "Z" bits of status register 210. Data transfer format 8 supports conditionally storing the resultant of arithmetic logic unit 230. The "r" bit (bit 30) indicates if storing the resultant is conditional. If the "r" bit is "1" then storing the resultant is conditional based upon the condition of the "cond." field. If the "r" bit is "0", then storing the resultant is unconditional. Note that in a conditional result operation, the status bits of status register 210 are set unconditionally. Thus these bits may be set even if the result is not stored. Data transfer format 8 also permits a conditional register to register move operation. The condition is defined by the same "cond." field that specifies conditional data unit operations. The register data source of the move is defined by the bank indicated by the "srcbank" field (bits 9-6) and the register number indicated by the "src" field (bits 12-10). The register data destination is defined by the bank indicated by the "dstbank" field (bits 21-18) and the register number indicated by the "dst" field (bits 5-3). The "g" bit (bit 29) indicates if the data move is conditional. If the "g" bit is "1", the data move is conditional based upon the condition specified in the "cond." field. If the "g" bit is "0", the data move is unconditional. Note that a destination of the zero value address register A15 of the global address unit generates a command word write operation as previously described above. Thus data transfer format 8 permits conditional command word generation. The "N C V Z" field (bits 28-25) indicates which bits of the status are protected from alteration during execution of the instruction. The conditions of the status register are: N negative; C carry; V overflow; and Z zero. If one or more of these bits are set to "1", the corresponding condition bit or bits in the status register are protected from modification during execution of the instruction. Otherwise the status bits of status register 210 are set normally according to the resultant of arithmetic logic unit 230. Data transfer format 9 is recognized by bits 38-37 being "00", bit 24 being "0" and bits 16-13 being "0001". Data transfer format 9 is called the conditional data unit operation and conditional field move transfer format. Data transfer format 9 permits conditional selection of the first source for arithmetic logic unit 230 and conditional storing of the resultant of arithmetic logic unit 230 in the same manner as data transfer format 8. The conditional arithmetic logic unit operations are defined by the fields "cond.", "c", "r" and "N C V Z" as noted above in the description of data transfer format 8. Data transfer format 9 also supports conditional register to register field moves. The condition is defined by the same "cond." field that specifies conditional data unit operations. The source of the field move must be one of data registers 200. The "src" field (bits 12-10) specifies the particular data register. The destination of the register to register move is the register defined by the register bank of the "dstbank" field (bits 21-18) and the register number of the "dst" field (bits 5-3). The fields "g" (bit 29), "itm" (bits 23-22), "e" (bit 9), "siz" (bits 8-7) and "D" (bit 6) define the parameters of the conditional field move. The "g" bit determines that the field move is unconditional if "g" = "0" and that the field move is conditional if "g" = "1". The "D" bit indicates if the field move is a field replicate move if "D" = "1", or a field extract move if "D" = "0". These options have been described above. In a field extract move the "itm" field (bits 23-22) indicates the little endian item number to be extracted from the source register base upon the data size specified by the "siz" field. The extracted field from the source register is sign extended if the "e" bit (bit 9) is "1" and zero extended if the "e" bit (bit 9) is "0". The "e" field is ignored during field replicate moves. Data transfer format 10 is recognized by bits 38-37 being "00", bits 16-15 not being "00" and bit 2 being "1". Data transfer format 10 is called the conditional data unit operation and conditional global data transfer format. Data transfer format 10 permits conditional selection of the first source for arithmetic logic unit 230 and conditional storing of the resultant of arithmetic logic unit 230. The conditional arithmetic logic unit operations are defined by the fields "cond.", "c", "r" and "N C V Z" as noted above in the description of data transfer format 8. Data transfer format 10 also supports conditional memory access via global address unit 610. The conditional memory access is specified by the fields "g", "Gim/x", "bank", "L", "Gmode", "reg", "e", "siz", "s", "Ga" and "Grm" as previously described. The "g" bit (bit 29) indicates if the data move is conditional in the manner previously described above. The "Gim/x" field specifies either an index register number or an offset field depending upon the state of the "Gmode" field. The "bank" field specifies the register bank and the "reg" field specifics the register number of the register source or destination of the global memory access. The "L" indicates a load operation (memory to register transfer) by a "1" and a store operation (register to memory transfer) by a "0". The "Gmode" field indicates the operation of global data unit 610 as set forth in Table 26. The "e" bit indicates sign or zero extension for load operations. Note an "L" field of "0" and an "e" field of "1" produces an address arithmetic operation. The "siz" field specifies the data size as set forth in Table 27. The "s" bit indicates whether the index is scaled to the data size as described above. The "Ga" field specifies the address register used in address computation. The "Grm" field indicates the type of addressing operation as set forth in Table 29. Data transfer format 11 is recognized by bits 38-37 being "00", bit 24 being "0" and bits 16-14 being "001". Data transfer format 11 is called the conditional non-data register data unit format. Data transfer format 11 permits no memory accesses. Instead data transfer format 11 permits conditional data unit operation with one source and the destination for arithmetic logic unit 230 as any register within digital image/graphics processor 71. These are called long distance arithmetic logic unit operations. The "As1bank" field (bits 9-6) specifies a bank of registers that defines the first arithmetic logic unit source in combination with the "src1" field (bits 47-45) in the data unit format of the instruction. Thus this source may be any register within digital image/graphics processor 71. The "Adstbnk" field (bits 21-18) specifies a bank of registers that defines the arithmetic logic unit destination in combination with the "dst" field (bits 50-48) in data unit formats A, B and C, and the "dst1" field (bits 50-48) in data unit format E. The conditional arithmetic logic unit operations are defined by the fields "cond.", "c", "r" and "N C V Z" as noted above in the description of data transfer format 8. The "R" bit (bit 0) is a reset bit. The "R" bit is used only at reset. This "R" bit is used only upon reset. The "R" bit determines whether the stack pointer register A14 is initialized upon reset of digital image/graphics processor 71. This "R" bit is not available to users via the instruction set and will not be further described. With so many operations possible within a single instruction, it is possible that more than one operation of a single instruction specifies the same destination data register 200. In such an event a fixed order of priority determines which operation saves its result in the commonly specified destination register. This fixed order of priority is shown in Table 30 in order from highest priority to lowest priority. Priority Rank Operation highest Global address unit data transfer median Local address unit data transfer lowest Data unit Multiply/ALU => Multiply Rotate/ALU => ALU Thus global address unit data transfers have the highest priority and data unit operations have the lowest priority. Since more than one data unit operation can take place during a single instruction, there is a further priority rank for such operations. If a multiply operation and an arithmetic logic unit operation have the same destination register, then only the result of the multiply operation is stored. In this case no status bits are changed by the aborted arithmetic logic unit operation. Note that if the storing of the result of an arithmetic logic unit operation is aborted due to conflict with a global or local address unit data transfer, then the status bits are set normally. If a barrel rotation result and an arithmetic logic unit operation have the same destination, then only the results of the arithmetic logic unit operation is stored. In this case the status bits are set normally for the completed arithmetic logic unit operation. Multiprocessor integrated circuit 101 is illustrated in Figure 19 as part of a color facsimile apparatus. Modem 1301 is bidirectionally coupled to a telephone line for sending and receiving. Modem 1301 also communicates with buffer 1302, which is further coupled the image system bus. Modem 1301 receives a facsimile signal via the telephone line. Modem 1301 demodulates these signals, which are then temporarily stored in buffer 1302. Transfer controller 80 services buffer 1302 by transferring data to data memories 22, 23 and 24 for processing by digital image/graphics processor 71. In the event that digital image/graphics processor 71 cannot keep ahead of the incoming data, transfer controller 80 may also transfer data from buffer 1302 to memory 9. Digital image/graphics processor 71 processes the image data of the incoming facsimile. This may include image decompression, noise reduction, error correction, color base correction and the like. Once processed, transfer controller 80 transfers image data from data memories 22, 23 and 24 to video random access memory (VRAM) 1303. Printer controller 1304 recalls the image data under control of frame controller 90 and supplies it to color printer 1305, which forms the hard copy. The apparatus of Figure 19 can also send a color facsimile. Imaging device 3 scans the source document. Imaging device 3 supplies the raw image data to image capture controller 4 that operates under control of frame controller 90. This image data is stored in video random access memory 1303. Note that the embodiment illustrated in Figure 19 shares video random access memory 1303 for both image capture and image display in contrast to the embodiment of Figure 1, which uses separate video random access memories. Transfer controller 80 transfers this image data to data memories 22, 23 and 24. Digital image/graphics processor 71 then processes the image data for image compression, error correction redundancy, color base correction and the like. The processed data is transferred to buffer 1303 by transfer controller 80 as needed to support the facsimile transmission. Depending upon the relative data rates, transfer controller 80 may temporarily store data in memory 9 before transfer to buffer 1302. This image data in buffer 1302 is modulated by modem 1301 and transmitted via the telephone line. Note that the presence of an imaging device and a color printer in the same system permits this system to also operate as a color copier. In this event data compression and decompression may not be required. However, digital image/graphics processor 71 is still useful for noise reduction and color base correction. It is also feasible for digital image/graphics processor 71 to be programmed to deliberately shift colors so that the copy has different coloring than the original. This technique, known as false coloring, is useful to conform the dynamic range of the data to the dynamic range of the available print colors.

Claims: A data processing apparatus (110) comprising a plurality of N data registers (200) characterised in that said plurality of N data registers (200) are connected to a data processor bus (201-206) and each data register (200) has a plurality of I bits divided into M equal bit groups, where N, I and M are integers and I equals N times M, the data processing apparatus (110) further comprising a register selection circuit connected to said N data registers (200), said register selection circuit being arranged to select a specified data register for read access via said data processor bus in a normal register read mode, select a specified data register for write access via said data processor bus in a normal register write mode and select I mutually noncontiguous bits from a predetermined position within each of said M equal bit groups for each said N data registers for read access via said data processor bus in response to a rotation register read mode. A data processing apparatus as claimed in claim 1, wherein said register selection circuit is further arranged to select I mutually noncontiguous bits from a predetermined position within each of said M sections for each said N data registers (200) for write access via said data processor bus in response to a rotation register write mode. A data processing apparatus as claimed in claim 1 and further comprising at least one additional data processor bus, wherein said each of said N data registers is connected to said at least one additional data processor bus and said register selection circuit is further arranged to select a specified data register for read access via a specified one of said at least one additional data processor bus in an additional data processor bus register read mode, and select a specified data register for write access via a specified one of said at least one additional data processor bus in an additional data processor bus register write mode. A data processing apparatus as claimed in claim 1, wherein: said N data registers (200) comprise 32 bit registers having 4 sections of 8 bits each; and said register selection circuit is further arranged to select 32 bits from a first position within each of said 4 sections of each said 8 data registers for read access via said data processor bus in response to a rotation register read mode. A data processing apparatus as claimed in claim 1 and further comprising: a source of instructions including at least one normal register read mode instruction, at least one normal register write mode instruction and at least one rotation register read mode instruction; an instruction decode logic connected to said register selection circuit and said source of instructions, said instruction decode logic being arranged to control said register selection circuit to: enter said normal register read mode, select an instruction specified data register and transfer I bits of data stored in said instruction specified data register to said data processor bus in response to a normal register read mode instruction; enter said normal register write mode, select an instruction specified data register and transfer I bits of data from said data processor bus to said instruction specified data register in response to a normal register write mode instruction; and enter said rotation register read mode, select said I mutually noncontiguous bits and transfer said selected I mutually noncontiguous bits from said plurality of data registers (200) to said data processor bus in response to a rotation register read mode instruction. A data processing apparatus as claimed in claim 5 and further comprising an arithmetic logic unit (230) having at least two inputs and an output, said arithmetic logic unit forming an instruction specified combination of said at least two inputs at said output, wherein said source of instructions includes at least one arithmetic logic unit instruction having source register fields specifying one of said data registers (200) for input to each of said at least two inputs of said arithmetic logic unit (230), a destination register field specifying one of said data registers (200) for storing said output of said arithmetic logic unit and an arithmetic logic unit operation field designating a combination to be formed by said arithmetic logic unit, and said instruction decode logic is further coupled to said arithmetic logic unit to supply data recalled from said data registers specified in said source register fields to corresponding inputs of said arithmetic logic unit, control said arithmetic logic unit to form said combination specified in said arithmetic logic unit operation field and store said output of said arithmetic logic unit in said data register specified by said destination field in response to an arithmetic logic unit instruction. A data processing apparatus as claimed in claim 5, wherein said at least one rotation register read mode instruction includes an indication of said predetermined position within each of said M sections of said selected I mutually noncontiguous bits and said instruction decode logic is arranged to select said I mutually noncontiguous bits within said plurality of data registers (200) corresponding to said predetermined position within each of said M sections indicated in said rotation register read mode instruction. A data processing apparatus as claimed in claim 1, wherein said plurality of N data registers (200) are connected together in a loop with a most significant bit of one data register connected to a least significant bit of a sequential data register, a most significant bit of a last sequential data register connected to a least significant bit of a first sequential data register and said register selection circuit is further arranged to rotate the bits in each data register within said loop in a register rotation mode. A data processing apparatus as claimed in claim 8, wherein said register selection circuit is further arranged to rotate the bits in each data register one bit position within said loop in said register rotation mode. A data processing apparatus (110) comprising a plurality of N data registers (200) characterised in that said plurality of N data registers (200) are connected to a data processor bus (201-206) and each data register (200) has a plurality of I bits divided into M equal bit groups, where N, I and M are integers and I equals N times M, the data processing apparatus (110) further comprising a register selection circuit connected to said N data registers (200), said register selection circuit being arranged to select a specified data register for read access via said data processor bus in a normal register read mode, select a specified data register for write access via said data processor bus in a normal register write mode and select I mutually noncontiguous bits from a predetermined position within each of said M equal bit groups for each said N data registers for write access via said data processor bus in response to a rotation register write mode. A data processing apparatus as claimed in claim 10 and further comprising at least one additional data processor bus wherein said each of said N data registers is connected to said at least one additional data processor bus and said register selection circuit is further arranged to select a specified data register for read access via a specified one of said at least one additional data processor bus in an additional data processor bus register read mode, and to select a specified data register for write access via a specified one of said at least one additional data processor bus in an additional data processor bus register write mode. A data processing apparatus as claimed in claim 10, wherein said N data registers (200) comprise 32 bit registers having 4 sections of 8 bits each and said register selection circuit is further arranged to select 32 bits from a first position within each of said 4 sections of each said 8 data registers for read access via said data processor bus in response to a rotation register read mode. A data processing apparatus as claimed in claim 10 and further comprising: a source of instructions including at least one normal register read mode instruction, at least one normal register write mode instruction and at least one rotation register write mode instruction; an instruction decode logic connected to said register selection circuit and said source of instructions, said instruction decode logic being arranged to control said register selection circuit to: enter said normal register read mode, select an instruction specified data register and transfer I bits from said instruction specified data register to said data processor bus in response to a normal register read mode instruction, enter said normal register write mode, select an instruction specified data register and transfer I bits from said data processor bus to said instruction specified data register in response to a normal register write mode instruction, and enter said rotation register write mode, select said I mutually noncontiguous bits and transfer I bits from said data processor bus to said I mutually noncontiguous bits of said plurality of N data registers (200) in response to a rotation register write mode instruction. A data processing apparatus as claimed in claim 13 and further comprising: an arithmetic logic unit (230) having at least two inputs and an output, said arithmetic logic unit forming an instruction specified combination of said at least two inputs at said output, wherein said source of instructions includes at least one arithmetic logic unit instruction having source register fields specifying one of said data registers (200) for input to each of said at least two inputs of said arithmetic logic unit (230), a destination register field specifying one of said data registers for storing said output of said arithmetic logic unit and an arithmetic logic unit operation field designating a combination to be formed by said arithmetic logic unit, and said instruction decode logic is further coupled to said arithmetic logic unit to supply data recalled from said data registers specified in said source register fields to corresponding inputs of said arithmetic logic unit, control said arithmetic logic unit to form said combination specified in said arithmetic logic unit operation field and store said output of said arithmetic logic unit in said data register specified by said destination field in response to an arithmetic logic unit instruction. A data processing apparatus as claimed in claim 13, wherein said at least one rotation register write mode instruction includes an indication of said predetermined position within each of said M sections of said selected I mutually noncontiguous bits and said instruction decode logic is further arranged to select said I mutually noncontiguous bits within said plurality of data registers (200) corresponding to said predetermined position within each of said M sections indicated in said rotation register write mode instruction. A data processing apparatus as claimed in claim 10, wherein said plurality of N data registers (200) are connected together in a loop with a most significant bit of one data register connected to a least significant bit of a sequential data register, a most significant bit of a last sequential data register connected to a least significant bit of a first sequential data register and said register selection circuit is further arranged to rotate the bits in each data register within said loop in a register rotation mode. A data processing apparatus as claimed in claim 16, wherein said register selection circuit is further arranged to rotate the bits in each data register one bit position within said loop in said register rotation mode.

Inventors: BALMER KEITH, BALMER, KEITH
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1994
Main classification: G06F5
IPC codes: G06F3, G06F17, G11C19, G06F9, G09G5