READ-ONLY MEMORY CELL

Abstract: A Read-Only Memory (ROM) cell (9) includes a first control gate (36) dielectrically disposed atop a first portion (34A) of a channel (34), and a second control gate (39) dielectrically disposed atop a second portion (34B) of the channel (34). Addressing of the ROM cell (9) involves a simultaneous energization of both the control gates (36 and 39). The energization of only one control gate, but not both, cannot activate the ROM cell (9). ROM cells of the present invention can be arranged in a matrix of rows and columns. The second control gates (39) in each of the memory cells in a row of the matrix can be electrically connected together, and the first control gates (36) of each of the memory cells in a column can be electrically connected together. Addressing of each of the ROM cell (9) in the matrix is simply the simultaneous energization of a pair of the connected control gates (36 and 39) criss-crossing the underlying memory cell.

Description: Description Read-only Memory Cell Technical Field This invention relates to electronic memory devices. More specifically, this invention is related to Read-Only Memory (ROM) devices fabricated in a semiconductor substrate. Contrary to volatile memory devices, such as Random Access Memory (RAM) , non-volatile devices such as ROM retain their informational contents even with power loss. The informational contents are built-in ROM codes pre-defined in the ROM cells during the fabrication process. Background Art Various methods have been practiced in the past for the implementation of a computational storage element. One approach is to insert a fuse or a diode between two address lines. The conducting or non-conducting states of the fuse or the diode are used to correspond to the digital bits "0" and "1", respectively, for example. A more sophisticated approach is to use a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as a basic storage element. A presence or an absence of a drain contact of the MOSFET can be utilized to represent the digital bits "1" or "0", respectively, for instance. Alternatively, different levels of the MOSFET's threshold voltage can also be used to correspond to the different digital data. As the demand for integrated circuits with large scale integration increases, ROM cells are designed with smaller geometries and with simpler structures. These simplified ROM cells are commonly known as "Flat Cells". An example of such a cell is shown in Fig. la, in which six cells C1-C6 are shown as compactly placed together in a semiconductor substrate 10. Figs, lb and lc are cross-sectional side views taken along lines lb-lb and lc-lc, respectively, of Fig. la. Formed in the semiconductor substrate 10 are a plurality of parallelly diffused N+ bitlines 12. Channel regions 14 are defined in between the plurality of bitlines 12. ROM codes can be pre-defined by doping the channel regions 14 at various dopant concentration. For example, via the process of ion implementation, selected channel regions 14 can be doped with a certain dosage of P+ ions, thereby raising the threshold voltage of the MOSFETs fabricated atop the channel regions 14 later. The MOSFETs with raised threshold voltages can be treated as storing the logical bits "1", for example. Formed atop insulating layer 16 are a plurality of polysilicon wordlines 18. ordlines 18 are generally perpendicular to and dielectrically disposed atop the bitlines 12. Beyond the channel regions 14 are P+ insulation regions 20, defining the individual ROM cells. Fig. 2 is a schematic representation of the ROM cells shown in Figs, la-lc. Simple as it may appear, such ROM cells require very complicated addressing and decoding circuitries in actual usage. In addition, extremely sensitive sense amplifiers are also needed for memory reading. Examples of such ROM circuits can be found in Okada, et al., entitled "16Mb ROM Design Using Bank Select Architecture", Symposium on VLSI Circuits, Tokyo, Japan, Aug. 22-23 1988, Digest of Technical Papers, pp 85-86; or in Yiu, United States Patent No. 5,117,389, entitled "Flat-Cell Read-Only Memory Integrated Circuit", May 26, 1992. Disclosure of the Invention In accordance with the present invention, there is provided a ROM cell with small geometry, capable of being addressed swiftly at random, and without any reliance on complicated addressing, decoding and current sensing circuitries. The ROM cell of the present invention achieves these ends with an unique design. Generally the ROM cell of the present invention comprises a source and a drain formed in a semiconductor substrate. The source and the drain defines a channel therebetween. The channel can be doped at a level such that the MOSFET subsequently formed will assume a predetermined threshold voltage. The predetermined threshold voltage level corresponds to a logical bit "1" or "0", for example. Dielectrically formed atop a first portion of the channel is a first control gate. Dielectrically formed atop a second portion of the channel the first control gate and is a second control gate. In the preferred embodiment, first and second control gates comprise polysilicon and are disposed on the semiconductor substrate substantially perpendicular to each other. Cell to cell isolations can be accomplished by diffused isolation regions, field oxide regions, or oxide-filled trenches. In field application, a plurality of ROM cells of the present invention are normally arranged in a matrix of rows and columns on a semiconductor substrate. The first control gates of each of the memory cells in a column are connected together to form Y-control traces. Similarly, the second control gates of each of the memory cells in a row are connected together to form X-control traces. Addressing of each of the ROM cells in the matrix involves no complicated addressing schemes or circuits. To select a particular ROM cell for the read operation, a simultaneous energization of a pair of X-control and Y-control traces criss-crossing the selected ROM cell turn the underlying channel on. Depending on the threshold voltage of the MOSFET in the ROM cell, current flowing through from source to drain, if any, will be fed to a sense amplifier for the determination of the appropriate logic level. It should be noted that all other ROM cells under the energization of only the X-control or the Y-control trace, but not both, are not available for the read operation as the underlying channels are not fully turned on. Brief Description of Drawings Fig. la is a top plan view showing a prior art read-only memory cell, commonly called the "Flat Cell"; Fig. lb is a cross-sectional side view taken along line la- la of Fig. la; Fig. lc is a cross-sectional side view taken along line lc- lc of Fig. la; Fig. 2 is a schematic representation of the read-only memory cell shown in Figs, la-lc; Fig. 3a is a top plan view showing a preferred embodiment of the read-only memory cell of the present invention; Fig. 3b is a cross-sectional side view taken along line 3b- 3b of Fig. 3a; Fig. 3c is a cross-sectional side view taken along line 3c- 3c of Fig. 3a; Fig. 4 is a schematic representation of the read-only memory cell shown in Figs. 3a-3c; Fig. 5a is a top plan view showing a partial memory array of the present invention, comprising memory cells as shown in Figs. 3a-3c arranged in a matrix of rows and columns; Fig. 5b is a cross-sectional side view taken along line 5b- 5b of Fig. 5a; Fig. 5c is a cross-sectional side view taken along line 5c- 5c of Fig. 5a; Fig. 6 is a schematic representation of the memory array shown in Figs. 5a-5c; Figs. 7a-7b are sequential drawings showing the fabrication of the memory cell of Figs. 3a-3c at various stages of the fabrication process; Fig. 8 is cross-sectional view of a read-only memory cell having a channel with a field oxide layer as a ROM code; Fig. 9a is a top plan view of another memory array having an intermediate layer with a predefined pattern for the implementation of the ROM codes; Fig. 9b is a cross-sectional side view taken along line 9b- 9b of Fig. 9a; Fig. 9c is a cross-sectional side view taken along line 9c- 9c of Fig. 9a; Fig. 10a is a top plan view of yet another memory array having each memory cell in the array layouted substantially the same as the adjacent cell; and Fig. 10b is a cross-sectional side view taken along line lOb-lOb of Fig. 10a. Modes for Carrying Out the Invention Reference is now made to Figs. 3a-3c, which show the first embodiment of the present invention generally designated by reference numeral 9. Fig. 3a is the top plan view of ROM cell 9, while Figs. 3b and 3c are cross- sectional side views taken along line 3b-3b and 3c-3c of Fig. 3a, respectively. In this embodiment, formed in a P- type semiconductor substrate 31, for example, are N-type source 32 and drain 33 defining a channel 34 therebetween. Source 6, drain 8 and channel 10 formed in semiconductor substrate 4 constitutes a basic MOSFET 11. Functionally, channel 34 is divided into a first portion 34A and a second portion 34B. Dielectrically overlying first portion 34A of channel 34 is a first control gate 36. There is also a second control gate 39 dielectrically disposed atop first control gate 36 and the second portion 34B of channel 34. Various insulating layers electrically isolate the different gates and the semiconductor substrate 31. In this embodiment, the insulating layers are thermally grown silicon dioxide (Si0 2 ) . For examples, formed between first control gate 36 and first portion 34A of channel 34 is insulating layer 35, while formed between first control gate 36 and second control gate 39 is insulating layer 30. Moreover, formed between second control gate 39 and second portion 34B of channel 34 is insulating layer 38. It should be noted that in this embodiment, first control gate 36 and second control gate 39 are elongated in shape and are dielectrically disposed atop the semiconductor substrate 31 substantially perpendicular to each other. This arrangement is clearly shown in Fig. 3a. There are also doped isolation regions 40 formed in semiconductor for cell-to-cell isolations. In this embodiment, isolation regions 40 are P- type diffusion regions. Alternatively, isolating regions 40 can be formed of insulators such as silicon dioxide. Fig. 4 shows the schematic representation of memory cell 9. For the sake of a clear illustration, MOSFET 11 inside memory cell 9 is subdivided into two transistors 11A and 11B. The same partition is also shown in Fig. 3b with parenthesis, where node 43 is labeled as a hypothetical point between first and second portions 34A and 34B of channel 34. As is clearly illustrated, transistor 11A is controlled by second control gate 39A while transistor 11B is controlled by first control gate 36. Both transistors 11A and 11B can be turned on when first and second control gates 36 and 39 are simultaneously energized. For a consistent illustration, in this description and in the appended claims, the terms "simultaneously" or "simultaneous" are construed as the occurrence of more than one event overlappingly in the time domain. Thus, in this case, when the two control gates are described as simultaneously energized, the timing of energization for each of the control gates may be different. However, there is always an overlap of time when both the control gates are energized. The read operation of memory cell 9 is herein described. To begin with, both first and second control gates 36 and 39 on the selected memory cell 9 need to be energized to 3 Volts. The drain is set at 3 Volts while the source is tied to the ground potential. Suppose, portions of or all of channel 34 is previously implanted with positively charged ions, as a result, the threshold voltage of MOSFET 11 is pre-programmed with a +5 Volts value. The 3 Volts potential applied to each of first and second control gates 36 and 39 is insufficient to surpass the +5 Volts threshold voltage of MOSFET 11 to turn channel 34 on. With channel 34 off, no current can flow from drain 33 to source 32, the digital bit "0" is said to be read, for instance. However, if MOSFET 11 of the selected memory cell 9 is pre-programmed with a +1 Volt threshold voltage, the 3 Volts potential applied to each of first and second control gates 36 and 39 is greater than the +1 Volt threshold voltage of MOSFET 11 and turn channel 34 on. Consequently, current flows from drain 33 to source 32, and the digital bit "1" is said to be read, for example. It here should be emphasized again that only the selected memory cell 9 with both the first and the second control gates 36 and 39 energized can be addressed for the read operation. All other memory cells, with only one control gate energized, but not both, can not be addressed. The reason is because one of the channel portions 34A or 34B is off, irrespective of the pre-programmed threshold voltage levels of the MOSFETs of these memory cells. This feature is especially advantageous when the ROM cells of the present invention are arranged in a matrix of rows and columns. Fig 5a-5c shows such a matrix arrangement. Fig. 5a is a top plan view of partial memory array including a plurality of memory cells labelled as C1-C8. First control gates of each of the memory cells in a column are connected together to form first control trace 37. Similarly, second control gates of each of the memory cells in a row are connected together to from second control trace 41. Figs. 5b and 5c are cross-sectional side views taken along lines 5b-5b and 5c-5c, respectively, of Fig. 5a. Fig. 6 is a schematic representation of the memory array shown in Fig. 5a. Figs. 7a and 7c are sequential drawings showing the making of memory cell 9 at various stages of the fabrication process. To begin with, P-type silicon substrate 31 is selected and oxidized on the top surface with an insulating film 35 to a thickness of approximately 20 nanometers. A layer of polysilicon is then deposited atop the insulating film and further doped to a resistance of 4 Ohms. Conventional masking and etching techniques are employed to define the first control gate 36. Another insulating layer 30 is then grown atop the first control gate 36 and the resultant structure up to this step is shown in Fig. 7a. Conventional masking and implantation methods are adopted for the formation of source 32 and drain 33. For proper isolations between cells, another ion implantation step must be conducted for the definition of P-type isolation regions 40 as shown in Fig. 3c. Thereafter, a second layer of polysilicon of approximately 450 nanometers is deposited atop the semiconductor substrate 31. The deposited polysilicon layer is then doped to a resistance of 4 Ohm. Again the deposited polysilicon is masked and etched via the conventional methods and the second control trace 39 is defined. The resultant structure up to this step is shown in Fig. 7b. It should be noted that the material used for first and second control gates can be other materials instead of polysilicon. Examples are metals such as aluminum, or other refractory suicides such as tungsten suicide or titanium suicide. Finally, other changes are possible within the scope of the invention. For example, implant isolation regions 40 shown in Figs. 3c and 5c can well be replaced by oxide isolation regions. Oxide insulating layer 30 shown in Figs. 3b, 3c, 7a can be substituted by a oxide-nitride-oxide composite layer. First and second control gates 36 and 39 can assume different shapes and sizes. ROM codes can be implemented with the absence or presence of field oxide regions 81 atop channels 34 as shown in Fig. 8, instead of ion implanted channels as described in the preferred embodiment. In addition, ROM codes can also be implemented by sandwiching an intermediate polysilicon layer 80 between first and second control traces 37 and 41 as shown in Fig. 9a-9c. Fig. 9a is the top plan view of such an array, while Figs. 9b and 9c are cross-sectional side views taken along lines 9b-9b and 9c-9c, respectively, of Fig. 9a. Intermediate layers 80 can be tied to the ground potential, for example. Memory cells with intermediate layer 80 overlying portions of the channels can be regarded as storing the "0" digital datum, while memory cells with no intermediate layer 80 overlying the channel can be regarded as storing the "1" digital datum, for example. More specifically, as shown diagrammatically in Fig. 9b, cell D6 can be regarded as storing a digital bit "1" while the other cells can be regarded as storing a digital bit "0". Figs. 10a and 10b show yet another variation of the preferred embodiment of the present invention. Within an array of memory cells, instead of being layouted as a mirror image of the adjacent cell, each cell can be positioned in the memory array substantially the same as the adjacent cell. Common diffusion regions 32/22 can be used as either the source region 32 or the drain region 33, and can be switched for either purposes. Fig. 10a shows the top plan view of such an array and Fig. 10b is the cross-sectional side view taken along line lOb-lOb of Fig. 10a. While the present invention has been shown and de¬ scribed with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that these and other changes in form and detail may be made therein without departing from the scope and spirit of the invention as defined by the appended claims.

Claims: Claims What is claimed is: 1. A read-only memory cell formed in a semiconductor substrate having a source, and a drain spaced from the source, wherein the improvement comprising: a channel of predetermined conductivity disposed between the source and the drain, said channel further includes a first and a second portion; a first control gate dielectrically disposed atop said first portion of said channel; and a second control gate dielectrically disposed atop said second portion of said channel; wherein said predetermined conductivity of said channel constitutes an informational storage of said read- only memory cell, and is capable of being detected by the simultaneous energization of said first and second control gates. 2. The read-only memory cell as set forth in claim 1 wherein said first and second control gates being elongated in shape and are dielectrically disposed atop the semiconductor substrate substantially perpendicular to each other. 3. The read-only memory cell as set forth in claim 1 wherein said channel further comprising implanted ions of a predetermined conductivity type. 4. The read-only memory cell as set forth in claim 1 wherein said channel further comprising a field oxide region. 5. The read-only memory cell as set forth in any of claims 1-4 wherein said first and second control gates comprises polysiliscon. 6. The read-only memory cell as set forth in any of claims 1-4 wherein said first and second control gates comprises metal. 7. The read-only memory cell as set forth in any of claims 1-4 wherein said first and second control gates comprises refractory suicide. 8. A memory cell array formed in a semiconductor substrate including a plurality of read-only memory cells, each of the read-only memory cells comprising: a source formed in the semiconductor substrate; a drain formed in the semiconductor substrate spaced from said source; a channel disposed between said drain and said source; a first control gate dielectrically disposed a first portion of said channel; and a second control gate dielectrically disposed atop a second portion of said channel; wherein said plurality of read-only memory cells being disposed in the semiconductor substrate in a matrix of rows and columns with each of said second control gates in each of said rows of said matrix being electrically connected together, and with each of said first control gates of in each of said columns being electrically connected together, thereby allowing each of said read-only memory cells to be selectively read when a selected pair of first and second control gates are substantially simultaneously energized to a predetermined set of potential values. 9. The memory cell array as set forth in claim 8 further comprising an intermediate layer disposed between said first and second control gates, said intermediate layer includes a predefined pattern which constitutes the read¬ only memory code of said memory cell array. 10. The memory cell array as set forth in claim 8 further comprising isolation regions disposed between each of said read-only memory cells. 11. A method of forming a read-only memory cell in a semiconductor substrate comprising the steps of: providing a semiconductor substrate; forming a channel with a predetermined conductivity by implanting ions in the semiconductor substrate; forming a first control gate dielectrically overlying a first portion of the channel; and forming a second control gate dielectrically overlying said first control gate and a second portion of the channel. 12. The method of forming a read-only memory cell as set forth in claim 11 further comprising the step of forming a source and a drain in the semiconductor substrate before the step of forming said second control gate. 13. The method of forming a read-only memory cell as set forth in claim 11 or claim 12 wherein said second control gate is being formed substantially perpendicular to said first control gate atop the semiconductor substrate.

Inventors: YU SHIH-CHIANG, YU, SHIH-CHIANG
Applicants: YU SHIH CHIANG, YU, SHIH-CHIANG
Application year: 1994
Main classification: G11C17
IPC codes: G11C11, G11C17, H01L21, H01L27