Apparatus for generating a display clock signal

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a display clock signal on the basis of the frequency of the horizontal synchronizing signal. The frequency of the display clock signal is frequency-divided in accordance with a frequency-dividing value selected from among a plurality of frequency-dividing signal stored in advance, the difference in frequency between the frequency-divided display clock signal and the horizontal synchronizing signal and the phase difference between them are obtained by a phase comparator, and the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the reference signal and the horizontal synchronizing signal input to the phase comparator are held fixed to prevent a fluctuation in the outputted display clock.

Description: BACKGROUND OF THE INVENTION This invention relates to a display control apparatus and, more particularly, to a display control apparatus for presenting a display by generating a signal having a divided frequency on the basis of the frequency of a reference signal. A well-known example of a circuit which, on the basis of the frequency of a given reference signal, generates a signal whose frequency is a frequency-divided of the reference frequency is an oscillator circuit referred to as a PLL (phase-locked loop) which compares the reference signal and the output signal in terms of both frequency and phase and performs control in such a manner that the input signal and a frequency signal outputted by a VCO (voltage-controlled oscillator) maintain a phase difference that is proportional to the difference between the free oscillation frequency of the VCO and the frequency of the input signal. In a PLL circuit of this kind, the output signal from the VCO is frequency-divided by a prescribed dividing value (a preset value), after which the frequency and phase of the resulting signal are compared with the frequency and phase of the reference signal. For example, in a display apparatus, a horizontal synchronizing signal is adopted as the reference signal and a PLL circuit of the above-mentioned type is used to multiply the frequency of the reference signal and generate the synchronizing clock of a video signal. Such an apparatus is e.g. known from US-A-5 479 073. However, there are display apparatuses in which the horizontal synchronizing signal serving as the reference signal is outputted at a frequency different from that at the time of the display operation in intervals where a vertical synchronizing signal is off, by way of example. In case of such an apparatus, the fact that the conventional PLL circuit can be preset to only one dividing value means that the PLL circuit will not operate normally during the time that the vertical synchronizing signal is off. The result is an increase in jitter or failure of the PLL circuit to lock the output signal. Document JP-A-03 009 615 discloses a PLL for a display control apparatus in which when the absence of the horizontal synchronizing signal is detected the frequency dividing operation is stopped for a specific period. Document JP-A-62 256 521 discloses a PLL circuit for a display control apparatus in which a voltage is hold in a specific state during a particular period of the vertical synchronizing signal. Document EP-A-0 544 245 discloses a clock recovery circuit in which a second PLL is used to provide pulses during the vertical sync interval. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a display control apparatus in which, even if a reference signal has a plurality of frequencies, is capable of outputting a display clock signal that is stable with respect to changes in frequency by changing the frequency-dividing value in conformity with the frequency of the reference signal. Another object of the present invention is to provide a display control apparatus in which, when a display clock signal is generated using a horizontal synchronizing signal as a reference signal, is capable of preventing disturbance of the display even if the frequency of the horizontal synchronizing signal fluctuates in a blank interval. A further object of the present invention is to provide a display control apparatus in which operation of a PLL circuit used in a display control circuit is assured. These objects are achieved by a display control apparatus as set out in claim 1. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating an information processing system having a display control apparatus according to an embodiment of the present invention; Fig. 2 is a block diagram illustrating the construction of a PLL circuit of a CRT-signal receiver according to a first embodiment of the present invention; Fig. 3 is a block diagram illustrating the construction of a PLL circuit of a CRT-signal receiver according to a second embodiment of the present invention; Fig. 4 is a timing chart showing the operation of the circuit of Fig. 3; Fig. 5 is a block diagram illustrating the construction of a PLL circuit of a CRT-signal receiver according to a modification of the second embodiment of the present invention; Fig. 6 is a block diagram illustrating the construction of a PLL circuit according to a third embodiment of the present invention; Fig. 7 is a timing chart showing the operation of the circuit of Fig. 6; Fig. 8 is a flowchart illustrating processing for setting a register of a controller according to the third embodiment; and Fig. 9 is a block diagram illustrating the construction of a PLL circuit of a CRT-signal receiver according to a modification of the third embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Fig. 1 is a block diagram illustrating an information processing system having a display control apparatus according to an embodiment of the present invention. The system of Fig. 1 includes a display control apparatus 1 according to this embodiment, a computer 2 such as a personal computer or work station serving as an information source for supplying the display control apparatus 1 with information, and a display panel unit 3 for displaying image information under the control of the display control apparatus 1. Though not illustrated, the display control panel 3 includes a drive circuit for driving a display panel, a control circuit for controlling drive under conditions ideal for the display panel, a panel back-light and a power supply. The display control apparatus 1 has a CRT-signal receiver 4 which receives CRT display signals (image signal and synchronizing signals) outputted by the computer 2, converts these signals to signals suited to the components of the next stage and then outputs the signals. Since CRT signals from an ordinary computer are analog video signals, the CRT-signal receiver 4 is internally provided with an A/D converter 40, a PLL circuit 41 which generates a sampling clock for the A/D conversion, and a synchronizing-signal receiver 42. Image information converted to a digital signal by the A/D converter 40 of the CRT-signal receiver 4 is applied to a pseudo-halftone processor 5, which executes pseudo-halftone processing for subjecting the image information to a binary or multivalued conversion. Methods of binary and multivalued pseudo-halftone processing are as follows: <Error-diffusion method> According to this method, weighting is applied to a binary or multivalued error produced when peripheral pixels of a pixel of interest (where the peripheral pixels are pixels which prevail before the pixel of interest is processed) are binarized or converted to multiple values, after which the resulting weighted value is added to the pixel of interest and binarization is performed using a fixed threshold value. <Mean-density preservation method> According to this method, the binarization threshold value is not fixed. Rather, the threshold value is decided by a weighted mean obtained from already binarized data neighboring the pixel of interest, and the threshold value is capable of being varied depending upon the state of the pixels. Pseudo-halftone processing can be executed using at least one of these methods. It is also possible to provide means for executing more than one of these methods and changeover between the means as by allowing the user to make the selection. The image information outputted by the CRT-signal receiver 4 is sent to an image discriminator 6, which is capable of executing simple binarization processing or multivalued-conversion processing. The image discriminator 6 separates portions of the image from the input image information that should not be subjected to binarizing halftone processing. These portions include characters, fine lines, etc. The image discriminator 6 includes a processor for executing simple binarization processing in cases where binarizing halftone processing is not performed. An example of a method of image discrimination carried out by the image discriminator 6 is as follows: <Luminance discriminating method> One method of separating a luminance signal is to separate an image based upon the magnitude of the luminance value of the CRT image signal. In general, characters and fine lines displayed by a computer represent important image information and therefore the luminance thereof is comparatively high. Accordingly, portions of high luminance are identified in the CRT image signal and the luminance signals of these portions are separated. A synthesizer (with a switching-priority function) 7 superimposes the data obtained by the pseudo-halftone processor 5 and simple binarized data obtained by the image discriminator 6. Image information of portions determined to be characters or fine lines by the image discriminator 6 are subjected to simple binarization at a higher priority. Implementation of this priority function can be changed over by the user. When the binary data that has been subjected to binarizing pseudo-halftone processing by the synthesizer 7 is stored in a frame memory 11, a compressor 8 compresses the binary data to reduce the volume of data so that the capacity of the frame memory 11 can be kept small. A decompressor 9 decompresses one frame of binary data stored in the frame memory 11. A partial-write controller 10 detects a portion which has undergone a change in a frame of image data displayed on the display panel unit 3 and outputs the data of the changed portion to the display panel unit 3 at a higher priority. This function makes it possible to give higher priority to the display of portions of image data that have changed. The frame memory 11 stores the image data displayed on the display panel unit 3. A controller 17 controls the operation of each component constructing the display control apparatus 1. The connections to these components is not illustrated. The controller 17 includes a CPU 170, a ROM 171 storing the control program of the CPU 170 as well as various data, and a RAM 172 used as the work area of the CPU 170. A control panel 18, which includes various keyboards and pointing devices, enters control data and commands on the basis of operations performed by the user. The construction of the computer 2 will now be described. The computer 2 includes a CPU 12 which controls the computer, and a system memory 13 which stores the control program of the CPU 12 as well as various data. The system memory 13 is also used as the work area of the CPU 12 and saves a variety of data temporarily. The computer 2 also has a frame memory 14 which stores image data processed by the computer 2, a CRT controller (CRTC) 15 for controlling transmission of the image information stored in the frame memory 14 to the display control apparatus 1, and a CRT interface 16 for converting image information stored in the frame memory 14 to CRT signals. The conversion includes conversion of analog signals, color conversion, etc. Operation of the components shown in Fig. 1 will now be described on the basis the arrangement set forth above. First, the computer 2, which is a source of image information, outputs the image information that has been stored in the frame memory 14 as the CRT signals via the CRT interface 16 under the control of the CRTC 15. The CRT signals are divided up into a video signal (e.g., three analog signals R, G, B in case of a color signal; one analog signal in case of a monochromatic display) and synchronizing signals (signals, inclusive of horizontal and vertical synchronizing signals, for partitioning the video signal line by line or frame by frame). The CRT signals enter the CRT-signal receiver 4 of the display control apparatus 1. The video signal is converted to a digital signal (comprising a plurality of bits) by the A/D converter 40. The sampling clock at the time of the A/D conversion is produced by the PLL circuit 41, which frequency-divides the horizontal synchronizing signal sent from the computer 2. The resulting digital signal enters the pseudo-halftone processor 5, where by the video signal is converted to binary or multivalued data. In order to convert the CRT signal from the computer 2 whenever required in the conversion procedure executed at this time, the conversion is performed in non-interlaced fashion. Distribution of error for pseudo-halftone processing and calculation of the threshold value can be carried out according to theory. As a result, the reproducibility of the image data that has been subjected to halftone processing is improved. The digital signal (image information) from the CRT-signal receiver 4 simultaneously enters the image discriminator 6, where portions of the signal not suited to pseudo-halftone processing, such as the aforesaid characters and fine lines, are identified, and only these portions are subjected to simple binarization or simple multivalued conversion and then outputted. The binary or multivalued signal obtained by the pseudo-halftone processor 5 and image discriminator 6 is switched to in the synthesizer 7 and the result is delivered from the synthesizer 7 to the compressor 8. The changeover in the synthesizer 7 is carried out in such a manner that the simple binary signal or simple multivalued signal obtained by the image discriminator 6 is outputted preferentially. The priority of changeover in the synthesizer 7 may be implemented by the display control apparatus 1 itself on the basis of a command or the like entered by the operator using the control panel 18 or forcibly in response to an instruction from the computer 2. This priority processing is particularly useful in a case where it is desired to display characters or fine lines preferentially or in a case where it is desired to display a natural picture such as a photograph preferentially. The compressor 8 compresses the signal from the synthesizer 7 and outputs the compressed signal to the frame memory 11. Since partial-write control by the partial-write controller 10 is control in line units, a desirable compression method is one which performs compression in line units. The signal thus compressed by the compressor 8 is sent to the partial-write controller 10 at the same time. Here a compressed signal of at least the preceding- frame is read out of the frame memory 11 and the read signal is compared with the signal just sent from the compressor 8. The partial-write controller 10 detects the line of a pixel for which a difference between the preceding image signal and the present image signal has been detected and performs control in such a manner that this line signal and line information (line-image compressed signal) are preferentially outputted to the decompressor 9 from the frame memory 11. The compressed image signal thus sent to the decompressor 9 is demodulated (decompressed) by the decompressor 9 and then outputted to the display panel unit 3. The latter accepts the line-unit image signal from the display control apparatus 1 and displays image information in dependence upon the line image information and line signal. When all of the input video signals are subjected to pseudo-halftone processing for the sake of a binary or multivalued conversion in a case where the painting speed of display panel unit 3 is lower than the input transfer speed of the video signal that enters from the display control apparatus 1, none of the signals converted to binary or multivalued signals can be displayed. Since this means that the pseudo-halftone processor 5 will be executing needless processing, the input video signals are entered upon being thinned out in frame units in dependence upon the painting speed of the display panel unit 3. As a result, the time during which pseudo-halftone processing is performed for the sake of the binary or multivalued conversion may be increased by an amount of time equivalent to the frames thinned out, and therefore the processing speed of pseudo-halftone processing may be lowered. Accordingly, even if it is desired to fabricate the pseudo-halftone processor 5, which is for the binary or multivalued conversion, as an IC, there is no need for the operating speed thereof to be very high. This makes it possible to prevent the generation of heat and the occurrence of erroneous operation caused by circuitry capable of high-speed operation. The construction of the PLL circuit 41 of CRT-signal receiver 4 will now be described with reference to Fig. 2. Fig. 2 is a block diagram illustrating the construction of the PLL circuit 41 contained in the CRT-signal receiver 4 of this embodiment. A horizontal synchronizing signal HD which enters from the computer 2 is fed into a phase comparator 21. A signal fv enters the other input terminal of the phase comparator 21. The phase comparator 21 senses the frequencies of these two input signals (HD, fv) as well as the phase difference between them, generates an average DC voltage proportional to the error (difference) between the signals and delivers the DC voltage to a low-pass filter (LPF) 22. The error signal is applied to the control terminal of a voltage-controlled oscillator (VCO) 23 through the low-pass filter. The frequency of the output signal f OUT of the VCO 23 is varied in a direction which reduces the difference between frequencies of the reference signal (HD) and VCO 23 as well as the phase difference between them. The voltage-controlled oscillator (VCO) 23 generates a signal f OUT (a pixel synchronizing signal or dot clock signal) on the basis of the DC voltage entering from the low-pass filter 22. The signal f OUT produced by the voltage-controlled oscillator 23 is frequency-divided by a frequency divider 24 on the basis of a value in a dividing-value register 25, and the resulting signal is fed back to the phase comparator 21 as the signal fv. By adopting this arrangement, the desired frequency signal f OUT (which has been frequency-divided in conformity with the value in the register 25) can be obtained from the voltage-controlled oscillator 23 on the basis of the reference signal (horizontal synchronizing signal HD). It should be noted that the dividing value in the register 25 is set at the start. The setting method is to write in the value by the CPU 170 of the controller 17 via a signal line 26. The dividing value that has been written in the register 25 is controlled on the basis of the signal fv. When the signal fv becomes logical "0", the dividing value in the register 25 is written in the divider 24 again via a signal line 27. The frequency divider 24 frequency-divides the output signal f OUT (which corresponds to a frequency-division of the horizontal synchronizing signal HD) of the voltage-controlled oscillator 23 by the prescribed dividing value and outputs the signal fv as the result. Thereafter, the phase comparator 21 compares the frequency of the reference signal (horizontal synchronizing signal HD) with the frequency of the phase signal fv, and applies phase locking. As a result, in a case where the value in the dividing-value register 25 is N, the frequency of the output signal f OUT from the voltage-controlled oscillator 23 is locked at a frequency which is N times the frequency of the reference signal (horizontal synchronizing signal HD). [Second Embodiment] Fig. 3 is a block diagram illustrating the construction of the PLL circuit 41 according to a second embodiment of the present invention. In a case where the horizontal synchronizing signal HD is outputted during the time that a vertical synchronizing signal VD is at a low level (i.e., in blank intervals) and, moreover, the period of the horizontal synchronizing signal is short, the frequency-dividing ratio is changed over in dependence upon the level of the vertical synchronizing signal VD to deal with a change in the frequency of the horizontal synchronizing signal HD in order to prevent a phase shift in the phase comparator 21. In Fig. 3, the controller 17 sets frequency-dividing values T1, T2 in frequency-dividing value registers 31, 32 via signal lines 33, 34, respectively, when power is introduced from the power supply. Output signal lines 35, 36 of these registers 31, 32 are connected to a selector 26. The selector 26 selects the signal on the signal line 35 or 36 in dependence upon a control signal (vertical synchronizing signal VD) and delivers the signal to the frequency divider 24 via the signal line 37. For example, when the control signal (vertical synchronizing signal VD) is logical "1", the frequency-dividing value T1 in the register 31 is delivered to the signal line 37 via the signal line 35 and selector 26, whereby the T1 is set in the frequency divider 24. When the control signal (vertical synchronizing signal VD) is logical "0" (the blank interval), the frequency-value T2 (T2>T1) in register 32 is selected and set in the frequency divider 24 via the signal line 37. The operation of the PLL circuit 41 shown in Fig. 3 is basically the same as that of the circuit shown in Fig. 2 described above. With the PLL circuit of Fig. 3, however, the two frequency-dividing values (T1, T2) are stored in advance and the two values are switched between in dependence upon the level of the control signal (vertical synchronizing signal VD). At the same time, a hold switch 20 is turned off (opened) only in an interval in which the vertical synchronizing signal VD is at logical "0" (the blank interval), as a result of which output of the signal to the phase comparator 21 is interrupted. The hold switch 20, whose inputs are the reference signal HD and the signal fv from the frequency divider 24, outputs these signals to the phase comparator 21 in dependence upon the control signal (VD). When the control signal is in an interval of logical "0", the hold switch 20 holds the status of the output which prevailed immediately before this interval. As a result, in the blank interval, the level of the signal sent from the phase comparator 21 to the voltage-controlled oscillator 23 via the low-pass filter 22 is held in the state which prevailed just before the opening of the hold switch 20. (This is the holding state.) In other words, even in the holding state, the clock signal four supplied to the system does not fluctuate since the input to the control terminal of the voltage-controlled oscillator 3 is constant. The clock signal f OUT may thus be supplied stably. Fig. 4 is a timing chart illustrating the operation timing of the circuit shown in Fig. 3. The timing chart shows the timing for switching between the frequency-dividing values T1, T2. The PLL circuit 41 operates at a period t1 when the signal level of the control signal (vertical synchronizing signal VD) is logical "1" (which corresponds to interval 1 ○ in Fig. 4), and at a period t2 when the signal level of the control signal (vertical synchronizing signal VD) is logical "0" (which corresponds to interval 2 ○ in Fig. 4). The timing at which the frequency-dividing value T1 or T2 is loaded in the frequency divider 24 from the frequency-dividing register 31 or 32 is that at which the signal level of the signal fv is logical "0". Here the horizontal synchronizing signal HD is outputted at the period t1 when the vertical synchronizing signal VD is at the high level (logical "1") and at a period t10 (t10<t1) when the vertical synchronizing signal VD is at the low level (logical "0"). If the signal level of the control signal (vertical synchronizing signal VD) is logical "1", then the hold switch 20 outputs the signal HD and the signal fv to the phase comparator 21 as is. At the same time, the frequency divider 24 outputs the signal fv, whose frequency is a multiple of that of the signal f OUT in accordance with the frequency-dividing value T1, since the value T1 in the frequency-dividing value register 31 has been selected by the selector 26. When the signal fv becomes logical "1" in this interval, the frequency-dividing value T1 (period t1) selected by the selector 26 is loaded in the frequency divider 24 again. By contrast, if the signal level of the control signal (vertical synchronizing signal VD) is logical "0", then the hold switch 20 is turned off so that the output signals to the phase comparator 21 are cut off. As a result, the output of the low-pass filter 22 assumes the holding state. Thus, the signal level which prevailed prior to turn-off of the hold switch 20 is kept applied to the voltage-controlled oscillator 23. The frequency of the signal f OUT does not change and the signal f OUT of stabilized frequency continues to be outputted. At this time the selector 26 selects the frequency-dividing value T2 (period t2) of the register 32 and delivers the value T2 to the frequency divider 24. Thus, the frequency-dividing values T1, T2 are set in conformity with the signal level of the control signal (vertical synchronizing signal VD) and the PLL circuit 41 operates in dependence upon this frequency-dividing value. The reason for changing over the frequency-dividing value of the frequency divider 24 from T1 to T2 when the vertical synchronizing signal VD is in the off interval (interval 2 ○) is to change the frequency of the signal fv in conformity with the frequency t10 of the horizontal synchronizing signal HD in the interval 2 ○, thereby changing the value held in the hold switch 20 in interval 2 ○ as opposed to interval 1 ○. As a result, the phase difference of the signals applied to the phase comparator 21 is reduced and fluctuation of the output from the phase comparator 21 can be suppressed even when the interval returns to the interval 1 ○. This means that the frequency of the clock signal f OUT will not be disturbed. [Modification of Second Embodiment] Fig. 5 is a block diagram illustrating the construction of the PLL circuit according to a modification of the second embodiment of the present invention. Though the construction and operation of this circuit are similar to those of the circuit shown in Fig. 3, this arrangement differs in that the hold switch 20 is provided between the low-pass filter 22 and the voltage-controlled oscillator 23. More specifically, in the holding state (interval 2 ○ in Fig. 4), the signal input to the voltage-controlled oscillator 23 is maintained at the voltage level which prevailed just before attainment of the holding state, even if there is a disturbance in the phases of the reference input signal (horizontal synchronizing signal HD) and the signal fv applied to the phase comparator 21. As a result, the output signal f OUT of the voltage-controlled oscillator 23 is stable and it is possible to supply a stabilized clock to the system even in the blank intervals. [Third Embodiment] Fig. 6 is a block diagram illustrating the construction of the PLL circuit in the display control apparatus according to a third embodiment of the present invention, and Fig. 7 is a timing chart showing the operation of the PLL circuit. It should be noted that components identical with those of the foregoing drawings are designated by like reference characters and need not be described again. The horizontal synchronizing signal HD is a reference input signal and the signal fv is a signal obtained by frequency-dividing the output f OUT of the voltage-controlled oscillator 23 by means of the frequency divider 24. The signal fv basically is a signal having a frequency the same as that of the reference input signal (horizontal synchronizing signal HD). The hold switch 20, whose inputs are the reference input signal HD and the signal fv, controls whether or not these signals are outputted to the phase comparator 21. The signal HD and the signal fv are allowed to pass to the phase comparator 21 as is when the control signal (vertical synchronizing signal VD) is logical "1" and are cut off when the control signal VD is logical "0". This is the same as in the foregoing embodiments. The frequency-dividing value (T1) in a register (REG1) 50 is loaded in the frequency divider 24 via signal line 52 when the signal level of the control signal (vertical synchronizing signal VD) is in the logical "1" interval. The loading timing is the interval in which the signal fv is logical "0". When the control signal (vertical synchronizing signal VD) is logical "0", the second frequency-dividing value T2 stored in a register (REG2) 51 is loaded in the register 50 via signal line 53 in response to a latch signal (LAT) 44 outputted by the controller 17. Thereafter, the frequency-dividing value (T2) is loaded in the frequency divider 24 via the signal line 52 and, at the same time, the frequency-dividing value T1 is written in the register 51 from the controller 17 via a data line (DATA) 45. The frequency-dividing value T1 is shifted to the register 50 by the latch signal (LAT) 44 from the controller 17 when the control signal (vertical synchronizing signal VD) changes from logical "0" to logical "1". Thus, the next frequency-dividing value is always set in the register 51 in advance and control is performed to change over the frequency-dividing value in dependence upon the signal level of the control signal (vertical synchronizing signal VD), thereby making it possible to operate the PLL circuit stably. In the timing chart of Fig. 7 showing the operation of the circuit of Fig. 6, it is assumed that the phase of the input reference signal (horizontal synchronizing signal HD) and the phase of the signal fv whose phase is compared with that of the reference signal are in agreement (the locked state). When the signal fv is logical "0" in an interval in which the level of the control signal (vertical synchronizing signal VD) is logical "1", the frequency-dividing value T1 is set in the frequency divider 24 from the register 50. Further, the frequency-dividing value T2 to be set in the interval in which the control signal (vertical synchronizing signal VD) is logical "0" is set in the register 51 in advance. The controller 17 monitors the signal level of the control signal (vertical synchronizing signal VD) at all times. When the level of the VD signal changes from logical "1" to logical "0", the controller 17 outputs the latch signal 44. As a result, the frequency-dividing value T2 in register 51 is loaded in the register 50 via the signal line 53. At the same time, the controller 17 sets the frequency-dividing value T1 in the register 51 through the data line 45. The frequency-dividing value T1 is a frequency-dividing value (T1) for operating the PLL circuit 41 in the interval in which the signal level of the control signal (vertical synchronizing signal VD) is logical "1", just as in the embodiments described above. Thus, the PLL circuit 41 is operated at period t2 in the interval in which the signal level of the control signal (vertical synchronizing signal VD) is logical "0" and at the period t1 when the signal level of the control signal (vertical synchronizing signal VD) is logical "1". Further, in the interval in which the control signal (vertical synchronizing signal VD) is logical "0", transmission of the input reference signal HD and signal fv to the phase comparator 21 is halted by the hold switch 20, whereby the outputs of the phase comparator 21 and low-pass filter 22 are held in a fixed state (the DC state). Thus, stabilized operation can be achieved. Fig. 8 is a flowchart showing the operation for setting data in the registers 50 and 51 by the controller 17 of the display control apparatus 1 of this embodiment. The control program for executing this processing is stored in the ROM 171. It should be noted that the frequency-dividing values T1 are T2 are assumed to have been set in the registers 50 and 51, respectively, before the start of this processing. First, at step S1, it is determined whether the vertical synchronizing signal (VD) has changed from logical "1" (the high level) to logical "0" (the low level). If the decision rendered is "YES", then the program proceeds to step S2, at which the latch signal (LAT) 44 is outputted and the frequency-dividing value (T2) stored in the register (REG2) 51 is set in the register (REG1) 50. As a result, the frequency-dividing value of the frequency divider 24 changes to T2 at the negative-going transition of the next signal fv. The program then proceeds to step S3, at which the frequency-dividing value (T2) prevailing when the display is blank is set in the register 51. Next, at step S4, it is determined whether the vertical synchronizing signal (VD) has changed from the low level to the high level. If the decision rendered is "YES", then the program proceeds to step S5, at which the latch signal 44 is outputted and the frequency-dividing value (T1) stored in the register 51 is set in the register (REG1) 50. The program then proceeds to step S6, at which the frequency-dividing value (T2) prevailing when the display is blank is set in the register 51. Fig. 9 illustrates a modification of the third embodiment. This arrangement differs from that of Fig. 6 in that the hold switch 20 is provided between the low-pass filter 22 and the voltage-controlled oscillator 23. The basic operation of this circuit is similar to that described in connection with Figs. 6 and 7 of the third embodiment. Here, however, the hold switch 20 allows the signal from the low-pass filter 22 to pass to the voltage-controlled oscillator 23 when the control signal (vertical synchronizing signal VD) is in the interval of logical "1" and blocks the signal from the low-pass filter 22 when the control signal (vertical synchronizing signal VD) is logical "0". In this case, the input signal level of the voltage-controlled oscillator 23 is held at a constant voltage level by the hold switch 20. As a result, the dot clock signal f OUT supplied to the system does not fluctuate and is outputted as a stable signal at all times. Other operations of this circuit are basically the same as those described above. In accordance with this embodiment as described above, when a PLL circuit is operated, frequency-dividing values corresponding to respective frequencies are set so that it is possible to deal with a situation in which signals having different frequencies enter as the reference signal. As a result, an increase in jitter or an unlocked state, which are problems encountered in PLL circuits, can be prevented. This makes it possible to operate the system in a stable state. The present invention can be applied to a system constituted by a plurality of devices or to an apparatus comprising a single device. Furthermore, it goes without saying that the invention is applicable also to a case where the object of the invention is attained by supplying a program to a system or apparatus. Thus, in accordance with the present invention as described above, a stabilized display clock can be outputted, even if a reference signal has a plurality of frequencies, by changing the frequency-multiplying value in conformity with the frequency. As many apparently widely different embodiments of the present invention can be made without departing from the scope of the invention as defined in the claims.

Claims: A display control apparatus for generating a display clock signal ( fout ), which corresponds to a video signal, from a reference signal ( HD ), comprising: frequency dividing means ( 24 ) for dividing the frequency ( fout ) of the display clock signal in dependence upon a frequency-dividing value ( T1, T2 ); comparator means ( 21 ) for comparing a frequency-divided signal ( fv ) produced by said frequency dividing means ( 24 ) with the reference signal ( HD ); clock generating means ( 23 ) for generating the display clock signal on the basis of the results of the comparison performed by said comparator means ( 21 ); and holding means ( 22) for holding an input to said clock generating means at a value in a predetermined range in dependence upon a display synchronizing signal; characterized by memory means ( 25; 31, 32; 50, 51 ) for storing a plurality of frequency-dividing values ( T1, T2 ); and setting means ( 17; 26 ) for selecting any one of the plurality of frequency-dividing values ( T1, T2 ), which have been stored in said memory means ( 25; 31, 32; 50, 51 ), in dependence upon the display synchronizing signal ( VD ) and setting the selected value in said frequency-dividing means ( 24 ). The apparatus according to claim 1, characterized by interrupting means ( 20 ) for interrupting an output from said comparator means ( 21 ), said interrupting means ( 20 ) being controlled so as to interrupt the output from said comparator means ( 21 ) in a period in which the display synchronizing signal ( VD ) is zero. The apparatus according to claim 2, characterized in that said interrupting means ( 20 ) interrupts the output from said comparator means when the display synchronizing signal ( VD ) is off. The apparatus according to claim 1, characterized in that said setting means ( 17; 26 ) selects a first frequency-dividing value ( T1 ) when the display synchronizing signal ( VD ) is on and a second frequency-dividing value ( T2 ) when the display synchronizing signal ( VD ) is off. The apparatus according to claim 1, characterized by switch means ( 20 ), to which a frequency-divided signal ( fv ) produced by said frequency-dividing means and the reference signal ( HD ) are applied as inputs, for outputting these input signals in dependence upon the display synchronizing signal. The apparatus according to claim 5, characterized in that, when the display synchronizing signal ( VD ) is off, said switch means ( 20 ) holds and outputs a state which prevailed when the display synchronizing signal ( VD ) was changed over from on to off, and when the display synchronizing signal ( VD ) is on, said switch means outputs its input signals as they are presented on the input of the switch means ( 20 ). The apparatus according to claim 6, characterized by converting means for converting results of the comparison from said comparator ( 21 ) means into a voltage signal and smoothing said voltage signal. The apparatus according to claim 1, characterized in that the comparator means ( 21 ) is arranged to output results of the comparison in the form of a voltage signal; and a switch means ( 20 ) is provided, to which the voltage signal is applied as an input, for outputting the voltage signal in dependence upon the display synchronizing signal ( VD ); and the clock generating means ( 23 ) generates the display clock signal ( fout ) having a frequency conforming to the voltage signal. The apparatus according to claim 8, characterized by smoothing means for smoothing the voltage signal output by said comparator means ( 21 ). The apparatus according to claim 8, characterized in that, when the display synchronizing signal ( VD ) is off, said switch means ( 20 ) holds and outputs the voltage signal which prevailed when the display synchronizing signal ( VD ) was changed over from on to off, and when the display synchronizing signal ( VD ) is on, said switch means ( 20 ) outputs its input signal as it is presented on the input of the switch means ( 20 ). The apparatus according to any one of the previous claims, characterized in that the reference signal ( HD ) is a horizontal synchronizing signal. The apparatus according to any one of the previous claims, characterized in that the display synchronizing signal ( VD ) is a vertical synchronizing signal.

Inventors: KANNO HIDEO, MATSUMOTO YUICHI, MIYAMOTO KATSUHIRO, TSUNODA TAKASHI, YUI HIDEAKI, KANNO, HIDEO, MATSUMOTO, YUICHI, MIYAMOTO, KATSUHIRO, TSUNODA, TAKASHI, YUI, HIDEAKI, KANNO, HIDEO, C/O CANON K.K., MATSUMOTO, YUICHI, C/O CANON K.K., MIYAMOTO, KATSUHIRO, C/O CANON K.K., TSUNODA, TAKASHI, C/O CANON K.K., YUI, HIDEAKI, C/O CANON K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1994
Main classification: G09G5
IPC codes: G06F1, H03L7, G09G5, H04N5, G09G3