Voltage-driven thyristor and method of manufacturing the same

Abstract: An n-buffer layer (2) and an n - -base layer (3) are formed on a p + -anode layer (1). A p-base layer (4) is formed on the n - -base layer (3). The p-base layer (4) has a p-type impurity layer (4a) protruding into n - -base layer (3). An n-cathode layer (5), an n + -cathode layer (6) and a P+-impurity layer (7) are formed on p-base layer (4). First trenches (16a) are formed through p + -impurity later (7), n-cathode layer (5) and p-base layer (4). On-gates (9a) are formed in the first trenches (16a). Second trenches (16b) are formed through p + -impurity layer (7) and n-cathode layer (5) with their bottom surfaces located in p-type impurity layer (4a). Off-gates (9b) are formed in the second trenches (16b). First and second trenches are preferably formed alternately. Thereby, a voltage-driven thyristor has improved turn-on and turn-off characteristics and a high reliability

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a voltage-driven thyristor, and in particular to a voltage-driven thyristor having superior turn-on and turn-off characteristics as well as high reliability. Description of the Related Art as is known, voltage-driven thyristors are a kind of switch elements. An example of the voltage driven thyristor is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED33, No. 10, October 1986 . Fig. 24 shows a section of the voltage-driven thyristor disclosed in the above reference. Referring to Fig. 24, an n-buffer layer 102 is formed on a p + -anode layer 101. An anode electrode 112 is formed on the bottom surface of the p + -anode layer 101. An n - -base layer 103 is formed on the n-buffer layer 102. P-base layers 104 are formed selectively on the surface of n - -base layer 103. An n + -cathode layer 106 and n-cathode layers 105 are formed on each p-base layer 104. n-cathode layers 105 are located at opposite sides of the n + -cathode layer 106. On n-cathode layers 105 are formed p + -impurity layers 107 which are also located at opposite sides of n + -cathode layer 106. Surface layers of the p-base layer 104 form first channel forming regions 113 of a n-channel MOS transistor, which will be described later. A surface layer of the n-cathode layer 105 adjacent to the first channel forming region 113 forms a second channel forming region 114 of an p-channel MOS transistor, which will be described later. A gate electrode 109 is formed on the first and second channel forming regions 113 and 114 with a gate oxide film 108 therebetween. Thus, the gate electrode 109, p-base layer 104 and p + -impurity layer 107 form a p-channel MOS transistor, of which channel forming region is the second channel forming region 114. The gate electrode 109, n - -base layer 103 and n-cathode layer 105 form the n-channel MOS transistor, of which channel forming region is the first channel forming region 113. The gate electrode 109 is covered with a cap oxide film 110. Cap oxide film 110 is covered with a cathode electrode 111 which are in contact with n + -cathode layer 106 and p + -impurity layers 107. Then, an operation of the conventional voltage-driven thyristor having the above structure will be described below with reference to Fig. 25, which shows an operation principle of the voltage-driven thyristor shown in Fig. 24. Referring to Fig. 25, a pnp transistor Tr1 is formed of p + -anode layer 101, n - -base layer 103, n-buffer layer 102 and p-base layer 104. An npn transistor Tr2 is formed of n - -base layer 103, p-base layer 104 and n + -cathode layer 106. A thyristor is formed of the p + -anode layer 101, n-buffer layer 102, n - -base layer 103, p-base layer 104 and n + -cathode layer 106. A p-channel MOS transistor M2 is formed of gate electrode 109, p + -impurity layer 107 and p-base layer 104. An n-channel MOS transistor M1 is formed of n-cathode layer 105, gate electrode 109 and n - -base layer 103. When the voltage-driven thyristor having the above structure is in the on-state, a main current flows from anode electrode 112 to cathode electrode 111. When it is in the off-state, the main current does not flow from anode electrode 112 to cathode electrode 111. The on-state and off-state of the voltage-driven thyristor will be described below. First, the on-state will be described below. The on-state is attained when a positive voltage is applied to anode electrode 112 against cathode electrode 111 and a positive voltage is applied to the gate electrode 109. By applying the positive voltage, which is not lower than a threshold voltage of the transistor M1, to gate electrode 109, n-channel MOS transistor M1 is turned on. Thereby, electrons flow into n - -base layer 103 through the channel of transistor M1, and thus pnp transistor Tr1 is turned on. Thereby, holes flow into p-base layer 104 from the p + -anode layer 101, so that npn transistor Tr2 is also turned on. Consequently, the thyristor formed of transistors Tr1 and Tr2 is turned on. Thus, the main current flows between anode electrode 112 and cathode electrode 111. Then, the off-state will be described below. The off-state of the thyristor is attained by applying a negative voltage to gate electrode 109. MOS transistor M1 is turned off and p-channel MOS transistor M2 is turned on by applying a negative voltage (not higher than the threshold voltage of p-channel MOS transistor M2) to gate electrode 109. Thereby, holes are drawn from p-base layer 104. Consequently, a depletion layer spreads at the junction portion between p-base layer 104 and n - -base layer 103, so that holes do not flow from the p + -anode layer 101 into p-base layer 104, whereby the off-state of the thyristor is attained. However, the conventional voltage-driven thyristor shown in Figs. 24 and 25 suffer from the following problem, which will be described below using Fig. 26. Fig. 26 is a schematic diagram showing the problem of the conventional voltage-driven thyristor. Referring to Fig. 26, an inverted layer is formed at the second channel forming region 114 when the thyristor is in the off-state. This inverted layer is formed only at the position directly under gate electrode 109. Therefore, all the holes to be drawn from p-base layer 104 must move up to the second channel forming region 114. Thus, even the holes existing at the portion remote from the second channel forming region 114 flows through the second channel forming region 114 into p + -impurity layer 107. Therefore, the holes, which existed at the position remote from the second channel forming region 114, move a long distance before reaching the channel forming region 114. This increases a resistance against the holes being drawn, resulting in such a problem that a long time is required for setting the thyristor to the off-state. Also, the increased resistance against the holes being drawn disadvantageously reduces a magnitude of the main current which can be interrupted. As an improvement for overcoming the problem that a long time is required for setting the thyristor to the off-state, there is a voltage-driven thyristor disclosed in Japanese Patent Laying-Open No. 60-253275. Fig. 27 is a cross section showing the voltage-driven thyristor disclosed in Japanese Patent Laying-Open No. 60-253275. Referring to Fig. 27, the voltage-driven thyristor is provided with deep first V-grooves 115a (only one is shown in the figure) for turning on the thyristor and shallow second V-grooves 115b for turning off the thyristor. A first gate electrode 109a is formed on the inner surface of each first V-groove 115a with the gate oxide film 108 therebetween. A second gate electrode 109b is formed on the inner surface of each second V-groove 115b with the gate oxide film 108 therebetween. The voltage-driven thyristor disclosed in Japanese Patent Laying-Open No. 60-253275 has such features that there are provided two kinds of grooves, i.e., deep first V-grooves 115a and shallow second V-grooves 115b, and that the deep first V-grooves 115a are small in number than the shallow second V-grooves 115b. An operation of the improved voltage-driven thyristor will be described below with reference to Figs. 27 and 28. Fig. 28 is a schematic diagram for showing an advantage of the improved voltage-driven thyristor. Referring to Fig. 27, the thyristor is turned on by applying a positive potential to the first gate electrode 109a. Thereby, electrons flow through the first channel forming regions 113 into n - -base layer 103. Thereby, the thyristor is turned on in a manner similar to the voltage-driven thyristor already described with reference to Figs. 24 and 25. The thyristor is turned off by applying a negative voltage to the first and second gate electrodes 109a and 109b. When the negative voltage is applied to the first and second gate electrodes 109a and 109b, inverted layers are formed at the second channel forming regions 114. Thereby, the thyristor is turned off in a manner similar to the conventional voltage-driven thyristor already described with reference to Figs. 24 and 25. In the improvement shown in Fig. 27, the second channel forming regions 114 are formed in a longitudinal direction and located near p-base layer 104. This reduces a resistance against holes being drawn from p-base layer 104. This results in an advantage that a time for setting the thyristor to the off-state is short. Also, a magnitude of the interruptible main current can be increased owing to the small resistance against holes being drawn from p-base layer 104. However, the above improvement suffers from the following two problems, which will be described below with reference to Figs. 29 and 30. A first problem will now be described below with reference to Fig. 29, which is a schematic cross section for showing the first problem of the above improvement. In the operation for setting the improved thyristor shown in Fig. 29 to the on-state, an inverted layer is formed in the first channel forming region 113 at each side wall of the first V-groove 115a, and electrons flow from n-cathode layer 105 into n - -base layer 103. These electrons flow into p + -anode layer 101. Holes are fed into the n - -base layer 103 through the same path as the electrons flowing into p + -anode layer 101. This improvement is designed to include a relatively small number of first V-grooves 115a. Therefore, fewer holes are supplied from p + -anode layer 101 into the portion of n - -base layer 103 remote from the first V-groove 115a. This results in a problem that a long time is required for setting the thyristor to the on-state. Then, the second problem of the improvement will be described below with reference to Fig. 30, which is an enlarged cross section of the first V-groove 115a for showing the second problem. Referring to Fig. 30, the first V-groove 115a has a bottom reaching n-base layer 103. Thus, a bottom end region 116 of the first V-groove 115a is located in n - -base layer 103. Therefore, an electric field is likely to concentrate at the vicinity of end region 116a. This likely results in breakage of the pn junction near end region 116 and thus flow of a leak current near end region 116. As a result, the thyristor may shift to the off-state due to the leak current even if the thyristor is to be held in the off-state. Thus, the reliability may decrease. EP 0 159 663 A2 discloses a thyristor comprising first to fifth semiconductor layers stacked above each other. Trenches are formed on the side of the fifth layer, a plurality of first trenches reaching the second layer and a plurality of second trenches ending in the third layer. First and second gate electrodes are formed in the first and second trenches, respectively. A cathode electrode is formed on the side of the fifth layer, and an anode electrode is formed on the side of the first layer. EP 0 480 356 A2 discloses a thyristor comprising stacked semiconductor layers. The trenches in which the gate electrodes are formed all have the same depth and end in the same layer. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to overcome the above problems, and particularly to provide a voltage-driven thyristor and a method of manufacturing the same, which can improve both the turn-on and turn-off characteristics of the thyristor. Another object of the invention is to provide a voltage-driven thyristor having high breakdown voltage as well as a method of manufacturing the same. The object is attained by a voltage-driven thyristor according to claim 1. Further developments of the invention are specified in the dependent claims, respectively. In the voltage-driven thyristor, the first and second trenches are disposed alternately. Therefore, the first trenches can be substantially equal in number to the second trenches. The improvement in the prior art described before has the problem relating to setting of the voltage-driven thyristor to the on-state due to the fact that V-grooves 115a for turning on the voltage-driven thyristor are small in number. Meanwhile, according to the invention, a rate of the first trenches, which contribute to the setting of the voltage-driven thyristor to the on-state, is increased, so that carriers can be efficiently supplied into the second semiconductor layer. Therefore, a time required for setting the voltage-driven thyristor to the on-state can be reduced. Also, the first gate electrodes can be disposed regularly at a high density. Accordingly, carriers can be supplied efficiently and uniformly into the second semiconductor layer from the first semiconductor layer. This also contributes to reductions of the time required for setting the voltage-driven thyristor to the on-state. In the voltage-driven thyristor of according to claim 3, a density of a region in the fourth semiconductor layer adjoining to the side wall of the first trench is high. Thus, the density of impurities is high at the region through which a main current flows during the on-state of the voltage-driven thyristor. Thereby, it is possible to reduce a resistance of a path of the main current, and thus a large current can be easily obtained during the on-state. In to the voltage-driven thyristor according to claim 4, the fifth semiconductor layer has the local portion reaching the side wall of the first trench. Thus, it is possible to increase a channel width of a transistor which operates as a major component when the voltage-driven thyristor is turned off. Thereby, the voltage-driven thyristor can smoothly shift to the off-state. In the voltage-driven thyristor according to claim 5, the fourth semiconductor layer has the local portion reaching the side wall of the second trench. Thereby, in contrast to the sixth aspect, the voltage-driven thyristor can smoothly shift to the on-state. Also, a contact area between the fourth semiconductor layer and the cathode electrode can be increased. Therefore, it is possible to increase a current flowing through the voltage-driven thyristor. In the voltage-driven thyristor according to claim 6, the density of the second region of the third semiconductor layer adjoining to the side wall of the second trench is higher than that of the first region of the third semiconductor layer adjoining to the side wall of the first trench. A channel of an MOS transistor, which operates as a major component for setting the voltage-driven thyristor to the off-state, is formed on this second region. Therefore, carriers can be efficiently supplied to the above channel when the voltage-driven thyristor shifts to the off-state. Therefore, the voltage-driven thyristor can quickly shift to the off-state. In the voltage-driven thyristor, the second junction portion is formed at a deep position. Therefore, a depletion layer can spread to cover a bottom of the first trench protruding into the second semiconductor layer when the voltage-driven thyristor is in the off-state. Therefore, a bottom edge of the first trench is located in the depletion layer. Meanwhile, in the depletion layer a uniform electric field is applied. Owing to the fact that the bottom edge of the first trench is located in the depletion layer, it is possible to prevent effectively the concentration of the electric field at the edge of the first trench. Thus, the reliability of the voltage-driven thyristor can be improved. In the voltage-driven thyristor, the concentration of impurities of the first conductivity type contained in the second region preferably is higher than that of impurities of the first conductivity type contained in the first region. The second region is located under the second trench. When the voltage-driven thyristor is turned off, an inverted layer is formed in the fourth semiconductor layer adjoining to a side wall of the second trench. Thus, a region in which the inverted layer is formed is located above the second region. When the inverted layer is formed in the fourth semiconductor layer located near the side wall of the second trench, carriers can be efficiently supplied to the inverted layer, because the concentration of impurities of the first conductivity type contained in the second region is high. Therefore, the voltage-driven thyristor can have improved turn-off characteristics such as a time required for turn-on. Preferably, a pair of the second regions are formed at opposite sides of the first region. The first trench is formed through the first region, and a pair of the second trenches have bottom surfaces located in a pair of the second regions. Since the second regions are formed at opposite sides of the first region, a depletion layer can easily cover a bottom edge of the first trench. Therefore, the voltage-driven thyristor can have improved reliability. Preferably, a plurality of first trenches are formed between a pair of second regions. A plurality of the first trenches are formed between the second regions, in which case bottom edges of first trenches can be covered with a depletion layer by appropriately adjusting a depth at which the second regions are formed. Therefore, similarly to the above case, the voltage-driven thyristor can have improved reliability. Preferably, a voltage-driven thyristor includes an anode layer of a first conductivity type, a first base layer of a second conductivity type, a second base layer of the first conductivity type, a cathode layer of the second conductivity type, an impurity layer of the first conductivity type, a plurality of first and second trenches, a plurality of on-gates, a plurality of off-gates, a cathode electrode and an anode electrode. The first base layer is formed on the anode layer. The second base layer is formed on the first base layer. The cathode layer is formed on the second base layer. The impurity layer is selectively formed in a surface of the cathode layer. The first trenches are formed through the cathode layer and the second base layer and reaches the first base layer. The second trenches are disposed alternately to the first trenches, and are formed through the impurity layer and the cathode layer with their bottom surfaces located in the second base layer. The on-gates are formed in the first trenches. The off-gates are formed in the second trenches. The cathode electrode is formed on the cathode layer and a surface of the impurity layer. The anode electrode is formed on a lower surface of the anode layer. The on-gates and the off-gates are disposed alternately. Therefore, a rate of the on-gates can be larger than that in the prior art improvement already described. This enables more uniform and efficient supply of carriers from the collector layer into the first base layer. This enables reduction of a time required for setting the voltage-driven thyristor to the on-state. The object is also attained by a method for manufacturing the voltage-driven thyristor according to claim 10. According to the method of manufacturing the voltage-driven thyristor, the impurity layer (a first region) and the third layer (a second region) are formed at different steps. Thereby, a concentration of impurities can be high regardless of a concentration of the third semiconductor layer. Therefore, a high impurity concentration region can be formed under the first trench. This can enhance an efficiency with which carries are supplied to a channel of an MOS transistor operating as a major component for setting the voltage-driven thyristor to the off-state. Thereby, it is possible to reduce a time required for setting the voltage-driven thyristor to the off-state. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing a voltage-driven thyristor of a first embodiment which is an embodiment according to the present invention; Fig. 2 schematically shows an operation principle of the voltage-driven thyristor of the first embodiment; Fig. 3 schematically shows a first feature of the voltage-driven thyristor of the first embodiment; Fig. 4 schematically shows a second feature of the voltage-driven thyristor of the first embodiment; Fig. 5 is an enlarged cross section of and around a second trench in the voltage-driven thyristor of the first embodiment; Figs. 6 - 10 are perspective views showing 1st to 5th steps in a process of manufacturing the voltage-driven thyristor of the first embodiment, respectively; Figs. 11A and 11B are perspective views showing modifications of the 5th steps shown in Fig. 10 Figs. 12 - 17 are perspective views showing 6th to 11th steps in a process of manufacturing the voltage-driven thyristor of the first embodiment, respectively; Fig. 18 is a perspective view showing a voltage-driven thyristor of a second embodiment which is a comparative embodiment; Fig. 19 schematically shows a feature of the voltage-driven thyristor of the second embodiment; Figs. 20 - 23 are perspective views showing first to fourth modifications of a pattern layout of p + -impurity layers and n + -cathode layers, respectively; Fig. 24 is a cross section showing an example of a conventional voltage-driven thyristor; Fig. 25 shows an operation principle of the conventional voltage-driven thyristor shown in Fig. 24; Fig. 26 is a schematic diagram for showing problems of the conventional voltage-driven thyristor shown in Fig. 24; Fig. 27 is a cross section showing an example of an improved voltage-driven thyristor in the prior art; Fig. 28 shows a distinctive operation of the improved voltage-driven thyristor shown in Fig. 27; Fig. 29 is a cross section for showing a first problem of the improved voltage-driven thyristor; and Fig. 30 is a cross section for showing a second problem of the improved voltage-driven thyristor. DESCRIPTION OF THE PREFERRED EMBODIMENT (First Embodiment) A first embodiment being an embodiment according to the present invention will now be described below with reference to Figs. 1 - 17. Fig. 1 is a perspective view partly in section showing a voltage-driven thyristor of the first embodiment of the invention. Referring to Fig. 1, an n-buffer layer 2 is formed on a p + -anode layer 1. An anode electrode 12 is formed on the lower surface of the p + -anode layer 1. The anode electrode 12 may be made of metal such as aluminum. An n - -base layer 3 is formed on n-buffer layer 2. On n - -base layer 3, there are formed a p-base layer 4 and a p-type impurity layer 4a. An n-cathode layer 5 is formed on p-base layer 4. On a surface of n-cathode layer 5, there are selectively formed n + -cathode layers 6 as well as p + -impurity layers 7. There are formed first trenches 16a of a depth D which extend through p + -impurity layer 7, n-cathode layer 5, n + -cathode layer 6 and p-base layer 4 into base layer 3. A first gate electrode (turn-on gate) 9a is formed on an inner surface of each first trench 16a with a gate oxide film 8 therebetween. There are also formed second trenches 16b of a depth D which extend through p + -impurity layer 7, n-cathode layer 5 and n + -cathode layer 6 and have bottom surfaces located in p-type impurity layer 4a. A second gate electrode 9b is formed on an inner surface of each second trench 16b with the gate oxide film 8 therebetween. Second and first gate electrodes 9b and 9a may be made of polysilicon containing impurity introduced thereinto. First and second gate electrodes 9a and 9b are electrically connected at the end of trenches. Cap oxide films 10 are formed on the first and second gate electrodes 9a and 9b. A cathode electrode 11 is formed on cap oxide films 10, p + -impurity layers 7 and n + -cathode layers 6. Cathode electrode 11 may be made of metal such as aluminum. Referring now to Fig. 2, an operation of the voltage-driven thyristor of the first embodiment having the above structure will be described below. Fig. 2 shows an operation principle of the voltage-driven thyristor of the first embodiment described above. The on-state will first be described below with reference to Fig. 2. In order to shift to the on-state, a positive voltage is applied to first and second gate electrodes 9a and 9b. Thereby, an n-channel MOS transistor near the side wall of first trench 16a is turned on, so that a current Ie flows in the n-channel MOS transistor. Thus, electrons flow into n - -base layer 3 through this n-channel MOS transistor. Thereby, a pnp transistor Tr1 is turned on, and a current I A flows through pnp transistor Tr1. As pnp transistor Tr1 is turned on, an npn transistor Tr2 is also turned on, so that a current I k flows. Owing to the turn-on of the pnp transistor Tr1 and npn transistor Tr2 in this manner, the thyristor is turned on, so that the main current flows through the voltage-driven thyristor. Then, the off-state will be described below. The off-state is attained by applying a negative potential to first and second gate electrodes 9a and 9b. By application of the negative voltage to the first and second gate electrodes 9a and 9b, the n-channel MOS transistor near the side wall of first trench 16a is turned off, and the p-channel MOS transistor near the side wall of second trench 16b is turned on. Thereby, holes are drawn from p-base layer 4. Consequently, a depletion layer spreads in the junction portion between p-base layer 4 n - -base layer 3, so that the voltage-driven thyristor is shifted to the off-state. Then, referring to Figs. 3 and 4, a feature of the voltage-driven thyristor of the first embodiment described above will be described below more in detail. Figs. 3 and 4 are cross sections schematically showing a distinctive operation of the voltage-driven thyristor of the first embodiment. Referring first to Fig. 3, p-type impurity layer 4a is formed under second trenches 16b. P-type impurity layer 4a is protruded into n - -base layer 3. A depth of p-type impurity layer 4a is preferably larger than a depth of first trench 16a. Fig. 3 shows a state where the voltage-driven thyristor is turned off and a depletion layer 17 spreads into the junction boundary between p-type impurity layer 4a and n - -base layer 3 and between p-base layer 4 and n - -base layer 3. P-type impurity layer 4a is deep and protruded into n - -base layer 3 as shown in Fig. 3, so that depletion layer 17 can spread into a deep position. Thereby, depletion layer 17 can cover the bottom edges of first trench 16a deeply. Therefore, concentration of an electric field at the bottom edges of first trench 16a can be effectively prevented. Therefore, the voltage-driven thyristor can have a high reliability. Owing to arrangement of p-type impurity layer 4a at opposite sides of first trench 16a, depletion layers 17, which spread at the junctions between p-type impurity layer 4a and n - -base layer 3, are joined under first trench 16a when the voltage-driven thyristor is in the off-state. Thereby, depletion layer 17 can be formed at a deep position under first trench 16a. In connection with this, the voltage-driven thyristor can have high reliability similarly to the case described before. In Fig. 3, one first trench 16a is formed between the adjacent trenches 16b. However, two or more first trenches 16a may be formed between second trenches 16b. Also in this case, p-type impurity layers 4a are formed at an appropriate depth so that depletion layer 17 can cover the bottom edges of these first trenches 16a. Thereby, the voltage-driven thyristor with high reliability is obtained. During shift to the off-state, inverted layers are formed at second channel forming regions 14. Holes are drawn through second channel forming regions 14 from p-base layer 4 and p-type impurity layer 4a into p + -impurity layer 7. In connection with this, p-base layer 4 located immediately under second channel forming region 14 has the highest concentration of impurities according to the structure of the first embodiment shown in Fig. 3. The reason of the above is that the region at which p-base layer 4 and p-type impurity layer 4a overlap with each other is located immediately under second channel forming region 14. Thus, p-base layer 4 of a high concentration exists immediately under second channel forming region 14 according to the structure shown in Fig. 3. Therefore, a resistance against holes, which are being drawn from p-base layer 4 when the voltage-driven thyristor is set to the off-state, can be small. This enables quick setting of the voltage-driven thyristor to the off-state. Referring to Fig. 4, first trenches 16a and second trenches 16b are formed alternately in the voltage-driven thyristor of the first embodiment shown in Fig. 1. This arrangement enables quick setting of the voltage-driven thyristor to the on-state. The reason of the above will be described below with reference to Fig. 4. Referring to Fig. 4, holes are supplied from p + -anode layer 1 to n - -base layer 3 through the same position or path in the p + -anode layer 1 as that through which electrons move into the p + -anode layer 1. These electrons have been injected into n - -base layer 3 through the channel region of the n-channel MOS transistor formed at the side wall of first trench 16a. Since the voltage-driven thyristor of the first embodiment shown in Fig. 4 is provided with first and second trenches 16a and 16b which are formed alternately, a degree of integration of the n-channel MOS transistors can be higher than that of the conventional improvement shown in Fig. 29. The high degree of integration of the n-channel MOS transistors enables a number of positions through which holes are supplied from p + -anode layer 1 into n - -base layer 3. Thereby, holes can be supplied efficiently from p + -anode layer 1 into n - -base layer 3. Therefore, a time required for setting the voltage-driven thyristor to the on-state can be shorter than that of the conventional improvement described before. Referring to Fig. 5, a structure near the second trench 16b will be described below in greater detail. Numerical limits which will be described below are premised on that a breakdown voltage of the voltage-driven thyristor is in a range from about 400V to about 500V. Fig. 5 is an enlarged cross section showing a structure of and around second trench 16b. Referring to Fig. 5, an open width W1 of second trench 16b is about 1µm. A diffusion depth D1 of p + -impurity layer 7 is preferably not more than about 1µm. A diffusion depth D2 of n-cathode layer 5 is preferably about 1.5µm. A diffusion depth D3 of p-base layer 4 is preferably in a range from about 1.5µm to about 2µm. A diffusion depth D4 of p-type impurity layer 4a is preferably in a range from about 2µm to about 3µm. In this case, a diffusion depth of p-type impurity layer 4a from the upper surface of impurity layer 7 is in a range from about 6µm to about 7µm. First and second trenches 16a and 16b preferably have a depth in a range from about 5µm to about 6µm. Also, a distance W2 between first and second trenches 16a and 16b is in a range from about 5µm to about 10µm. The reason of this is that p-type impurity for p-type impurity layer 4a is diffused into a deep position and hence the p-type impurity spreads also in a lateral direction. A concentration of p-base layer 4 is approximately in a range from 10 16 cm -3 to 10 17 cm -3 . This range is determined based on a threshold voltage Vth of the n-channel MOS transistor formed at the side wall of first trench 16a. A concentration of p-type impurity layer 4a is approximately in a range from 10 16 cm -3 to 10 18 cm -3 or more. Thereby, the region 4b at which p-base layer 4 and p-type impurity layer 4a overlap with each other has the highest concentration in a range from 2×10 16 cm -3 to 10 18 cm -3 . This region 4b is located immediately under the channel forming region of the p-channel MOS transistor which operates as a major component when the voltage-driven thyristor is set to the off-state. Therefore, holes can be supplied efficiently to the p-channel MOS transistor. Referring now to Figs. 6 to 17, a method of manufacturing the voltage-driven thyristor of the first embodiment of the invention will be described below. Figs. 6 to 10 are perspective views showing 1st to 5th steps in a process of manufacturing the voltage-driven thyristor of the first embodiment, respectively. Figs. 11A and 11B are perspective views showing modifications of a formation pattern of p + -impurity layers 7. Figs. 12 to 17 are perspective views showing 6th to 11th steps in a process of manufacturing the voltage-driven thyristor of the first embodiment. The voltage-driven thyristor completed through the manufacturing process which will be described below has, for example, the structure including relatively large cap oxide films 10 as shown in Fig. 17. Cap oxide films 10 partially fill first and second trenches or grooves 16a and 16b so as to complete the voltage-driven thyristor of the first embodiment shown in Fig. 1. Referring to Fig. 6, n-buffer layer 2 and n - -base layer 3 are successively formed on the p + -anode layer 1 by an epitaxial growth method. Then, referring to Fig. 7, an oxide film 18 is formed on the surface of n - -base layer 3. Through the oxide film p-type impurities are selectively introduced into n - -base layer 3, for example, by the ion implantation or diffusion from gas. A thermal diffusion process is effected to form p-type impurity layer 4a preferably at a concentration of about 10 16 /cm 3 to 10 18 /cm 3 . Referring to Fig. 8, p-type impurities are introduced through oxide film 18 into the whole surface of n - -base layer 3. A thermal diffusion process is effected to form p-base layer 4 preferably at a concentration of about 10 16 /cm 3 to 10 17 /cm 3 . P-base layer 4 thus formed has a diffusion depth smaller than that of p-type impurity layer 4a. As described above, p-base layer 4 and p-type impurity layer 4a are formed at different steps, so that it is possible to form the high concentration region at which p-base layer 4 and p-type impurity layer 4a overlap with each other. The side wall of second trench 16b is partially formed in this high impurity concentration region. Thereby, it is possible to increase the concentration of p-type impurities in p-base layer 4 near the side wall of second trench 16b. Therefore, it is possible to improve the turn-off characteristics of the voltage-driven thyristor. Referring to Fig. 9, n-type impurities are introduced into the whole surface of p-base layer 4. Then, a thermal diffusion process is effected to form n-cathode layer 5. Referring to Fig. 10, n-type impurities and p-type impurities are selectively introduced into the surface of n-cathode layer 5 to form n + -cathode layers 6 and p + -impurity layers 7, respectively. N + -cathode layers 6 thus formed may be deep enough to reach the upper surface of p-base layer 4. As shown in Figs. 11A and 11B, various pattern structures of p + -impurity layers 7 and n + -cathode layers 6 may be selected in accordance with required characteristics of a device. Referring to Fig. 12, oxide films 19 of a predetermined thickness are formed on p + -impurity layers 7 and n + -cathode layers 6. Using oxide films 19 as a mask, etching is effected to form first and second trenches 16a and 16b. In this embodiment, since first and second trenches 16a and 16b have the same depth, they can be formed simultaneously. Thereby, the process is simplified. Referring to Fig. 13, a thermal oxidation method or a CVD method is used to form gate oxide films 8 in first and second trenches 16a and 16b. A polysilicon layer is deposited on oxide films 19. The polysilicon layer has a thickness enough to fill first and second trenches 16a and 16b and contains impurity doped therein. An etch-back process is effected on the polysilicon layer to form polysilicon layers 9a and 9b filling first and second trenches 16a and 16b as shown in Fig. 14. In this manner, first and second gate electrodes 9a and 9b are formed. Above polysilicon layer is left at the end of first and second trenches 16a and 16b to electrically connect first and second gate electrodes 9a and 9b. Referring to Fig. 15, the thermal oxidation method, CVD method or the like is used to form oxide films 10a. The CVD method is used to form cap oxide film 10 on oxide films 10a and 19. Referring to Fig. 16, the cap oxide films 10 and 19 are patterned to expose the surfaces of p + -impurity layers 7 and n + -cathode layers 6 while partially remaining oxide films 19 and cap oxide films 10 on first and second gate electrodes. Referring to Fig. 17, a sputtering method or the like is used to form cathode electrode 11 on oxide films 10, p + -impurity layers 7 and n + -cathode layers 6. The anode electrode 12 is formed on the lower surface of the p - -anode layer 1. (Second Embodiment) Referring now to Figs. 18 and 19, a voltage-driven thyristor of a second embodiment of the invention will be described below as a comparative embodiment. Fig. 18 is a perspective view of the voltage-driven thyristor of the second embodiment. Referring to Fig. 18, the second embodiment is not provided with p-type impurity layer 4a in contrast to the first embodiment already described. Therefore, The junction portion between p-base layer 4 and n - -base layer 3 is spaced by a substantially constant distance from the surfaces of p + -impurity layers 7 and n + -cathode layers 6. Naturally, the step of forming the p-type impurity layer 4a is not required. Thus, p-base layer 4 is formed by introducing p-type impurities into the whole surface of n - -base layer 3. In this embodiment, first trench 16a has a depth D5 larger than a depth D6 of second trench 16b. Therefore, first gate electrode 9a formed in first trench 16a functions as a turn-on gate, and second gate electrode 9b formed in second trench 16b functions as a turn-off gate. Other structures are the same as those of the voltage-driven thyristor of the first embodiment shown in Fig. 1. Since first and second trenches 16a and 16b have different depths, they are formed at different steps. In the voltage-driven thyristor of this embodiment, a space between first and second trenches 16a and 16b can be smaller than that in the first embodiment. Therefore, a degree of integration of first and second trenches can be increased. Consequently, a time for setting the voltage-driven thyristor to the turn-on state can be further reduced to a value smaller than that in the first embodiment. The reason of the above will be described below in greater detail with reference to Figs. 5 and 19. Referring to Fig. 5 again, p-type impurity layer 4a must be diffused into a deep position in the first embodiment. Therefore, p-type impurity layer 4a inevitably spreads in a lateral direction. Accordingly, in the form shown in Fig. 5, first and second trenches 16a and 16b are spaced from each other by the relatively large distance W2 of about 5 to 10µm. Meanwhile, the second embodiment is not provided with p-type impurity layer 4a as can be seen from Fig. 19, so that the degree of integration of first and second trenches 16a and 16b can be increased. More specifically, a distance W3 between first and second trenches 16a and 16b can be a small value of about 2 to 3µm. Therefore, it is possible to increase the degree of integration of the n-channel MOS transistors formed at the side walls of first trenches 16a. Accordingly, the time required for setting the voltage-driven thyristor to the on-state can be further reduced to a value smaller than that in the first embodiment. Referring to Figs. 20 - 23, modifications of the pattern of p + -impurity layers 7 and n + -cathode layers 6 will be described below. {Modification 1} Fig. 20 is a perspective view showing a first modification of the pattern of p + -impurity layer 7 and n + -cathode layer 6. In this modification in Fig. 20, each n + -cathode layer 6 has a bottom at a deep position which reaches the upper surface of p-base layer 4. Other structures are the same as those of the voltage-driven thyristor of the first embodiment shown in Fig. 1. {Modification 2} Referring to Fig. 21, a second modification of the pattern of p + -impurity layers 7 and n + -cathode layers 6 will be described below. In this modification, each n + -cathode layer 6 is elongated parallel to the longitudinal direction of first trench 16a. Therefore, the inverted layer of the n-channel MOS transistor is continuously formed along the side wall of first trench 16a during setting to the on-state. As a result, the on-current can flow to the cathode electrode through the channel more efficiently than the first modification. N + -cathode layer 6 has the bottom at a deep position which reaches the upper surface of p-base layer 4. Therefore, it is possible to reduce a resistance against a main current flowing through cathode layer 6 during the on-state of the voltage-driven thyristor. Accordingly, a large current can flow through the voltage-driven thyristor. P + -impurity layer 7 is continuously elongated parallel to the side wall of the second trench 16b. {Modification 3} A third modification will be described below with reference to Fig. 22. Fig. 22 is a perspective view showing a voltage-driven thyristor of the third modification. Referring to Fig. 22, this modification is preferably employed in the case where, rather than turn-on characteristics, intended turn-off characteristics are to be ensured. In this modification, as shown in Fig. 22, p + -impurity layer 7 extends along the side wall of second trench 16b. P + -impurity layer 7 has local portions reaching the side wall of first trench 16a. Therefore, n + -cathode layers 6 are formed selectively and intermittently along the side wall of first trench 16a. As described above, since p'-impurity layer 7 extends along second trench 16b and has the local portions reaching the side wall of both first and second trenches 16a and 16b, it is possible to increase a channel width of the p-channel transistor (i.e., transistor functioning as a major component when turning off the voltage-driven thyristor) compared with the case of the second modification described before. Therefore, the voltage-driven thyristor can be set to the off-state more quickly and surely than that of the second modification. {Modification 4} A fourth modification will be described below with reference to Fig. 23, which is a perspective view showing a voltage-driven thyristor of the fourth modification. This modification is preferably employed in the case where, rather than turn-off characteristics, intended turn-on characteristics are to be ensured. In this modification, as shown in Fig. 23, n'-cathode layer 6 is continuously formed along each side wall of first trench 16a, and has local portions reaching the side wall of second trench 16b. Thereby, it is possible to increase a contact area between the cathode electrode and n'-cathode layer 6. Therefore, it is possible to reduce a resistance against the main current flowing through cathode layer 6 during the on-state of the voltage-driven thyristor. This enables the structure in which a large current can be easily obtained. P + -impurity layers 7 are formed selectively and intermittently along each side wall of second trench 16b. The first to fourth modifications described above can be applied to the second embodiment. As described hereinbefore, the third semiconductor layer is provided with the second region, so that concentration of the electric field at the bottom edge of the first trench can be prevented effectively. Therefore, the voltage-driven thyristor can have high reliability. The concentration of impurities of the first conductivity type contained in the second region of the third semiconductor layer is larger than the concentration of impurities of the first conductivity type contained in the first region of the third semiconductor layer, whereby carriers can be supplied efficiently to the MOS transistor which operates when setting the voltage-driven thyristor to the off-state. Therefore, it is possible to reduce the time required for setting the voltage-driven thyristor to the off-state and to turn the voltage-driven thyristor off even a large current. Thus, the voltage-driven thyristor can have superior turn-off characteristics. Owing to the alternate arrangement of the first and second trenches, it is possible to increase the degree of integration of MOS transistors which operate when setting the voltage-driven thyristor to the on-state, compared with the conventional improvement. Therefore carriers can be supplied uniformly and efficiently from the first semiconductor layer into the second semiconductor layer, compared with the conventional improvement. Accordingly, it is possible to reduce a time required for setting the voltage-driven thyristor to the on-state. Thus, the voltage-driven thyristor can have superior turn-on characteristics. Owing to arrangement of the second regions at the opposite sides of the first trench, the bottom edge of the first trench can be covered with the depletion layer spreading at the junction between the third and second semiconductor layers when the voltage-driven thyristor is in the off-state. Therefore, the voltage-driven thyristor can have improved reliability. The impurity concentration of the first region in the third semiconductor layer adjoining to the side wall of the first trench is lower than the impurity concentration of the second region in the third semiconductor layer adjoining to the side wall of the second trench, so that carries can be supplied efficiently to the channel region of the MOS transistor which operates as a major component when the voltage-driven thyristor is set to the off-state. Therefore, it is possible to reduce the time required for setting the voltage-driven thyristor to the off-state. Thus, the voltage-driven thyristor can have superior turn-off characteristics. The impurity layer of the first conductivity type and the third semiconductor layer are formed at different steps, so that it is possible to increase an impurity concentration of the impurity layer regardless of the impurity concentration of the third semiconductor layer. Thereby, the region, which is formed in the impurity layer and adjoins to the side wall of the first trench, has a high impurity concentration. Therefore, the voltage-driven thyristor has superior turn-off characteristics. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A voltage-driven thyristor comprising: a first semiconductor layer (1) of a first conductivity type; a second semiconductor layer (3) of a second conductivity type formed on said first semiconductor layer (1); a third semiconductor layer (4) of the first conductivity type formed on said second semiconductor layer (3); a fourth semiconductor layer (5) of the second conductivity type formed on said third semiconductor layer (4); a fifth semiconductor layer (7) of the first conductivity type selectively formed in the surface of said fourth semiconductor layer (5); a plurality of first trenches (16a) formed through said fourth and third semiconductor layers (5, 4) and reach said second semiconductor layer (3); a plurality of second trenches (16b) formed through said fifth and fourth semiconductor layers (7, 5) and have bottom surfaces located in said third semiconductor layer (4), wherein said first and second trenches (16a, 16b) are disposed alternately; said voltage-driven thyristor further comprising: first and second gate electrodes (9a, 9b) formed in said first and second trenches (16a, 16b), respectively; a cathode electrode (11) formed on said fourth and fifth semiconductor layers (5, 7); and an anode electrode (12) formed on a lower surface of said first semiconductor layer (1); wherein said third semiconductor layer (4) has a first region and a second region (4a), said first region having a first junction portion joining to said second semiconductor layer (3) and located at a first depth from an upper surface of said fifth semiconductor layer (7), and said second region (4a) having a second junction portion joining to said second semiconductor layer (3) and located at a second depth from said upper surface of said fifth semiconductor layer (7), which is larger than said first depth; and said first trenches (16a) are located through said first region, and said second trenches (16b) have bottom surfaces located in said second region (4a). The voltage-driven thyristor according to claim 1, wherein said fifth semiconductor layer (7) is selectively formed along a longitudinal direction of said first and second trenches (16a, 16b), said fourth semiconductor layer (5) exists between said fifth semiconductor layers (7), and a concentration of impurities of the second conductivity type contained in said fourth semiconductor layer (5) existing between said fifth semiconductor layers (7) is higher than that of said fourth semiconductor layer (5) existing under said fifth semiconductor layer (7). The voltage-driven thyristor according to claims 1 or 2, wherein said fifth semiconductor layer (7) extends parallel to said second trench (16b) and along a side wall of said second trench (16b), a surface layer of said fourth semiconductor layer (5) extends parallel to said first trench (16a) and along a side wall of said first trench (16a) The voltage-driven thyristor according to one of claims 1 to 3, wherein said fifth semiconductor layer (7) extends parallel to said second trench (16b) and along a side wall of said second trench (16b), and said fifth semiconductor layer (7) has a local portion reaching a side wall of said first trench (16a). The voltage-driven thyristor according to one of claims 1 to 4, wherein a surface layer of said fourth semiconductor layer (5) extends parallel to said first trench (16a) and along a side wall of said first trench (16a), said fourth semiconductor layer (5) is provided at its surface layer with a local portion reaching a side wall of said second trench (16b). The voltage-driven thyristor according to one of claims 1 to 5, wherein a concentration of impurities of a first conductivity type contained in a first region of said third semiconductor layer (4) adjoining to a side wall of said first trench (16a) is lower than that of a second region (4a) of said third semiconductor layer (4) adjoining to a side wall of said second trench (16b). The voltage-driven thyristor according to one of claims 1 to 6, wherein said third semiconductor layer (4) has a third region of the first conductivity type which has a portion located under said second trench (16b) and protrudes into said second semiconductor layer (3). The voltage-driven thyristor according to claim 6 or 7, wherein a concentration of impurities of said first conductivity type contained in said second region (4a) is higher than that of impurities of the first conductivity type contained in said third region. The voltage-driven thyristor according to claim 7 or 8, wherein a junction portion between said third region and said second semiconductor layer (3) is located at a position deeper than that of a bottom surface of said first trench (16a). A method of manufacturing a voltage-driven thyristor comprising the steps of: forming a second semiconductor layer (3) of a second conductivity type on a first semiconductor layer (1) of a first conductivity type; introducing impurities of the first conductivity type into a surface of said second semiconductor layer (3) to form a third semiconductor layer (4) of the first conductivity type; introducing impurities of the second conductivity type into a whole surface of said third semiconductor layer (4) to form a fourth semiconductor layer (5) of the second conductivity type; selectively introducing impurities of the first conductivity type into a surface of said fourth semiconductor layer (5) to form a fifth semiconductor layer (7); forming first and second trenches (16a, 16b), said first trench (16a) extending through said fifth and fourth semiconductor layers (7, 5) and having a bottom surface located in said third semiconductor layer (4), and said second trench (16b) extending up to said second semiconductor layer (3) through said fifth, fourth and third semiconductor layers (7, 5, 4), said first and second trenches (16a, 16b) being disposed alternately; forming first and second gate electrodes (9a, 9b) on inner surfaces of said first and second trenches (16a, 16b) with insulating layers (8) therebetween, respectively; forming an insulating layer (10) on said first and second gate electrodes (9a, 9b); forming a cathode electrode (11) on a surface of said fifth semiconductor layer (7) and a portion of said surface of said fourth semiconductor layer (5); and forming an anode electrode (12) on a lower surface of said first semiconductor layer (1); wherein said third semiconductor layer (4) includes a first region having a first diffusion depth from its surface, and a second region (4a) having a second diffusion depth from its surface which is larger than said first diffusion depth, said first trenches (16a) are formed to be located through said first region, said second trenches (16b) are formed to have bottom surfaces located in said second region (4a), and said step of forming said third semiconductor layer (4) includes the steps of: selectively introducing impurities of the first conductivity type into a surface of said second semiconductor layer (3) and thereby effecting a diffusion process for forming said second region (4a); and introducing impurities of the first conductivity type into the whole surface of said second semiconductor layer (3) to diffuse said impurities of the first conductivity type up to said first diffusion depth for forming said first region.

Inventors: HARADA MASANA, HARADA, MASANA, HARADA, MASANA, C/O MITSUBISHI DENKI K.K. ULSI LAB
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1994
Main classification: H01L29
IPC codes: H01L21, H01L29