Cell processing system

Abstract: Supplied with first and second signals from first and second control units (19, 29), first and second reading units (17, 27) read first and second readout ATM signals from first and second primary memory units (15, 25) which memorize an ATM signal (11). The second control unit produces the second reading signal when a predetermined interval lapses after supplied with a first reading start signal from the first control unit. A first processing unit (21) processes the first readout ATM signal into a first STM signal and a first processed content signal, A second processing unit (31) processes, in response to the first processed content signal, the second readout ATM signal into a second STM signal. An output reading unit (35) reads first and second output STM signals at the same time from first and second secondary memory units (23, 33) which memorize the first and the second readout STM signals.

Description: This invention relates to a cell processing system and a cell processing method for processing an input first-type signal, which is one of an asynchronous transfer mode ("ATM") signal and a synchronous transfer mode or module ("STM") signal, to produce an output second-type signal, which is the other of an ATM signal and an STM signal. A conventional such cell processing system comprises : first and second primary memory means for receiving the input first-type signal and memorising it as first and second memorised first-type signals, respectively; first and second processing means for processing first and second readout first-type signals, respectively, read out from the first and second primary memory means, respectively, to produce first and second generated second-type signals, respectively; first and second secondary memory means for receiving the first and second generated second-type signals, respectively, and memorising them as first and second memorised second-type signals, respectively; and an output selecting means for selecting one of first and second readout second-type signals read out from the first and second secondary memory means in dependence upon first and second selection signals and outputting the selected signal as the output second-type signal. Examples of such a system and method are described in DE-C1- 4 123 851 and EP-A- 0 531 772. In such a conventional cell processing system, either the first and second processing means must stop processing the first-type signals while the output selecting means is changing its selection, or it must be accepted that part of the second-type signal will be lost while the output selecting means is changing its selection. The present invention is concerned with enabling the system to continue processing the first-type signals while the output selecting device changes its selection without a part of the second-type signal being lost. The system of one aspect of the present invention is characterised by: a first reading control means for producing a first reading signal and a first reading start signal representing a start of the first reading signal; a second reading control means responsive to the first reading start signal for producing a second reading signal when a first predetermined time interval elapses after supply with the first reading start signal; first and second reading means for reading out the first and second memorised first-type signals, respectively, as the first and second readout first-type signals, respectively, when the first and second reading means, respectively, are supplied with the first and second reading signals, respectively; the first processing means being operable also to produce a first processed content signal representing the process of the first processing means; the second processing means being operable to process the second readout first-type signal to produce the second generated second-type signal in response to the first processed content signal; and an output reading means for reading out the first and second readout second-type signals from the first and second secondary memory means, respectively, at the same time. The system preferably further includes a main control means operable to produce the first and second selection signals, and the main control means is preferably operable also to produce first to third input control signals for controlling input to the system. Preferably, the second reading control means is also responsive to the second and third input control signals so as to produce: the second reading signal when supplied with the second input control signal or when the first predetermined time interval elapses after supply with the first reading start signal; and a second reading start signal representing a start of the second reading signal when supplied with the second and third input control signals; and the first reading control means is responsive to the second reading start signal and the first and third input control signals so as to produce: the first reading signal when supplied with the first input control signal or when a second predetermined time interval elapses after supply with the second reading start signal; and the first reading start signal when supplied with the first and third input control signals. Preferably, the main control means is operable to produce first to third processing control signals; the second processing means is also responsive to the second and third processing control signals so as to produce: the second generated second-type signal when supplied with the second processing control signal or the first processed content signal; and a second processed content signal representing the process of the second processing means when supplied with the second and third processing control signals; and the first processing means is responsive to the second processed content signal and the first and third processing control signals so as to produce: the first generated second-type signal when supplied with the first processing control signal or the second processed content signal; and the first processed content signal when supplied with the first and third processing control signals. The system preferably further includes: a first writing control means for producing a first writing signal and a first writing start signal representing a start of the first writing signal; a second writing control means responsive to the first writing start signal for producing a second writing signal when a third predetermined time interval elapses after receipt of the first writing start signal; and first and second writing means operable to write the first and second generated second-type signals, respectively, in the first and second secondary memory means, respectively, as the first and second memorised second-type signals, respectively, when the first and second writing means, respectively, are supplied with the first and second writing signals, respectively. Preferably, the main control means is operable to produce first to third writing control signals; the second writing control means is also responsive to the second and third writing control signals so as to produce: the second writing signal when supplied with the second writing control signal or when the third predetermined time interval elapses after supply with the first writing start signal; and a second writing start signal representing a start of the second writing signal when supplied with the second and third writing control signals; and the first writing control means is responsive to the second writing start signal and the first and third writing control signals so as to produce: the first writing signal when supplied with the first writing control signal or when a fourth predetermined time interval elapses after supply with the second writing start signal; and the first writing start signal when supplied with the first and third writing control signals. The system preferably further includes an input control means for receiving the input first-type signal and operable to supply the input first-type signal to: the first primary memory means when the input control means is supplied with the first or third input control signal; and the second primary memory means when the input control means is supplied with the second or third input control signal. In one embodiment, the first-type signal is an ATM signal and the second-type signal is an STM signal. In another embodiment, the first-type signal is an STM signal and the second-type signal is an ATM signal. Another aspect of the present invention provides a cell processing method analogous to the system described above. Preferred features of the invention are now described, purely by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a cell processing system according to a first preferred embodiment of this invention; Fig. 2 is a block diagram of a cell processing system according to a second preferred embodiment of this invention; Fig. 3 is a block diagram of a cell processing system according to a third preferred embodiment of this invention; Fig. 4 is a block diagram of a cell processing system according to a fourth preferred embodiment of this invention; Fig. 5 is a block diagram of a cell processing system according to a fifth preferred embodiment of this invention; Fig. 6 is a block diagram of a cell processing system according to a sixth preferred embodiment of this invention; Fig. 7 is a block diagram of a cell processing system according to a seventh preferred embodiment of this invention; and Fig. 8 is a block diagram of a cell processing system according to an eighth preferred embodiment of this invention. Referring to Fig. 1, the description will proceed to a cell processing system according to a first embodiment of this invention. The cell processing system receives an ATM signal 11 and processes the ATM signal 11 into an STM signal 13 to output the STM signal 13. The cell processing system comprises a first primary memory unit 15 which receives the ATM signal 11 to memorize the ATM signal 11 as a first memorized ATM signal. The first primary memory unit 15 comprises a first-in first-out (FIFO) memory device. A first reading unit 17 is connected to the first primary memory unit 15 and reads the first memorized ATM signal out of the first primary memory unit 15 as a first readout ATM signal when the first reading unit 17 is supplied with a first reading signal. A first reading control unit 19 is connected to the first reading unit 17 and produces the first reading signal and a first reading start signal representing a start of the first reading signal. A first processing unit 21 is connected to the first primary memory unit 15 and processes the first readout ATM signal to produce a first STM signal and a first processed content signal representing a process of the first processing unit 21. A first secondary memory unit 23 is connected to the first processing unit 21 and receives the first STM signal to memorize the first STM signal as a first memorized STM signal. The first secondary memory unit 23 comprises a FIFO memory device. A second primary memory unit 25 receives the ATM signal 11 to memorize the ATM signal 11 as a second memorized ATM signal. The second primary memory unit 25 comprises a FIFO memory device. A second reading unit 27 is connected to the second primary memory unit 25 and reads the second memorized ATM signal out of the second primary memory unit 25 as a second readout ATM signal when the second reading unit 27 is supplied with a second reading signal. A second reading control unit 29 is connected to the second reading unit 27 and to the first reading control unit 19 and produces the second reading signal when a first predetermined time interval lapses after the second reading control unit 29 is supplied with the first reading start signal. A second processing unit 31 is connected to the second primary memory unit 25 and to the first processing unit 21 and processes, in response to the first processed content signal, the second readout ATM signal to produce a second STM signal. As a result, a second process of the second processing unit 31 is equal to the first process of the first processing unit 21. A second secondary memory unit 33 is connected to the second processing unit 31 and receives the second STM signal to memorize the second STM signal as a second memorized STM signal. The second secondary memory unit 33 comprises a FIFO memory device. An output reading unit 35 is connected to the first and the second secondary memory units 23 and 33 and reads the first and the second memorized STM signal at the same time out of the first and the second secondary memory units 23 and 33 as first and second output STM signals. An output selecting unit 37 is connected to the first and the second secondary memory units 23 and 33 and selects one of the first and the second output STM signals to output the one of the first and the second output STM signals as the STM signal 13 when the output selecting unit 37 is supplied with one of first and second selection signals. A first writing unit 39 is connected to the first secondary memory unit 23 and writes the first STM signal in the first secondary memory unit 23 as the first memorized STM signal when the first writing unit 39 is supplied with a first writing signal. A first writing control unit 41 is connected to the first writing unit 39 and produces the first writing signal and a first writing start signal representing a start of the first writing signal. A second writing unit 43 is connected to the second secondary memory unit 33 and writes the second STM signal in the second secondary memory unit 33 as the second memorized STM signal when the second writing unit 43 is supplied with a second writing signal. A second writing control unit 45 is connected to the second writing unit 43 and to the first writing control unit 41 and produces the second writing signal when a second predetermined time interval lapses after the second writing control unit 45 is supplied with the first writing start signal. Referring to Fig. 2, the description will proceed to a cell processing system according to a second embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises a main control unit 47 which produces first, second, and third input control signals, first, second, and third processing control signals, and the first, the second, and third writing control signals. The first reading control unit 19 is connected to the first reading unit 17 and to the main control unit 47 and produces the first reading signal when the first reading control unit 19 is supplied with the first input control signal. The first reading control unit 19 produces the first reading signal and the first reading start signal representing the start of the first reading signal when the first reading control unit 19 is supplied with the first and the third input control signals. The first reading control unit 19 produces the first reading signal when a first predetermined time interval lapses after the first reading control unit 19 is supplied with a second reading start signal. The first processing unit 21 is connected to the first primary memory unit 15 and to the main control unit 47 and processes the first readout ATM signal to produce the first STM signal when the first processing unit 21 is supplied with the first processing control signal. The first processing unit 21 processes the first readout ATM signal to produce the first STM signal and the first processed content signal representing the process of the first processing unit 21 when the first processing unit 21 is supplied with the first and the third processing control signals. The first processing unit 21 processes, in response to a second processed content signal, the first readout ATM signal to produce the first STM signal when the first processing unit 21 is supplied with the second processed content signal. The second reading control unit 29 is connected to the second reading unit 27, to the first reading control unit 19, and to the main control unit 47 and produces the second reading signal when the second reading control unit 29 is supplied with the second input control signal. The second reading control unit 29 produces the second reading signal and the second reading start signal representing a start of the second reading signal when the second reading control unit 29 is supplied with the second and the third input control signals. The second reading control unit 29 produces the second reading signal when a second predetermined time interval lapses after the second reading control unit 29 is supplied with the first reading start signal. The second processing unit 31 is connected to the second primary memory unit 25, to the first processing unit 21, and to the main control unit 47 and processes the second readout ATM signal to produce the second STM signal when the second processing unit 31 is supplied with the second processing control signal. The second processing unit 31 processes the second readout ATM signal to produce the second STM signal and the second processed content signal representing the second process of the second processing unit 31 when the second processing unit 31 is supplied with the second and the third processing control signals. The second processing unit 31 processes, in response to the first processed content signal, the second readout ATM signal to produce the second STM signal when the second processing unit 31 is supplied with the first processed content signal. The second process of the second processing unit 31 is equal to the first process of the first processing unit 21. The first writing unit 39 is connected to the first secondary memory unit 23 and writes the first STM signal in the first secondary memory unit 23 as the first memorized STM signal when the first writing unit 39 is supplied with the first writing signal. The first writing control unit 41 is connected to the first writing unit 39 and to the main control unit 47 and produces the first writing signal when the first writing control unit 41 is supplied with the first writing control signal. The first writing control unit 41 produces the first writing signal and the first writing start signal representing the start of the first writing signal when the first writing control unit 41 is supplied with the first and the third writing control signals and produces the first writing signal when a primary determined time interval lapses after the first writing control unit is supplied with a second writing start signal. The second writing unit 43 is connected to the second secondary memory unit 33 and writes the second STM signal in the second secondary memory unit 33 as the second memorized STM signal when the second writing unit is supplied with the second writing signal. The second writing control unit 45 is connected to the second writing unit 43, to the first writing control unit 41, and to the main control unit 47 and produces the second writing signal when the second writing control unit 45 is supplied with the second writing control signal. The second writing control unit 45 produces the second writing signal and the second writing start signal representing a start of the second writing signal when the second writing control unit 45 is supplied with the second and the third writing control signals. The second writing control unit 45 produces the second writing signal when a secondary predetermined time interval lapses after the second writing control unit 45 is supplied with the first writing start signal. Referring to Fig. 3, the description will proceed to a cell processing system according to a third embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises the main control unit 47 which produces the first, the second, and the third input control signals, the first, the second, and the third writing control signals, and the first and the second selection signals. The cell processing system comprises an input control unit 49 which is connected to the main control unit 47 and receives the ATM signal to produce the first ATM signal when the input control unit 49 is supplied with the first input control signal, the second ATM signal when the input control unit 49 is supplied with the second input control signal, and the first and the second ATM signals when the input control unit 49 is supplied with the third input control signal. Each of the first and the second ATM signals is equal to the ATM signal. The first primary memory unit 15 is connected to the input control unit 49 and receives the first ATM signal to memorize the first ATM signal as the first memorized ATM signal. The second primary memory unit 25 is connected to the input control unit 49 and receives the second ATM signal to memorize the second ATM signal as the second memorized ATM signal. The output selecting unit 47 is connected to the first and the second secondary memory units 23 and 33 and to the main control unit 47 and selects one of the first and the second output STM signals to output the one of the first and the second output STM signals as the STM signal when the output selecting unit 37 is supplied with one of the first and the second selection signals. Referring to Fig. 4, the description will proceed to a cell processing system according to a fourth embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises the main control unit 47 which produces the first, the second, and the third input control signals, the first, the second, and the third processing control signals, the first, the second, and the third writing control signals, and the first and the second selection signals. Referring to Fig. 5, the description will proceed to a cell processing system according to a fifth embodiment of this invention. The cell processing system receives an STM signal 111 and processes the STM signal 111 into an ATM signal 113 to output the ATM signal 113. The cell processing system comprises a first primary memory unit 115 which receives the STM signal 111 to memorize the STM signal 111 as a first memorized STM signal. The first primary memory unit 115 comprises a first-in first-out (FIFO) memory device. A first reading unit 117 is connected to the first primary memory unit 115 and reads the first memorized STM signal out of the first primary memory unit 115 as a first readout STM signal when the first reading unit 117 is supplied with the first reading signal. A first reading control unit 119 is connected to the first reading unit 117 and produces the first reading signal and the first reading start signal representing the start of the first reading signal. A first processing unit 121 is connected to the first primary memory unit 115 and processes the first readout STM signal to produce a first ATM signal and the first processed content signal representing the first process of the first processing unit 121. A first secondary memory unit 123 is connected to the first processing unit 121 and receives the first ATM signal to memorize the first ATM signal as a first memorized ATM signal. The first secondary memory unit 123 comprises a FIFO memory device. A second primary memory unit 125 receives the STM signal 111 to memorize the STM signal 111 as a second memorized STM signal. The second primary memory unit 125 comprises a FIFO memory device. A second reading unit 127 is connected to the second primary memory unit 125 and reads the second memorized STM signal out of the second primary memory unit 125 as a second readout STM signal when the second reading unit 127 is supplied with the second reading signal. A second reading control unit 129 is connected to the second reading unit 127 and to the first reading control unit 119 and produces the second reading signal when the first predetermined time interval lapses after the second reading control unit 129 is supplied with the first reading start signal. A second processing unit 131 is connected to the second primary memory unit 125 and to the first processing unit 121 and processes, in response to the first processed content signal, the second readout STM signal to produce a second ATM signal. As a result, the second process of the second processing unit 131 is equal to the first process of the first processing unit 121. A second secondary memory unit 133 is connected to the second processing unit 131 and receives the second ATM signal to memorize the second ATM signal as a second memorized ATM signal. The second secondary memory unit 133 comprises a FIFO memory device. An output reading unit 135 is connected to the first and the second secondary memory units 123 and 133 and reads the first and the second memorized ATM signal at the same time out of the first and the second secondary memory units 123 and 133 as first and second output ATM signals. An output selecting unit 137 is connected to the first and the second secondary memory units 123 and 133 and selects one of the first and the second output ATM signals to output the one of the first and the second output ATM signals as the ATM signal 113 when the output selecting unit 137 is supplied with one of first and second selection signals. A first writing unit 139 is connected to the first secondary memory unit 123 and writes the first ATM signal in the first secondary memory unit 123 as the first memorized ATM signal, when the first writing unit 139 is supplied with the first writing signal. A first writing control unit 141 is connected to the first writing unit 139 and produces the first writing signal and the first writing start signal representing the start of the first writing signal. A second writing unit 143 is connected to the second secondary memory unit 133 and writes the second ATM signal in the second secondary memory unit 133 as the second memorized ATM signal when the second writing unit 143 is supplied with the second writing signal. A second writing control unit 145 is connected to the second writing unit 143 and to the first writing control unit 141 and produces the second writing signal when the second predetermined time interval lapses after the second writing control unit 145 is supplied with the first writing start signal. Referring to Fig. 6, the description will proceed to a cell processing system according to a sixth embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises a main control unit 147 which produces first, second, and third input control signals, first, second, and third processing control signals, and the first, the second, and third writing control signals. The first reading control unit 119 is connected to the first reading unit 117 and to the main control unit 147 and produces the first reading signal when the first reading control unit 119 is supplied with the first input control signal. The first reading control unit 119 produces the first reading signal and the first reading start signal representing the start of the first reading signal when the first reading control unit 119 is supplied with the first and the third input control signals. The first reading control unit 119 produces the first reading signal when the first predetermined time interval lapses after the first reading control unit 119 is supplied with the second reading start signal. The first processing unit 121 is connected to the first primary memory unit 115 and to the main control unit 147 and processes the first readout STM signal to produce the first ATM signal when the first processing unit 121 is supplied with the first processing control signal. The first processing unit 121 processes the first readout STM signal to produce the first ATM signal and the first processed content signal representing the process of the first processing unit 121 when the first processing unit 121 is supplied with the first and the third processing control signals. The first processing unit 121 processes, in response to the second processed content signal, the first readout STM signal to produce the first ATM signal when the first processing unit 121 is supplied with the second processed content signal. The second reading control unit 129 is connected to the second reading unit 127, to the first reading control unit 119, and to the main control unit 147 and produces the second reading signal when the second reading control unit 129 is supplied with the second input control signal. The second reading control unit 129 produces the second reading signal and the second reading start signal representing the start of the second reading signal when-the second reading control unit 129 is supplied with the second and the third input control signals. The second reading control unit 129 produces the second reading signal when the second predetermined time interval lapses after the second reading control unit 129 is supplied with the first reading start signal. The second processing unit 131 is connected to the second primary memory unit 125, to the first processing unit 121, and to the main control unit 147 and processes the second readout STM signal to produce the second ATM signal when the second processing unit 131 is supplied with the second processing control signal. The second processing unit 131 processes the second readout STM signal to produce the second ATM signal and the second processed content signal representing the second process of the second processing unit 131 when the second processing unit 131 is supplied with the second and the third processing control signals. The second processing unit 131 processes, in response to the first processed content signal, the second readout STM signal to produce the second ATM signal, when the second processing unit 131 is supplied with the first processed content signal. The second process of the second processing unit 131 is equal to the first process of the first processing unit 121. The first writing unit 139 is connected to the first secondary memory unit 123 and writes the first ATM signal in the first secondary memory unit 123 as the first memorized ATM signal when the first writing unit 139 is supplied with the first writing signal. The first writing control unit 141 is connected to the first writing unit 139 and to the main control unit 147 and produces the first writing signal when the first writing control unit 141 is supplied with the first writing control signal. The first writing control unit 141 produces the first writing signal and the first writing start signal representing the start of the first writing signal when the first writing control unit 141 is supplied with the first and the third writing control signals and produces the first writing signal when the primary determined time interval lapses after the first writing control unit is supplied with the second writing start signal. The second writing unit 143 is connected to the second secondary memory unit 133 and writes the second ATM signal in the second secondary memory unit 133 as the second memorized ATM signal when the second writing unit is supplied with the second writing signal. The second writing control unit 145 is connected to the second writing unit 143, to the first writing control unit 141, and to the main control unit 147 and produces the second writing signal when the second writing control unit 145 is supplied with the second writing control signal. The second writing control unit 145 produces the second writing signal and the second writing start signal representing a start of the second writing signal when the second writing control unit 145 is supplied with the second and the third writing control signals. The second writing control unit 145 produces the second writing signal when the secondary predetermined time interval lapses after the second writing control unit 145 is supplied with the first writing start signal. Referring to Fig. 7, the description will proceed to a cell processing system according to a seventh embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises the main control unit 147 which produces the first, the second, and the third input control signals, the first, the second, and the third writing control signals, and the first and the second selection signals. The cell processing system comprises an input control unit 149 connected to the main control unit 147 and receives the STM signal to produce the first STM signal when the input control unit 149 is supplied with the first input control signal, the second STM signal when the input control unit 149 is supplied with the second input control signal, and the first and the second STM signals when the input control unit 149 is supplied with the third input control signal. Each of the first and the second STM signals is equal to the STM signal. The first primary memory unit 115 is connected to the input control unit 149 and receives the first STM signal to memorize the first STM signal as the first memorized STM signal. The second primary memory unit 125 is connected to the input control unit 149 and receives the second STM signal to memorize the second STM signal as the second memorized STM signal. The output selecting unit 137 is connected to the first and the second secondary memory units 123 and 133 and to the main control unit 147 and selects one of the first and the second output ATM signals to output the one of the first and the second output ATM signals as the ATM signal when the output selecting unit 137 is supplied with one of the first and the second selection signals. Referring to Fig. 8, the description will proceed to a cell processing system according to an eighth embodiment of this invention. Similar parts are designated by like reference numerals. The cell processing system comprises the main control unit 147 which produces the first, the second, and the third input control signals, the first, the second, and the third processing control signals, the first, the second, and the third writing control signals, and the first and the second selection signals. In summary, in the preferred embodiments of the invention, supplied with first and second signals from first and second control units, first and second reading units read first and second readout ATM signals from first and second primary memory units which memorize an ATM signal. The second control unit produces the second reading signal when a predetermined interval lapses after supply with a first reading start signal from the first control unit. A first processing unit processes the first readout ATM signal into a first STM signal and a first processed content signal. A second processing unit processes, in response to the first processed content signal, the second readout ATM signal into a second STM signal. An output reading unit reads first and second output STM signals at the same time from first and second secondary memory units which memorize the first and the second readout STM signals. An analogous technique is provided for processing an STM signal into an ATM signal. It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention.

Claims: A cell processing system for processing an input first-type signal, which is one of an ATM signal and an STM signal, to produce an output second-type signal, which is the other of an ATM signal and an STM signal, comprising: first and second primary memory means (15, 25 ; 115, 125) for receiving the input first-type signal and memorising it as first and second memorised first-type signals, respectively; first and second processing means (21, 31; 121, 131) for processing first and second readout first-type signals, respectively, read out from the first and second primary memory means, respectively, to produce first and second generated second-type signals, respectively; first and second secondary memory means (23, 33; 123, 133) for receiving the first and second generated second-type signals, respectively, and memorising them as first and second memorised second-type signals, respectively; and an output selecting means (37; 137) for selecting one of first and second readout second-type signals read out from the first and second secondary memory means in dependence upon first and second selection signals and outputting the selected signal as the output second-type signal; characterised by : a first reading control means (19; 119) for producing a first reading signal and a first reading start signal representing a start of the first reading signal; a second reading control means (29; 129) responsive to the first reading start signal for producing a second reading signal when a first predetermined time interval elapses after supply with the first reading start signal; first and second reading means (17, 27; 117, 127) for reading out the first and second memorised first-type signals, respectively, as the first and second readout first-type signals, respectively, when the first and second reading means, respectively, are supplied with the first and second reading signals, respectively; the first processing means being operable also to produce a first processed content signal representing the process of the first processing means; the second processing means being operable to process the second readout first-type signal to produce the second generated second-type signal in response to the first processed content signal; and an output reading means (35; 135) for reading out the first and second readout second-type signals from the first and second secondary memory means, respectively, at the same time. A system as claimed in claim 1, further including a main control means (47; 147) operable to produce the first and second selection signals. A system as claimed in claim 2, wherein the main control means is operable also to produce first to third input control signals for controlling input to the system. A system as claimed in claim 3, wherein: the second reading control means is also responsive to the second and third input control signals so as to produce: the second reading signal when supplied with the second input control signal or when the first predetermined time interval elapses after supply with the first reading start signal; and a second reading start signal representing a start of the second reading signal when supplied with the second and third input control signals; and the first reading control means is responsive to the second reading start signal and the first and third input control signals so as to produce: the first reading signal when supplied with the first input control signal or when a second predetermined time interval elapses after supply with the second reading start signal; and the first reading start signal when supplied with the first and third input control signals. A system as claimed in any of claims 2 to 4, wherein: the main control means is operable to produce first to third processing control signals; the second processing means is also responsive to the second and third processing control signals so as to produce: the second generated second-type signal when supplied with the second processing control signal or the first processed content signal; and a second processed content signal representing the process of the second processing means when supplied with the second and third processing control signals; and the first processing means is responsive to the second processed content signal and the first and third processing control signals so as to produce: the first generated second-type signal when supplied with the first processing control signal or the second processed content signal; and the first processed content signal when supplied with the first and third processing control signals. A system as claimed in any preceding claim, further including: a first writing control means (41; 141) for producing a first writing signal and a first writing start signal representing a start of the first writing signal; a second writing control means (45; 145) responsive to the first writing start signal for producing a second writing signal when a third predetermined time interval elapses after receipt of the first writing start signal; and first and second writing means (39, 43 ; 139, 143) operable to write the first and second generated second-type signals, respectively, in the first and second secondary memory means, respectively, as the first and second memorised second-type signals, respectively, when the first and second writing means, respectively, are supplied with the first and second writing signals, respectively. A system as claimed in claim 6 when dependent on any of claims 2 to 5, wherein: the main control means is operable to produce first to third writing control signals; the second writing control means is also responsive to the second and third writing control signals so as to produce: the second writing signal when supplied with the second writing control signal or when the third predetermined time interval elapses after supply with the first writing start signal; and a second writing start signal representing a start of the second writing signal when supplied with the second and third writing control signals; and the first writing control means is responsive to the second writing start signal and the first and third writing control signals so as to produce: the first writing signal when supplied with the first writing control signal or when a fourth predetermined time interval elapses after supply with the second writing start signal; and the first writing start signal when supplied with the first and third writing control signals. A system as claimed in claim 3 or 4, or any of claims 5 to 7 when dependent on claim 3 or 4, further including: an input control means (49; 149) for receiving the input first-type signal and operable to supply the input first-type signal to: the first primary memory means when the input control means is supplied with the first or third input control signal; and the second primary memory means when the input control means is supplied with the second or third input control signal. A system as claimed in any preceding claim, wherein the first-type signal is an ATM signal and the second-type signal is an STM signal. A system as claimed in any of claims 1 to 8, wherein the first-type signal is an STM signal and the second-type signal is an ATM signal. A cell processing method for processing an input first-type signal, which is one of an ATM signal and an STM signal, to produce an output second-type signal, which is the other of an ATM signal and an STM signal, comprising the steps of: memorising the input first-type signal as first and second memorised first-type signals in first and second primary memory means (15, 25; 115, 125), respectively ; processing first and second readout first-type signals, respectively, read out from the first and second primary memory means, respectively, to produce first and second generated second-type signals, respectively; memorising the first and second generated second-type signals as first and second memorised second-type signals, respectively, in first and second secondary memory means (23, 33; 123, 133), respectively; selecting one of first and second readout second-type signals read out from the first and second secondary memory means in dependence upon first and second selection signals and outputting the selected signal as the output second-type signal; characterised by the steps of: producing a first reading signal and a first reading start signal representing a start of the first reading signal; producing a second reading signal when a first predetermined time interval elapses after production of the first reading start signal; reading out the first and second memorised first-type signals, respectively, as the first and second readout first-type signals, respectively, in response to supply of the first and second reading signals, respectively; producing a first processed content signal representing the process of the first processing means; processing the second readout first-type signal to produce the second generated second-type signal in response to the first processed content signal; and reading out the first and second readout second-type signals from the first and second secondary memory means, respectively, at the same time.

Inventors: HONDA NAOTO, NAKAGAWA TATSUO, YAMADA KENJI, HONDA, NAOTO, NAKAGAWA, TATSUO, YAMADA, KENJI, HONDA, NAOTO, C/O NEC COMMUNICATION SYSTEMS, LTD.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1994
Main classification: H04Q11
IPC codes: H04Q11, H04L12